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rene s a s m cu m16 c family / m16 c /tin y s erie s m16c/28 group (t-ver./v-ver.) 16 rev. 1.10 revision date: mar.30, 2007 hardware manual www.renesas.com all information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by renesas technology corp. without notice. please review the latest information published by renesas technology corp. through various means, including the renesas technology corp. website (http://www.renesas.com). rej09b0287-0110
1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas products for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. you should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. all information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas products listed in this document, please confirm the latest product information with a renesas sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas such as that disclosed through our website. (http://www.renesas.com ) 5. renesas has used reasonable care in compiling the information included in this document, but renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. when using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or renesas products. 7. with the exception of products specified by renesas as suitable for automobile applications, renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. if you are considering the use of our products for such purposes, please contact a renesas sales office beforehand. renesas shall have no liability for damages arising out of the uses set forth above. 8. notwithstanding the preceding paragraph, you should not use renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use renesas products in any of the foregoing applications shall indemnify and hold harmless renesas technology corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. you should use the products described herein within the range specified by renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas shall have no liability for malfunctions or damages arising out of the use of renesas products beyond such specified ranges. 10. although renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. you should implement safety measures so that renesas products may not be easily detached from your products. renesas shall have no liability for damages arising out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from renesas. 13. please contact a renesas sales office if you have any questions regarding the information contained in this document, renesas semiconductor products, or if you have any other inquiries. notes regarding these materials
general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the rele vant sections of the manu al. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the bod y of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directi ons given under handling of unused pins in the manual. ? the input pins of cmos products are general ly in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through cu rrent flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at t he moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a pr oduct that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the po ssible future expansion of functions. do not access these addresses; the correct operat ion of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during pr ogram execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset li ne is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different part numbe rs, implement a system-evaluation test for each of the products.
how to use this manual 1. purpose and target readers this manual is designed to provide the user with an understanding of the hardwa re functions and electrical characteristics of the mcu. it is intended for users de signing application systems incorporating the mcu. a basic knowledge of electric circuits, logi cal circuits, and mcus is necessa ry in order to use this manual. the manual comprises an overview of the product; descriptions of the cpu, system control functions, peripheral functions, and electrical charac teristics; and usage notes. particular attention should be paid to the precautio nary notes when using the manual. these notes occur within the body of the text, at the end of each section, and in the usage notes section. the revision history summarizes the loca tions of revisions and additions. it does not list all revisions. refer to the text of the manual for details. the following documents apply to the m16c/28 group (t-ver./ v-ver.). make sure to refer to the latest versions of these documents. the newest versions of the documents listed may be obtained from the renesas technology web site. document type description document title document no. hardware manual hardware specifications (pin assignments, memory maps, peripheral function specifications, electrical characteristics, timing charts) and operation description note: refer to the applic ation notes for details on using peripheral functions. m16c/28 group (t-ver./v-ver.) hardware manual this hardware manual software manual description of cpu instruction set m16c/60, m16c/20, m16c/tiny series software manual rej09b-0137 application note information on using peripheral functions and application examples sample programs information on writing programs in assembly language and c available from renesas technology web site. renesas technical update product specifications, updates on documents, etc.
2. notation of numbers and symbols the notation conventions for register na mes, bit names, numbers, and symbols used in this manual are described below. (1) register names, bit names, and pin names registers, bits, and pins are referred to in the text by symbols. the symbol is accompanied by the word ?register,? ?bit,? or ?pin? to distinguish the three categories. examples the pm03 bit in the pm0 register p3_5 pin, vcc pin (2) notation of numbers the indication ? 2 ? is appended to numeric values given in binary format. however, nothing is appended to the values of single bits. the indication ? 16 ? is appended to numeric values given in hexadecimal format. nothing is appended to numeric values given in decimal format. examples binary: 11 2 hexadecimal: efa0 16 decimal: 1234
3. register notation the symbols and terms used in register diagrams are described below. *1 blank: set to 0 or 1 acco rding to the application. 0: set to 0. 1: set to 1. x: nothing is assigned. *2 rw: read and write. ro: read only. wo: write only. ? : nothing is assigned. *3 ? reserved bit reserved bit. set to specified value. *4 ? nothing is assigned nothing is assigned to the bit. as the bit may be used for future functions, if necessary, set to 0. ? do not set to a value operation is not guaranteed when a value is set. ? function varies according to the operating mode. the function of the bit varies with the peripheral functi on mode. refer to the regist er diagram for information on the individual modes. xxx register symbol address after reset xxx xxx 00 16 bit name bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 xxx bits 1 0: xxx 0 1: xxx 1 0: do not set. 1 1: xxx b1 b0 xxx1 xxx0 xxx4 reserved bits xxx5 xxx7 xxx6 function nothing is assigned. if necessary, set to 0. when read, the content is undefined. xxx bit function varies according to the operating mode. set to 0. 0 (b3) (b2) rw rw rw rw wo rw ro xxx bits 0: xxx 1: xxx *1 *2 *3 *4
4. list of abbrevia tions and acronyms abbreviation full form acia asynchronous communication interface adapter bps bits per second crc cyclic redundancy check dma direct memory access dmac direct memory access controller gsm global system for mobile communications hi-z high impedance iebus inter equipment bus i/o input/output irda infrared data association lsb least significant bit msb most significant bit nc non-connection pll phase locked loop pwm pulse width modulation sfr special function registers sim subscriber identity module uart universal asynchrono us receiver/transmitter vco voltage controlled oscillator all trademarks and registered trademarks ar e the property of their respective owners. iebus is a registered trademark of nec electronics corporation.
a-1 table of contents quick reference to pages classified by address _____________________ b-1 1. overview ____________________________________________________ 1 1.1 features ................................................................................................................... ........ 1 1.1.1 applications ............................................................................................................. ... 1 1.1.2 specifications ........................................................................................................... .. 2 1.2 block diagram .............................................................................................................. .... 4 1.3 product list ............................................................................................................... ........ 6 1.4 pin configuration .......................................................................................................... .. 10 1.5 pin description ............................................................................................................ ... 16 2. central processing unit (cpu) __________________________________ 19 2.1 data registers (r0, r1, r2 and r3) .............................................................................. 19 2.2 address registers (a0 and a1) ...................................................................................... 19 2.3 frame base register (fb) .............................................................................................. 20 2.4 interrupt table register (intb) ....................................................................................... 20 2.5 program counter (pc) .................................................................................................... 20 2.6 user stack pointer (usp) and interrupt stack pointer (isp) .......................................... 20 2.7 static base register (sb) ............................................................................................... 20 2.8 flag register (flg) ........................................................................................................ 20 2.8.1 carry flag (c flag) .................................................................................................. 20 2.8.2 debug flag (d flag) ................................................................................................. 20 2.8.3 zero flag (z flag) ................................................................................................... 20 2.8.4 sign flag (s flag) .................................................................................................... 20 2.8.5 register bank select flag (b flag) .......................................................................... 20 2.8.6 overflow flag (o flag) ............................................................................................. 20 2.8.7 interrupt enable flag (i flag) ................................................................................... 20 2.8.8 stack pointer select flag (u flag) ........................................................................... 20 2.8.9 processor interrupt priority level (ipl) .................................................................... 20 2.8.10 reserved area ....................................................................................................... 20 3. memory ____________________________________________________ 21 4. special function register (sfrs) ________________________________ 22
a-2 5. reset ______________________________________________________ 29 5.1 hardware reset ............................................................................................................. .29 5.1.1 hardware reset 1 .................................................................................................... 29 5.2 software reset ............................................................................................................. .. 30 5.3 watchdog timer reset ................................................................................................... 30 5.4 oscillation stop detection reset .................................................................................... 30 6. processor mode _____________________________________________ 32 7. clock generation circuits ______________________________________ 35 7.1 main clock ................................................................................................................. ..... 42 7.2 sub clock .................................................................................................................. ..... 43 7.3 on-chip oscillator clock ................................................................................................. 44 7.4 pll clock .................................................................................................................. ..... 44 7.5 cpu clock and peripheral function clock ..................................................................... 46 7.5.1 cpu clock ................................................................................................................ 46 7.5.2 peripheral function clock(f 1 , f 2 , f 8 , f 32 , f 1sio , f 2sio , f 8sio , f 32sio , f ad , f c32 ) ........... 46 7.5.3 clockoutput function ............................................................................................... 46 7.6 power control .............................................................................................................. ... 47 7.6.1 normal operation mode ........................................................................................... 47 7.6.2 wait mode ................................................................................................................ 48 7.6.3 stop mode ............................................................................................................... 50 7.7 system clock protective function .................................................................................. 54 7.8 oscillation stop and re-oscillation detect function ....................................................... 54 7.8.1 operation when cm27 bit = 0 (oscillation stop detection reset)........................... 55 7.8.2 operation when cm27 bit = 1 (oscillation stop and re-oscillation detect interrupt) ... 55 7.8.3 how to use oscillation stop and re-oscillation detect function ............................. 56 8. protection __________________________________________________ 57 9. interrupts ___________________________________________________ 58 9.1 type of interrupts ......................................................................................................... ... 58 9.1.1 software interrupts ................................................................................................... 59 9.1.2 hardware interrupts ................................................................................................. 60 9.2 interrupts and interrupt vector ........................................................................................ 61 9.2.1 fixed vector tables .................................................................................................. 61 9.2.2 relocatable vector tables ........................................................................................ 62 9.3 interrupt control .......................................................................................................... .... 63 9.3.1 i flag ................................................................................................................... ..... 66 9.3.2 ir bit ................................................................................................................... ..... 66 9.3.3 ilvl2 to ilvl0 bits and ipl...................................................................................... 66
a-3 9.4 interrupt sequence ......................................................................................................... 67 9.4.1 interrupt response time .......................................................................................... 68 9.4.2 variation of ipl when interrupt request is accepted ............................................... 68 9.4.3 saving registers ...................................................................................................... 69 9.4.4 returning from an interrupt routine ......................................................................... 71 9.5 interrupt priority ......................................................................................................... ..... 71 9.5.1 interrupt priority resolution circuit .......................................................................... 71 ______ 9.6 int interrupt .............................................................................................................. ..... 73 ______ 9.7 nmi interrupt .............................................................................................................. ..... 74 9.8 key input interrupt ........................................................................................................ .. 74 9.9 address match interrupt ................................................................................................. 75 10. watchdog timer ____________________________________________ 77 10.1 count source protective mode ..................................................................................... 78 11. dmac ____________________________________________________ 79 11.1 transfer cycles .......................................................................................................... .. 84 11.1.1 effect of source and destination addresses ......................................................... 84 11.1.2 effect of software wait .......................................................................................... 84 11.2 dma transfer cycles .................................................................................................... 86 11.3 dma enable ................................................................................................................ .. 87 11.4 dma request ............................................................................................................... .87 11.5 channel priority and dma transfer timing .................................................................. 88 12. timer _____________________________________________________ 89 12.1 timer a .................................................................................................................. ...... 91 12.1.1 timer mode ............................................................................................................ 94 12.1.2 event counter mode .............................................................................................. 95 12.1.3 one-shot timer mode .......................................................................................... 100 12.1.4. pulse width modulation (pwm) mode ................................................................ 102 12.2 timer b .................................................................................................................. .... 105 12.2.1 timer mode ......................................................................................................... 107 12.2.2 event counter mode ............................................................................................ 108 12.2.3 pulse period and pulse width measurement mode ............................................ 109 12.2.4 a/d trigger mode ................................................................................................ 111 12.3 three-phase motor control timer function ................................................................ 113 12.3.1 position-data-retain function ............................................................................. 124 12.3.2 three-phase/port output switch function ........................................................... 126
a-4 13. timer s __________________________________________________ 128 13.1 base timer ................................................................................................................ . 139 13.1.1 base timer reset register(g1btrr) ................................................................. 143 13.2 interrupt operation ..................................................................................................... 14 4 13.3 dma support .............................................................................................................. 1 44 13.4 time measurement function ...................................................................................... 145 13.5 waveform generating function .................................................................................. 149 13.5.1 single-phase waveform output mode ................................................................. 150 13.5.2 phase-delayed waveform output mode.............................................................. 152 13.5.3 set/reset waveform output (sr waveform output) mode ................................. 154 13.6 i/o port function select ............................................................................................. 156 13.6.1 inpc17 alternate input pin selection .................................................................. 157 ________ 13.6.2 digital debounce function for pin p17/int5/inpc17 .......................................... 157 14. serial i/o _________________________________________________ 158 14.1 uarti (i=0 to 2) .......................................................................................................... 158 14.1.1 clock synchronous serial i/o mode ..................................................................... 168 14.1.2 clock asynchronous serial i/o (uart) mode ..................................................... 176 14.1.3 special mode 1 (i 2 c bus mode) (uart2) ............................................................ 184 14.1.4 special mode 2 (uart2) ..................................................................................... 194 14.1.5 special mode 3 (iebus mode)(uart2) .............................................................. 198 14.1.6 special mode 4 (sim mode) (uart2)................................................................. 200 14.2 si/o3 and si/o4 ........................................................................................................ 20 5 14.2.1 si/oi operation timing ........................................................................................ 208 14.2.2 clk polarity selection ........................................................................................ 208 14.2.3 functions for setting an souti initial value ....................................................... 209 15. a/d converter _____________________________________________ 210 15.1 operating modes ........................................................................................................ 216 15.1.1 one-shot mode .................................................................................................... 216 15.1.2 repeat mode ........................................................................................................ 218 15.1.3 single sweep mode ............................................................................................ 220 15.1.4 repeat sweep mode 0 ......................................................................................... 222 15.1.5 repeat sweep mode 1 ......................................................................................... 224 15.1.6 simultaneous sample sweep mode .................................................................... 226 15.1.7 delayed trigger mode 0 ....................................................................................... 229 15.1.8 delayed trigger mode 1 ....................................................................................... 235 15.2 resolution select function ......................................................................................... 241 15.3 sample and hold ........................................................................................................ 241
a-5 15.4 power consumption reducing function .................................................................... 241 15.5 output impedance of sensor under a/d conversion ................................................. 242 16. multi-master i 2 c bus interface _________________________________ 243 16.1 i 2 c0 data shift register (s00 register) ....................................................................... 252 16.2 i 2 c0 address register (s0d0 register) ....................................................................... 252 16.3 i 2 c0 clock control register (s20 register) ................................................................ 253 16.3.1 bits 0 to 4: scl frequency control bits (ccr0?ccr4) ..................................... 253 16.3.2 bit 5: scl mode specification bit (fast mode) .............................................. 253 16.3.3 bit 6: ack bit (ackbit) ...................................................................................... 253 16.3.4 bit 7: ack clock bit (ack-clk) .......................................................................... 253 16.4 i 2 c0 control register 0 (s1d0) ................................................................................. 255 16.4.1 bits 0 to 2: bit counter (bc0?bc2) ..................................................................... 255 16.4.2 bit 3: i 2 c interface enable bit (es0) .................................................................... 255 16.4.3 bit 4: data format select bit (als) ..................................................................... 255 16.4.4 bit 6: i 2 c bus interface reset bit (ihr) ............................................................... 255 16.4.5 bit 7: i 2 c bus interface pin input level select bit (tiss) .................................... 256 16.5 i 2 c0 status register (s10 register) ........................................................................... 257 16.5.1 bit 0: last receive bit (lrb) ............................................................................... 257 16.5.2 bit 1: general call detection flag (adr0) .......................................................... 257 16.5.3 bit 2: slave address comparison flag (aas) ..................................................... 257 16.5.4 bit 3: arbitration lost detection flag (al)(1) ....................................................... 257 16.5.5 bit 4: i 2 c bus interface interrupt request bit (pin) ............................................. 258 16.5.6 bit 5: bus busy flag (bb) .................................................................................... 258 16.5.7 bit 6: communication mode select bit (transfer direction select bit: trx) ....... 259 16.5.8 bit 7: communication mode select bit (master/slave select bit: mst) ................ 259 16.6 i 2 c0 control register 1 (s3d0 register) .................................................................... 260 16.6.1 bit 0 : interrupt enable bit by stop condition (sim ) ......................................... 260 16.6.2 bit 1: interrupt enable bit at the completion of data receive (wit) .................. 260 16.6.3 bits 2,3 : port function select bits ped, pec .................................................... 261 16.6.4 bits 4,5 : sda/scl logic output value monitor bits sdam/sclm .................... 262 16.6.5 bits 6,7 : i 2 c system clock select bits ick0, ick1 ............................................ 262 16.6.6 address receive in stop/wait mode ............................................................... 262 16.7 i 2 c0 control register 2 (s4d0 register) ................................................................... 263 16.7.1 bit0: time-out detection function enable bit (toe) .......................................... 264 16.7.2 bit1: time-out detection flag (tof ).................................................................. 264 16.7.3 bit2: time-out detection period select bit (tosel) .......................................... 264 16.7.4 bits 3,4,5: i 2 c system clock select bits (ick2-4) ............................................... 264 16.7.5 bit7: stop condition detection interrupt request bit (scpin).......................... 264
a-6 16.8 i 2 c0 start/stop condition control register (s2d0 register) ............................... 265 16.8.1 bit0-bit4: start/stop condition setting bits (ssc0-ssc4) ............................ 265 16.8.2 bit5: scl/sda interrupt pin polarity select bit (sip) .......................................... 265 16.8.3 bit6 : scl/sda interrupt pin select bit (sis) ...................................................... 265 16.8.4 bit7: start/stop condition generation select bit (stspsel) ....................... 265 16.9 start condition generation method ....................................................................... 266 16.10 start condition duplicate protect function ........................................................... 267 16.11 stop condition generation method ........................................................................ 267 16.12 start/stop condition detect operation ............................................................... 269 16.13 address data communication ................................................................................. 270 16.13.1 example of master transmit ............................................................................. 270 16.13.2 example of slave receive ................................................................................ 271 16.14 precautions .............................................................................................................. . 272 17. crc calculation circuit _____________________________________ 275 17.1 crc snoop ................................................................................................................ 2 75 18. programmable i/o ports _____________________________________ 278 18.1 port pi direction register (pdi register, i = 0 to 3, 6 to 10) ....................................... 278 18.2 port pi register (pi register, i = 0 to 3, 6 to 10) ......................................................... 278 18.3 pull-up control register 0 to 2 (pur0 to pur2 registers) ........................................ 278 18.4 port control register (pcr register) ......................................................................... 278 18.5 pin assignment control register (pacr) ................................................................... 279 18.6 digital debounce function ......................................................................................... 279 19. flash memory version ______________________________________ 292 19.1 flash memory performance ....................................................................................... 292 19.1.1 boot mode ........................................................................................................... 293 19.2 memory map ............................................................................................................... 2 94 19.3 functions to prevent flash memory from rewriting .................................................. 296 19.3.1 rom code protect function ................................................................................ 296 19.3.2 id code check function ...................................................................................... 296 19.4 cpu rewrite mode ..................................................................................................... 298 19.4.1 ew mode 0 .......................................................................................................... 299 19.4.2 ew mode 1 .......................................................................................................... 299 19.5 register description ................................................................................................... 300 19.5.1 flash memory control register 0 (fmr0) ........................................................... 300 19.5.2 flash memory control register 1 (fmr1) ........................................................... 301 19.5.3 flash memory control register 4 (fmr4) ........................................................... 301
a-7 19.6 precautions in cpu rewrite mode ............................................................................. 306 19.6.1 operation speed .................................................................................................. 306 19.6.2 prohibited instructions .......................................................................................... 306 19.6.3 interrupts .............................................................................................................. 306 19.6.4 how to access ...................................................................................................... 306 19.6.5 writing in the user rom area .............................................................................. 306 19.6.6 dma transfer ....................................................................................................... 307 19.6.7 writing command and data ................................................................................. 307 19.6.8 wait mode ............................................................................................................ 307 19.6.9 stop mode ............................................................................................................ 307 19.6.10 low power consumption mode and on-chip oscillator-low power consumption mode ... 307 19.7 software commands .................................................................................................. 308 19.7.1 read array command (ff 16 )............................................................................... 308 19.7.2 read status register command (70 16 ) ............................................................... 308 19.7.3 clear status register command (50 16 ) ............................................................... 308 19.7.4 program command (40 16 ) ................................................................................... 309 19.7.5 block erase .......................................................................................................... 310 19.8 status register ........................................................................................................... 312 19.8.1 sequence status (sr7 and fmr00 bits ) ............................................................ 312 19.8.2 erase status (sr5 and fmr07 bits) ................................................................... 312 19.8.3 program status (sr4 and fmr06 bits) ............................................................... 312 19.8.4 full status check ................................................................................................. 313 19.9 standard serial i/o mode ........................................................................................... 315 19.9.1 id code check function ...................................................................................... 315 19.9.2 example of circuit application in standard serial i/o mode ................................ 319 19.10 parallel i/o mode ...................................................................................................... 32 1 19.10.1 rom code protect function .............................................................................. 321 20. electrical characteristics _____________________________________ 322 20.1 t version ................................................................................................................. .... 322 20.2 v version ................................................................................................................. ... 343 21. precautions _______________________________________________ 356 21.1 sfr ....................................................................................................................... ..... 356 21.1.1 for 80-pin package ............................................................................................. 356 21.1.2 for 64-pin package ............................................................................................. 356 21.1.3 register setting .................................................................................................... 356 21.2 clock generation circuit ............................................................................................. 357 21.2.1 pll frequency synthesizer ................................................................................. 357 21.2.2 power control ...................................................................................................... 358
a-8 21.3 protection ................................................................................................................ ... 361 21.4 interrupts ................................................................................................................ .... 362 21.4.1 reading address 00000 16 ..................................................................................................... 362 21.4.2 setting the sp ...................................................................................................... 362 _______ 21.4.3 nmi interrupt ....................................................................................................... 362 21.4.4 changing the interrupt generate factor .............................................................. 362 ______ 21.4.5 int interrupt ......................................................................................................... 36 3 21.4.6 rewrite the interrupt control register .................................................................. 364 21.4.7 watchdog timer interrupt ..................................................................................... 364 21.5 dmac ...................................................................................................................... ... 365 21.5.1 write to dmae bit in dmicon register ............................................................... 365 21.6 timer ..................................................................................................................... ...... 366 21.6.1 timer a ................................................................................................................. 366 21.6.2 timer b ................................................................................................................. 369 21.6.3 three-phase motor control timer function ......................................................... 370 21.7 timer s ................................................................................................................... .... 371 21.7.1 rewrite the g1ir register .................................................................................. 371 21.7.2 rewrite the icociic register ............................................................................. 372 21.7.3 waveform generating function .......................................................................... 372 21.7.4 ic/oc base timer interrupt .................................................................................. 372 21.8 serial i/o ................................................................................................................ ..... 373 21.8.1 clock-synchronous serial i/o .............................................................................. 373 21.8.2 uart mode .......................................................................................................... 374 21.8.3 si/o3, si/o4 ......................................................................................................... 374 21.9 a/d converter ............................................................................................................. 375 21.10 multi-master i 2 c bus interface ................................................................................. 377 21.10.1 writing to the s00 register ................................................................................ 377 21.10.2 al flag ............................................................................................................... 3 77 21.11 programmable i/o ports ........................................................................................... 378 21.12 electric characteristic differences between mask rom .......................................... 379 21.13 mask rom version ................................................................................................... 380 21.13.1 internal rom area ............................................................................................. 380 21.13.2 reserved bit ....................................................................................................... 380 21.14 flash memory version .............................................................................................. 381 21.14.1 functions to inhibit rewriting flash memory rewrite ........................................ 381 21.14.2 stop mode .......................................................................................................... 381 21.14.3 wait mode .......................................................................................................... 381 21.14.4 low power dissipation mode, on-chip oscillator low power dissipation mode ... 381 21.14.5 writing command and data ............................................................................... 381
a-9 21.14.6 program command ............................................................................................ 381 21.14.7 operation speed ................................................................................................ 381 21.14.8 instructions inhibited against use ...................................................................... 381 21.14.9 interrupts ............................................................................................................ 3 82 21.14.10 how to access .................................................................................................. 382 21.14.11 writing in the user rom area .......................................................................... 382 21.14.12 dma transfer ................................................................................................... 382 21.14.13 regarding programming/erasure times and execution time ......................... 382 21.14.14 definition of programming/erasure times ....................................................... 383 21.14.15 flash memory version electrical characteristics 10,000 e/w cycle product (u7)... 383 21.14.16 boot mode ........................................................................................................ 383 21.15 noise .................................................................................................................... .... 384 21.16 instruction for a device use ..................................................................................... 385 appendix 1. package dimensions ________________________________ 386 appendix 2. functional comparison _______________________________ 387 appendix 2.1 difference between m16c/28 group normal-ver. and m16c/28 group t-/v-ver. . 387 appendix 2.2 difference between m16c/28 group t-/v-ver. and m16c/29 group t-/v-ver. .. 388 register index ________________________________________________ 389
b-1 quick reference to pages classified by address int3 interrupt control register int3ic 65 ic/oc 0 interrupt control register icoc0ic 65 ic/oc 1 interrupt control register, icoc1ic 65 i 2 c bus interface interrupt control register iicic 65 ic/oc base timer interrupt control register, btic 65 s cl s da interrupt control register scldaic 65 si/o4 interrupt control register, s4ic, 65 int5 interrupt control register int5ic 65 si/o3 interrupt control register, s3ic, 65 int4 interrupt control register int4ic 65 uart2 bus collision detection interrupt control register bcnic 65 dma0 interrupt control register dm0ic 65 dma1 interrupt control register dm1ic 65 a/d conversion interrupt control register adic 65 key input interrupt control register kupic 65 uart2 transmit interrupt control register s2tic 65 uart2 receive interrupt control register s2ric 65 uart0 transmit interrupt control register s0tic 65 uart0 receive interrupt control register s0ric 65 uart1 transmit interrupt control register s1tic 65 uart1 receive interrupt control register s1ric 65 timer a0 interrupt control register ta0ic 65 timer a1 interrupt control register ta1ic 65 timer a2 interrupt control register ta2ic 65 timer a3 interrupt control register ta3ic 65 timer a4 interrupt control register ta4ic 65 timer b0 interrupt control register tb0ic 65 timer b1 interrupt control register tb1ic 65 timer b2 interrupt control register tb2ic 65 int0 interrupt control register int0ic 65 int1 interrupt control register int1ic 65 int2 interrupt control register int2ic 65 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 address note: the blank areas are reserved and cannot be accessed b y users. register symbol page 0040 16 0041 16 0042 16 0043 16 0044 16 0045 16 0046 16 0047 16 0048 16 0049 16 004a 16 004b 16 004c 16 004d 16 004e 16 004f 16 0050 16 0051 16 0052 16 0053 16 0054 16 0055 16 0056 16 0057 16 0058 16 0059 16 005a 16 005b 16 005c 16 005d 16 005e 16 005f 16 0060 16 0061 16 0062 16 0063 16 0064 16 0065 16 0066 16 0067 16 0068 16 0069 16 006a 16 006b 16 006c 16 006d 16 006e 16 006f 16 0070 16 0071 16 0072 16 0073 16 0074 16 0075 16 0076 16 0077 16 0078 16 to 017f 16 processor mode register 0 pm0 34 processor mode register 1 pm1 34 system clock control register 0 cm0 38 system clock control register 1 cm1 39 address match interrupt enable register aier 77 protect register prcr 58 oscillation stop detection register cm2 40 watchdog timer start register wdts 79 watchdog timer control register wdc 79 address match interrupt register 0 rmad0 77 address match interrupt register 1 rmad1 77 pll control register 0 plc0 42 processor mode register 2 pm2 35, 41 dma0 source pointer sar0 84 dma0 destination pointer dar0 84 dma0 transfer counter tcr0 84 dma0 control register dm0con 83 dma1 source pointer sar1 84 dma1 destination pointer dar1 84 dma1 transfer counter tcr1 84 dma1 control register dm1con 83 address register symbol page
b-2 quick reference to pages classified by address note 1: the blank areas are reserved and cannot be accessed by users. note 2: this register is included in the flash memory version. 0180 16 0181 16 0182 16 0183 16 0184 16 0185 16 0186 16 0187 16 to 01af 16 01b0 16 01b1 16 01b2 16 01b3 16 01b4 16 01b5 16 01b6 16 01b7 16 01b8 16 01b9 16 01ba 16 01bb 16 01bc 16 01bd 16 to 019f 16 0200 16 0201 16 0202 16 0203 16 0204 16 0205 16 0206 16 0207 16 0208 16 0209 16 020a 16 020b 16 020c 16 020d 16 020e 16 020f 16 0210 16 0211 16 0212 16 0213 16 0214 16 0215 16 0216 16 0217 16 0218 16 0219 16 021a 16 021b 16 021c 16 021d 16 021e 16 021f 16 0210 16 0211 16 to 02fd 16 02fe 16 02ff 16 address register symbol page flash memory control register 4 (note 2) fmr4 304 flash memory control register 1 (note 2) fmr1 303 flash memory control register 0 (note 2) fmr0 303 low-power consumption control register 0 lpcc0 359 0240 16 0241 16 0242 16 0243 16 0244 16 0245 16 0246 16 0247 16 0248 16 0249 16 024a 16 024c 16 024d 16 024e 16 024f 16 0250 16 0251 16 0252 16 0253 16 0254 16 0255 16 0256 16 0257 16 0258 16 0259 16 025a 16 025b 16 025c 16 025d 16 025e 16 025f 16 0260 16 0261 16 0262 16 0263 16 0264 16 0265 16 0266 16 0267 16 0268 16 0269 16 026a 16 026b 16 026c 16 026d 16 to 02df 16 02df 16 02e0 16 02e1 16 02e2 16 02e3 16 02e4 16 02e5 16 02e6 16 02e7 16 02e8 16 02e9 16 02ea 16 02eb 16 to 02fe 16 02fe 16 02ff 16 address register symbol page three-phase protect control register tprc 128 0n-chip oscillator control register rocr 39 pin assignment control register pacr 166, 289 peripheral clock select register pclkr 41 low-power consumption control register 1 lpcc1 359 i 2 c0 data shift register s00 247 i 2 c0 address register s0d0 246 i 2 c0 control register 0 s1d0 248 i 2 c0 clock control register s20 247 i 2 c0 start/stop condition control register s2d0 252 i 2 c0 control register 1 s3d0 250 i 2 c0 control register 2 s4d0 251 i 2 c0 status register s10 249
b-3 quick reference to pages classified by address note : the blank areas are reserved and cannot be accessed by users. 0340 16 0341 16 0342 16 0343 16 0344 16 0345 16 0346 16 0347 16 0348 16 0349 16 034a 16 034b 16 034c 16 034d 16 034e 16 034f 16 0350 16 0351 16 0352 16 0353 16 0354 16 0355 16 0356 16 0357 16 0358 16 0359 16 035a 16 035b 16 035c 16 035d 16 035e 16 035f 16 0360 16 0361 16 0362 16 0363 16 0364 16 0365 16 0366 16 0367 16 0368 16 0369 16 036a 16 036b 16 036c 16 036d 16 036e 16 036f 16 0370 16 0371 16 0372 16 0373 16 0374 16 0375 16 0376 16 0377 16 0378 16 0379 16 037a 16 037b 16 037c 16 037d 16 037e 16 037f 16 timer a1-1 register ta11 119 timer a2-1 register ta21 119 timer a4-1 register ta41 119 three-phase pwm control register 0 invc0 116 three-phase pwm control register 1 invc1 117 three-phase output buffer register 0 idb0 118 three-phase output buffer register 1 idb1 118 dead time timer dtt 118 timer b2 interrupt occurrence frequency set counter ictb2 118 position-data-retain function contol register pdrf 126 port function control register pfcr 128 interrupt request cause select register 2 ifsr2a 66 interrupt request cause select register ifsr 66, 74 si/o3 transmit/receive register s3trr 207 si/o3 control register s3c 207 si/o3 bit rate generator s3brg 207 si/o4 transmit/receive register s4trr 207 si/o4 control register s4c 207 si/o4 bit rate generator s4brg 207 uart2 special mode register 4 u2smr4 168 uart2 special mode register 3 u2smr3 168 uart2 special mode register 2 u2smr2 167 uart2 special mode register u2smr 167 uart2 transmit/receive mode register u2mr 164 uart2 bit rate generator u2brg 163 uart2 transmit buffer register u2tb 163 uart2 transmit/receive control register 0 u2c0 165 uart2 transmit/receive control register 1 u2c1 166 uart2 receive buffer register u2rb 163 address register symbol page 0300 16 0301 16 0302 16 0303 16 0304 16 0305 16 0306 16 0307 16 0308 16 0309 16 030a 16 030b 16 030c 16 030d 16 030e 16 030f 16 0310 16 0311 16 0312 16 0313 16 0314 16 0315 16 0316 16 0317 16 0318 16 0319 16 031a 16 031b 16 031c 16 031d 16 031e 16 031f 16 0320 16 0321 16 0322 16 0323 16 0324 16 0325 16 0326 16 0327 16 0328 16 0329 16 032a 16 032b 16 032c 16 032d 16 032e 16 032f 16 0330 16 0331 16 0332 16 0333 16 0334 16 0335 16 0336 16 0337 16 0338 16 0339 16 033a 16 033b 16 033c 16 033d 16 033e 16 033f 16 address register symbol page tm, wg register 0 g1tm0, g1po0 135, 136 tm, wg register 1 g1tm1, g1po1 135, 136 tm, wg register 2 g1tm2, g1po2 135, 136 tm, wg register 3 g1tm3, g1po3 135, 136 tm, wg register 4 g1tm4, g1po4 135, 136 tm, wg register 5 g1tm5, g1po5 135, 136 tm, wg register 6 g1tm6, g1po6 135, 136 tm, wg register 7 g1tm7, g1po7 135, 136 wg control register 0 g1pocr0 135 wg control register 1 g1pocr1 135 wg control register 2 g1pocr2 135 wg control register 3 g1pocr3 135 wg control register 4 g1pocr4 135 wg control register 5 g1pocr5 135 wg control register 6 g1pocr6 135 wg control register 7 g1pocr7 135 tm control register 0 g1tmcr0 134 tm control register 1 g1tmcr1 134 tm control register 2 g1tmcr2 134 tm control register 3 g1tmcr3 134 tm control register 4 g1tmcr4 134 tm control register 5 g1tmcr5 134 tm control register 6 g1tmcr6 134 tm control register 7 g1tmcr7 134 base timer register g1bt 131 base timer control register 0 g1bcr0 131 base timer control register 1 g1bcr1 132 tm prescale register 6 g1tpr6 134 tm prescale register 7 g1tpr7 134 function enable register g1fe 137 function select register g1fs 137 base timer reset register g1btrr 133 divider register g1dv 132 interrupt request register g1ir 138 interrupt enable register 0 g1ie0 139 interrupt enable register 1 g1ie1 139 nmi digital debounce register nddr 290 p1 7 digital debounce register p17ddr 290
b-4 quick reference to pages classified by address note : the blank areas are reserved and cannot be accessed by users. 03c0 16 03c1 16 03c2 16 03c3 16 03c4 16 03c5 16 03c6 16 03c7 16 03c8 16 03c9 16 03ca 16 03cb 16 03cc 16 03cd 16 03ce 16 03cf 16 03d0 16 03d1 16 03d2 16 03d3 16 03d4 16 03d5 16 03d6 16 03d7 16 03d8 16 03d9 16 03da 16 03db 16 03dc 16 03dd 16 03de 16 03df 16 03e0 16 03e1 16 03e2 16 03e3 16 03e4 16 03e5 16 03e6 16 03e7 16 03e8 16 03e9 16 03ea 16 03eb 16 03ec 16 03ed 16 03ee 16 03ef 16 03f0 16 03f1 16 03f2 16 03f3 16 03f4 16 03f5 16 03f6 16 03f7 16 03f8 16 03f9 16 03fa 16 03fb 16 03fc 16 03fd 16 03fe 16 03ff 16 a/d register 0 ad0 215 a/d register 1 ad1 215 a/d register 2 ad2 215 a/d register 3 ad3 215 a/d register 4 ad4 215 a/d register 5 ad5 215 a/d register 6 ad6 215 a/d register 7 ad7 215 a/d trigger control register adtrgcon 214 a/d convert status register 0 adstat0 215 a/d control register 2 adcon2 213 a/d control register 0 adcon0 213 a/d control register 1 adcon1 213 port p0 register p0 287 port p1 register p1 287 port p0 direction register pd0 286 port p1 direction register pd1 286 port p2 register p2 287 port p3 register p3 287 port p2 direction register pd2 286 port p3 direction register pd3 286 port p6 register p6 287 port p7 register p7 287 port p6 direction register pd6 286 port p7 direction register pd7 286 port p8 register p8 287 port p9 register p9 287 port p8 direction register pd8 286 port p9 direction register pd9 286 port p10 register p10 287 port p10 direction register pd10 286 pull-up control register 0 pur0 288 pull-up control register 1 pur1 288 pull-up control register 2 pur2 288 port control register pcr 289 address register symbol page 0380 16 0381 16 0382 16 0383 16 0384 16 0385 16 0386 16 0387 16 0388 16 0389 16 038a 16 038b 16 038c 16 038d 16 038e 16 038f 16 0390 16 0391 16 0392 16 0393 16 0394 16 0395 16 0396 16 0397 16 0398 16 0399 16 039a 16 039b 16 039c 16 039d 16 039e 16 039f 16 03a0 16 03a1 16 03a2 16 03a3 16 03a4 16 03a5 16 03a6 16 03a7 16 03a8 16 03a9 16 03aa 16 03ab 16 03ac 16 03ad 16 03ae 16 03af 16 03b0 16 03b1 16 03b2 16 03b3 16 03b4 16 03b5 16 03b6 16 03b7 16 03b8 16 03b9 16 03ba 16 03bb 16 03bc 16 03bd 16 03be 16 03bf 16 count start flag tabsr clock prescaler reset flag cpsrf one-shot start flag onsf 94 trigger select register trgsr 94, 121 up-down flag udf 93 timer a0 register ta0 93 timer a1 register ta1 93 timer a2 register ta2 93 timer a3 register ta3 93 timer a4 register ta4 93 timer b0 register tb0 107 timer b1 register tb1 107 timer b2 register tb2 107 timer a0 mode register ta0mr 92,122 timer a1 mode register ta1mr 92,122 timer a2 mode register ta2mr 92,122 timer a3 mode register ta3mr 92,122 timer a4 mode register ta4mr 92,122 timer b0 mode register tb0mr 106,122 timer b1 mode register tb1mr 106,122 timer b2 mode register tb2mr 106,122 timer b2 special mode register tb2sc 120,216 uart0 transmit/receive mode register u0mr 164 uart0 bit rate generator u0brg 163 uart0 transmit buffer register u0tb 163 uart0 transmit/receive control register 0 u0c0 165 uart0 transmit/receive control register 1 u0c1 165 uart0 receive buffer register u0rb 163 uart1 transmit/receive mode register u1mr 164 uart1 bit rate generator u1brg 163 uart1 transmit buffer register u1tb 163 uart1 transmit/receive control register 0 u1c0 165 uart1 transmit/receive control register 1 u1c1 166 uart1 receive buffer register u1rb 163 uart transmit/receive control register 2 ucon 165 crc snoop address register crcsar 277 crc mode register crcmr 277 dma0 request cause select register dm0sl 82 dma1 request cause select register dm1sl 83 crc data register crcd 277 crc input register crcin 277 93, 107, 121 94, 107 address register symbol page
m16c/28 group (t-ver./v-ver.) single-chip 16-bit cmos microcomputer page 1 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 1. overview 1.1 features the m16c/28 group (t-ver./v-ver.) of single-chip control mcu incorporates the m16c/60 series cpu core, employing the high-performance silicon gate cmos technology and sophisticated instructions for a high level of efficiency. the m16c/28 group (t-ver./v-ver.) is housed in 64-pin and 80-pin plastic molded lqfp packages. this single-chip mcu operates using sophisticated instructions featuring a high level of instruction efficiency. this mcu is capable of executing instructions at high speed, makes it suitable for control of cars and lan system of fa. in addition, the cpu core boasts a multiplier and dmac for high- speed processing to make adequate for office automation, communication devices, and other high-speed processing applications. , also making it suitable for control of various oa, communication, and industrial equipment which requires high-speed arithmetic/logic operations. 1.1.1 applications automotive body, car audio, lan system of fa, etc.
1. overview page 2 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r item performance cpu number of basic instructions 91 instructions shortest instruction 50 ns (f(bclk)= 20mh z , v cc = 3.0 to 5.5v) (t-ver.) excution time 50 ns (f(bclk)= 20mh z , v cc = 4.2 to 5.5v, -40 to 105 c) (v-ver.) 62.5 ns (f(bclk)= 16mh z , v cc = 4.2 to 5.5v, -40 to 125 c) (v-ver.) operation mode single chip mode address space 1 mbytes memory capacity rom/ram : see table 1.3 and table 1.4 peripheral port input/output : 71 lines function multifunction timer timera:16 bits x 5 channels, timerb:16 bits x 3 channels three-phase motor control timer timers (input capture/output compare) : 16bit base timer x 1 channel (input/output x 8 channels ) serial i/o 2 channels (uart, clock synchronous serial i/o) 1 channel ( uart, clock synchronous serial i/o, i 2 c bus, or iebus (1) ) 2 channels (clock synchronous serial i/o) 1 channel (multi-master i 2 c bus) a/d converter 10 bits x 27 channels dmac 2 channels crc calculation circuit 2 polynomial (crc-ccitt and crc-16) with msb/lsb selectable watchdog timer 15 bits x 1 channel (with prescaler) interrupt 25 internal and 8 external sources, 4 software sources, 7 levels clock generation circuit 4 circuits ? main clock ? sub-clock ? on-chip oscillator (main-clock oscillation stop detect function) ? pll frequency synthesizer oscillation stop detect main clock oscillation stop, re-oscillation detect function function voltage detection circuit not available electrical power supply voltage v cc =3.0 to 5.5v (t-ver.) characteristics v cc =4.2 to 5.5v (v-ver.) power consumption 18ma (v cc =5v, f(bclk)=20mhz) 25 a (v cc =5v, f(bclk)=f(x cin )=32khz on ram) 3 a (v cc =5v, f(bclk)=f(x cin )=32khz, in wait mode) 0.8 a (v cc =5v, in stop mode) flash memory program/erase voltage 3.0v to 5.5v (t-ver.) 4.2v to 5.5v (v-ver.) number of program/erase 100 times (all space) or 1,000 times (blocks 0 to 4)/ 10,000 times (blocks a and b (2) ) operating ambient temperature -40 to 85 c (t-ver.), -40 to 125 c (v-ver.) package 80-pin plastic mold lqfp table 1.1 performance overview of m16c/28 group (t-ver./v-ver.) (80-pin package) 1.1.2 specifications table 1.1 lists performance overview of m16c/28 group (t-ver./v-ver.) 80-pin package. table 1.2 lists performance overview of m16c/28 group (t-ver./v-ver.) 64-pin package. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (these circuits contain a built-in feedback resistor) notes: 1. iebus is a trademark of nec electronics corporation. 2. refer to table 1.5 and table 1.6 for number of program/erase endurance and ambient temperature.
1. overview page 3 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r table 1.2 performance overview of m16c/28 group (64-pin package) item performance cpu number of basic instructions 91 instructions shortest instruction 50 ns (f(bclk)= 20mh z , v cc = 3.0 to 5.5v) (t-ver.) excution time 50 ns (f(bclk)= 20mh z , v cc = 4.2 to 5.5v, -40 to 105 c) (v-ver.) 62.5 ns (f(bclk)= 16mh z , v cc = 4.2 to 5.5v, -40 to 125 c) (v-ver.) operation mode single chip mode address space 1 mbytes memory capacity rom/ram : see table 1.3 and table 1.4 peripheral port input/output : 55 lines function multifunction timer timera:16 bits x 5 channels, timerb:16 bits x 3 channels three-phase motor control timer timers (input capture/output compare) : 16bit base timer x 1 channel (input/output x 8 channels ) serial i/o 2 channels (uart, clock synchronous serial i/o) 1 channel ( uart, clock synchronous serial i/o, i 2 c bus, or iebus (1) ) 1 channel (clock synchronous serial i/o) 1 channel (multi-master i 2 c bus) a/d converter 10 bits x 16 channels dmac 2 channels crc calculation circuit 2 polynomial (crc-ccitt and crc-16) with msb/lsb selectable watchdog timer 15 bits x 1 channel (with prescaler) interrupt 24 internal and 8 external sources, 4 software sources, 7 levels clock generation circuit 4 circuits ? main clock ? sub-clock ? on-chip oscillator (main-clock oscillation stop detect function) ? pll frequency synthesizer oscillation stop detect main clock oscillation stop, re-oscillation detect function function voltage detection circuit not available electrical power supply voltage v cc =3.0 to 5.5v (t-ver.) characteristics v cc =4.2 to 5.5v (v-ver.) power consumption 18ma (v cc =5v, f(bclk)=20mhz) 25 a (v cc =5v, f(bclk)=f(x cin )=32khz on ram) 3 a (v cc =5v, f(bclk)=f(x cin )=32khz, in wait mode) 0.8 a (v cc =5v, in stop mode) flash memory program/erase voltage 3.0v to 5.5v (t-ver.) 4.2v to 5.5v (v-ver.) number of program/erase 100 times (all space) or 1,000 times (blocks 0 to 4)/ 10,000 times (blocks a and b (2) ) operating ambient temperature -40 to 85 c (t-ver.), -40 to 125 c (v-ver.) package 64-pin plastic mold lqfp notes: 1. iebus is a trademark of nec electronics corporation. 2. refer to table 1.5 and table 1.6 for number of program/erase endurance and ambient temperature. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (these circuits contain a built-in feedback resistor)
1. overview page 4 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 1.2 block diagram figure 1.1 is a block diagram of the m16c/28 group (t-ver./v-ver.), 80-pin package. figure 1.1 m16c/28 group (t-ver./v-ver.), 80-pin package block diagram output (timer a) : 5 input ( timer b) : 3 i n t e r n a l p e r i p h e r a l f u n c t i o n s w a t c h d o g t i m e r ( 1 5 b i t s ) dmac ( 2 cha nnels) m e m o r y rom (1 ) r a m ( 2 ) a/d conv erte r uart/clock synchronous si/o (8 bits x 3 chann els) system clock generator x in -x ou t x cin -x cout on-chip oscillator pll frequency syn thesizer m 1 6 c / 6 0 s e r i e s c p u c o r e r0 l r 0 h r 1 hr 1l r 2 r 3 a 0 a 1 f b sb i s p us p intb m u l t i p l i e r 8 p o r t p 1 0 7 p o r t p 9 8 p o r t p 8 p o r t p 7 8 p o r t p 6 8 port p 2 8 p c f l g t i m e r ( 1 6 b i t s ) 3-phase p wm p o r t p 3 8 p o r t p 1 8 i / o p o r t s port p 0 8 clock synchronous si/o (8 bits x 2 chann els) multi-master i 2 c bus ( ) timer s input capture/ output compare time measurem en t : 8 chann els waveform generati ng : 8 ch annels crc calculation circuit (crc-ccitt and crc16 ) notes: 1. rom size depends on mcu type. 2. ram size depends on mcu type. (10 bits x 27 channels)
1. overview page 5 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 1.2 is a block diagram of the m16c/28 group (t-ver./v-ver.), 64-pin package. figure 1.2 m16c/28 group (t-ver./v-ver.), 64-pin package block diagram ou tput (timer a) : 5 input (ti mer b) : 3 i n t e r n a l p e r i p h e r a l f u n c t i o n s w a t c h d o g t i m e r ( 1 5 b i t s ) dmac (2 chann els) memory r o m ( 1 ) r a m ( 2 ) uart/clock synchro nous si/o (8 bits x 3 chann els) system clock generator x in -x ou t x ci n -x cout on-chip oscillator pll frequency syn thesizer m16c/60 series cpu cor e r 0 l r0h r1h r 1 l r 2 r 3 a 0 a 1 fb s b i s p us p i n t b multipli er 8 p o r t p 1 0 4 p o r t p 9 8 p o r t p 8 p o r t p 7 8 p o r t p 6 8 port p 2 8 pc fl g t i m e r ( 1 6 b i t s ) 3-phase p wm p o r t p 3 4 p o r t p 1 3 i / o p o r t s p o r t p 0 4 t i m e r s i n p u t c a p t u r e / o u t p u t c o m p a r e t i m e m e a s u r e m e n t : 8 c h a n n e l s w a v e f o r m g e n e r a t i n g : 8 c h a n n e l s c l o c k s y n c h r o n o u s s i / o ( 8 b i t s x 1 c h a n n e l ) m u l t i - m a s t e r i 2 c b u s ( ) a / d c o n v e r t e r crc calculation circuit (crc-ccitt and crc16 ) notes: 1. rom size depends on mcu type. 2. ram size depends on mcu type. (10 bits x 16 channels)
1. overview page 6 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 1.3 product list tables 1.3 and 1.4 list the m16c/28 group (t-ver./v-ver.) products and figure 1.3 shows the type num- bers, memory sizes and packages. tables 1.5 and 1.8 list the product code for m16c/28 group. figure 1.4 shows the marking diagram of flash memory version for m16c/28 group t version. figure 1.5 shows the marking diagram of flash memory version for m16c/28 group v version. table 1.3 product list (1) -t version as of march, 2007 r e b m u n e p y t m o r y t i c a p a c m a r y t i c a p a c e p y t e g a k c a ps k r a m e r t c u d o r p e d o c p h t a f 0 8 2 0 3 mk 4 + k 6 9k 8) a - q 6 p 0 8 ( a - b k 0 8 0 0 p q l p h s a l f y r o m e m 7 u , 3 u p h t a f 1 8 2 0 3 mk 4 + k 6 9k 8) a - q 6 p 4 6 ( a - b k 4 6 0 0 p q l p p h x x x - t 8 m 0 8 2 0 3 mk 4 6k 4 ) a - q 6 p 0 8 ( a - b k 0 8 0 0 p q l p m o r k s a m0 u p h x x x - t a m 0 8 2 0 3 mk 6 9k 8 p h x x x - t 8 m 1 8 2 0 3 mk 4 6k 4 ) a - q 6 p 4 6 ( a - b k 4 6 0 0 p q l p p h x x x - t a m 1 8 2 0 3 mk 6 9k 8 r e b m u n e p y t m o r y t i c a p a c m a r y t i c a p a c e p y t e g a k c a ps k r a m e r t c u d o r p e d o c p h v a f 0 8 2 0 3 mk 4 + k 6 9k 8) a - q 6 p 0 8 ( a - b k 0 8 0 0 p q l p h s a l f y r o m e m 7 u , 3 u p h v a f 1 8 2 0 3 mk 4 + k 6 9k 8) a - q 6 p 4 6 ( a - b k 4 6 0 0 p q l p p h x x x - v 8 m 0 8 2 0 3 mk 4 6k 4 ) a - q 6 p 0 8 ( a - b k 0 8 0 0 p q l p m o r k s a m0 u p h x x x - v a m 0 8 2 0 3 mk 6 9k 8 p h x x x - v 8 m 1 8 2 0 3 mk 4 6k 4 ) a - q 6 p 4 6 ( a - b k 4 6 0 0 p q l p p h x x x - v a m 1 8 2 0 3 mk 6 9k 8 table 1.4 product list (2) -v version as of march, 2007
1. overview page 7 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 1.3 product numbering system version (no): normal-ver. t : t-ver. v : v-ver. rom capacity /ram capacity: 8: (64k+4k) bytes (note 1) /4k bytes a: (96k+4k) bytes (note 1) /8k bytes note 1: only flash memory version exists in "+4k bytes" memory type: m: mask rom version f: flash memory version type no. m 3 0 2 8 0 f a t h p - u3 m16c/28 group m16c family show pin count (the value itself has no specific meaning) product code package type: hp : package plqp0080kb-a(80p6q-a) plqp0064kb-a(64p6q-a)
1. overview page 8 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r table 1.5 product code of flash memory version -m16c/28 group t-ver. table 1.6 product code of flash memory version -m16c/28 group v-ver. t c u d o r p e d o c e g a k c a p m o r l a n r e t n i ) 4 o t 0 s k c o l b : e c a p s m a r g o r p ( m o r l a n r e t n i ) b d n a a s k c o l b : e c a p s a t a d ( t n e i b m a g n i t a r e p o e r u t a r e p m e t d n a m a r g o r p e s a r e e c n a r u d n e e r u t a r e p m e t e g n a r d n a m a r g o r p e s a r e e c n a r u d n e e r u t a r e p m e t e g n a r 3 u e e r f - d a e l 0 0 1 c o 0 6 o t 0 0 0 1 c o 5 8 o t 0 4 -c o 5 8 o t 0 4 - 7 u0 0 0 , 10 0 0 , 0 1 t c u d o r p e d o c e g a k c a p m o r l a n r e t n i ) 4 o t 0 s k c o l b : e c a p s m a r g o r p ( m o r l a n r e t n i ) b d n a a s k c o l b : e c a p s a t a d ( t n e i b m a g n i t a r e p o e r u t a r e p m e t d n a m a r g o r p e s a r e e c n a r u d n e e r u t a r e p m e t e g n a r d n a m a r g o r p e s a r e e c n a r u d n e e r u t a r e p m e t e g n a r 3 u e e r f - d a e l 0 0 1 c o 0 6 o t 0 0 0 1 c o 5 2 1 o t 0 4 -c o 5 2 1 o t 0 4 - 7 u0 0 0 , 10 0 0 , 0 1 table 1.7 product code of mask rom version -m16c/28 group t-ver. table 1.8 product code of mask rom version -m16c/28 group v-ver. t c u d o r p e d o c e g a k c a p t n e i b m a g n i t a r e p o e r u t a r e p m e t 0 ue e r f - d a e lc o 5 8 o t 0 4 - t c u d o r p e d o c e g a k c a p t n e i b m a g n i t a r e p o e r u t a r e p m e t 0 ue e r f - d a e lc o 5 2 1 o t 0 4 -
1. overview page 9 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r m16c m30280fathp a u3 xxxxxxx product name : indicates m30280fathp chip version and product code: a : indicates chip version the first edition is shown to be blank and continues with a and b. u3 : indicates product code (see table 1.5 ) date code (7 digits) : indicates manufacturing management code a u3 m30281fathp xxxxxxx chip version and product code: a : indicates chip version the first edition is shown to be blank and continues with a and b. u3 : indicates product code (see table 1.5 ) product name : indicates m30281fathp date code (7 digits) : indicates manufacturing management code (1) flash memory version, plqp0080kb-a (80p6q-a), t-ver. (2) flash memory version, plqp0064kb-a (64p6q-a), t-ver. m16c m30280favhp a u3 xxxxxxx product name : indicates m30280favhp chip version and product code: a : indicates chip version the first edition is shown to be blank and continues with a and b. u3 : indicates product code (see table 1.6 ) date code (7 digits) : indicates manufacturing management code a u3 m30281favhp xxxxxxx chip version and product code: a : indicates chip version the first edition is shown to be blank and continues with a and b. u3 : indicates product code (see table 1.6 ) product name : indicates m30281favhp date code (7 digits) : indicates manufacturing management code (1) flash memory version, plqp0080kb-a (80p6q-a), v-ver. (2) flash memory version, plqp0064kb-a (64p6q-a), v-ver. figure 1.4 marking diagram of flash memory version - m16c/28 group t-ver. (top view) figure 1.5 marking diagram of flash memory version - m16c/28 group v-ver. (top view)
1. overview page 10 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r m16c/28 group (t-ver./v-ver.) plqp0080kb-a (80p6q-a) (top view) figure 1.6 pin assignment (top view) of 80-pin package 123 45 678 91 01 11 21 31 41 51 61 71 81 92 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 5 6 p 6 1 / c l k 0 p 3 5 p 3 4 p 3 3 p 3 2 / s o u t 3 p 3 1 / s i n 3 p 3 7 p 6 7 / t x d 1 p 7 1 / r x d 2 / s c l 2 / t a 0 i n / c l k 1 p 7 2 / c l k 2 / t a 1 o u t / v / r x d 1 p 7 3 / c t s 2 / r t s 2 / t a 1 i n / v / t x d 1 p 6 5 / c l k 1 p 6 6 / r x d 1 p 6 4 / c t s 1 / r t s 1 / c t s 0 / c l k s 1 p 7 0 / t x d 2 / s d a 2 / t a 0 o u t / c t s 1 / r t s 1 / c t s 0 / c l k s 1 p 7 5 / t a 2 i n / w p 3 0 / c l k 3 p 7 4 / t a 2 o u t / w p 1 0 / a n 2 0 p 1 1 / a n 2 1 p 1 2 / a n 2 2 p 1 5 / i n t 3 / a d t r g / i d v p 1 6 / i n t 4 / i d w p 1 7 / i n t 5 / i n p c 1 7 / i d u p 2 0 / o u t c 1 0 / i n p c 1 0 / s d a m m p 2 1 / o u t c 1 1 / i n p c 1 1 / s c l m m p 2 2 / o u t c 1 2 / i n p c 1 2 p 2 3 / o u t c 1 3 / i n p c 1 3 p 2 4 / o u t c 1 4 / i n p c 1 4 p 2 5 / o u t c 1 5 / i n p c 1 5 p 2 6 / o u t c 1 6 / i n p c 1 6 p 2 7 / o u t c 1 7 / i n p c 1 7 p 6 0 / c t s 0 / r t s 0 v c c x i n x o u t v s s r e s e t c n v s s p 8 7 / x c i n p 8 6 / x c o u t p 7 6 / t a 3 o u t p 7 7 / t a 3 i n p 9 2 /an3 2 /tb2 in p 9 3 / a n 2 4 p 9 5 /an2 5 /clk 4 p 9 1 /an3 1 /tb1 in p 8 2 / i n t 0 p 8 3 / i n t 1 p 8 1 / t a 4 i n / u p 8 4 / i n t 2 / z p p 8 0 / t a 4 o u t / u p 8 5 / n m i / s d p 0 0 / a n 0 0 p 0 1 / a n 0 1 p 0 2 / a n 0 2 p 0 3 / a n 0 3 p 0 4 / a n 0 4 p 0 5 / a n 0 5 p 0 6 / a n 0 6 p 0 7 / a n 0 7 v r e f a v s s a v c c p 1 0 0 / a n 0 p 1 0 1 / a n 1 p 1 0 2 / a n 2 p 1 0 3 / a n 3 p 1 0 4 / a n 4 / k i 0 p 1 0 5 / a n 5 / k i 1 p 1 0 6 / a n 6 / k i 2 p 1 0 7 / a n 7 / k i 3 p 9 6 / a n 2 6 / s o u t 4 p 9 7 / a n 2 7 / s i n 4 / tb0 in /clk ou t p 6 3 / t x d 0 p 6 2 / r x d 0 p 3 6 p 1 3 / a n 2 3 p 1 4 notes: 1. set bits pacr2 to pacr0 in the pacr register to 011 2 before you input and output it after resetting to each pin. when the pacr register is not set, the input and output function of some of the pins are disabled. 1.4 pin configuration figures 1.6 and 1.7 show the pin configurations (top view).
1. overview page 11 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r table 1.9 pin characteristics for 80-pin package n i p . o n l o r t n o c n i p t r o p t p u r r e t n i n i p n i p r e m i tn i p s r e m i tn i p t r a u r e t s a m - i t l u m i 2 n i p s u b c n i p g o l a n a 19 p 5 k l c 4 2 n a 5 29 p 3 2 n a 4 39 p 2 b t n i 2 3 n a 2 49 p 1 b t n i 1 3 n a 1 5k l c t u o 9 p 0 b t n i 0 3 n a 0 6s s v n c 7x n i c 8 p 7 8x t u o c 8 p 6 9t e s e r 0 1x t u o 1 1s s v 2 1x n i 3 1c c v 4 18 p 5 i m nd s 5 18 p 4 t n i 2 p z 6 18 p 3 t n i 1 7 18 p 2 t n i 0 8 18 p 1 a t n i 4 u / 9 18 p 0 a t t u o 4 u / 0 27 p 7 a t n i 3 1 27 p 6 a t t u o 3 2 27 p 5 a t n i 2 w / 3 27 p 4 a t t u o 2 w / 4 27 p 3 a t n i 1 v /s t c 2 s t r / 2 t / x d 1 5 27 p 2 a t t u o 1 v /k l c 2 r / x d 1 6 27 p 1 a t n i 0 r x d 2 l c s / 2 k l c / 1 7 27 p 0 a t t u o 0 t x d 2 a d s / 2 s t r / 1 / s t c 1 s t c / 0 s k l c / 1 8 26 p 7 t x d 1 9 26 p 6 r x d 1 0 36 p 5 k l c 1 1 36 p 4 s t r 1 s t c / 1 s t c / 0 / s k l c 1 2 33 p 7 3 33 p 6 4 33 p 5 5 33 p 4 6 33 p 3 7 33 p 2 s 3 t u o 8 33 p 1 s 3 n i 9 33 p 0 k l c 3 0 46 p 3 t x d 0
1. overview page 12 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r table 1.9 pin characteristics for 80-pin package (continued) n i p . o n l o r t n o c n i p t r o p t p u r r e t n i n i p n i p r e m i tn i p s r e m i tn i p t r a u r e t s a m - i t l u m i 2 n i p s u b c n i p g o l a n a 1 46 p 2 r x d 0 2 46 p 1 k l c 0 3 46 p 0 s t r 0 s t c / 0 4 42 p 7 1 c t u o 7 1 c p n i / 7 5 42 p 6 1 c t u o 6 1 c p n i / 6 6 42 p 5 1 c t u o 5 1 c p n i / 5 7 42 p 4 1 c t u o 4 1 c p n i / 4 8 42 p 3 1 c t u o 3 1 c p n i / 3 9 42 p 2 1 c t u o 2 1 c p n i / 2 0 52 p 1 1 c t u o 1 1 c p n i / 1 l c s m m 1 52 p 0 1 c t u o 0 1 c p n i / 0 a d s m m 2 51 p 7 t n i 5 u d i1 c p n i 7 3 51 p 6 t n i 4 w d i 4 51 p 5 t n i 3 v d id a g r t 5 51 p 4 6 51 p 3 2 n a 3 7 51 p 2 2 n a 2 8 51 p 1 2 n a 1 9 51 p 0 2 n a 0 0 60 p 7 0 n a 7 1 60 p 6 0 n a 6 2 60 p 5 0 n a 5 3 60 p 4 0 n a 4 4 60 p 3 0 n a 3 5 60 p 2 0 n a 2 6 60 p 1 0 n a 1 7 60 p 0 0 n a 0 8 60 1 p 7 i k 3 n a 7 9 60 1 p 6 i k 2 n a 6 0 70 1 p 5 i k 1 n a 5 1 70 1 p 4 i k 0 n a 4 2 70 1 p 3 n a 3 3 70 1 p 2 n a 2 4 70 1 p 1 n a 1 5 7s s v a 6 70 1 p 0 n a 0 7 7v f e r 8 7c c v a 9 79 p 7 s 4 n i 2 n a 7 0 89 p 6 s 4 t u o 2 n a 6
1. overview page 13 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 3 2 3 1 3 0 2 9 2 8 2 6 2 5 2 4 2 3 2 2 2 1 20 19 1 8 1 7 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 61 6 2 6 3 2 7 64 4 8 4 7 4 6 4 5 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 4 4 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 p 0 3 / a n 0 3 p 1 5 / i n t 3 / a d t r g / i d v p 1 6 / i n t 4 / i d w p 1 7 / i n t 5 / i n p c 1 7 / i d u p 2 0 / o u t c 1 0 / i n p c 1 0 / s d a m m p 2 1 / o u t c 1 1 / i n p c 1 1 / s c l m m p 2 2 / o u t c 1 2 / i n p c 1 2 p 2 5 / o u t c 1 5 / i n p c 1 5 p 2 3 / o u t c 1 3 / i n p c 1 3 p 2 4 / o u t c 1 4 / i n p c 1 4 p 2 6 / o u t c 1 6 / i n p c 1 6 p6 6 /rxd 1 p3 0 /clk 3 p3 1 /s in3 p3 2 /s out3 p3 3 p6 4 /cts 1 /rts 1 /cts0/clks1 p6 5 /clk 1 p6 7 /txd 1 p7 0 /txd 2 /sda 2 /ta0 out /rts1/cts1/cts0/clks1 p7 1 /rxd 2 /scl 2 /ta0 in /clk1 p7 6 /ta3 out p7 4 /ta2 out /w p7 5 /ta2 in /w p7 2 /clk 2 /ta1 out /v/rxd1 p7 3 /cts 2 /rts 2 /ta1 in /v/txd1 p 0 0 / a n 0 0 p 1 0 7 / a n 7 / k i 3 p 1 0 4 / a n 4 / k i 0 p 1 0 3 / a n 3 p 1 0 2 / a n 2 p 1 0 1 / a n 1 a v s s p 1 0 0 / a n 0 v ref a v c c p 9 3 / a n 2 4 p9 2 /an3 2 /tb2 in p 0 2 / a n 0 2 p 0 1 / a n 0 1 p 1 0 6 / a n 6 / k i 2 p 1 0 5 / a n 5 / k i 1 p9 0 /an3 0 /tb0 in /clk out c n v s s p 8 7 / x c i n p 8 6 / x c o u t r e s e t x o u t x i n v c c p 8 4 / i n t 2 / z p p 8 5 / n m i / s d p 8 1 / t a 4 i n / u p 8 0 / t a 4 o u t / u p 7 7 / t a 3 i n p 9 1 / a n 3 1 / t b 1 i n p 8 3 / i n t 1 v s s p 2 7 / o u t c 1 7 / i n p c 1 7 p 6 0 / c t s 0 / r t s 0 p 6 1 / c l k 0 p 6 2 / r x d 0 p 6 3 / t x d 0 p 8 2 / i n t 0 note: 1. set bits pacr2 to pacr0 in the pacr register to 010 2 before you input and output it after resetting to each pin. when the pacr register is not set, the input and output function of some of the pins are disabled. figure 1.7 pin assignment (top view) of 64-pin package m16c/28 group (t-ver./v-ver.) plqp0064kb-a (64p6q-a) (top view)
1. overview page 14 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r table 1.10 pin characteristics for 64-pin package n i p . o n l o r t n o c n i p t r o p t p u r r e t n i n i p n i p r e m i tn i p s r e m i tn i p t r a u r e t s a m - t l u m i 2 n i p s u b c n i p g o l a n a 19 p 1 b t n i 1 3 n a 1 2k l c t u o 9 p 0 b t n i 0 3 n a 0 3s s v n c 4x n i c 8 p 7 5x t u o c 8 p 6 6t e s e r 7x t u o 8s s v 9x n i 0 1c c v 1 18 p 5 i m nd s 2 18 p 4 t n i 2 p z 3 18 p 3 t n i 1 4 18 p 2 t n i 0 5 18 p 1 a t n i 4 u / 6 18 p 0 a t t u o 4 u / 7 17 p 7 a t n i 3 8 17 p 6 a t t u o 3 9 17 p 5 a t n i 2 w / 0 27 p 4 a t t u o 2 w / 1 27 p 3 a t n i 1 v /s t c 2 s t r / 2 t / x d 1 2 27 p 2 a t t u o 1 v /k l c 2 r / x d 1 3 27 p 1 a t n i 0 r x d 2 l c s / 2 k l c / 1 4 27 p 0 a t t u o 0 t x d 2 a d s / 2 s t r / 1 / s t c 1 s t c / 0 s k l c / 1 5 26 p 7 t x d 1 6 26 p 6 r x d 1 7 26 p 5 k l c 1 8 26 p 4 s t r 1 s t c / 1 s t c / 0 / s k l c 1 9 23 p 3 0 33 p 2 s 3 t u o 1 33 p 1 s 3 n i 2 33 p 0 k l c 3 3 36 p 3 t x d 0 4 36 p 2 r x d 0 5 36 p 1 k l c 0 6 36 p 0 s t r 0 s t c / 0 7 32 p 7 1 c t u o 7 1 c p n i / 7 8 32 p 6 1 c t u o 6 1 c p n i / 6 9 32 p 5 1 c t u o 5 1 c p n i / 5 0 42 p 4 1 c t u o 4 1 c p n i / 4
1. overview page 15 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r table 1.10 pin characteristics for 64-pin package (continued) n i p . o n l o r t n o c n i p t r o p t p u r r e t n i n i p n i p r e m i tn i p s r e m i tn i p t r a u r e t s a m - i t l u m i 2 n i p s u b c n i p g o l a n a 1 42 p 3 1 c t u o 3 1 c p n i / 3 2 42 p 2 1 c t u o 2 1 c p n i / 2 3 42 p 1 1 c t u o 1 1 c p n i / 1 l c s m m 4 42 p 0 1 c t u o 0 1 c p n i / 0 a d s m m 5 41 p 7 t n i 5 u d i1 c p n i 7 6 41 p 6 t n i 4 w d i 7 41 p 5 t n i 3 v d id a g r t 8 40 p 3 0 n a 3 9 40 p 2 0 n a 2 0 50 p 1 0 n a 1 1 50 p 0 0 n a 0 2 50 1 p 7 i k 3 n a 7 3 50 1 p 6 i k 2 n a 6 4 50 1 p 5 i k 1 n a 5 5 50 1 p 4 i k 0 n a 4 6 50 1 p 3 n a 3 7 50 1 p 2 n a 2 8 50 1 p 1 n a 1 9 5s s v a 0 60 1 p 0 n a 0 1 6v f e r 2 6c c v a 3 69 p 3 2 n a 4 4 69 p 2 b t n i 2 3 n a 2
1. overview page 16 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 1.5 pin description apply 0v to the vss pin. apply following voltage to the vcc pin. 2.7 to 5.5 v (normal), 3.0 to 5.5 v (t-ver.), 4.2 to 5.5 v (v-ver.) supplies power to the a/d converter. connect the av cc pin to v cc and the av ss pin to v ss ___________ the microcomputer is in a reset state when "l" is applied to the reset pin connect the cnv ss pin to v ss i/o pins for the main clock oscillation circuit. connect a ceramic resonator or crystal oscillator between x in and x out . to apply external clock, apply it to x in and leave x out open. if x in is not used (for external oscillator or external clock) connect x in pin to v cc and leave x out open i/o pins for the sub clock oscillation circuit. connect a crystal oscillator between x cin and x cout outputs the clock having the same frequency as f1, f 8 , f 32 , or f c ______ ________ input pins for the int interrupt. int2 can be used for timer a z-phase function _______ _______ input pin for the nmi interrupt. nmi cannot be used as i/o port while the three- _______ phase motor control is enabled. apply a stable "h" to nmi after setting it's direction register to "0" when the three-phase motor control is enabled input pins for the key input interrupt i/o pins for the timer a0 to a4 input pins for the timer a0 to a4 input pin for z-phase input pins for the timer b0 to b2 output pins for the three-phase motor control timer input and output pins for the three-phase motor control timer input pins for data transmission control output pins for data reception control inputs and outputs the transfer clock inputs serial data inputs serial data outputs serial data outputs serial data output pin for transfer clock inputs and outputs serial data inputs and outputs the transfer clock inputs and outputs serial data inputs and outputs the transfer clock applies reference voltage to the a/d converter analog input pins for the a/d converter input pin for an external a/d trigger v cc, v ss av cc av ss ____________ reset cnv ss x in x out x cin x cout clk out ________ ________ int0 to int5 _______ nmi _____ _____ ki 0 to ki 3 ta0 out to ta4 out ta0 in to ta4 in zp tb0 in to tb2 in ___ ___ u, u, v, v, ___ w, w idu, idw, _____ idv, sd _________ _________ cts0 to cts2 _________ _________ rts0 to rts2 clk0 to clk3 rxd0 to rxd2 s in3 txd0 to txd2 s out3 clks1 sda2 scl2 sda mm scl mm v ref an 0 to an 7 an0 0 to an0 3 an2 4 an3 0 to an3 2 ___________ ad trg power supply analog power supply reset input cnv ss main clock input main clock output sub clock input sub clock output clock output ______ int interrupt input _______ nmi interrupt input key input interrupt timer a timer b three-phase motor control timer output serial i/o i 2 c bus mode multi-master i 2 c bus reference voltage input a/d converter i i i i i o i o o i i i i/o i i i o i/o i o i/o i i o o o i/o i/o i i i i : input o : output i/o : input and output classification symbol i/o type function table 1.11 pin description (64-pin and 80-pin packages)
1. overview page 17 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m input pins for the time measurement function output pins for the waveform generating function cmos i/o ports which have a direction register determines an individual pin is used as an input port or an output port. a pull-up resistor is select- able for every 4 input ports. inpc1 0 to inpc1 7 outc1 0 to outc1 7 p0 0 to p0 3 p1 5 to p1 7 p2 0 to p2 7 p3 0 to p3 3 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 3 p10 0 to p10 7 timer s i/o ports i o i/o i : input o : output i/o : input and output classification symbol i/o type function table 1.11 pin description (64-pin and 80-pin packages) (continued)
1. overview page 18 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m inputs and outputs the transfer clock inputs serial data outputs serial data analog input pins for the a/d converter cmos i/o ports which have a direction register determines an individual pin is used as an input port or an output port. a pull-up resistor is select- able for every 4 input ports. clk4 s in4 s out4 an0 4 to an0 7 an2 0 to an2 3 an2 5 to an2 7 p0 4 to p0 7 p1 0 to p1 4 p3 4 to p3 7 p9 5 to p9 7 serial i/o a/d converter i/o ports i/o i o i i/o classification symbol i/o type function table 1.12 pin description (80-pin packages only) (continued) i : input o : output i/o : input and output
2. central processing unit(cpu) page 19 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 2. central processing unit (cpu) figure 2.1 shows the cpu registers. the cpu has 13 registers. of these, r0, r1, r2, r3, a0, a1 and fb comprise a register bank. there are two register banks. figure 2.1. central processing unit register 2.1 data registers (r0, r1, r2 and r3) the r0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. r1 to r3 are the same as r0. the r0 register can be separated between high (r0h) and low (r0l) for use as two 8-bit data registers. r1h and r1l are the same as r0h and r0l. conversely, r2 and r0 can be combined for use as a 32-bit data register (r2r0). r3r1 is the same as r2r0. 2.2 address registers (a0 and a1) the register a0 consists of 16 bits, and is used for address register indirect addressing and address regis- ter relative addressing. they also are used for transfers and arithmetic/logic operations. a1 is the same as a0. in some instructions, registers a1 and a0 can be combined for use as a 32-bit address register (a1a0). data registers (note) address registers (note) frame base registers (note) program counter interrupt table register user stack pointer interrupt stack pointer static base register flag register note: these registers comprise a register bank. there are two register banks. r0h(r0's high bits) b15 b8 b7 b0 r3 intbh usp isp sb r0l(r0's low bits) r1h(r1's high bits) r1l(r1's low bits) r2 b31 r3 r2 a1 a0 fb b19 intbl b15 b0 pc b19 b0 b15 b0 flg b15 b0 b15 b0 b7 b8 b reserved area carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved area processor interrupt priority level the upper 4 bits of intb are intbh and the lower 16 bits of intb are intbl.
2. central processing unit(cpu) page 20 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 2.3 frame base register (fb) fb is configured with 16 bits, and is used for fb relative addressing. 2.4 interrupt table register (intb) intb is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 program counter (pc) pc is configured with 20 bits, indicating the address of an instruction to be executed. 2.6 user stack pointer (usp) and interrupt stack pointer (isp) stack pointer (sp) comes in two types: usp and isp, each configured with 16 bits. your desired type of stack pointer (usp or isp) can be selected by the u flag of flg. 2.7 static base register (sb) sb is configured with 16 bits, and is used for sb relative addressing. 2.8 flag register (flg) flg consists of 11 bits, indicating the cpu status. 2.8.1 carry flag (c flag) this flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. 2.8.2 debug flag (d flag) the d flag is used exclusively for debugging purpose. during normal use, it must be set to 0. 2.8.3 zero flag (z flag) this flag is set to 1 when an arithmetic operation resulted in 0; otherwise, it is 0. 2.8.4 sign flag (s flag) this flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, it is 0. 2.8.5 register bank select flag (b flag) register bank 0 is selected when this flag is 0; register bank 1 is selected when this flag is 1. 2.8.6 overflow flag (o flag) this flag is set to 1 when the operation resulted in an overflow; otherwise, it is 0. 2.8.7 interrupt enable flag (i flag) this flag enables a maskable interrupt. maskable interrupts are disabled when the i flag is 0, and are enabled when the i flag is 1. the i flag is cleared to 0 when the interrupt request is accepted. 2.8.8 stack pointer select flag (u flag) isp is selected when the u flag is 0; usp is selected when the u flag is 1. the u flag is cleared to 0 when a hardware interrupt request is accepted or an int instruction for software interrupt nos. 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. if a requested interrupt has priority greater than ipl, the interrupt is enabled. 2.8.10 reserved area when write to this bit, write 0. when read, its content is indeterminate.
3. memory page 21 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 3. memory figure 3.1 is a memory map of the m16c/28 group. m16c/28 group provides 1-mbyte address space from addresses 00000 16 to fffff 16 . the internal rom is allocated lower addresses beginning with address fffff 16 . for example, 64 kbytes internal rom is allocated addresses f0000 16 to fffff 16 . two 2-kbyte internal rom areas, block a and block b, are available in the flash memory version. the blocks are allocated addresses f000 16 to ffff 16 . the fixed interrupt vector tables are allocated addresses fffdc 16 to fffff 16 . it stores the starting ad- dress of each interrupt routine. see the section on interrupts for details. the internal ram is allocated higher addresses beginning with address 00400 16 . for example, 4-kbytes internal ram is allocated addresses 00400 16 to 013ff 16 . besides sotring data, it becomes stacks when the subroutines is called or an interrupt is acknowledged. sfr, consisting of control registers for peripheral functions such as i/o port, a/d converter, serial i/o, timers is allocated addresses 00000 16 to 003ff 16 . all blank spaces within sfr are reserved and cannot be accessed by users. the special page vector table is allocated to the addresses ffe00 16 to fffdb 16 . this vector is used by the jmps or jsrs instruction. for details, refer to the m16c/60 and m16c/20 series software manual . figure 3.1 memory map 0ffff 16 00000 16 xxxx x 16 fffff 16 00 400 16 yyyy y 16 internal rom (program space) sfr internal ram ffe00 16 fffdc 16 fffff 16 undefined instruction overflow brk instruction address match single step watchdog timer reset special page vector table dbc reserved space internal rom (data space) reserved space 0f000 16 xxxx x 16 yyyy y 16 internal ram internal rom memory size 013ff 16 f0000 16 4 kbytes 64 kbytes memory size e8000 16 96 kbytes (1) 023ff 16 8 kbytes nmi (2) notes: 1. the block a (2 kbytes) and block b (2 kbytes) are shown (only flash memory) 2. when using the masked rom version, write nothing to internal rom area.
4. special function registers (sfrs) page 22 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 4. special function register (sfrs) sfrs (special function registers) are the control registers of peripheral functions. table 4.1 to 4.7 list the sfr address map. address register symbol after reset 0000 16 0001 16 0002 16 0003 16 0004 16 processor mode register 0 pm0 00 16 0005 16 processor mode register 1 pm1 00001000 2 0006 16 system clock control register 0 cm0 01001000 2 0007 16 system clock control register 1 cm1 00100000 2 0008 16 0009 16 address match interrupt enable register aier xxxxxx00 2 000a 16 protect register prcr xx000000 2 000b 16 000c 16 oscillation stop detection register (2) cm2 0x000010 2 000d 16 000e 16 watchdog timer start register wdts xx 16 000f 16 watchdog timer control register wdc 00xxxxxx 2 0010 16 address match interrupt register 0 rmad0 00 16 0011 16 00 16 0012 16 x0 16 0013 16 0014 16 address match interrupt register 1 rmad1 00 16 0015 16 00 16 0016 16 x0 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 pll control register 0 plc0 0001x010 2 001d 16 001e 16 processor mode register 2 pm2 xxx00000 2 001f 16 0020 16 dma0 source pointer sar0 xx 16 0021 16 xx 16 0022 16 xx 16 0023 16 0024 16 dma0 destination pointer dar0 xx 16 0025 16 xx 16 0026 16 x/ 16 0027 16 0028 16 dma0 transfer counter tcr0 xx 16 0029 16 xx 16 002a 16 002b 16 002c 16 dma0 control register dm0con 00000x00 2 002d 16 002e 16 002f 16 0030 16 dma1 source pointer sar1 xx 16 0031 16 xx 16 0032 16 xx 16 0033 16 0034 16 dma1 destination pointer dar1 xx 16 0035 16 xx 16 0036 16 xx 16 0037 16 0038 16 dma1 transfer counter tcr1 xx 16 0039 16 xx 16 003a 16 003b 16 003c 16 dma1 control register dm1con 00000x00 2 003d 16 003e 16 003f 16 notes: 1. the blank areas are reserved and cannot be used by users. 2. the cm20, cm21, and cm27 bits do not change at oscillation stop detection reset. x : undefined table 4.1 sfr information(1) (1)
4. special function registers (sfrs) page 23 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m int3 interrupt control register int3ic xx00x000 2 ic/oc 0 interrupt control register icoc0ic xxxxx000 2 ic/oc 1 interrupt control register, i 2 c bus interface interrupt control register icoc1ic, iicic xxxxx000 2 ic/oc base timer interrupt control register, sclsda interrupt control register btic, s cldaic xxxxx000 2 si/o4 interrupt control register, int5 interrupt control register s4ic, int5ic xx00x000 2 si/o3 interrupt control register, int4 interrupt control register s3ic, int4ic xx00x000 2 uart2 bus collision detection interrupt control register bcnic xxxxx000 2 dma0 interrupt control register dm0ic xxxxx000 2 dma1 interrupt control register dm1ic xxxxx000 2 key input interrupt control register kupic xxxxx000 2 a/d conversion interrupt control register adic xxxxx000 2 uart2 transmit interrupt control register s2tic xxxxx000 2 uart2 receive interrupt control register s2ric xxxxx000 2 uart0 transmit interrupt control register s0tic xxxxx000 2 uart0 receive interrupt control register s0ric xxxxx000 2 uart1 transmit interrupt control register s1tic xxxxx000 2 uart1 receive interrupt control register s1ric xxxxx000 2 timer a0 interrupt control register ta0ic xxxxx000 2 timer a1 interrupt control register ta1ic xxxxx000 2 timer a2 interrupt control register ta2ic xxxxx000 2 timer a3 interrupt control register ta3ic xxxxx000 2 timer a4 interrupt control register ta4ic xxxxx000 2 timer b0 interrupt control register tb0ic xxxxx000 2 timer b1 interrupt control register tb1ic xxxxx000 2 timer b2 interrupt control register tb2ic xxxxx000 2 int0 interrupt control register int0ic xx00x000 2 int1 interrupt control register int1ic xx00x000 2 int2 interrupt control register int2ic xx00x000 2 0040 16 0041 16 0042 16 0043 16 0044 16 0045 16 0046 16 0047 16 0048 16 0049 16 004a 16 004b 16 004c 16 004d 16 004e 16 004f 16 0050 16 0051 16 0052 16 0053 16 0054 16 0055 16 0056 16 0057 16 0058 16 0059 16 005a 16 005b 16 005c 16 005d 16 005e 16 005f 16 0060 16 0061 16 0062 16 0063 16 0064 16 0065 16 0066 16 0067 16 0068 16 0069 16 006a 16 006b 16 006c 16 006d 16 006e 16 006f 16 0070 16 0071 16 0072 16 0073 16 0074 16 0075 16 0076 16 0077 16 0078 16 0079 16 007a 16 007b 16 007c 16 007d 16 007e 16 007f 16 address register symbol after reset note 1: the blank spaces are reserved. no access is allowed. x : undefined table 4.2 sfr information(2) (1)
4. special function registers (sfrs) page 24 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 01b0 16 01b1 16 01b2 16 01b3 16 01b4 16 01b5 16 01b6 16 01b7 16 01b8 16 01b9 16 0210 16 0211 16 0212 16 0213 16 0214 16 0215 16 0216 16 0217 16 0218 16 0219 16 0250 16 0251 16 0252 16 0253 16 0254 16 0255 16 0256 16 0257 16 0258 16 0259 16 025a 16 025b 16 025c 16 025d 16 025e 16 025f 16 02e0 16 02e1 16 02e2 16 02e3 16 02e4 16 02e5 16 02e6 16 02e7 16 02e8 16 02e9 16 02ea 16 02fe 16 02ff 16 note 1:the blank spaces are reserved. no access is allowed. note 2:this register is included in the flash memory version. x : undefined address register symbol after reset flash memory control register 4 (2) fmr4 01000000 2 flash memory control register 1 (2) fmr1 000xxx0x 2 flash memory control register 0 (2) fmr0 00000001 2 low-power consumption control 0 lpcc0 x0000001 2 three-phase protect control register tprc 00 16 on-chip oscillator control register rocr x0000101 2 pin assignment control register pacr 00 16 peripheral clock select register pclkr 00000011 2 low-power consumption control 1 lpcc1 00 16 i 2 c0 data shift register s00 xx 16 i 2 c0 address register s0d0 00 16 i 2 c0 control register 0 s1d0 00 16 i 2 c0 clock control register s20 00 16 i 2 c0 start/stop condition control register s2d0 00011010 2 i 2 c0 control register 1 s3d0 00110000 2 i 2 c0 control register 2 s4d0 00 16 i 2 c0 status register s10 0001000x 2 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ table 4.3 sfr information(3) (1)
4. special function registers (sfrs) page 25 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m address register symbol after reset 0300 16 time measurement, pulse generation register 0 g1tm0,g1po0 xx 16 0301 16 xx 16 0302 16 time measurement, pulse generation register 1 g1tm1,g1po1 xx 16 0303 16 xx 16 0304 16 time measurement, pulse generation register 2 g1tm2,g1po2 xx 16 0305 16 xx 16 0306 16 time measurement, pulse generation register 3 g1tm3,g1po3 xx 16 0307 16 xx 16 0308 16 time measurement, pulse generation register 4 g1tm4,g1po4 xx 16 0309 16 xx 16 030a 16 time measurement, pulse generation register 5 g1tm5,g1po5 xx 16 030b 16 xx 16 030c 16 time measurement, pulse generation register 6 g1tm6,g1po6 xx 16 030d 16 xx 16 030e 16 time measurement, pulse generation register 7 g1tm7,g1po7 xx 16 030f 16 xx 16 0310 16 pulse generation control register 0 g1pocr0 0x00xx00 2 0311 16 pulse generation control register 1 g1pocr1 0x00xx00 2 0312 16 pulse generation control register 2 g1pocr2 0x00xx00 2 0313 16 pulse generation control register 3 g1pocr3 0x00xx00 2 0314 16 pulse generation control register 4 g1pocr4 0x00xx00 2 0315 16 pulse generation control register 5 g1pocr5 0x00xx00 2 0316 16 pulse generation control register 6 g1pocr6 0x00xx00 2 0317 16 pulse generation control register 7 g1pocr7 0x00xx00 2 0318 16 time measurement control register 0 g1tmcr0 00 16 0319 16 time measurement control register 1 g1tmcr1 00 16 031a 16 time measurement control register 2 g1tmcr2 00 16 031b 16 time measurement control register 3 g1tmcr3 00 16 031c 16 time measurement control register 4 g1tmcr4 00 16 031d 16 time measurement control register 5 g1tmcr5 00 16 031e 16 time measurement control register 6 g1tmcr6 00 16 031f 16 time measurement control register 7 g1tmcr7 00 16 0320 16 base timer register g1bt xx 16 0321 16 xx 16 0322 16 base timer control register 0 g1bcr0 00 16 0323 16 base timer control register 1 g1bcr1 00 16 0324 16 time measurement prescale register 6 g1tpr6 00 16 0325 16 time measurement prescale register 7 g1tpr7 00 16 0326 16 function enable register g1fe 00 16 0327 16 function select register g1fs 00 16 0328 16 base timer reset register g1btrr xx 16 0329 16 xx 16 032a 16 count source division register g1dv 00 16 032b 16 032c 16 032d 16 032e 16 032f 16 0330 16 interrupt request register g1ir xx 16 0331 16 interrupt enable register 0 g1ie0 00 16 0332 16 interrupt enable register 1 g1ie1 00 16 0333 16 0334 16 0335 16 0336 16 0337 16 0338 16 0339 16 033a 16 033b 16 033c 16 033d 16 033e 16 nmi digital debounce register nddr ff 16 033f 16 port p1 7 digital debounce register p17ddr ff 16 note: 1. the blank areas are reserved and cannot be used by users. x : undefined table 4.4 sfr information(4) (1)
4. special function registers (sfrs) page 26 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m address register symbol after reset 0340 16 0341 16 0342 16 timer a1-1 register ta11 xx 16 0343 16 xx 16 0344 16 timer a2-1 register ta21 xx 16 0345 16 xx 16 0346 16 timer a4-1 register ta41 xx 16 0347 16 xx 16 0348 16 three phase pwm control register 0 invc0 00 16 0349 16 three phase pwm control register 1 invc1 00 16 034a 16 three phase output buffer register 0 idb0 00111111 2 034b 16 three phase output buffer register 1 idb1 00111111 2 034c 16 dead time timer dtt xx 16 034d 16 timer b2 interrupt occurrence frequency set counter ictb2 xx 16 034e 16 position - data - retain function control register pdrf xxxx0000 2 034f 16 0350 16 0351 16 0352 16 0353 16 0354 16 0355 16 0356 16 0357 16 0358 16 port function control register pfcr 00111111 2 0359 16 035a 16 035b 16 035c 16 035d 16 035e 16 interrupt cause select register 2 ifsr2a 00xxxxx0 2 (2) 035f 16 interrupt cause select register ifsr 00 16 0360 16 si/o3 transmit/receive register s3trr xx 16 0361 16 0362 16 si/o3 control register s3c 01000000 2 0363 16 si/o3 bit rate register s3brg xx 16 0364 16 si/o4 transmit/receive register s4trr xx 16 0365 16 0366 16 si/o4 control register s4c 01000000 2 0367 16 si/o4 bit rate register s4brg xx 16 0368 16 0369 16 036a 16 036b 16 036c 16 036d 16 036e 16 036f 16 0370 16 0371 16 0372 16 0373 16 0374 16 uart2 special mode register 4 u2smr4 00 16 0375 16 uart2 special mode register 3 u2smr3 000x0x0x 2 0376 16 uart2 special mode register 2 u2smr2 x0000000 2 0377 16 uart2 special mode register u2smr x0000000 2 0378 16 uart2 transmit/receive mode register u2mr 00 16 0379 16 uart2 bit rate register u2brg xx 16 037a 16 uart2 transmit buffer register u2tb xx 16 037b 16 xx 16 037c 16 uart2 transmit/receive control register 0 u2c0 00001000 2 037d 16 uart2 transmit/receive control register 1 u2c1 00000010 2 037e 16 uart2 receive buffer register u2rb xx 16 037f 16 xx 16 notes: 1. the blank areas are reserved and cannot be used by users. 2. write "1" to bit 0 after reset. x : undefined table 4.5 sfr information(5) (1)
4. special function registers (sfrs) page 27 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m address register symbol after reset 0380 16 count start flag tabsr 00 16 0381 16 clock prescaler reset flag cpsrf 0xxxxxxx 2 0382 16 one-shot start flag onsf 00 16 0383 16 trigger select register trgsr 00 16 0384 16 up-dowm flag udf 00 16 0385 16 0386 16 timer a0 register ta0 xx 16 0387 16 xx 16 0388 16 timer a1 register ta1 xx 16 0389 16 xx 16 038a 16 timer a2 register ta2 xx 16 038b 16 xx 16 038c 16 timer a3 register ta3 xx 16 038d 16 xx 16 038e 16 timer a4 register ta4 xx 16 038f 16 xx 16 0390 16 timer b0 register tb0 xx 16 0391 16 xx 16 0392 16 timer b1 register tb1 xx 16 0393 16 xx 16 0394 16 timer b2 register tb2 xx 16 0395 16 xx 16 0396 16 timer a0 mode register ta0mr 00 16 0397 16 timer a1 mode register ta1mr 00 16 0398 16 timer a2 mode register ta2mr 00 16 0399 16 timer a3 mode register ta3mr 00 16 039a 16 timer a4 mode register ta4mr 00 16 039b 16 timer b0 mode register tb0mr 00xx0000 2 039c 16 timer b1 mode register tb1mr 00xx0000 2 039d 16 timer b2 mode register tb2mr 00xx0000 2 039e 16 timer b2 special mode register tb2sc x0000000 2 039f 16 03a0 16 uart0 transmit/receive mode register u0mr 00 16 03a1 16 uart0 bit rate register u0brg xx 16 03a2 16 uart0 transmit buffer register u0tb xx 16 03a3 16 xx 16 03a4 16 uart0 transmit/receive control register 0 u0c0 00001000 2 03a5 16 uart0 transmit/receive control register 1 u0c1 00000010 2 03a6 16 uart0 receive buffer register u0rb xx 16 03a7 16 xx 16 03a8 16 uart1 transmit/receive mode register u1mr 00 16 03a9 16 uart1 bit rate register u1brg xx 16 03aa 16 uart1 transmit buffer register u1tb xx 16 03ab 16 xx 16 03ac 16 uart1 transmit/receive control register 0 u1c0 00001000 2 03ad 16 uart1 transmit/receive control register 1 u1c1 00000010 2 03ae 16 uart1 receive buffer register u1rb xx 16 03af 16 xx 16 03b0 16 uart transmit/receive control register 2 ucon x0000000 2 03b1 16 03b2 16 03b3 16 03b4 16 sfr snoop address register crcsar xx 16 03b5 16 00xxxxxx 2 03b6 16 crc mode register crcmr 0xxxxxx0 2 03b7 16 03b8 16 dma0 request cause select register dm0sl 00 16 03b9 16 03ba 16 dma1 request cause select register dm1sl 00 16 03bb 16 03bc 16 crc data register crcd xx 16 03bd 16 xx 16 03be 16 crc input register crcin xx 16 03bf 16 note: 1. the blank areas are reserved and cannot be used by users. x : undefined table 4.6 sfr information(6) (1)
4. special function registers (sfrs) page 28 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m address register symbol after reset 03c0 16 a/d register 0 ad0 xx 16 03c1 16 xx 16 03c2 16 a/d register 1 ad1 xx 16 03c3 16 xx 16 03c4 16 a/d register 2 ad2 xx 16 03c5 16 xx 16 03c6 16 a/d register 3 ad3 xx 16 03c7 16 xx 16 03c8 16 a/d register 4 ad4 xx 16 03c9 16 xx 16 03ca 16 a/d register 5 ad5 xx 16 03cb 16 xx 16 03cc 16 a/d register 6 ad6 xx 16 03cd 16 xx 16 03ce 16 a/d register 7 ad7 xx 16 03cf 16 xx 16 03d0 16 03d1 16 03d2 16 a/d trigger control register adtrgcon 00 16 03d3 16 a/d status register 0 adstat0 00000x00 2 03d4 16 a/d control register 2 adcon2 00 16 03d5 16 03d6 16 a/d control register 0 adcon0 00000xxx 2 03d7 16 a/d control register 1 adcon1 00 16 03d8 16 03d9 16 03da 16 03db 16 03dc 16 03dd 16 03de 16 03df 16 03e0 16 port p0 register p0 xx 16 03e1 16 port p1 register p1 xx 16 03e2 16 port p0 direction register pd0 00 16 03e3 16 port p1 direction register pd1 00 16 03e4 16 port p2 register p2 xx 16 03e5 16 port p3 register p3 xx 16 03e6 16 port p2 direction register pd2 00 16 03e7 16 port p3 direction register pd3 00 16 03e8 16 03e9 16 03ea 16 03eb 16 03ec 16 port p6 register p6 xx 16 03ed 16 port p7 register p7 xx 16 03ee 16 port p6 direction register pd6 00 16 03ef 16 port p7 direction register pd7 00 16 03f0 16 port p8 register p8 xx 16 03f1 16 port p9 register p9 xx 16 03f2 16 port p8 direction register pd8 00 16 03f3 16 port p9 direction register pd9 000x0000 2 03f4 16 port p10 register p10 xx 16 03f5 16 03f6 16 port p10 direction register pd10 00 16 03f7 16 03f8 16 03f9 16 03fa 16 03fb 16 03fc 16 pull-up control register 0 pur0 00 16 03fd 16 pull-up control register 1 pur1 00 16 03fe 16 pull-up control register 2 pur2 00 16 03ff 16 port control register pcr 00 16 note: 1. the blank areas are reserved and cannot be used by users. x : undefined table 4.7 sfr information(7) (1)
5. reset page 29 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 5. reset hardware reset 1, software reset, watchdog timer reset, and oscillation stop detection reset are imple- mented to reset the mcu. 5.1 hardware reset 5.1.1 hardware reset 1 ____________ pins, cpu, and sfrs are reset by using the reset pin. when a low-level ( ? l ? ) signal is applied to the ____________ reset pin while the supply voltage meets the recommended operating condition, pins, cpu, and sfrs ____________ are reset (see table 5.1 pin status when reset pin level is ? l ? ). the oscillation circuit is also reset and the on-chip oscillator starts oscillating as the cpu clock. cpu and sfrs re reset when the signal applied ____________ to the reset pin changes from ? l ? to high ( ? h ? ). the mcu executes a program beginning with the address indicated by the reset vector. the internal ram is not reset. when an ? l ? signal is applied to the ____________ reset pin while writing data to the internal ram, the content of internal ram is undefined. figure 5.1 shows an example of the reset circuit. figure 5.2 shows a reset sequence. table 5.1 shows ____________ status of the other pins while the reset pin is held ? l ? . figure 5.3 shows cpu register states after reset. refer to 4. special function register (sfr) about sfr states after reset. 1. reset on a stable supply voltage ____________ (1) apply an ? l ? signal to the reset pin (2) wait td(roc) or more ____________ (3) apply an ? h ? signal to the reset pin 2. power-on reset ____________ (1) apply an ? l ? signal to the reset pin (2) increase the supply voltage until it meets the the recommended performance condition (3) wait for td(p-r) or more to allow the internal power supply to stabilize (4) wait td(roc) or more ____________ (5) apply an ? h ? signal to the reset pin
5. reset page 30 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 5.2 software reset the mcu resets its pins, cpu, and sfrs when the pm03 bit in the pm0 register is set to 1 (reset) and the mcu executes a program in an address indicated by the reset vector. then the on-chip oscillator is se- lected as the cpu clock. the software reset does not reset some portions of the sfrs. refer to 4. special function registers (sfrs) for details. 5.3 watchdog timer reset the mcu resets its pins, cpu, and sfrs when the pm12 bit in the pm1 register is set to 1 (watchdog timer reset) and the watchdog timer underflows. the mcu executes a program in an address indicated by the reset vector. then the on-chip oscillator is selected as the cpu clock. the watchdog timer reset does not reset some portions of the sfrs. refer to 4. special function regis- ters (sfrs) for details. 5.4 oscillation stop detection reset the mcu resets its pins, cpu, and sfrs and stops if the main clock stop is detected when the cm20 bit in the cm2 register is set to 1 (oscillation stop, re-oscillation detection function enabled) and the cm27 bit in the cm2 register is 0 (reset at oscillation stop detection). refer to the section 7.8 oscillation stop, re- oscillation detection function for details. the oscillation stop detection reset does not reset some portions of the sfrs. refer to 4. special func- tion registers (sfrs) . figure 5.1 example reset circuit reset v cc r e s e t v c c 0 v 0 v more than td(roc) + td(p-r ) re c o m m e n d e d o p e r a t i n g v o l t a g e 0.2 vcc or below 0.2 vcc or below
5. reset page 31 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m ____________ table 5.1 pin status when reset pin level is ? figure 5.3 cpu register status after reset figure 5.2 reset sequence td(p-r) more than td(roc) cpu clock address roc reset content of reset vector cpu clock: 28 cycles ffffe 16 ffffc 16 v cc max. 2 ms status pin name p0 to p3, p6 to p10 input port (high impedance) b15 b0 data register(r0) address register(a0) frame base register(fb) program counter(pc) interrupt table register(intb) user stack pointer(usp) interrupt stack pointer(isp) static base register(sb) flag register(flg) 0000 16 0000 16 0000 16 aa aa aa aa a a aa aa aaaaaa aaaaaa aa aa aa aa a a aa aa aa aa c d z s b o i u ipl 0000 16 0000 16 0000 16 0000 16 0000 16 b19 b0 content of addresses ffffe 16 to ffffc 16 b15 b0 b15 b0 b15 b0 b7 b8 00000 16 data register(r1) data register(r2) data register(r3) address register(a1) 0000 16 0000 16 0000 16
6. processor mode page 32 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 6. processor mode the mcu supports single-chip mode only. figures 6.1 and 6.2 show the associated registers. figure 6.1 pm0 register, pm1 register processor mode register 0 (1) symbol address after reset pm0 0004 16 00 16 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 the mcu is reset when this bit is set to 1. when read, its content is 0. software reset bit pm03 rw rw rw note: 1. set the pm0 register after the prc1 bit in the prcr register is set to 1 (write enable). set to 0 (b2-b0) reserved bit set to 0 (b7-b4) reserved bit 000 0 00 0 processor mode register 1 (1) symbol address after reset pm1 0005 16 00001000 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 flash data block access bit (2) 0: disabled 1: enabled (3) pm10 rw pm17 wait bit (5) 0 : no wait state 1 : wait state (1 wait) 0 : watchdog timer interrupt 1 : watchdog timer reset (4) watchdog timer function select bit pm12 rw rw rw rw rw notes: 1. rewrite the pm1 register after the prc1 bit in the prcr register is set to 1 (write enable). 2. to access the two 2k-byte data spaces in data block a and data block b, set the pm10 bit to 1. the pm10 bit is not available in mask version. 3. when the fmr01 bit in the fmr0 register is set to 1 (enables cpu rewrite mode), the pm10 bit is automatically set to 1. 4. set the pm12 bit to 1 by program. (writing 0 by program has no effect) 5. when the pm17 bit is set to 1 (wait state), one wait is inserted when accessing the internal ram or the internal rom. set to 0 (b1) reserved bit set to 1 reserved bit set to 0 (b6-b4) reserved bit (b3) 0 1 0 00
6. processor mode page 33 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 6.2 pm2 register function bit symbol bit name processeor mode register 2 (1) symbol address after reset pm2 001e 16 xxx00000 2 rw b7 b6 b5 b4 b3 b2 b1 b0 pm20 0 pm21 system clock protective bit (3,4) rw rw rw (b7-b5) pm22 pm24 (b3) reserved bit set to ? 0 ? rw rw notes: 1. write to this register after setting the prc1 bit in the prcr register to ? 1 ? (write enable). 2. the pm20 bit become effective when plc07 bit in the plc0 register is set to "1" (pll on). change the pm20 bit when the plc07 bit is set to "0" (pll off). set the pm20 bit to "0" (2 waits) when pll clock > 16 mhz. 3. once this bit is set to ? 1 ? , it cannot be set to ? 0 ? by program. 4. writing to the following bits has no effect when the pm21 bit is set to ? 1 ? : cm02 bit in the cm0 register cm05 bit in the cm0 register (main clock is not halted) cm07 bit in the cm0 register (cpu clock source does not change) cm10 bit in the cm1 register (stop mode is not entered) cm11 bit in the cm1 register (cpu clock source does not change) cm20 bit in the cm2 register (oscillation stop, re-oscillation detection function settings do not change) all bits in the plc0 register (pll frequency synthesizer setting do not change) when the pm21 bit is set to "1", do not execute the wait instruction. 5. setting the pm22 bit to ? 1 ? results in the following conditions: - the on-chip oscillator continues oscillating even if the cm21 bit in the cm2 register is set to "0" (main clock or pll clock) (system clock of count source selected by the cm21 bit is valid) - the on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer count source. - the cm10 bit in the cm1 register is disabled against write. (writing a ? 1 ? has no effect, nor is stop mode entered) - the watchdog timer does not stop in wait mode. 6. for nmi function, the pm24 bit must be set to ? 1 ? (nmi function). once this bit is set to ? 1 ? , it cannot be cleared to ? 0 ? by program. 7. sd input is valid regardless of the pm24 setting. specifying wait when accessing sfr during pll operation (2) 0: 2 waits 1: 1 wait wdt count source protective bit (3,5) p85/nmi configuration bit (6,7) 0: p8 5 function (nmi disable) 1: nmi function 0: cpu clock is used for the watchdog timer count source 1: on-chip oscillator clock is used for the watchdog timer count source 0: clock is protected by prcr register 1: clock modification disabled nothing is assigned. when write, set to ? 0 ? . when read,its content is indeterminate
6. processor mode page 34 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m the internal bus consists of cpu bus, memory bus, and peripheral bus. bus interface unit (biu) is used to interfere with cpu, rom/ram, and perpheral functions by controling cpu bus, memory bus, and periph- eral bus. figure 6.3 shows the block diagram of the internal bus. cpu rom biu i/o cp u address bus memory data bus periphral data bus dmac memory address bus peripheral address bus timer wdt serial i/o adc peripheral function cpu clock ram cpu data bus peripheral function . . . . clock generation circuit s f r figure 6.3 bus block diagram the number of bus cycle varies by the internal bus. table 6.1 lists the accessible area and bus cycle. table 6.1 accessible area and bus cycle accessible area bus cycle sfr pm20 bit = 0 (2 waits) 3 cpu clock cycles pm20 bit = 1 (1 wait) 2 cpu clock cycles rom/ram pm17 bit = 0 (no wait) 1 cpu clock cycle pm17 bit = 1 (1 wait) 2 cpu clock cycles
7. clock generation circuits page 35 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m - cpu clock source - peripheral function clock source use of clock main clock oscillation circui t sub clock oscillation circuit item - cpu clock source - timer a, b's clock source clock frequency 0 to 20 mhz 32.768 khz - ceramic oscillator - crystal oscillator usable oscillator - crystal oscillator x in , x out pins to connect oscillator x cin , x cout available oscillation stop, restart function oscillating oscillator status after reset stopped externally derived clock can be input other pll frequency synthesize r 10 to 20 mhz stopped variable on-chip oscillator - cpu clock source - peripheral function clock source - cpu and peripheral function clock sources when the main clock stops oscillating selectable source frequency: f 1(roc) , f 2(roc) , f 3(roc) selectable divider: by 2, by 4, by 8 oscillating - cpu clock source - peripheral function clock sourc e (cpu clock source) available available available 7. clock generation circuits the mcu has four clock generation circuits as follows: (1) main clock oscillation circuit (2) sub clock oscillation circuit (3) on-chip oscillator (4) pll frequency synthesizer table 7.1 lists the specifications of the clock generation circuit. figure 7.1 shows the clock generation circuits. figures 7.2 to 7.7 show the clock-associated registers. table 7.1 clock generation circuit specifications
7. clock generation circuits page 36 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 7.1 clock generation circuits phase comparator charge pump voltage control oscillator (vco) pll clock main clock 1/2 programmable counter internal low- pass filter pll frequency synthesizer pulse generation circuit for clock edge detection and charge, discharge control charge, discharge circuit reset generating circuit oscillation stop, re-oscillation detection interrupt generating circuit main clock oscillation stop detection reset cm27=0 cm21 switch signal oscillation stop, re-oscillation detection signal oscillation stop, re-oscillation detection circuit cm27=1 1/2 1/2 1/2 rocr3, rocr2=11 2 on-chip oscillator clock 1/8 1/4 1/2 rocr3, rocr2=10 2 rocr3, rocr2=01 2 rocr1, rocr0=00 2 f 1(roc) f 2(roc) f 3(roc) rocr1,rocr0=01 2 rocr1, rocr0=11 2 variable on-chip oscillator on-chip oscillator f c3 2 cm00, cm01, cm02, cm04, cm05, cm06, cm07: bits in the cm0 register cm10, cm11, cm16, cm17: bits in the cm1 register pclk0, pclk1, pclk5: bits in the pclkr register cm21, cm27: bits in the cm2 register 1/32 main clock oscillation circuit f c cm02 cm04 cm10=1(stop mode) q s r wait instruction cm05 q s r nmi interrupt request level judgment output reset software reset f c cpu clock cm07 = 0 cm07 = 1 a d 1/2 1/2 1/2 1/2 cm06=0 cm17, cm16=00 2 cm06=0 cm17, cm16=01 2 cm06=0 cm17, cm16=10 2 cm06=1 cm06=0 cm17, cm16=11 2 d a details of divider sub clock oscillation circuit x cin x cout x out x in f 8 f 32 c b b 1/2 c f 32sio f 8s i o f ad f 1 e e 1/2 1/4 1/8 1/16 1/32 p c lk 0 = 1 pll frequency s y nt h es i z e r 0 1 c m21= 1 c m11 c m21= 0 pl l cloc k sub clock p c lk 0 = 0 f 2 f 1 s i o p c lk1=1 p c lk1= 0 f 2 s i o main clock oscillation stop, re- oscillation detection circuit d4int clock bclk clk out i/o ports pclk5=0,cm01-cm00=00 2 pclk5=0,cm01-cm00=01 2 pclk5=1,cm01-cm00=00 2 pclk5=0, cm01-cm00=10 2 pclk5=0, cm01-cm00=11 2 cm21 on-chip oscillator clock
7. clock generation circuits page 37 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 7.2 cm0 register system clock control register 0 (1) bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 cm07 cm05 cm04 cm03 cm02 cm06 wait mode peripheral function clock stop bit (10) 0: do not stop peripheral function clock in wait mode 1: stop peripheral function clock in wait mode (8) x cin -x cout drive capacity select bit (2) 0: low 1: high main clock stop bit (3, 10, 12, 13) 0: on (4) 1: off (5) main clock division select bit 0 (7, 13, 14) 0: cm16 and cm17 valid 1: division by 8 mode system clock select bit (6, 10, 11, 12) 0: main clock, pll clock, or on-chip oscillator clock 1: sub-clock rw port x c select bit (2) rw rw rw rw rw rw rw clock output function select bit see table 7.3 cm00 cm01 rw notes: 1. write to this register after setting the prc0 bit in the prcr register to 1 (write enable). 2. the cm03 bit is set to 1 (high) when the cm04 bit is set to 0 (i/o port) or the mcu goes to a stop mode. 3. this bit is provided to stop the main clock when the low power dissipation mode or on-chip oscillator low power dissipa tion mode is selected. this bit cannot be used for detection as to whether the main clock stopped or not. to stop the main cloc k, the following setting is required: (1) set the cm07 bit to 1 (sub-clock select) or the cm21 bit in the cm2 register to 1 (on-chip oscillator select) with the sub- clock stably oscillating. (2) set the cm20 bit in the cm2 register to 0 (oscillation stop, re-oscillation detection function disabled). (3) set the cm05 bit to 1 (stop). 4. during external clock input, set the cm05 bit to 0 (on). 5. when cm05 bit is set to 1, the x out pin goes "h". futhermore, because the internal feedback resistor remains connected, the x in pin is pulled "h" to the same level as x out via the feedback resistor. 6. after setting the cm04 bit to 1 (x cin -x cout oscillator function), wait until the sub-clock oscillates stably before switching the cm07 bit from 0 to 1 (sub-clock). 7. when entering stop mode from high or middle speed mode, on-chip oscillator mode or on-chip oscillator low power mode, t he cm06 bit is set to 1 (divided-by-8 mode). 8. the f c32 clock does not stop. during low speed or low power dissipation mode, do not set this bit to 1(peripheral clock turned off in wait mode). 9. to use a sub-clock, set this bit to 1. also, make sure ports p8 6 and p8 7 are directed for input, with no pull-ups. 10. when the pm21 bit in the pm2 register is set to 1 (clock modification disable), writing to bits cm02, cm05, and cm07 has no effect. 11. if the pm21 bit needs to be set to 1, set the cm07 bit to 0 (main clock) before setting it. 12. to use the main clock a the clock source for the cpu clock, follow the procedure below. (1) set the cm05 bit to 0 (oscillate). (2) wait the main clock oscillation stabilized. (3) set all bits cm11, cm21, and cm07 to 0. 13. when the cm21 bit is set to 0 (on-chip oscillaor turned off) and the cm05 bit is set to 1 (main clock turned off), the c m06 bit is fixed to 1 (divide-by-8 mode) and the cm15 bit is fixed to 1 (drive capability high). 14. to return from on-chip oscillator mode to high-speed or middle-speed mode set both bits cm06 and cm15 to 1. symbol address after reset cm0 01001000 2 0006 16 0: i/o port p8 6 , p8 7 1: x cin -x cout generation function (9)
7. clock generation circuits page 38 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 7.3 cm1 register figure 7.4 rocr register b7 b6 b5 b4 b3 b2 b1 b0 rw rocr0 rocr1 on-chip oscillator control register (1) bit name function bit symbol frequency select bits rw rw reserved bit 00 0 0 0: f 1 (roc) 0 1: f 2 (roc) 1 0: do not set to this value 1 1: f 3 (roc) b1 b0 rocr2 rocr3 divider select bits rw rw 0 0: do not set to this value 0 1: divide by 2 1 0: divide by 4 1 1: divide by 8 b3 b2 note: 1. write to this register after setting the prc0 bit in the prcr register to 1 (write enable). (b6-b4) set to 0 (b7) rw nothing is assigned. when write, set to 0. when read, the content is undefined symbol address after reset rocr 025c 16 x0000101 2 system clock control register 1 (1) symbol address after reset cm1 0007 16 00100000 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 cm10 all clock stop control bit (4, 6 ) 0 : clock on 1 : all clocks off (stop mode) cm15 x in -x out drive capacity select bit (2) 0 : low 1 : hig h rw cm16 cm17 reserved bit set to 0 main clock division select bits (3) 0 0 : no division mode 0 1 : division by 2 mode 1 0 : division by 4 mode 1 1 : division by 16 mode b7 b6 0 00 cm11 system clock select bit 1 (6, 7) 0 : main clock 1 : pll clock (5) rw rw rw rw rw rw (b4-b2) notes: 1. write to this register after setting the prc0 bit in the prcr register to 1 (write enable). 2. when entering stop mode from high or middle speed mode, or when the cm05 bit is set to 1 (main clock turned off) in low speed mode, the cm15 bit is set to 1 (drive capability high). 3. effective when the cm06 bit is 0 (bits cm16 and cm17 enable). 4. if the cm10 bit is 1 (stop mode), x out goes ? h ? and the internal feedback resistor is disconnected. the x cin and x cout pins are placed in the high-impedance state. when the cm11 bit is set to 1 (pll clock), or the cm20 bit in the cm2 register is set to 1 (oscillation stop, re-oscillation detection function enabled), do not set the cm10 bit to 1. 5. after setting the plc07 bit in the plc0 register to 1 (pll operation), wait until tsu (pll) elapses before setting the cm11 bit to 1 (pll clock). 6. when the pm21 bit in the pm2 register is set to 1 (clock modification disable), writing to bits cm10, cm11 has no effect. when the pm22 bit in the pm2 register is set to 1 (watchdog timer count source is on-chip oscillator clock), writing to the cm10 bit has no effect. 7. effective when cm07 bit is 0 and cm21 bit is 0 .
7. clock generation circuits page 39 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 7.5 cm2 register b7 b6 b5 b4 b3 b2 b1 b0 rw cm20 cm21 oscillation stop detection register (1) symbol address after reset cm2 000c 16 0x000010 2 (11) bit name function bit symbol system clock select bit 2 (2, 3, 6, 8, 11, 12 ) 0: oscillation stop, re-oscillation detection function disabled 1: oscillation stop, re-oscillation detection function enabled 0: main clock or pll clock 1: on-chip oscillator clock (on-chip oscillator oscillating) oscillation stop, re- oscillation detection bit (7, 9, 10, 11) cm22 cm23 oscillation stop, re- oscillation detection flag 0: main clock stop,or re-oscillation not detected 1: main clock stop,or re-oscillation detected 0: main clock oscillating 1: main clock not oscillating x in monitor flag (4) cm27 0: oscillation stop detection reset 1: oscillation stop, re-oscillation detection interrupt nothing is assigned. when write, set to 0. when read, its content is undefined operation select bit (when an oscillation stop, re-oscillation is detected) (11) rw rw rw rw ro (b6) (5) reserved bit (b5-b4) set to 0 rw 00 notes: 1. write to this register after setting the prc0 bit in the prcr register to 1 (write enable). 2. when the cm20 bit is 1 (oscillation stop, re-oscillation detection function enabled), the cm27 bit is set to 1 (oscillation stop, re-oscillation detection interrupt), and the cpu clock source is the main clock, the cm21 bit is automatically set to 1 (on-chip oscillator clock) if the main clock stop is detected. 3. if the cm20 bit is set to 1 and the cm23 bit is set to 1 (main clock not oscillating), do not set the cm21 bit to 0. 4. this flag is set to 1 when the main clock is detected to have stopped or when the main clock is detected to have restarted oscillating. when this flag changes state from 0 to 1, an oscillation stop, reoscillation restart detection interrupt is generated. use this flag in an interrupt routine to discriminate the causes of interrupts between the oscillation stop, reoscillation detection interrupts and the watchdog timer interrupt. the flag is cleared to 0 by writing 0 by program. (writing 1 has no effect. nor is it cleared to 0 by an oscillation stop or an oscillation restart detection interrupt request acknowledged.) if when the cm22 bit is set to 1 an oscillation stoppage or an oscillation restart is detected, no oscillation stop, reoscillation restart detection interrupts are generated. 5. read the cm23 bit in an oscillation stop, re-oscillation detection interrupt handling routine to determine the main clock status. 6. effective when the cm07 bit in the cm0 register is set to 0. 7. when the pm21 bit in the pm2 register is 1 (clock modification disabled), writing to the cm20 bit has no effect. 8. when the cm20 bit is set to 1 (oscillation stop, re-oscillation detection function enabled), the cm27 bit is set 1 (oscillation stop, re-oscillation detection interrupt), and the cm11 bit is 1 (the cpu clock source is pll clock), the cm21 bit remains unchanged even when main clock stop is detected. if the cm22 bit is set to 0 under these conditions, oscillation stop, re-oscillation detection interrupt occur at main clock stop detection; it is, therefore, necessary to set the cm21 bit to 1 (on-chip oscillator clock) inside the interrupt routine. 9. set the cm20 bit to 0 (disable) before entering stop mode. after exiting stop mode, set the cm20 bit back to 1 (enable). 10. set the cm20 bit to 0 (disable) before setting the cm05 bit in the cm0 register. 11. bits cm20, cm21 and cm27 do not change at oscillation stop detection reset. 12. when the cm21 bit is set to 0 (on-chip oscillator turned off) and the cm05 bit is set to 1 (main clock turned off), the cm06 bit is fixed to 1 (divide-by-8 mode) and the cm15 bit is fixed to 1 (drive capability high).
7. clock generation circuits page 40 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 7.6 pclkr register and pm2 register function bit symbol bit name processeor mode register 2 (1) symbol address after reset pm2 001e 16 xxx00000 2 rw b7 b6 b5 b4 b3 b2 b1 b0 pm20 0 pm21 system clock protective bit (3,4) rw rw rw (b7-b5) pm22 pm24 (b3) reserved bit set to ? 0 ? rw rw notes: 1. write to this register after setting the prc1 bit in the prcr register to ? 1 ? (write enable). 2. the pm20 bit become effective when plc07 bit in the plc0 register is set to "1" (pll on). change the pm20 bit when the plc07 bit is set to "0" (pll off). set the pm20 bit to "0" (2 waits) when pll clock > 16 mhz. 3. once this bit is set to ? 1 ? , it cannot be set to ? 0 ? by program. 4. writing to the following bits has no effect when the pm21 bit is set to ? 1 ? : cm02 bit in the cm0 register cm05 bit in the cm0 register (main clock is not halted) cm07 bit in the cm0 register (cpu clock source does not change) cm10 bit in the cm1 register (stop mode is not entered) cm11 bit in the cm1 register (cpu clock source does not change) cm20 bit in the cm2 register (oscillation stop, re-oscillation detection function settings do not change) all bits in the plc0 register (pll frequency synthesizer setting do not change) when the pm21 bit is set to "1", do not execute the wait instruction. 5. setting the pm22 bit to ? 1 ? results in the following conditions: - the on-chip oscillator continues oscillating even if the cm21 bit in the cm2 register is set to "0" (main clock or pll clock) (system clock of count source selected by the cm21 bit is valid) - the on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer count source. - the cm10 bit in the cm1 register is disabled against write. (writing a ? 1 ? has no effect, nor is stop mode entered) - the watchdog timer does not stop in wait mode. 6. for nmi function, the pm24 bit must be set to ? 1 ? (nmi function). once this bit is set to ? 1 ? , it cannot be cleared to ? 0 ? by program. 7. sd input is valid regardless of the pm24 setting. specifying wait when accessing sfr during pll operation (2) 0: 2 waits 1: 1 wait wdt count source protective bit (3,5) p85/nmi configuration bit (6,7) 0: p8 5 function (nmi disable) 1: nmi function 0: cpu clock is used for the watchdog timer count source 1: on-chip oscillator clock is used for the watchdog timer count source 0: clock is protected by prcr register 1: clock modification disabled nothing is assigned. when write, set to ? 0 ? . when read,its content is indeterminate function bit symbol bit name peripheral clock select register (1) symbol address after reset pclkr 025e 16 00000011 2 rw b7 b6 b5 b4 b3 b2 b1 b0 pclk0 0: f 2 1: f 1 000 reserved bit set to 0 note: 1. write to this register after setting the prc0 bit in prcr register to 1 (write enable). 00 pclk1 0: f 2 sio 1: f 1 sio rw rw rw (b4-b2) reserved bit set to 0 rw (b7-b6) rw pclk5 refer to table 7.3 clock output function expansion select bit timers a, b clock select bit (clock source for the timers a, b, the timer s, the dead timer, si/o3, si/o4 and multi-master i 2 c bus) si/o clock select bit (clock source for uart0 to uart2)
7. clock generation circuits page 41 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 7.7 plc0 register plc00 plc01 plc02 plc07 (3) (4) function notes: 1. write to this register after setting the prc0 bit in the prcr register to 1 (write enable). 2. when the pm21 bit in the pm2 register is 1 (clock modification disable), writing to this register has no effect. 3. these three bits can only be modified when the plc07 bit is set to 0 (pll turned off). the value once written to this bit cannot be modified. 4. before setting this bit to 1 , set the cm07 bit to 0 (main clock), set bits cm17 to cm16 bits to 00 2 (main clock undivided mode), and set the cm06 bit to 0 (cm16 and cm17 bits enable). pll control register 0 (1,2) pll multiplying factor select bit nothing is assigned. when write, set to 0. when read, its content is undefined operation enable bit 0 0 0: 0 0 1: multiply by 2 0 1 0: multiply by 4 0 1 1: 1 0 0: 1 0 1: 1 1 0: 1 1 1: 0: pll off 1: pll on bit name bit symbol symbol address after reset plc0 001c 16 0001x010 2 rw b1b0 b2 reserved bit set to 0 do not set rw rw rw rw rw reserved bit set to 1 rw do not set (b4) (b6-b5) (b3) b7 b6 b5 b4 b3 b2 b1 b0 0 1 0
7. clock generation circuits page 42 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 7.8 examples of main clock connection circuit the following describes the clocks generated by the clock generation circuit. 7.1 main clock the main clock is generated by the main clock oscillation circuit. this clock is used as the clock source for the cpu and peripheral function clocks. the main clock oscillator circuit is configured by connecting a resonator between the x in and x out pins. the main clock oscillator circuit contains a feedback resistor, which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip. the main clock oscillator circuit may also be configured by feeding an exter nally generated clock to the x in pin. figure 7.8 shows the examples of main clock connection circuit. the power consumption in the chip can be reduced by setting the cm05 bit in the cm0 register to 1 (main clock oscillator circuit turned off) after switching the clock source for the cpu clock to a sub clock or on-chip oscillator clock. in this case, x out goes ? h ? . furthermore, because the internal feedback resistor remains on, x in is pulled ? h ? to x out via the feedback resistor. during stop mode, all clocks including the main clock are turned off. refer to ? power control ? . if the main clock is not used, it is recommended to connect the xin pin to vcc to reduce power consump- tion during reset. external clock x in x out open v cc v ss note: 1. insert a damping resistor if required. resistance value varies depending on the oscillator setting. use resistance value recommended by the oscillator manufacturer. if the oscillator manufacturer recommends that a feedback resistor be added to the chip externally, insert a feedback resistor between x in and x out . 2. the external clock should not be stopped when it is connected to the x in pin and the main clock is selected as the cpu clock. oscillator rd (1) c in c out x in x out mcu (built-in feedback resistor) mcu (built-in feedback resistor) v ss
7. clock generation circuits page 43 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 7.9 examples of sub clock connection circuit 7.2 sub clock the sub clock is generated by the sub clock oscillation circuit. this clock is used as the clock source for the cpu clock, as well as the timer a and timer b count sources. the sub clock oscillator circuit is configured by connecting a crystal resonator between the x cin and x cout pins. the sub clock oscillator circuit contains a feedback resistor, which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip. the sub clock oscillator circuit may also be configured by feeding an externally generated clock to the x cin pin. figure 7.9 shows the examples of sub clock connection circuit. after reset, the sub clock is turned off. at this time, the feedback resistor is disconnected from the oscillator circuit. to use the sub clock for the cpu clock, set the cm07 bit in the cm0 register to 1 (sub clock) after the sub clock becomes oscillating stably. during stop mode, all clocks including the sub clock are turned off. refer to ? power control ? . external clock x c in x c out open v cc v ss note: 1. place a damping resistor if required. resistance values vary depending on the oscillator setting. use values recommended by each oscillator manufacturer. place a feedback resistor between x cin and x cout if the oscillator manufacturer recommends placing the resistor externally. oscillator r c d (1) c cin c cout x cin x cout mcu (built-in feedback resistor) mcu (built-in feedback resistor) v ss
7. clock generation circuits page 44 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 7.3 on-chip oscillator clock this clock is supplied by a variable on-chip oscillator. this clock is used as the clock source for the cpu and peripheral function clocks. in addition, if the pm22 bit in the pm2 register is 1 (on-chip oscillator clock for the watchdog timer count source), this clock is used as the count source for the watchdog timer (refer to 10. watchdog timer ? count source protective mode ? ). after reset, the on-chip oscillator clock divided by 16 is used for the cpu clock. it can also be turned on by setting the cm21 bit in the cm2 register to 1 (on-chip oscillator clock), and is used as the clock source for the cpu and peripheral function clocks. if the main clock stops oscillating when the cm20 bit in the cm2 register is 1 (oscillation stop, re-oscillation detection function enabled) and the cm27 bit is 1 (oscillation stop, re-oscillation detection interrupt), the on-chip oscillator automatically starts operating, supplying the necessary clock for the mcu. 7.4 pll clock the pll clock is generated from the main clock by a pll frequency synthesizer. this clock is used as the clock source for the cpu and peripheral function clocks. after reset, the pll clock is turned off. the pll frequency synthesizer is activated by setting the plc07 bit to 1 (pll operation). when the pll clock is used as the clock source for the cpu clock, wait t su (pll) for the pll clock to be stable, and then set the cm11 bit in the cm1 register to 1. before entering wait mode or stop mode, be sure to set the cm11 bit to 0 (cpu clock source is the main clock). furthermore, before entering stop mode, be sure to set the plc07 bit in the plc0 register to 0 (pll stops). figure 7.10 shows the procedure for using the pll clock as the clock source for the cpu. the pll clock frequency is determined by the equation below. pll clock frequency=f(x in ) (multiplying factor set by bits plc02 to plc00 in the plc0 register (however, 10 mhz pll clock frequency 20 mhz) bits plc02 to plc00 can be set only once after reset. table 7.2 shows the example for setting pll clock frequencies. table 7.2 example for setting pll clock frequencies x in (mhz) plc02 plc01 plc00 multiplying factor pll clock (mhz) (1) 10 0 0 1 2 20 50 1 0 4 note: 1. 10mhz pll clock frequency 20mhz.
7. clock generation circuits page 45 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 7.10 procedure to use pll clock as cpu clock source start set the cm07 bit to 0 (main clock), bits cm17 and cm16 to 00 2 (main clock undivided), and the cm06 bit to 0 (bits cm17 and cm16 enabled). (1) set bits plc02 to plc00 (multiplying factor). (to select a 16 mhz or higher pll clock) set the pm20 bit to 0 (2-wait states). set the plc07 bit to 1 (pll operation). wait until the pll clock becomes stable (t su (pll)). set the cm11 bit to 1 (pll clock for the cpu clock source). end note: 1. pll operation mode can be entered from high speed mode.
7. clock generation circuits page 46 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 7.5 cpu clock and peripheral function clock the cpu clock is used to operate the cpu and peripheral function clocks are used to operate the peripheral functions. 7.5.1 cpu clock this is the operating clock for the cpu and watchdog timer. the clock source for the cpu clock can be chosen to be the main clock, sub clock, on-chip oscillator clock or the pll clock. if the main clock or on-chip oscillator clock is selected as the clock source for the cpu clock, the selected clock source can be divided by 1 (undivided), 2, 4, 8 or 16 to produce the cpu clock. use the cm06 bit in cm0 register and bits cm17 to cm16 in cm1 register to select the divide-by-n value. when the pll clock is selected as the clock source for the cpu clock, the cm06 bit should be set to 0 and bits cm17 and cm16 to 00 2 (undivided). after reset, the on-chip oscillator clock divided by 16 provides the cpu clock. note that when entering stop mode from high or middle speed mode, on-chip oscillator mode or on-chip oscillator low power dissipation mode, or when the cm05 bit in the cm0 register is set to 1 (main clock turned off) in low-speed mode, the cm06 bit in the cm0 register is set to 1 (divide-by-8 mode). 7.5.2 peripheral function clock(f 1 , f 2 , f 8 , f 32 , f 1sio , f 2sio , f 8sio , f 32sio , f ad , f c32 ) these are operating clocks for the peripheral functions. of these, fi (i = 1, 2, 8, 32) and fi sio are derived from the main clock, pll clock, or on-chip oscillator clock divided by 1, 2, 8, or 32. the clock fi is used for timer a, timer b, si/o3 and si/o4 while fisio is used for uart0 to uart2. additionally, the f1 and f2 are also used for dead time timer, timer s, and multi-master i 2 c bus. the f ad is produced from the main clock, pll clock, or on-chip oscillator clock, and is used for the a/d converter. when the wait instruction is executed after setting the cm02 bit in the cm0 register to 1 (peripheral function clock turned off during wait mode), or when the mcu is in low power dissipation mode, the fi, fi sio , and f ad are turned off. the f c32 clock is produced from the sub clock, and is used for timers a and b. this clock can only be used when the sub clock is on. 7.5.3 clockoutput function the f 1 , f 8 , f 32 or f c clock can be output from the clk out pin. use the pclk5 bit in the pclkr register and bits cm01 to cm00 in the cm0 register to select. table 7.3 shows the function of the clk out pin. table 7.3 the function of the clk out pin pclk5 cm01 cm00 the function of the clk out pin 0 0 0 i/o port p9 0 001f c 010f 8 011f 32 100f 1 1 0 1 do not set 1 1 0 do not set 1 1 1 do not set
7. clock generation circuits page 47 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 7.6 power control there are three power control modes. in this chapter, all modes other than wait and stop modes are referred to as normal operation mode. 7.6.1 normal operation mode normal operation mode is further classified into seven modes. in normal operation mode, because the cpu clock and the peripheral function clocks both are on, the cpu and the peripheral functions are operating. power control is exercised by controlling the cpu clock frequency. the higher the cpu clock frequency, the greater the processing capability. the lower the cpu clock frequency, the smaller the power consumption in the chip. if the unnecessary oscillator circuits are turned off, the power consumption is further reduced. before the clock sources for the cpu clock can be switched over, the new clock source must be in stable oscillation. if the new clock source is the main clock, sub clock or pll clock, allow a sufficient wait time in a program until it becomes oscillating stably. note that operation modes cannot be changed directly from low power dissipation mode to on-chip oscil- lator mode or on-chip oscillator dissipation mode. nor can operation modes be changed directly from on- chip oscillator mode or on-chip oscillator dissipation mode to low power dissipation mode. when the cpu clock source is changed from the on-chip oscillator to the main clock, change the opera- tion mode to the medium speed mode (divided by 8 mode) after the clock was divided by 8 (the cm06 bit in the cm0 register was set to 1) in the on-chip oscillator mode. 7.6.1.1 high-speed mode the main clock divided by 1 provides the cpu clock. if the sub clock is on, f c32 can be used as the count source for timers a and b. 7.6.1.2 pll operation mode the main clock multiplied by 2 or 4 provides the pll clock, and this pll clock serves as the cpu clock. if the sub clock is on, f c32 can be used as the count source for timers a and b. pll operation mode can be entered from high speed mode. if pll operation mode is to be changed to wait or stop mode, first go to high speed mode before changing. 7.6.1.3 medium-speed mode the main clock divided by 2, 4, 8 or 16 provides the cpu clock. if the sub clock is on, f c32 can be used as the count source for timers a and b. 7.6.1.4 low-speed mode the sub clock provides the cpu clock. the main clock is used as the clock source for the peripheral function clock when the cm21 bit is set to 0 (on-chip oscillator turned off), and the on-chip oscillator clock is used when the cm21 bit is set to 1 (on-chip oscillator oscillating). the f c32 clock can be used as the count source for timers a and b. 7.6.1.5 low power dissipation mode in this mode, the main clock is turned off after being placed in low speed mode. the sub clock provides the cpu clock. the f c32 clock can be used as the count source for timers a and b. periph- eral function clock can use only f c32 . simultaneously when this mode is selected, the cm06 bit in the cm0 register becomes 1 (divided by 8 mode). in the low power dissipation mode, do not change the cm06 bit. consequently, the medium speed (divided by 8) mode is to be selected when the main clock is operated next.
7. clock generation circuits page 48 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 7.6.1.6 on-chip oscillator mode the selected on-chip oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the cpu clock. the on-chip oscillator clock is also the clock source for the peripheral function clocks. if the sub clock is on, f c32 can be used as the count source for timers a and b. the on-chip oscillator frequency can be selected by bits rocr3 to rocr0 in the rocr register. when the operation mode is returned to the high and medium speed modes, set the cm06 bit to 1 (divided by 8 mode). 7.6.1.7 on-chip oscillator low power dissipation mode the main clock is turned off after being placed in on-chip oscillator mode. the cpu clock can be se- lected as in the on-chip oscillator mode. the on-chip oscillator clock is the clock source for the periph- eral function clocks. if the sub clock is on, f c32 can be used as the count source for timers a and b. table 7.4 setting clock related bit and modes 7.6.2 wait mode in wait mode, the cpu clock is turned off, so are the cpu (because operated by the cpu clock) and the watchdog timer. however, if the pm22 bit in the pm2 register is 1 (on-chip oscillator clock for the watch- dog timer count source), the watchdog timer remains active. because the main clock, sub clock, on-chip oscillator clock and pll clock all are on, the peripheral functions using these clocks keep operating. 7.6.2.1 peripheral function clock stop function when the cm02 bit is 1 (peripheral function clocks turned off during wait mode), f 1 , f 2 , f 8 , f 32 , f 1sio , f 2sio , f 8sio , f 32sio , and f ad stop running in wait mode to reduce power consumption. however, f c32 remains active. 7.6.2.2 entering wait mode the mcu enters wait mode by executing the wait instruction. when the cm11 bit is set to 1 (cpu clock source is the pll clock), be sure to clear the cm11 bit to 0 (cpu clock source is the main clock) before going to wait mode. the power consumption of the chip can be reduced by clearing the plc07 bit to 0 (pll stops). 1 (1) modes cm2 register cm21 cm1 register cm11 cm17, cm16 cm0 register cm07 cm06 cm05 cm04 pll operation mode 0100 2 00 high-speed mode 0 0 00 2 00 0 medium- speed mode 0001 2 00 0 0010 2 00 0 divided by 2 00 01 0 0011 2 00 0 low-speed mode 1 0 1 low power dissipation mode 11 on-chip oscillator mode (3) 1 divided by 4 divided by 8 divided by 16 on-chip oscillator low power dissipation mode notes: 1. when the cm05 bit is set to 1 (main clock turned off) in low-speed mode, the mode goes to low power dissipation mode and cm06 bit is set to 1(divided by 8 mode) simultaneously. 2. the divide-by-n value can be selected the same way as in on-chip oscillator mode. 3. on-chip oscillator frequency can be any of those described in the section 7.6.1.6 on-chip oscillator mode . 0 0 101 2 000 110 2 000 110 111 2 00 0 100 2 00 0 (2) divided by 2 divided by 4 divided by 8 divided by 16 divided by 1 1 (1) (2) 1 0
7. clock generation circuits page 49 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m table 7.6 interrupts to exit wait mode interrupt cm02 = 0 cm02 = 1 _______ nmi interrupt available available serial i/o interrupt available when internal and external available when external clock is used clocks are used multi-master i 2 c interrupt available do not used key input interrupt available available a/d conversion interrupt available in one-shot or single sweep do not use mode timer a interrupt available in all modes available in event counter mode or when timer b interrupt count source is fc32 timer s interrupt available in all modes do not use _______ int interrupt available available 7.6.2.3 pin status during wait mode table 7.5 lists pin status during wait mode. table 7.5 pin status in wait mode pin status i/o ports maintains status immediately before entering wait mode when fc selected outputs clock clk out outputs the clock when the cm02 bit in the cm0 register is set when f1, f8, f32 to 0 (peripheral clock does not stop in wait mode selected maintains state immediately before entering stop mode when the cm02 bit is set to 1 (peripheral clock stops in wait mode) to use peripheral function interrupts to exit wait mode, set the followings before executing the wait instruction. 1. set the interrupt priority level to the bits ilvl2 to ilvl0 in the interrupt control register of the periph- eral function interrupts that are used to exit wait mode. also, set bits ilvl2 to ilvl0 of all peripheral function interrupts that are not used to exit wait mode to 000 2 (interrupt disabled). 2. set the i flag to 1. 3. operate the peripheral functions that are used to exit wait mode. when the peripheral function interrupts are used to exit wait mode, an interrupt routine is executed after an interrupt request is generated and the cpu is clocked. the cpu clock used when exiting wait mode by a peripheral function interrupt is the same cpu clock that is used when executing the wait instruction. 7.6.2.4 exiting wait mode ______ the mcu exits from wait mode by a hardware reset, nmi interrupt, or peripheral function interrupt. ______ if wait mode is exited by a hardware reset or nmi interrupt, set the peripheral function interrupt priority bits ilvl2 to ilvl0 to 000 2 (interrupts disabled) before executing the wait instruction. the cm02 bit affects the peripheral function interrupts. if the cm02 bit is 0 (peripheral function clocks not turned off during wait mode), all peripheral function interrupts can be used to exit wait mode. if the cm02 bit is 1 (peripheral function clock stops during wait mode), the peripheral functions using the peripheral function clock stops operating, so that only the peripheral functions clocked by external sig- nals can be used to exit wait mode. table 7.6 lists the interrupts to exit wait mode.
7. clock generation circuits page 50 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 7.6.3 stop mode in stop mode, all oscillator circuits are turned off, so are the cpu clock and the peripheral function clocks. therefore, the cpu and the peripheral functions clocked by these clocks stop operating. the least amount of power is consumed in this mode. if the voltage applied to vcc pin is v ram or more, the internal ram is retained. when applying 2.7 or less voltage to vcc pin, make sure vcc v ram . however, the peripheral functions clocked by external signals keep operating. the following interrupts can be used to exit stop mode. ______ ? nmi interrupt ? key interrupt ______ ? int interrupt ? timer a, timer b interrupt (when counting external pulses in event counter mode) ? serial i/o interrupt (when external clock is selected) 7.6.3.1 entering stop mode the mcu is placed into stop mode by setting the cm10 bit in the cm1 register to 1 (all clocks turned off). at the same time, the cm06 bit in the cm0 register is set to 1 (divide-by-8 mode) and the cm15 bit in the cm10 register is set to 1 (main clock oscillator circuit drive capability high). before entering stop mode, set the cm20 bit to 0 (oscillation stop, re-oscillation detection function dis- able). also, if the cm11 bit is 1 (pll clock for the cpu clock source), set the cm11 bit to 0 (main clock for the cpu clock source) and the plc07 bit to 0 (pll turned off) before entering stop mode. 7.6.3.2 pin status during stop mode the i/o pins retain their status held just prior to entering stop mode. 7.6.3.3 exiting stop mode ______ the mcu is moved out of stop mode by a hardware reset, nmi interrupt or peripheral function interrupt. ______ if the mcu is to be moved out of stop mode by a hardware reset or nmi interrupt, set the peripheral function interrupt priority bits ilvl2 to ilvl0 to 000 2 (interrupts disable) before setting the cm10 bit to 1. if the mcu is to be moved out of stop mode by a peripheral function interrupt, set up the following before setting the cm10 bit to 1. 1. in bits ilvl2 to ilvl0 of the interrupt control register, set the interrupt priority level of the peripheral function interrupt to be used to exit stop mode. also, for all of the peripheral function interrupts not used to exit stop mode, set bits ilvl2 to ilvl0 to 000 2 . 2. set the i flag to 1. 3. enable the peripheral function whose interrupt is to be used to exit stop mode. in this case, when an interrupt request is generated and the cpu clock is thereby turned on, an interrupt service routine is executed. ______ which cpu clock will be used after exiting stop mode by a peripheral function or nmi interrupt is deter- mined by the cpu clock that was on when the mcu was placed into stop mode as follows: if the cpu clock before entering stop mode was derived from the sub clock: sub clock if the cpu clock before entering stop mode was derived from the main clock: main clock divide-by-8 if the cpu clock before entering stop mode was derived from the on-chip oscillator clock: on-chip oscil- lator clock divide-by-8
7. clock generation circuits page 51 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 7.11 state transition to stop mode and wait mode reset medium-speed mode (divided-by-8 mode) high-speed, medium- speed mode stop mode wait mode interrupt interrupt low-speed mode stop mode interrupt wait mode interrupt stop mode all oscillators stopped interrupt wait mode wait instructio n interrupt cpu operation stopped pll operation mode (1, 2) wait mode interrupt cm10=1 (6 ) interrupt (4) stop mode wait instruction wait instruction wait instruction on-chip oscillator mode (selectable frequency) on-chip oscillator mode (f 2 (roc) /16) normal operation mode cm07=0 cm06=1 cm05=0 cm11=0 cm10=1 (5) on-chip oscillator low power dissipation mode stop mode interrupt (4 ) wait mode interrupt wait instructio n cm05, cm06, cm07: bits in the cm0 register cm10, cm11: bits in the cm1 register cm10=1 (6) cm10=1 (6) cm10=1 (6) cm10=1 (6) low power dissipation mode stop mode interrupt wait mode interrupt wait instruction cm21=1 cm21=0 cm10=1 (6 ) (7 ) : arrow shows mode can be changed. do not change mode to another mode when no arrow is shown. notes: 1. do not go directly from pll operation mode to wait or stop mode. 2. pll operation mode can be entered from high speed mode. similarly, pll operation mode can be changed back to high speed mode . 3. when the pm21 bit is set to 0 (system clock protective function unused). 4. the on-chip oscillator clock divided by 8 provides the cpu clock. 5. write to the cm0 register and cm1 register simultaneously by accessing in word units while cm21 bit is set to 0 (on-chip osc illator turned off). when the clock generated externally is input to the x cin pin, transit to stop mode with this process. 6. before entering stop mode, be sure to clear the cm20 bit in the cm2 register to 0 (oscillation stop and oscillation restart detection function disabled). 7. the cm06 bit is set to 1 (divide-by-8). figure 7.11 shows the state transition from normal operation mode to stop mode and wait mode. figure 7.12 shows the state transition in normal operation mode. table 7.7 shows a state transition matrix describing allowed transition and setting. the vertical line shows current state and horizontal line shows state after transition.
7. clock generation circuits page 52 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 7.12 state transition in normal mode cm04=0 cpu clock: f(pll) cm07=0 cm06=0 cm17=0 cm16=0 pll operation mode cm07=0 cm06=0 cm17=0 cm16=0 cm07=0 cm17=0 cm06=0 cm16=0 cm07=0 cm17=0 cm06=0 cm16=1 cm07=0 cm17=1 cm06=0 cm16=0 cm07=0 cm06=1 cm07=0 cm17=1 cm06=0 cm16=1 high-speed mode cm07=0 cm17=0 cm06=0 cm16=0 cm07=0 cm17=0 cm06=0 cm16=1 cm07=0 cm17=1 cm06=0 cm16=0 cm07=0 cm06=1 cm07=0 cm17=1 cm06=0 cm16=1 cm07=0 low-speed mode cm07=0 low power dissipation mode cm06=1 cm15=1 on-chip oscillator mode cpu clock on-chip oscillator mode cpu clock cpu clock on-chip oscillator low power dissipation mode cpu clock cm07=0 low-speed mode plc07=1 cm11=1 (5) plc07=0 cm11=0 (5) cm04=0 plc07=1 cm11=1 plc07=0 cm11=0 cm04=0 cm04=1 cm04=1 cm04=1 cm04=0 cm04=1 cm07=0 (2, 4) cm07=1 (3) cm05=1 (1, 7) cm05=0 cm21=0 (2, 6) cm21=1 cm21=0 (2, 6) cm21=1 cm21=0 cm21=1 main clock oscillation on-chip oscillator clock oscillation sub clock oscillation f(roc) f(roc)/2 f(roc)/4 f(roc)/8 f(roc)/16 f(roc) f(roc)/2 f(roc)/4 f(roc)/8 f(roc)/16 f(roc) f(roc)/2 f(roc)/4 f(roc)/8 f(roc)/16 f(roc) f(roc)/2 f(roc)/4 f(roc)/8 f(roc)/16 pll operation mode cpu clock: f(pll) cpu clock: f(x in ) high-speed mode middle-speed mode (divide by 2) cpu clock: f(x in )/2 cpu clock: f(x in )/4 cpu clock: f(x in )/8 cpu clock: f(x in )/16 cpu clock: f(x cin ) cpu clock: f(x cin ) cpu clock: f(x cin ) cm05=0 m0 m cm05=1 (1) cm05=1 (1) cm05=0 (5) (5) middle-speed mode (divide by 4) middle-speed mode (divide by 8) middle-speed mode (divide by 16) middle-speed mode (divide by 2) middle-speed mode (divide by 4) middle-speed mode (divide by 8) middle-speed mode (divide by 16) cpu clock: f(x in ) cpu clock: f(x in )/2 cpu clock: f(x in )/4 cpu clock: f(x in )/8 cpu clock: f(x in )/16 on-chip oscillator low power dissipation mode : arrow shows mode can be changed. do not change mode to another mode when no arrow is shown. notes: 1. avoid making a transition when the cm20 bit is set to 1 (oscillation stop, re-oscillation detection function enabled). set the cm20 bit to 0 (oscillation stop, re-oscillation detection function disabled) before transiting. 2. wait for the main clock oscillation stabilization time before switching over. set the cm15 bit in the cm1 register to 1 (drive capacity high) until main clock oscillation is stabilized. 3. switch clock after oscillation of sub-clock is sufficiently stable. 4. change bits cm17 and cm16 before changing the cm06 bit. 5. the pm20 bit in the pm2 register becomes effective when the plc07 bit in the plc0 register is set to 1 (pll on). chan ge the pm20 bit when the plc07 bit is set to 0 (pll off). set the pm20 bit to 0 (2 waits) when pll clock > 16mhz. 6. set the cm06 bit to 1 (division by 8 mode) before changing back the operation mode from on-chip oscillator mode to hig h- or middle-speed mode. 7. when the cm21 bit is set to 0 (on-chip oscillator turned off) and the cm05 bit is set to 1 (main clock turned off), th e cm06 bit is fixed to 1 (divide-by-8 mode) and the cm15 bit is fixed to 1 (drive capability high). cm07=1 (3) cm07=0 (4)
7. clock generation circuits page 53 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m table 7.7 allowed transition and setting high-speed mode, middle-speed mode on-chip oscillator mode stop mode wait mode on-chip oscillator low power dissipation mode pll operation mode 2 low power dissipation mode low-speed mode 2 current state state after transition 8 -- (8) (18) 5 (9) 7 -- (10) (11) 1, 6 (12) 3 (14) 4 -- -- -- -- (13) 3 (15) -- -- -- -- -- -- (10) -- -- -- -- -- -- -- -- (18) (18) -- -- (16) 1 (17) (16) 1 (17) (16) 1 (17) (16) 1 (17) (16) 1 (17) -- -- (18) 5 (18) 5 (18) (18) (18) (18) (18) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) setting operation cm04 = 0 sub clock turned off cm04 = 1 sub clock oscillating cm06 = 0, cpu clock no division mode cm17 = 0 , cm16 = 0 cm06 = 0, cpu clock division by 2 mode cm17 = 0 , cm16 = 1 cm06 = 0, cpu clock division by 4 mode cm17 = 1 , cm16 = 0 cm06 = 1 cpu clock division by 8 mode cm06 = 0, cpu clock division by 16 mode cm17 = 1 , cm16 = 1 cm07 = 0 main clock, pll clock, or on-chip oscillator clock selected cm07 = 1 sub clock selected cm05 = 0 main clock oscillating cm05 = 1 main clock turned off plc07 = 0, cm11 = 0 main clock selected plc07 = 1, cm11 = 1 pll clock selected cm21 = 0 main clock or pll clock selected cm21 = 1 on-chip oscillator clock selected cm10 = 1 transition to stop mode wait instruction transition to wait mode hardware interrupt exit stop mode or wait mode notes: 1. avoid making a transition when the cm20 bit is set to 1 (oscillation stop, re-oscillation detection function enabled). set the cm20 bit to 0 (oscillation stop, re-oscillation detection function disabled) before transiting. 2. on-chip oscillator clock oscillates and stops in low-speed mode. in this mode, the on-chip oscillator can be used as pe ripheral function clock. sub clock oscillates and stops in pll operation mode. in this mode, sub clock can be used as a clock for the timers a and b. 3. pll operation mode can only be entered from and changed to high-speed mode. 4. set the cm06 bit to 1 (division by 8 mode) before transiting from on-chip oscillator mode to high- or middle-speed mode . 5. when exiting stop mode, the cm06 bit is set to 1 (division by 8 mode). 6. if the cm05 bit is set to 1 (main clock stop), then the cm06 bit is set to 1 (division by 8 mode). 7. a transition can be made only when sub clock is oscillating. 8. state transitions within the same mode (divide-by-n values changed or subclock oscillation turned on or off) are shown in the table below. --: cannot transit (11) 1 high-speed mode, middle-speed mode on-chip oscillator mode stop mode wait mode on-chip oscillator low power dissipation mode pll operation mode 2 low power dissipation mode low-speed mode 2 8 8 (3) (3) (3) (3) (4) (4) (4) (4) (5) (7) (7) (5) (5) (5) (7) (7) (6) (6) (6) (6) no division divided by 2 (3) (3) (3) (3) (4) (4) (4) (4) (5) (5) (5) (5) (7) (7) (7) (7) (6) (6) (6) (6) (1) (1) (1) (1) (1) (2) (2) (2) (2) (2) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- sub clock oscillating sub clock turned off --: cannot transit divided by 4 divided by 8 divided by 16 no division divided by 2 divided by 4 divided by 8 divided by 16 no division divided by 4 sub clock oscillating sub clock turned off divided by 8 divided by 16 divided by 2 no division divided by 4 divided by 8 divided by 16 divided by 2 9. ( ) : setting method. refer to following table. cm04, cm05, cm06, cm07 : bits in the cm0 register cm10, cm11, cm16, cm17 : bits in the cm1 register cm20, cm21 : bits in the cm2 register plc07 : bit in the plc0 register (9) 7 (8)
7. clock generation circuits page 54 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 7.7 system clock protective function when the main clock is selected for the cpu clock source, this function protects the clock from modifica- tions in order to prevent the cpu clock from becoming halted by run-away. if the pm21 bit in the pm2 register is set to 1 (clock modification disabled), the following bits are protected against writes: ? bits cm02, cm05, and cm07 in cm0 register ? bits cm10 and cm11 in cm1 register ? cm20 bit in cm2 register ? all bits in the plc0 register before the system clock protective function can be used, the following register settings must be made while the cm05 bit in the cm0 register is 0 (main clock oscillating) and cm07 bit is 0 (main clock selected for the cpu clock source): (1) set the prc1 bit in the prcr register to 1 (enable writes to pm2 register). (2) set the pm21 bit in the pm2 register to 1 (disable clock modification). (3) set the prc1 bit in the prcr register to 0 (disable writes to pm2 register). do not execute the wait instruction when the pm21 bit is 1. 7.8 oscillation stop and re-oscillation detect function the oscillation stop and re-oscillation detect function detects the re-oscillation after stop of main clock oscillation circuit. when the oscillation stop and re-oscillation detection occurs, the oscillation stop detect function is reset or oscillation stop and re-oscillation detection interrupt is generated, depending on the cm27 bit set in the cm2 register. the oscillation stop detect function is enabled or disabled by the cm20 bit in the cm2 register. table 7.8 lists a specification overview of the oscillation stop and re-oscillation detect function. table 7.8 specification overview of oscillation stop and re-oscillation detect function item specification oscillation stop detectable clock and f(x in ) 2 mhz frequency bandwidth enabling condition for oscillation stop, set cm20 bit to 1(enable) re-oscillation detection function operation at oscillation stop, ? reset occurs (when cm27 bit =0) re-oscillation detection ? oscillation stop, re-oscillation detection interrupt occurs(when cm27 bit =1)
7. clock generation circuits page 55 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 7.8.1 operation when cm27 bit = 0 (oscillation stop detection reset) when main clock stop is detected when the cm20 bit is 1 (oscillation stop, re-oscillation detection func- tion enabled), the mcu is initialized, coming to a halt (oscillation stop reset; refer to ? sfr ? , ? reset ? ). this status is reset with hardware reset 1. also, even when re-oscillation is detected, the mcu can be initialized and stopped; it is, however, necessary to avoid such usage. (during main clock stop, do not set the cm20 bit to 1 and the cm27 bit to 0.) 7.8.2 operation when cm27 bit = 1 (oscillation stop and re-oscillation detect interrupt) when the main clock corresponds to the cpu clock source and the cm20 bit is 1 (oscillation stop and re- oscillation detect function enabled), the system is placed in the following state if the main clock comes to a halt: ? oscillation stop and re-oscillation detect interrupt request occurs. ? the on-chip oscillator starts oscillation, and the on-chip oscillator clock becomes the cpu clock and clock source for peripheral functions in place of the main clock. ? cm21 bit = 1 (on-chip oscillator clock for cpu clock source) ? cm22 bit = 1 (main clock stop detected) ? cm23 bit = 1 (main clock stopped) when the pll clock corresponds to the cpu clock source and the cm20 bit is 1, the system is placed in the following state if the main clock comes to a halt: since the cm21 bit remains unchanged, set it to 1 (on-chip oscillator clock) inside the interrupt routine. ? oscillation stop and re-oscillation detect interrupt request occurs. ? cm22 bit = 1 (main clock stop detected) ? cm23 bit = 1 (main clock stopped) ? cm21 bit remains unchanged when the cm20 bit is 1, the system is placed in the following state if the main clock re-oscillates from the stop condition: ? oscillation stop and re-oscillation detect interrupt request occurs. ? cm22 bit = 1 (main clock re-oscillation detected) ? cm23 bit = 0 (main clock oscillation) ? cm21 bit remains unchanged
7. clock generation circuits page 56 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m switch to the main clock determine several times whether the cm23 bit is set to 0 (main clock oscillates) set the cm22 bit to 0 ("oscillatin stop, re-oscillation" not detected) set the cm06 bit to 1 (divide-by-8 mode) set the cm21 bit to 0 (main clock or pll clock) cm06: bit in the cm0 register cm23 to cm21: bits in the cm2 register yes no end note: 1. if the clock source for cpu clock is to be changed to pll clock, set to pll operation mode after set to high-speed mode. 7.8.3 how to use oscillation stop and re-oscillation detect function ? the oscillation stop and re-oscillation detect interrupt shares the vector with the watchdog timer inter- rupt. if the oscillation stop, re-oscillation detection and watchdog timer interrupts both are used, read the cm22 bit in an interrupt routine to determine which interrupt source is requesting the interrupt. ? where the main clock re-oscillated after oscillation stop, return the main clock to the cpu clock and peripheral function clock source by program. figure 7.13 shows the procedure for switching the clock source from the on-chip oscillator to the main clock. ? simultaneously with oscillation stop, re-oscillation detection interrupt occurrence, the cm22 bit be- comes 1. when the cm22 bit is set at 1, oscillation stop, re-oscillation detection interrupt are disabled. by setting the cm22 bit to 0 by program, oscillation stop, re-oscillation detection interrupt are enabled. ? if the main clock stops during low speed mode where the cm20 bit is 1, an oscillation stop, re-oscillation detection interrupt request is generated. at the same time, the on-chip oscillator starts oscillating. in this case, although the cpu clock is derived from the sub clock as it was before the interrupt occurred, the peripheral function clocks now are derived from the on-chip oscillator clock. ? to enter wait mode while using the oscillation stop, re-oscillation detection function, set the cm02 bit to 0 (peripheral function clocks not turned off during wait mode). ? since the oscillation stop, re-oscillation detection function is provided in preparation for main clock stop due to external factors, set the cm20 bit to 0 (oscillation stop, re-oscillation detection function disabled) where the main clock is stopped or oscillated by program, that is where the stop mode is selected or the cm05 bit is altered. ? this function cannot be used if the main clock frequency is 2 mhz or less. in that case, set the cm20 bit to 0. figure 7.13 procedure to switch clock source from on-chip oscillator to main clock
8. protection page 57 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 8. protection in the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. figure 8.1 shows the prcr register. the following lists the registers protected by the prcr register. ? registers protected by the prc0 bit: cm0, cm1, cm2, lpcc1, plc0, rocr, and pclkr ? registers protected by the prc1 bit: pm0, pm1, pm2, tb2sc, invc0, and invc1 ? registers protected by the prc2 bit: pd9 , pacr, s4c, and nddr the prc2 bit is set to 0 (write enabled) when data is written to the sfr area after setting the prc2 bit to 1 (write enable). set registers pd9, pacr, s4c and nddr immediately after setting the prc2 bit in the prcr register to 1 (write enable). do not generate an interrupt or a dma transfer between the instruction to set the prc2 bit to 1 and the next instruction. bits prc3, prc1, and prc0 are not set to 0 even if data is written to the sfr area. set bits prc3, prc1, and prc0 to 0 by program. protect register symbol address after reset prcr 000a 16 xx000000 2 bit name bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 : write protected 1 : write enabled prc1 prc0 prc2 function rw 0 rw rw rw nothing is assigned. if necessary, set to 0. when read, the content is undefined protect bit 0 protect bit 1 protect bit 2 enable write to registers cm0, cm1, cm2, lpcc1, rocr, plc0, and pclkr 0 : write protected 1 : write enabled enable write to pm0, pm1, pm2, tb2sc, invc0 and invc1 registers 0 : write protected 1 : write enabled (1) enable write to pd9, pacr, s4c, and nddr registers rw (b7-b6) 00 reserved bit set to 0 (b5-b3) note: 1. the prc2 bit is set to 0 when writing into the sfr area after the prc2 bit is set to 1. bits prc0 and prc1 are not automatically set to 0. set them to 0 by program. figure 8.1 prcr register
9. interrupts page 58 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m ? maskable interrupt: an interrupt which can be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority can be changed by priority level. ? non-maskable interrupt: an interrupt which cannot be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority cannot be changed by priority level. figure 9.1 interrupts interrupt ? ? ? ? ? ? ? ? ? ? ? software (non-maskable interrupt) hardware ? ? ? ? ? ? ? ? special (non-maskable interrupt) peripheral function (1) (maskable interrupt) ? ? ? ? ? undefined instruction (und instruction) overflow (into instruction) brk instruction int instruction ? ? ? ? ? ? ? ? ? _______ nmi ________ dbc (2) watchdog timer oscillation stop and re-oscillation detection single step (2) address match notes: 1. peripheral function interrupts are generated by the mcu's internal functions. 2. do not normally use this interrupt because it is provided exclusively for use by development tools. 9. interrupts note the si/o4 interrupt of peripheral function interrupts is not available in the 64-pin package. 9.1 type of interrupts figure 9.1 shows types of interrupts.
9. interrupts page 59 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 9.1.1 software interrupts a software interrupt occurs when executing certain instructions. software interrupts are non-maskable interrupts. 9.1.1.1 undefined instruction interrupt an undefined instruction interrupt occurs when executing the und instruction. 9.1.1.2 overflow interrupt an overflow interrupt occurs when executing the into instruction with the o flag set to 1 (the opera- tion resulted in an overflow). the following are instructions whose o flag changes by arithmetic: abs, adc, adcf, add, cmp, div, divu, divx, neg, rmpa, sbb, sha, sub 9.1.1.3 brk interrupt a brk interrupt occurs when executing the brk instruction. 9.1.1.4 int instruction interrupt an int instruction interrupt occurs when executing the int instruction. software interrupt nos. 0 to 63 can be specified for the int instruction. because software interrupt nos. 1 to 31 are assigned to peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be executed by executing the int instruction. in software interrupt nos. 0 to 31, the u flag is saved to the stack during instruction execution and is cleared to 0 (isp selected) before executing an interrupt sequence. the u flag is restored from the stack when returning from the interrupt routine. in software interrupt nos. 32 to 63, the u flag does not change state during instruction execution, and the sp then selected is used.
9. interrupts page 60 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 9.1.2 hardware interrupts hardware interrupts are classified into two types ? special interrupts and peripheral function interrupts. 9.1.2.1 special interrupts special interrupts are non-maskable interrupts. _______ 9.1.2.1.1 nmi interrupt _______ _______ an nmi interrupt is generated when input on the nmi pin changes state from high to low. for details _______ about the nmi interrupt, refer to the section "nmi interrupt". ________ 9.1.2.1.2 dbc interrupt this interrupt is exclusively for debugger, do not use in any other circumstances. 9.1.2.1.3 watchdog timer interrupt generated by the watchdog timer. once a watchdog timer interrupt is generated, be sure to initialize the watchdog timer. for details about the watchdog timer, refer to the section "watchdog timer". 9.1.2.1.4 oscillation stop and re-oscillation detection interrupt generated by the oscillation stop and re-oscillation detection function. for details about the oscilla- tion stop and re-oscillation detection function, refer to the section "clock generating circuit". 9.1.2.1.5 single-step interrupt do not normally use this interrupt because it is provided exclusively for use by development tools. 9.1.2.1.6 address match interrupt an address match interrupt is generated immediately before executing the instruction at the address indicated by the rmad0 or rmad1 register, if the corresponding enable bit (aier0 or aier1 bit in the aier register) is set to 1. for details about the address match interrupt, refer to the section ? address match interrupt ? . 9.1.2.2 peripheral function interrupts peripheral function interrupts are maskable interrupts and generated by the mcu's internal functions. the interrupt sources for peripheral function interrupts are listed in table 9.2 relocatable vector tables. for details about the peripheral functions, refer to the description of each peripheral function in this manual.
9. interrupts page 61 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m interrupt source vector table addresses remarks reference address (l) to address (h) undefined instruction fffdc 16 to fffdf 16 interrupt on und instruction m16c/60, m16c/20 overflow fffe0 16 to fffe3 16 interrupt on into instruction serise software brk instruction fffe4 16 to fffe7 16 if the contents of address fffe7 16 maual is ff 16 , program execution starts from the address shown by the vec- tor in the relocatable vector table address match fffe8 16 to fffeb 16 address match interrupt single step (1) fffec 16 to fffef 16 watchdog timer ffff0 16 to ffff3 16 watchdog timer, oscillation stop and clock generation circuits re-oscillation detection ________ dbc (1) ffff4 16 to ffff7 16 _______ nmi ffff8 16 to ffffb 16 _______ nmi interrupt reset (2) ffffc 16 to fffff 16 reset figure 9.2 interrupt vector 9.2 interrupts and interrupt vector one interrupt vector consists of 4 bytes. set the start address of each interrupt routine in the respective interrupt vectors. when an interrupt request is accepted, the cpu branches to the address set in the corresponding interrupt vector. figure 9.2 shows the interrupt vector. 9.2.1 fixed vector tables the fixed vector tables are allocated to the addresses from fffdc 16 to fffff 16 . table 9.1 lists the fixed vector tables. in the flash memory version of mcu, the vector addresses (h) of fixed vectors are used by the id code check function. for details, refer to the section "flash memory rewrite disabling function". table 9.1 fixed vector tables mid address low address 0 0 0 0 high address 0 0 0 0 0 0 0 0 vector address (l) lsb msb vector address (h) note: 1. do not normally use this interrupt because it is provided exclusively for use by development tools.
9. interrupts page 62 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 9.2.2 relocatable vector tables the 256 bytes beginning with the start address set in the intb register comprise a reloacatable vector table area. table 9.2 lists the relocatable vector tables. setting an even address in the intb register results in the interrupt sequence being executed faster than in the case of odd addresses. software interrupt number reference vector address (1) address (l) to address (h) 0 11 12 13 14 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 63 to 10 15 16 5 6 7 8 4 9 1 to 3 interrupt source brk instruction int3 si/o3, int4 si/o4, int5 ic/oc interrupt 1, i 2 c bus interface ic/oc interrupt 0 (2) (2) dma0 dma1 key input interrupt a/d uart0 transmit uart0 receive uart1 transmit uart1 receive timer a0 timer a1 timer a2 timer a3 timer a4 timer b0 timer b1 timer b2 int0 int1 int2 software interrupt uart 2 bus collision detection uart2 transmit, nack2 (3) uart2 receive, ack2 (3) ( 4 ) ic/oc base timer, s cl /s da ( 4 ) m16c/60, m16c/20 series software manual int interrupt timer s timer s multi-master i 2 c bus interface serial i/o int interrupt serial i/o dmac key input interrupt a/d convertor serial i/o timer int interrupt m16c/60, m16c/20 series software manual (5 ) (reserved) +0 to +3 (0000 16 to 0003 16 ) +44 to +47 (002c 16 to 002f 16 ) +48 to +51 (0030 16 to 0033 16 ) +52 to +55 (0034 16 to 0037 16 ) +56 to +59 (0038 16 to 003b 16 ) +68 to +71 (0044 16 to 0047 16 ) +72 to +75 (0048 16 to 004b 16 ) +76 to +79 (004c 16 to 004f 16 ) +80 to +83 (0050 16 to 0053 16 ) +84 to +87 (0054 16 to 0057 16 ) +88 to +91 (0058 16 to 005b 16 ) +92 to +95 (005c 16 to 005f 16 ) +96 to +99 (0060 16 to 0063 16 ) +100 to +103 (0064 16 to 0067 16 ) +104 to +107 (0068 16 to 006b 16 ) +108 to +111 (006c 16 to 006f 16 ) +112 to +115 (0070 16 to 0073 16 ) +116 to +119 (0074 16 to 0077 16 ) +120 to +123 (0078 16 to 007b 16 ) +124 to +127 (007c 16 to 007f 16 ) +128 to +131 (0080 16 to 0083 16 ) +252 to +255 (00fc 16 to 00ff 16 ) +40 to +43 (0028 16 to 002b 16 ) +60 to +63 (003c 16 to 003f 16 ) +64 to +67 (0040 16 to 0043 16 ) +20 to +23 (0014 16 to 0017 16 ) +24 to +27 (0018 16 to 001b 16 ) +28 to +31 (001c 16 to 001f 16 ) +32 to +35 (0020 16 to 0023 16 ) +16 to +19 (0010 16 to 0013 16 ) +36 to +39 (0024 16 to 0027 16 ) to (5) (6) notes: 1. address relative to address in intb. 2. use the ifsr6 and ifsr7 bits in the ifsr register to select. 3. during i 2 c bus mode, nack and ack interrupts comprise the interrupt source. 4. use the ifsr26 and ifsr27 bits in the ifsr2a register to select. 5. these interrupts cannot be disabled using the i flag. 6. bus collision detection: during iebus mode, this bus collision detection constitutes the cause of an interrupt. during i 2 c bus mode, however, a start condition or a stop condition detection constitutes the cause of an interrupt. table 9.2 relocatable vector tables
9. interrupts page 63 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 9.3 interrupt control the following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. what is explained here does not apply to nonmaskable interrupts. use i flag in the the flg register, ipl, and bits ilvl2 to ilvl0 in the each interrupt control register to enable/disable the maskable interrupts. whether an interrupt is requested is indicated by the ir bit in each interrupt control register. figure 9.3 shows the interrupt control registers. also, the following interrupts share a vector and an interrupt control register. ________ ? int4 and sio3 ________ ? int5 and sio4 ? ic/oc base timer and s cl /s da ? ic/oc interrupt 1 and i 2 c bus interface an interrupt request is set by bits ifsr7 and ifsr6 in the ifsr register and bits ifsr27 and ifsr26 in the ifsr2a register. figure 9.4 shows registers ifsr and ifsr2a.
9. interrupts page 64 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 9.3 interrupt control registers c01wkic, c0recic, c0trmic, icoc0ic, icoc1ic, iicic, btic, scldaic, bcnic, dm0ic, dm1ic, c01erric, adic, kupic, s0tic to s2tic, s0ric to s2ric, ta0ic to ta4ic, tb0ic to tb2ic, int3ic, s4ic, int5ic, s31c, int4ic, int0ic to int2ic registers symbol address after reset int3ic 0044 16 xx00x000 2 s4ic, int5ic 0048 16 xx00x000 2 s3ic, int4ic 0049 16 xx00x000 2 int0ic to int2ic 005d 16 to 005f 16 xx00x000 2 bit name function bit symbol b b 4 b3 b 2b1b0 ilvl0 ir pol interrupt priority level select bit interrupt request bit polarity select bit reserved bit 0: interrupt not requested 1: interrupt requested 0: selects falling edge (3, 4) 1: selects rising edge set to 0 ilvl1 ilvl2 interrupt control register (2) b b 4 b3 b 2b1b0 bit name function bit symbol rw symbol address after reset icoc0ic 0045 16 xxxxx000 2 icoc1ic, iicic (3) 0046 16 xxxxx000 2 btic, scldaic (3) 0047 16 xxxxx000 2 bcnic 004a 16 xxxxx000 2 dm0ic, dm1ic 004b 16 , 004c 16 xxxxx000 2 adic, kupic (3) 004e 16 xxxxx000 2 s0tic to s2tic 0051 16 , 0053 16 , 004f 16 xxxxx000 2 s0ric to s2ric 0052 16 , 0054 16 , 0050 16 xxxxx000 2 ta0ic to ta4ic 0055 16 to 0059 16 xxxxx000 2 tb0ic to tb2ic 005a 16 to 005c 16 xxxxx000 2 ilvl0 ir interrupt priority level select bit interrupt request bit 0: interrupt not requested 1: interrupt requested ilvl1 ilvl2 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 rw rw rw rw (1) (b7-b4) rw rw rw rw rw rw (b7-b6) (b5) rw (1) notes: 1. this bit can only be reset by writing 0 (do not write 1). 2. to rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that register. for details, refer to 21. 4 interrupts . 3. use the ifsr2a register to select. notes: 1. this bit can only be reset by writing 0 (do not write 1). 2. to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. for details, refer to 21.4 interrupts . 3. if the ifsri bit in the ifsr register (i = 0 to 5) is 1 (both edges), set the pol bit in the intiic register to 0 (falling edge). 4. set the pol bit in register s3ic or s4ic to 0 (falling edge) when the ifsr6 bit in the ifsr register is set to 0 (si/o3 selected) or ifsr7 bit in the ifsr register to 0 (si/o4 selected), respectively. nothing is assigned. if necessary, set to 0. when read, the contents are undefined nothing is assigned. if necessary, set to 0. when read, the contents are undefined
9. interrupts page 65 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 9.4 ifsr register and ifsr2a register interrupt request cause select register bit name function bit symbol rw symbol address after reset ifsr 035f 16 00 16 ifsr0 b7 b6 b5 b4 b3 b2 b1 b0 int0 interrupt polarity switching bit 0 : si/o 3 1 : int4 0 : si/o 4 1 : int5 0 : one edge 1 : both edges 0 : one edge 1 : both edges 0 : one edge 1 : both edges 0 : one edge 1 : both edges 0 : one edge 1 : both edges int1 interrupt polarity switching bit int2 interrupt polarity switching bit int3 interrupt polarity switching bit int4 interrupt polarity switching bit int5 interrupt polarity switching bit 0 : one edge 1 : both edges interrupt request cause select bit interrupt request cause select bit ifsr1 ifsr2 ifsr3 ifsr4 ifsr5 ifsr6 ifsr7 rw rw rw rw rw rw rw rw (1) (1) (1) (1) (1) (1) (2) (2) notes: 1. when setting this bit to 1 (both edges), make sure the pol bit in registers int0ic to int5ic is set to 0 (falling edge). 2. when setting this bit to 0 (si/o3, si/o4), make sure the pol bit in registers s3ic and s4ic is set to 0 (falling edge). interrupt request cause select register 2 bit name function bit symbol rw symbol address after reset ifsr2a 035e 16 00xxxxx0 2 b7 b6 b5 b4 b3 b2 b1 b0 0: ic/oc base timer 1: s cl /s da 0: ic/oc interrupt 1 1: i 2 c bus interface ifsr26 ifsr27 interrupt request cause select bit interrupt request cause select bit rw rw set to 1 (b5-b1) nothing is assigned. if necessary, set to 0 when read, their contents are undefined note: 1. after reset, set this bit to 1 to enable interrupt. ifsr20 1 reserved bit rw (1)
9. interrupts page 66 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 9.3.1 i flag the i flag enables or disables the maskable interrupt. setting the i flag to 1 (= enabled) enables the maskable interrupt. setting the i flag to 0 (= disabled) disables all maskable interrupts. 9.3.2 ir bit the ir bit is set to 1 (= interrupt requested) when an interrupt request is generated. then, when the interrupt request is accepted and the cpu branches to the corresponding interrupt vector, the ir bit is cleared to 0 (= interrupt not requested). the ir bit can be cleared to 0 in a program. note that do not write 1 to this bit. 9.3.3 ilvl2 to ilvl0 bits and ipl interrupt priority levels can be set using bits ilvl2 to ilvl0. table 9.3 shows the settings of interrupt priority levels and table 9.4 shows the interrupt priority levels enabled by the ipl. the following are conditions under which an interrupt is accepted: i flag = 1 ir bit = 1 interrupt priority level > ipl the i flag, ir bit, bits ilvl2 to ilvl0, and ipl are independent of each other. in no case do they affect one another. table 9.4 interrupt priority levels enabled by ipl table 9.3 settings of interrupt priority levels ilvl2 to ilvl0 bits interrupt priority level priority order 000 2 001 2 010 2 011 2 100 2 101 2 110 2 111 2 level 0 (interrupt disabled) level 1 level 2 level 3 level 4 level 5 level 6 level 7 low high enabled interrupt priority levels interrupt levels 1 and above are enabled interrupt levels 2 and above are enabled interrupt levels 3 and above are enabled interrupt levels 4 and above are enabled interrupt levels 5 and above are enabled interrupt levels 6 and above are enabled interrupt levels 7 and above are enabled all maskable interrupts are disabled ipl 000 2 001 2 010 2 011 2 100 2 101 2 110 2 111 2
9. interrupts page 67 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 9.4 interrupt sequence an interrupt sequence (the device behavior from the instant an interrupt is accepted to the instant the interrupt routine is executed) is described here. if an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. if an interrupt occurs during execution of either the smovb, smovf, sstr or rmpa instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. the cpu behavior during the interrupt sequence is described below. figure 9.5 shows time required for executing the interrupt sequence. (1) the cpu gets interrupt information (interrupt number and interrupt request priority level) by reading the address 00000 16 . then it clears the ir bit for the corresponding interrupt to 0 (interrupt not requested). (2) the flg register immediately before entering the interrupt sequence is saved to the cpu ? s internal temporary register (note) . (3) the i, d and u flags in the flg register become as follows: the i flag is cleared to 0 (interrupts disabled). the d flag is cleared to 0 (single-step interrupt disabled). the u flag is cleared to 0 (isp selected). however, the u flag does not change state if an int instruction for software interrupt nos. 32 to 63 is executed. (4) the cpu ? s internal temporary register (1) is saved to the stack. (5) the pc is saved to the stack. (6) the interrupt priority level of the accepted interrupt is set in the ipl. (7) the start address of the relevant interrupt routine set in the interrupt vector is stored in the pc. after the interrupt sequence is completed, the processor resumes executing instructions from the start address of the interrupt routine. note: 1. this register cannot be used by user. figure 9.5 time required for executing interrupt sequence 123456789 101 1121314151617 18 sp-2 contents sp-4 contents vec contents vec+2 contents interrupt information address 0000 16 undefined (1) sp-2 sp-4 vec vec+2 pc cpu clock address bus data bus wr (2 ) rd notes: 1. the undefined state depends on the instruction queue buffer. a read cycle occurs when the instruction queue buffer is ready to accept instructions. 2. when the stack is in the internal ram, the wr signal indicates the write timing by changing high-level to low-level. undefined (1) undefined (1 )
9. interrupts page 68 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m interrupt sources _______ watchdog timer, nmi, oscillation stop and re-oscillation detection _________ software, address match, dbc, single-step 9.4.2 variation of ipl when interrupt request is accepted when a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the ipl. when a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed in table 9.5 is set in the ipl. shown in table 9.5 are the ipl values of software and special interrupts when they are accepted. table 9.5 ipl level that is set to ipl when a software or special interrupt is accepted figure 9.6 interrupt response time 9.4.1 interrupt response time figure 9.6 shows the interrupt response time. the interrupt response or interrupt acknowledge time denotes time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed. specifically, it consists of the time from when an interrupt request is generated till when the instruction then executing is completed ((a) in figure 9.6 ) and the time during which the inter- rupt sequence is executed ((b) in figure 9.6 ). instruction interrupt sequence instruction in interrupt routine time interrupt response time (a) (b) interrupt request acknowledged interrupt request generated (a) the time from when an interrupt request is generated till when the instruction then executing is completed. the length of this time varies with the instruction being executed. the divx instruction requires the longest time, which is equal to 30 cycles (without wait state, the divisor being a register). (b) the time during which the interrupt sequence is executed. for details, see the table below. note, however, that the values in this table must be increased 2 cycles for the dbc interrupt and 1 cycle for the address match and single-step interrupts. interrupt vector address even even odd odd sp value even odd even odd without wait 18 cycles 19 cycles 19 cycles 20 cycles ipl setting 7 no change
9. interrupts page 69 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 9.4.3 saving registers in the interrupt sequence, the flg register and pc are saved to the stack. at this time, the 4 high-order bits of the pc and the 4 high-order (ipl) and 8 low-order bits of the flg register, 16 bits in total, are saved to the stack first. next, the 16 low-order bits of the pc are saved. figure 9.7 shows the stack status before and after an interrupt request is accepted. the other necessary registers must be saved in a program at the beginning of the interrupt routine. use the pushm instruction, and all registers except sp can be saved with a single instruction. figure 9.7 stack status before and after acceptance of interrupt request address content of previous stack stack [sp] sp value before interrupt request is accepted. m m ? 1 m ? 2 m ? 3 m ? 4 stack status before interrupt request is acknowledged stack status after interrupt request is acknowledged content of previous stack m + 1 msb lsb m m ? 1 m ? 2 m ? 3 m ? 4 address flg l content of previous stack stack flg h pc h [sp] new sp value content of previous stack m + 1 msb lsb pc l pc m
9. interrupts page 70 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 9.8 operation of saving register the operation of saving registers carried out in the interrupt sequence is dependent on whether the sp (1) , at the time of acceptance of an interrupt request, is even or odd. if the stack pointer (1) is even, the flg register and the pc are saved, 16 bits at a time. if odd, they are saved in two steps, 8 bits at a time. figure 9.8 shows the operation of the saving registers. note: 1. when any int instruction in software numbers 32 to 63 has been executed, this is the sp indicated by the u flag. otherwise, it is the isp. (2) sp contains odd number [sp] (odd) [sp] ? 1 (even) [sp] ? 2 (odd) [sp] ? 3 (even) [sp] ? 4 (odd) [sp] ? 5 (even) address sequence in which order registers are saved (2) (1) finished saving registers in four operations. (3) (4) (1) sp contains even number [sp] (even) [sp] ? 1 (odd) [sp] ? 2 (even) [sp] ? 3 (odd) [sp] ? 4 (even) [sp] ? 5 (odd) note: 1. [sp] denotes the initial value of the sp when interrupt request is acknowledged. after registers are saved, the sp content is [sp] minus 4. address pc m stack flg l pc l sequence in which order registers are saved (2) saved simultaneously, all 16 bits (1) saved simultaneously, all 16 bits finished saving registers in two operations. pc m stack flg l pc l saved, 8 bits at a time flg h pc h flg h pc h
9. interrupts page 71 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 9.4.4 returning from an interrupt routine the flg register and pc in the state in which they were immediately before entering the interrupt se- quence are restored from the stack by executing the reit instruction at the end of the interrupt routine. thereafter the cpu returns to the program which was being executed before accepting the interrupt request. return the other registers saved by a program within the interrupt routine using the popm or similar instruction before executing the reit instruction. 9.5 interrupt priority if two or more interrupt requests are generated while executing one instruction, the interrupt request that has the highest priority is accepted. for maskable interrupts (peripheral functions), any desired priority level can be selected using bits ilvl2 to ilvl0. however, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by hardware, with the highest priority interrupt accepted. the watchdog timer and other special interrupts have their priority levels set in hardware. figure 9.9 shows the priorities of hardware interrupts. software interrupts are not affected by the interrupt priority. if an instruction is executed, control branches invariably to the interrupt routine. reset watchdog timer, oscillation stop and re-oscillation detection peripheral function single step address match high low nmi dbc figure 9.9 hardware interrupt priority 9.5.1 interrupt priority resolution circuit the interrupt priority resolution circuit is used to select the interrupt with the highest priority among those requested. figure 9.10 shows the circuit that judges the interrupt priority level.
9. interrupts page 72 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m timer b2 timer b0 timer a3 timer a1 timer b1 timer a4 timer a2 uart1 reception uart0 reception uart2 reception, ack2 a/d conversion dma1 uart 2 bus collision timer a0 uart1 transmission uart0 transmission uart2 transmission, nack2 key input interrupt dma0 ipl i flag int1 int2 int0 watchdog timer dbc nm i interrupt request accepted level 0 (initial value) priority level of each interrupt highest lowest priority of peripheral function interrupts (if priority levels are same ) ic/oc interrupt 1, i 2 c bus interface int3 ic/oc base timer, s cl /s da ic/oc interrupt 0 si/o4, int5 si/o3, int4 address match interrupt request level resolution output to clock generation circuit ( figure 7.1 ) oscillation stop and re-oscillation detection figure 9.10 interrupts priority select circuit
9. interrupts page 73 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m interrupt request cause select register bit name function bit symbol rw symbol address after reset ifsr 035f 16 00 16 ifsr0 b7 b6 b5 b4 b3 b2 b1 b0 int0 interrupt polarity switching bit 0 : si/o 3 1 : int4 0 : si/o 4 1 : int5 0 : one edge 1 : both edges 0 : one edge 1 : both edges 0 : one edge 1 : both edges 0 : one edge 1 : both edges 0 : one edge 1 : both edges int1 interrupt polarity switching bit int2 interrupt polarity switching bit int3 interrupt polarity switching bit int4 interrupt polarity switching bit int5 interrupt polarity switching bit 0 : one edge 1 : both edges interrupt request cause select bit interrupt request cause select bit ifsr1 ifsr2 ifsr3 ifsr4 ifsr5 ifsr6 ifsr7 rw rw rw rw rw rw rw rw (1) (1) (1) (1) (1) (1) (2) (2) notes: 1. when setting this bit to 1 (both edges), make sure the pol bit in registers int0ic to int5ic is set to 0 (falling edge). 2. when setting this bit to 0 (si/o3, si/o4), make sure the pol bit in registers s3ic and s4ic is set to 0 (falling edge). ______ 9.6 int interrupt _______ inti interrupt (i=0 to 5) is triggered by the edges of external inputs. the edge polarity is selected using the ifsri bit in the ifsr register. ________ the int5 input has an effective digital debounce function for a noise rejection. refer to " 18.6 digital ________ debounce function " for this detail. to use int5 interrupt to exit stop mode, set the p17ddr register to ff 16 before entering stop mode. ________ ________ ________ to use the int4 interrupt, set the ifsr6 bit in the ifsr register to 1 (int4). to use the int5 interrupt, set ________ the ifsr7 bit in the ifsr register to 1 (int5). after modifiying bit ifsr6 or ifsr7, clear the corresponding ir bit to 0 (interrupt not requested) before enabling the interrupt. figure 9.11 shows the ifsr registers. figure 9.11 ifsr register
9. interrupts page 74 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m interrupt control circuit kupic register key input interrupt request ki 3 ki 2 ki 1 ki 0 pu25 bit in the pur2 register pd10_7 bit in the pd10 register pull-up transistor pd10_7 bit in the pd10 register pd10_6 bit in the pd10 register pd10_5 bit in the pd10 register pd10_4 bit in the pd10 register pull-up transistor pull-up transistor pull-up transistor ______ 9.7 nmi interrupt _______ _______ an nmi interrupt request is generated when input on the nmi pin changes state from high to low, after the _______ ______ nmi interrupt was enabled by writing a 1 to bit 4 in the register pm2. the nmi interrupt is a non-maskable interrupt, once it is enabled. _______ the input level of this nmi interrupt input pin can be read by accessing the p8_5 bit in the p8 register. _______ nmi is disabled by default after reset (the pin is a gpio pin, p8 5 ) and can be enabled using bit 4 in the pm2 register. once enabled, it can only be disabled by a reset signal. _______ the nmi input has a digital debounce function for noise rejection. refer to " 19.6 digital debounce func- _______ tion " for details. to use nmi interrupt to exit stop mode, set the nddr register to ff 16 before entering stop mode. 9.8 key input interrupt a key input interrupt is generated when input on any of the p10 4 to p10 7 pins which has had bits pd10_7 to pd10_4 in the pd10 register set to 0 (= input) goes low. key input interrupts can be used for a key-on wakeup function to get the mcu to exit stop or wait modes. however, if you intend to use the key input interrupt, do not use p10 4 to p10 7 as analog input ports. figure 9.12 shows the block diagram of the key input interrupt. note, however, that while input on any pin which has had bits pd10_7 to pd10_4 set to 0 (= input mode) is pulled low, inputs on all other pins of the port are not detected as interrupts. figure 9.12 key input interrupt
9. interrupts page 75 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m ? 2-byte op-code instruction ? 1-byte op-code instructions which are followed: add.b:s #imm8,dest sub.b:s #imm8,dest and.b:s #imm8,dest or.b:s #imm8,dest mov.b:s #imm8,dest stz.b #imm8,dest stnz.b #imm8,dest stzx.b #imm81,#imm82,dest cmp.b:s #imm8,dest pushm src popm dest jmps #imm8 jsrs #imm8 mov.b:s #imm,dest (however, dest=a0 or a1) instructions other than the above instruction at the address indicated by the rmadi register value of the pc that is saved to the stack area the address indicated by the rmadi register +2 the address indicated by the rmadi register +1 value of the pc that is saved to the stack area : refer to ? saving registers ? . op-code is an abbreviation of operation code. it is a portion of instruction code. refer to chapter 4 instruction code/number of cycles in m16c/60, m16c/20 series software manual. op-code is shown as a bold-framed figure directly below the syntax. table 9.7 relationship between address match interrupt sources and associated registers address match interrupt sources address match interrupt enable bit address match interrupt register address match interrupt 0 aier0 rmad0 address match interrupt 1 aier1 rmad1 9.9 address match interrupt an address match interrupt request is generated immediately before executing the instruction at the ad- dress indicated by the rmadi register (i=0 to 1). set the start address of any instruction in the rmadi register. use bits aier1 and aier0 in the aier register to enable or disable the interrupt. note that the address match interrupt is unaffected by the i flag and ipl. for address match interrupts, the value of the pc that is saved to the stack area varies depending on the instruction being executed (refer to ? saving registers ? ). (the value of the pc that is saved to the stack area is not the correct return address.) therefore, follow one of the methods described below to return from the address match interrupt. ? rewrite the content of the stack and then use the reit instruction to return. ? restore the stack to its previous state before the interrupt request was accepted by using the pop or similar other instruction and then use a jump instruction to return. table 9.6 shows the value of the pc that is saved to the stack area when an address match interrupt request is accepted. figure 9.13 shows registers aier, rmad0, and rmad1. table 9.6 value of the pc that is saved to the stack area when an address match interrupt request is accepted.
9. interrupts page 76 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 9.13 aier register, rmad0 and rmad1 registers bit name bit symbol symbol address after reset aier 0009 16 xxxxxx00 2 address match interrupt enable register function rw address match interrupt 0 enable bit 0: interrupt disabled 1: interrupt enabled aier0 address match interrupt 1 enable bit aier1 symbol address after reset rmad0 0012 16 to 0010 16 x00000 16 rmad1 0016 16 to 0014 16 x00000 16 b7 b6 b5 b4 b3 b2 b1 b0 address setting register for address match interrupt function setting range address match interrupt register i (i = 0 to 1) 00000 16 to fffff 16 0: interrupt disabled 1: interrupt enabled b0 b7 b0 b3 (b19) (b16) b7 b0 (b15) (b8) b7 (b23) rw rw (b7-b2) rw rw nothing is assigned. if necessary, set to 0. when read, the content is undefined nothing is assigned. if necessary, set to 0. when read, the content is undefined
10. watchdog timer page 77 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 10.1 watchdog timer block diagram 10. watchdog timer the watchdog timer is the function of detecting when the program is out of control. therefore, we recom- mend using the watchdog timer to improve reliability of a system. the watchdog timer contains a 15-bit counter which counts down the clock derived by dividing the cpu clock using the prescaler. whether to generate a watchdog timer interrupt request or apply a watchdog timer reset as an operation to be per- formed when the watchdog timer underflows after reaching the terminal count can be selected using the pm12 bit in the pm1 register. the pm12 bit can only be set to 1 (reset). once this bit is set to 1, it cannot be set to 0 (watchdog timer interrupt) in a program. refer to 5.3 watchdog timer reset for the details of watchdog timer reset. when the main clock source is selected for cpu clock, on-chip oscillator clock, pll clock, the wdc7 bit in the wdc register value for prescaler can be chosen to be 16 or 128. if a sub-clock is selected for cpu clock, the prescaler is always 2 no matter how the wdc7 bit is set. the period of watchdog timer can be calculated as given below. the period of watchdog timer is, however, subject to an error due to the prescaler. for example, when cpu clock is set to 16 mhz and the divide-by-n value for the prescale ris set to 16, the watchdog timer period is approx. 32.8 ms. the watchdog timer is initialized by writing to the wdts register. the prescaler is initialized after reset. note that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is activated to start counting by writing to the wdts register. write the wdts register with shorter cycle than the watchdog timer cycle. set the wdts register also in the beginning of the watchdog timer interrupt routine. the watchdog timer and prescaler stop in stop mode and wait mode. when the modes are exited counting is resumed from the held value . figure 10.1 shows the block diagram of the watchdog timer. figure 10.2 shows the wdc register and the wdts register. with main clock source chosen for cpu clock, on-chip oscillator clock, pll clock watchdog timer period = with sub-clock chosen for cpu clock prescaler dividing (2) x watchdog timer count (32768) cpu clock watchdog timer period = prescaler dividing (16 or 128) x watchdog timer count (32768) cpu clock cpu clock write to wdts register pm12 = 0 watchdog timer set to 7fff 16 1/12 8 1/16 cm07 = 0 wdc7 = 1 cm07 = 0 wdc7 = 0 cm07 = 1 1/ 2 prescaler pm12 = 1 reset pm22 = 0 pm22 = 1 on-chip oscillator clock internal reset signal (low active) watchdog timer interrupt request
10. watchdog timer page 78 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 10.2 wdc register and wdts register 10.1 count source protective mode in this mode, a on-chip oscillator clock is used for the watchdog timer count source. the watchdog timer can be kept being clocked even when cpu clock stops as a result of run-away. before this mode can be used, the following register settings are required: (1) set the prc1 bit in the prcr register to 1 (enable writes to pm1 and pm2 registers). (2) set the pm12 bit in the pm1 register to 1 (reset when the watchdog timer underflows). (3) set the pm22 bit in the pm2 register to 1 (on-chip oscillator clock used for the watchdog timer count source). (4) set the prc1 bit in the prcr register to 0 (disable writes to pm1 and pm2 registers). (5) write to the wdts register (watchdog timer starts counting). setting the pm22 bit to 1 results in the following conditions ? the on-chip oscillator continues oscillating even if the cm21 bit in the cm2 register is set to "0" (main clock or pll clock) (system clock of count source selected by the cm21 bit is valid) ? the on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer count source. ? the cm10 bit in the cm1 register is disabled against write. (writing a 1 has no effect, nor is stop mode entered.) ? the watchdog timer does not stop when in wait mode. watchdog timer period = watchdog timer count (32768) on-chip oscillator clock watchdog timer control register symbol address after reset wdc 000f 16 00xxxxxx 2 function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 high-order bit of watchdog timer wdc7 bit name prescaler select bit 0 : divided by 16 1 : divided by 128 reserved bit set to 0 0 ro rw rw rw (b4-b0) (b6) 0 (b5) reserved bit set to 0 watchdog timer start register symbol address after reset wdts 000e 16 undefined wo b7 b0 function the watchdog timer is initialized and starts counting after a write instruction to this register. the watchdog timer value is always initialized to 7fff 16 regardless of whatever value is written. rw
11. dmac page 79 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 11. dmac note do not use si/o4 interrupt request as a dma request in the 64-pin package. the dmac (direct memory access controller) allows data to be transferred without the cpu intervention. two dmac channels are included. each time a dma request occurs, the dmac transfers one (8 or 16-bit) data from the source address to the destination address. the dmac uses the same data bus as used by the cpu. because the dmac has higher priority of bus control than the cpu and because it makes use of a cycle steal method, it can transfer one word (16 bits) or one byte (8 bits) of data within a very short time after a dma request is generated. figure 11.1 shows the block diagram of the dmac. table 11.1 shows the dmac specifications. figures 11.2 to 11.4 show the dmac-related registers. figure 11.1 dmac block diagram a dma request is generated by setting the dsr bit in the dmisl register (i = 0,1), as well as by an interrupt request which is generated by any function specified by bits dms, dsel3, dsel2, dsel1, and dsel0 in the dmisl register. however, unlike in the case of interrupt requests, dma requests are not affected by the i flag and the interrupt control register, so that even when interrupt requests are disabled and no interrupt request can be accepted, dma requests are always accepted. furthermore, because the dmac does not affect interrupts, the ir bit in the interrupt control register does not change state due to a dma transfer. a data transfer is initiated each time a dma request is generated when the dmae bit in the dmicon register is set to 1 (dma enabled). however, if the cycle in which a dma request is generated is faster than the dma transfer cycle, the number of transfer requests generated and the number of times data is trans- ferred may not match. for details, refer to ? dma requests ? . data bus lo w- o r de r bits dma latch high-order bits dma latch low-order bits dma0 source pointer sar0(20) dma0 destination pointer dar0 (20) dma0 forward address pointer (20) (1) d ata b us high -or d er bi ts address bus dma1 destination pointer dar1 (20) dma1 source pointer sar1 (20) dma1 forward address pointer (20) (1) dma0 transfer counter reload register tcr0 (16) dma0 transfer counter tcr0 (16) dma1 transfer counter reload register tcr1 (16) dma1 transfer counter tcr1 (16) (addresses 0029 16 , 0028 16 ) (addresses 0039 16 , 0038 16 ) (addresses 0022 16 to 0020 16 ) (addresses 0026 16 to 0024 16 ) (addresses 0032 16 to 0030 16 ) (addresses 0036 16 to 0034 16 ) note: 1. pointer is incremented by a dma request.
11. dmac page 80 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m item specification no. of channels 2 (cycle steal method) transfer memory space ? from any address in the 1m bytes space to a fixed address ? from a fixed address to any address in the 1m bytes space ? from a fixed address to a fixed address maximum no. of bytes transferred 128k bytes (with 16-bit transfers) or 64k bytes (with 8-bit transfers) dma request factors (1, 2) ________ ________ falling edge of int0 or int1 ________ ________ both edge of int0 or int1 timer a0 to timer a4 interrupt requests timer b0 to timer b2 interrupt requests uart0 transfer, uart0 reception interrupt requests uart1 transfer, uart1 reception interrupt requests uart2 transfer, uart2 reception interrupt requests si/o3, si/o4 interrupt requests a/d conversion interrupt requests timer s(ic/oc) requests software triggers channel priority dma0 > dma1 (dma0 takes precedence) transfer unit 8 bits or 16 bits transfer address direction forward or fixed (the source and destination addresses cannot both be in the forward direction) transfer mode single transfer transfer is completed when the dmai transfer counter (i = 0,1) underflows after reaching the terminal count repeat transfer when the dmai transfer counter underflows, it is reloaded with the value of the dmai transfer counter reload register and a dma transfer is con tinued with it dma interrupt request generation timing when the dmai transfer counter underflowed dma startup data transfer is initiated each time a dma request is generated when the dmae bit in the dmaicon register = 1 (enabled) dma shutdown single transfer ? when the dmae bit is set to 0 (disabled) ? after the dmai transfer counter underflows repeat transfer when the dmae bit is set to 0 (disabled) when a data transfer is started after setting the dmae bit to 1 (en abled), the forward address pointer is reloaded with the value of the sari or the dari pointer whichever is specified to be in the forward direction and the dmai transfer counter is reloaded with the value of the dmai transfer counter reload register table 11.1 dmac specifications notes: 1. dma transfer is not effective to any interrupt. dma transfer is affected neither by the i flag nor by the interrupt control register. 2. the selectable causes of dma requests differ with each channel. 3. make sure that no dmac-related registers (addresses 0020 16 to 003f 16 ) are accessed by the dmac. reload timing for forward ad- dress pointer and transfer counter
11. dmac page 81 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 11.2 dm0sl register dma0 request cause select register symbol address after reset dm0sl 03b8 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 dma request cause select bit dsel0 rw dsel1 dsel2 dsel3 dsr bit name dms rw rw rw rw rw rw (b5-b4) refer to note (1) a dma request is generated by setting this bit to 1 when the dms bit is 0 (basic cause) and bits dsel3 to dsel0 are 0001 2 (software trigger). the value of this bit when read is 0 software dma request bit nothing is assigned. when write, set to 0. when read, their content are 0 dma request cause expansion select bit 0: basic cause of request 1: extended cause of request note: 1. the causes of dma0 requests can be selected by a combination of dms bit and bits dsel3 to dsel0 in the manner described below. dsel3 to dsel0 dms=0(basic cause of request) dms=1(extended cause of request) 0 0 0 0 2 falling edge of int0 pin ic/oc base timer 0 0 0 1 2 software trigger ? 0 0 1 0 2 timer a0 ic/oc channel 0 0 0 1 1 2 timer a1 ic/oc channel 1 0 1 0 0 2 timer a2 ? 0 1 0 1 2 timer a3 ? 0 1 1 0 2 timer a4 two edges of int0 pin 0 1 1 1 2 timer b0 ? 1 0 0 0 2 timer b1 ? 1 0 0 1 2 timer b2 ? 1 0 1 0 2 uart0 transmit ic/oc channel 2 1 0 1 1 2 uart0 receive ic/oc channel 3 1 1 0 0 2 uart2 transmit ic/oc channel 4 1 1 0 1 2 uart2 receive ic/oc channel 5 1 1 1 0 2 a/d conversion ic/oc channel 6 1 1 1 1 2 uart1 transmit ic/oc channel 7
11. dmac page 82 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 11.3 dm1sl register, dm0con register, and dm1con registers dmai control register (i=0,1) symbol address after reset dm0con 002c 16 00000x00 2 dm1con 003c 16 00000x00 2 bit name function bit symbol transfer unit bit select bit b7 b6 b5 b4 b3 b2 b1 b0 0: 16 bits 1: 8 bits dmbit dmasl dmas dmae repeat transfer mode select bit 0: single transfer 1: repeat transfer dma request bit 0: dma not requested 1: dma requested 0: disabled 1: enabled 0: fixed 1: forward dma enable bit source address direction select bit (2) destination address direction select bit (2) 0: fixed 1: forward dsd dad nothing is assigned. if necessary, set to 0. when read, their contents are 0 notes: 1. the dmas bit can be set to 0 by writing 0 by program (this bit remains unchanged even if 1 is written). 2. at least one of bits dad and dsd must be set to 0 (address direction fixed). (1) dma1 request cause select register symbol address after reset dm1sl 03ba 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 dma request cause select bit dsel0 rw dsel1 dsel2 dsel3 software dma request bit dsr dsel3 to dsel0 dms=0(basic cause of request ) dms=1(extended cause of request ) 0 0 0 0 2 falling edge of int1 pin ic/oc base timer 0 0 0 1 2 software trigger ? 0 0 1 0 2 timer a0 ic/oc channel 0 0 0 1 1 2 timer a1 ic/oc channel 1 0 1 0 0 2 timer a2 ? 0 1 0 1 2 timer a3 si/o3 0 1 1 0 2 timer a4 si/o4 0 1 1 1 2 timer b0 two edges of int1 1 0 0 0 2 timer b1 ? 1 0 0 1 2 timer b2 ? 1 0 1 0 2 uart0 transmit ic/oc channel 2 1 0 1 1 2 uart0 receive ic/oc channel 3 1 1 0 0 2 uart2 transmit ic/oc channel 4 1 1 0 1 2 uart2 receive/ack2 ic/oc channel 5 1 1 1 0 2 a/d conversion ic/oc channel 6 1 1 1 1 2 uart1 receive ic/oc channel 7 bit name dma request cause expansion select bit dms rw rw rw rw rw rw (b5-b4) rw rw rw rw rw rw rw (b7-b6) notes: 1. the causes of dma1 requests can be selected by a combination of dms bit and bits dsel3 to dsel0 in the manner described below. nothing is assigned. if necessary, set to 0. when read, their contents are 0 a dma request is generated by setting this bit to 1 when the dms bit is 0 (basic cause) and the dsel3 to dsel0 bits are 0001 2 (software trigger). the value of this bit when read is 0 0: basic cause of request 1: extended cause of request refer to note (1)
11. dmac page 83 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 11.4 sar0, sar1, dar0, dar1, tcr0, and tcr1 registers b7 b0 b7 b0 (b8) (b15) function set the transfer count minus 1. the written value is stored in the dmai transfer counter reload register, and when the dmae bit in the dmicon register is set to 1 (dma enabled) or the dmai transfer counter underflows when the dmasl bit in the dmicon register is 1 (repeat transfer), the value of the dmai transfer counter reload register is transferred to the dmai transfer counter. when read, the dmai transfer counter is read symbol address after reset tcr0 0029 16 , 0028 16 undefined tcr1 0039 16 , 0038 16 undefined dmai transfer counter (i = 0, 1 ) setting range 0000 16 to ffff 16 b7 (b23) b3 b0 b7 b0 b7 b0 (b8) (b16)(b15) (b19) function rw set the source address of transfer symbol address after reset sar0 0022 16 to 0020 16 undefined sar1 0032 16 to 0030 16 undefined dmai source pointer (i = 0, 1) (1) setting range 00000 16 to fffff 16 nothing is assigned. if necessary, set 0. when read, the contents are 0 symbol address after reset dar0 0026 16 to 0024 16 undefined dar1 0036 16 to 0034 16 undefined b3 b0 b7 b0 b7 b0 (b8) (b15) (b16) (b19) function set the destination address of transfer dmai destination pointer (i = 0, 1) (1) setting range 00000 16 to fffff 16 b7 (b23) rw rw rw rw rw note: 1. if the dsd bit in the dmicon register is 0 (fixed), this register can only be written to when the dmae bit in the dmicon register is set to 0 (dma disabled). if the dsd bit is set to 1 (forward direction), this register can be written to at any time. if the dsd bit is set to 1 and the dmae bit is set to 1 (dma enabled), the dmai forward address pointer can be read from this register. otherwise, the value written to it can be read. nothing is assigned. if necessary, set 0. when read, the contents are 0 note: 1. if the dad bit in the dmicon register is 0 (fixed), this register can only be written to when the dmae bit in the dmicon register is set to 0 (dma disabled). if the dad bit is set to 1 (forward direction), this register can be written to at any time. if the dad bit is set to 1 and the dmae bit is set to 1 (dma enabled), the dmai forward address pointer can be read from this register. otherwise, the value written to it can be read.
11. dmac page 84 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 11.1 transfer cycles the transfer cycle consists of a memory or sfr read (source read) bus cycle and a write (destination write) bus cycle. the number of read and write bus cycles is affected by the source and destination addresses of transfer. furthermore, the bus cycle itself is extended by a software wait. 11.1.1 effect of source and destination addresses if the transfer unit is 16 bits and the source address of transfer begins with an odd address, the source read cycle consists of one more bus cycle than when the source address of transfer begins with an even address. similarly, if the transfer unit is 16 bits and the destination address of transfer begins with an odd address, the destination write cycle consists of one more bus cycle than when the destination address of transfer begins with an even address. 11.1.2 effect of software wait for memory or sfr accesses in which one or more software wait states are inserted, the number of bus cycles required for that access increases by an amount equal to software wait states. figure 11.5 shows the example of the cycles for a source read. for convenience, the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown. in reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. when calculating transfer cycles, take into consideration each condition for the source read and the destination write cycle, respectively. for example, when data is transferred in 16 bit units and when both the source address and destination address are an odd address ((2) in figure 11.5 ), two source read bus cycles and two destination write bus cycles are required.
11. dmac page 85 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 11.5 transfer cycles for source read cpu clock address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle (1) when the transfer unit is 8 or 16 bits and the source of transfer is an even address address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle (3) when the source read cycle under condition (1) has one wait state inserted address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle source + 1 source + 1 (2) when the transfer unit is 16 bits and the source address of transfer is an odd address. address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle source + 1 source + 1 (4) when the source read cycle under condition (2) has one wait state inserted note: 1. the same timing changes occur with the respective conditions at the destination as at the source. cpu clock cpu clock cpu clock
11. dmac page 86 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m table 11.2 dma transfer cycles table 11.3 coefficient j, k 11.2 dma transfer cycles any combination of even or odd transfer read and write adresses is possible. table 11.2 shows the number of dma transfer cycles. table 11.3 shows the coefficient j, k. the number of dmac transfer cycles can be calculated as follows: no. of transfer cycles per transfer unit = no. of read cycles x j + no. of write cycles x k transfer unit access address no. of read cycles no. of write cycles 8-bit transfers even 1 1 (dmbit= ? 1 ? ) odd 1 1 16-bit transfers even 1 1 (dmbit= ? 0 ? ) odd 2 2 internal area internal rom, ram sfr no wait with wait 1 1 2 2 2 2 j k 3 3 1 wait 2 wait (1) (1) note: 1. depends on the set value of pm20 bit in pm2 register
11. dmac page 87 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 11.3 dma enable when a data transfer starts after setting the dmae bit in the dmicon register (i = 0, 1) to 1 (enabled), the dmac operates as follows: (a) reload the forward address pointer with the sari register value when the dsd bit in dmicon register is 1 (forward) or the dari register value when the dad bit in the dmicon register is 1 (forward). (b) reload the dmai transfer counter with the dmai transfer counter reload register value. if the dmae bit is set to 1 again while it remains set, the dmac performs the above operation. however, if a dma request may occur simultaneously when the dmae bit is being written, follow the steps below. (1) write 1 to bits dmae and dmas in dmicon register simultaneously. (2) make sure that the dmai is in an initial state as described above (a) and (b) by program. if the dmai is not in an initial state, the above steps should be repeated. 11.4 dma request the dmac can generate a dma request as triggered by the cause of request that is selected with the dms bit and bits dsel3 to dsel0 in the dmisl register (i = 0, 1) on either channel. table 11.4 shows the timing at which the dmas bit changes state. whenever a dma request is generated, the dmas bit is set to 1 (dma requested) regardless of whether or not the dmae bit is set. if the dmae bit was set to 1 (enabled) when this occurred, the dmas bit is set to 0 (dma not requested) immediately before a data transfer starts. this bit cannot be set to 1 by program (it can only be set to 0). the dmas bit may be set to 1 when the dms or the dsel3 to dsel0 bits change state. therefore, always be sure to set the dmas bit to 0 after changing the dms or the dsel3 to dsel0 bits. because if the dmae bit is set to 1, a data transfer starts immediately after a dma request is generated, the dmas bit in almost all cases is 0 when read by program. read the dmae bit to determine whether the dmac is enabled. table 11.4 timing at which the dmas bit changes state dma factor software trigger peripheral function timing at which the bit is set to 1 timing at which the bit is set to 0 dmas bit in the dmicon register when the dsr bit in the dmisl register is set to 1 when the interrupt control register for the peripheral function that is selected by bits dsel3 to dsel0 and the dms bit in the dmisl register has its ir bit set to 1 ? immediately before a data transfer starts ? when set by writing 0 by program
11. dmac page 88 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 11.5 channel priority and dma transfer timing if both dma0 and dma1 are enabled and dma transfer request signals from dma0 and dma1 are de- tected active in the same sampling period (one period from a falling edge to the next falling edge of cpu clock), the dmas bit on each channel is set to 1 (dma requested) at the same time. in this case, the dma requests are arbitrated according to the channel priority, dma0 > dma1. the following describes dmac operation when dma0 and dma1 requests are detected active in the same sampling period. figure 11.6 shows an example of dma transfer effected by external factors. dma0 request having priority is received first to start a transfer when a dma0 request and dma1 request are generated simultanelously. after one dma0 transfer is completed, a bus arbitration is returned to the cpu. when the cpu has completed one bus access, a dma1 transfer starts. after one dma1 transfer is completed, the bus arbitration is again returned to the cpu. in addition, dma requsts cannot be counted up since each channel has one dmas bit. therefore, when dma requests, as dma1 in figure 11.6 occurs more than one time, the dams bit is set to 0 as soon as getting the bus arbitration. the bus arbitration is returned to the cpu when one transfer is completed. figure 11.6 dma transfer by external factors dma0 dma1 dma0 request bit dma1 request bit cpu int0 int1 obtainment of the bus right an example where dma requests for external causes are detected active at the same cpu clock
12. timer page 89 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 12. timer eight 16-bit timers, each capable of operating independently of the others, can be classified by function as either timer a (five) and timer b (three). the count source for each timer acts as a clock, to control such timer operations as counting, reloading, etc. figures 12.1 and 12.2 show block diagrams of timer a and timer b configuration, respectively. figure 12.1 timer a configuration ? timer mode ? one-shot timer mode ? pulse width measuring (pwm) mode ? timer mode ? one-shot timer mode ? pwm mode ? timer mode ? one-shot timer mode ? pwm mode ? timer mode ? one-shot timer mode ? pwm mode ? timer mode ? one-shot timer mode ? pwm mode ? event counter mode ? event counter mode ? event counter mode ? event counter mode ? event counter mode ta0 in ta1 in ta2 in ta3 in ta4 in timer a0 timer a1 timer a2 timer a3 timer a4 f 8 f 32 f c32 timer a0 interrupt timer a1 interrupt timer a2 interrupt timer a3 interrupt timer a4 interrupt noise filter noise filter noise filter noise filter noise filter 1/32 f c32 1/8 1/4 f 1 or f 2 f 8 f 32 ? main clock ? pll clock ? on-chip oscillator clock x cin set the cpsr bit in the cpsrf register to 1 (prescaler reset) reset clock prescaler timer b2 overflow or underflow 1/2 f 1 f 2 pclk0 bit = 0 pclk0 bit = 1 f 1 or f 2
12. timer page 90 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 12.2. timer b configuration ? event counter mode ? event counter mode ? event counter mode ? timer mode ? pulse width measuring mode, pulse period measuring mode ? timer mode ? pulse width measuring mode, pulse period measuring mode ? timer mode ? pulse width measuring mode, pulse period measuring mode tb0 in tb1 in tb2 in timer b0 timer b1 timer b2 f 8 f 32 f c32 timer b0 interrupt noise filter noise filter noise filter 1/32 f c32 x cin reset clock prescaler timer b2 overflow or underflow ( to timer a count source) timer b1 interrupt timer b2 interrupt 1/ 8 1/ 4 f 8 f 32 1/ 2 f 1 or f 2 ? main clock ? pll clock ? on-chip oscillator clock set the cpsr bit in the cpsrf register to 1 (prescaler reset) f 1 f 2 pclk0 bit = 0 pclk0 bit = 1 f 1 or f 2
12. timer a page 91 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 12.1 timer a figure 12.3 shows a block diagram of the timer a. figures 12.4 to 12.6 show registers related to the timer a. the timer a supports the following four modes. except in event counter mode, timers a0 to a4 all have the same function. use bits tmod1 to tmod0 in the taimr register (i = 0 to 4) to select the desired mode. ? timer mode: the timer counts an internal count source. ? event counter mode: the timer counts pulses from an external device or overflows and underflows of other timers. ? one-shot timer mode: the timer outputs a pulse only once before it reaches the minimum count 0000 16 . ? pulse width modulation (pwm) mode: the timer outputs pulses in a given width successively. figure 12.4 ta0mr to ta4mr registers figure 12.3 timer a block diagram tabsr register increment/decrement tai addresses taj tak timer a0 0387 16 - 0386 16 timer a4 timer a1 timer a1 0389 16 - 0388 16 timer a0 timer a2 timer a2 038b 16 - 038a 16 timer a1 timer a3 timer a3 038d 16 - 038c 16 timer a2 timer a4 timer a4 038f 16 - 038e 16 timer a3 timer a 0 always counts down except in event counter mode reload register counter low-order 8 bits high-order 8 bits clock source selection ? timer (gate function) ? timer ? one shot ? pwm f 1 or f 2 f 8 f 32 tai in (i = 0 to 4) tb2 overflow ? event counter f c32 clock selection taj overflow (j = i ? 1. however, j = 4 when i = 0) pulse output toggle flip-flop tai out (i = 0 to 4 ) data bus low-order bits data bus high-order bits udf register decrement tak overflow (k = i + 1. however, k = 0 when i = 4) polarity selection to external trigger circuit (1) (1) note: 1. overflow or underflow clock selection timer ai mode register (i=0 to 4) symbol address after reset ta0mr to ta4mr 0396 16 to 039a 16 00 16 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : one-shot timer mode 1 1 : pulse width modulation (pwm) mode b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 function varies with each operation mode count source select bit operation mode select bi t rw rw rw rw rw rw rw rw function varies with each operation mode
12. timer a page 92 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 12.5 ta0 to ta4 registers, tabsr register, and udf register symbol address after reset ta0 0387 16 , 0386 16 undefined ta1 0389 16 , 0388 16 undefined ta2 038b 16 , 038a 16 undefined ta3 038d 16 , 038c 16 undefined ta4 038f 16 , 038e 16 undefined b7 b0 b7 b0 (b15) (b8) timer ai register (i= 0 to 4) (1) function setting range timer mode event counter mode one-shot timer mode mode rw wo rw rw wo wo symbol address after reset tabsr 0380 16 00 16 count start flag b7 b6 b5 b4 b3 b2 b1 b0 notes: 1. the register must be accessed in 16 bit units. 2. if the tai register is set to 0000 16 , the counter does not work and timer ai interrupt requests are not generated either. furthermore, if ? pulse output ? is selected, no pulses are output from the taiout pin. 3. if the tai register is set to 0000 16 , the pulse width modulator does not work, the output level on the taiout pin remains low, and timer ai interrupt requests are not generated either. the same applies when the 8 high-order bits of the timer tai register are set to 0000 16 while operating as an 8-bit pulse width modulator. 4. use the mov instruction to write to the tai register. 5. the timer counts pulses from an external device or overflows or underflows in other timers. divide the count source by n + 1 where n = set value 0000 16 to fffe 16 (3, 4) 0000 16 to ffff 16 0000 16 to ffff 16 0000 16 to ffff 16 (2, 4) 00 16 to fe 16 (high-order address) 00 16 to ff 16 (low-order address) (3, 4) modify the pulse width as follows: pwm period: (2 8 ? 1) x (m + 1)/ fj high level pwm pulse width: (m + 1)n / fj where n = high-order address set value, m = low-order address set value, fj = count source frequency modify the pulse width as follows: pwm period: (2 16 ? 1) / fj high level pwm pulse width: n / fj where n = set value, fj = count source frequency divide the count source by n where n = set value and cause the timer to stop divide the count source by ffff 16 ? n + 1 where n = set value when counting up or by n + 1 when counting down (5) pulse width modulation mode (16-bit pwm) pulse width modulation mode (8-bit pwm) bit name function bit symbol 0 : stops counting 1 : starts counting timer b2 count start flag tb2s timer b1 count start flag tb1s timer b0 count start flag tb0s timer a4 count start flag ta4s timer a3 count start flag ta3s timer a2 count start flag ta2s timer a1 count start flag ta1s timer a0 count start flag ta0s rw rw rw rw rw rw rw rw rw symbol address after reset udf 0384 16 00 16 up/down flag (1) b7 b6 b5 b4 b3 b2 b1 b0 bit name function bit symbol 0: down count 1: up count ta4p ta3p ta2p timer a4 up/down flag ta4ud timer a3 up/down flag ta3ud timer a2 up/down flag ta2ud timer a1 up/down flag ta1ud timer a0 up/down flag ta0ud rw rw rw rw rw rw wo wo wo enabled by setting the mr2 bit in the taimr register to 0 (= switching source in udf register) during event counter mode 0: two-phase pulse signal processing disabled 1: two-phase pulse signal processing enabled (2, 3) timer a2 two-phase pulse signal processing select bit timer a3 two-phase pulse signal processing select bit timer a4 two-phase pulse signal processing select bit notes: 1. use mov instruction to write to this register. 2. make sure the port direction bits for the ta2 in to ta4i n and ta2 out to ta4 out pins are set to 0 input mode. 3. when the two-phase pulse signal processing function is not used, set the corresponding bit to 0.
12. timer a page 93 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 12.6 onsf register, trgsr register, and cpsrf register symbol address after reset cpsrf 0381 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 clock prescaler reset flag setting this bit to 1 initializes the prescaler for the timekeeping clock. (when read, its content is 0 ) cpsr nothing is assigned. if necessary, set to 0. when read, their contents are undefined ta1tgl symbol address after reset trgsr 0383 16 00 16 timer a1 event/trigger select bit 0 0: input on ta1 in is selected (1) 0 1: tb2 is selected (2) 1 0: ta0 is selected (2) 1 1: ta2 is selected (2) trigger select register bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0: input on ta2 in is selected (1) 0 1: tb2 is selected (2) 1 0: ta1 is selected (2) 1 1: ta3 is selected (2) 0 0: input on ta3 in is selected (1) 0 1: tb2 is selected (2) 1 0: ta2 is selected (2) 1 1: ta4 is selected (2) 0 0: input on ta4 in is selected (1) 0 1: tb2 is selected (2) 1 0: ta3 is selected (2) 1 1: ta0 is selected (2) timer a2 event/trigger select bit timer a3 event/trigger select bit timer a4 event/trigger select bit ta1tgh ta2tgl ta2tgh ta3tgl ta3tgh ta4tgl ta4tg h b1 b0 b3 b2 b5 b4 b7 b6 ta1os ta2os ta0os one-shot start flag symbol address after reset onsf 0382 16 00 16 timer a0 one-shot start flag timer a1 one-shot start flag timer a2 one-shot start flag timer a3 one-shot start flag timer a4 one-shot start flag ta3os ta4os bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 ta0tg l ta0tgh 0 0: input on ta0 in is selected (1) 0 1: tb2 overflow is selected (2) 1 0: ta4 overflow is selected (2) 1 1: ta1 overflow is selected (2 ) timer a0 event/trigger select bit b7 b6 rw the timer starts counting by setting this bit to 1 while bits tmod1 and tmod0 in the taimr register (i = 0 to 4) = 10 2 (= one-shot timer mode) and the mr2 bit in the taimr register = 0 (=taios bit enabled). when read, its content is 0 z-phase input enable bit tazie 0: z-phase input disabled 1: z-phase input enabled rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw (b6-b0) notes: 1. make sure the pd7_1 bit in the pd7 register is set to 0 (input mode). 2. overflow or underflow. notes: 1. make sure the port direction bits for the ta1 in to ta4 in pins are set to 0 ( input mode). 2. overflow or underflow.
12. timer a page 94 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r item specification count source f 1 , f 2 , f 8 , f 32 , f c32 count operation ? decrement ? when the timer underflows, it reloads the reload register contents and continues counting divide ratio 1/(n+1) n: set value of tai register (i= 0 to 4) 0000 16 to ffff 16 count start condition set tais bit in the tabsr register to 1 (start counting) count stop condition set tais bit to 0 (stop counting) interrupt request generation timing timer underflow tai in pin function i/o port or gate input tai out pin function i/o port or pulse output read from timer count value can be read by reading tai register write to timer ? when not counting and until the 1st count source is input after counting start value written to tai register is written to both reload register and counter ? when counting (after 1st count source input) value written to tai register is written to only reload register (transferred to counter when reloaded next) select function ? gate function counting can be started and stopped by an input signal to tai in pin ? pulse output function whenever the timer underflows, the output polarity of tai out pin is inverted. when not counting, the pin outputs a low. 12.1.1 timer mode in timer mode, the timer counts a count source generated internally (see table 12.1 ). figure 12.7 shows taimr register in timer mode. table 12.1 specifications in timer mode figure 12.7 timer ai mode register in timer mode note: 1. the port direction bit for the tai in pin must be set to 0 ( input mode). timer ai mode register (i=0 to 4) symbol address after reset ta0mr to ta4mr 0396 16 to 039a 16 00 16 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 0: timer mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit 0: pulse is not output (ta iout pin is a normal port pin) 1: pulse is output (ta iout pin is a pulse output pin ) gate function select bit 0 0: gate function not available 0 1: (tai in pin functions as i/o port) 1 0: counts while input on the tai in pin is low (1) 1 1: counts while input on the tai in pin is high (1) b4 b3 mr2 mr1 mr3 set to 0 in timer mode 0 0: f 1 or f 2 0 1: f 8 1 0: f 32 1 1: f c32 b7 b6 tck1 tck0 count source select bi t 00 0 rw rw rw rw rw rw rw rw }
12. timer a page 95 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r item specification count source ? external signals input to tai in pin (i=0 to 4) (effective edge can be selected in program) ? timer b2 overflows or underflows, timer aj (j=i-1, except j=4 if i=0) overflows or underflows, timer ak (k=i+1, except k=0 if i=4) overflows or underflows count operation ? increment or decrement can be selected by external signal or program ? when the timer overflows or underflows, it reloads the reload register con- tents and continues counting. when operating in free-running mode, the timer continues counting without reloading. divided ratio 1/ (ffff 16 - n + 1) for increment 1/ (n + 1) for down-count n : set value of tai register 0000 16 to ffff 16 count start condition set tais bit in the tabsr register to 1 (start counting) count stop condition set tais bit to 0 (stop counting) interrupt request generation timing timer overflow or underflow tai in pin function i/o port or count source input tai out pin function i/o port, pulse output, or up/down-count select input read from timer count value can be read by reading tai register write to timer ? when not counting and until the 1st count source is input after counting start value written to tai register is written to both reload register and counter ? when counting (after 1st count source input) value written to tai register is written to only reload register (transferred to counter when reloaded next) select function ? free-run count function even when the timer overflows or underflows, the reload register content is not reloaded to it ? pulse output function whenever the timer underflows or underflows, the output polarity of tai out pin is inverted . when not counting, the pin outputs a low. 12.1.2 event counter mode in event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. timers a2, a3, and a4 can count two-phase external signals. table 12.2 lists specifica- tions in event counter mode (when not processing two-phase pulse signal). table 12.3 lists specifica- tions in event counter mode (when processing two-phase pulse signal with the timers a2, a3 and a4). figure 12.8 shows taimr register in event counter mode (when not processing two-phase pulse signal). figure 12.9 shows ta2mr to ta4mr registers in event counter mode (when processing two-phase pulse signal with the timers a2, a3 and a4). table 12.2 specifications in event counter mode (when not processing two-phase pulse signal)
12. timer a page 96 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 12.8 taimr register in event counter mode (when not using two-phase pulse signal processing) symbol address after reset ta0mr to ta4mr 0396 16 to 039a 16 00 16 w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode (1) b1 b0 tmod0 mr0 0: pulse is not output (ta iout pin functions as i/o port) 1: pulse is output (tai out pin functions as pulse output pin) mr2 mr1 mr3 set to 0 in event counter mode tck0 count operation type select bi t 01 0 0: counts external signal's falling edge 1: counts external signal's rising edge up/down switching cause select bit 0: reload type 1: free-run type bit symbol bit name function rw tck1 can be 0 or 1 when not using two-phase pulse signal processing tmod1 timer ai mode register (i=0 to 4) (when not using two-phase pulse signal processing) rw rw rw rw rw rw rw rw notes: 1. during event counter mode, the count source can be selected using registers onsf and trgsr. 2. effective when bits taitgh and taitgl in the onsf or trgsr register are 00 2 (tai in pin input). 3. decrement when input on tai out pin is low or increment when input on that pin is high. the port direction bit for tai out pin must be set to 0 (input mode). pulse output function select bit count polarityselect bit (2) 0: udf register 1: input signal to ta iout pin (3)
12. timer a page 97 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r item specification count source ? two-phase pulse signals input to tai in or tai out pins (i = 2 to 4) count operation ? increment or down-count can be selected by two-phase pulse signal ? when the timer overflows or underflows, it reloads the reload register con- tents and continues counting. when operating in free-running mode, the timer continues counting without reloading. divide ratio 1/ (ffff 16 - n + 1) for increment 1/ (n + 1) for down-count n : set value of tai register 0000 16 to ffff 16 count start condition set tais bit in the tabsr register to 1 (start counting) count stop condition set tais bit to 0 (stop counting) interrupt request generation timing timer overflow or underflow tai in pin function two-phase pulse input tai out pin function two-phase pulse input read from timer count value can be read by reading timer a2, a3 or a4 register write to timer ? when not counting and until the 1st count source is input after counting start value written to tai register is written to both reload register and counter ? when counting (after 1st count source input) value written to tai register is written to reload register (transferred to counter when reloaded next) select function (note) ? normal processing operation (timer a2 and timer a3) the timer counts up rising edges or counts down falling edges on taj in pin when input signals on taj out pin is ? h ? . ? multiply-by-4 processing operation (timer a3 and timer a4) if the phase relationship is such that tak in (k=3, 4) pin goes ? h ? when the input signal on tak out pin is ? h ? , the timer counts up rising and falling edges on tak out and tak in pins. if the phase relationship is such that tak in pin goes ? l ? when the input signal on tak out pin is ? h ? , the timer counts down rising and falling edges on tak out and tak in pins. table 12.3 specifications in event counter mode (when processing two-phase pulse signal with timers a2, a3 and a4) ? counter initialization by z-phase input (timer a3) the timer count value is initialized to 0 by z-phase input. note: 1. only timer a3 is selectable. timer a2 is fixed to normal processing operation, and timer a4 is fixed to multiply-by-4 processing operation. taj out increment increment increment decrement decrement decrement taj in (j=2,3) tak out tak in (k=3,4) increment all edges increment all edges decrement all edges decrement all edges
12. timer a page 98 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 12.9 ta2mr to ta4mr registers in event counter mode (when using two-phase pulse signal processing with timer a2, a3 or a4) timer ai mode register (i=2 to 4) (when using two-phase pulse signal processing) symbol address after reset ta2mr to ta4mr 0398 16 to 039a 16 00 16 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1: event counter mode b1 b0 tmod1 tmod0 mr0 to use two-phase pulse signal processing, set this bit to 0 mr2 mr1 mr3 tck1 tck0 01 0 bit name functio n rw count operation type select bit two-phase pulse signal processing operation select bit (1)(2) 0: reload type 1: free-run type 0: normal processing operation 1: multiply-by-4 processing operation 0 0 1 to use two-phase pulse signal processing, set this bit to 0 to use two-phase pulse signal processing, set this bit to 1 to use two-phase pulse signal processing, set this bit to 0 bit symbol rw rw rw rw rw rw rw rw notes: 1. the tck1 bit is valid for timer a3 mode register. no matter how this bit is set, timers a2 and a4 always operate in normal processing mode and x4 processing mode, respectively. 2. if two-phase pulse signal processing is desired, following register settings are required: ? set the taip bit in the udf register to 1 (two-phase pulse signal processing function enabled). ? set bits taitgh and taitgl in the trgsr register to 00 2 (taiin pin input). ? set the port direction bits for tai in and tai out to 0 (input mode).
12. timer a page 99 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 12.1.2.1 counter initialization by two-phase pulse signal processing this function initializes the timer count value to 0 by z-phase (counter initialization) input during two- phase pulse signal processing. this function can only be used in timer a3 event counter mode during two-phase pulse signal process- _______ ing, free-running type, x4 processing, with z-phase entered from the int2 pin. counter initialization by z-phase input is enabled by writing 0000 16 to the ta3 register and setting the tazie bit in onsf register to 1 (z-phase input enabled). counter initialization is accomplished by detecting z-phase input edge. the active edge can be cho- sen to be the rising or falling edge by using the pol bit in the int2ic register. the z-phase pulse _______ width applied to the int2 pin must be equal to or greater than one clock cycle of the timer a3 count source. the counter is initialized at the next count timing after recognizing z-phase input. figure 12.9 shows the relationship between the two-phase pulse (a phase and b phase) and the z phase. if timer a3 overflow or underflow coincides with the counter initialization by z-phase input, a timer a3 interrupt request is generated twice in succession. do not use the timer a3 interrupt when using this function. figure 12.10 two-phase pulse (a phase and b phase) and the z phase m m+1 1 2 3 4 5 ta3 out (a phase) count source ta3 in (b phase) timer a3 int2 (z phase) (1) input equal to or greater than one clock cycle of count source note: 1. this timing diagram is for the case where the pol bit in the int2ic register is set to 1 (rising edge).
12. timer a page 100 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r item specification count source f 1 , f 2 , f 8 , f 32 , f c32 count operation ? decrement ? when the counter reaches 0000 16 , it stops counting after reloading a new value ? if a trigger occurs when counting, the timer reloads a new count and restarts counting divide ratio 1/n n : set value of tai register 0000 16 to ffff 16 however, the counter does not work if the divide-by-n value is set to 0000 16 . count start condition tais bit in the tabsr register is set to 1 (start counting) and one of the following triggers occurs. ? external trigger input from the tai in pin ? timer b2 overflow or underflow, timer aj (j=i-1, except j=4 if i=0) overflow or underflow, timer ak (k=i+1, except k=0 if i=4) overflow or underflow ? the taios bit in the onsf register is set to 1 (timer starts) count stop condition ? when the counter is reloaded after reaching 0000 16 ? tais bit is set to ? 0 ? (stop counting) interrupt request generation timing when the counter reaches 0000 16 tai in pin function i/o port or trigger input tai out pin function i/o port or pulse output read from timer an undefined value is read by reading tai register write to timer ? when not counting and until the 1st count source is input after counting start value written to tai register is written to both reload register and counter ? when counting (after 1st count source input) value written to tai register is written to only reload register (transferred to counter when reloaded next) select function ? pulse output function the timer outputs a low when not counting and a high when counting. table 12.4 specifications in one-shot timer mode 12.1.3 one-shot timer mode in one-shot timer mode, the timer is activated only once by one trigger. (see table 12.4 ) when the trigger occurs, the timer starts up and continues operating for a given period. figure 12.11 shows the taimr register in one-shot timer mode.
12. timer a page 101 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 12.11 taimr register in one-shot timer mode bit name timer ai mode register (i=0 to 4) symbol address after reset ta0mr to ta4mr 396 16 to 039a 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0: one-shot timer mode b1 b0 tmod1 tmod0 mr0 mr2 mr1 mr3 set to 0 in one-shot timer mode tck1 tck0 count source select bit 10 0 trigger select bit external trigger select bit (1) rw rw rw rw rw rw rw rw rw notes: 1. effective when bits taitgh and taitgl in the onsf or trgsr register are 00 2 (tai in pin input). 2. the port direction bit for the tai in pin must be set to 0 (input mode). 0: pulse is not output (ta iout pin functions as i/o port) 1: pulse is output (tai out pin functions as a pulse output pin) 0: taios bit is enabled 1: selected by bits taitgh to taitgl 0: falling edge of input signal to taiin pin (2) 1: rising edge of input signal to taiin pin (2) pulse output function select bit b7 b6 0 0: f 1 or f 2 0 1: f 8 1 0: f 32 1 1: f c32
12. timer a page 102 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 12.1.4. pulse width modulation (pwm) mode in pwm mode, the timer outputs pulses of a given width in succession (see table 12.5 ). the counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. figure 12.12 shows taimr register in pulse width modulation mode. figures 12.13 and 12.14 show examples of how a 16- bit pulse width modulator operates and how an 8-bit pulse width modulator operates. table 12.5 specifications in pulse width modulation mode item specification count source f 1 , f 2 , f 8 , f 32 , f c32 count operation ? d ecrement (operating as an 8-bit or a 16-bit pulse width modulator) ? the timer reloads a new value at a rising edge of pwm pulse and continues counting ? the timer is not affected by a trigger that occurs during counting 16-bit pwm ? high level width n / fj n : set value of tai register (i=o to 4) ? cycle time (2 16 -1) / fj fixed fj: count source frequency (f 1 , f 2 , f 8 , f 32 , f c32 ) 8-bit pwm ? high level width n x (m+1) / fj n : set value of tai register high-order address ? cycle time (2 8 -1) x (m+1) / fj m : set value of tai register low-order address count start condition ? tais bit in the tabsr register is set to ? 1 ? (= start counting) ? the tais bit = 1 and external trigger input from the tai in pin ? the tais bit = 1 and one of the following external triggers occurs ? timer b2 overflow or underflow, timer aj (j=i-1, except j=4 if i=0) overflow or underflow, timer ak (k=i+1, except k=0 if i=4) overflow or underflow count stop condition tais bit is set to 0 (stop counting) interrupt request generation timing pwm pulse goes ? l ? tai in pin function i/o port or trigger input tai out pin function pulse output read from timer an undefined value is read by reading tai register write to timer ? when not counting and until the 1st count source is input after counting start value written to tai register is written to both reload register and counter ? when counting (after 1st count source input) value written to tai register is written to only reload register (transferred to counter when reloaded next)
12. timer a page 103 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 12.12 taimr register in pulse width modulation mode bit name timer ai mode register (i= 0 to 4) symbol address after reset ta0mr to ta4mr 0396 16 to 039a 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 b1 b0 1 1: pwm mode tmod1 tmod0 mr0 mr2 mr1 mr3 tck1 tck0 count source select bit rw 11 0: functions as a 16-bit pulse width modulator 1: functions as an 8-bit pulse width modulator trigger select bit external trigger select bit (1) rw rw rw rw rw rw rw rw 0: write 1 to tais bit in the tasf register 1: selected by bits taitgh to taitgl notes: 1. effective when bits taitgh and taitgl in the onsf or trgsr register are 00 2 (tai in pin input). 2. the port direction bit for the tai in pin must be set to 0 ( input mode). 16/8-bit pwm mode select bit pulse output funcion select bit operation mode select bit 0: falling edge of input signal to taiin pin (2) 1: rising edge of input signal to taiin pin (2) b7 b6 0 0: f 1 or f 2 0 1: f 8 1 0: f 32 1 1: f c32 0: pulse is not output (taiout pin functions as i/o port) 1: pulse is output (taiout pin functions as a pulse output pin)
12. timer a page 104 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 12.13 example of 16-bit pulse width modulator operation figure 12.14 example of 8-bit pulse width modulator operation 1 / f i x (2 ? 1) 16 count source input signal to ta iin pin pwm pulse output from ta iout pin trigger is not generated by this signal ? h ? ? h ? ? l ? ? l ? ir bit in the taiic register 1 0 f j : frequency of count source (f 1 , f 2 , f 8 , f 32 , f c32 ) i = 0 to 4 notes: 1. n = 0000 16 to fffe 16 . 2. this timing diagram is for the case where the tai register is 0003 16 , bits taitgh and taitgl in the onsf or trgsr register is set to 00 2 (tai in pin input), the mr1 bit in the taimr register is set to 1 (rising edge), and the mr2 bit in the taimr register is set to 1 (trigger selected by taitgh and taitgl bits). 1 / f j x n set to 0 upon accepting an interrupt request or by program count source (1) input signal to ta iin pin underflow signal of 8-bit prescaler (2) pwm pulse output from ta iout pin ? h ? ? h ? ? h ? ? l ? ? l ? ? l ? 1 0 set to 0 upon accepting an interrupt request or by program 1 / f j x (m + 1) x (2 ? 1) 8 1 / f j x (m + 1) x n 1 / f j x (m + 1) ir bit in the taiic register f j : frequency of count source (f 1 , f 2 , f 8 , f 32 , f c32 ) i = 0 to 4 notes: 1. the 8-bit prescaler counts the count source. 2. the 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. 3. m = 00 16 to ff 16 ; n = 00 16 to fe 16 . 4. this timing diagram is for the case where the tai register is 0202 16 , bits taitgh and taitgl in the onsf or trgsr register is set to 00 2 (tai in pin input), the mr1 bit in the taimr register is set to 0 (falling edge), and the mr2 bit in the taimr register is set to 1 (trigger selected by bits taitgh and taitgl).
12. timer b ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 105 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 12.2 timer b figure 12.15 shows a block diagram of the timer b. figures 12.16 and 12.17 show registers related to the timer b. timer b supports the following four modes. use bits tmod1 and tmod0 in the tbimr register (i = 0 to 2) to select the desired mode. ? timer mode: the timer counts the internal count source. ? event counter mode: the timer counts the external pulses or overflows and underflows of other timers. ? pulse period/pulse width measurement mode: the timer measures the pulse period or pulse width of external signal. ? a/d trigger mode: the timer starts counting by one trigger until the count value becomes 0000 16 . this mode is used together with simultaneous sample sweep mode or delayed trigger mode 0 of a/d converter to start a/d conversion. figure 12.15 timer b block diagram figure 12.16 tb0mr to tb2mr registers clock source selection ? event counter reload register low-order 8 bits high-order 8 bits data bus low-order bits data bus high-order bits f 8 tabsr register polarity switching, edge pulse counter reset circuit counter clock selection ? timer mode ? pulse period/, pulse width measuring mode ? a/d trigger mode f 1 or f 2 f c32 f 32 tbj overflow (1) (j = i ? 1, except j = 2 if i = 0) can be selected in onlyevent counter mode tbi in (i = 0 to 2) note: 1. overflow or underflow. tbi address tbj timer b0 0391 16 - 0390 16 timer b2 timer b1 0393 16 - 0392 16 timer b0 timer b2 0395 16 - 0394 16 timer b1 timer bi mode register (i=0 to 2) symbol after reset tb0mr to tb2mr bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 operation mode select bit (1) (2) rw rw rw rw rw rw rw ro notes: 1. timer b0. 2. timer b1, timer b2. function varies with each operation mode count source select bit function varies with each operation mode address 039b 16 to 039d 16 00xx0000 2 0 0 : timer mode or a/d trigger mode 0 1 : event counter mode 1 0 : pulse period measurement mode, pulse width measurement mode 1 1 : do not set
12. timer b ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 106 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 12.17 tb0 to tb2 registers, tabsr register, cpsrf register symbol address after reset tabsr 0380 16 00 16 count start flag bit name bit symbol b7 b6 b5 b4 b3 b2 b1 b0 timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0: stops counting 1: starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s function rw rw rw rw rw rw rw rw rw symbol address after reset cpsrf 0381 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 clock prescaler reset flag cpsr nothing is assigned. if necessary, set to 0. when read, the contents are undefined rw rw (b6-b0) symbol address after reset tb0 0391 16 , 0390 16 undefined tb1 0393 16 , 0392 16 undefined tb2 0395 16 , 0394 16 undefined b7 b0 b7 b0 (b15) (b8) timer bi register (i=0 to 2) (1) rw measures a pulse period or width functio n rw rw ro divide the count source by n + 1 where n = set value timer mode event counter mode 0000 16 to ffff 16 divide the count source by n + 1 where n = set value (2) 0000 16 to ffff 16 mode setting rrange a/d trigger mode (3) divide the count source by n + 1 where n = set value and cause the timer stop rw 0000 16 to ffff 16 setting this bit to 1 initializes the prescaler for the timekeeping clock. (when read, the value of this bit is 0) pulse period modulation mode, pulse width modulation mode notes: 1. the register must be accessed in 16 bit units 2. the timer counts pulses from an external device or overflows or underflows of other timers. 3. when this mode is used combining delayed trigger mode 0, set the larger value than the value in the timer b0 register to the timer b1 register.
12. timer b ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 107 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r item specification count source f 1 , f 2 , f 8 , f 32 , f c32 count operation ? decrement ? when the timer underflows, it reloads the reload register contents and continues counting divide ratio 1/(n+1) n: set value of tbi register (i= 0 to 2) 0000 16 to ffff 16 count start condition set tbis bit (1) to 1 (start counting) count stop condition set tbis bit to 0 (stop counting) interrupt request generation timing timer underflow tbi in pin function i/o port read from timer count value can be read by reading tbi register write to timer ? when not counting and until the 1st count source is input after counting start value written to tbi register is written to both reload register and counter ? when counting (after 1st count source input) value written to tbi register is written to only reload register (transferred to counter when reloaded next) note: 1. bits tb0s to tb2s are assigned to the bit 7 to bit 5 in the tabsr register. 12.2.1 timer mode in timer mode, the timer counts a count source generated internally (see table 12.6 ). figure 12.18 shows tbimr register in timer mode. table 12.6 specifications in timer mode figure 12.18 tbimr register in timer mode timer bi mode register (i= 0 to 2) symbol address after reset tb0mr to tb2mr 039b 16 to 039d 16 00xx0000 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 0: timer mode or a/d trigger mode b1 b0 tmod1 tmod0 mr0 no effect in timer mode can be set to 0 or 1 mr2 mr1 mr3 0 0: f 1 or f 2 0 1: f 8 1 0: f 32 1 1: f c32 tck1 tck0 count source select bit 0 0 tb0mr register set to 0 in timer mode b7 b6 rw rw rw rw rw rw rw ro tb1mr, tb2mr registers nothing is assigned. if necessary, set to 0. when read, the content is undefined when write in timer mode, set to 0. when read in timer mode, the content is undefined
12. timer b ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 108 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r item specification count source ? external signals input to tbi in pin (i=0 to 2) (effective edge can be selected in program) ? timer bj overflow or underflow (j=i-1, except j=2 if i=0) count operation ? decrement ? when the timer underflows, it reloads the reload register contents and continues counting divide ratio 1/(n+1) n: set value of tbi register 0000 16 to ffff 16 count start condition set tbis bit (1) to 1 (start counting) count stop condition set tbis bit to 0 (stop counting) interrupt request generation timing timer underflow tbi in pin function count source input read from timer count value can be read by reading tbi register write to timer ? when not counting and until the 1st count source is input after counting start value written to tbi register is written to both reload register and counter ? when counting (after 1st count source input) value written to tbi register is written to only reload register (transferred to counter when reloaded next) note: 1. bits tb2s to tb0s are assigned to the bit 7 to bit 5 in the tabsr register. 12.2.2 event counter mode in event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers (see table 12.7 ). figure 12.19 shows the tbimr register in event counter mode. table 12.7 specifications in event counter mode figure 12.19 tbimr register in event counter mode timer bi mode register (i=0 to 2) symbol address after reset tb0mr to tb2mr 039b 16 to 039d 16 00xx0000 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bi t 0 1: event counter mode b1 b0 tmod1 tmod0 mr0 count polarity select bit (1) mr2 mr1 mr3 tck1 tck0 01 0 0: counts external signal's falling edges 0 1: counts external signal's rising edges 1 0: counts external signal's falling and rising edges 1 1: do not set b3 b2 no effect in event counter mode can be set to 0 or 1 event clock select 0 : input from tbi in pin (2) 1 : tbj overflow or underflow (j = i ? 1, except j = 2 if i = 0) rw rw rw rw rw rw rw ro tb0mr register set to 0 in timer mode tb1mr, tb2mr registers nothing is assigned. if necessary, set to 0. when read, the content is undefined notes: 1. effective when the tck1 bit is set to 0 (input from tbiin pin). if the tck1 bit is set to 1 (tbj overflow or underflow ), these bits can be set to 0 or 1. 2. the port direction bit for the tbi in pin must be set to 0 (= input mode). when write in event counter mode, set to 0. when read in event counter mode, the content is undefined
12. timer b ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 109 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r item specification count source f 1 , f 2 , f 8 , f 32 , f c32 count operation ? increment ? counter value is transferred to reload register at an effective edge of mea- surement pulse. the counter value is set to 0000 16 to continue counting. count start condition set tbis (i=0 to 2) bit (3) to 1 (start counting) count stop condition set tbis bit to 0 (stop counting) interrupt request generation timing ? when an effective edge of measurement pulse is input (1) ? timer overflow. when an overflow occurs, mr3 bit in the tbimr register is set to 1 (overflowed) simultaneously. mr3 bit is cleared to 0 (no overflow) by writing to tbimr register at the next count timing or later after mr3 bit was set to 1. at this time, make sure tbis bit is set to 1 (start counting). tbi in pin function measurement pulse input read from timer contents of the reload register (measurement result) can be read by reading tbi register (2) write to timer value written to tbi register is written to neither reload register nor counter notes: 1. interrupt request is not generated when the first effective edge is input after the timer started counting. 2. value read from tbi register is undefined until the second valid edge is input after the timer starts counting. 3. bits tb0s to tb2s are assigned to the bit 5 to bit 7 in the tabsr register . 12.2.3 pulse period and pulse width measurement mode in pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an external signal (see table 12.8 ). figure 12.20 shows the tbimr register in pulse period and pulse width measurement mode. figure 12.21 shows the operation timing when measuring a pulse period. figure 12.22 shows the operation timing when measuring a pulse width. table 12.8 specifications in pulse period and pulse width measurement mode figure 12.20 tbimr register in pulse period and pulse width measurement mode timer bi mode register (i=0 to 2) symbol address after reset tb0mr to tb2mr 039b 16 to 039d 16 00xx0000 2 bit name bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0 : pulse period / pulse width measurement mode b1 b0 tmod1 tmod0 mr0 measurement mode select bit mr2 mr1 mr3 tck1 tck0 0 1 0 0: pulse period measurement (measurement between a falling edge and the next falling edge of measured pulse) 0 1: pulse period measurement (measurement between a rising edge and the next rising edge of measured pulse) 1 0: pulse width measurement (measurement between a falling edge and the next rising edge of measured pulse and between a rising edge and the next falling edge) 1 1: do not set. functio n b3 b2 count source select bi t timer bi overflow flag (1 ) 0 : timer did not overflow 1 : timer has overflowed 0 0: f 1 or f 2 0 1: f 8 1 0: f 32 1 1: f c32 b7 b6 ro tb0mr register set to 0 in pulse period and pulse width measurement mode tb1mr, tb2mr registers nothing is assigned. if necessary, set to 0. when read, the content is undefined rw rw rw rw rw rw rw note: 1.this flag is undefined after reset. when the tbis bit is set to 1 (start counting), the mr3 bit is cleared to 0 (no ov erflow) by writing to the tbimr register at the next count timing or later after the mr3 bit was set to 1 (overflowed). the mr3 bit canno t be set to 1 by program. bits tb0s to tb2s are assigned to the bit 5 to bit 7 in the tabsr register.
12. timer b ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 110 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 12.22 operation timing when measuring a pulse width figure 12.21 operation timing when measuring a pulse period count source measurement pulse tbis bit tbiic register's ir bit timing at which counter reaches 0000 16 ? h ? 1 transfer (undefined value) ? l ? 0 0 tbimr register's mr3 bit 1 0 (1) (1) (2) transfer (measured value) 1 reload register counter transfer timing bits tb0s to tb2s are assigned to the bit 5 to bit 7 in the tabsr register. set to 0 upon accepting an interrupt request or by program i = 0 to 2 notes: 1. counter is initialized at completion of measurement. 2. timer has overflowed. 3. this timing diagram is for the case where bits mr1 and mr0 in the tbimr register are 00 2 (measure the interval from falling edge to falling edge of the measurement pulse). measurement pulse ? h ? count source timing at which counter reaches 0000 16 1 1 transfer (measured value) transfer (measured value) ? l ? 0 0 1 0 (1) (1) (1 ) transfer (measured value) (1 ) (1 ) transfer (undefined value) reload register counter transfer timing tbis bit tbiic register's ir bit the mr3 bit in the tbimr register bits tb2s to tb0s are assigned to the bit 7 to bit 5 in the tabsr register. set to 0 upon accepting an interrupt request or by program i = 0 to 2 notes: 1. counter is initialized at completion of measurement. 2. timer has overflowed. 3. this timing diagram is for the case where bits mr1 to mr0 in the tbimr register are 10 2 (measure the interval from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of the measurement pulse).
12. timer b ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 111 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 12.2.4 a/d trigger mode a/d trigger mode is used together with simultaneous sample sweep mode or delayed trigger mode 0 of a/d conversion to start a/d conversion. it is used in timer b0 and timer b1 only. in this mode, the timer starts counting by one trigger until the count value becomes 0000 16 . figure 12.23 shows the tbimr register in a/d trigger mode and figure 12.24 shows the tb2sc register. item specification count source f 1 , f 2 , f 8 , f 32 , and f c32 count operation ? decrement ? when the timer underflows, reload register contents are reloaded before stopping counting ? when a trigger is generated during the count operation, the count is not affected divide ratio 1/(n+1) n: setting value of tbi register (i=0,1) 0000 16 -ffff 16 count start condition when the tbis (i=0,1) bit in the tabsr register is 1(count started), tbien(i=0,1) in tb2sc register is 1 (a/d trigger mode) and the following trigger is generated.(selection based on bits tb2sel in the tb2sc) ? timer b2 interrupt ? underflow of timer b2 interrupt generation frequency counter setting count stop condition ? after the count value is 0000 16 and reload register contents are reloaded ? set the tbis bit to 0 (count stopped) i nterrupt request timer underflows (1) generation timing tbiin pin function i/o port read from timer count value can be read by reading tbi register write to timer (2) ? when writing in the tbi register during count stopped. value is written to both reload register and counter ? when writing in the tbi register during count. value is written to only reload register (transfered to counter when reloaded next) notes: 1: a/d conversion is started by the timer underflow. for details refer to 15. a/d converter . 2: when using in delayed trigger mode 0, set the larger value than the value of the timer b0 register to the timer b1 register. table 12.9 specifications in a/d trigger mode
12. timer b ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 112 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 12.23 tbimr register in a/d trigger mode figure 12.24 tb2sc register in a/d trigger mode timer bi mode register (i= 0 to 1) symbol address after reset tb0mr to tb1mr 039b 16 to 039c 16 00xx0000 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 0: timer mode or a/d trigger mode b1 b0 tmod1 tmod0 mr0 invalid in a/d trigger mode either 0 or 1 is enabled mr2 mr1 mr3 0 0: f 1 or f 2 0 1: f 8 1 0: f 32 1 1: f c32 tck1 tck0 count source select bit 0 0 tb0mr register set to 0 in a/d trigger mode b7 b6 ro tb1mr register nothing is assigned. if necessary, set to 0. when read, its content is undefined when write in a/d trigger mode, set to 0. when read in a/d trigger mode, the content is undefined note: 1. when this bit is used in delayed trigger mode 0, set the same count source to the timer b0 and timer b1. (1) rw rw rw rw rw rw rw pwcon symbol address tb2sc 039e 16 x0000000 2 timer b2 reload timing switch bit 0: timer b2 underflow 1: timer a output at odd-numbered timer b2 special mode register (1) bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 ivpcr1 three-phase output port sd control bit 1 0: three-phase output forcible cutoff by sd pin input (high impedance) disabled 1: three-phase output forcible cutoff by sd pin input (high impedance) enabled 1. write to this register after setting the prc1 bit in the prcr register to 1 (write enabled). 2. if the inv11 bit is 0 (three-phase mode 0) or the inv06 bit is 1 (triangular wave modulation mode), set this bit to 0 (timer b2 underflow). rw rw rw nothing is assigned. if necessary, set to 0. when read, its content is 0 (b7) tb2sel trigger select bit 0: tb2 interrupt 1: underflow of tb2 interrupt generation frequency setting counter [ictb2] rw rw tb0en timer b0 operation mode select bit 0: other than a/d trigger mode 1: a/d trigger mode rw tb1en timer b1 operation mode select bit 0: other than a/d trigger mode 1: a/d trigger mode rw 3. when setting the ivpcr1 bit to 1 (three-phase output forcible cutoff by sd pin input enabled), set the pd8_5 bit to 0 (= input mode). 4. related pins are u(p8 0 ), u(p8 1 ), v(p7 2 ), v(p7 3 ), w(p7 4 ), w(p7 5 ). after forcible cutoff, input "h" to the p8 5 /nmi/sd pin. set the ivpcr1 bit to 0, and this forcible cutoff will be reset. if ? l ? is input to the p8 5 /nmi/sd pin, a three-phase motor control timer output will be disabled (inv03=0). at this time, when the ivpcr1 bit is 0, the target pins changes to programmable i/o port. when the ivpcr1 bit is 1, the target pins changes to high-impedance state regardless of which functions of those pins are used. 5. when this bit is used in delayed trigger mode 0, set bits tb0en and tb1en to 1 (a/d trigger mode). 6. when setting the tb2sel bit to 1 (underflow of tb2 interrupt generation frequency setting counter[ictb2]), set the inv02 bit to 1 (three-phase motor control timer function). 7. refer to " 18.6 digital debounce function " for the sd input. (2) (3, 4, 7) (5) (5) (6) (b6-b5) reserved bits set to 0 notes: 00 11 after reset
12. timer (three-phase motor control timer function) ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 113 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 12.3 three-phase motor control timer function timers a1, a2, a4 and b2 can be used to output three-phase motor drive waveforms. table 12.10 lists the specifications of the three-phase motor control timer function. figure 12.25 shows the block diagram for three-phase motor control timer function. also, the related registers are shown on figures 12.26 to 12.32. table 12.10 three-phase motor control timer function specifications item specification three-phase waveform output pin ___ ___ ___ six pins (u, u, v, v, w, w) forced cutoff input (1) _____ input ? l ? to sd pin used timers timer a4, a1, a2 (used in the one-shot timer mode) ___ timer a4: u- and u-phase waveform control ___ timer a1: v- and v-phase waveform control ___ timer a2: w- and w-phase waveform control timer b2 (used in the timer mode) carrier wave cycle control dead time timer (3 eight-bit timer and shared reload register) dead time control output waveform triangular wave modulation, sawtooth wave modification enable to output ? h ? or ? l ? for one cycle enable to set positive-phase level and negative-phase level respectively carrier wave cycle triangular wave modulation: count source x (m+1) x 2 sawtooth wave modulation: count source x (m+1) m: setting value of tb2 register, 0 to 65535 count source: f 1 , f 2 , f 8 , f 32 , f c32 three-phase pwm output width triangular wave modulation: count source x n x 2 sawtooth wave modulation: count source x n n: setting value of ta4, ta1 and ta2 register (of ta4, ta41, ta1, ta11, ta2 and ta21 registers when setting the inv11 bit to 1), 1 to 65535 count source: f 1 , f 2 , f 8 , f 32 , f c32 dead time count source x p, or no dead time p: setting value of dtt register, 1 to 255 count source: f 1 , f 2 , f 1 divided by 2, f 2 divided by 2 active level eable to select ? h ? or ? l ? positive and negative-phase concurrent positive and negative-phases concurrent active disable function positive and negative-phases concurrent active detect func- tion interrupt frequency for timer b2 interrupt, select a carrier wave cycle-to-cycle basis through 15 times carrier wave cycle-to-cycle basis note: _____ 1. when the inv02 bit in the invc0 register is set to 1 (three-phase motor control timer function), the sd function o f _____ _____ the p8 5 /sd pin is enabled. at this time, the p8 5 pin cannot be used as a programmable i/o port. when the sd _____ function is not used, apply ? h ? to the p8 5 /sd pin. _____ when the ivpcr1 bit in the tb2sc register is set to 1 (enable three-phase output forced cutoff by sd pin input), _____ and ? l ? is applied to the sd pin, the related pins enter high-impedance state regardless of the functions which are _____ used. when the ivpcr1 bit is set to 0 (disabled three-phase output forced cutoff by sd pin input) and ? l ? is _____ applied to the sd pin, the related pins can be selected as a programmable i/o port and the setting of the port and port direction registers are enable. related pins: p7 2 /clk 2 /ta1 out /v/rxd 1 _________ _________ ___ p7 3 /cts 2 /rts 2 /ta1 in /v/txd 1 p7 4 /ta2 out /w ____ p7 5 /ta2 in /w p8 0 /ta4 out /u ___ p8 1 /ta4 in /u
12. timer (three-phase motor control timer function) ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 114 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 12.25 three-phase motor control timer functions block diagram d r q 0 in v 12 1 trigger trigger timer b2 (timer mode ) s ignal to b e written to timer b2 1 timer b2 int err up t re qu e s t bit du1 b it d t q q q u three -phase output shif t regi ster (u phase) dead tim e tim er n = 1 to 255 trigger trigger reload regi ster n = 1 to 255 trigger trigger u phase output sig nal u v v v w w w phase ou tpu t cont rol circuit d q t d q t w d q t d q t v d q t d q t u w v u reload t imer a1 cou nt er (on e-shot ti mer mode) trigger t q reload timer a2 cou nt e r (on e-sho t ti mer mode) trigger t q re load t imer a4 count er ( on e-sho t ti mer mode) trigger t q transfer trigger ( n ot e 1 ) ti mer b2 u nderflow du0 bit dub0 bit ta4 register ta41 register ta1 register ta11 register ta2 register ta21 register timer ai(i = 1, 2, 4) start trigger signal timer a4 reload control signal timer a4 one-shot pulse du b1 bit dead time timer n = 1 to 2 55 dead time timer n = 1 to 255 interrupt occurrence set circuit ictb2 register n = 1 to 15 0 inv13 ictb2 counter n = 1 to 15 sd reset inv03 inv14 inv05 inv04 inv00 inv01 inv11 inv11 inv11 inv11 inv06 inv06 inv06 inv07 inv10 1/2 f1 or f2 phase ou tpu t cont ro l circuit p hase outpu t cont rol circuit ph as e outpu t signal ph ase outpu t signal phase output signal ph ase outpu t signal ph as e outpu t signal reverse cont rol r ev erse cont rol reverse cont rol reverse cont rol reverse cont rol d t d t q d t reverse cont rol idw idv idu d q t d q t d q t b2 b0 b1 bits 2 through 0 of position-data - retain function control regi ster (address 034e 16 ) pd8_0 pd8_1 pd7_2 pd7_3 pd7_4 pd7_5 s q r reset sd ivprc1 data bus note: 1. if the inv06 bit is set to 0 (triangular wave modulation mode), a transfer trigger is generated at only the first occur rence of a timer b2 underflow after writing to the idb0 and idb1 registers. set to 0 when ta2s bit is set to 0 set to 0 when ta1s bit = 0 set to 0 when ta4s bit is set to 0 diagram for switching to p8 0 , p81 and p7 2 - p7 5 is not shown.
12. timer (three-phase motor control timer function) ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 115 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 12.26 invc0 register three-phase pwm control register 0 (1) symbol address after reset invc0 0348 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 inv00 bit symbol bit name function rw inv01 inv02 mode select bit (4) inv04 inv07 software trigger select bit inv06 modulation mode select bit (8) inv05 inv03 output control bit (6) rw rw rw rw rw rw rw rw item mode timing at which transferred from registers idb0 to idb1 to three-phase output shift register timing at which dead time timer trigger is generated when inv16 bit is 0 inv13 bit inv06=0 triangular wave modulation mode transferred only once synchronously with the transfer trigger after writing to registers idb0 to idb1 synchronous with the falling edge of timer a1, a2, or a4 one-shot pulse effective when inv11 is set to 1 and inv06 is set to 0 inv06=1 sawtooth wave modulation mode transferred every transfer trigger synchronous with the transfer trigger and the falling edge of timer a1, a2, or a4 one-shot pulse no effect notes: 1. write to this register after setting the prc1 bit in the prcr register to 1 (write enable). note also that bits inv00 to inv 02, bits inv04 and inv06 can only be rewritten when timers a1, a2, a4 and b2 are idle. 2. if this bit needs to be set to 1, set any value in the ictb2 register before writing to it. 3. effective when the inv11 bit in the inv1 register is 1 (three-phase mode 1). if inv11 is set to 0 (three-phase mode 0), the ictb2 counter is incremented by 1 each time the timer b2 underflows, regardless of whether the inv00 and inv01 bits are set. when setting the inv01 bit to 1, the first interrupt is generated when the timer b2 underflows n-1 times, if n is the valu e set in the ictb2 counter. subsequent interrupts are generated every n times the timer b2 underflow. 4. setting the inv02 bit to 1 activates the dead time timer, u/v/w-phase output control circuits and ictb2 counter. 5. when the inv02 bit is set to 1 and the inv03 bit is set to 0, u, u, v, v, w, w pins, including pins shared with other output functions, enter a high-impedance state. when inv03 is set to 1, u/v/w corresponding pins generate the three-phase pwm output. 6. the inv03 bit is set to 0 in the following cases: ? when reset ? when positive and negative go active (inv05 = 1) simultaneously while inv04 bit is 1 ? when set to 0 by program ? when input on the sd pin changes state from ? h ? to ? l ? regardless of the value of the invcr1 bit. (the inv03 bit cannot be set to 1 when sd input is ? l ? .) inv03 is set to 0 when both bits inv05 and inv04 are set to 1. effective interrupt output polarity select bit (3) effective interrupt output specification bit (2, 3) 0: ictb2 counter incremented by 1 at a timer b2 underflow 1: selected by inv00 bit 0: three-phase motor control timer function unused 1: three-phase motor control timer function (5) 0: three-phase motor control timer output disabled (5) 1: three-phase motor control timer output enabled positive and negative phases concurrent output disable bit positive and negative phases concurrent output detect flag 0: not detected yet 1: already detected (7) 0: simultaneous active output enabled 1: simultaneous active output disabled 0: triangular wave modulation mode 1: sawtooth wave modulation mode (9) setting this bit to 1 generates a transfer trigger. if the inv06 bit is 1, a trigger for the dead time timer is also generated. the value of this bit when read is 0 0: ictb2 counter is incremented by 1 on the rising edge of timer a1 reload control signal 1: ictb2 counter is incremented by 1 on the falling edge of timer a1 reload control signal transfer trigger: timer b2 underflow, write to the inv07 bit or write to the tb2 register when the inv10 bit is set to 1. 9: if the inv06 bit is set to 1, set the inv11 bit to 0 (three-phase mode 0) and set the pwcon bit to 0 (timer b2 reloaded by a timer b2 underflow) 10. when the pfci (i = 0 to 5) bit in the pfcr register is set to 1 (three-phase pwm output), individual pins are enabled to ou tput.
12. timer (three-phase motor control timer function) ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 116 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 12.27 invc1 register three-phase pwm control register 1 (1) symbol address after reset invc1 0349 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 timer a1, a2, a4 start trigger signal select bit inv10 bit symbol bit name function rw inv11 timer a1-1, a2-1, a4-1 control bit inv12 dead time timer count source select bit inv14 output polarity control bit (b7) reserved bit inv16 inv15 dead time invalid bit inv13 carrier wave detect flag (5) 0: timer b2 underflow 1: timer b2 underflow and write to the tb2 register (2) 0: three-phase mode 0 1: three-phase mode 1 0: f 1 or f 2 1: f 1 divided by 2 or f 2 divided by 2 0: timer reload control signal is set to 0 1: timer reload control signal is set to 1 0 : output waveform ? l ? active 1 : output waveform ? h ? active 0: dead time timer enabled 1: dead time timer disabled set to 0 rw rw rw rw rw rw rw ro (3) item mode ta11, ta21, ta41 registers inv00 bit, inv01 bit inv13 bit inv11=0 three-phase mode 1 three-phase mode 0 not used has no effect. ictb2 counted every time timer b2 underflows regardless of whether bits inv00 and inv01 are set has no effect inv11=1 used effect effective when inv11 bit is 1 and inv06 bit is 0 (4) 0 4. if the inv06 bit is 1 (sawtooth wave modulation mode), set this bit to 0 (three-phase mode 0). also, if the inv11 bit is 0, set the pwcon bit to 0 (timer b2 reloaded by a timer b2 underflow). 5. the inv13 bit is effective only when the inv06 bit is set to 0 (triangular wave modulation mode) and the inv11 bit is set to 1 (three-phase mode 1). 6. if all of the following conditions hold true, set the inv16 bit to 1 (dead time timer triggered by the rising edge of three- phase output shift register output) ? the inv15 bit is 0 (dead time timer enabled) ? when the inv03 bit is set to 1 (three-phase motor control timer output enabled), the dij bit and dibj bit (i:u, v, or w, j: 0 to 1) have always different values (the positive-phase and negative-phase always output different levels during the period other than dead time). conversely, if either one of the above conditions holds false, set the inv16 bit to 0 (dead time timer triggered by the falling edge of one-shot pulse). notes: 1. write to this register after setting the prc1 bit in the prcr register to 1 (write enable). note also that this register can only be rewritten when timers a1, a2, a4 and b2 are idle. 2. a start trigger is generated by writing to the tb2 register only while timer b2 stops. 3. the effects of the inv11 bit are described in the table below. 0: falling edge of timer a4, a1 or a2 one-shot pulse 1: rising edge of three-phase output shift register (u, v or w phase) output (6) dead time timer trigger select bit
12. timer (three-phase motor control timer function) ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 117 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 12.28 idb0 register, idb1register, dtt register, and ictb2 register three-phase o utput buffer re g ister(i=0,1) (1) symbol address after reset idb0 034a 16 00111111 2 idb1 034b 16 00111111 2 rw rw rw rw bit name function bit symbol dui dubi dvi u phase output buffer i note: 1. registers idb0 and idb1 values are transferred to the three-phase shift register by a transfer trigger. the value written to the idb0 register aftera transfer trigger represents the output signal of each phase, and the next value written to the idb1 register at the falling edge of the timer a1, a2, or a4 one-shot pulse represents the output signa l of each phase. (b7-b6) rw dvbi nothing is assigned. if necessary, set to 0. when read, these contents are 0 write the output level 0: active level 1: inactive level when read, these bits show the three-phase output shift register value. dwi dwbi rw rw u phase output buffer i v phase output buffer i v phase output buffer i w phase output buffer i w phase output buffer i b 7 b 4 b3 b 2b1b0 dead time timer (1, 2) symbol address after reset dtt 034c 16 undefined wo rw function setting range notes: 1. use mov instruction to write to this register. 2. effective when the inv15 bit is set to 0 (dead time timer enable). if the inv15 bit is set to 1, the dead time time r is disabled and has no effect. 1 to 255 b7 b0 assuming the set value = n, upon a start trigger the timer starts counting the count souce selected by the inv12 bit and stops after counting it n times. the positive or negative phase whichever is going from an inactive to an active level changes at the same time the dead time timer stops. ro 0 timer b2 interrupt occurrences frequency set counter symbol ictb2 address 034d 16 after reset undefined function setting range b7 b6 b5 b4 b0 if the inv01 bit is 0 (ictb2 counter counted every time timer b2 underflows), assuming the set value = n, a timer b2 interrupt is generated at every n th occurrence of a timer b2 underflow. if the inv01 bit is 1 (ictb2 counter count timing selected by the inv00 bit), assuming the set value = n, a timer b2 interrupt is generated at every n th occurrence of a timer b2 underflow that meets the condition selected by the inv00 bit. 1 to 15 note: 1. use mov instruction to write to this register. if the inv01 bit is set to 1, make sure the tb2s bit also is set to 0 (timer b2 count stopped) when writing to this register. if the inv01 bit is set to 0, although this register can be written even when the tb2s bit is set to 1 (timer b2 count start), do not write synchronously with a timer b2 underflow. rw wo (1) nothing is assigned. when write, set to "0". when read, the content is undefined. b3
12. timer (three-phase motor control timer function) ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 118 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 12.29 ta1, ta2, ta4, ta11, ta21, and ta41 registers symbol address after reset ta1 0389 16 -0388 16 undefined ta2 038b 16 -038a 16 undefined ta4 038f 16 -038e 16 undefined ta11 (6,7) 0343 16 -0342 16 undefined ta21 (6,7) 0345 16 -0344 16 undefined ta41 (6,7) 0347 16 -0346 16 undefined b7 b0 b7 b0 (b15) ( b8) rw assuming the set value = n, upon a start trigger the timer starts counting the count source and stops after counting it n times. the positive and negative phases change at the same time timer a, a2 or a4 stops. function setting range timer ai, ai-1 register (i=1, 2, 4) (1, 2, 3, 4, 5) notes: 1. the register must be accessed in 16 bit units. 2. when the timer ai register is set to 0000 16 , the counter does not operate and a timer ai interrupt does not occur. 3. use mov instruction to write to these registers. 4. if the inv15 bit is 0 (dead time timer enable), the positive or negative phase whichever is going from an inactive to an active level changes at the same time the dead time timer stops. 5. if the inv11 bit is 0 (three-phase mode 0), the tai register value is transferred to the reload register by a timer ai (i = 1, 2 or 4) start trigger. if the inv11 bit is 1 (three-phase mode 1), the tai1 register value is transferred to the reload register by a timer ai start trigger first and then the tai register value is transferred to the reload register by the next timer ai start t rigger. thereafter, the tai1 register and tai register values are transferred to the reload register alternately. 6. do not write to tai1 registers synchronously with a timer b2 underflow in three-phase mode 1. 7. write to the tai1 register as follows: (1) write a value to the tai1 register (2) wait for one cycle of timer ai count source. (3) write the same value to the tai1 register again. wo 0000 16 to ffff 16
12. timer (three-phase motor control timer function) ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 119 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 12.30 tb2sc register 0: three-phase output forcible cutoff by sd pin input (high impedance) disabled 1: three-phase output forcible cutoff by sd pin input (high impedance) enabled notes: 1. when "l" is applied to the sd pin, inv03 bit is changed to 0 at the same time. 2. the value of the port register and the port direction register becomes effective. 3. when sd function is not used, set to 0 (input) in pd8 5 and pullup to "h" in sd pin from outside. 4. to leave the high-impedance state and restart the three-phase pwm signal output after the three-phase pwm signal output forced cutoff, set the ivpcr1 bit to 0 after the sd pin input level becomes high ( ? h ? ). ivpcr1 bit status of u/v/w pins remarks sd pin inputs 1 (three-phase output forcrible cutoff enable) 0 (three-phase output forcrible cutoff disable) h l h l high impedance peripheral input/output or input/output port peripheral input/output or input/output port peripheral input/output or input/output port three-phase output forcrible cutoff (1) ivpcr1 bit status of u/v/w pins remarks sd pin inputs (3) 1 (three-phase output forcrible cutoff enable) 0 (three-phase output forcrible cutoff disable) h l (1) h l (1) high impedance (4) three-phase output forcrible cutoff input/output port (2) three-phase pwm output three-phase pwm output the effect of sd pin input is below. 1.case of inv03 = 1(three-phase motor control timer output enabled) pwcon symbol address after reset tb2sc 039e 16 x0000000 2 timer b2 reload timing switch bit timer b2 special mode register (1) bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 ivpcr1 three-phase output port sd control bit 1 rw rw rw nothing is assigned. if necessary, set to 0. when read, the content is 0. (b7) tb2sel trigger select bit 0: tb2 interrupt 1: underflow of tb2 interrupt generation frequency setting counter [ictb2] rw rw tb0en timer b0 operation mode select bit 0: other than a/d trigger mode 1: a/d trigger mode rw tb1en timer b1 operation mode select bit 0: other than a/d trigger mode 1: a/d trigger mode rw (2) (3, 4, 7) (5) (5) (6) (b6-b5) reserved bits set to 0 0 0 notes: 1. write to this register after setting the prc1 bit in the prcr register to 1 (write enabled). 2. if the inv11 bit is 0 (three-phase mode 0) or the inv06 bit is 1 (triangular wave modulation mode), set this bit to 0 (time r b2 underflow). 3. when setting the ivpcr1 bit to 1 (three-phase output forcible cutoff by sd pin input enabled), set the pd8 5 bit to 0 (= input mode). 4. related pins are u(p8 0 ), u(p8 1 ), v(p7 2 ), v(p7 3 ), w(p7 4 ), w(p7 5 ). when a high-level ("h") signal is applied to the sd pin and set the ivpcr1 bit to 0 after forcible cutoff, pins u, u, v, v, w, and w are exit from the high-impedance state. if a low- level ( ? l ? ) signal is applied to the sd pin, three-phase motor control timer output will be disabled (inv03=0). at this time, when the ivpcr1 bit is 0, pins u, u, v, v, w, and w become programmable i/o ports. when the ivpcr1 bit is set to 1, pins u, u, v, v, w, and w are placed in a high-impedance state regardless of which function of those pins is used. 5. when this bit is used in delayed trigger mode 0, set bits tb0en and tb1en to 1 (a/d trigger mode). 6. when setting the tb2sel bit to 1 (underflow of tb2 interrupt generation frequency setting counter[ictb2]), set the inv02 bit to 1 (three-phase motor control timer function). 7. refer to " 18.6 digital debounce function " for the sd input. note: 1. the three-phase output forcrible cutoff function becomes effective if the inpcr1 bit is set to 1 (three-phase output forcrible cutoff function enable) even when the inv03 bit is 0 (three-phase motor control timer output disalbe) 2.case of inv03 = 0(three-phase motor control timer output disabled) 0: timer b2 underflow 1: timer a output at odd-numbered
12. timer (three-phase motor control timer function) ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 120 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 12.31 tb2 register, trgsr register, and tabsr register symbol address after reset tb2 0395 16 -0394 16 undefined b7 b0 b7 b0 (b15) ( b8) rw 0000 16 to ffff 16 function setting range timer b2 register (1) note: 1. access the register by 16 bit units. rw divide the count source by n + 1 where n = set value. timer a1, a2 and a4 are started at every occurrence of underflow. ta1tgl symbol address after reset trgsr 0383 16 00 16 timer a1 event/trigger select bit to use the v-phase output control circuit, set these bits to ? 01 2 ? (tb2 underflow). trigger select register bit name function bit symbol b0 to use the w-phase output control circuit, set these bits to ? 01 2 ? (tb2 underflow). 0 0 : input on ta3 in is selected (1) 0 1 : tb2 is selected (2) 1 0 : ta2 is selected (2) 1 1 : ta4 is selected (2) to use the u-phase output control circuit, set these bits to ? 01 2 ? (tb2 underflow). timer a2 event/trigger select bit timer a3 event/trigger select bit timer a4 event/trigger select bit rw ta1tgh ta2tgl ta2tgh ta3tgl ta3tgh ta4tgl ta4tgh b5 b4 notes: 1. set the corresponding port direction bit to 0 (input mode). 2. overflow or underflow. b7 b6 b5 b4 b3 b2 b1 symbol address after reset tabsr 0380 16 00 16 count start fla g bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
12. timer (three-phase motor control timer function) ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 121 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 12.32 ta1mr, ta2mr, ta4mr, and tb2mr registers bit name timer ai mode register symbol address after reset ta1mr 0397 16 00 16 ta2mr 0398 16 00 16 ta4mr 039a 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit set to 10 2 (one-shot timer mode) for the three-phase motor control timer function tmod1 tmod0 mr0 pulse output function select bit set to 0 for the three-phase motor control timer function mr2 mr1 mr3 set to 0 for the three-phase motor control timer function 0 0 : f 1 or f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 10 0 set to 1 (selected by event/trigger select register) for the three-phase motor control timer function trigger select bit external trigger select bit rw timer b2 mode register symbol address after reset tb2mr 039d 16 00xx0000 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit set to 00 2 (timer mode) for the three- phase motor control timer function tmod1 tmod0 mr0 mr2 mr1 mr3 tck1 tck0 count source select bit 0 0 1 0 no effect for the three-phase motor control timer function rw rw rw rw rw rw rw rw rw rw rw rw rw rw ro no effect for the three-phase motor control timer function. if necessary, set to 0. when read, the contents are undefined set to 0 for the three-phase motor control timer function 0 rw when write in three-phase motor control timer function, write 0. when read, the content is undefined b7 b6 0 0: f 1 or f 2 0 1: f 8 1 0: f 32 1 1: f c32
12. timer (three-phase motor control timer function) ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 122 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 12.33 triangular wave modulation operation the three-phase motor control timer function is enabled by setting the inv02 bit in the invc0 register to 1. when this function is on, timer b2 is used to control the carrier wave, and timers a4, a1 and a2 are used to __ ___ ___ control three-phase pwm outputs (u, u, v, v, w and w). the dead time is controlled by a dedicated dead- time timer. figure 12.33 shows the example of triangular modulation waveform, and figure 12.34 shows the example of sawtooth modulation waveform. start trigger signal for timer a4 (1) timer b2 u phase triangular wave signal wave u phase output signal (1) m nn p p m u phase u phase u phase inv14 = 0 triangular waveform as a carrier wave timer a4 one-shot pulse (1) inv14 = 1 dead time dead time rewrite registers idb0 and idb1 note: 1. internal signals. see figure 12.25 . examples of pwm output change are: (1)when inv11 = 1 (three-phase mode 1) inv01 = 0 and ictb2 = 2 16 (the timer b2 interrupt is generated every two times the timer b2 underflows), or inv01 = 1, inv00 = 1, and ictb2=1 16 (the timer b2 interrupt is generated at the falling edge of the timer a1 reload control signal.) default value of the timer: ta41 = m, ta4 = m. registers ta4 and ta41 are changed whenever the timer b2 interrupt is generated. first time, ta41 = n, ta4 = n. second time, ta41 = p, ta4 = p. default values of registers idb0 and idb1: du0 = 1, dub0 = 0, du1 = 0, dub1 = 1. they are changed to du0 = 1, dub0 = 0, du1= 1 and dub1 = 0 when the third timer b2 interrupt is generated. (2)when inv11 = 0 (three-phase mode 0) inv01 = 0, ictb2 = 1 16 (the timer b2 interrupt is generated whenever timer b2 underflows) default value of the timer: ta4 = m. the ta4 register is changed whenever the timer b2 interrupt is generated. first time: ta4 = m. second tim:, ta4 = n. third time: ta4 = n. fourth time: ta4 = p. fifth time: ta4 = p. default values of registers idb0 and idb1: du0 = 1, dub0 = 0, du1 = 0, dub1 = 1. they are changed to du0 = 1, dub0 = 0, du1 = 1, and dub1 = 0 when the sixth timer b2 interrupt is generated. tb2s bit in the tabsr register inv13 (inv11=1(three-phase mode 1)) the above applies under the following conditions: invc0 = 00xx11xx 2 (x varies depending on each system) and invc1 = 010xxxx0 2 . u phase output signal (1) ( ? l ? active) ( ? h ? active) the value written to registers ta4 and ta41 becomes effective at the rising edge of the timer a1 reload control signal. transfer the values to the three-phase output shift register
12. timer (three-phase motor control timer function) ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 123 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 12.34 sawtooth wave modulation operation timer b2 u phase sawtooth wave signal wave u phase output signal (1) u phase u phase output signal (1) u phase u phase inv14 = 0 sawtooth waveform as a carrier wave inv14 = 1 note: 1. internal signals. see figure 12.25 . the above applies under the following conditions: invc0 = 01xx110x 2 (x varies depending on each system) and invc1 = 010xxx00 2 . examples of pwm output change are: ? default value of registers idb0 and idb1: du0=0, dub0=1, du1=1, dub1=1. they are changed to du0=1, dub0=0, du1=1, dub1=1 when the timer b2 interrupt is generated. start trigger signal for timer a4 (1) timer a4 one-shot pulse (1) dead time dead time ( ? h ? active) ( ? l ? active) transfer the values to the three- phase output shift register rewrite registers idb0 and idb1
12. timer (three-phase motor control timer function) ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 124 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 12.3.1 position-data-retain function this function is used to retain the position data synchronously with the three-phase waveform output.there are three position-data input pins for u, v, and w phases. a trigger to retain the position data (hereafter, this trigger is referred to as "retain trigger") can be selected by the pdrt bit in the pdrf register. this bit selects the retain trigger to be the falling edge of each positive phase, or the rising edge of each positive phase. 12.3.1.1 operation of the position-data-retain function figure 12.35 shows a usage example of the position-data-retain function (u phase) when the retain trigger is selected as the falling edge of the positive signal. (1) at the falling edge of the u-phase waveform ouput, the state at pin idu is transferred to the pdru bit in the pdrf register. (2) until the next falling edge of the uphase waveform output,the above value is retained. t r a n sfe rr ed carrier wave u-phase waveform output u-phase waveform output 1 2 t r a n sfe rr ed t r a n sfe rr ed t r a n sfe rr ed pin idu note: n o t e : the retain trigger is the falling edge of the positive signal. pdru bit figure 12.35 usage example of position-data-retain function (u phase )
12. timer (three-phase motor control timer function) ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 125 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 12.3.1.2 position-data-retain function control register figure 12.36 shows the structure of the position-data-retain function contol register. figure 12.36 pdrf register 12.3.1.2.1 w-phase position data retain bit (pdrw) this bit is used to retain the input level at pin idw. 12.3.1.2.2 v-phase position data retain bit (pdrv) this bit is used to retain the input level at pin idv. 12.3.1.2.3 u-phase position data retain bit (pdru) this bit is used to retain the input level at pin idu. 12.3.1.2.4 retain-trigger polarity select bit (pdrt) this bit is used to select the trigger polarity to retain the position data. when this bit is set to 0, the rising edge of each positive phase selected. when this bit is set to 1, the falling edge of each pocitive phase selected. position-data-retain function c ontrol re g ister (1) symbol address after reset pdrf 034e 16 xxxx 0000 2 ro ro ro rw bit name function bit symbol pdrw pdrv pdru w-phase position data retain bit input level at pin idu is read out. 0: "l" level 1: "h" level note: 1.this register is valid only in the three-phase mode. retain-trigger polarity select bit (b7-b4) rw pdrt v-phase position data retain bit nothing is assigned. when write, set to 0. when read, contents are undefined u-phase position data retain bit input level at pin idv is read out. 0: "l" level 1: "h" level input level at pin idw is read out. 0: "l" level 1: "h" level 0: rising edge of positive phase 1: falling edge of positive phase b 7 b3 b 2b1b0
12. timer (three-phase motor control timer function) ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 126 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 12.3.2 three-phase/port output switch function when the invc03 bit in the invc0 register set to 1 (timer output enabled for three-phase motor control) __ and setting the pfci (i=0 to 5) in the pfcr register to 0 (i/o port), the three-phase pwm output pin (u, u, __ ___ v, v, w and w) functions as i/o port. each bit of the pfci bits (i=0 to 5) is applicable for each one of three-phase pwm output pins. figure 12.37 shows the example of three-phase/port output switch func- tion. figure 12.38 shows the pfcr register and the three-phase protect control register. figure 12.37 usage example of three-phse/port output switch function timer b2 u phase v phase w phase writing pfcr register pfc0 bit: 1 pfc2 bit: 1 pfc4 bit: 0 functions as port p7 4 functions as port p7 2 writing pfcr register pfc0 bit: 1 pfc2 bit: 0 pfc4 bit: 1
12. timer (three-phase motor control timer function) ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 127 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 12.38 pfcr register, and tprc register port function c ontrol re g ister (1) symbol address after reset pfcr 0358 16 0011 1111 2 rw rw rw rw bit name function bit symbol pfc0 pfc1 pfc2 port p8 0 output function select bit note: 1. this register is valid only when the invc03 bit in the invc0 register is 1 (three-phase motor control timer. (b7-b6) rw pfc3 nothing is assigned. when write, set to 0. when read, these contents are 0 0: input/output port p8 0 1: three-phase pwm output (u phase output) pfc4 pfc5 rw rw port p8 1 output function select bit port p7 2 output function select bit port p7 3 output function select bit port p7 4 output function select bit port p7 5 output function select bit 0: input/output port p8 1 1: three-phase pwm output (u phase output) 0: input/output port p7 2 1: three-phase pwm output (v phase output) 0: input/output port p7 3 1: three-phase pwm output (v phase output) 0: input/output port p7 4 1: three-phase pwm output (w phase output) 0: input/output port p7 5 1: three-phase pwm output (w phase output) b 7 b5 b 4 b3 b 2b1b0 three-phase protect c ontrol re g ister symbol address after reset tprc 025a 16 00 16 rw rw bit name function bit symbol tprc0 three-phase protect control bit (b7-b1) nothing is assigned. if necessary, set to 0. when read, the contents are 0 enable write to pfcr register 0: write protected 1: write enabled b 7 b3 b 2b1b0
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 128 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 13. timer s the timer s (input capture/output compare : here after, timer s is referred to as "ic/oc".) is a high- performance i/o port for time measurement and waveform generation. the ic/oc has one 16-bit base timer for free-running operation and eight 16-bit registers for time measure- ment and waveform generation. table 13.1 lists functions and channels of the ic/oc. table 13.1 ic/oc functions and channels function description time measurement (1) 8 channels digital filter 8 channels trigger input prescaler 2 channels trigger input gate 2 channels waveform generation (1) 8 channels single-phase waveform output available phase-delayed waveform output available set/reset waveform output available note: 1. the time measurement function and the waveform generating function share a pin. the time measurement function or waveform generating function can be selected for each channel.
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 129 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 13.1 ic/oc block diagram bts: bits in the g1bcr1 register cts1 to cts0, df1 to df0, gt, pr : bits in the g1tmcrj register (j= 0 to 7) pclk0 : bits in the pclkr register g1tm0, g1po0 register g1tm1, g1po1 register g1tm2, g1po2 register g1tm3, g1po3 register g1tm4, g1po4 register g1tm5, g1po5 register g1tm6, g1po6 register g1tm 7, g 1po 7 register pwm output pwm output pwm output pwm output base timer reset (n+1) divider register edge select digital filter gate functio n edge select digital filter gate function edge select digital filter edge select digital filter inpc1 0 inpc1 1 inpc1 6 (g1dv) gt gt pr pr ch0 to ch7 interrupt request signal outc1 0 outc1 1 outc1 4 outc1 5 prescaler function prescaler function outc1 6 outc1 7 outc1 2 outc1 3 (note 1) base timer f bt 1 edge select digital filter inpc1 2 two-phase pulse input bck1 to bck0 : bits in the g1bcr0 register request from int1 pi n bts request by matching g1po0 register and base timer base timer over flow request bck1 to bck0 11 10 00 10:f bt1 11: f 1 or f 2 df1 to df0 cts1 to cts0 cts1 to cts0 cts1 to cts0 00 df1 to df0 00 df1 to df0 00 df1 to df0 00 0 0 1 0 1 0 1 1 df1 to df0 base timer reset register (g1btrr) request by matching g1btrr and base timer 00 cts1 to cts0 df1 to df0 edge select digital filter inpc1 3 df1 to df0 edge select digital filter inpc1 4 cts1 to cts0 df1 to df0 edge select digital filter inpc1 5 cts1 to cts0 inpc1 7 digital debounce base timer reset request base timer interrupt request 00 00 cts1 to cts0 cts1 to cts0 1/2 pclk0=0 pclk0=1 f 1 or f 2 f 1 or f 2 main clock, pll clock, on-chip oscillator clock 10:f bt1 11: f 1 or f 2 10:f bt1 11: f 1 or f 2 10:f bt1 11: f 1 or f 2 10:f bt1 11: f 1 or f 2 10:f bt1 11: f 1 or f 2 10:f bt1 11: f 1 or f 2 10:f bt1 11: f 1 or f 2 figure 13.1 shows the block diagram of the ic/oc.
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 130 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figures 13.2 to 13.10 show registers associated with the ic/oc base timer, the time measurement func- tion, and the waveform generating function. figure 13.2 g1bt and g1bcr0 registers base timer register (1) symbol address after reset g1bt 0321 16 - 0320 16 indeterminate rw rw function (b7) b0 setting range 0000 16 to ffff 16 b8 b15 b7 (b0) when the base timer is operating: when read, the value of base timer plus 1 can be read. when write, the counter starts counting from the value written. when the base timer is reset, this register is set to "0000 16 ". (2) when the base timer is reset: this register is set to "0000 16 " but a value read is indeterminate. no value is written (2) notes: 1. the g1bt register reflects the value of the base timer, synchronizing with the count source f bt1 cycles. 2. this base timer stops only when the bck1 to bck0 bits in the g1bcr0 register are set to "00 2 " (count source clock stop). the base timer operates when the bck1 to bck0 bits are set to other than "00 2 ". when the bts bit in the g1bcr1 register is set to "0", the base timer is reset continuously, and remaining set to "0000 16 ". when the bts bit is set to "1", this state is cleared and the timer starts counting. base timer control register 0 symbol address after reset g1bcr0 0322 16 00 16 rw rw rw rw rw rw bit name function bit symbol : clock stop : do not set to this value : two-phase input (1) : f 1 or f 2 (2) b1 0 0 1 1 b0 0 1 0 1 bck0 bck1 rst4 count source select bit channel 7 input select bit it base timer interrupt bit 0: bit 15 overflow 1: bit 14 overflow ch7insel 0: do not reset base timer by matching g1btrr 1: reset base timer by matching g1btrr (3) notes: 1. this setting can be used when bits ud1 to ud0 in the g1bcr1 register are set to 10 2 (two- phase signal processing mode). do not set bits bck1 to bck0 to 10 2 in other modes. 2. when the pclk0 bit in the pclkr register is set to 0, the count source is f 2 cycles. and when the pclk0 bit is set to set to 1, the count source is f 1 cycles. 3. when the rst4 bit is set to 1, set the rst1 bit in the g1bcr1 register to 0. base timer reset cause select bit 4 0: p2 7 /outc1 7 /inpc1 7 pin 1: p1 7 /int5/inpc1 7 /idu pin reserved bit set to 0 (b5-b3) rw b7 b6 b5 b4 b3 b2 b1 b0 0 0 0
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 131 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 13.3 g1dv register and g1bcr1 register divider register symbol address after reset g1dv 032a 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 rw rw function setting range divide f 1 , f 2 or two-phase pulse input by (n+1) for f bt1 clock cycles generation. n: the setting value of the g1dv register 00 16 to ff 16 rst1 0: the base timer is not reset by applying "l" to the int1 pin 1: the base timer is reset by applying "l" to the int1 pin base timer control register 1 symbol address after reset g1bcr1 0323 16 00 16 rw rw rw rw rw rw rw rw bit name function bit symbol b6 0 0 1 1 b5 0 1 0 1 (b0) rst2 bts ud0 ud1 base timer reset cause select bit 1 base timer reset cause select bit 2 counter increment/ decrement control bit 0: base timer is reset 1: base timer starts counting : counter increment mode : counter increment/decrement mode : two-phase pulse signal processing mode : do not set to this value note: 1. the base timer is reset two f bt1 clock cycles after the base timer matches the value set in the g1po0 register. (see figure 13.7 for details on the g1po0 register) when the rst1 bit is set to 1, the value of the g1poj register (j=1 to 7) for the waveform generating function must be set to a value smaller than that of the g1po0 register. when the rst1 bit is set to 1, set the rst4 bit in the g1bcr0 register to 0. reserved bit set to 0 0: the base timer is not reset by matching the g1po0 register 1: the base timer is reset by matching with the g1po0 register (1) reserved bit set to 0 reserved bit set to 0 rw (b3) (b7) base timer start bit 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 132 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 13.4 g1btrr register base timer reset register (1) symbol address after reset g1btrr 0329 16 - 0328 16 undefined rw rw function setting range when enabled by the rst4 bit in the g1bcr0 register, the base timer is reset by matching the g1btrr register setting value and the base timer setting value. 0000 16 to ffff 16 b15 b0 b7 b8 (b7) (b0) note: 1. the g1btrr register reflects the value of the base timer, synchronizing with the count source f bt1 cycles.
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 133 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 13.5 g1tmcr0 to g1tmcr7 registers, and g1tpr6 to g1tpr7 registers time measurement control register j (j=0 to 7) symbol g1tmcr0 to g1tmcr3 g1tmcr4 to g1tmcr7 address 0318 16 , 0319 16 , 031a 16 , 031b 16 031c 16 , 031d 16 , 031e 16 , 031f 16 after reset 00 16 00 16 rw rw rw rw rw rw rw rw rw bit name function bit symbol cts0 cts1 df0 time measurement trigger select bit df1 gate function select bit (2) gt goc pr gsc digital filter function select bit gate function clear select bit (2, 3, 4) 0: gate function is not used 1: gate function is used gate function clear bit (2, 3) prescaler function select bit (2) b1 0 0 1 1 b0 0 1 0 1 : no time measurement : rising edge : falling edge : both edges b3 0 0 1 1 b2 0 1 0 1 : no digital filter : do not set to this value : f bt1 : f 1 or f 2 (1) 0: not cleared 1: the gate is cleared when the base timer matches the g1pok register the gate is cleared by setting the gsc bit to 1 0: not used 1: used notes: 1. when the pclk0 bit in the pclkr register is set to 0, the count source is f 2 cycles. and when the pclk0 bit is set to 1, the count source is f 1 cycles. 2. these bits are in registers g1tmcr6 and g1tmcr7. set all bits 4 to 7 in registers g1tmcr0 to g1tmcr5 to 0. 3. these bits are enabled when the gt bit is set to 1. 4. the goc bit is set to 0 after the gate function is cleared. see figure 13.7 for details on the g1pok register (k=4 when j=6 and k=5 when j=7). b7 b6 b5 b4 b3 b2 b1 b0 time measurement prescale register j (j=6,7) (1) symbol address after reset g1tpr6 to g1tpr7 0324 16 , 0325 16 00 16 rw rw function setting range as the setting value is n, time is measured when- ever a trigger input is counted by n+1 (2) 00 16 to ff 16 notes: 1. the g1tpr6 to g1tpr7 registers reflect the base timer value, synchronizing with the count source f bt1 cycles. 2. the first prescaler, after the pr bit in the g1tmcrj register is changed from 0 (not used) to 1 (used), may be divided by n , rather than n+1 . the subsequent prescaler is divided by n+1 . b7 b0
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 134 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 13.6 g1tm0 to g1tm7 registers, and g1pocr0 to g1pocr7 registers waveform generation control register j (j=0 to 7) symbol address after reset g1pocr0 to g1pocr3 0310 16 , 0311 16 , 0312 16 , 0313 16 0x00 xx00 2 g1pocr4 to g1pocr7 0314 16 , 0315 16 , 0316 16 , 0317 16 0x00 xx00 2 rw rw rw rw rw rw bit name function bit symbol mod0 mod1 operating mode select bit output initial value select bit (4) ivl rld inv 0: "l" output as a default value 1: "h" output as a default value inverse output function select bit (2) : single waveform output mode : sr waveform output mode (1) : phase-delayed waveform output mode : do not set to this value 0: output is not inversed 1: output is inversed b1 0 0 1 1 b0 0 1 0 1 g1poj register value reload timing select bit notes : 1. this setting is enabled only for even channels. in sr waveform output mode, values written to the corresponding odd channel (next channel after an even channel) are ignored. even channels provide waveform output. odd channels provide no waveform output. 2. the inverse output function is the final step in waveform generating process. when the inv bit is set to 1, and "h" signal is provided a default output by setting the ivl bit to 0, and an "l" signal is provided by setting it to 1. 3. in the sr waveform output mode, set not only the even channel but also the correspoinding even channel (next channel after the even channel). 4. to provide either "h" or "l" signal output set in the ivl bit, set the fscj bit in the g1fs register to 0 (select waveform generating function) and ifej bit in the g1fe register to 1 (functions for channel j enabled). then set the ivl bit to 0 or 1. nothing is assigned. if necessary, set to 0. when read, their contents are undefined nothing is assigned. if necessary, set to 0. when read, its content is undefined 0: reloads the g1poj register when value is written 1: reloads the g1poj register when the base timer is reset (b3-b2) (b6) b7 b6 b5 b4 b3 b2 b1 b0 waveform generation register j (j=0 to 7) symbol g1tm0 to g1tm2 g1tm3 to g1tm5 g1tm6 to g1tm7 rw ro function setting range b15 (b7) b8 (b0) address 0301 16 -0300 16, 0303 16 -0302 16, 0305 16 -0304 16 0307 16 -0306 16, 0309 16 -0308 16, 030b 16 -030a 16 030d 16 -030c 16, 030f 16 -030e 16 after reset indeterminte indeterminte indeterminte the base timer value is stored every measurement timing b7 b0
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 135 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 13.7 g1po0 to g1po7 registers waveform generation register j (j=0 to 7) symbol g1po0 to g1po2 g1po3 to g1po5 g1po6 to g1po7 rw rw function setting range b15 (b7) b8 (b0) address 0301 16 -0300 16, 0303 16 -0302 16, 0305 16 -0304 16 0307 16 -0306 16, 0309 16 -0308 16, 030b 16 -030a 16 030d 16 -030c 16, 030f 16 -030e 16 after reset undefined undefined undefined when the rld bit in the g1pocrj register is set to 0, value written is immediately reloaded into the g1poj register for output, for example, a waveform output,reflecting the value. when the rld bit is set to 1, value reloaded while the base timer is reset. the value written can be read until reloaded b7 b0 0000 16 to ffff 16
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 136 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 13.8 g1fs and g1fe registers function enable register (1) symbol address after reset g1fe 0326 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 rw rw rw rw rw rw rw rw rw bit name bit symbol ife0 ife1 ife2 channel 0 function enable bit ife3 ife4 ife5 ife7 function ife6 0 : disable function s for channel j (2) 1 : enable functions for channel j (j=0 to 7) channel 1 function enable bit channel 2 function enable bit channel 3 function enable bit channel 4 function enable bit channel 5 function enable bit channel 6 function enable bit channel 7 function enable bit notes: 1. the g1fe register reflects the base timer value, synchronizing with the count source f bt1 cycles. 2. when functions for the channel j are disabled, each pin functions as an i/o port. function select register symbol address after reset g1fs 0327 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 rw rw rw rw rw rw rw rw rw bit name bit symbol fsc0 fsc1 fsc2 channel 0 time measure- ment/waveform generating function select bit fsc3 fsc4 fsc5 fsc7 function fsc6 0: select the waveform generating function 1: select the time measurement function channel 1 time measure- ment/waveform generating function select bit channel 2 time measure- ment/waveform generating function select bit channel 3 time measure- ment/waveform generating function select bit channel 4 time measure- ment/waveform generating function select bit channel 5 time measure- ment/waveform generating function select bit channel 6 time measure- ment/waveform generating function select bit channel 7 time measure- ment/waveform generating function select bit
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 137 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 13.9 g1ir register interrupt request register (1) symbol address after reset g1ir 0330 16 undefined b7 b6 b5 b4 b3 b2 b1 b0 rw rw rw rw rw rw rw rw rw bit name bit symbol g1ir0 g1ir1 g1ir2 interrupt request, ch0 g1ir3 g1ir4 g1ir5 g1ir7 function g1ir6 0 : no interrupt request 1 : interrupt requested interrupt request, ch1 interrupt request, ch2 interrupt request, ch3 interrupt request, ch4 interrupt request, ch5 interrupt request, ch6 interrupt request, ch7 note: 1. when writing 0 to each bit in the g1ir register, use the following instruction: and, bclr
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 138 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 13.10 g1ie0 and g1ie1 registers interrupt enable register 0 symbol address after reset g1ie0 0331 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 rw rw rw rw rw rw rw rw rw bit name bit symbol g1ie00 g1ie01 g1ie02 interrupt enable 0, ch0 g1ie03 g1ie04 g1ie05 g1ie07 function g1ie06 0 : ic/oc interrupt 0 request disable 1 : ic/oc interrupt 0 request enable interrupt enable 0, ch1 interrupt enable 0, ch2 interrupt enable 0, ch3 interrupt enable 0, ch4 interrupt enable 0, ch5 interrupt enable 0, ch6 interrupt enable 0, ch7 interrupt enable register 1 symbol address after reset g1ie1 0332 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 rw rw rw rw rw rw rw rw rw bit name bit symbol g1ie10 g1ie11 g1ie12 interrupt enable 1, ch0 g1ie13 g1ie14 g1ie15 g1ie17 function g1ie16 0 : ic/oc interrupt 1 request disable 1 : ic/oc interrupt 1 request enable interrupt enable 1, ch1 interrupt enable 1, ch2 interrupt enable 1, ch3 interrupt enable 1, ch4 interrupt enable 1, ch5 interrupt enable 1, ch6 interrupt enable 1, ch7
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 139 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r the timer increments a counter on all edges the timer decrements a counter on all edges p8 0 p8 1 13.1 base timer the base timer is a free-running counter that counts an internally generated count source. table 13.2 lists specifications of the base timer. table 13.3 shows registers associated with the base timer. figure 13.11 shows a block diagram of the base timer. figure 13.12 shows an example of the base timer in counter increment mode. figure 13.13 shows an example of the base timer in counter increment/decre- ment mode. figure 13.14 shows an example of two-phase pulse signal processing mode. table 13.2 base timer specifications item specification count source(f bt1 )f 1 or f 2 divided by (n+1) , two-phase pulse input divided by (n+1) n: determined by the div7 to div0 bits in the g1dv register. n=0 to 255 however, no division when n=0 counting operation the base timer increments the counter value the base timer increments/decrements the counter value two-phase pulse signal processing count start condition the bts bit in the g1bcr1 register is set to 1 ( base timer starts counting) count stop condition the bts bit in the g1bcr1 register is set to 0 (base timer reset) base timer reset condition (1) the value of the base timer matches the value of the g1btrr register (2) the value of the base timer matches the value of g1po0 register. ________ (3) apply a low-level signal ("l") to external interrupt pin,int1 pin value for base timer reset 0000 16 interrupt request the base timer interrupt request is generated: (1) when the bit 14 or bit 15 in the base timer overflows (2) the value of the base timer value matches the value of the base timer reset register read from timer ? the g1bt register indicates a counter value while the base timer is running ? the g1bt register is undefined when the base timer is reset write to timer when a value is written while the base timer is running, the timer counter immediately starts counting from this value. no value can be written while the base timer is reset. selectable function ? counter increment/decrement mode the base timer starts counting from 0000 16 . after incrementing to ffff 16 , the timer counter is then decremented back to 0000 16 . the base timer increments the counter value again when the timer counter reaches 0000 16 . (see figure 13.13 ) ? two-phase pulse processing mode two-phase pulse signals from pins p8 0 and p8 1 are counted (see figure 13.14 )
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 140 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r table 13.3 base timer associated register settings (time measurement function, waveform generation function, communication function) register bit function g1bcr0 bck1 to bck0 select a count source rst4 select base timer reset timing it select the base timer overflow g1bcr1 rst2 to rst1 select base timer reset timing bts used to start the base timer ud1 to ud0 select how to count g1bt - read or write base timer value g1dv - divide ratio of a count source set the following registers to set the rst1 bit to 1 (base timer reset by matching the base timer with the g1po0 register) g1pocr0 mod1 to mod0 set to 00 2 (single-phase waveform output mode) g1po0 - set reset cycle g1fs fsc0 set to 0 (waveform generating function) g1fe ife0 set to 1 (channel operation start) figure 13.11 base timer block diagram (n+1) divider rst4 rst1 rst2 matched with g1btrr matched with g1po0 register base timer b14 b15 base timer overflow request bck1 to bck0 it bts bit in g1bcr1 register two-phase pulse input overflow signal input "l" to int1 pin base timer reset 11 10 0 1 f bt1 note: 1. divider is reset when the bts bit is set to 0. it, rst4, bck1 to bck0: bits in the g1bcr0 register rst2 to rst1: bits in the g1bcr1 register (note 1) f 1 or f 2
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 141 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 13.12 counter increment mode figure 13.13 counter increment/decrement mode ffff 16 8000 16 0000 16 4000 16 c000 16 state of a counter base timer interrupts 1 0 b14 overflow signal 1 0 b15 overflow signal base timer interrupt it=0 in the g1bcr0 register (base timer interrupt generated by the bit 15 overflow) it=1 in the g1bcr0 register (base timer interrupt generated by the bit 14 overflow) the above applies to the following conditions. the rst4 bit in the g1bcr0 register is set to 0 (the base timer is not reset by matching the g1btrr register) the rst1 bit in the g1bcr1 register is set to 0 (the base timer is not reset by matching the g1po0 register) bits ud1 to ud0 in the g1bcr1 register are set to 00 2 (counter increment mode) ffff 16 8000 16 4000 16 c000 16 0000 16 state of a counter 1 0 base timer interrupts b14 overflow signal 1 0 b15 overflow signal base timer interrupt it=0 in the g1bcr0 register (base timer interrupt generated by the bit 15 overflow) it=1 in the g1bcr0 register (base timer interrupt generated by the bit 14 overflow)
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 142 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 13.14 base timer operation in two-phase pulse signal processing mode (1) when the base timer is reset while the base timer increments the counter (2) when the base timer is reset while the base timer decrements the counter ( ) m when selects no division with the divider by (n+1) value of counter min 1 s (note 1) min 1 s m+1 1 2 0 set to 0 at this timing base timer starts counting p8 0 (a-phase) p8 1 (b-phase) int1 (z-phase) set to 1 at this timing min 1 s (1) min 1 s m input waveform value of counter m-1 ffff 16 fffe 16 0 set to 0 at this timing note: 1. 1.5 f bt1 clock cycle or more are required. base timer starts counting p8 0 (a-phase) p8 1 (b-phase) int1 (z-phase) set to ffff 16 at this timing input waveform f bt1 f bt1 ( ) when selects no division with the divider by (n+1)
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 143 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 13.1.1 base timer reset register(g1btrr) the g1btrr register provides the capability to reset the base timer when the base timer count value matches the value stored in the g1btrr register. the g1btrr register is enabled by the rst4 bit in the g1bcr0 register. this function is identical in operation to the g1po0 base timer reset that is enabled by the rst1 bit in the g1bcr0 reigster. if the free-running operation is not selected, the channel 0 can be used for a waveform generation when the base timer is reset by the g1btrr register. do not enable bits rst1 and rst4 simultaneously. figure 13.15 base timer reset operation by base timer reset register figure 13.16 base timer reset operation by g1po0 register _______ figure 13.17 base timer reset operation by int1 note: ________ ________ 1. int1 base timer reset does not generate a base timer interrupt. int1 may generate an interrupt if enabled. base timer g1btrr register (base timer reset register) base timer interrupt rst4 m - 2 m - 1 m m + 1 0000 16 m base timer overflow request (1) note: 1. following conditions are required to generate a base timer overflow request by resetting the base timer. if the it bit is set to 0: 07fff 16 m 0fffe 16 if the it bit is set to 1: 07fff 16 m 0fffe 16 or 0bfff 16 m 0fffe 16 0001 16 base timer g1po0 g1ir0 rst1 m - 2 m - 1 m m + 1 0000 16 m 0001 16 rst2 base timer p8 3 /int1 m - 2 m - 1 m m + 1 0000 16 0001 16
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 144 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 13.2 interrupt operation the ic/oc interrupt contains several request causes. figure 13.18 shows the ic/oc interrupt block dia- gram and table 13.4 shows the ic/oc interrupt assignation. when either the base timer reset request or base timer overflow request is generated, the ir bit in the btic register corresponding to the ic/oc base timer interrupt is set to 1 (with an interrupt request). also when an interrupt request in each eight channels (channel i) is generated, the bit i in the g1ir register is set to 1 (with an interrupt request). at this time, if the bit i in the g1ie0 register is 1 (ic/oc interrupt 0 request enabled), the ir bit in the icoc0ic register corresponding to the ic/oc interrupt 0 is set to 1 (with an interrupt request). and if the bit i in the g1ie1 register is 1 (ic/oc interrupt 1 request enabled), the ir bit in the icoc1ic register corresponding to the ic/oc interrupt 1 is set to 1(with an interrupt request). additionally, because each bit in the g1ir register is not automatically set to 0 even if the interrupt is acknowledged, set to 0 by program. if these bits are left as 1, all ic/oc channel interrupt causes, which are generated after setting the ir bit to 1, will be disabled. figure 13.18 ic/oc interrupt and dma request generation table 13.4 interrupt assignment interrupt interrupt control register ic/oc base timer interrupt btic(0047 16 ) ic/oc interrupt 0 icoc0ic(0045 16 ) ic/oc interrupt 1 icoc0ic(0046 16 ) 13.3 dma support each of the interrupt sources - the eight ic/oc channel interrupts and the one base timer interrupt - are capable of generating a dma request. interrupt select logi c cha nnel 0 to 7 interrupt re quests dma requests (channel 0 to 7) all regi ster are re ad / write g1ie0 g1ir g1ie1 ic/o c interrupt 1 re quest ic/oc interrupt 0 re ques t ic/oc base ti mer interrupt re q uest base ti mer re set request base ti mer overflow re quest base timer interrupt / dma request enable request enable
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 145 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 13.4 time measurement function in synchronization with an external trigger input, the value of the base timer is stored into the g1tmj register (j=0 to 7). table 13.5 shows specifications of the time measurement function. table 13.6 shows register settings associated with the time measurement function. figures 13.19 and 13.20 display opera- tional timing of the time measurement function. figure 13.21 shows operational timing of the prescaler function and the gate function. table 13.5 time measurement function specifications item specification measurement channel channels 0 to 7 selecting trigger input polarity rising edge, falling edge, both edges of the inpc1j pin (1) measurement start condition the ifej bit in the g1fe register should be set to 1 (channels j function enabled) when the fscj bit (j=0 to 7) in the g1fs register is set to 1 (time measurement function selected). measurement stop condition the ifej bit should be set to 0 (channel j function disabled) time measurement timing ? no prescaler : every time a trigger signal is applied ? prescaler (for channel 6 and channel 7): every g1tpr k (k=6,7) register value +1 times a trigger signal is applied interrupt request generation timing the g1iri bit (i=0 to 7) in the interrupt request register (see figure 13.9 ) is set to 1 at time measurement timing inpc1j pin function (1) trigger input pin selectable function ? digital filter function the digital filter samples a trigger input signal level every f 1 , f 2 or f bt1 cycles and passes pulse signal matching trigger input signal level three times ? prescaler function (for channel 6 and channel 7) time measurement is executed every g1tprk register value +1 times a trigger signal is applied ? gate function (for channel 6 and channel 7) after time measurement by the first trigger input, trigger input cannot be accepted. however, while the goc bit in the g1tmcrk register is set to 1 (gate cleared by matching the base timer with the g1pop register (p=4 when k=6, p=5 when k=7)), trigger input can be accepted again by matching the base timer value with the g1pop register setting ? digital debounce function (for channel7) ________ see 13.6.2 digital debounce function for p1 7 /int5/inpc17 and 18.6 digital debounce function for details note: 1. the inpc1 0 to inpc1 7 pins
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 146 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r table 13.6 register settings associated with the time measurement function register bit function g1tmcrj cts1 to cts0 select time measurement trigger df1 to df0 select the digital filter function gt, goc, gsc select the gate function pr select the prescaler function g1tprk - setting value of prescaler g1fs fscj set to 1 (time measurement function) g1fe ifej set to 1 (channel j function enabled) j = 0 to 7 k = 6, 7 bit configurations and function varys with channels used. registers associated with the time measurement function must be set after setting registers associated with the base timer. figure 13.19 time measurement function (1) ffff 16 p p n n m m base timer inpc1j pin input 0000 16 g1tmj register g1irj bit when setting to 0, write 0 by program j = 0 to 7 g1irj bit: bits in the g1ir register set the base timer to 0000 16 (setting the rst1 bit to 1, and bits rst4 and rst2 to 0), when the base timer value matches the g1po0 register setting. the base timer is set to 0000 16 after it reaches the g1po0 register value + 2 . the above applies to the following condition. bits cts1 to cts0 in the g1tmcrj registers are set to 01 2 (rising edge). the pr bit is set to 0 (no prescaler used) and the gt bit is set to 0 (no gate function used). bits rts4, rts2, and rts1 in registers g1bcr0 and g1bcr1 are set to 0 (no base timer reset). bits ud1 to ud0 bits are set to 00 2 (counter increment mode).
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 147 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 13.20 time measurement function (2) 2. no interrupt is generated if the mcu receives a trigger signal when the g1irj bit is set to 1. 1. bits in the g1ir register. 2. input pulse applied to the inpc1j pin requires 1.5 f bt1 clock cycles or more. n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14 n n +5 n+8 n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14 n n+2 n+5 n+8 n+12 delayed by 1 clock f bt1 base timer inpc1j pin input or trigger signal after passing the digital filter g1tmj register (a) when selecting the rising edge as a timer measurement trigger (bits cts1 and cts0 in the g1tmcrj register (j=0 to 7)=01 2 ) g1irj bit (1) write 0 by program if setting to 0 notes : . (2) (b) when selecting both edges as a timer measurement trigger (bits cts1 and cts0 = 11 2 ) maximum 3.5 f 1 or f 2 or f bt1 clock cycles (1) (c) trigger signal when using digital filter (bits df1 to df0 in the g1tmcrj register =10 2 or 11 2 ) signals, which do not match 3 times, are stripped off f bt1 base timer inpc1j pin input or trigger signal after passing the digital filter g1tmj register (2) g1irj bit (1) f 1 or f 2 or f bt1 (1) inpc1j pin trigger signal after passing the digital filter notes : . 1. bits in the g1ir register. however, the value of the g1tmj register is updated. note: 1. f bt1 when bits df1 to df0 are set to 10 2 , and f 1 or f 2 when set to 11 2 . the trigger signal is delayed by the digital filter write 0 by program if setting to 0
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 148 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 13.21 prescaler function and gate function note: 1. bits in the g1ir register. g1irj bit (1) f bt1 f bt1 base timer g1irj bit (2) g1tmj register internal time measurement trigger prescaler (1) (a) with the prescaler function (when the g1tprj register (j = 6, 7) is set to 02 16 , the pr bit in the g1tmcrj (j = 6, 7) register is set to 1) base timer inpc1j pin input or trigger signal after passing the digital filter internal time measurement trigger ifej bit in g1fe register g1pok register match signal gate control signal g1tmj register value of the g1pok register this trigger input is disabled due to gate function . 21 0 ffff 16 0000 16 n-2 n-1 n n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+14 n+ 1 n+13 2 (b) with the gate function (the gate function is cleared by matching the base timer with the g1pok register(k=4,5), the gt bit in the g1tmcrj register is set to 1, the goc bit is set to 1) inpc1j pin input or trigger signal after passing the digital filter set 0 by program if necessary set 0 by program if necessary gate gate gate cleared n+1 +12 n+13 notes: 1. this applies to 2nd or later prescaler cycle after the pr bit in the g1tmcrj register is set to 1 (prescaler used). 2. bits in the g1ir register.
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 149 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 13.5 waveform generating function waveforms are generated when the base timer value matches the g1poj (j=0 to 7) register value. the waveform generating function has the following three modes : ? single-phase waveform output mode ? phase-delayed waveform output mode ? set/reset waveform output (sr waveform output) mode table 13.7 lists registers associated with the waveform generating function. table 13.7 registers related to the waveform generating function settings register bit function g1pocrj mod1 to mod0 select output waveform mode ivl select default value rld select g1poj register value reload timing inv select inverse output g1poj - select timing to output waveform inverted g1fs fscj set to 0 (waveform generating function) g1fe ifej set to 1 (enables function on channel j) j = 0 to 7 bit configurations and functions vary with channels used. registers associated with the waveform generating function must be set after setting registers associated with the base timer.
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 150 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 13.5.1 single-phase waveform output mode output signal level of the outc1j pin becomes high ("h") when the inv bit in the g1pocrj (j=0 to 7) register is set to 0(output is not reversed) and the base timer value matches the g1poj (j=0 to 7) register value. the "h" signal switches to a low-level ("l") signal when the base timer reaches 0000 16 . table 13.8 lists specifications of single-phase waveform mode. figure 13.22 lists an example of single-phase wave- form mode operation. table 13.8 single-phase waveform output mode specifications item specification output waveform ? free-running operation (bits rst1, rst2, and rst4 of registers g1bcr1 and g1bcr0 are set to 0 (no reset)) cycle : default output level width : inverse level width : ? the base timer is cleared to 0000 16 by matching the base timer with either following register (a) g1po0 register (enabled by setting rst1 bit to 1, and rst4 and rst2 bits to 0), or (b) g1btrr register (enabled by setting rst4 bit to 1, and rst2 and rst1 bits to 0) cycle : default output level width : inverse level width : m : setting value of the g1poj register (j=0 to 7), 0001 16 to fffd 16 n : setting value of the g1po0 register or the g1btrr register, 0001 16 to fffd 16 waveform output start condition the ifej bit in the g1fe register is set to 1 (channel j function enabled) waveform output stop condition the ifej bit is set to 0 (channel j function disabled) interrupt request the g1irj bit in the g1ir register is set to 1 when the base timer value matches the g1poj register value (see figure 13.22 ) outc1j pin (1) pulse signal output pin selectable function ? default value set function: set starting waveform output level ? inverse output function: waveform output signal is inversed and provided from the outc1j pin m f bt1 65536-m f bt1 n+2 f bt1 m f bt1 n+2-m f bt1 65536 f bt1 note: 1. pins outc1 0 to outc1 7 .
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 151 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 13.22 single-phase waveform output mode ffff 16 m m f bt1 65536-m f bt1 inverse 65536 f bt1 when setting to 0, write 0 by program base timer (1) free-running operation (the rst4, rst2, and rst1 bits in the g1bcr0 and g1bcr1 registers are set to 0) (2) the base timer is reset when the base timer matches either following register (a) g1po0 (enabled by setting bit rst1 to 1, and bits rst4 and rst2 to 0), or (b) g1btrr (enabled by setting bit rst4 to 1, and bits rst2 and rst1 to 0) 0000 16 outc1j pin g1irj bit g1irj bit j=0 to 7 m : setting value of the g1poj register g1irj bit : bits in the g1ir register outc1j pin ffff 16 m n+2 base timer 0000 16 inverse m f bt1 n+2-m f bt1 inverse n+2 f bt1 return to default output level write 0 by program if setting to 0 return to default output level inverse inverse j=1 to 7 m : setting value of the g1poj register n: setting value of either g1po0 register or g1btrr register g1irj bit : bits in the g1ir register the above applies under the following conditions. -the ivl bit in the g1pocrj register is set to 0 ("l" output as a default value) and the inv bit is set to 0 (not inversed). -bits ud1 to ud0 are set to 00 2 (counter increment mode). the above applies under the following conditions. -the ivl bit in the g1pocrj register is set to 0 ("l" output as a default value) and the inv bit is set to 0 (not inversed). -bits ud1 to ud0 are set to 00 2 (counter increment mode).
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 152 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 13.5.2 phase-delayed waveform output mode output signal level of the outc1j pin is inversed every time the base timer value matches the g1poj register value ( j=0 to 7). table 13.9 lists specifications of phase-delayed waveform mode. figure 13.23 shows an example of phase-delayed waveform mode operation. table 13.9 phase-delayed waveform output mode specifications item specification output waveform ? free-running operation (bits rst1, rst2, and rst4 in registers g1bcr1 and g1bcr0 are set to 0 (no reset)) cycle : "h" and "l" width : ? the base timer is cleared to 0000 16 by matching the base timer with either following register (a) g1po0 register (enabled by setting rst1 bit to 1, and bits rst4 and rst2 to 0), or (b) g1btrr register (enabled by setting rst4 bit to 1, and bits rst2 and rst1 to 0) cycle : "h" and "l" width : n : setting value of either g1po0 register or g1btrr register waveform output start condition the ifej bit in the g1fe register is set to 1 (channel j function enabled) waveform output stop condition the ifej bit is set to 0 (channel j function disabled) interrupt request the g1irj bit in the interrupt request register is set to 1 when the base timer value matches the g1poj register value. (see figure 13.23 ) outc1j pin (1) pulse signal output pin selectable function ? default value set function: set starting waveform output level ? inverse output function : waveform output signal is inversed and provided from the outc1j pin note: 1. pins outc1 0 to outc1 7 . 65536 x 2 f bt1 65536 f bt1 2(n+2) f bt1 n+2 f bt1
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 153 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 13.23 phase-delayed waveform output mode ffff 16 m 65536 f bt1 65536x2 f bt1 0000 16 ffff 16 m n+2 0000 16 65536 f bt1 m f bt1 n+2 f bt1 n+2 f bt1 2(n+2) f bt1 base timer (1) free-running operation (bits rst4, rst2, and rst1 in the registers g1bcr0 and g1bcr1 are set to 0) outc1j pin g1irj bit j=0 to 7 m : setting value of the g1poj register g1irj bit : bits in the g1ir register inverse write 0 by program if setting to 0 inverse (2) base timer is reset when the base timer matches either following register (a) g1po0 (enabled by setting bit rst1 to 1, and bits rst4 and rst2 to 0), or (b) g1btrr (enabled by setting bit rst4 to 1, and bits rst2 and rst1 to 0) g1irj bit outc1j pin base timer write 0 by program if setting to 0 inverse j=1 to 7 m : setting value of the g1poj register n: setting value of either register g1po0 or g1btrr g1irj bit : bits in the g1ir register the above applies under the following conditions. the ivl bit in the g1pocrj register is set to 0 (l output as a default value). the inv bit is set to 0 (not inversed). bits ud1 to ud0 are set to 00 2 (counter increment mode). the above applies under the following conditions. the ivl bit in the g1pocrj register is set to 0 (l output as a default value). the inv bit is set to 0 (not inversed). bits ud1 to ud0 are set to 00 2 (counter increment mode). inverse inverse
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 154 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 13.5.3 set/reset waveform output (sr waveform output) mode output signal level of the outc1j pin becomes high ("h") when the inv bit in the g1pocri (i=0 to 7) is set to 0 (output is not reversed) and the base timer value matches the g1poj register value (j=0, 2, 4, 6). the "h" signal switches to a low-level ("l") signal when the base timer value matches the g1pok (k=j+1) register value. table 13.10 lists specifications of sr waveform mode. figure 13.24 shows an example of the sr waveform mode operation. table 13.10 sr waveform output mode specifications item specification output waveform ? free-running operation (the rst1, rts2, and rst4 bits of the g1bcr1 and g1bcr0 registers are set to 0 (no reset)) cycle : inverse level width (1) : ? the base timer is cleared to 0000 16 by matching the base timer with either following register (a) g1po0 register (enabled by setting rst1 bit to 1, and bits rst4 and rst2 to 0) (2) , or (b) g1btrr register (enabled by setting rst4 bit to 1, and bits rst2 and rst1 to 0) cycle : inverse level width (1) : m : setting value of the g1poj register (j=0, 2, 4, 6 ) n : setting value of the g1pok register (k=j+1) p : setting value of the g1po0 register or g1btrr register value range of m, n, p: 0001 16 to fffd 16 waveform output start condition bits ifej and ifek in the g1fe register are set to 1 (channel j function enabled) waveform output stop condition bits ifej and ifek are set to 0 (channel j function disabled) interrupt request the g1irj bit in the g1ir register is set to 1 when the base timer value matches the g1poj register value. the g1irk bit in the interrupt request register is set to 1 when the base timer value matches the g1pok register value (see figure 13.24 ) outc1j pin (3) pulse signal output pin selectable function ? default value set function : set starting waveform output level ? inverse output function: waveform output signal is inversed and provided from the outc1j pin notes: 1. the odd channel's waveform generating register must have greater value than the even channel's. 2. when the g1po0 register resets the base timer, the channel 0 and channel 1 sr waveform generating functions are not available. 3. pins outc1 0 , outc1 2 , outc14, outc1 6 . 65536 f bt1 n-m f bt1 p+2 f bt1 n-m f bt1
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 155 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 13.24 set/reset waveform output mode ffff 16 m n n-m f bt1 65536 f bt1 0000 16 ffff 16 m p+2 n 0000 16 65536-n+m f bt1 n-m f bt1 p+2-n+m f bt1 p+2 f bt1 (1) free-running operation (bits rst2 and rst1 in the g1bcr0 register and the rst4 bit in the g1bcr1 register are set to 0) j=0, 2, 4, 6 k=j+1 m : setting value of the g1poj register n: setting value of the g1pok register g1irj, g1irk bits: bits in the g1ir register inverse write 0 by program if setting to 0 inverse (2) base timer is reset when the base timer matches either following register (a) g1po0 (enabled by setting bit rst1 to 1, and bits rst4 and rst2 to 0), or (b) g1btrr (enabled by setting bit rst4 to 1, and bits rst2 and rst1 to 0) j=2, 4, 6 k=j+1 m : setting value of the g1poj register n: setting value of the g1pok register p: setting value of either register g1po0 or g1btrr g1irj, g1irk bits: bits in the g1ir register return to default output level inverse return to default output level write 0 by program if setting to 0 when setting to 0, write 0 by program base timer outc1j pin g1irj bit g1irk bit base timer outc1j pin g1irj bit g1irk bit the above applies under the following conditions. the ivl bit in the g1pocrj register is set to 0 (l output as a default value). the inv bit is set to 0 (not inversed). bits ud1 and ud0 are set to 00 2 (counter increment mode). the above applies under the following conditions. the ivl bit in the g1pocrj register is set to 0 (l output as a default value). the inv bit is set to 0 (not inversed). bits ud1 and ud0 are set to 00 2 (counter increment mode).
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 156 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r pin ife fsc mod1 mod0 port direction port data p2 7 /inpc1 7 / 0 x x x determined by pd2 7 p2 7 outc1 7 1 1 x x determined by pd2 7 , input to inpc1 7 is always active p2 7 or inpc1 7 1 0 0 0 single-phase waveform output outc1 7 1 0 0 1 determined by pd2 7 , sr waveform output mode p2 7 1 0 1 0 phase-delayed waveform output outc1 7 p2 6 /inpc1 6 / 0 x x x determined by pd2 6 p2 6 outc1 6 1 1 x x determined by pd2 6 , input to inpc1 6 is always active p2 6 or inpc1 6 1 0 0 0 single-phase waveform output outc1 6 1 0 0 1 sr waveform output outc1 6 1 0 1 0 phase-delayed waveform output outc1 6 p2 5 /inpc1 5 / 0 x x x determined by pd2 5 p2 5 outc1 5 1 1 x x determined by pd2 5 , input to inpc1 5 is always active p2 5 or inpc1 5 1 0 0 0 single-phase waveform output outc1 5 1 0 0 1 determined by pd2 5 , sr waveform output mode p2 5 1 0 1 0 phase-delayed waveform output outc1 5 p2 4 /inpc1 4 / 0 x x x determined by pd2 4 p2 4 outc1 4 1 1 x x determined by pd2 4 , input to inpc1 4 is always active p2 4 or inpc1 4 1 0 0 0 single-phase waveform output outc1 4 1 0 0 1 sr waveform output outc1 4 1 0 1 0 phase-delayed waveform output outc1 4 p2 3 /inpc1 3 / 0 x x x determined by pd2 3 p2 3 outc1 3 1 1 x x determined by pd2 3 , input to inpc1 3 is always active p2 3 or inpc1 3 1 0 0 0 single-phase waveform output outc1 3 1 0 0 1 determined by pd2 3 , sr waveform output mode p2 3 1 0 1 0 phase-delayed waveform output outc1 3 p2 2 /inpc1 2 / 0 x x x determined by pd2 2 p2 2 outc1 2 1 1 x x determined by pd2 2 , input to inpc1 2 is always active p2 2 or inpc1 2 1 0 0 0 single-phase waveform output outc1 2 1 0 0 1 sr waveform output outc1 2 1 0 1 0 phase-delayed waveform output outc1 2 p2 1 /inpc1 1 / 0 x x x determined by pd2 1 p2 1 outc1 1 1 1 x x determined by pd2 1 , input to inpc1 1 is always active p2 1 or inpc1 1 1 0 0 0 single-phase waveform output outc1 1 1 0 0 1 determined by pd2 1 , sr waveform output mode p2 1 1 0 1 0 phase-delayed waveform output outc1 1 p2 0 /inpc1 0 / 0 x x x determined by pd2 0 p2 0 outc1 0 1 1 x x determined by pd2 0 , input to inpc1 0 is always active p2 0 or inpc1 0 1 0 0 0 single-phase waveform output outc1 0 1 0 0 1 sr waveform output outc1 0 1 0 1 0 phase-delayed waveform output outc1 0 13.6 i/o port function select the value in the g1fe and g1fs registers decides which ic/oc pin to be an input or output pin. in sr waveform generating mode, two channels, a set of even channel and odd channel, are used every output waveform, however, the waveform is output from an even channel only. in this case, the correspond- ing pin to the odd channel can be used as an i/o port. table 13.11 pin setting for time measurement and waveform generating functions ife: ifej (j=0 to 7) bits in the g1fe register. fsc: fscj (j=0 to 7) bits in the g1fs register. mod2 to mod1: bits in the g1pocrj (j=0 to 7) register.
13. timer s ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 157 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 13.6.1 inpc17 alternate input pin selection the input capture pin for ic/oc channel 7 can be assigned to one of two package pins. the ch7insel ________ bit in the g1bcr0 register selects ic/oc inpc1 7 from p2 7 /outc1 7 /inpc1 7 or p17/int5/inpc1 7 /idu. ________ 13.6.2 digital debounce function for pin p17/int5/inpc17 ________ ________ the int5/inpc1 7 input from the p1 7 /int5/inpc1 7 /idu pin has an effective digital debounce function against a noise rejection. refer to 18.6 digital debounce function for this detail.
14.serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 158 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 14. serial i/o note the si/o4 interrupt of peripheral function interrupt is not available in the 64-pin package. serial i/o is configured with five channels: uart0 to uart2, si/o3 and si/o4. 14.1 uarti (i=0 to 2) uarti each have an exclusive timer to generate a transfer clock, so they operate independently of each other. figure 14.1 shows the block diagram of uarti. figures 14.2 and 14.3 shows the block diagram of the uarti transmit/receive. uarti has the following modes: ? clock synchronous serial i/o mode ? clock asynchronous serial i/o mode (uart mode). ? special mode 1 (i 2 c bus mode): uart2 ? special mode 2: uart2 ? special mode 3 (bus collision detection function, iebus mode): uart2 ? special mode 4 (sim mode): uart2 figures 14.4 to 14.9 show the uarti-associated registers. refer to tables 14.2, 14.6, 14.11, 14.12, 14.16, 14.17 , and 14.19 to set the registers in individual mode.
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 159 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 14.1 block diagram of uarti (i = 0 to 2) clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) clock source selection internal external cts/rts disabled cts/rts selected rxd 0 1 / (n 0 +1) 1/16 1/16 1/2 u0brg registe r clk 0 cts 0 / rts 0 f 1sio or f 2sio f 8sio f 32sio v cc rts 0 cts 0 txd 0 (uart0) clk1 to clk0 00 2 01 2 10 2 ckdir=0 ckdir=1 ckpol ckdir=0 ckdir= 1 crs=1 crs=0 crd=0 crd=1 rcsp=0 rcsp=1 v cc crd=0 crd=1 uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) receive clock transmit clock reception control circuit transmission control circuit transmit/ receive unit clk polarity reversing circuit cts/rts disabled cts 0 from uart 1 uart reception clock synchronous type rxd 1 txd 1 (uart1) 1 / (n 1 +1) 1/16 1/16 1/2 u1brg register clk 1 f 1sio or f 2sio f 8sio f 32sio clk1 to clk0 00 2 01 2 10 2 ckdir=0 ckdir=1 ckpol ckdir=0 ckdir= 1 v cc crd=0 crd=1 clkmd0=0 clkmd1=0 crs=1 crs=0 rcsp=0 rcsp=1 clkmd0=1 clkmd1=1 clock source selection internal external uart transmission clock synchronous type clock synchronous type (when internal clock is selected) receive clock transmit clock reception control circuit transmission control circuit transmit/ receive unit clock synchronous type (when external clock is selected) clock synchronous type (when internal clock is selected) clk polarity reversing circuit rts1 cts1 clock output pin select cts/rts disable d cts/rts disable d cts/rts selecte d cts 0 from uart 0 cts 1 / rts 1 / cts 0 / clks 1 i = 0 to 2 n i : values set to the uibrg register smd2 to smd0, ckdir: bists in the uimr register clk1 to clk0, ckpol, crd, crs: bits in the uic0 register clkmd0, clkmd1, rcsp: bits in the ucon register rxd 2 clk 2 cts 2 / rts 2 rts 2 cts 2 txd 2 (uart2) 1 / (n 2 +1) 1/16 1/16 1/2 u2brg registe r f 1sio or f 2sio f 8sio f 32sio clk1 to clk0 00 2 01 2 10 2 ckdir=0 ckdir=1 ckpol ckdir=0 ckdir= 1 crs=1 crs=0 v cc crd=0 crd=1 reception control circuit transmission control circuit uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) receive clock transmit clock rxd polarity reversing circuit internal external clock source selection txd polarity reversing circuit transmit/ receive unit clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) clk polarity reversing circuit cts/rts disabled cts/rts disabled cts/rts selecte d main clock, pll clock, or on-chip oscillator clock 1/2 1/8 1/4 f 1sio f 2sio f 8sio f 32sio f 1sio or f 2sio pclk1=1 pclk1=0
14.serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 160 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 14.2 block diagram of uarti (i = 0, 1) transmit/receive unit sp sp pa r 2sp 1sp uart uart (7 bits) uart (8 bits) uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type txdi uarti transmit register par enabled par disabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sp: stop bit par: parity bit uarti transmit buffer register msb/lsb conversion circuit uart (8 bits) uart (9 bits) clock synchronous type uarti receive buffer register uarti receive registe r 2sp 1sp stps=0 par enabled par disabled uart uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type uart (7 bits) uart (8 bits ) rxdi clock synchronous type uart (8 bits) uart (9 bits) address 03a6 16 address 03a7 16 address 03ae 16 address 03af 16 address 03a2 16 address 03a3 16 address 03aa 16 address 03ab 16 data bus low-order bit s msb/lsb conversion circuit d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 0000000 sp sp par 0 data bus high-order bits stps=1 prye=0 prye=1 stps=0 stps=1 prye=0 prye=1 smd2 to smd0, stps, prye, iopol, ckdir : bits in the uimr
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 161 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 14.3 block diagram of uart2 transmit/receive unit sp sp pa r 2sp 1sp uart uart (7 bits) uart (8 bits) uart(7 bits) uart (9 bits) clock synchronous type clock synchronous type data bus low-order bits txd2 uarti transmit registe r par disabled par enabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 uart2 transmit buffer register uart (8 bits) uart (9 bits) clock synchronous type uart2 receive buffer registe r uarti receive registe r 2sp 1sp uart (7 bits) uart (8 bits) uart(7 bits) uart (9 bits) clock synchronous type clock synchronous type rxd2 uart (8 bits) uart (9 bits) address 037e 16 address 037f 16 address 037a 16 address 037b 16 data bus high-order bit s d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 0000000 sp sp par 0 reverse no revers e error signal output circui t rxd data reverse circuit error signal output enable error signal output disable reverse no reverse logic reverse circuit + msb/lsb conversion circuit logic reverse circuit + msb/lsb conversion circuit par enabled par disabled uart clock synchronous type txd data reverse circuit sp: stop bit par: parity bit stps=0 stps=1 prye=0 prye=1 stps=0 stps=1 prye=0 prye=1 iopol=0 iopol=1 iopol =0 iopol =1 u2ere =0 u2ere =1 smd2 to smd0, stps, prye, iopol, ckdir : bits in the u2mr register u2ere : bits in the u2c1 register
14.serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 162 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 14.4 u0tb to u2tb, u0rb to u2rb, u0brg to u2brg registers (b15) b7 b0 (b8) b7 b0 uarti transmit buffer register (i=0 to 2) (1) function transmit data nothing is assigned. if necessary, set to 0. when read, their contents are undefined symbol address after reset u0tb 03a3 16 -03a2 16 undefined u1tb 03ab 16 -03aa 16 undefined u2tb 037b 16 -037a 16 undefined notes: 1. use mov instruction to write to this register. rw wo b7 uarti baud rate generation register (i=0 to 2) (1, 2, 3) b0 symbol address after reset u0brg 03a1 16 undefined u1brg 03a9 16 undefined u2brg 0379 16 undefined function assuming that set value = n, uibrg divides the count source by n + 1 setting range notes: 1. write to this register while serial i/o is neither transmitting nor receiving. 2. use mov instruction to write to this register. the transfer clock is shown below when the setting value in the uibrg register is set as n. (1) when the ckdir bit in the uimr register to 0 (internal clock) ? clock synchronous serial i/o mode : fj/(2(n+1)) ? clock asynchronous serial i/o (uart) mode : fj/(16(n+1)) (2) when the ckdir bit in the uimr register to 1 (external clock) ? clock synchronous serial i/o mode : f ext ? clock asynchronous serial i/o (uart) mode : f ext /(16(n+1)) fj : f1sio, f2sio, f8sio, f32sio f ext : input from clki pin 3. set the uibrg register after setting bits clk1 and clk0 in the registers uic0. rw wo (b15) symbol address after reset u0rb 03a7 16 -03a6 16 undefined u1rb 03af 16 -03ae 16 undefined u2rb 037f 16 -037e 16 undefined b7 b0 (b8) b7 b0 uarti receive buffer register (i=0 to 2) function bit name bit symbol 0 : no framing error 1 : framing error found 0 : no parity error 1 : parity error found 0 : no error 1 : error found oer fer per sum overrun error flag (1) framing error flag (1) parity error flag (1) error sum flag (1) 0 : no overrun error 1 : overrun error found abt arbitration lost detecting flag (2) 0 : not detected 1 : detected (b7-b0) (b10-b9) (b8) nothing is assigned. if necessary, set to 0. when read, their contents are undefined rw ro rw ro ro ro ro ro 00 16 to ff 16 receive data (d 8 ) receive data (d 7 to d 0 ) notes: 1. when the smd2 to smd0 bits in the uimr register are set to 000 2 (serial i/o disabled) or the re bit in the uic1 register is set to 0 (reception disabled), all bits sum, per, fer and oer are set to 0 (no error). the sum bit is set to 0 (no error) when all of the per, fer and oer bits are set to 0 (no error). also, bits per and fer are set to 0 by reading the lower byte of the uirb register. 2. the abt bit is set to 0 by setting to 0 by program. (writing 1 has no effect.) nothing is assigned at the bit 11 in th e u0rb and u1rb registers. if necessary, set to 0. when read, its content is 0.
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 163 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 14.5 u0mr to u2mr registers uarti transmit/receive mode register (i=0, 1) b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol ckdir smd1 smd0 serial i/o mode select bit (2) smd2 internal/external clock select bit stps pry prye (b7) parity enable bit 0 : internal clock 1 : external clock (1) stop bit length select bit odd/even parity select bit reserve bit 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled b2 b1 b0 effective when prye = 1 0 : odd parity 1 : even parity set to 0 function rw rw rw rw rw rw rw rw rw uart2 transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol ckdir smd1 smd0 serial i/o mode select bit (2) smd2 internal/external clock select bit stps pry prye iopol parity enable bit 0 : internal clock 1 : external clock (1) stop bit length select bit odd/even parity select bit txd, rxd i/o polarity reverse bit 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled b2 b1 b0 effective when prye = 1 0 : odd parity 1 : even parity 0 : no reverse 1 : reverse function rw rw rw rw rw rw rw rw rw 0 symbol address after reset u2mr 0378 16 00 16 notes: 1. set the corresponding port direction bit for each clki pin to 0 (input mode). 2. to receive data, set the corresponding port direction bit for each rxdi pin to 0. symbol address after reset u0mr, u1mr 03a0 16 , 03a8 16 00 16 notes: 1. set the corresponding port direction bit for each clk2 pin to 0 (input mode). 2. to receive data, set the corresponding port direction bit for each rxd2 pin to 0 (input mode). 3. set the corresponding port direction bit for scl 2 and sda 2 pins to 0 (input mode). 0 0 0 : serial i/o disabled 0 0 1 : clock synchronous serial i/o mode 0 1 0 : i 2 c bus mode (3) 1 0 0 : uart mode transfer data 7 bit long 1 0 1 : uart mode transfer data 8 bit long 1 1 0 : uart mode transfer data 9 bits long do not set the value other than the above 0 0 0 : serial i/o disabled 0 0 1 : clock synchronous serial i/o mode 1 0 0 : uart mode transfer data 7 bit long 1 0 1 : uart mode transfer data 8 bit long 1 1 0 : uart mode transfer data 9 bit long do not set the value other than the above
14.serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 164 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r uarti transmit/receive control rregister 0 (i=0 to 2) symbol address after reset u0c0 to u2c0 03a4 16 , 03ac 16 , 037c 16 00001000 2 b7 b6 b5 b4 b3 b2 b1 b0 function txept clk1 clk0 crs crd nch ckpol brg count source select bit (7) transmit register empty flag 0 : transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : transmit data is output at rising edge of transfer clock and receive data is input at falling edge clk polarity select bit cts/rts function select bit cts/rts disable bi t data output select bit (5) 0 0 : f 1sio or f 2sio is selected 0 1 : f 8sio is selected 1 0 : f 32sio is selected 1 1 : do not set b1 b0 0 : lsb first 1 : msb first 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0 : cts/rts function enabled 1 : cts/rts function disabled (p6 0 , p6 4 and p7 3 can be used as i/o ports) (6) 0 : txd2/sda2 and scli pins are cmos output 1 : txd2/sda2 and scli pins are n-channel open-drain output (4) uform transfer format select bit (2) effective when crd is set to 0 0 : cts function is selected (1) 1 : rts function is selected bit name bit symbol rw rw rw rw rw rw rw rw ro (3) notes: 1. set the corresponding port direction bit for each ctsi pin to 0 (input mode). 2. effective when bits smd2 to smd0 in the umr register to 001 2 (clock synchronous serial i/o mode) or 010 2 (uart mode transfer data 8 bits long). set the uform bit to 1 when bits smd2 to smd0 are set to 101 2 (i 2 c bus mode) and 0 when they are set to 100 2. 3. cts 1 /rts 1 can be used when the clkmd1 bit in the ucon register is set to 0 (only clk 1 output) and the rcsp bit in the ucon register is set to 0 (cts 0 /rts 0 not separated). 4. sda2 and scl2 are effective when i = 2. 5. when bits smd2 to smd in the uimr regiser are set to 000 2 (serial i/o disable), do not set nch bit to 1 (txdi/sda2 and scl2 pins are n-channel open-drain output). 6. when the u1map bit in pacr register is 1 (p7 3 to p7 0 ), p7 0 functions as cts/rts pin in uart1. 7. when the clk1 and clk0 bit settings are changed, set the uibrg register. uart transmit/receive control register 2 symbol address after reset ucon 03b0 16 x0000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol rw function clkmd0 clkmd1 nothing is assigned. if necessary, set to 0. when read, the content is undefined u0irs u1irs u0rrm u1rrm rcsp (b7) rw rw rw rw rw rw rw 0 : output from clk1 only 1 : transfer clock output from multiple pins function selected effective when the clkmd1 bit is set to 1 0 : clock output from clk1 1 : clock output from clks1 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : continuous receive mode disabled 1 : continuous receive mode enable 0 : continuous receive mode disabled 1 : continuous receive mode enabled uart1 transmit interrupt cause select uart0 continuous receive mode enable bit uart0 transmit interrupt cause select bit uart1 continuous receive mode enable bit uart1 clk/clks select bit 0 uart1 clk/clks select bit 1 (1) separate uart0 cts/rts bit 0 : cts/rts shared pin 1 : cts/rts separated (p6 4 pin functions as cts 0 pin ) (2) notes: 1. when using multiple transfer clock output pins, make sure the following conditions are met:set the ckdir bit in the u1mr register to 0 (internal clock) 2. when the u1map bit in pacr register is set to 1 (p7 3 to p7 0 ), p7 0 pin functions as cts 0 pin. figure 14.6 u0c0 to u2c0 and ucon registers
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 165 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 14.7 u0c1 to u2c1 register, and pacr register uarti transmit/receive control register 1 (i=0, 1) symbol address after reset u0c1, u1c1 03a5 16 ,03ad 16 00000010 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol rw function te ti re ri transmit enable bit receive enable bit receive complete flag transmit buffer empty flag 0 : transmission disabled 1 : transmission enabled 0 : data present in uitb register 1 : no data present in uitb register 0 : reception disabled 1 : reception enabled 0 : no data present in uirb register 1 : data present in uirb register nothing is assigned. if necessary, set to 0. when read, the content is 0 uart2 transmit/receive control register 1 symbol address after reset u2c1 037d 16 00000010 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol function te ti re ri transmit enable bit receive enable bit receive complete flag transmit buffer empty flag 0 : transmission disabled 1 : transmission enabled 0 : reception disabled 1 : reception enabled u2irs uart2 transmit interrupt cause select bit 0 : transmit buffer empty (ti = 1) 1 : transmit is completed (txept = 1) u2rrm uart2 continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enabled data logic select bit 0 : no reverse 1 : reverse u2lch u2ere error signal output enable bit 0 : output disabled 1 : output enabled rw rw ro ro rw rw rw rw rw rw rw ro ro (b7-b4) 0 : data present in u2tb register 1 : no data present in u2tb register 0 : no data present in u2rb register 1 : data present in u2rb register pin assignment control register (1) symbpl address after reset pacr 025d 16 00 16 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 pin enabling bit rw (b6-b3) 010 : 64 pin 011 : 80 pin all other values are reserved. do not use. pacr0 pacr1 pacr2 rw rw reserved bits u1map uart1 pin remapping bit uart1 pins assigned to 0 : p6 7 to p6 4 1 : p7 3 to p7 0 rw note: 1. set the pacr register by the next instruction after setting the prc2 bit in the prcr register to 1(write enable). nothing is assigned. if necessary, set to 0. when read, the content is 0
14.serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 166 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r uart2 special mode register 2 symbol address after reset u2smr2 0376 16 x0000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol rw function stac swc2 sdhi i c bus mode select bit 2 scl 2 wait output bit 0 : disabled 1 : enabled sda 2 output stop bit uart initialization bit clock-synchronous bit refer to table 14.13 0 : disabled 1 : enabled iicm2 csc swc als 0 : disabled 1 : enabled sda 2 output disable bit scl 2 wait output bit 2 0: enabled 1: disabled (high impedance) 0 : disabled 1 : enabled 0: transfer clock 1: ? l ? output 2 nothing is assigned. if necessary, set to 0. when read, the content is undefined rw rw rw rw rw rw rw (b7) uart2 special mode register symbol address after reset u2smr 0377 16 x0000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol function abscs acse sss i 2 c mode select bit bus busy flag 0 : stop condition detected 1 : start condition detected (busy) bus collision detect sampling clock select bit arbitration lost detecting flag control bit 0 : other than i 2 c mode 1 : i 2 c mode 0 : update per bit 1 : update per byte iicm abc bbs 0 : not synchronized to rxd 2 1 : synchronized to rxd 2 (2) set to 0 transmit start condition select bit 0 : rising edge of transfer clock 1 : underflow signal of timer a0 auto clear function select bit of transmit enable bit 0 : no auto clear function 1 : auto clear at occurrence of bus collision notes: 1: the bbs bit is set to 0 by writing 0 by program. (writing 1 has no effect). 2: when a transfer begins, the sss bit is set to 0 (not synchronized to rxd 2 ). (1) nothing is assigned. if necessary, set to 0. when read, the content is undefined rw rw rw rw rw rw rw rw (b7) 0 (b3) reserved bit figure 14.8 u2smr and u2smr2 registers
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 167 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 14.9 u2smr3 and u2smr4 registers uart2 special mode register 3 symbol address after reset u2smr3 0375 16 000x0x0x 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol function dl2 sda 2 digital delay setup bit (1, 2 ) dl0 dl1 0 0 0 : without delay 0 0 1 : 1 to 2 cycle(s) of u2brg count source 0 1 0 : 2 to 3 cycles of u2brg count source 0 1 1 : 3 to 4 cycles of u2brg count source 1 0 0 : 4 to 5 cycles of u2brg count source 1 0 1 : 5 to 6 cycles of u2brg count source 1 1 0 : 6 to 7 cycles of u2brg count source 1 1 1 : 7 to 8 cycles of u2brg count source nothing is assigned. if necessary, set to 0. when read, the content is undefined b7 b6 b5 0 : without clock delay 1 : with clock delay clock phase set bit 0 : clk 2 is cmos output 1 : clk 2 is n-channel open drain output clock output select bit ckph nodc rw rw rw rw rw rw (b0) nothing is assigned. if necessary, set to 0. when read, the content is undefined nothing is assigned. if necessary, set to 0. when read, the content is undefined (b2) (b4) notes: 1. bits dl2 to dl0 are used to generate a delay in sda output by digital means during i 2 c bus mode. in other than i 2 c bus mode, set these bits to 000 2 (no delay). 2. the amount of delay varies with the load on pins scl2 and sda2. also, when using an external clock, the amount of delay increases by about 100 ns. uart2 special mode register 4 symbol address after reset u2smr4 0374 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol rw function ackc sclhi swc9 start condition generate bit (1) stop condition generate bit (1) 0 : clear 1 : start scl 2 ,sda 2 output select bit ack data bit restart condition generate bit (1) 0 : clear 1 : start 0 : clear 1 : start stareq rstareq stpreq ackd 0 : start and stop conditions not output 1 : start and stop conditions output scl 2 output stop enable bit ack data output enable bit 0 : disabled 1 : enabled 0 : ack 1 : nack 0 : serial i/o data output 1 : ack data output note: 1. set to 0 when each condition is generated. stspsel 0 : scl 2 ? l ? hold disabled 1 : scl 2 ? l ? hold enabled scl 2 wait bit 3 rw rw rw rw rw rw rw rw
14.serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 168 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 14.1.1 clock synchronous serial i/o mode the clock synchronous serial i/o mode uses a transfer clock to transmit and receive data. table 14.1 lists the specifications of the clock synchronous serial i/o mode. table 14.2 lists the registers used in clock synchronous serial i/o mode and the register values set. item specification transfer data format ? transfer data length: 8 bits transfer clock ? the ckdir bit in the uimr(i=0 to 2) register is set to 0 (internal clock) : fj/ (2(n+1)) fj = f 1sio , f 2sio , f 8sio , f 32sio . n: setting value of uibrg register 00 16 to ff 16 ? ckdir bit is set to 1 (external clock ) : input from clki pin transmission, reception control _______ _______ _______ _______ ? selectable from cts function, rts function or cts/rts function disable transmission start condition ? before transmission can start, the following requirements must be met (1) _ the te bit in the uic1 register is set to 1 (transmission enabled) _ the ti bit in the uic1 register is set to 0 (data present in uitb register) _______ _______ _ if cts function is selected, input on the ctsi pin is set to ? l ? reception start condition ? before reception can start, the following requirements must be met (1) _ the re bit in the uic1 register is set to 1 (reception enabled) _ the te bit in the uic1 register is set to 1 (transmission enabled) _ the ti bit in the uic1 register is set to 0 (data present in the uitb register) ? for transmission, one of the following conditions can be selected _ the uiirs bit (3) is set to 0 (transmit buffer empty): when transferring data from the uitb register to the uarti transmit register (at start of transmission) _ the uiirs bit is set to 1 (transfer completed): when the serial i/o finished sending data from the uarti transmit register ? for reception when transferring data from the uarti receive register to the uirb register (at completion of reception) error detection ? overrun error (2) this error occurs if the serial i/o started receiving the next data before reading the uirb register and received the 7th bit in the the next data select function ? clk polarity selection transfer data input/output can be chosen to occur synchronously with the rising or the falling edge of the transfer clock ? lsb first, msb first selection whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected ? continuous receive mode selection reception is enabled immediately by reading the uirb register ? switching serial data logic (uart2) this function reverses the logic value of the transmit/receive data ? transfer clock output from multiple pins selection (uart1) the output pin can be selected in a program from two uart1 transfer clock pins that have been set _______ _______ ? separate cts/rts pins (uart0) _________ _________ cts 0 and rts 0 are input/output from separate pins ? uart1 pin remapping selection the uart1 pin can be selected from the p6 7 to p6 4 or p7 3 to p7 0 interrupt request generation timing table 14.1 clock synchronous serial i/o mode specifications notes: 1. when an external clock is selected, the conditions must be met while if the ckpol bit in the uic0 register is set to 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the high state; if the ckpol bit in the uic0 register is set to 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state. 2. if an overrun error occurs, bits 8 to 0 in the uirb register (i = 0 to 2) are undefined. the ir bit in the siric register remains unchanged. 3. the u0irs and u1irs bits respectively are the bits 0 and 1 in the ucon register; the u2irs bit is bit 4 in the u2c1 register.
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 169 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r table 14.2 registers to be used and settings in clock synchronous serial i/o mode register bit function uitb (3) 0 to 7 set transmission data uirb (3) 0 to 7 reception data can be read oer overrun error flag uibrg 0 to 7 set a transfer rate uimr (3) smd2 to smd0 set to 001 2 ckdir select the internal clock or external clock iopol(i=2) (4) set to 0 uic0 clk1 to clk0 select the count source for the uibrg register crs _______ _______ select cts or rts to use txept transmit register empty flag crd _______ _______ enable or disable the cts or rts function nch select txdi pin output mode ckpol select the transfer clock polarity uform select the lsb first or msb first uic1 te set this bit to 1 to enable transmission/reception ti transmit buffer empty flag re set this bit to 1 to enable reception ri reception complete flag u2irs (1) select the source of uart2 transmit interrupt u2rrm (1) set this bit to 1 to use uart2 continuous receive mode u2lch (3) set this bit to 1 to use uart2 inverted data logic u2ere (3) set to 0 u2smr 0 to 7 set to 0 u2smr2 0 to 7 set to 0 u2smr3 0 to 2 set to 0 nodc select clock output mode 4 to 7 set to 0 u2smr4 0 to 7 set to 0 ucon u0irs, u1irs select the source of uart0/uart1 transmit interrupt u0rrm, u1rrm set this bit to 1 to use continuous receive mode clkmd0 select the transfer clock output pin when clkmd1 is set to 1 clkmd1 set this bit to 1 to output uart1 transfer clock from two pins rcsp _________ set this bit to 1 to accept as input the uart0 cts 0 signal from the p6 4 pin 7 set to 0 notes: 1. set bits 5 and 4 in registers u0c1 and u1c1 to 0. bits u0irs, u1irs, u0rrm, and u1rrm are in the ucon register. 2. not all register bits are described above. set those bits to 0 when writing to the registers in clock synchronous serial i/o mode. 3. set bits 7 and 6 in registers u0c1 and u1c1 to 0. 4. set the bit 7 in registers u0mr and u1mr to 0. i=0 to 2
14.serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 170 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r table 14.3 lists pin functions for the case where the multiple transfer clock output pin select function is deselected. table 14.4 lists the p6 4 pin functions during clock synchronous serial i/o mode. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs an ? h ? . (if the n-channel open-drain output is selected, this pin is in a high-impedance state.) table 14.3 pin functions ( when not select multiple transfer clock output pin function ) (1) table 14.4 p6 4 pin functions (1) pin name function method of selection txdi (i = 0 to 2) (p6 3 , p6 7 , p7 0 ) serial data output serial data input transfer clock output transfer clock in put i/o por t (outputs dummy data when performing reception only) rxdi (p6 2 , p6 6 , p7 1 ) clk i (p6 1 , p6 5 , p7 2 ) set the ckdir bit in the uimr register to 0 set the ckdir bit in the uimr register to 1 set the pd6_1 bit and pd6_5 bit in the pd6 register, and the pd7_2 bit in the pd7 register to 0 set the pd6_2 bit and pd6_6 bit in the pd6 register, and pd7_1 bit in the pd7 register to 0 (can be used as an in put port when performing transmission only) set the crd bit in the uic0 register to 0 set the crs bit in the uic0 register to 0 set the pd6_0 bit an d pd6_4 bit in the pd6 register is set to 0, the pd7_3 bit in the pd7 register to 0 set the crd bit in the uic0 register to 0 set the crs bit in the uic0 register to 1 set the crd bit in the uic0 register to 1 cts in put rts output ctsi/rtsi (p6 0 , p6 4 , p7 3 ) note: 1: when the u1map bit in pacr register is 1 (p7 3 to p7 0 ), uart1 pin is assgined to p7 3 to p7 0 . pin fun ction bit set value u1c0 register ucon register pd6 register crd crs rcsp clkmd1 clkmd0 pd6_4 p6 4 1 0 0 input: 0, output: 1 cts 1 000 0 rts 1 10 0 cts 0 (2 ) 0 clks 1 0 0 00 1 1 0 1 (3) notes: 1. when the u1map bit in pacr register is 1 (p7 3 to p7 0 ), this table lists the p7 0 functions. 2. in addition to this, set the crd bit in the u0c0 register to 0 (ct0 0 /rt0 0 enabled) and the crs bit in the u0c0 register to 1 (rts 0 selected). 3. when the clkmd1 bit is set to 1 and the clkmd0 bit is set to 0, the following logic levels are output: ? high if the clkpol bit in the u1c0 register is set to 0 ? low if the clkpol bit in the u1c0 register is set to 1
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 171 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 14.10 typical transmit/receive timings in clock synchronous serial i/o mode d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 tc t clk stopped pulsing because the te bit = 0 write data to the uitb register tc = t clk = 2(n + 1) / fj fj: frequency of uibrg count source (f 1sio , f 2sio , f 8sio , f 32sio ) n: value set to uibrg register i: 0 to 2 transfer clock uic1 register te bit uic1 register ti bit clki txdi ? h ? ? l ? 0 1 0 1 0 1 ctsi 0 1 stopped pulsing because ctsi = ? h ? 1 / f ext write dummy data to uitb register uic1 register te bit uic1 register ti bit clki rxdi uic1 register ri bit rtsi ? h ? ? l ? 0 1 0 1 0 1 uic1 register re bit 0 1 receive data is taken in transferred from uitb register to uarti transmit register read out from uirb registe r f ext : frequency of external clock transferred from uarti receive register to uirb registe r siric register ir bit 0 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 transferred from uitb register to uarti transmit register make sure the following conditions are met when input to the clki pin before receiving data is high: ? uic0 register te bit is set to 1 (transmit enabled) ? uic0 register re bit is set to 1 (receive enabled) ? write dummy data to the uitb register the above timing diagram applies to the case where the register bits are set as follows: ? the ckdir bit in the uimr register is set to 0 (internal clock) ? the crd bit in the uic0 register is set to 0 (cts/rts enabled); crs bit is set to 0 (cts selected) ? the ckpol bit in the uic0 register is set to 0 (transmit data output at the falling edge and receive data taken in at the risi ng edge of the transfer clock) ? the uiirs bit is set to 0 (an interrupt request occurs when the transmit buffer becomes empty): u0irs bit is the bit 0 in the ucon register u1irs bit is the bit 1 in the ucon register, and u2irs bit is the bit 4 in the u2c1 register. cleared to 0 when interrupt request is accepted, or cleared to 0 by program cleared to ? 0 ? when interrupt request is accepted, or cleared to 0 by program the above timing diagram applies to the case where the register bits are set as follows: ? the ckdir bit in the uimr register is set to 1 (external clock) ? the crd bit in the uic0 register is set to 0 (cts/rts enabled); the crs bit is set to 1 (rts selected) ? uic0 register ckpol bit is set to 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock) uic0 register txept bit sitic register ir bit even if the reception is completed, the rts does not change. the rts becomes ? l ? when the ri bit changes to 0 from 1. (1) example of transmit timing (internal clock is selected) (2) example of receive timing (external clock is selected)
14.serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 172 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 14.1.1.1 counter measure for communication error occurs if a communication error occurs while transmitting or receiving in clock synchronous serial i/o mode, follow the procedures below. ? resetting the uirb register (i=0 to 2) (1) set the re bit in the uic1 register to 0 (reception disabled) (2) set bits smd2 to smd0 in the uimr register to 000 2 (serial i/o disabled) (3) set bits smd2 to smd0 in the uimr register to 001 2 (clock synchronous serial i/o mode) (4) set the re bit in the uic1 register to 1 (reception enabled) ? resetting the uitb register (i=0 to 2) (1) set bits smd2 to smd0 in the uimr register to 000 2 (serial i/o disabled) (2) set bits smd2 to smd0 in the uimr register to 001 2 (clock synchronous serial i/o mode) (3) 1 is written to te bit in the uic1 register (reception enabled), regardless to the te bit.
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 173 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 14.1.1.2 clk polarity select function use the ckpol bit in the uic0 register (i=0 to 2) to select the transfer clock polarity. figure 14.11 shows the polarity of the transfer clock. figure 14.11 polarity of transfer clock 14.1.1.3 lsb first/msb first select function use the uform bit in the uic0 register (i=0 to 2) to select the transfer format. figure 14.12 shows the transfer format. figure 14.12 transfer format (2) when the ckpol bit in the uic0 register is set to 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock) d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 0 t x d i r x d i clk i (1) when the ckpol bit in the uic0 register is set to 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) d 1 d 2 d 3 d 4 d 5 d 6 d 7 d0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 t x d i r x d i clk i (2) (3) i = 0 to 2 notes: 1. this applies to the case where the uform bit in the uic0 register is set to 0 (lsb first) and the uilch bit in the uic1 register is set to 0 (no reverse). 2. when not transferring, the clki pin outputs a high signal. (1) when the uform bit in the uic0 register 0 (lsb first) d0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 t x d i r x d i clk i (2) when the uform bit in the uic0 register is set to 1 (msb first) d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 t x d i r x d i clk i i = 0 to 2 note: 1. this applies to the case where the ckpol bit in the uic0 register is set to 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) and the uilch bit in the uic1 register 0 (no reverse).
14.serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 174 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 14.1.1.4 continuous receive mode when the uirrm bit (i=0 to 2) is set to 1 (continuous receive mode), the ti bit in the uic1 register is set to ? 0 ? (data present in the uitb register) by reading the uirb register. in this case, i.e., uirrm bit is set to 1, do not write dummy data to the uitb register in a program. the u0rrm and u1rrm bits are the bit 2 and bit 3 in the ucon register, respectively, and the u2rrm bit is the bit 5 in the u2c1 register. 14.1.1.5 serial data logic switch function (uart2) when the u2lch bit in the u2c1 register is set to 1 (reverse), the data written to the u2tb register has its logic reversed before being transmitted. similarly, the received data has its logic reversed when read from the u2rb register. figure 14.13 shows serial data logic. figure 14.13 serial data logic switch timing 14.1.1.6 transfer clock output from multiple pins function (uart1) the clkmd1 to clkmd0 bits in the ucon register can choose one from two transfer clock output pins. (see figure 14.14 ) this function is valid when the internal clock is selected for uart1. figure 14.14 transfer clock output from multiple pins d0 d1 d2 d3 d4 d5 d6 d7 transfer clock txd 2 (no reverse) ? h ? ? l ? ? h ? ? l ? txd 2 (reverse) d0 d1 d2 d3 d4 d5 d6 d7 ? h ? ? l ? (1) when the u2lch bit in the u2c1 register is set to 0 (no reverse) transfer clock ? h ? ? l ? (2) when the u2lch bit in the u2c1 register is set to 1 (reverse) note: 1. this applies to the case where the ckpol bit in the u2c0 register is set to 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) and the uform bit is set to 0 (lsb first). mcu t x d 1 (p6 7 ) clks 1 (p6 4 ) clk 1 (p6 5 ) in clk in clk transfer enabled when the clkmd0 bit in the ucon register is set to 0 transfer enabled when the clkmd0 bit in the ucon register is set to 1 notes: 1. this applies to the case where the ckdir bit in the u1mrregister is set to 0 (internal clock) and the clkmd1 bit in the ucon register is set to 1 (transfer clock output from multiple pins). 2. this applies to the case where u1map bit in pacr register is set to 0 (p6 7 to p6 4 ).
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 175 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r _______ _______ 14.1.1.7 cts/rts separate function (uart0) _______ _______ _______ _______ this function separates cts 0 /rts 0 , outputs rts 0 from the p6 0 pin, and accepts as input the cts 0 from the p6 4 pin or p7 0 pin. to use this function, set the register bits as shown below. _______ _______ ? the crd bit in the u0c0 register is set to 0 (enables uart0 cts/rts) _______ ? the crs bit in the u0c0 register is set to 1 (outputs uart0 rts) _______ _______ ? the crd bit in the u1c0 register is set to 0 (enables uart1 cts/rts) _______ ? the crs bit in the u1c0 register is set to 0 (inputs uart1 cts) _______ ? the rcsp bit in the ucon register is set to 1 (inputs cts 0 from the p6 4 pin or p7 0 pin) ? the clkmd1 bit in the ucon register is set to 0 (clks 1 not used) _______ _______ _______ _______ note that when using the cts/rts separate function, uart1 cts/rts separate function cannot be used. figure 14.15 cts/rts separate function usage mcu t x d 0 (p6 3 ) clk 0 (p6 1 ) cts 0 (p6 4 ) ic in out clk rxd 0 (p6 2 ) rts 0 (p6 0 )cts rts note: 1. this applies to the case where the u1map bit in the pacr register is set to 0 (p6 7 to p6 4 ).
14.serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 176 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r item specification transfer data format ? character bit (transfer data): selectable from 7, 8 or 9 bits ? start bit: 1 bit ? parity bit: selectable from odd, even, or none ? stop bit: selectable from 1 or 2 bits transfer clock ? the ckdir bit in the uimr(i=0 to 2) register is set to 0 (internal clock) : fj/ (16(n+1)) fj = f 1sio , f 2sio , f 8sio , f 32sio . n: setting value of uibrg register 00 16 to ff 16 ? ckdir bit is set to ? 1 ? (external clock ) : f ext /16(n+1) f ext : input from clki pin. n :setting value of uibrg register 00 16 to ff 16 transmission, reception control _______ _______ _______ _______ ? selectable from cts function, rts function or cts/rts function disable transmission start condition ? before transmission can start, the following requirements must be met _ the te bit in the uic1 register is set to 1 (transmission enabled) _ the ti bit in the uic1 register is set to 0 (data present in uitb register) _______ _______ _ if cts function is selected, input on the ctsi pin is set to ? l ? reception start condition ? before reception can start, the following requirements must be met" _ the re bit in the uic1 register is set to 1 (reception enabled) _ start bit detection ? for transmission, one of the following conditions can be selected _ the uiirs bit (2) is set to 0 (transmit buffer empty): when transferring data from the uitb register to the uarti transmit register (at start of transmission) _ the uiirs bit is set to1 (transfer completed): when the serial i/o finished sending data from the uarti transmit register ? for reception when transferring data from the uarti receive register to the uirb register (at completion of reception) error detection ? overrun error (1) this error occurs if the serial i/o started receiving the next data before reading the uirb register and received the bit one before the last stop bit in the the next data ? framing error this error occurs when the number of stop bits set is not detected ? parity error this error occurs when if parity is enabled, the number of 1 in parity and character bits does not match the number of 1 set ? error sum flag this flag is set to 1 when any of the overrun, framing, and parity errors is encountered select function ? lsb first, msb first selection whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected ? serial data logic switch (uart2) this function reverses the logic of the transmit/receive data. the start and stop bits are not reversed. ? t x d, r x d i/o polarity switch (uart2) this function reverses the polarities of hte t x d pin output and r x d pin input. the logic levels of all i/o data is reversed. _______ _______ ? separate cts/rts pins (uart0) _________ _________ cts 0 and rts 0 are input/output from separate pins ? uart1 pin remapping selection the uart1 pin can be selected from the p6 7 to p6 4 or p7 3 to p7 0 14.1.2 clock asynchronous serial i/o (uart) mode the uart mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. tables 14.5 lists the specifications of the uart mode. table 14.5 uart mode specifications interrupt request generation timing notes: 1. if an overrun error occurs, bits 8 to 0 in the uirb (i=0 to 2) register are undefined. the ir bit in the siric register remains unchanged. 2. bits u0irs and u1irs respectively are the ucon register bits 0 and 1; the u2irs bit is the u2c1 register bit 4.
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 177 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r table 14.6 registers to be used and settings in uart mode register bit function uitb 0 to 8 set transmission data (1) uirb 0 to 8 reception data can be read (1) oer,fer,per,sum error flag uibrg 0 to 7 set a transfer rate uimr smd2 to smd0 set these bits to 100 2 when transfer data is 7 bits long set these bits to 101 2 when transfer data is 8 bits long set these bits to 110 2 when transfer data is 9 bits long ckdir select the internal clock or external clock stps select the stop bit pry, prye select whether parity is included and whether odd or even iopol(i=2) (4) select the txd/rxd input/output polarity uic0 clk0, clk1 select the count source for the uibrg register crs _______ _______ select cts or rts to use txept transmit register empty flag crd _______ _______ enable or disable the cts or rts function nch select txdi pin output mode ckpol set to 0 uform lsb first or msb first can be selected when transfer data is 8 bits long. set this bit to 0 when transfer data is 7 or 9 bits long. uic1 te set this bit to 1 to enable transmission ti transmit buffer empty flag re set this bit to 1 to enable reception ri reception complete flag u2irs (2) select the source of uart2 transmit interrupt u2rrm (2) set to 0 uilch (3) set this bit to 1 to use uart2 inverted data logic uiere (3) set to 0 uismr 0 to 7 set to 0 uismr2 0 to 7 set to 0 uismr3 0 to 7 set to 0 uismr4 0 to 7 set to 0 ucon u0irs, u1irs select the source of uart0/uart1 transmit interrupt u0rrm, u1rrm set to 0 clkmd0 invalid because clkmd1 is set to 0 clkmd1 set to 0 rcsp _________ set this bit to 1 to accept as input the uart0 cts 0 signal from the p6 4 pin 7 set to 0 notes: 1. the bits used for transmit/receive data are as follows: bit 0 to bit 6 when transfer data is 7 bits long; bits 7 to 0 when transfer data is 8 bits long; bit 0 to bit 8 when transfer data is 9 bits long. 2. set bits 5 and 4 in registers u0c1 and u1c1 to 0. bits u0irs, u1irs, u0rrm and u1rrm are included in the ucon register. 3. set bits 7 and 6 in registers u0c1 and u1c1 to 0. 4. set the bit 7 in registers u0mr and u1mr to 0. i=0 to 2
14.serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 178 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r table 14.7 lists the functions of the input/output pins in uart mode. table 14.8 lists the p6 4 pin func- tions during uart mode. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs an ? h ? . (if the n-channel open-drain output is selected, this pin is in a high-impedance state.) table 14.7 i/o pin functions in uart mode (1) table 14.8 p6 4 pin functions in uart mode (1) pin name function method of selection txdi (i = 0 to 2) (p6 3 , p6 7 , p7 0 ) serial data output serial data input input/output port transfer clock input input /output port (outputs "h" when performing reception only) rxdi (p6 2 , p6 6 , p7 1 ) clki (p6 1 , p6 5 , p7 2 ) set the ckdir bit in the uimr register to 0 set the ckdir bit in the uimr register to 1 set the pd6 _1 bit and pd6_5 bit in the pd6 register to 0, pd7_2 bit in the pd7 register to 0 pd6_2 bit, pd6_6 bit in the pd6 register and the pd7_1 bit in the pd7 register (can be used as an in put port when performing transmission only) set the crd bit in the uic0 register to 0 set the crs bit in the uic0 register to 0 set the pd6_0 bit and pd6_4 bit in the pd6 register to 0, the pd7_3 bit in the pd7 register 0 set the crd bit in the uic0 register to 0 set the crs bit in the uic0 register to 1 set the crd bit in the uic0 register 1 cts input rts output ctsi/rtsi (p6 0 , p6 4 , p7 3 ) note: 1. when the u1map bit in pacr register is set to 1 (p7 3 to p7 0 ), uart1 pin is assgined to p7 3 to p7 0 . pin function bit set value u1c0 register ucon register pd6 register crd crs rcsp clkmd1 pd6_4 p6 4 1 0 0 input: 0, output: 1 cts 1 0000 rts 1 10 0 cts 0 (2) 0 0 0 00 10 notes: 1. when the u1map bit in pacr register is 1 (p7 3 to p7 0 ), this table lists the p7 0 functions. 2. in addition to this, set the crd bit in the u0c0 register to 0 (cts 0 /rts 0 enabled) and the crs bit in the u0c0 register to 1 (rts 0 selected).
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 179 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 14.16 typical transmit timing in uart mode (uart0, uart1) start bit parity bit txdi ctsi 1 0 1 ? l ? ? h ? 0 1 0 1 txd i 0 1 0 1 0 1 transfer clock tc 0 1 tc transfer clock d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st pd 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 sp st p sp d 0 d 1 st stop bi t start bit the transfer clock stops momentarily as ctsi is ? h ? when the stop bit is checked. the transfer clock starts as the transfer starts immediately ctsi changes to ? l ? . d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st sp d 8 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st d 8 d 0 d 1 st sp sp stop bit stop bit 0 sp stopped pulsing because the te bit = ? 0 ? write data to the uitb register uic1 register te bit uic1 register ti bit uic0 register txept bit sitic register ir bit transferred from uitb register to uarti transmit register the above timing diagram applies to the case where the register bits are set as follows: ? set the prye bit in the uimr register to 1 (parity enabled) ? set the stps bit in the uimr register to 0 (1 stop bit) ? set the crd bit in the uic0 register to 0 (cts/rts enabled), the crs bit to 0 (cts selected). ? set the uiirs bit to 1 (an interrupt request occurs when transmit completed): u0irs bit is the ucon register bit 0, u1irs bit is the ucon register bit 1, and u2irs bit is the u2c1 register bit 4 cleared to 0 when interrupt request is accepted, or cleared to 0 by program uic1 register te bit uic1 register ti bit uic0 register txept bit sitic register ir bit cleared to 0 when interrupt request is accepted, or cleared to 0 by program write data to the uitb register transferred from uitb register to uarti transmit register the above timing diagram applies to the case where the register bits are set as follows: ? set the prye bit in the uimr register to 0 (parity disabled) ? set the stps bit in the uimr register to 1 (2 stop bits) ? set the crd bit in the uic0 register to 1 (cts/rts disabled) ? set the uiirs bit to 0 (an interrupt request occurs when transmit buffer becomes empty): u0irs bit is the ucon register bit 0, u1irs bit is the ucon register bit 1, and u2irs bit is the u2c1 register bit 4 ? example of transmit timing when transfer data is 9-bit long (parity disabled, two stop bits) ? example of transmit timing when transfer data is 8-bit long (parity enabled, one stop bit) tc = 16 (n + 1) / fj or 16 (n + 1) / f ext fj: frequency of uibrg count source (f 1sio , f 2sio , f 8sio , f 32sio ) f ext : frequency of uibrg count source (external clock) n: value set to uibrg i = 0 to 2 tc = 16 (n + 1) / fj or 16 (n + 1) / f ext fj: frequency of uibrg count source (f 1sio , f 2sio , f 8sio , f 32sio ) f ext : frequency of uibrg count source (external clock) n: value set to uibrg i = 0 to 2
14.serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 180 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ? example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) figure 14.17 receive operation d 0 start bit sampled ? l ? uibrg count source rxdi transfer clock rtsi stop bit 1 0 0 1 ? h ? ? l ? 0 1 reception triggered when transfer clock is generated by falling edge of start bit uic1 register re bit uic1 register ri bit siric register ir bit cleared to 0 when interrupt request is accepted, or cleared to 0 by program receive data taken in d 7 d 1 transferred from uarti receive register to uirb register read out from uirb register the above timing diagram applies to the case where the register bits are set as follows: ? set the prye bit in the uimr register to 0 (parity disabled) ? set the stps bit in the uimr register to 0 (1 stop bit) ? set the crd bit in the uic0 register to 0 (ctsi/rtsi enabled), the crs bit to 1 (rtsi selected) i = 0 to 2 14.1.2.1 bit rates in uart mode, the frequency set by the uibrg register (i=0 to 2) divided by 16 become the bit rates. table 14.9 lists example of bit rate and settings. table 14.9 example of bit rates and settings bit rate count source peripheral function clock : 16mhz peripheral function clock : 20mhz (bps) of brg set value of brg : n actual time (bps) set value of brg : n actual time (bps) 1200 f8 103(67h) 1202 129(81h) 1202 2400 f8 51(33h) 2404 64(40h) 2404 4800 f8 25(19h) 4808 32(20h) 4735 9600 f1 103(67h) 9615 129(81h) 9615 14400 f1 68(44h) 14493 86(56h) 14368 19200 f1 51(33h) 19231 64(40h) 19231 28800 f1 34(22h) 28571 42(2ah) 29070 31250 f1 31(1fh) 31250 39(27h) 31250 38400 f1 25(19h) 38462 32(20h) 37879 51200 f1 19(13h) 50000 24(18h) 50000
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 181 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r (1) when the uform bit in the uic0 register is set to 0 (lsb first) (2) when the uform bit in the uic0 register is set to 1 (msb first) d 1 d 2 d 3 d 4 d 5 d 6 sp d0 d 1 d 2 d 3 d 4 d 5 d 6 sp d 0 t x d i r x d i clk i d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 t x d i r x d i clk i st st d 7 p d 7 p sp sp st st p p d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 st : start bit p : parity bit sp : stop bit i = 0 to 2 note: 1. this applies to the case where the ckpol bit in the uic0 register is set to 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the uilch bit in the uic1 register is set to 0 (no reverse), the stps bit in the uimr register is set to 0 (1 stop bit) and the prye bit in the uimr register is set to 1 (parity enabled). 14.1.2.2 counter measure for communication error if a communication error occurs while transmitting or receiving in uart mode, follow the procedure below. ? resetting the uirb register (i=0 to 2) (1) set the re bit in the uic1 register to 0 (reception disabled) (2) set the re bit in the uic1 register to 1 (reception enabled) ? resetting the uitb register (i=0 to 2) (1) set bits smd2 to smd0 in uimr register 000 2 (serial i/o disabled) (2) set bits smd2 to smd0 in uimr register 001 2 , 101 2 , 110 2 (3) 1 is written to te bit in the uic1 register (reception enabled), regardless of the te bit 14.1.2.3 lsb first/msb first select function as shown in figure 14.18 , use the uform bit in the uic0 register to select the transfer format. this function is valid when transfer data is 8 bits long. figure 14.18 transfer format
14.serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 182 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r transfer clock ? h ? ? l ? d0 d1 d2 d3 d4 d5 d6 d7 psp st txd 2 (no reverse) ? h ? ? l ? txd 2 (reverse) sp st d3 d4 d5 d6 d7 p d0 d1 d2 ? h ? ? l ? (1) when the u2lch bit in the u2c1 register is set to 0 (no reverse) (2) when the u2lch bit in the u2c1 register is set 1 (reverse) transfer clock ? h ? ? l ? note: 1. this applies to the case where the ckpol bit in the u2c0 register is set to 0 (transmit data output at the falling edge of the transfer clock), the uform bit in the u2c0 register is set to 0 (lsb first), the stps bit in the u2mr register is set to 0 (1 stop bit) and the prye bit in the u2mr register is set to 1 (parity st: start bit p: parity bit sp: stop bit (1) when the iopol bit in the u2mr register is set to 0 (no reverse) (2) when the iopol bit in the u2mr register is set to 1 (reverse) st: start bit p: parity bit sp: stop bit d0 d1 d2 d3 d4 d5 d6 d7 psp st sp st d3 d4 d5 d6 d7 p d0 d1 d2 d0 d1 d2 d3 d4 d5 d6 d7 psp st ? h ? sp st d3 d4 d5 d6 d7 p d0 d1 d2 transfer clock txd 2 (no reverse) rxd 2 (no reverse) transfer clock txd 2 (reverse) rxd 2 (reverse) ? l ? ? h ? ? l ? ? h ? ? l ? ? h ? ? l ? ? h ? ? l ? ? h ? ? l ? note: 1. this applies to the case where the uform bit in the u2c0 register is set to 0 (lsb first), the stps bit in the u2mr register is set to 0 (1 stop bit) and the prye bit in the u2mr register is set to 1 (parity enabled). 14.1.2.4 serial data logic switching function (uart2) the data written to the u2tb register has its logic reversed before being transmitted. similarly, the received data has its logic reversed when read from the u2rb register. figure 14.19 shows serial data logic. figure 14.19 serial data logic switching 14.1.2.5 txd and rxd i/o polarity inverse function (uart2) this function inverses the polarities of the t x d2 pin output and r x d2 pin input. the logic levels of all input/output data (including the start, stop and parity bits) are inversed. figure 14.20 shows the t x d pin output and r x d pin input polarity inverse. figure 14.20 t x d and r x d i/o polarity inverse
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 183 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r _______ _______ 14.1.2.6 cts/rts separate function (uart0) _______ _______ _______ _______ this function separates cts 0 /rts 0 , outputs rts 0 from the p6 0 pin, and accepts as input the cts 0 from the p6 4 pin or p7 0 pin. to use this function, set the register bits as shown below. _______ _______ ? the crd bit in the u0c0 register is set to 0 (enables uart0 cts/rts) _______ ? the crs bit in the u0c0 register is set to 1 (outputs uart0 rts) _______ _______ ? the crd bit in the u1c0 register is set to 0 (enables uart1 cts/rts) _______ ? the crs bit in the u1c0 register is set to 0 (inputs uart1 cts) _______ ? the rcsp bit in the ucon register is set to 1 (inputs cts 0 from the p6 4 pin or p7 0 pin) ? the clkmd1 bit in the ucon register is set to 0 (clks 1 not used) _______ _______ _______ _______ note that when using the cts/rts separate function, uart1 cts/rts separate function cannot be used. _______ _______ figure 14.21 cts/rts separate function mcu t x d 0 (p6 3 ) cts 0 (p6 4 ) ic in out rxd 0 (p6 2 ) rts 0 (p6 0 )cts rts note: 1. this applies to the case where the u1map bit in the pacr register is set to 0 (p6 7 to p6 4 ).
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 184 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 14.1.3 special mode 1 (i 2 c bus mode) (uart2) i 2 c bus mode is provided for use as a simplified i 2 c bus interface compatible mode. table 14.10 lists the specifications of the i 2 c bus mode. tables 14.11 and 14.12 list the registers used in the i 2 c bus mode and the register values set. table 14.13 lists the i 2 c bus mode fuctions. figure 14.22 shows the block diagram for i 2 c bus mode. figure 14.23 shows scl 2 timing. as shown in table 14.11 , the mcu is placed in i 2 c bus mode by setting bits smd2 to smd0 to 010 2 and the iicm bit to 1. because sda 2 transmit output has a delay circuit attached, sda output does not change state until scl 2 goes low and remains stably low. table 14.10 i 2 c bus mode specifications item specification transfer data format ? transfer data length: 8 bits transfer clock ? during master the ckdir bit in the u2mr register is set to 0 (internal clock) : fj/ (2(n+1)) fj = f 1sio , f 2sio , f 8sio , f 32sio . n: setting value in the u2brg register 00 16 to ff 16 ? during slave ckdir bit is set to 1 (external clock) : input from scl 2 pin transmission start ? before transmission can start, the following requirements must be met (1) condition _ the te bit in the u2c1 register is set to 1 (transmission enabled) _ the ti bit in the u2c1 register is set to 0 (data present in u2tb register) reception start ? before reception can start, the following requirements must be met (1) condition _ the re bit in the u2c1 register is set to 1 (reception enabled) _ the te bit in the u2c1 register is set to 1 (transmission enabled) _ the ti bit in the u2c1 register is set to 0 (data present in the uitb register) interrupt request when start / stop condition is detected, acknowledge undetected, generation timing and acknowledge detected error detection ? overrun error (2) this error occurs if the serial i/o started receiving the next data before reading the u2rb register and received the 8th bit in the the next data select function ? arbitration lost timing at which the abt bit in the u2rb register is updated can be selected ? sda digital delay no digital delay or a delay of 2 to 8 u2brg count source clock cycles selectable ? clock phase setting with or without clock delay selectable notes: 1. when an external clock is selected, the conditions must be met while the external clock is in the high state. 2. if an overrun error occurs, bits 8 to 0 in the uirb register (i = 0 to 2) are undefined. the ir bit in the s2ric register remains unchanged.
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 185 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 14.22 i 2 c bus mode block diagram clk control falling edge detection external clock internal clock start/stop condition detection interrupt request start condition detection stop condition detection reception register bus busy transmission register arbitration noise filter sda2 scl2 uart2 d t q d t q d t q nack ac k uart2 uart2 uart2 r uart2 transmit, nack interrupt request uart2 receive, ack interrupt request, dma1 request iicm=1 and iicm2=0 s r q als r s swc iicm=1 and iicm2=0 iicm2=1 iicm2=1 swc2 sdhi dma0, dma1 request noise filter iicm=0 iicm=1 dma0 stspsel=0 stspsel=1 stspsel=1 stspsel=0 sda stsp scl stsp ackc=1 ackc=0 q port register (1) i/o port 9th bit falling edge 9th bit ackd bit delay circuit start and stop condition generation block this diagram applies to the case where bits smd2 to smd0 in the u2mr register is set to 010 2 and the iicm bit in the u2smr register is set to 1. iicm : bit in the u2smr register iicm2, swc, als, swc2, sdhi : bits in the u2smr2 register stspsel, ackd, ackc : bits in the u2smr4 register note: 1. if the iicm bit is set to 1, the pin can be read even when the pd7_1 bit is set to 1 (output mode).
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 186 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r table 14.11 registers to be used and settings in i 2 c bus mode (1) (continued) register bit function master slave u2tb 0 to 7 set transmission data set transmission data u2rb (1) 0 to 7 reception data can be read reception data can be read 8 ack or nack is set in this bit ack or nack is set in this bit abt arbitration lost detection flag invalid oer overrun error flag overrun error flag u2brg 0 to 7 set a transfer rate invalid u2mr (1) smd2 to smd0 set to 010 2 set to 010 2 ckdir set to 0 set to 1 iopol set to 0 set to 0 u2c0 clk1, clk0 select the count source for the u2brg invalid register crs invalid because crd = 1 invalid because crd = 1 txept transmit buffer empty flag transmit buffer empty flag crd set to 1 set to 1 nch set to 1 set to 1 ckpol set to 0 set to 0 uform set to 1 set to 1 u2c1 te set this bit to 1 to enable transmission set this bit to 1 to enable transmission ti transmit buffer empty flag transmit buffer empty flag re set this bit to 1 to enable reception set this bit to 1 to enable reception ri reception complete flag reception complete flag u2irs invalid invalid u2rrm, set to 0 set to 0 u2lch, u2ere u2smr iicm set to 1 set to 1 abc select the timing at which arbitration-lost invalid is detected bbs bus busy flag bus busy flag 3 to 7 set to 0 set to 0 u2smr2 iicm2 refer to table 14.13 refer to table 14.13 csc set this bit to 1 to enable clock set to 0 synchronization swc set this bit to 1 to have scl 2 output set this bit to 1 to have scl 2 output fixed to l at the falling edge of the 9th fixed to ? l ? at the falling edge of the 9 th bit of clock bit of clock als set this bit to 1 to have sda 2 output set to 0 stopped when arbitration-lost is detected stac set to 0 set this bit to 1 to initialize uart2 at start condition detection swc2 set this bit to 1 to have scl 2 output set this bit to 1 to have scl 2 output forcibly pulled low forcibly pulled low sdhi set this bit to 1 to disable sda 2 output set this bit to 1 to disable sda 2 output 7 set to 0 set to 0 u2smr3 0, 2, 4 and nodc set to 0 set to 0 ckph refer to table 14.13 refer to table 14.13 dl2 to dl0 set the amount of sda 2 digital delay set the amount of sda 2 digital delay note: 1. not all bits in the register are described above. set those bits to 0 when writing to the registers in i 2 c bus mode.
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 187 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r u2smr4 stareq set this bit to 1 to generate start set to 0 condition rstareq set this bit to 1 to generate restart set to 0 condition stpreq set this bit to 1 to generate stop set to 0 condition stspsel set this bit to 1 to output each condition set to 0 ackd select ack or nack select ack or nack ackc set this bit to 1 to output ack data set this bit to 1 to output ack data sclhi set this bit to 1 to have scl 2 output set to 0 stopped when stop condition is detected swc9 set to 0 set this bit to 1 to set the scl 2 to ? l ? hold at the falling edge of the 9th bit of clock register bit function master slave table 14.12 registers to be used and settings in i 2 c bus mode (2) (continued) note: 1: not all bits in the register are described above. set those bits to 0 when writing to the registers in i 2 c bus mode.
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 188 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r table 14.13 i 2 c bus mode functions function i 2 c bus mode (smd2 to smd0 = 01 0 2 , iicm = 1) noise filter width ) no delay txd2 output rxd2 input delay sda 2 input and output scl 2 input and output 200n value set in the port register before entering i 2 c bus mode (1) iicm2 = 0 (nack/ack interrupt) iicm2 = 1 (uart transmit/ receive interrupt) ckpol = 0 (rising edge) ckpol = 1 (falling edge) acknowledgment detection (ack) l the u2rb register status is read ckph = 0 (no clock delay) uart2 transmit operation - at the next falling edge after the 9th bit of scl 2 clock synchronous serial i/o mode (smd2 to smd0 = 001 2 , iicm = 0) interrupt source for number 10 (1) (see fig.14.23 ) interrupt source for number 15 (1) (see fig.14.23 ) interrupt source for number 16 (1) (see fig.14.23 ) ckph = 1 (clock delay) ckph = 0 (no clock delay) ckph = 1 (clock delay) start condition detection or stop condition detection (refer to table 14.14 ) bit 6 to bit 0 in the u2rb register are read as bit 7 to bit 1. bit 8 in the u2rb register is read as bit 0 (4) 1st to 8th bits are stored into bits 7 to 0 in the u2rb register (3) 1st to 7th bits are stored into the bit 6 to bit 0 in the u2rb register, with 8th bit stored in the bit 8 in the u2rb register 1st to 8th bits are stored into bits 7 to 0 in the u2rb register data transfer timing from the uart receive shift register to the u2rb register uart2 transmit operation - at the rising edge of 9th bit of scl 2 no acknowledgment detection (nack) - at the rising edge of 9th bit of scl 2 acknowledgment detection (ack) - at the rising edge of 9th bit of scl 2 uart2 receive operation - at the falling edge of 9th bit of scl 2 falling edge of 9th bit of scl 2 falling edge and rising edge of 9th bit of scl 2 uart2 transmit operation - transmit operation is started or completed (selected by u2irs uart2 receive timing - when 8th bit is received, ckpol = 0 (rising edge) ckpol = 1 (falling edge) uart2 transmit output delay function of p7 0 function of p7 1 function of p7 2 at the rising edge of 9th bit of scl 2 reading rxd2, scl 2 pin levels default value of txd2, sda 2 output dma1 source (see fig.14.23 ) select clk2 input or output - (not used in i 2 c bus mode) 15ns ckpol = 0 (h) ckpol = 1 (l) 1st to 8th bits are stored into bits 7 to 0 in the u2rb register uart2 receive operation storing receive data uart2 receive operation - at the falling edge of 9th bit of scl 2 can be read regardless of the corresponding port direction bit can be read if the corresponding port direction bit is set to 0 reading receive data scl 2 default and end values - - l hh notes: 1. if the interrupt source is changed, the ir bit in the interrupt control register for the changed interrupt may be set t o 1 (interrupt requested). (refer to ? interrupts ? in precautions.) if any of the following bits are changed, the interrupt source, the interrupt timing, etc. will be changed also. therefore, set the ir bit to 0 (interrupt not requested) after those bits are changed. bits smd2 to smd0 in the u2mr register, the iicm bit in the u2smr register, the iicm2 bit in the u2smr2 register, the ckph bit in the u2smr3 register 2. set the default value of the sda 2 output when bits smd2 to smd0 in the u2mr register are set to 000 2 (serial i/o disabled). 3. second data transfer to the u2rb register (at the rising edge of the ninth bit of scl 2 ) 4. first data transfer to the u2rb register (at falling edge of the ninth bit of scl 2 )
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 189 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 14.23 transfer to u2rb register and interrupt timing (4) when the iicm2 bit is set to 1 and the ckph bit is set to 1 (3) when the iicm2 bit is set to 1 (uart transmit or receive interrupt) and the ckph bit is set to 0 sda2 scl2 receive interrupt (dma request) transmit interrupt sda2 scl2 the above timing applies to the following setting : ? the ckdir bit in the u2mr register is set to 1 (slave) (1) when the iicm2 bit is set to 0 (ack or nack interrupt) and the ckph bit is set to 0 (no clock delay) d 6 d 5 d 4 d 3 d 2 d 1 d 8 (ack or nack) d 7 sda2 scl2 d 0 ack interrupt (dma request) or nack interrupt (2) when the iicm2 bit is set to 0 and the ckph bit is set to 1 (clock delay) sda2 scl2 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit b15 ??? b9 b8 b7 b0 d 8 contents of the u2rb register b15 ??? b9 b8 b7 b0 b15 ??? b9 b8 b7 b0 b15 ??? b9 b8 b7 b0 b15 ??? b9 b8 b7 b0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 6 d 5 d 4 d 3 d 2 d 1 d 7 d 0 ack interrupt (dma request) or nack interrupt d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 6 d 5 d 4 d 3 d 2 d 1 d 7 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 6 d 5 d 4 d 3 d 2 d 1 d 7 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 (ack or nack) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit d 8 (ack or nack) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit d 8 (ack or nack) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit data is transferred to the u2rb register data is transferred to the u2rb register data is transferred to the u2rb register receive interrupt (dma request) transmit interrupt data is transferred to the u2rb register data is transferred to the u2rb register contents of the u2rb register contents in the u2rb register contents in the u2rb register contents in the u2rb register
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 190 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 14.1.3.1 detection of start and stop condition whether a start or a stop condition has been detected is determined. a start condition-detected interrupt request is generated when the sda 2 pin changes state from high to low while the scl 2 pin is in the high state. a stop condition-detected interrupt request is generated when the sda 2 pin changes state from low to high while the scl 2 pin is in the high state. because the start and stop condition-detected interrupts share the interrupt control register and vec- tor, check the bbs bit in the u2smr register to determine which interrupt source is requesting the interrupt. figure 14.24 detection of start and stop condition 14.1.3.2 output of start and stop condition a start condition is generated by setting the stareq bit in the u2smr4 register to 1 (start). a restart condition is generated by setting the rstareq bit in the u2smr4 register to 1 (start). a stop condition is generated by setting the stpreq bit in the u2smr4 register to 1 (start). the output procedure is described below. (1) set the stareq bit, rstareq bit or stpreq bit to 1 (start). (2) set the stspsel bit in the u2smr4 register to 1 (output). make sure that no interrupts or dma transfers will occur between (1) and (2). the function of the stspsel bit is shown in table 14.14 and figure 14.25 . setup tim e hold time scl2 sda2 ( start condition) sda2 ( stop condition) 3 to 6 cycles < setup tim e (1) 3 to 6 cycles < hold time (1) note: 1. when the pclk1 bit in the pclkr register is set to 1, the cycles indicates the f1sio's generation frequency cycles; when pclk1 bit is set to 0, the cycles indicated the f2sio's generation frequency cycles.
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 191 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r table 14.14 stspsel bit functions figure 14.25 stspsel bit functions function output of scl2 and sda2 pins start/stop condition interrupt request generation timing stspsel = 0 output transfer clock and data/ program with a port determines how the start condition or stop condition is output start/stop condition are detec- ted stspsel = 1 the stareq, rstareq and stpreq bit determine how the start condition or stop condition is output start/stop condition generation are completed 14.1.3.3 arbitration unmatching of the transmit data and sda 2 pin input data is checked synchronously with the rising edge of scl 2 . use the abc bit in the u2smr register to select the timing at which the abt bit in the u2rb register is updated. if the abc bit is set to 0 (updated bitwise), the abt bit is set to 1 at the same time unmatching is detected during check, and is cleared to 0 when not detected. in cases when the abc bit is set to 1, if unmatching is detected even once during check, the abt bit is set to 1 (unmatching detected) at the falling edge of the clock pulse of 9th bit. if the abt bit needs to be updated bytewise, clear the abt bit to 0 (undetected) after detecting acknowledge in the first byte, before transferring the next byte. setting the als bit in the u2smr2 register to 1 (sda 2 output stop enabled) causes arbitration-lost to occur, in which case the sda 2 pin is placed in the high-impedance state at the same time the abt bit is set to 1 (unmatching detected). sda2 (1) in slave mode, ckdir is set to 1 (external clock) scl2 sda2 start condition detection interrupt stop condition detection interrupt (2) in master mode, ckdir is set to 0 (internal clock), ckph is set to 1(clock delayed) scl2 set stareq to 1 (start) set stpreq to 1 (start) stpsel bit 0 stpsel bi t set to 1 by program set to 0 by program set to 1 by program set to 0 by program 1st 2nd 3rd 5th 6th 7th 8th 9th bit 1st 2nd 3rd 5th 6th 7th 8th 9th bit 4th 4th start condition detection interrupt stop condition detection interrupt
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 192 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 14.1.3.4 transfer clock data is transmitted/received using a transfer clock like the one shown in figure 14.25 . the csc bit in the u2smr2 register is used to synchronize the internally generated clock (internal scl2) and an external clock supplied to the scl 2 pin. in cases when the csc bit is set to 1 (clock synchronization enabled), if a falling edge on the scl 2 pin is detected while the internal scl 2 is high, the internal scl 2 goes low, at which time the u2brg register value is reloaded with and starts count- ing in the low-level interval. if the internal scl 2 changes state from low to high while the scl 2 pin is low, counting stops, and when the scl 2 pin goes high, counting restarts. in this way, the uart2 transfer clock is comprised of the logical product of the internal scl 2 and scl 2 pin signal. the transfer clock works from a half period before the falling edge of the internal scl 2 1st bit to the rising edge of the 9 th bit. to use this function, select an internal clock for the transfer clock. the swc bit in the u2smr2 register allows to select whether the scl 2 pin should be fixed to or freed from low-level output at the falling edge of the 9th clock pulse. if the sclhi bit in the u2smr4 register is set to 1 (enabled), scl 2 output is turned off (placed in the high-impedance state) when a stop condition is detected. setting the swc2 bit in the u2smr2 register is set to 1 (0 output) makes it possible to forcibly output a low-level signal from the scl 2 pin even while sending or receiving data. clearing the swc2 bit to 0 (transfer clock) allows the transfer clock to be output from or supplied to the scl 2 pin, instead of outputting a low-level signal. if the swc9 bit in the u2smr4 register is set to 1 (scl 2 hold low enabled) when the ckph bit in the u2smr3 register is set to 1, the scl 2 pin is fixed to low-level output at the falling edge of the clock pulse next to the ninth. setting the swc9 bit to 0 (scl 2 hold low disabled) frees the scl 2 pin from low-level output. 14.1.3.5 sda output the data written to the bit 7 to bit 0 (d 7 to d 0 ) in the u2tb register is sequentially output beginning with d 7 . the ninth bit (d 8 ) is ack or nack. the initial value of sda 2 transmit output can only be set when iicm is set to 1 (i 2 c bus mode) and bits smd2 to smd0 in the u2mr register is set to 000 2 (serial i/o disabled). bits dl2 to dl0 in the u2smr3 register allow to add no delays or a delay of 2 to 8 u2brg count source clock cycles to sda 2 output. setting the sdhi bit in the u2smr2 register to 1 (sda 2 output disabled) forcibly places the sda 2 pin in the high-impedance state. do not write to the sdhi bit synchronously with the rising edge of the uart2 transfer clock. this is because the abt bit may inadvertently be set to 1 (detected). 14.1.3.6 sda input when the iicm2 bit is set to 0, the 1st to 8th bits (d 7 to d 0 ) in the received data are stored in bits 7 to 0 in the u2rb register. the 9th bit (d 8 ) is ack or nack. when the iicm2 bit is set to 1, the 1st to 7th bits (d 7 to d 1 ) in the received data are stored in the bit 6 to bit 0 in the u2rb register and the 8th bit (d 0 ) is stored in the bit 8 in the u2rb register. even when the iicm2 bit is set to 1, providing the ckph bit is set to 1, the same data as when the iicm2 bit is set to 0 can be read out by reading the u2rb register after the rising edge of the corresponding clock pulse of 9th bit.
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 193 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 14.1.3.7 ack and nack if the stspsel bit in the u2smr4 register is set to 0 (start and stop conditions not generated) and the ackc bit in the u2smr4 register is set to 1 (ack data output), the value of the ackd bit in the u2smr4 register is output from the sda 2 pin. if the iicm2 bit is set to 0, a nack interrupt request is generated if the sda 2 pin remains high at the rising edge of the 9th bit of transmit clock pulse. an ack interrupt request is generated if the sda 2 pin is low at the rising edge of the 9th bit of transmit clock pulse. if ack2 is selected for the cause of dma1 request, a dma transfer can be activated by detection of an acknowledge. 14.1.3.8 initialization of transmission/reception if a start condition is detected while the stac bit is set to 1 (uart2 initialization enabled), the serial i/ o operates as described below. - the transmit shift register is initialized, and the content of the u2tb register is transferred to the transmit shift register. in this way, the serial i/o starts sending data synchronously with the next clock pulse applied. however, the uart2 output value does not change state and remains the same as when a start condition was detected until the first bit in the data is output synchronously with the input clock. - the receive shift register is initialized, and the serial i/o starts receiving data synchronously with the next clock pulse applied. - the swc bit is set to 1 (scl 2 wait output enabled). consequently, the scl 2 pin is pulled low at the falling edge of the ninth clock pulse. note that when uart2 transmission/reception is started using this function, the ti does not change state. note also that when using this function, the selected transfer clock should be an external clock.
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 194 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 14.1.4 special mode 2 (uart2) multiple slaves can be serially communicated from one master. transfer clock polarity and phase are selectable. table 14.15 lists the specifications of special mode 2. table 14.16 lists the registers used in special mode 2 and the register values set. figure 14.26 shows communication control example for special mode 2. table 14.15 special mode 2 specifications item specification transfer data format ? transfer data length: 8 bits transfer clock ? master mode the ckdir bit in the u2mr register is set to 0 (internal clock) : fj/ (2(n+1)) fj = f 1sio , f 2sio , f 8sio , f 32sio . n: setting value in the u2brg register 00 16 to ff 16 ? slave mode ckdir bit is set to 1 (external clock selected) : input from clk2 pin transmit/receive control controlled by input/output ports transmission start condition ? before transmission can start, the following requirements must be met (1) _ the te bit in the u2c1 register is set to 1 (transmission enabled) _ the ti bit in the u2c1 register is set to 0 (data present in u2tb register) reception start condition ? before reception can start, the following requirements must be met (1) _ the re bit in the u2c1 register is set to 1 (reception enabled) _ the te bit in the u2c1 register is set to 1 (transmission enabled) _ the ti bit in the u2c1 register is set to 0 (data present in the u2tb register) ? for transmission, one of the following conditions can be selected _ the u2irs bit in the u2c1 register is set to 0 (transmit buffer empty): when trans ferring data from the u2tb register to the uart2 transmit register (at start of transmission) _ the u2irs bit is set to 1 (transfer completed): when the serial i/o finished sending data from the uart2 transmit register ? for reception when transferring data from the uart2 receive register to the u2rb register (at completion of reception) error detection ? overrun error (2) this error occurs if the serial i/o started receiving the next data before reading the u2rb register and received the 7th bit in the the next data select function ? clock phase setting selectable from four combinations of transfer clock polarities and phases notes: 1. when an external clock is selected, the conditions must be met while if the ckpol bit in the u2c0 register is set to 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the high state; if the ckpol bit in the u2c0 register is set to 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state. 2. if an overrun error occurs, bits 8 to 0 in the u2rb register are undefined. the ir bit in the s2ric register remains unchanged. interrupt request generation timing
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 195 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r table 14.16 registers to be used and settings in special mode 2 register bit function u2tb (1) 0 to 7 set transmission data u2rb (1) 0 to 7 reception data can be read oer overrun error flag u2brg 0 to 7 set a transfer rate u2mr (1) smd2 to smd0 set to 001 2 ckdir set this bit to 0 for master mode or 1 for slave mode iopol set to 0 u2c0 clk1, clk0 select the count source for the u2brg register crs invalid because crd is set to 1 txept transmit register empty flag crd set to 1 nch select txd2 pin output format ckpol clock phases can be set in combination with the ckph bit in the u2smr3 register uform select the lsb first or msb first u2c1 te set this bit to 1 to enable transmission ti transmit buffer empty flag re set this bit to 1 to enable reception ri reception complete flag u2irs select uart2 transmit interrupt cause u2rrm, set to 0 u2lch, u2ere u2smr 0 to 7 set to 0 u2smr2 0 to 7 set to 0 u2smr3 ckph clock phases can be set in combination with the ckpol bit in the u2c0 register nodc set to 0 0, 2, 4 to 7 set to 0 u2smr4 0 to 7 set to 0 note: 1.not all bits in the registers are described above. set those bits to 0 when writing to the registers in special mode 2. figure 14.26 serial bus communication control example (uart2) p1 3 p1 2 p7 0( txd 2 ) p7 2( clk 2 ) p7 1( rxd 2 ) p9 3 p7 0( txd 2 ) p7 2( clk 2 ) p7 1( rxd 2 ) p9 3 p7 0( txd 2 ) p7 2( clk 2 ) p7 1( rxd 2 ) mcu (master) mcu (slave) mcu (slave)
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 196 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 14.1.4.1 clock phase setting function one of four combinations of transfer clock phases and polarities can be selected using the ckph bit in the u2smr3 register and the ckpol bit in the u2c0 register. make sure the transfer clock polarity and phase are the same for the master and slave to communi- cate. 14.1.4.1.1 master (internal clock) figure 14.27 shows the transmission and reception timing in master (internal clock). 14.1.4.1.2 slave (external clock) figure 14.28 shows the transmission and reception timing (ckph=0) in slave (external clock) while figure 14.29 shows the transmission and reception timing (ckph=1) in slave (external clock). figure 14.27 transmission and reception timing in master mode (internal clock) d a t a o u t p u t t i m i n g d a t a i n p u t t i m i n g d 0 d 1 d 2 d 3 d 4 d 6 d 7 d 5 c l o c k o u t p u t ( c k p o l = 0 , c k p h = 0 ) " h " " l " c l o c k o u t p u t ( c k p o l = 1 , c k p h = 0 ) " h " " l " c l o c k o u t p u t ( c k p o l = 0 , c k p h = 1 ) " h " " l " clock output (ckpol=1, ckph= 1) "h" " l " "h" "l "
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 197 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 14.28 transmission and reception timing (ckph=0) in slave mode (external clock) figure 14.29 transmission and reception timing (ckph=1) in slave mode (external clock) slave control input clock input (ckpol=0, ckph=0) clock input (ckpol=1, ckph=0) data output timing data input timin g "h" "l" "h" "l" "h" "l" "h" "l" d 0 d 1 d 2 d 3 d 4 d 6 d 7 d 5 undefined clock input (ckpol=0, ckph=1) clock input (ckpol=1, ckph=1) data output timing data input timing "h" "l" "h" "l" "h" "l" "h" "l" d 0 d 1 d 2 d 3 d 6 d 7 d 4 d 5 slave control input
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 198 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 14.1.5 special mode 3 (iebus mode)(uart2) in this mode, one bit in the iebus is approximated with one byte of uart mode waveform. table 14.17 lists the registers used in iebus mode and the register values set. figure 14.30 shows the functions of bus collision detect function related bits. if the txd2 pin output level and rxd2 pin input level do not match, a uart2 bus collision detect interrupt request is generated. table 14.17 registers to be used and settings in iebus mode register bit function u2tb 0 to 8 set transmission data u2rb (1) 0 to 8 reception data can be read oer,fer,per,sum error flag u2brg 0 to 7 set a transfer rate u2mr smd2 to smd0 set to 110 2 ckdir select the internal clock or external clock stps set to 0 pry invalid because prye is set to 0 prye set to 0 iopol select the txd/rxd input/output polarity u2c0 clk1, clk0 select the count source for the u2brg register crs invalid because crdis set to 1 txept transmit register empty flag crd set to 1 nch select txd2 pin output mode ckpol set to 0 uform set to 0 u2c1 te set this bit to 1 to enable transmission ti transmit buffer empty flag re set this bit to 1 to enable reception ri reception complete flag u2irs select the source of uart2 transmit interrupt u2rrm, set to 0 u2lch, u2ere u2smr 0 to 3, 7 set to 0 abscs select the sampling timing at which to detect a bus collision acse set this bit to 1 to use the auto clear function of transmit enable bit sss select the transmit start condition u2smr2 0 to 7 set to 0 u2smr3 0 to 7 set to 0 u2smr4 0 to 7 set to 0 note: 1. not all register bits are described above. set those bits to 0 when writing to the registers in iebus mode.
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 199 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 14.30 bus collision detect function-related bits (2) the acse bit in the u2smr register (auto clear of transmit enable bit) (1) the abscs bit in the u2smr register (bus collision detect sampling clock select) if abscs=0, bus collision is determined at the rising edge of the transfer clock transfer clock timer a0 (3) the sss bit in the u2smr register (transmit start condition select) transmission enable condition is met if sss bit = 1, the serial i/o starts sending data at the rising edge (note 1) of rxd2 txd2 clk2 txd2 rxd2 txd2 rxd2 st d0 d1 d2 d3 d4 d5 d6 d7 d8 sp input to ta0 in if abscs is set to 1, bus collision is determined when timer a0 (one-shot timer mode) underflows . txd2 rxd2 st d0 d1 d2 d3 d4 d5 d6 d7 d8 sp st d0 d1 d2 d3 d4 d5 d6 d7 d8 sp st d0 d1 d2 d3 d4 d5 d6 d7 d8 sp transfer clock bcnic register ir bit (note) u2c1 register te bit if acse bit is set to 1 automatically clear when bus collision occurs), the te bit is cleared to 0 (transmission disabled) when the ir bit in the bcnic register is set to 1 (unmatching detected). if sss bit is set to 0, the serial i/o starts sending data one transfer clock cycle after the transmission enable condition is met. transfer clock (note 2) notes: 1: the falling edge of rxd2 when the iopol is set to 0; the rising edge of rxd2 when the iopol is set to 1. 2: the transmit condition must be met before the falling edge (note 1) of rxd. this diagram applies to the case where the iopol is set to 1 (reversed) .
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 200 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r item specification transfer data format ? direct format ? inverse format transfer clock ? the ckdir bit in the u2mr register is set to 0 (internal clock) : fi/ (16(n+1)) fi = f 1sio , f 2sio , f 8sio , f 32sio . n: setting value of u2brg register 00 16 to ff 16 ? the ckdir bit is set to 1 (external clock) : f ext /16(n+1) f ext : input from clk 2 pin. n: setting value of u2brg register 00 16 to ff 16 transmission start ? before transmission can start, the following requirements must be met condition _ the te bit in the u2c1 register is set to 1 (transmission enabled) _ the ti bit in the u2c1 register is set to 0 (data present in u2tb register) reception start ? before reception can start, the following requirements must be met condition _ the re bit in the u2c1 register is set to 1 (reception enabled) _ start bit detection ? for transmission when the serial i/o finished sending data from the u2tb transfer register (u2irs bit =1) ? for reception when transferring data from the uart2 receive register to the u2rb register (at completion of reception) error detection ? overrun error (1) this error occurs if the serial i/o started receiving the next data before reading the u2rb register and received the bit one before the last stop bit in the the next data ? framing error this error occurs when the number of stop bits set is not detected ? parity error during reception, if a parity error is detected, parity error signal is output from the txd 2 pin. during transmission, a parity error is detected by the level of input to the r x d 2 pin when a transmission interrupt occurs ? error sum flag this flag is set to 1 when any of the overrun, framing, and parity errors is encountered 14.1.6 special mode 4 (sim mode) (uart2) based on uart mode, this is an sim interface compatible mode. direct and inverse formats can be implemented, and this mode allows output of a low from the txd2 pin when a parity error is detected. tables 14.18 lists the specifications of sim mode. table 14.19 lists the registers used in the sim mode and the register values set. table 14.18 sim mode specifications interrupt request generation timing (2) notes: 1. if an overrun error occurs, bits 8 to 0 in the u2rb register are undefined. the ir bit in the s2ric register remains unchanged. 2. a transmit interrupt request is generated by setting the u2irs bit in the u2c1 register to 1 (transmis- sion complete) and u2ere bit to 1 (error signal output) after reset. therefore, when using sim mode, be sure to clear the ir bit to 0 (no interrupt request) after setting these bits.
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 201 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r table 14.19 registers to be used and settings in sim mode register bit function u2tb (1) 0 to 7 set transmission data u2rb (1) 0 to 7 reception data can be read oer,fer,per,sum error flag u2brg 0 to 7 set a transfer rate u2mr smd2 to smd0 set to 101 2 ckdir select the internal clock or external clock stps set to 0 pry set this bit to 1 for direct format or 0 for inverse format prye set to 1 iopol set to 0 u2c0 clk1, clk0 select the count source for the u2brg register crs invalid because crdis set to 1 txept transmit register empty flag crd set to 1 nch set to 0 ckpol set to 0 uform set this bit to 0 for direct format or 1 for inverse format u2c1 te set this bit to 1 to enable transmission ti transmit buffer empty flag re set this bit to 1 to enable reception ri reception complete flag u2irs set to 1 u2rrm set to 0 u2lch set this bit to 0 for direct format or 1 for inverse format u2ere set to 1 u2smr (1) 0 to 3 set to 0 u2smr2 0 to 7 set to 0 u2smr3 0 to 7 set to 0 u2smr4 0 to 7 set to 0 note: 1. not all register bits are described above. set those bits to 0 when writing to the registers in sim mode.
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 202 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 14.31 transmit and receive timing in sim mode d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st pd 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp sp d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp sp start bit parity bit 0 1 0 1 0 1 set to 0 by an interrupt request acknowledgement or by program tc transfer clock stop bit data is written to the uart2 register an "l" signal is applied from the sim card due to a parity error an interrupt routine detects "h" or "l" txd2 0 1 transfer clock read the u2rb register rxd 2 pin level (2) txd 2 rxd 2 pin level (1) data is transferred from the u2tb register to the uart2 transmit register re bit in u2c1 register ri bit in u2c1 register ir bit in s2ric register te bit in u2c1 register ti bit in u2c1 register txept bit in u2 c0 register ir bit in s2tic register start bit set to 0 by an interrupt request acknowledgement or by program stop bit txd 2 outputs "l" due to a parity error parity bit 0 1 0 0 1 (1) transmit timing (2) receive timing parity error signal returned from receiving end transmit waveform from the transmitting end 1 sp an interrupt routine detects "h" or "l " sp tc the above timing diagram applies to the case where data is transferred in the direct format. ? u2mr register stps bit = 0 (1 stop bit) ? u2mr register pry bit = 1 (even) ? u2c0 register uform bit = 0 (lsb first) ? u2c1 register u2lch bit = 0 (no reverse) ? u2c1 register u2irsch bit = 1 (transmit is completed) tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of u2brg count source (f 1sio , f 2sio , f 8sio , f 32sio ) f ext : frequency of u2brg count source (external clock) n : value set to u2brg the above timing diagram applies to the case where data is transferred in the direct format. ? u2mr register stps bit = 0 (1 stop bit) ? u2mr register pry bit = 1 (even) ? u2c0 register uform bit = 0 (lsb first) ? u2c1 register u2lch bit = 0 (no reverse) ? u2c1 register u2irsch bit = 1 (transmit is completed) tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of u2brg count source (f 1sio , f 2sio , f 8sio , f 32sio ) f ext : frequency of u2brg count source (external clock) n : value set to u2brg notes: 1. because txd 2 and rxd 2 are connected, this is composite waveform consisting of the txd 2 output and the parity error signal sent back from receiver. 2. because txd 2 and rxd 2 are connected, this is composite waveform consisting of the transmitter's transmit waveform and the parity error signal received.
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 203 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 14.32 shows the example of connecting the sim interface. connect t x d 2 and r x d 2 and apply pull-up. figure 14.32 sim interface connection 14.1.6.1 parity error signal output the parity error signal is enabled by setting the u2ere bit in theu2c1 register to 1. ? when receiving the parity error signal is output when a parity error is detected while receiving data. this is achieved by pulling the txd2 output low with the timing shown in figure 14.33 . if the r2rb register is read while outputting a parity error signal, the per bit is cleared to 0 and at the same time the txd2 output is returned high. ? when transmitting a transmission-finished interrupt request is generated at the falling edge of the transfer clock pulse that immediately follows the stop bit. therefore, whether a parity signal has been returned can be determined by reading the port that shares the rxd2 pin in a transmission-finished interrupt service routine. figure 14.33 parity error signal output timing mcu sim card txd 2 rxd 2 d0 d1 d2 d3 d4 d5 d6 d7 psp st (1) transfer clock rxd 2 txd 2 u2c1 register ri bit ? h ? ? l ? ? h ? ? l ? ? h ? ? l ? 1 0 this timing diagram applies to the case where the direct format is implemented. note: 1. the output of mcu is in the high-impedance state (pulled up externally). st: start bit p: even parity sp: stop bit
14. serial i/o ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m page 204 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 14.1.6.2 format ? direct format set the pry bit in the u2mr register to 1, the uform bit in u2c0 register to 0 and the u2lch bit in u2c1 register to 0. ? inverse format set the pry bit to 0, uform bit to 1 and u2lch bit to 1. figure 14.34 shows the sim interface format. figure 14.34 sim interface format p : even parity d0 d1 d2 d3 d4 d5 d6 d7 p transfer clcck txd 2 txd 2 d7 d6 d5 d4 d3 d2 d1 d0 p transfer clcck (1) direct format ? h ? ? l ? ? h ? ? l ? (2) inverse format p : odd parity ? h ? ? l ? ? h ? ? l ?
14. serial i/o page 205 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 14.2 si/o3 and si/o4 note the si/o4 interrupt of peripheral function interrupt is not available in the 64-pin package. si/o3 and si/o4 are exclusive clock-synchronous serial i/os. figure 14.35 shows the block diagram of si/o3 and si/o4, and figure 14.36 shows the si/o3 and si/o4- related registers. table 14.20 shows the specifications of si/o3 and si/o4. figure 14.35 si/o3 and si/o4 block diagram data bus si/oi interrupt request note: i = 3, 4. n = a value set in the sibrg register. sitrr register si/o counter i 8 smi5 lsb msb smi2 smi3 smi3 smi6 smi1 to smi0 clk i s outi s ini sibrg register smi6 1/(n+1) 1/2 1/2 main clock, pll clock, or on-chip oscillator clock f 1sio 1/2 1/8 1/4 f 8sio f 32sio f 2sio pclk1=0 pclk1=1 smi4 00 2 01 2 10 2 clock source select synchronous circuit clk polarity reversing circuit
14. serial i/o page 206 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 14.36 s3c and s4c registers, s3brg and s4brg registers, and s3trr and s4trr registers b 7 b 0 symbol address after reset s3brg 0363 16 undefined s4brg 0367 16 undefined 0 0 1 6 t o f f 1 6 b 7 b 0 symbol address after reset s3trr 0360 16 undefined s4trr 0364 16 undefined s y m b o la d d r e s sa f t e r r e s e t s 3 c0 3 6 2 1 6 0 1 0 0 0 0 0 0 2 s 4 c0 3 6 6 1 6 0 1 0 0 0 0 0 0 2 b 7b 6b 5b 4b 3b 2b 1b 0 rw function smi5 s m i 1 smi0 s m i 3 smi6 s m i 7 internal synchronous clock select bit transfer direction select bit s i / o i p o r t s e l e c t b i t s o u t i i n i t i a l v a l u e s e t b i t 0 0 : selecting f 1 or f 2 0 1 : selecting f 8 1 0 : selecting f 32 1 1 : do not set b1 b0 0 : external clock (2) 1 : internal clock (3) effective when the smi3 is set to 0 0 : ? l ? output 1 : ? h ? output 0 : input/output port 1 : s out i output, clki function bit name b i t s y m b o l synchronous clock select bit 0 : lsb first 1 : msb firs t s m i 2s o u t i o u t p u t d i s a b l e b i t0 : s out i output 1 : s out i output disable(high impedanc e) s m i 4c l k p o l a r i t y s e l c t b i t 0 : transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : transmit data is output at rising edge of transfer clock and receive data is input at falling edg e rw rw rw rw rw rw rw rw rw rw rw w o ( 4 ) ( 5 ) notes: 1. set the s4c register by the next instruction after setting the prc2 bit in the prcr register to 1 (write enable). 2. set the smi3 bit to 1 and the corresponding port direction bit to 0 (input mode). 3. set the smi3 bit to 1 (souti output, clki function) . 4. when the smi2 bit is set to 1, the corresponding pin goes to high-impedance regardless of the function in use. 5. when the smi1 and smi0 bit settings are changed, set the sibrg register . notes: 1. write to this register while serial i/o is neither transmitting or receiving. 2. to receive data, set the corresponding port direction bit for s in i to 0 (input mode). notes: 1. write to this register while serial i/o is neither transmitting or receiving. 2. use mov instruction to write to this register. 3. set the sibrg register after setting bits smi1 and smi0 in the sic register. transmission/reception starts by writing transmit data to this register. after transmission/reception completion, reception data can be read by reading this register. assuming that set value = n, brgi divides the count source by n + 1 setting range description description si/oi control register (i = 3, 4) (1) si/oi bit rate generation register (i = 3, 4) (1, 2, 3) si/oi transmit/receive register (i = 3, 4) (1, 2)
14. serial i/o page 207 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m item specification transfer data format ? transfer data length: 8 bits transfer clock ? the smi6 bit in the sic (i=3, 4) register is set to 1 (internal clock) : fj/ (2(n+1)) fj = f 1sio , f 2sio , f 8sio , f 32sio . n=setting value of sibrg register 00 16 to ff 16 . ? smi6 bit is set to 0 (external clock) : input from clki pin (1) transmission/reception ? before transmission/reception can start, the following requirements must be met start condition write transmit data to the sitrr register (2, 3) ? when the smi4 bit in the sic register is set to 0 the rising edge of the last transfer clock pulse (4) ? when smi4 is set to 1 the falling edge of the last transfer clock pulse (4) clki pin fucntion i/o port, transfer clock input, transfer clock output s out i pin function i/o port, transmit data output, high-impedance sini pin function i/o port, receive data input select function ? lsb first or msb first selection whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected ? function for setting an s out i initial value set function when the smi6 bit in the sic register is set to 0 (external clock), the s out i pin output level while not tranmitting can be selected. ? clk polarity selection whether transmit data is output/input timing at the rising edge or falling edge of transfer clock can be selected. note: 1. to set the smi6 bit in the sic register to 0 (external clock), follow the procedure described below. ? if the smi4 bit in the sic register is set to 0, write transmit data to the sitrr register while input on the clki pin is high. the same applies when rewriting the smi7 bit in the sic register. ? if the smi4 bit is set to 1, write transmit data to the sitrr register while input on the clki pin is low. the same applies when rewriting the smi7 bit. ? because shift operation continues as long as the transfer clock is supplied to the si/oi circuit, stop the transfer clock 2. unlike uart0 to uart2, si/oi (i = 3 to 4) is not separated between the transfer register and buffer. therefore, do not write the next transmit data to the sitrr register during transmission. 3. when the smi6 bit in the sic register is set to 1 (internal clock), s outi retains the last data for a 1/2 transfer clock period after completion of transfer and, thereafter, goes to a high-impedance state. however, if transmit data is written to the sitrr register during this period, s outi immediately goes to a high-impedance state, with the data hold time thereby reduced. 4. when the smi6 bit in the sic register is set to 1 (internal clock), the transfer clock stops in the high state if the smi4 bit is set to 0, or stops in the low state if the smi4 bit is set to 1. table 14.20 si/o3 and si/o4 specifications interrupt request generation timing
14. serial i/o page 208 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 14.2.1 si/oi operation timing figure 14.37 shows the si/oi operation timing figure 14.37 si/oi operation timing 14.2.2 clk polarity selection the the smi4 bit in the sic register allows selection of the polarity of the transfer clock. figure 14.38 shows the polarity of the transfer clock. figure 14.38 polarity of transfer clock (2) when the smi4 bit in the sic register is set to 1 (3) d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 0 s ini s outi clk i (1) when the smi4 bit in the sic register is set to 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 s ini s outi clk i (2) i=3 and 4 notes: 1. this diagram applies to the case where the sic register bits are set as follows: smi5 = 0 (lsb first) and smi6 = 1 (internal clock) 2. when the smi6 bit is set to 1 (internal clock), a high level is output from the clki pin if not transferring data. 3 when the smi6 bit is set to 1 (internal clock), a low level is output from the clki pin if not transferring data. d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 i= 3, 4 1.5 cycle (max) si/oi internal clock clki output signal written to the sitrr register s out i output s in i input siic register ir bit (2) "h" "l" "h" "l" "h" "l" "h" "l" "h" "l" 1 0 (3) notes: 1. this diagram applies to the case where the sic register bits are set as follows: smi2 = 0 (s out i output), smi3 = 1 (s out i output, clki function), smi4 = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock), smi5 = 0 (lsb first) and smi6 = 1 (internal clock) 2. when the smi6 bit is set to 0 (internal clock), the s out i pin is placed in the high-impedance state after the transfer is completed. 3. if the smi6 bit is set to 0 (internal clock), the serial i/o starts sending or receiving data a maximum of 1.5 transfer clock c ycles after writing to the sitrr register.
14. serial i/o page 209 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 14.2.3 functions for setting an s out i initial value if the smi6 bit in sic register is set to 0 (external clock), the s outi pin output level can be fixed high or low when not transferring data. however, when transmitting data consecutively, the last bit (bit 0) value of the last transmitted data is retained between the sccessive data transmissions. figure 14.39 shows the timing chart for setting an s outi initial value and how to set it. figure 14.39 s out i initial value setting s i g n a l w r i t t e n t o s i t r r r e g i s t e r s o u t i ( i n t e r n a l ) s m i 7 b i t s out i pin outpu t s m i 3 b i t s e t t i n g t h e s o u t i i n i t i a l v a l u e t o ? h ? port selection switching (i/o port s out i) d 0 ( i = 3 , 4 ) i n i t i a l v a l u e = ? h ? ( 3 ) port output d 0 ( e x a m p l e ) w h e n ? h ? s e l e c t e d f o r s o u t i i n i t i a l v a l u e ( 1 ) ( 2 ) notes: 1. this diagram applies to the case where the bits in the sic register are set as follows: smi2 = 0 (s out i output), smi5 = 0 (lsb first) and smi6 = 0 (external clock) 2. s out i can only be initialized when input on the clki pin is in the high state if the smi4bit in the sic register is set to 0 (transmit data output at the falling edge of the transfer clock) or in the low state if the smi4 bit is set to 1 (transmit data output at the rising edge of the transfer clock). 3. if the smi6 bit is set to 1 (internal clock) or if the smi2 bit is set to 1 (s outi output disabled), this output goes to the high-impedance state. setting of the initial value of s out i output and starting of transmission/ reception set the smi3 bit to 0 (s out i pin functions as an i/o port) write to the sitrr register serial transmit/reception starts set the smi7 bit to 1 (s out i initial value = ? h ? ) set the smi3 bit to 1 (s out i pin functions as s out i output) ? h ? level is output from the s out i pin
15. a/d converter page 210 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 15. a/d converter note ports p0 4 to p0 7 (an0 4 to an0 7 ), p1 0 to p1 3 (an2 0 to an2 3 ) and p9 5 to p9 7 (an2 5 to an2 7 ) are not available in 64-pin package. do not use port p0 4 to p0 7 (an0 4 to an0 7 ), p1 0 to p1 3 (an2 0 to an2 3 ) and p9 5 to p9 7 (an2 5 to an2 7 ) as analog input pins in 64-pin ver. the mcu contains one a/d converter circuit based on 10-bit successive approximation method configured with a capacitive-coupling amplifier. the analog inputs share the pins with p10 0 to p10 7 (an 0 to an 7 ), p0 0 to p0 7 (an0 0 to an0 7 ), and p1 0 to p1 3 , p9 3 , p9 5 to p9 7 (an2 0 to an2 7 ), and p9 0 to p9 2 (an3 0 to an3 2 ). ____________ similarly, ad trg input shares the pin with p1 5 . therefore, when using these inputs, make sure the corre- sponding port direction bits are set to 0 (input mode). when not using the a/d converter, set the vcut bit to 0 (vref unconnected), so that no current will flow from the vref pin into the resistor ladder, helping to reduce the power consumption of the chip. the a/d conversion result is stored in the adi register bits for an i , an0 i , an2 i (i = 0 to 7), and an3 i pins (i = 0 to 2). table 15.1 shows the a/d converter performance. figure 15.1 shows the a/d converter block diagram and figures 15.2 to 15.5 show the a/d converter associated with registers. item performance a/d conversion method successive approximation (capacitive coupling amplifier) analog input voltage (1) 0v to av cc (v cc ) operating clock ad (2) f ad /divided-by-2 or f ad /divided-by-3 or f ad /divided-by-4 or f ad /divided-by-6 or f ad /divided-by-12 or f ad resolution 8-bit or 10-bit (selectable) integral nonlinearity error when av cc = vref = 5v ? with 8-bit resolution: 2lsb ? with 10-bit resolution: 3lsb when av cc = vref = 3.3v ? with 8-bit resolution: 2lsb ? with 10-bit resolution: 5lsb operating modes one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, repeat sweep mode 1, simultaneous sample sweep mode and delayed trigger mode 0,1 analog input pins 8 pins (an 0 to an 7 ) + 8 pins (an0 0 to an0 7 ) + 8 pins (an2 0 to an2 7 ) + 3 pins (an3 0 to an3 2 ) (80pin-ver.) 8 pins (an 0 to an 7 ) + 4 pins (an0 0 to an0 3 ) + 1 pin (an2 4 ) + 3 pins (an3 0 to an3 2 ) (64pin-ver.) conversion speed per pin ? without sample and hold function 8-bit resolution: 49 ad cycles , 10-bit resolution: 59 ad cycles ? with sample and hold function 8-bit resolution: 28 ad cycles , 10-bit resolution: 33 ad cycles table 15.1 a/d converter performance notes: 1. not dependent on use of sample and hold function. 2. set the ad frequency to 10 mhz or less. without sample-and-hold function, set the ad frequency to 250 kh z or more. with the sample and hold function, set the ad frequency to 1mh z or more.
15. a/d converter page 211 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 15.1 a/d converter block diagram =000 2 =001 2 =010 2 =011 2 =100 2 =101 2 =110 2 =111 2 an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 an 00 an 01 an 02 an 03 an 04 an 05 an 06 an 07 v ref v in ch2 to ch0 decoder for channel selection a/d register 0(16) data bus low-order v ref av ss vcut=0 vcut=1 data bus high-order port p10 group adgsel1 to adgsel0=10 2 adgsel1 to adgsel0=00 2 adgsel1 to adgsel0=11 2 f ad cks0=1 cks0=0 cks1=1 cks1=0 1/3 cks2=0 cks2=1 1/2 1/2 ? ad a/d conversion rate selection (03c1 16 to 03c0 16 ) (03c3 16 to 03c2 16 ) (03c5 16 to 03c4 16 ) (03c7 16 to 03c6 16 ) (03c9 16 to 03c8 16 ) (03cb 16 to 03ca 16 ) (03cd 16 to 03cc 16 ) (03cf 16 to 03ce 16 ) resistor ladder successive conversion register adcon0 register (address 03d6 16 ) adcon1 register (address 03d7 16 ) comparator 0 addresses decoder for a/d register a/d register 1(16) a/d register 2(16) a/d register 3(16) a/d register 4(16) a/d register 5(16) a/d register 6(16) a/d register 7(16) adcon2 register (address 03d4 16 ) port p0 group =000 2 =001 2 =010 2 =011 2 =100 2 =101 2 =110 2 =111 2 ch2 to ch0 sse = 1 ch2 to ch0=001 2 comparator 1 adgsel1 to adgsel0=00 2 adgsel1 to adgsel0=10 2 adgsel1 to adgsel0=11 2 v in 1 port p1/port p9 group an 20 an 21 an 22 an 23 an 24 an 25 an 26 an 27 =000 2 =001 2 =010 2 =011 2 =100 2 =101 2 =110 2 =111 2 ch2 to ch0 (note) note: an 04 to an 07 , an 20 to an 23 , and an 25 to an 27 , is available for only 80-pin package. (note) port p9 group an 30 an 31 an 32 =000 2 =001 2 =010 2 ch2 to ch0 adgsel1 to adgsel0=01 2 adgsel1 to adgsel0=01 2
15. a/d converter page 212 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 15.2 adcon0 to adcon2 registers a/d control register 0 (1) symbol address after reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a/d operation mode select bit 0 md0 md1 trigger select bit 0: software trigger 1: hardware trigger trg adst a/d conversion start flag 0: a/d conversion disabled 1: a/d conversion started frequency select bit 0 see table 15.2 cks0 rw note: 1. if the adcon0 register is rewritten during a/d conversion, the conversion result will be undefined. rw rw rw rw rw rw rw rw function varies with each operation mode b4 b3 0 0: one-shot mode or delayed trigger mode 0,1 0 1: repeat mode 1 0: single sweep mode or simultaneous sample sweep mode 1 1: repeat sweep mode 0 or repeat sweep mode 1 a/d control register 1 (1) symbol address after reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut a/d operation mode select bit 1 0 : other than repeat sweep mode 1 1 : repeat sweep mode 1 0 : vref not connected 1 : vref connected frequency select bit 1 cks1 rw rw rw rw rw rw rw function varies with each operation mode see table 15.2 nothing is assigned. if necessary, set to 0. when read, the content is 0 (b7-b6) notes: 1. if the adcon1 register is rewritten during a/d conversion, the conversion result will be undefined. 2. if the vcut bit is reset from 0 (vref unconnected) to 1 (vref connected), wait for 1 s or more before starting a/d conversion. vref connect bit (2) 0 a/d control register 2 (1) symbol address after reset adcon2 03d4 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d conversion method select bit smp reserved bit set to 0 trg1 a/d input group select bit b2 b1 0 0: select port p10 group 0 1: select port p9 group 1 0: select port p0 group 1 1: select port p1/p9 group function varies with each operation mode frequency select bit 2 cks2 rw rw rw rw rw rw rw 0: without sample and hold 1: with sample and hold see table 15.2 nothing is assigned. if necessary, set to 0. when read, the content is 0 (b7-b6) note: 1. if the adcon2 register is rewritten during a/d conversion, the conversion result will be undefined. trigger select bit adgsel0 adgsel1 (b3)
15. a/d converter page 213 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 15.3 adtrgcon register table 15.2 a/d conversion frequency select 2 s k c1 s k c0 s k cd a ? 000 4 y b d e d i v i d d a f 00 1 2 y b d e d i v i d d a f 010 d a f 011 10 0 2 1 y b d e d i v i d d a f 10 1 6 y b d e d i v i d d a f 110 3 y b d e d i v i d d a f 111 : e t o n . 1? e h t n i t i b 0 s k c e h t f o n o i t a n i b m o c . z h m 0 1 r e d n u e b t s u m y c n e u q e r f d a e h t n i t i b 2 s k c e h t d n a , r e t s i g e r 1 n o c d a e h t n i t i b 1 s k c e h t , r e t s i g e r 0 n o c d a s t c e l e s r e t s i g e r 2 n o c d a. d a ? a/d trigger control register (1, 2) symbol address after reset adtrgcon 03d2 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 a/d operation mode select bit 2 0 : other than simultaneous sample sweep mode or delayed trigger mode 0,1 1 : simultaneous sample sweep mode or delayed trigger mode 0,1 bit symbol bit name function rw sse a/d operation mode select bit 3 hptrg1 dte hptrg0 rw rw rw rw nothing is assigned. if necessary, set to 0. when read, its content is 0 (b7-b4) 0 : other than delayed trigger mode 0,1 1 : delayed trigger mode 0, 1 notes: 1. if the adtrgcon register is rewritten during a/d conversion, the conversion result will be undefined. 2. set 00 16 in this register in one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0 and repeat sweep mode 1. an1 trigger select bit an0 trigger select bit function varies with each operation mode function varies with each operation mode
15. a/d converter page 214 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 15.4 adstat0 register and ad0 to ad7 registers a/d register i (i=0 to 7) symbol address after reset ad0 03c1 16 to 03c0 16 undefined ad1 03c3 16 to 03c2 16 undefined ad2 03c5 16 to 03c4 16 undefined ad3 03c7 16 to 03c6 16 undefined ad4 03c9 16 to 03c8 16 undefined ad5 03cb 16 to 03ca 16 undefined ad6 03cd 16 to 03cc 16 undefined ad7 03cf 16 to 03ce 16 undefined eight low-order bits of a/d conversion result functio n (b15) b7 b7 b0 b0 (b8) when the bits bit in the adcon1 register is 1 (10-bit mode) nothing is assigned. if necessary, set to 0. when read, its content is 0 when read, its content is undefined rw ro ro two high-order bits of a/d conversion result when the bits bit in the adcon1 register is 0 (8-bit mode) a/d conversion result a/d conversion status register 0 (1) symbol address after reset adstat0 03d3 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 an1 trigger status flag 0: an1 trigger did not occur during an0 conversion 1: an1 trigger occured during an0 conversion bit symbol bit name function rw aderr0 conversion termination fla g an0 conversion status flag adstt0 aderr1 adtcsf rw ro rw ro ro nothing is assigned. if necessary, set to 0. when read, its content is 0 (b2) adstrt0 an0 conversion completion status fla g 0: conversion not terminated 1: conversion terminated by timer b0 underflo w delayed trigger sweep status flag 0: sweep not in progress 1: sweep in progress 0: an0 conversion not in progress 1: an0 conversion in progress adstt1 rw 0: an0 conversion not completed 1: an0 conversion completed adstrt1 rw an1 conversion status flag 0: an1 conversion not in progress 1: an1 conversion in progress an1 conversion completion status flag 0: an1 conversion not completed 1: an1 conversion completed note: 1. adstat0 register is valid only when the dte bit in the adtrgcon register is set to 1. rw
15. a/d converter page 215 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 15.5 tb2sc register pwcom symbol address after reset tb2sc 039e 16 x0000000 2 timer b2 reload timing switch bit 0: timer b2 underflow 1: timer a output at odd-numbered timer b2 special mode register (1) bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 ivpcr1 three-phase output port sd control bit 1 (3, 4, 7) 0: three-phase output forcible cutoff by sd pin input (high impedance) disabled 1: three-phase output forcible cutoff by sd pin input (high impedance) enabled notes: 1. write to this register after setting the prc1 bit in the prcr register to 1 (write enabled). 2. if the inv11 bit is 0 (three-phase mode 0) or the inv06 bit is 1 (triangular wave modulation mode), set this bit to 0 (timer b2 underflow). rw rw rw (2) nothing is assigned. if necessary, set to 0. when read, its content is 0 (b7) tb2sel trigger select bit 0: tb2 interrupt 1: underflow of tb2 interrupt generation frequency setting counter [ictb2] (6) rw rw tb0en timer b0 operation mode select bit 0: other than a/d trigger mode 1: a/d trigger mode (5) rw tb1en timer b1 operation mode select bit 0: other than a/d trigger mode 1: a/d trigger mode (5) rw 3. when setting the ivpcr1 bit to 1 (three-phase output forcible cutoff by sd pin input enabled), set the pd8 5 bit to 0 (= input mode). 4. related pins are u(p8 0 ), u(p8 1 ), v(p7 2 ), v(p7 3 ), w(p7 4 ), w(p7 5 ). after forcible cutoff, input "h" to the p8 5 /nmi/sd pin. set the ivpcr1 bit to 0, and this forcible cutoff will be reset. if ? l ? is input to the p8 5 /nmi/sd pin, a three-phase motor control timer output will be disabled (inv03=0). at this time, when the ivpcr1 bit is 0, the target pins change s to programmable i/o port. when the ivpcr1 bit is 1, the target pins changes to high-impedance state regardless of which functions of those pins are used. 5. when using in delay trigger mode, set both bits tb0en and tb1en to 1. 6. when setting the tb2sel bit to 1 (underflow of tb2 interrupt generation frequency setting counter[ictb2]), set the inv02 bit to 1 (three-phase motor control timer function). 7. refer to 1 8.6 digital debounce function for sd input. (b6-b5) reserved bit set to 0 0 0
15. a/d converter page 216 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 15.1 operating modes 15.1.1 one-shot mode in one-shot mode, analog voltage applied to a selected pin is once converted to a digital code. table 15.3 shows the one-shot mode specifications. figure 15.6 shows the operation example in one-shot mode. figure 15.7 shows registers adcon0 to adcon2 in one-shot mode. table 15.3 one-shot mode specifications item specification function bits ch2 to ch0 in the adcon0 register and registers adgsel1 and adgsel0 in the adcon2 register select pins. analog voltage applied to a selected pin is once converted to a digital code a/d conversion start ? when the trg bit in the adcon0 register is 0 (software trigger) condition set the adst bit in the adcon0 register to 1 (a/d conversion started) ? when the trg bit in the adcon0 register is 1 (hardware trigger) the ad trg pin input changes state from ? h ? to ? l ? after setting the adst bit to 1 (a/d conversion started) a/d conversion stop ? a/d conversion completed (if a software trigger is selected, the adst bit is condition set to 0 (a/d conversion halted)). ? set the adst bit to 0 interrupt request generation timing a/d conversion completed analog input pin select one pin from an 0 to an 7 , an0 0 to an0 7 , an2 0 to an2 7 , an3 0 to an3 2 readout of a/d conversion result readout one of registers ad0 to ad7 that corresponds to the selected pin figure 15.6 operation example in one-shot mode a n 0 a n 1 a n 2 a n 3 a n 4 a n 5 a n 6 a n 7 a / d c o n v e r s i o n s t a r t e d a / d i n t e r r u p t r e q u e s t g e n e r a t e d a / d p i n i n p u t v o l t a g e s a m p l i n g a/d pin conversion ? example when selecting an 2 to an analog input pin (ch2 to ch0 = 010 2 )
15. a/d converter page 217 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 15.7 adcon0 to adcon2 registers in one-shot mode a/d control register 0 (1) symbol address after reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit (2, 3) ch0 bit symbol bit name function ch1 ch2 a/d operation mode select bit 0 (3) md0 md1 trigger select bit 0: software trigger 1: hardware trigger (ad trg trigger) trg adst a/d conversion start flag 0: a/d conversion disabled 1: a/d conversion started frequency select bit 0 see table 15.2 cks0 rw rw rw rw rw rw rw rw rw a/d control register 1 (1) symbol address after reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0: 8-bit mode 1: 10-bit mode vcut a/d operation mode select bit 1 0: other than repeat sweep mode 1 1: vref connected frequency select bit 1 cks1 rw rw rw rw rw rw rw invalid in one-shot mode see table 15.2 nothing is assigned. if necessary, set to 0. when read, the content is 0 (b7-b6) notes: 1. if the adcon1 register is rewritten during a/d conversion, the conversion result will be undefined. 2. if the vcut bit is reset from 0 (vref unconnected) to 1 (vref connected), wait for 1 s or more before starting a/d conversion. vref connect bit (2) 0 a/d control register 2 (1) symbol address after reset adcon2 03d4 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d conversion method select bit smp reserved bit set to 0 trg1 a/d input group select bit b2 b1 0 0: select port p10 group 0 1: select port p9 group 1 0: select port p0 group 1 1: select port p1/p9 group set to 0 in one-shot mode frequency select bit 2 cks2 rw rw rw rw rw rw rw 0: without sample and hold 1: with sample and hold see table 15.2 nothing is assigned. if necessary, set to 0. when read, the content is 0 (b7-b6) note: 1. if the adcon2 register is rewritten during a/d conversion, the conversion result will be undefined. trigger select bit adgsel0 adgsel1 (b3) 10 00 b2 b1 b0 0 0 0: select an 0 0 0 1: select an 1 0 1 0: select an 2 0 1 1: select an 3 1 0 0: select an 4 1 0 1: select an 5 1 1 0: select an 6 1 1 1: select an 7 b4 b3 0 0: one-shot mode or delayed trigger mode 0,1 notes: 1. if the adcon0 register is rewritten during a/d conversion, the conversion result will be undefined. 2. an0 0 to an0 7 , an2 0 to an2 7 , and an3 0 to an3 2 can be used in the same way as an 0 to an 7 . use bits adgsel1 and adgsel 0 in the adcon2 register to select the desired pin. 3. after rewriting bits md1 and md0, set bits ch2 to ch0 over again using an another instruction. 00
15. a/d converter page 218 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 15.1.2 repeat mode in repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. table 15.4 shows the repeat mode specifications. figure 15.8 shows the operation example in repeat mode. figure 15.9 shows the adcon0 to adcon2 registers in repeat mode. item specification function bits ch2 to ch0 in the adcon0 register and the adgsel1 to adgsel0 bits in the adcon2 register select pins. analog voltage applied to a selected pin is repeatedly converted to a digital code a/d conversion start ? when the trg bit in the adcon0 register is 0 (software trigger) condition set the adst bit in the adcon0 register to 1 (a/d conversion started) ? when the trg bit in the adcon0 register is 1 (hardware trigger) the ad trg pin input changes state from ? h ? to ? l ? after setting the adst bit to 1 (a/d conversion started) a/d conversion stop condition set the adst bit to 0 (a/d conversion halted) interrupt request generation timing none generated analog input pin select one pin from an 0 to an 7 , an0 0 to an0 7 , an2 0 to an2 7 , and an3 0 to an3 2 readout of a/d conversion result readout one of the ad0 to ad7 registers that corresponds to the selected pin table 15.4 repeat mode specifications figure 15.8 operation example in repeat mode a / d c o n v e r s i o n s t a r t e d a n 0 a n 1 a n 2 a n 3 a n 4 a n 5 a n 6 a n 7 a / d p i n i n p u t v o l t a g e s a m p l i n g a / d p i n c o n v e r s i o n ? example when selecting an 2 to an analog input pin (ch2 to ch0 = 010 2 )
15. a/d converter page 219 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 15.9 adcon0 to adcon2 registers in repeat mode a/d control register 0 (1) symbol address after reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit (2, 3) ch0 bit symbol bit name function ch1 ch2 a/d operation mode select bit 0 (3) md0 md1 trigger select bit 0: software trigger 1: hardware trigger (ad trg trigger) trg adst a/d conversion start flag 0: a/d conversion disabled 1: a/d conversion started frequency select bit 0 see table 15.2 cks0 rw rw rw rw rw rw rw rw rw a/d control register 1 (1) symbol address after reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0: 8-bit mode 1: 10-bit mode vcut a/d operation mode select bit 1 0: other than repeat sweep mode 1 1: vref connected frequency select bit 1 cks1 rw rw rw rw rw rw rw invalid in repeat mode see table 15.2 nothing is assigned. if necessary, set to 0. when read, the content is 0 (b7-b6) notes: 1. if the adcon1 register is rewritten during a/d conversion, the conversion result will be undefined. 2. if the vcut bit is reset from 0 (vref unconnected) to 1 (vref connected), wait for 1 s or more before starting a/d conversion. vref connect bit (2) 0 a/d control register 2 (1) symbol address after reset adcon2 03d4 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d conversion method select bit smp reserved bit set to 0 trg1 a/d input group select bit b2 b1 0 0: select port p10 group 0 1: select port p9 group 1 0: select port p0 group 1 1: select port p1/p9 group set to 0 in one-shot mode frequency select bit 2 cks2 rw rw rw rw rw rw rw 0: without sample and hold 1: with sample and hold see table 15.2 nothing is assigned. if necessary, set to 0. when read, the content is 0 (b7-b6) note: 1. if the adcon2 register is rewritten during a/d conversion, the conversion result will be undefined. trigger select bit adgsel0 adgsel1 (b3) 10 00 b2 b1 b0 0 0 0: select an 0 0 0 1: select an 1 0 1 0: select an 2 0 1 1: select an 3 1 0 0: select an 4 1 0 1: select an 5 1 1 0: select an 6 1 1 1: select an 7 b4 b3 0 1: repeat mode notes: 1. if the adcon0 register is rewritten during a/d conversion, the conversion result will be undefined. 2. an0 0 to an0 7 , an2 0 to an2 7 , and an3 0 to an3 2 can be used in the same way as an 0 to an 7 . use bits adgsel1 and adgsel 0 in the adcon2 register to select the desired pin. 3. after rewriting bits md1 and md0, set bits ch2 to ch0 over again using an another instruction. 01
15. a/d converter page 220 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 15.1.3 single sweep mode in single sweep mode, analog voltages applied to the selected pins are converted one-by-one to a digital code. table 15.5 shows the single sweep mode specifications. figure 15.10 shows the operation example in single sweep mode. figure 15.11 shows the adcon0 to adcon2 registers in single sweep mode. item specification function bits scan1 to scan0 in the adcon1 register and bits adgsel1 and adgsel0 in the adcon2 register select pins. analog voltage applied to the selected pins is converted one-by-one to a digital code a/d conversion start condition ? when the trg bit in the adcon0 register is 0 (software trigger) set the adst bit in the adcon0 register to 1 (a/d conversion started) ? when the trg bit in the adcon0 register is 1 (hardware trigger) the ad trg pin input changes state from ? h ? to ? l ? after setting the adst bit to 1 (a/d conversion started) a/d conversion stop condition ? a/d conversion completed(when selecting a software trigger, the adst bit is set to 0 (a/d conversion halted)). ? set the adst bit to 0 interrupt request generation timing a/d conversion completed analog input pin select from an 0 to an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins), an 0 to an 7 (8 pins) (1) readout of a/d conversion result readout one of registers ad0 to ad7 that corresponds to the selected pin table 15.5 single sweep mode specifications note: 1. an0 0 to an0 7 , an 2 0 to an2 7 , and an3 0 to an3 2 can be used in the same way as an 0 to an 7 . however, all input pins need to belong to the same group. figure 15.10 operation example in single sweep mode a / d c o n v e r s i o n s t a r t e d a / d i n t e r r u p t r e q u e s t g e n e r a t e d a n 0 a n 1 a n 2 a n 3 a n 4 a n 5 a n 6 a n 7 a/d pin input voltage sampling a / d p i n c o n v e r s i o n ? example when selecting an 0 to an 3 to a/d sweep pins (scan1 to scan0 = 01 2 )
15. a/d converter page 221 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 15.11 adcon0 to adcon2 registers in single sweep mode a/d control register 0 (1) symbol address after reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a/d operation mode select bit 0 md0 md1 trigger select bit 0: software trigger 1: hardware trigger (ad trg trigger) trg adst a/d conversion start flag 0: a/d conversion disabled 1: a/d conversion started frequency select bit 0 see table 15.2 cks0 rw note: 1. if the adcon0 register is rewritten during a/d conversion, the conversion result will be undefined. rw rw rw rw rw rw rw rw invalid in single sweep mode b4 b3 1 0: single sweep mode or simultaneous sample sweep mode a/d control register 1 (1) symbol address after reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d sweep pin select bit (2) scan0 scan1 md2 bits 8/10-bit mode select bit 0: 8-bit mode 1: 10-bit mode vcut a/d operation mode select bit 1 0: other than repeat sweep mode 1 1: vref connected frequency select bit 1 cks1 rw rw rw rw rw rw rw see table 15.2 nothing is assigned. if necessary, set to 0. when read, the content is 0 (b7-b6) notes: 1. if the adcon1 register is rewritten during a/d conversion, the conversion result will be undefined. 2. an0 0 to an0 7 , an2 0 to an2 7 , and an3 0 to an3 2 can be used in the same way as an 0 to an 7 . use bits adgsel1 and adgsel 0 in the adcon2 register to select the desired pin. 3. if the vcut bit is reset from 0 (vref unconnected) to 1 (vref connected), wait for 1 s or more before starting a/d conversion. vref connect bit (3) a/d control register 2 (1) symbol address after reset adcon2 03d4 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d conversion method select bit smp reserved bit set to 0 trg1 a/d input group select bit b2 b1 0 0: select port p10 group 0 1: select port p9 group 1 0: select port p0 group 1 1: select port p1/p9 group set to 0 in single sweep mode frequency select bit 2 cks2 rw rw rw rw rw rw rw 0: without sample and hold 1: with sample and hold see table 15.2 nothing is assigned. if necessary, set to 0. when read, the content is 0 (b7-b6) note: 1. if the adcon2 register is rewritten during a/d conversion, the conversion result will be undefined. trigger select bit adgsel0 adgsel1 (b3) 10 10 when single sweep mode is selected, b1 b0 0 0: an 0 to an 1 (2 pins) 0 1: an 0 to an 3 (4 pins) 1 0: an 0 to an 5 (6 pins) 1 1: an 0 to an 7 (8 pins) 0 0
15. a/d converter page 222 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m item specification function bits scan1 and scan0 in the adcon1 register and bits adgsel1 and adgsel0 in the adcon2 register select pins. analog voltage applied to the selected pins is repeatedly converted to a digital code a/d conversion start condition ? when the trg bit in the adcon0 register is 0 (software trigger) set the adst bit in the adcon0 register to 1 (a/d conversion started) ? when the trg bit in the adcon0 register is 1 (hardware trigger) the ad trg pin input changes state from ? h ? to ? l ? after setting the adst bit to 1 (a/d conversion started) a/d conversion stop condition set the adst bit to 0 (a/d conversion halted) interrupt request generation timing none generated analog input pin select from an 0 to an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins), an 0 to an 7 (8 pins) (1) readout of a/d conversion result readout one of registers ad0 to ad7 that corresponds to the selected pin 15.1.4 repeat sweep mode 0 in repeat sweep mode 0, analog voltages applied to the selected pins are repeatedly converted to a digital code. table 15.6 shows the repeat sweep mode 0 specifications. figure 15.12 shows the opera- tion example in repeat sweep mode 0. figure 15.13 shows the adcon0 to adcon2 registers in repeat sweep mode 0. table 15.6 repeat sweep mode 0 specifications notes: 1. an0 0 to an0 7 , an 2 0 to an2 7 , and an3 0 to an3 2 can be used in the same way as an 0 to an 7 . however, all input pins need to belong to the same group. figure 15.12 operation example in repeat sweep mode 0 a / d c o n v e r s i o n s t a r t e d a n 0 a n 1 a n 2 a n 3 a n 4 a n 5 a n 6 a n 7 a / d p i n i n p u t v o l t a g e s a m p l i n g a/d pin conversion ? example when selecting an 0 to an 3 to a/d sweep pins (scan1 to scan0 = 01 2 )
15. a/d converter page 223 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 15.13 adcon0 to adcon2 registers in repeat sweep mode 0 a/d control register 0 (1) symbol address after reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a/d operation mode select bit 0 md0 md1 trigger select bit 0: software trigger 1: hardware trigger (ad trg trigger) trg adst a/d conversion start flag 0: a/d conversion disabled 1: a/d conversion started frequency select bit 0 see table 15.2 cks0 rw note: 1. if the adcon0 register is rewritten during a/d conversion, the conversion result will be undefined. rw rw rw rw rw rw rw rw invalid in repeat sweep mode 0 b4 b3 1 1: repeat sweep mode 0 or repeat sweep mode 1 a/d control register 1 (1) symbol address after reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d sweep pin select bit (2) scan0 scan1 md2 bits 8/10-bit mode select bit 0: 8-bit mode 1: 10-bit mode vcut a/d operation mode select bit 1 0: other than repeat sweep mode 1 1: vref connected frequency select bit 1 cks1 rw rw rw rw rw rw rw see table 15.2 nothing is assigned. if necessary, set to 0. when read, the content is 0 (b7-b6) notes: 1. if the adcon1 register is rewritten during a/d conversion, the conversion result will be undefined. 2. an0 0 to an0 7 , an2 0 to an2 7 , and an3 0 to an3 2 can be used in the same way as an 0 to an 7 . use bits adgsel1 and adgsel 0 in the adcon2 register to select the desired pin. 3. if the vcut bit is reset from 0 (vref unconnected) to 1 (vref connected), wait for 1 s or more before starting a/d conversion. vref connect bit (3) a/d control register 2 (1) symbol address after reset adcon2 03d4 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d conversion method select bit smp reserved bit set to 0 trg1 a/d input group select bit b2 b1 0 0: select port p10 group 0 1: select port p9 group 1 0: select port p0 group 1 1: select port p1/p9 group set to 0 in repeat sweep mode 0 frequency select bit 2 cks2 rw rw rw rw rw rw rw 0: without sample and hold 1: with sample and hold see table 15.2 nothing is assigned. if necessary, set to 0. when read, the content is 0 (b7-b6) note: 1. if the adcon2 register is rewritten during a/d conversion, the conversion result will be undefined. trigger select bit adgsel0 adgsel1 (b3) 11 10 when repeat sweep mode 0 is selected, b1 b0 0 0: an 0 to an 1 (2 pins) 0 1: an 0 to an 3 (4 pins) 1 0: an 0 to an 5 (6 pins) 1 1: an 0 to an 7 (8 pins) 0 0
15. a/d converter page 224 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 15.1.5 repeat sweep mode 1 in repeat sweep mode 1, analog voltage is applied to the all selected pins are converted to a digital code, with mainly used in the selected pins. table 15.7 shows the repeat sweep mode 1 specifications. figure 15.14 shows the operation example in repeat sweep mode 1. figure 15.15 shows registers adcon0 to adcon2 in repeat sweep mode 1. table 15.7 repeat sweep mode 1 specifications item specification function bits scan1 and scan0 in the adcon1 register and bits adgsel1 and adgsel0 in the adcon2 register mainly select pins. analog voltage applied to the all selected pins is repeatedly converted to a digital code example : when selecting an 0 analog voltage is converted to a digital code in the following order an 0 an 1 an 0 an 2 an 0 an 3 , and so on. a/d conversion start condition ? when the trg bit in the adcon0 register is 0 (software trigger) set the adst bit in the adcon0 register to 1 (a/d conversion started) ? when the trg bit in the adcon0 register is 1 (hardware trigger) the ad trg pin input changes state from ? h ? to ? l ? after setting the adst bit to 1 (a/d conversion started) a/d conversion stop condition set the adst bit to 0 (a/d conversion halted) interrupt request generation timing none generated analog input pins mainly select from an 0 (1 pins), an 0 to an 1 (2 pins), an 0 to an 2 (3 pins), an 0 to used in a/d conversions an 3 (4 pins) (1) readout of a/d conversion result readout one of registers ad0 to ad7 that corresponds to the selected pin notes: 1. an0 0 to an0 7 , an 2 0 to an2 7 , and an3 0 to an3 2 can be used in the same way as an 0 to an 7 . however, all input pins need to belong to the same group. figure 15.14 operation example in repeat sweep mode 1 ? example when selecting an 0 to a/d sweep pins (scan1 to scan0 = 00 2 ) an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 a/d conversion started a/d pin input voltage sampling a/d pin conversion
15. a/d converter page 225 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 15.15 adcon0 to adcon2 registers in repeat sweep mode 1 a/d control register 0 (1) symbol address after reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a/d operation mode select bit 0 md0 md1 trigger select bit 0: software trigger 1: hardware trigger (ad trg trigger) trg adst a/d conversion start flag 0: a/d conversion disabled 1: a/d conversion started frequency select bit 0 see table 15.2 cks0 rw note: 1. if the adcon0 register is rewritten during a/d conversion, the conversion result will be undefined. rw rw rw rw rw rw rw rw invalid in repeat sweep mode 1 b4 b3 1 1: repeat sweep mode 0 or repeat sweep mode 1 a/d control register 1 (1) symbol address after reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d sweep pin select bit (2) scan0 scan1 md2 bits 8/10-bit mode select bit 0: 8-bit mode 1: 10-bit mode vcut a/d operation mode select bit 1 1: repeat sweep mode 1 1: vref connected frequency select bit 1 cks1 rw rw rw rw rw rw rw see table 15.2 nothing is assigned. if necessary, set to 0. when read, the content is 0 (b7-b6) notes: 1. if the adcon1 register is rewritten during a/d conversion, the conversion result will be undefined. 2. an0 0 to an0 7 , an2 0 to an2 7 , and an3 0 to an3 2 can be used in the same way as an 0 to an 7 . use bits adgsel1 and adgsel 0 in the adcon2 register to select the desired pin. 3. if the vcut bit is reset from 0 (vref unconnected) to 1 (vref connected), wait for 1 s or more before starting a/d conversion. vref connect bit (3) a/d control register 2 (1) symbol address after reset adcon2 03d4 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d conversion method select bit smp reserved bit set to 0 trg1 a/d input group select bit b2 b1 0 0: select port p10 group 0 1: select port p9 group 1 0: select port p0 group 1 1: select port p1/p9 group set to 0 in repeat sweep mode 1 frequency select bit 2 cks2 rw rw rw rw rw rw rw 0: without sample and hold 1: with sample and hold see table 15.2 nothing is assigned. if necessary, set to 0. when read, the content is 0 (b7-b6) note: 1. if the adcon2 register is rewritten during a/d conversion, the conversion result will be undefined. trigger select bit adgsel0 adgsel1 (b3) 11 10 when repeat sweep mode 0 is selected, b1 b0 0 0: an 0 (1 pin) 0 1: an 0 to an 1 (2 pins) 1 0: an 0 to an 2 (3 pins) 1 1: an 0 to an 3 (4 pins) 0 0
15. a/d converter page 226 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m item specification function bits scan1 and scan0 in the adcon1 register and bits adgsel1 and adgsel0 in the adcon2 register select pins. analog voltage applied to the selected pins is converted one-by-one to a digital code. at this time, the input voltage of an 0 and an 1 are sampled simultaneously. a/d conversion start condition when the trg bit in the adcon0 register is 0 (software trigger) set the adst bit in the adcon0 register to 1 (a/d conversion started) when the trg bit in the adcon0 register is 1 (hardware trigger) the trigger is selected by bits trg1 and hptrg0 (see table 15.9 ) the ad trg pin input changes state from ? h ? to ? l ? after setting the adst bit to 1 (a/d conversion started) timer b0, b2 or timer b2 interrupt generation frequency setting counter underflow after setting the adst bit to 1 (a/d conversion started) a/d conversion stop condition a/d conversion completed (if selecting software trigger, the adst bit is automatically set to 0 ). set the adst bit to 0 (a/d conversion halted) interrupt generation timing a/d conversion completed analog input pin select from an 0 to an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins), or an 0 to an 7 (8 pins) (1) readout of a/d conversion result readout one of registers an0 to an7 that corresponds to the selected pin note: 1. an0 0 to an0 7 , an 2 0 to an2 7 , and an3 0 to an3 2 can be used in the same way as an 0 to an 7 . however, all input pins need to belong to the same group. 15.1.6 simultaneous sample sweep mode in simultaneous sample sweep mode, analog voltages applied to the selected pins are converted one-by- one to a digital code. the input voltages of an0 and an1 are sampled simultaneously using two circuits of sample and hold circuit. table 15.8 shows the simultaneous sample sweep mode specifications. figure 15.16 shows the operation example in simultaneous sample sweep mode. figure 15.17 shows registers adcon0 to adcon2 and figure 15.18 shows adtrgcon registers in simultaneous sample sweep mode. table 15.9 shows the trigger select bit setting in simultaneous sample sweep mode. in simultaneous sample sweep mode, timer b0 underflow can be selected as a trigger by combining soft- ___________ ware trigger, ad trg trigger, timer b2 underflow, timer b2 interrupt generation frequency setting counter underflow or a/d trigger mode of timer b. figure 15.16 operation example in simultaneous sample sweep mode table 15.8 simultaneous sample sweep mode specifications ? example when selecting an 0 to an 3 to a/d pins for sweep (scan1 to scan0 = 01 2 ) a/d conversion started a/d interrupt request generated an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 a/d pin input voltage sampling a/d pin conversion
15. a/d converter page 227 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 15.17 adcon0 to adcon2 registers in simultaneous sample sweep mode a/d control register 0 (1) symbol address after reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a/d operation mode select bit 0 md0 md1 trigger select bit trg adst a/d conversion start flag 0: a/d conversion disabled 1: a/d conversion started frequency select bit 0 see table 15.2 cks0 rw note: 1. if the adcon0 register is rewritten during a/d conversion, the conversion result will be undefined. rw rw rw rw rw rw rw rw invalid in repeat sweep mode 0 b4 b3 1 0: single sweep mode or simultaneous sample sweep mode a/d control register 1 (1) symbol address after reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d sweep pin select bit (2) scan0 scan1 md2 bits 8/10-bit mode select bit 0: 8-bit mode 1: 10-bit mode vcut a/d operation mode select bit 1 0: other than repeat sweep mode 1 frequency select bit 1 cks1 rw rw rw rw rw rw rw see table 15.2 nothing is assigned. if necessary, set to 0. when read, the content is 0 (b7-b6) notes: 1. if the adcon1 register is rewritten during a/d conversion, the conversion result will be undefined. 2. an0 0 to an0 7 , an2 0 to an2 7 , and an3 0 to an3 2 can be used in the same way as an 0 to an 7 . use bits adgsel1 and adgsel 0 in the adcon2 register to select the desired pin. 3. if the vcut bit is reset from 0 (vref unconnected) to 1 (vref connected), wait for 1 s or more before starting a/d conversion. vref connect bit (3) a/d control register 2 (1) symbol address after reset adcon2 03d4 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d conversion method select bit smp reserved bit set to 0 trg1 a/d input group select bit b2 b1 0 0: select port p10 group 0 1: select port p9 group 1 0: select port p0 group 1 1: select port p1/p9 group see table 15.9 frequency select bit 2 cks2 rw rw rw rw rw rw rw set to 1 in simultaneous sample sweep mode see table 15.2 nothing is assigned. if necessary, set to 0. when read, the content is 0 (b7-b6) note: 1. if the adcon2 register is rewritten during a/d conversion, the conversion result will be undefined. trigger select bit adgsel0 adgsel1 (b3) 11 10 1 0 1: vref connected when simultaneous sample sweep mode is selected, b1 b0 0 0: an 0 to an 1 (2 pins) 0 1: an 0 to an 3 (4 pins) 1 0: an 0 to an 5 (6 pins) 1 1: an 0 to an 7 (8 pins) see table 15.9
15. a/d converter page 228 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 15.18 adtrgcon register in simultaneous sample sweep mode table 15.9 trigger select bit setting in simultaneous sample sweep mode trg hptrg0 trg1 trigger 0 1 1 1 - 1 0 0 software trigger timer b0 underflow (1) timer b2 or timer b2 interrupt generation frequency setting counter underflow (2) ad trg - - 1 0 notes: 1. a count can be started for timer b2, timer b2 interrupt generation frequency setting counter underflow or the int5 pin falling edge as count start conditions of timer b0. 2. select timer b2 or timer b2 interrupt generation frequency setting counter using the tb2sel bit in the tb2sc register. a/d trigger control register (1) symbol address after reset adtrgcon 03d2 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d operation mode select bit 2 sse an 0 trigger select bit see table 15.9 hptrg1 an 1 trigger select bit hptrg0 rw rw rw rw rw nothing is assigned. if necessary, set to 0. when read, the content is 0 (b7-b4) note: 1. if adtrgcon is rewritten during a/d conversion, the conversion result will be undefined. dte 1 01 1: simultaneous sample sweep mode or delayed trigger mode 0, 1 a/d operation mode select bit 3 0: other than delayed trigger mode 0, 1 set to 0 in simultaneous sample sweep mode
15. a/d converter page 229 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m notes: 1. set the larger value than the value of the timer b0 register to the timer b1 register. the count source for timer b0 and timer b1 must be the same. 2. do not write 1 (a/d conversion started) to the adst bit in delayed trigger mode 0. when write 1, unexpected interrupts may be generated. 3. an0 0 to an0 7 , an 2 0 to an2 7 , and an3 0 to an3 2 can be used in the same way as an 0 to an 7 . however, all input pins need to belong to the same group. 15.1.7 delayed trigger mode 0 in delayed trigger mode 0, analog voltages applied to the selected pins are converted one-by-one to a digital code. the delayed trigger mode 0 used in combination with a/d trigger mode of timer b. the timer b0 underflow starts a single sweep conversion. after completing the an 0 pin conversion, the an 1 pin is not sampled and converted until the timer b1 underflow is generated. when the timer b1 under- flow is generated, the single sweep conversion is restarted with the an 1 pin. table 15.10 shows the delayed trigger mode 0 specifications. figure 15.19 shows the operation example in delayed trigger mode 0. figures 15.20 and 15.21 show each flag operation in the adstat0 register that corresponds to the operation example. figure 15.22 shows registers adcon0 to adcon2 in delayed trigger mode 0. figure 15.23 shows the adtrgcon register in delayed trigger mode 0 and table 15.11 shows the trigger select bit setting in delayed trigger mode 0. item specification function bits scan1 and scan0 in the adcon1 register and bits adgsel1 and adgsel0 in the adcon2 register select pins. analog voltage applied to the input voltage of the selected pins are converted one-by-one to the digital code. at this time, timer b0 underflow generation starts an 0 pin conversion. timer b1 underflow generation starts conversion after the an 1 pin. (1) a/d conversion start an 0 pin conversion start condition ? when timer b0 underflow is generated if timer b0 underflow is generated again before timer b1 underflow is generated , the conversion is not affected ? when timer b0 underflow is generated during a/d conversion of pins after the an 1 pin, conversion is halted and the sweep is restarted from the an 0 pin again an 1 pin conversion start condition ? when timer b1 underflow is generated during a/d conversion of the an 0 pin, the input voltage of the an 1 pin is sampled. the an 1 conversion and the rest of the sweep start when an 0 conversion is completed. a/d conversion stop ? when single sweep conversion from the an 0 pin is completed condition ? set the adst bit to 0 (a/d conversion halted) (2) interrupt request a/d conversion completed generation timing analog input pin select from an 0 to an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins) and an 0 to an 7 (8 pins) (3) readout of a/d conversion readout one of registers an0 to an7 that corresponds to the selected pins result table 15.10 delayed trigger mode 0 specifications
15. a/d converter page 230 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 15.19 operation example in delayed trigger mode 0 an 0 an 1 an 2 an 3 timer b0 underflow a/d pin input voltage sampling a/d pin conversion an 0 an 1 an 2 an 3 timrt b0 underflow (an interrupt does not affect a/d conversion) timer b0 underflow timer b1 underflow timer b1 underflow ? example when selecting an 0 to an 3 to a/d sweep pins (scan1 to scan0 = 01 2 ) example 1: when timer b1 underflow is generated during an 0 pin conversion an 0 an 1 an 2 an 3 timer b0 underflow timer b1 underflow example 2: when timer b1 underflow is generated after an 0 pin conversion an 0 an 1 an 2 an 3 timer b0 underflow (abort othrt pins conversion) timer b0 underflow timer b1 under flow timer b1 underflow example 3: when timer b0 underflow is generated during a/d conversion of any pins except an 0 pin example 4: when timer b0 underflow is generated again before timer b1 underflow is generated after timer b0 underflow generation
15. a/d converter page 231 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 15.20 each flag operation in adstat0 register associated with the operation example in delayed trigger mode 0 (1) a n 0 a n 1 a n 2 a n 3 t i m e r b 0 u n d e r f l o w 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 a n 0 a n 1 a n 2 a n 3 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 a / d p i n i n p u t v o l t a g e s a m p l i n g a/d pin conversion d o n o t s e t t o 1 b y p r o g r a m d o not set to 1 b y program s et to 0 b y an i nterrupt request ac k now e d gement or a program s e t t o 0 b y a n i n t e r r u p t r e q u e s t a c k n o w e d g e m e n t o r a p r o g r a m s et to 0 b y program s e t t o 0 b y p r o g r a m adst flag: bit 6 in the adcon0 register aderr0, aderr1, adtcsf, adstt0, adstt1, adstrt0 and adstrt1 flag: bits 0, 1, 3, 4, 5, 6, and 7 in the adstat0 register a d s t f l a g a d e r r 0 f l a g a d e r r 1 f l a g a d t c s f f l a g a d s t t 0 f l a g a d s t t 1 f l a g a d s t r t 0 f l a g a d s t r t 1 f l a g i r b i t i n t h e a d i c r e g i s t e r adst flag aderr0 flag aderr1 flag adtcsf flag adstt0 flag adstt1 flag adstrt0 flag adstrt1 flag ir bit in the adic register timer b0 underflow t i m e r b 1 u n d e r f l o w timer b1 underflow example 1: when timer b1 underflow is generated during an 0 pin conversion ? example when selecting an 0 to an 3 to a/d sweep pins (scan1 to scan0 = 01 2 ) example 2: when timer b1 underflow is generated after an 0 pin conversion
15. a/d converter page 232 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 15.21 each flag operation in adstat0 register associated with the operation example in delayed trigger mode 0 (2) an 0 an 1 an 2 an 3 timer b0 underflow (abort othrt pins conversion ) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 an 0 an 1 an 2 an 3 timrt b0 underflow (an interrupt does not affect a/d conversion) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 a/d pin input voltage sampling a/d pin conversion a/d pin input voltage sampling a/d pin conversion do not set to 1 by program do not set to 1 by program set to 0 by interrupt request acknowledgement or a program set to 0 by interrupt request acknowledgement or a program set to 0 by program set to 0 by program adst flag: bit 6 in the adcon0 register aderr0, aderr1, adtcsf, adstt0, adstt1, adstrt0 a n d adstrt1 fl ag:bits0,1,3,4,5,6a n d7i n t h e adstat0 register adst flag: bit 6 in the adcon0 register aderr0, aderr1, adtcsf, adstt0, adstt1, adstrt0 and adstrt1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the adstat0 register adst flag aderr0 flag aderr1 flag adtcsf flag adstt0 flag adstt1 flag adstrt0 flag adstrt1 flag ir bit in the adic register adst flag aderr0 flag aderr1 flag adtcsf flag adstt0 flag adstt1 flag adstrt0 flag adstrt1 flag ir bit in the adic register timer b0 underflow timer b0 underflow timer b1 underflow timer b1 underflow timer b1 underflow example 3: when timer b0 underflow is generated during a/d pin conversion of any pins except an 0 pin example 4: after timer b0 underflow is generated and when timer b0 underflow is generated again before timer b1 underflow is genetaed
15. a/d converter page 233 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 15.22 adcon0 to adcon2 registers in delayed trigger mode 0 a/d control register 0 (1) symbol address after reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a/d operation mode select bit 0 md0 md1 trigger select bit trg adst a/d conversion start flag (2) 0: a/d conversion disabled 1: a/d conversion started frequency select bit 0 see table 15.2 cks0 rw note: 1. if the adcon0 register is rewritten during a/d conversion, the conversion result will be undefined. 2. do not write 1 in delayed trigger mode 0. when write, set to 0. rw rw rw rw rw rw rw rw b2 b1 b0 1 1 1: set to 111b in delayed trigger mode 0 b4 b3 0 0: one-shot mode or delayed trigger mode 0, 1 a/d control register 1 (1) symbol address after reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d sweep pin select bit (2) scan0 scan1 md2 bits 8/10-bit mode select bit 0: 8-bit mode 1: 10-bit mode vcut a/d operation mode select bit 1 0: other than repeat sweep mode 1 frequency select bit 1 cks1 rw rw rw rw rw rw rw see table 15.2 nothing is assigned. if necessary, set to 0. when read, the content is 0 (b7-b6) notes: 1. if the adcon1 register is rewritten during a/d conversion, the conversion result will be undefined. 2. an0 0 to an0 7 , an2 0 to an2 7 , and an3 0 to an3 2 can be used in the same way as an 0 to an 7 . use bits adgsel1 and adgsel 0 in the adcon2 register to select the desired pin. 3. if the vcut bit is reset from 0 (vref unconnected) to 1 (vref connected), wait for 1 s or more before starting a/d conversion. vref connect bit (3) a/d control register 2 (1) symbol address after reset adcon2 03d4 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d conversion method select bit (2) smp reserved bit set to 0 trg1 a/d input group select bit b2 b1 0 0: select port p10 group 0 1: select port p9 group 1 0: select port p0 group 1 1: select port p1/p9 group see table 15.11 frequency select bit 2 cks2 rw rw rw rw rw rw rw 1: with sample and hold see table 15.2 nothing is assigned. if necessary, set to 0. when read, the content is 0 (b7-b6) note: 1. if the adcon2 register is rewritten during a/d conversion, the conversion result will be undefined. 2. set to 1 in delayed trigger mode 0. trigger select bit adgsel0 adgsel1 (b3) 00 10 1 0 1: vref connected when delayed trigger sweep mode 0 is selected, b1 b0 0 0: an 0 to an 1 (2 pins) 0 1: an 0 to an 3 (4 pins) 1 0: an 0 to an 5 (6 pins) 1 1: an 0 to an 7 (8 pins) see table 15.11 1 1 1 0 0
15. a/d converter page 234 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 15.23 adtrgcon register in delayed trigger mode 0 table 15.11 trigger select bit setting in delayed trigger mode 0 trigger timer b0, b1 underflow trg 0 hptrg0 1 trg1 0 hptrg1 1 a/d trigger control register (1) symbol address after reset adtrgcon 03d2 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d operation mode select bit 2 sse an 0 trigger select bit see table 15.11 hptrg1 an 1 trigger select bit hptrg0 rw rw rw rw rw see table 15.11 nothing is assigned. if necessary, set to 0. when read, the content is 0 (b7-b4) note: 1. if adtrgcon is rewritten during a/d conversion, the conversion result will be undefined. dte 1 11 simultaneous sample sweep mode or delayed trigger mode 0, 1 a/d operation mode select bit 3 delayed trigger mode 0, 1 1
15. a/d converter page 235 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m notes: ___________ 1. do not generate the next ad trg pin falling edge after the an1 pin conversion is started until all selected pins ___________ complete a/d conversion. when an ad trg pin falling edge is generated again during a/d conversion, its trigger ___________ is ignored. the falling edge of ad trg pin, which was input after all selected pins complete a/d conversion, is considered to be the next an0 pin conversion start condition. ___________ ___________ 2. the ad trg pin falling edge is detected synchronized with the operation clock fad. therefore, when the ad trg pin ___________ falling edge is generated in shorter periods than fad, the second ad trg pin falling edge may not be detected. do ___________ not generate the ad trg pin falling edge in shorter periods than fad. 3. do not write 1 (a/d conversion started) to the adst bit in delayed trigger mode 1. when write 1,unexpected interrupts may be generated. 4. an0 0 to an0 7 , an 2 0 to an2 7 , and an3 0 to an3 2 can be used in the same way as an 0 to an 7 . however, all input pins need to belong to the same group. 15.1.8 delayed trigger mode 1 in delayed trigger mode 1, analog voltages applied to the selected pins are converted one-by-one to a ___________ digital code. when the input of the ad trg pin (falling edge) changes state from ? h ? to ? l ? , a single sweep conversion is started. after completing the an 0 pin conversion, the an 1 pin is not sampled and converted ___________ until the second ad trg pin falling edge is generated. when the second ad trg falling edge is generated, the single sweep conversion of the pins after the an 1 pin is restarted. table 15.12 shows the delayed trigger mode 1 specifications. figure 15.24 shows the operation example of delayed trigger mode 1. figure 15.25 and 15.26 show each flag operation in the adstat0 register that corresponds to the operation example. figure 15.27 shows registers adcon0 to adcon2 in delayed trigger mode 1. figure 15.28 shows the adtrgcon register in delayed trigger mode 1. table 15.13 shows the trigger select bit setting in delayed trigger mode 1. table 15.12 delayed trigger mode 1 specifications item specification function bits scan1 and scan0 in the adcon1 register and bits adgsel1 and adgsel0 in the adcon2 register select pins. analog voltages applied to the selecte d ___________ pins are converted one-by-one to a digital code. at this time, the ad trg pin ___________ falling edge starts an 0 pin conversion and the second ad trg pin falling edge starts conversion of the pins after an 1 pin a/d conversion start an 0 pin conversion start condition condition ___________ the ad trg pin input changes state from ? h ? to ? l ? (falling edge) (1) an 1 pin conversion start condition (2) ___________ the ad trg pin input changes state from ? h ? to ? l ? (falling edge) ___________ ? when the second ad trg pin falling edge is generated during a/d conversion of ___________ the an 0 pin, input voltage of an 1 pin is sampled or after at the time of ad trg falling edge. the conversion of an 1 and the rest of the sweep starts when an 0 conversion is completed. ___________ ? when the ad trg pin falling edge is generated again during single sweep conversion of pins after the an 1 pin, the conversion is not affected a/d conversion stop ? a/d conversion completed condition ? set the adst bit to 0 (a/d conversion halted) (3) interrupt request single sweep conversion completed generation timing analog input pin select from an 0 to an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins) and an 0 to an 7 (8 pins) (4) readout of a/d conversion result readout one of registers an0 to an7 that corresponds to the selected pins
15. a/d converter page 236 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 15.24 operation example in delayed trigger mode1 ? example when selecting an 0 to an 3 to a/d sweep pins (scan1 to scan0 = 01 2 ) a/d pin input voltage sampling a/d pin conversion an 0 an 1 an 2 an 3 ad trg pin input example 1: when ad trg pin falling edge is generated during an 0 pin conversion an 0 an 1 an 2 an 3 example 2: when ad trg pin falling edge is generated again after an 0 pin conversion ad trg pin input example 3: when ad trg pin falling edge is generated more than two times after an 0 pin conversion an 0 an 1 an 2 an 3 (invalid) (valid after single sweep conversion) ad trg pin input
15. a/d converter page 237 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 15.25 each flag operation in adstat0 register associated with the operation example in delayed trigger mode 1 (1) ? example when selecting an 0 to an 3 to a/d sweep pins (scan1 to scan0 = 01 2 ) a/d pin input voltage sampling a/d pin conversion an 0 an 1 an 2 an 3 ad trg pin input example 1: when ad trg pin falling edge is generated during an 0 pin conversion adst flag aderr0 flag aderr1 flag adtcsf flag adstt0 flag adstt1 flag adstrt0 flag adstrt1 flag ir bit in the adic register 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 set to 0 b y interru p t re q uest acknowled g ement or a p ro g ram set to 0 by program do not set to 1 by program an 0 an 1 an 2 an 3 example 2: when ad trg pin falling edge is generated again after an 0 pin conversion adst flag aderr0 flag aderr1 flag adtcsf flag adstt0 flag adstt1 flag adstrt0 flag adstrt1 flag ir bit in the adic register 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 adst flag: bit 6 in the adcon0 register aderr0, aderr1, adtcsf, adstt0, adstt1, adstrt0 and adstrt1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the adstat0 register set to 0 by interrupt request acknowledgment or a program set to 0 by program do not set to 1 by program ad trg pin input
15. a/d converter page 238 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 15.26 each flag operation in adstat0 register associated with the operation example in delayed trigger mode 1 (2) example 3: when ad trg input falling edge is generated more than two times after an 0 pin conversion a n 0 a n 1 a n 2 a n 3 (invalid ) (valid after single sweep conversion) a d s t f l a g a d e r r 0 f l a g a d e r r 1 f l a g a d t c s f f l a g a d s t t 0 f l a g a d s t t 1 f l a g a d s t r t 0 f l a g a d s t r t 1 f l a g i r b i t i n t h e a d i c r e g i s t e r 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 s et to 0 w h en i nterrupt request ac k now e d gement or a program s et to 0 b y program d o n o t s e t t o 1 b y p r o g r a m a / d p i n i n p u t v o l t a g e s a m p l i n g a / d p i n c o n v e r s i o n a d s t f l a g : b i t 6 i n t h e a d c o n 0 r e g i s t e r a d e r r 0 , a d e r r 1 , a d t c s f , a d s t t 0 , a d s t t 1 , a d s t r t 0 a n d a d s t r t 1 f l a g : b i t s 0 , 1 , 3 , 4 , 5 , 6 a n d 7 i n t h e a d s t a t 0 r e g i s t e r ad trg pin inpu t
15. a/d converter page 239 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 15.27 adcon0 to adcon2 registers in delayed trigger mode 1 a/d control register 0 (1) symbol address after reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a/d operation mode select bit 0 md0 md1 trigger select bit trg adst a/d conversion start flag (2) 0: a/d conversion disabled 1: a/d conversion started frequency select bit 0 see table 15.2 cks0 rw note: 1. if the adcon0 register is rewritten during a/d conversion, the conversion result will be undefined. 2. do not write 1 in delayed trigger mode 0. when write, set to 0. rw rw rw rw rw rw rw rw b2 b1 b0 1 1 1: set to 111b in delayed trigger mode 0 b4 b3 0 0: one-shot mode or delayed trigger mode 0, 1 a/d control register 1 (1) symbol address after reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d sweep pin select bit (2) scan0 scan1 md2 bits 8/10-bit mode select bit 0: 8-bit mode 1: 10-bit mode vcut a/d operation mode select bit 1 0: other than repeat sweep mode 1 frequency select bit 1 cks1 rw rw rw rw rw rw rw see table 15.2 nothing is assigned. if necessary, set to 0. when read, the content is 0 (b7-b6) notes: 1. if the adcon1 register is rewritten during a/d conversion, the conversion result will be undefined. 2. an0 0 to an0 7 , an2 0 to an2 7 , and an3 0 to an3 2 can be used in the same way as an 0 to an 7 . use bits adgsel1 and adgsel 0 in the adcon2 register to select the desired pin. 3. if the vcut bit is reset from 0 (vref unconnected) to 1 (vref connected), wait for 1 s or more before starting a/d conversion. vref connect bit (3) a/d control register 2 (1) symbol address after reset adcon2 03d4 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d conversion method select bit (2) smp reserved bit set to 0 trg1 a/d input group select bit b2 b1 0 0: select port p10 group 0 1: select port p9 group 1 0: select port p0 group 1 1: select port p1/p9 group see table 15.13 frequency select bit 2 cks2 rw rw rw rw rw rw rw 1: with sample and hold see table 15.2 nothing is assigned. if necessary, set to 0. when read, the content is 0 (b7-b6) note: 1. if the adcon2 register is rewritten during a/d conversion, the conversion result will be undefined. 2. set to 1 in delayed trigger mode 1. trigger select bit adgsel0 adgsel1 (b3) 00 10 1 0 1: vref connected when delayed triger mode 1 is selected, b1 b0 0 0: an 0 to an 1 (2 pins) 0 1: an 0 to an 3 (4 pins) 1 0: an 0 to an 5 (6 pins) 1 1: an 0 to an 7 (8 pins) see table 15.13 1 1 1 0 1
15. a/d converter page 240 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 15.28 adtrgcon register in delayed trigger mode 1 table 15.13 trigger select bit setting in delayed trigger mode 1 trigger trg 0 hptrg0 0 trg1 1 ad trg hptrg1 0 a/d trigger control register (1) symbol address after reset adtrgcon 03d2 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d operation mode select bit 2 sse an 0 trigger select bit see table 15.13 hptrg1 an 1 trigger select bit hptrg0 rw rw rw rw rw see table 15.13 nothing is assigned. if necessary, set to 0. when read, the content is 0 (b7-b4) note: 1. if adtrgcon is rewritten during a/d conversion, the conversion result will be undefined. dte 1 01 simultaneous sample sweep mode or delayed trigger mode 0, 1 a/d operation mode select bit 3 delayed trigger mode 0, 1 0
15. a/d converter page 241 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 15.2 resolution select function the bits bit in the adcon1 register determines the resolution. when the bits bit is set to 1 (10-bit precision), the a/d conversion result is stored into bits 0 to 9 in the adi register (i=0 to 7). when the bits bit is set to 0 (8-bit precision), the a/d conversion result is stored into bits 7 to 0 in the adi register. 15.3 sample and hold when the smp bit in the adcon 2 register is set to 1 (with the sample and hold function), a/d conversion rate per pin increases to 28 ad cycles for 8-bit resolution or 33 ad cycles for 10-bit resolution. the sample and hold function is available in one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0 and repeat sweep mode 1. in these modes, start a/d conversion after selecting whether the sample and hold circuit is to be used or not. in simultaneous sample sweep mode, delayed trigger mode 0 or delayed trigger mode, set to use the sample and hold function before starting a/d conversion. 15.4 power consumption reducing function when the a/d converter is not used, the vcut bit in the adcon1 register isolates the resistor ladder of the a/d converter from the reference voltage input pin (v ref ). power consumption is reduced by shutting off any current flow into the resistor ladder from the v ref pin. when using the a/d converter, set the vcut bit to 1 (vref connected) before setting the adst bit in the adcon0 register to 1 (a/d conversion started). do not set the adst bit and vcut bit to 1 simulta- neously, nor set the vcut bit to 0 (vref unconnected) during a/d conversion.
15. a/d converter page 242 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 15.29 analog input pin and external sensor equivalent circuit 15.5 output impedance of sensor under a/d conversion to carry out a/d conversion properly, charging the internal capacitor c shown in figure 15.29 has to be completed within a specified period of time. t (sampling time) as the specified time. let output imped- ance of sensor equivalent circuit be r0, mcu?s internal resistance be r, precision (error) of the a/d converter be x, and the a/d converter?s resolution be y (y is 1024 in the 10-bit mode, and 256 in the 8- bit mode). vc is generally vc = vin{1-e c(r0+r) } and when t = t, vc=vin- vin=vin(1- ) e c(r0+r) = - t = ln hence, r0 = - - r figure 15.29 shows analog input pin and externalsensor equivalent circuit. when the difference be- tween vin and vc becomes 0.1 lsb, we find impedance r0 when voltage between pins. vc changes from 0 to vin-(0.1/1024) vin in timer t. (0.1/1024) means that a/d precision drop due to insufficient capacitor chage is held to 0.1lsb at time of a/d conversion in the 10-bit mode. actual error however is the value of absolute precision added to 0.1lsb. when f(xin) = 10mhz, t=0.3 s in the a/d conversion mode with sample & hold. output inpedance r0 for sufficiently charging capacitor c within time t is determined as follows. t = 0.3 s, r = 7.8k ? , c = 1.5pf, x = 0.1, and y = 1024. hence, r0 = - - 7.8 x 10 3 ? 13.9 x 10 3 thus, the allowable output impedance of the sensor circuit capable of thoroughly driving the a/d con- verter turns out of be approximately 13.9k ? . 1 1 t t c(r0+r) 1 x y x y x y x y t c?ln x y 1.5x10 -12 ?ln 0.1 1024 0.3x10 -6 r 0 r (7.8 k ? ) c (1.5 pf) v in v c sampling time sample-and-hold function enabled: sample-and-hold function disabled: 3 ad mcu sensor equivalent circuit 2 ad (1) (1) note: 1. reference value
16. multi-master i 2 c bus interface page 243 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m item function format based on philips i 2 c bus standard: 7-bit addressing format high-speed clock mode standard clock mode communication mode based on philips i 2 c bus standard: master transmit master receive slave transmit slave receive scl clock frequency 16.1khz to 400khz (at v iic (1) = 4mhz) i/o pin serial data line sda mm (sda) serial clock line sdl mm (scl) 16. multi-master i 2 c bus interface the multi-master i 2 c bus interface is a serial communication circuit based on philips i 2 c bus data transfer format, equipped with arbitration lost detection and synchronous functions. figure 16.1 shows a block diagram of the multi-master i 2 c bus interface and table 16.1 lists the multi-master i 2 c bus interface func- tions. the multi-master i 2 c bus interface consists of the s0d0 register, the s00 register, the s20 register, the s3d0 register, the s4d0 register, the s10 register, the s2d0 register and other control circuits. figures 16.2 to 16.8 show the registers associated with the multi-master i 2 c bus. table 16.1 multi-master i 2 c bus interface functions note: 1. v iic =i 2 c system clock
16. multi-master i 2 c bus interface page 244 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 16.1 block diagram of multi-master i 2 c bus interface serial data (sda) bb circuit noise elimination circuit (scl) b7 b0 ack clk ack bit fast mode ccr4 ccr3 ccr2 ccr1 ccr0 internal data bus clock division s20 b7 b0 sad6 sad5 sad4 sad3 sad2 sad1 sad0 address comparator b7 b0 s00 s0d0 (s cl s da irq) b7 b0 ick1 ick0 sclm sdam wit sim s3d0 interrupt generation circui t b7 mst trx b b pin al aas ad0 lrb b0 s10 b7 b0 tiss als bc2 bc1 es0 i 2 c system clock (viic) time-out detection circuit tof to e ick4 ick3 ick2 tosel system clock select circut i 2 c0 control register 1 i 2 c0 start/stop condition control register s2d0 stsp sel sis sip ssc4 ssc3 ssc2 ssc1 ssc0 i 2 c0 address registers i 2 c0 data shift registers i 2 c0 control registers 2 s4d0 i 2 c0 clock control registers i 2 c0 status registers i 2 c0 control registers 0 s1d0 i 2 c bus interface interrupt request signal bit counter (i 2 c irq) serial clock bc0 clock control circuit al circuit noise elimination circuit data control circuit interrupt request signal interrupt generation circuit f 1 f 2 pclk0=1 f iic pclk0=0
16. multi-master i 2 c bus interface page 245 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 16.2 s0d0 register sad6 sad5 sad4 sad3 sad2 sad1 sad0 reserved bit function bit name bit symbol address after reset symbol c 0 a d d r e s s r e g i s t e r s0d0 02e2 16 00 16 b 7 b6 b5 b 4 b3 b 2b1b0 i 2 slave address set to 0 compare with received address data rw rw rw rw rw rw rw rw rw (b0) 0
16. multi-master i 2 c bus interface page 246 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 16.3 s00 and s20 registers 0: standard clock mode 1: high-speed clock mode 0: ack is returned 1: ack is not returned 0: no ack clock 1: with ack clock ack clock bit ack bit s cl mode specification bit s cl frequency control bits ccr0 ccr1 ccr2 ccr3 ccr4 fast mode ackbit ack-clk function bit name bit symbol 00 16 after reset 02e4 16 address symbol s20 b 7 b6 b5 b 4 b3 b2 b1 b0 c 0 c lock c ontrol re g ister i 2 rw see table 16.3 rw rw rw rw rw rw rw rw symbol address after reset s00 02e0 16 xx 16 b 7b 6b 5b 4b 3b 2b 1b 0 i c 0 d a t a s h i f t r e g i s t e r 2 rw function rw ( 1 ) note: 1. write is enabled only when the es0 bit in the s1d0 register is 1 (i 2 c bus interface is enabled). write the transmit data after the receive data is read because the s00 register is used to store both the transmit and receive data. when the s00 register is set, bits bc2 to bc0 in the s1d0 register are set to 000 2 , while bits lrb, aas, and al in the s10 register are set to 0 respectively. transmit/receive data are stored. in master transmit mode, the start condition/stop condition are triggered by writing data to the register (refer to 16.9 start condition generation method and 16.11 stop condition generation method ). start transmitting/receiving data while synchronizing with s cl
16. multi-master i 2 c bus interface page 247 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 16.4 s1d0 register 0: disabled 1: enabled 0: addressing format 1: free data format set to 0 0: reset release (automatic) 1: reset note: 1.in the following status, the bit counter is set to 000 automatically ? start condition/stop condition are detected ? immediately after the completion of 1-byte data transmit ? immediately after the completion of 1-byte data receive i 2 c bus interface pin input level select bit i 2 c bus interface reset bit reserved bit data format select bit i c bus interface enable bit 2 bit counter (number of transmit/receive bits) bc2 tiss ihr (b5) als es0 bc1 bc0 function bit name bit symbol 00 16 after reset 02e3 16 address symbol s1d0 c 0 c ontrol re g ister 0 i 2 b 7 b6 b5 b 4 b3 b 2 b 1b0 (1) rw 0: i 2 c bus input 1: smbus input rw rw rw rw rw rw rw rw b2 b1 b0 0 0 0: 8 0 0 1: 7 0 1 0: 6 0 1 1: 5 1 0 0: 4 1 0 1: 3 1 1 0: 2 1 1 1: 1
16. multi-master i 2 c bus interface page 248 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 16.5 s10 register notes: 1. this bit is read only if it is used for the status check. to write to this bit, refer to 16.9 start condition generation method and 16.11 stop condition generation method . 2. read only. when write, set to 0. 3. to write to these bits, refer to 16.9 start condition generation method and 16.11 stop condition generation method. 0: bus free 1: bus busy 0: interrupt request issued 1: no interrupt request issued 0: not detected 1: detected 0: no address matched 1: address matched 0: no general call detected 1: general call detected 0: last bit = 0 1: last bit = 1 communication mode select bits 0 bus busy flag i c bus interface interrupt request bit 2 arbitration lost detection flag slave address comparison flag general call detecting flag last receive bit mst trx bb pin al aas adr0 lrb function bit name bit symbol 0001000x 2 after reset 02e8 16 address symbol s10 c 0 s t a t u s r e g i s t e r i 2 rw 0: receive mode 1: transmit mode b 7 b6 b5 b 4 b3 b 2b1b0 ro (1) ro (1) ro (1) ro (2) ro (1) ro (2) rw (3) rw (3) 0: slave mode 1: master mode communication mode select bit 1
16. multi-master i 2 c bus interface page 249 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 16.6 s3d0 register 0: s cl output logic value = 0 1: s cl output logic value = 1 0: s da output logic value = 0 1: s da output logic value = 1 0: s cl i/o pin 1: port output pin 0: s da i/o pin 1: port output pin 0: disable the i 2 c bus interface interrupt of data receive completion 1: enable the i 2 c bus interface interrupt of data receive completion when setting nack (ack bit = 0), write 0 0: disable the i 2 c bus interface interrupt of stop condition detection 1: enable the i 2 c bus interface interrupt of stop condition detection i c bus system clock selection bits, if bits ick4 to ick2 in the s4d0 register is 000 2 2 the logic value monitor bit of s cl output the logic value monitor bit of s da output s cl /port function switch bit (1) s da /port function switch bit (1) the interrupt enable bit for data receive completion the interrupt enable bit for stop condition detection ick1 ick0 sclm sdam pec ped wit sim function bit name bit symbol 00110000 2 after reset 02e6 16 address symbol s3d0 c 0 c ontrol re g ister 1 i 2 b 7 b6 b5 b 4 b3 b 2b1b0 rw b7 b6 0 0 : 0 1 : 1 0 : v iic =1/2 f iic =1/4f iic =1/8 f iic 1 1 : reserved v iic v iic rw rw rw rw ro ro rw rw note: 1. bits ped and pec are enabled when the es0 bit in the s1d0 register is set to 1 (i 2 c bus interface enabled). 2. when the pclk0 bit in the pclkr register is set to 0, f iic =f 2 . when the pclk0 bit in the pclkr register is set to 1, f iic =f 1 . (2)
16. multi-master i 2 c bus interface page 250 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 16.7 s4d0 register scpin reserved bit ick4 ick3 ick2 tosel tof toe function bit name bit symbol 00 16 after reset 02e7 16 address symbol s4d0 c 0 c ontrol re g ister 2 i 2 rw b 7 b6 b5 b 4 b3 b 2b1b0 0: long time 1: short time stop condition detection interrupt request bit set to 0 b5 b4 b3 0 0 0 v iic set by ick1 and ick0 bits in s3d0 register 0 0 1 v iic = 1/2.5 f iic 0 1 0 v iic = 1/3 f iic 0 1 1 v iic = 1/5 f iic 1 0 0 v iic = 1/6 f iic time out detection time select bit time out detection flag time out detection function enable bit i 2 c bus system clock select bits 0: no i 2 c bus interface interrupt request 1: i 2 c bus interface interrupt request 0: not detected 1: detected 0: disabled 1: enabled rw ro rw rw rw rw rw rw (b6) (1) note: 1. when the pclk0 bit in the pclkr register is set to 0, f iic = f 2 . when the pclk0 bit is set to 1, f iic =f 1 .
16. multi-master i 2 c bus interface page 251 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 16.8 s2d0 register notes: 1. do not set odd values or 00000 2 to start/stop condition setting bits (ssc4 to ssc0) 2. when the pclk0 bit in the pclkr register is set to 1. oscillation i 2 c bus system i 2 c bus system ssc4-ssc0 (1) scl release setup time hold time f1 (mhz) clock select clock(mhz) time (cycle) (cycle) (cycle) 10 1 / 2 f1 (2) 5 xxx11110 6.2 s (31) 3.2 s (16) 3.0 s (15) 8 1 / 2 f1 (2) 4 xxx11010 6.75 s(27) 3.5 s (14) 3.25 s(13) xxx11000 6.25 s(25) 3.25 s (13) 3.0 s (12) 8 1 / 8 f1 (2) 1 xxx00100 5.0 s (5) 3.0 s (3) 2.0 s (2) 4 1 / 2 f1 (2) 2 xxx01100 6.5 s (13) 3.5 s (7) 3.0 s (6) xxx01010 5.5 s (11) 3.0 s (6) 2.5 s (5) 2 1 / 2 f1 (2) 1 xxx00100 5.0 s (5) 3.0 s (3) 2.0 s (2) table 16.2 recommended setting (ssc4-ssc0) start/stop condition at each oscillation frequency 0: short setup/hold time mode 1: long setup/hold time mode 0: s da enabled 1: s cl enabled 0: active in falling edge 1: active in rising edge start/stop condition generation select bit s cl /s da interrupt pin select bit s cl /s da i nterrupt pin polarity select bit start/stop condition setting bits (1) stspsel sis sip ssc4 ssc3 ssc2 ssc1 ssc0 function bit name bit symbol 00011010 2 after reset 02e5 16 address symbol s2d0 c 0 s tart/stop c ondition c ontrol re g ister i 2 rw b 7 b6 b5 b 4 b3 b 2b1b0 note: 1. do not set 00000 2 or odd values. rw rw rw rw rw rw rw rw setting for detection condition of start/stop condition. see table 16.2
16. multi-master i 2 c bus interface page 252 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 16.2 i 2 c0 address register (s0d0 register) the s0d0 register consists of bits sad6 to sad0, total of 7. at the addressing is formatted, slave address is detected automatically and the 7-bit received address data is compared with the contents of bits sad6 to sad0. 16.1 i 2 c0 data shift register (s00 register) the s00 register is an 8-bit data shift register to store a received data and to write a transmit data. when a transmit data is written to the s00 register, the transmit data is synchronized with a scl clock and the data is transferred from bit 7. then, every one bit of the data is transmitted, the register's content is shifted for one bit to the left. when the scl clock and the data is imported into the s00 register from bit 0. every one bit of the data is imported, the register's content is shifted for one bit to the left. figure 16.9 shows the timing to store the receive data to the s00 register. the s00 register can be written when the es0 bit in the s1d0 register is set to 1 (i 2 c0 bus interface enabled). if the s00 register is written when the es0 bit is set to 1 and the mst bit in the s10 register is set to 1 (master mode), the bit counter is reset and the scl clock is output. write to the s00 register when the start condition is generatedor when an "l" signal is applied to the scl pin. the s00 register can be read anytime regardless of the es0 bit value. figure 16.9 the receive data storing timing of s00 register internal s cl tdfil store data at the rising edge of shift clock internal s da shift clock s cl s da tdfil tdsft tdfil: noise elimination circuit delay time 1 to 2 v iic cycle tdsft: shift clock delay time 1 v iic cycle
16. multi-master i 2 c bus interface page 253 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 16.3 i 2 c0 clock control register (s20 register) the s20 register is used to set theack control, scl mode and the scl frequency. 16.3.1 bits 0 to 4: scl frequency control bits (ccr0 ccr4) these bits control the scl frequency. see table 16.3 . 16.3.2 bit 5: scl mode specification bit (fast mode) the fast mode bit selects scl mode. when the fast mode bit is set to 0, standard clock mode is entered. when it is set to 1, high-speed clock mode is entered. when using the high-speed clock mode i 2 c bus standard (400 kbits/s maximum) to connect buses, set the fast mode bit to 1 (select scl mode as high-speed clock mode) and use the i 2 c bus system clock (v iic ) at 4 mhz or more frequency. 16.3.3 bit 6: ack bit (ackbit) the ackbit bit sets the sda status when an ack clock (1) is generated. when the ackbit bit is set to ? 0 ? , ack is returned and te clock applied to sda becomes "l" when ack clock is generated. when it is set to 1, ack is not returned and the clock clock applied to sda maintains "h" at ack clock generation. when the ackbit bit is set to 0, the address data is received. when the slave address matches with the address data, sda becomes "l" automatically (ack is returned). when the slave address and the address data are not matched, sda becomes "h" (ack is not returned). note: 1. ack clock: clock for acknowledgment 16.3.4 bit 7: ack clock bit (ack-clk) the ack-clk bit set a clock for data transfer acknowledgement. when the ack-clk bit is set to 0, ack clock is not generated after data is transferred. when it is set to 1, a master generates ack clock every one-bit data transfer is completed. the device, which transmits address data and control data, leave sda pin open (apply "h" signal to sda) when ack clock is generated. the device which receives data, receives the generated ackbit bit. note: 1.do not rewrite the s20 register, other than the ackbit bit during data transfer. if data is written to other than the ackbit bit during transfer, the i 2 c bus clock circuit is reset and the data may not be transferred successfully.
16. multi-master i 2 c bus interface page 254 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m setting value of ccr4 to ccr0 scl frequency (at v iic =4mhz, unit : khz) (1) ccr4 ccr3 ccr2 ccr1 ccr0 standard clock mode high-speed clock mode 0 0 0 0 0 setting disabled setting disabled 0 0 0 0 1 setting disabled setting disabled 0 0 0 1 0 setting disabled setting disabled 0 0 0 1 1 - (2) 333 0 0 1 0 0 - (2) 250 0 0 1 0 1 100 400 (3) 0 0 1 1 0 83.3 166 500 / ccr value (3) 1000 / ccr value (3) 1 1 1 0 1 17.2 34.5 1 1 1 1 0 16.6 33.3 1 1 1 1 1 16.1 32.3 notes: 1. the duty of the scl clock output is 50 %. the duty becomes 35 to 45 % only when high-speed clock mode is selected and the ccr value = 5 (400 khz, at viic = 4 mhz). ? h ? duration of the clock fluctuates from ? 4 to +2 i 2 c system clock cycles in standard clock mode, and fluctuates from ? 2 to +2 i 2 c system clock cycles in high-speed clock mode. in the case of negative fluctuation, the frequency does not increase because the ? l ? is extended instead of ? h ? reduction. these are the values when the scl clock synchronization by the synchronous function is not performed. the ccr value is the decimal notation value of the ccr4 to ccr0 bits. 2. each value of the scl frequency exceeds the limit at v iic = 4 mhz or more. when using these setting values, use v iic = 4 mhz or less. refer to figure 16.6 . 3. the data formula of scl frequency is described below: v iic /(8 x ccr value) standard clock mode v iic /(4 x ccr value) high-speed clock mode (ccr value 5) v iic /(2 x ccr value) high-speed clock mode (ccr value = 5) do not set 0 to 2 as the ccr value regardless of the viic frequency. set 100 khz (max.) in standard clock mode and 400 khz (max.) in high-speed clock mode to the scl frequency by setting the ccr4 to ccr0 bits. table 16.3 setting values of s20 register and scl frequency
16. multi-master i 2 c bus interface page 255 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 16.4 i 2 c0 control register 0 (s1d0) the s1d0 register controls data communication format. 16.4.1 bits 0 to 2: bit counter (bc0 bc2) bits bc2 to bc0 decide how many bits are in one byte data transferred next. after the selected num- bers of bits are transferred successfully, i 2 c bus interface interrupt request is gnerated and bits bc2 to bc0 are reset to 000 2 . at this time, if the ack-clk bit in the s20 register is set to 1 (with ack clock), one bit for ack clock is added to the numbers of bits selected by the bc2 to bc0 bits. in addition, bits bc2 to bc0 become 000 2 even though the start condition is detected and the address data is transferred in 8 bits. 16.4.2 bit 3: i 2 c interface enable bit (es0) the es0 bit enables to use the multi-master i 2 c bus interface. when the es0 bit is set to 0, i 2 c bus interface is disabled and the sda and scl pins are placed in a high-h-impedance state. when the es0 bit is set to 1, the interface is enabled. when the es0 bit is set to 0, the process is followed. 1)the bits in the s10 register are set as mst = 0, trx = 0, pin = 1, bb = 0, al = 0, aas = 0, adr0 = 0 2)the s00 register cannot be written. 3)the tof bit in the s4d0 register is set to 0 (time-out detection flag is not detected) 4)the i 2 c system clock (v iic ) stops counting while the internal counter and flags are reset. 16.4.3 bit 4: data format select bit (als) the als bit determines whether the salve address is recognized. when the als bit is set to 0, an addressing format is selected and a address data is recognized. only if the comparison is matched between the slave address stored into the s0d0 register and the received address data or if the general call is received, the data is transferred. when the als bit is set to 1, the free data format is selected and the slave address is not recognized. 16.4.4 bit 6: i 2 c bus interface reset bit (ihr) the ihr bit is used to reset the i 2 c bus interface circuit when the error communication occurs. when the es0 bit in the s1d0 register is set to 1 (i 2 c bus interface is enabled), the hardware is reset by writing 1 to the ihr bit. flags are processed as follows: 1)the bits in the s10 register are set as mst = 0, trx = 0, pin to 1, bb = 0, al = 0, aas = 0, and adr0 = 0 2)the tof bit in the s4d0 register is set to 0 (time-out detection flag is not detected) 3)the internal counter and flags are reset. the i 2 c bus interface circuit is reset after 2.5 v iic cycles or less, and the ihr bit becomes 0 automati- cally by writing 1 to the ihr bit. figure 16.10 shows the reset timing.
16. multi-master i 2 c bus interface page 256 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 16.10 the timing of reset to the i 2 c bus interface circuit a reset signal to i 2 c bus interface circuit write 1 to ihr bit ihr bit 2.5 v iic cycles 16.4.5 bit 7: i 2 c bus interface pin input level select bit (tiss) the tiss bit selects the input level of the scl and sda pins for the multi-master i 2 c bus interface. when the tiss bit is set to 1, the p2 0 and p2 1 become the smbus input level.
16. multi-master i 2 c bus interface page 257 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 16.5 i 2 c0 status register (s10 register) the s10 register monitors the i 2 c bus interface status. when using the s10 register to check the status, use the 6 low-order bits for read only. 16.5.1 bit 0: last receive bit (lrb) the lrb bit stores the last bit value of received data. it can also be used to confirm whether ack is received. if the ack-clk bit in the s20 register is set to 1 (with ack clock) and ack is returned when the ack clock is generated, the lrb bit is set to 0. if ack is not returned, the lrb bit is set to 1. when the ack-clk bit is set to 0 (no ack clock), the last bit value of received data is input. when writing data to the s00 register, the lrb bit is set to 0. 16.5.2 bit 1: general call detection flag (adr0) when the als bit in the s1d0 register is set to 0 (addressing format), this adr0 flag is set to 1 by receiving the general calls (1) ,whose address data are all 0, in slave mode. the adr0 flag is set to 0 when stop or start conditions is detected or when the ihr bit in the s1d0 register is set to 1 (reset). note: 1. general call: a master device transmits the general call address 00 16 to all slaves. when the master device transmits the general call, all slave devices receive the controlled data after general call. 16.5.3 bit 2: slave address comparison flag (aas) the aas flag indicates a comparison result of the slave address data after enabled by setting the als bit in the s1d0 register to 0 (addressing format). the aas flag is set to 1 when the 7 bits of the address data are matched with the slave address stored into the s0d0 register, or when a general call is received, in slave receive mode. the aas flag is set to 0 by writing data to the s00 register. when the es0 bit in the s1d0 register is set to 0 (i 2 c bus interface disabled) or when the ihr bit in the s1d0 register is set to 1 (reset), the aas flag is also set to 0. 16.5.4 bit 3: arbitration lost detection flag (al) (1) in master transmit mode, if an "l" signal is applied to the sda pin by other than the mcu, the al flag is set to 1 by determining that the arbitration is los and the trx bit in the s10 register is set to 0 (receive mode) at the same time. the mst bit in the s10 register is set to 0 (slave mode) after transferring the bytes which lost the arbitration. the arbitration lost can be detected only in master transmit mode. when writing data to the s00 register, the al flag is set to 0. when the es0 bit in the s1d0 register is set to 0 (i 2 c bus interface disabled) or when the ihr bit in the s1d0 register is set to 1 (reset), the al flag is set to 0. note: 1. arbitration lost: communication disabled as a master
16. multi-master i 2 c bus interface page 258 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 16.5.5 bit 4: i 2 c bus interface interrupt request bit (pin) the pin bit generates an i 2 c bus interface interrupt request signal. every one byte data is ransferred, the pin bit is changed from 1 to 0. at the same time, an i 2 c bus interface interrupt request is generated. the pin bit is synchronized with the last clock of the internal transfer clock (when ack-clk=1, the last clock is the ack clock: when the ack-clk=0, the last clock is the 8th clock) and it becomes 0. the interrupt request is generated on the falling edge of the pin bit. when the pin bit is set to 0, the clock applied to scl maintains "l" and further clock generation is disabled. when the ack-clk bit is set to 1 and the wit bit in the s3d0 register is set to 1 (enable the i 2 c bus interface interrupt of data receive completion). the pin bit is synchronized with the last clock and the falling edge of the ack clock. then, the pin bit is set to 0 and i 2 c bus interface interrupt request is generated. figure 16.11 shows the timing of the i 2 c bus interface interrupt request generation. the pin bit is set to 1 in one of the following conditions: ? when data is written to the s00 register ? when data is written to the s20 register (when the wit bit is set to 1 and the internal wait flag is set to 1) ? when the es0 bit in the s1d0 register is set to 0 (i 2 c bus interface disabled) ? when the ihr bit in the s1d0 register is set to 1(reset) the pin bit is set to 0 in one of the following conditions: ? with completion of 1-byte data transmit (including a case when arbitration lost is detected) ? with completion of 1-byte data receive ? when the als bit in the s1d0 register is set to 0 (addressing format) and slave address is matched or general call address is received successfully in slave receive mode ? when the als bit is set to 1 (free format) and the address data is received successfully in slave receive mode 16.5.6 bit 5: bus busy flag (bb) the bb flag indicates the operating conditions of the bus system. when the bb flag is set to 0, a bus system is not in use and a start condition can be generated. the bb flag is set and reset based on an input signal of the scl and sda pins either in master mode or in slave mode. when the start condition is detected, the bb flag is set to 1. on the other hand, when the stop condition is detected, the bb flag is set to 0. bits ssc4 to ssc0 in the s2d0 register decide to detect between the start condition and the stop condition. when the es0 bit in the s1d0 register is set to 0 (i 2 c bus interface disabled) or when the ihr bit in the s1d0 register is set to 1 (reset), the bb flag is set to 0. refer to 16.9 start condition generation method and 16.11 stop condition generation method . figure 16.11 interrupt request signal generation timing s c l pin flag i 2 c i r q
16. multi-master i 2 c bus interface page 259 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 16.5.7 bit 6: communication mode select bit (transfer direction select bit: trx) this trx bit decides a transfer direction for data communication. when the trx bit is set to 0, receive mode is entered and data is received from a transmit device. when the trx bit is set to 1, transmit mode is entered, and address data and control data are output to the sda mm, synchronized with a clock gener- ated in the scl mm . the trx bit is set to 1 automatically in the following condition: ? in slave mode, when the als in the s1d0 register to 0(addressing format), the aas flag is set to ___ 1 (address match) after the address data is received, and the received r/w bit is set to 1 the trx bit is set to 0 in one of the following conditions: ? when an arbitration lost is detected ? when a stop condition is detected ? when a start condition is detected ? when a start condition is disabled by the start condition duplicate protect function (1) ? when the mst bit in the s10 register is set to 0(slave mode) and a start condition is detected ? when the mst bit is set to 0 and the ack non-return is detected ? when the es0 bit is set to 0(i 2 c bus interface disabled) ? when the ihr bit in the s1d0 register is set to 1(reset) 16.5.8 bit 7: communication mode select bit (master/slave select bit: mst) the mst bit selects either master mode or slave mode for data communication. when the mst bit is set to 0, slave mode is entered and the start/stop condition generated by a master device are received. the data communication is synchronized with the clock generted by the master. when the mst bit is set to 1, master mode is entered and the start/stop condition is generated. additionally, clocks required for the data communication are generated on the scl mm . the mst bit is set to 0 in one of the following conditions. ? after 1-byte data of a master whose arbtration is lost if arbitration lost is detected ? when a stop condition is detected ? when a start condition is detected ? when a start condition is disabled by the start condition duplicate protect function (1) ? when the ihr bit in the s1d0 register is set to 1(reset) ? when the es0 bit is set to 0(i 2 c bus interface disabled) note: 1. start condition duplicate protect function: when the start condition is generated, after confirming that the bb flag in the s1d0 register is set to 0 (bus free), all the mst, trx and bb flags are set to 1 at the same time. however, if the bb flag is set to 1 immediately after the bb flag setting is confirmed because a start condition is generated by other master device, bits mst and trx cannot be written. the duplicate protect function is valid from the rising edge of the bb flag until slave address is received. refer to 16.9 start condition generation method for details.
16. multi-master i 2 c bus interface page 260 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 16.6 i 2 c0 control register 1 (s3d0 register) the s3d0 register controls the i 2 c bus interface circuit. 16.6.1 bit 0 : interrupt enable bit by stop condition (sim ) the sim bit enables the i 2 c bus interface interrupt request by detecting a stop condition. if the sim bit is set to ? 1 ? , the i 2 c bus interface interrupt request is generated by the stop condition detect (no need to change in the pin flag). 16.6.2 bit 1: interrupt enable bit at the completion of data receive (wit) if the wit bit is set to 1 while the ack-clk bit in the s20 register is set to 1 (ack clock), the i 2 c bus interface interrupt request is generated and the pin bit is set to 1 at the falling edge of the last data bit clock. then an "l" signal is applied to the scl mm and the ack clock generation is controlled. table 16.4 and figure 16.12 show the interrupt generation timing and the procedure of communication restart. after the communication is restarted, the pin bit is set to 0 again, synchronized with the falling edge of the ack clock, and the i 2 c bus interface interrupt request is generated. table16.4 timing of interrupt generation in data receive mode the internal wait flag can be read by reading the wit bit. the internal wait flag is set to 1 after writing data to the s00 register and it is set to 0 after writing to the s20 register. consequently, the i 2 c bus interface interrupt request generated by the timing 1) or 2) can be determined. (see figure 16.12 ) when the data is transmitted and the address data is received immediately after the start condition, the wait flag remains 0 regardless of the wit bit setting, and the i 2 c bus interface interrupt request is only generated at the falling edge of the ack clock. set the wit bit to 0 when the ack-clk bit in the s20 register is set to 0 (no ack clock). i 2 c bus interface interrupt generation timing procedure of communication restart 1) synchronized with the falling edge of the set the ack bit in the s20 register. last data bit clock set the pin bit to 1. (do not write to the s00 register. the ack clock operation may be unstable.) 2) synchronized with the falling edge of the set the s00 register ack clock
16. multi-master i 2 c bus interface page 261 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 16.12 the timing of the interrupt generation at the completion of the data receive 16.6.3 bits 2,3 : port function select bits ped, pec if the es0 bit in the s1d0 register is set to 1 (i 2 c bus interface enabled), the sda mm functions as an output port. when the ped bit is set to 1 and the scl mm functions as an output port when the pec bit is set to 1. then the setting values of bits p2_0 and p2_1 in the port p2 register are output to the i 2 c bus, regardless of he internal scl/sda output signals. (scl/sda pins are onnected to i 2 c bus interface circuit) the bus data can be read by reading the port pi direction register in input mode, regardless of the setting values of the ped and pec bits. table 16.5 shows the port specification. table 16.5 port specifications in receive mode, ack bit = 1 wit bit = 0 7 clock 8 clock ack clock 1 clock 1 bit 7 bit 8 bit ack bit s cl s da ackbit bit pin flag internal wait flag i 2 c bus interface interrupt request signal the writing signal of the s00 register 7 clock 8 clock ack clock 1 bit 7 bit 8 bit s cl s da ackbit bit pin flag internal wait flag i 2 c bus interface interrupt request signal the writing signal of the s00 register the writing signal of the s2 0 register 1) note: 1. do not write to the i 2 c0 clock control register except the bit ack-bit. in receive mode, ack bit = 1 wit bit = 1 2) e m a n n i pt i b 9 s et i b d e p 2 p 0 n o i t c e r i d t r o p r e t s i g e r n o i t c n u f 2 p 0 0- 1 / 0n o i t c n u f o / i t r o p 10 -s a d n o i t c n u f o / i 11 -s a d n o i t c n u f t u p t u o t r o p , n o i t c n u f t u p n i e m a n n i pt i b 0 s et i b c e p 2 p 1 n o i t c e r i d t r o p r e t s i g e r n o i t c n u f 2 p 1 0- 1 / 0n o i t c n u f o / i t r o p 10 -s l c n o i t c n u f o / i 11 -s l c n o i c n u f t u p t u o t r o p , n o i t c n u f t u p n i
16. multi-master i 2 c bus interface page 262 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 16.6.6 address receive in stop/wait mode when wait mode is entered after the cm02 bit in the cm0 register is set to 0 (do not stop the peripheral function clock in wait mode), the i 2 c bus interface circuit can receive address data in wait mode. how- ever, the i 2 c bus interface circuit is not operated in stop mode or in low power consumption mode, because the i 2 c bus system clock v iic is not supplied. 16.6.4 bits 4,5 : sda/scl logic output value monitor bits sdam/sclm bits sdam/sclm can monitor the logic value of the sda and scl output signals from the i 2 c bus interface circuit. the sdam bit monitors the sda output logic value. the sclm bit monitors the scl output logic value. the sdam and sclm bits are read-only. when write, set them to 0. 16.6.5 bits 6,7 : i 2 c system clock select bits ick0, ick1 the ick1 bit, ick0 bit, bits ick4 to ick2 in the s4d0 register, and the pclk0 bit in the pclkr register can select the system clock (v iic ) of the i 2 c bus interface circuit. the i 2 c bus system clock v iic can be selected among 1/2 f iic , 1/2.5 f iic , 1/3 f iic , 1/4 f iic , 1/5 f iic , 1/6 f iic and 1/8 f iic . f iic can be selected between f 1 and f 2 by the pclk0 bit setting. i3ck4[s4d0] ick3[s4d0] ick2[s4d0] ick1[s3d0] ick0[s3d0] i 2 c system clock 00000v iic = 1/2 f iic 00001v iic = 1/4 f iic 00010v iic = 1/8 f iic 001xxv iic = 1/2.5 f iic 010xxv iic = 1/3 f iic 011xxv iic = 1/5 f iic 100xxv iic = 1/6 f iic table 16.6 i 2 c system clock select bits ( do not set the combination other than the above)
16. multi-master i 2 c bus interface page 263 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 16.7 i 2 c0 control register 2 (s4d0 register) the s4d0 register controls the error communication detection. if the scl clock is stopped counting dring data transfer, each device is stopped, staying online. to avoid the situation, the i 2 c bus interface circuit has a function to detect the time-out when the scl clock is stopped in high-level ("h") state for a specific period, and to generate an i 2 c bus interface interrupt request. see figure 16.13 . figure 16.13 the timing of time-out detection 1 clock 1 bit s cl s da bb flag internal counter start signal internal counter stop, reset signal internal counter overflow signal i 2 c-bus interface interrupt request signal 2 bit 3 bit 2 clock 3 clock s cl clock stop ( ? h ? ) the time of timeout detection
16. multi-master i 2 c bus interface page 264 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 16.7.1 bit0: time-out detection function enable bit (toe) the toe bit enables the time-out detection function. when the toe bit is set to 1, time-out is detected and the i 2 c bus interface interrupt request is generated when the following conditions are met. 1) the bb flag in the s10 register is set to 1 (bus busy) 2) the scl clock stops for time-out detection period while high-level ("h") signal is maintained (see table 16.7 ) the internal counter measures the time-out detection time and the tosel bit selects between two modes, long time and short time. when time-out is detected, set the es0 bit to 0 (i 2 c bus interface disabled) and reset the counter. 16.7.2 bit1: time-out detection flag (tof ) the tof flag indicates the time-out detection. if the internal counter which measures the time-out period overflows, the tof flag is set to 1 and the i 2 c bus interface interrupt request is generated at the same time. 16.7.3 bit2: time-out detection period select bit (tosel) the tosel bit selects time-out detection period from long time mode and short time mode. when the tosel bit is set to 0, long time mode is selected. when it is set to 1, short time mode is selected, respectively. the internal counter increments as a 16-bit counter in long time mode, while the counter increments as a 14-bit counter in short time mode, based on the i 2 c system clock (v iic ) as a counter source. table 16.7 shows examples of time-out detection period. table 16.7 examples of time-out detection period (unit: ms) 16.7.4 bits 3,4,5: i 2 c system clock select bits (ick2-4) bits ick4 to ick2, and bits ick1 and ick0 in the s3d0 register, and the pclk0 bit in the pclkr register select the system clock (v iic ) of the i 2 c bus interface circuit. see table 16.6 for the setting values. 16.7.5 bit7: stop condition detection interrupt request bit (scpin) the scpin bit monitors the stop condition detection interrupt. the scpin bit is set to 1 when the i 2 c bus interface interrupt is generated by detecting the stop condition. when this bit is set to 0 by program, it becomes 0. however, no change occurs even if it is set to 1. v iic (mhz) long time mode short time mode 4 16.4 4.1 2 32.8 8.2 1 65.6 16.4
16. multi-master i 2 c bus interface page 265 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 16.8 i 2 c0 start/stop condition control register (s2d0 register) the s2d0 register controls the start/stop condition detections. 16.8.1 bit0-bit4: start/stop condition setting bits (ssc0-ssc4) the scl release time and the set-up and hold times are mesured on the base of the i 2 c bus system clock (v iic ). therefore, the detection conditions changes, depending on the oscillation frequency (x in ) and the i 2 c bus system clock select bits. it is necessary to set bits ssc4 to ssc0 to the appropriate value to set the scl release time, the set-up and hold times by the system clock frequency (see table 16.10 ). do not set odd numbers or 00000 2 to bits ssc4 to ssc0. table 16.2 shows the reference value to bits ssc4 to ssc0 at each oscillation frequency in standard clock mode. the detection of start/stop conditions starts immediately after the es0 bit in the s1d0 register is set to 1 (i 2 c bus interface enabled). 16.8.2 bit5: scl/sda interrupt pin polarity select bit (sip) the the sip bit detect the rising edge or the falling edge of the scl mm or sda mm to generate scl/sda interrupts. the sip bit selects the polarity of the scl mm or the sda mm for interrupt. 16.8.3 bit6 : scl/sda interrupt pin select bit (sis) the sis bit selects a pin to enable scl/sda interrupt. note: 1. the scl/sda interrupt request may be set when changing the sip, sis and es0 bit settings in the s1d0 register. when using the scl/sda interrupt, set the above bits, while the scl/sda interrupt is disabled. then, enable the scl/sda interrupt after setting the scl/sda bit in the ir register to 0. 16.8.4 bit7: start/stop condition generation select bit (stspsel) the stspsel bit selects the set-up/hold times, based on the i2c system clock cycles, when the start/ stop condition is generated (see table 16.8 ). set the stspsel bit to 1 if the i 2 c bus system clock frequency is over 4mhz.
16. multi-master i 2 c bus interface page 266 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 16.9 start condition generation method set the mst bit, trx bit and bb flags in the s10 register to 1 and set the pin bit and 4 low-order bits in the s10 register to 0 simultaneously, to enter start condition standby mode, when the es0 bit in the s1d0 register is set to 1 (i 2 c bus interface enabled) and the bb flag is set to 0 (bus free). when the slave address is written to the s00 register next, start condition is generated and the bit counter is reset to 000 2 and 1- byte scl signal is output. the start condition generation timing varies between standard clock mode and high-speed clock mode. see figure 16.16 and table 16.8 . figure 16.14 start condition generation flow chart i n t e r r u p t d i s a b l e bb=0? s10 = e0 16 s00 = data interrupt enable n o yes start condition trigger generation start condition standby status setting *data = slave address data
16. multi-master i 2 c bus interface page 267 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 16.11 stop condition generation method when the es0 bit in the s1d0 register is set to 1 (i 2 c bus interface enabled) and bits mst and trx in the s10 register are set to 1 at the same time, set the bb flag, pin bit and 4 low-order bits in the s10 register to 0 simultaneously, to enter stop condition standby mode. when dummy data is written to the s00 register next, the stop condition is generated. the stop condition generation timing varies between standard clock mode and high-speed clock mode. see figure 16.17 and table 16.8 . until the bb flag in the s10 register becomes 0 (bus free) after an instruction to generate the stop condi- tion is executed, do not write data to registers s10 and s00. otherwise, the stop condition waveform may not be generated correctly. if an input signal level of the s cl pin is set to low ("l") after the instruction to generate the stop condition is executed, a signal level of the s cl pin becomes high ("h"), and the bb flag is set to 0 (bus free), the mcu outputs an "l" signal to s cl pin. in that case, the mcu can stop an "l" signal output to the s cl pin by generating the stop condition, writing 0 to the es0 bit in the s1d0 register (disabled), or writing 1 to the ihr bit in the s1d0 register (reset release). 16.10 start condition duplicate protect function a start condition is generated when verifying that the bb flag in the s10 register does not use buses. however, if the bb flag is set to 1 (bus busy) by the start condition which other master device generates immediately after the bb flag is verified, the start condition is suspended by the start condition dupli- cate protect function. when the start condition duplicate protect function starts, it operates as follows: ? disable the start condition standby setting if the function has already been set, first exit start condition standby mode and then set bits mst and trx in the s10 register to 0. ? writing to the s00 register is disabled. (the start condition trigger generation is disabled) ? if the start condition generation is interrupted, the al flag in the s10 register becomes 1.(arbitration lost detection) the start condition duplicate protect function is valid between the sda falling edge of the start condi- tion and the receive completion of the slave address. figure16.15 shows the duration of the start condition duplicate protect function. figure 16.15 the duration of the start condition duplicate protect function 1 clock 1 bit s cl s da bb flag 2 bit 3 bit 2 clock 3 clock 8 bit ack bit the duration of start condition duplicate protect 8 clock ack clock
16. multi-master i 2 c bus interface page 268 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 16.16 start condition generation timing diagram figure 16.17 stop condition generation timing diagram table 16.8 start/stop generation timing table as mentioned above, when bits mst and trx are set to 1, start condition or stop condition mode is entered by writing 1 or 0 to the bb flag in the s10 register and writing 0 to the pin bit and 4 low-order bits in the s10 register at the same time. then sda mm is left open in the start condition standby mode and sda mm is set to low-level ("l") in the stop condition standby mode. when the s00 register is set, the start/stop conditions are generated. in order to set bits mst and trx to 1 without generating the start/stop conditions, write 1 to the 4 low-order bits simultaneously. table 16.9 lists functions along with the s10 register settings. note: 1. actual time at the time of v iic = 4mhz, the contents in () denote cycle numbers. table 16.9 s10 register settings and functions s 0 0 r e g i s t e r s c l s d a hold time s e t u p t i m e s 00 reg i st er s c l s da setup time h o l d t i m e n o i t i d n o c p o t s / t r a t s t i b t c e l e s n o i t a r e n e g e d o m k c o l c d r a d n a t se d o m k c o l c d e e p s - h g i h e m i t p u t e s 00 . 5 ) s e l c y c 0 2 ( s5 . 2 ) s e l c y c 0 1 ( s 10 . 3 1 ) s e l c y c 2 5 ( s5 . 6 ) s e l c y c 6 2 ( s e m i t d l o h 00 . 5 ) s e l c y c 0 2 ( s5 . 2 ) s e l c y c 0 1 ( s 10 . 3 1 ) s e l c y c 2 5 ( s5 . 6 ) s e l c y c 6 2 ( s s g n i t t e s r e t s i g e r 0 1 s n o i t c n u f t s mx r tb bn i pl as a a0 s ab r l 11 1000 0 0 r e t s a m n i y b d n a t s n o i t i d n o c t r a t s e h t p u g n i t t e s e d o m t i m s n a r t 110 000 0 0 r e t s a m n i y b d n a t s n o i t i d n o c p o t s e h t p u g n i t t e s e d o m t i m s n a r t 1 / 01 / 0-01111 o t r e f e r ( e d o m n o i t a c i n u m m o c h c a e p u g n i t t e s 5 . 6 1 i 2 r e t s i g e r s u t a t s c )
16. multi-master i 2 c bus interface page 269 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 16.12 start/stop condition detect operation figure 16.18 , figure 16.19 and table 16.10 show start/stop condition detect operations. bits ssc4 to ssc0 in the s2d0 register set the start/stop conditions. the start/stop condition can be de- tected only when the input signal of the scl mm and sda mm met the following conditions: the scl release time, the set-up time, and the hold time (see table 16.10 ). the bb flag in the s10 register is set to 1 when the start condition is detected and it is set to 0 when the stop condition is detected. the bb flag set and reset timing varies between standard clock mode and high-speed clock mode. see table 16.10 . figure 16.18 start condition detection timing diagram figure 16.19 stop condition detection timing diagram standard clock mode high-speed clock mode scl release time ssc value + 1 cycle (6.25 s) 4 cycles (1.0 s) setup time ssc value + 1 cycle < 4.0 s (3.25 s) 2 cycles (0.5 s) 2 hold time ssc value cycle < 4.0 s (3.0 s) 2 cycles (0.5 s) 2 bb flag set/reset ssc value - 1 +2 cycles (3.375 s) 3.5 cycles (0.875 s) time 2 table 16.10 start/stop detection timing table s cl release time hold time setup time bb flag set time bb flag s da s cl bb flag s da s cl s cl release time hold time setup time bb flag set time note: 1. unit : number of cycle for i 2 c system clock v iic the ssc value is the decimal notation value of bits ssc4 to ssc0. do not set 0 or odd numbers to the ssc setting. the values in ( ) are examples when the s2d0 register is set to 18 16 at v iic = 4 mhz.
16. multi-master i 2 c bus interface page 270 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 16.13 address data communication this section describes data transmit control when a master transferes data or a slave receives data in 7-bit address format. figure 16.20 (1) shows a master transmit format. figure 16.20 address data communication format 16.13.1 example of master transmit for example, a master transmits data as shown below when following conditions are met: standard clock mode, scl clock frequency of 100khz and ack clock added. 1) set s slave address to the 7 high-order bits in the s0d0 register 2) set 85 16 to the s20 register, 000 2 to bits ick4 to ick2 in the s4d0 register and 00 16 to the s3d0 registe to generate an ack clock and set scl clock frequency t 100 khz (f 1 =8mhz, f iic =f1) 3) set 00 16 to the s10 register to reset transmit/receive 4) set 08 16 to the s1d0 register to enable data communication 5) confirm whether the bus is free by bb flag setting in the s10 register 6) set e0 16 to the s10 register to enter start condition standby mode 7) set the destination address in 7 high-order bits and 0 to a least significant bit in the s00 register to generate start condition. at this time, the first byte consisting of scl and ack clock are auto- matically generated 8) set a transmit data to the s00 register. at this time, scl and an ack clock are automatically generated 9) when transmitting more than 1-byte control data, repeat the above step 8). 10) set c0 16 in the s10 register to enter stop condition standby mode if ack is not returned from the slave receiver or if the transmit is completed 11) write dummy data to the s00 regiser to generate stop condition 1 - 8 bits s: start condition p: stop condition a: ack bit r/w: read/write bit s s l a v e a d d r e s s r/ w a d a t a aa/ a p sr/ w a a a p 1 d a t a d a t a d a t a s l a v e a d d r e s s 7 bits (1) a master transmit device transmits data to a receive device (2) a master receive device receives data from a transmit device 1 - 8 bits 1 - 8 bits 0 7 bits 1 - 8 bits
16. multi-master i 2 c bus interface page 271 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 16.13.2 example of slave receive for example, a slave receives data as shown below when following conditions are met: high-speed clock mode, scl frequency of 400 khz, ack clock added and addressing format. 1) set a slave address in the 7 high-order bits in the s0d0 register 2) set a5 16 to the s20 register, 000 2 to bits ick4 to ick2 in the s4d0 register, and 00 16 to the s3d0 register to generate an ack clock and set scl clock frequency at 400khz (f 1 = 8 mhz, f iic = f 1 ) 3) set 00 16 to the s10 register to reset transmit/receive mode 4) set 08 16 to the s1d0 register to enable data communication 5) when a start condition is received, addresses are compared 6) ? when the transmitted addresses are all 0 (general call), the adr0 bit in the s10 register is set to 1 and an i 2 c bus interface interrupt request signal is generated. ? when the transmitted addresses match with the address set in 1), the ass bit in the s10 register is set to 1 and an i 2 c bus interface interrupt request signal is generated. ? in other cases, bits adr0 and aas are set to 0 and i 2 c bus interface interrupt request signal is not generated. 7) write dummy data to the s00 register. 8) after receiving 1-byte data, an ack-clk bit is automatically returned and an i 2 c bus interface interrupt request signal is generated. 9) to determine whether the ack should be returned depending on contents in the received data, set dummy data to the s00 register to receive data after setting the wit bit in te s3d0 register to 1 (enable the i 2 c bus interface interrupt of data receive completion). because the i 2 c bus interface interrupt is generated when the 1-byte data is received, set the ackbit bit to 1 or 0 to output a signal from the ackbit bit. 10) when receiving more than 1-byte control data, repeat steps 7) and 8) or 7) and 9). 11) when a stop condition is detected, the communication is ended.
16. multi-master i 2 c bus interface page 272 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 16.14 precautions (1) access to the registers of i 2 c bus interface circuit the following is precautions when read or write the control registers of i 2 c bus interface circuit ? s00 register do not rewrite the s00 register during data transfer. if the bits in the s00 register are rewritten, the bit counter for transfer is reset and data may not be transferred successfully. ? s1d0 register bits bc2 o bc0 are set to 000 2 when start condition is detected or when 1-byte data transfer is completed. do not read or write the s1d0 register at this timing. otherwise, data may be read or written unsuccessfully. figures 16.22 and 16.23 show the bit counter reset timing. ? s20 register do not rewrite the s20 register except the ackbit bit during transfer. if the bits in the s20 register except ackbit bit are rewritten, the i 2 c bus clock circuit is reset and data may be transferred incom- pletely. ? s3d0 register rewrite bits ick4 to ick0 in the s3d0 register when the es0 bit in the s1d0 register is set to 0 (i 2 c bus interface is disabled). when the wit bit is read, the internal wait flag is read. therefore, do not use the bit managing instruction(read-modify-write instruction) to access the s3d0 register. ? s10 register do not use the bit managing instruction (read-modify-write instruction) because all bits in the s10 register will be changed, depending on the communication conditions. do not read/write when te communication mode select bits, bits mst and trx, are changing their value. otherwise, data may be read or written unsuccessfully. figures 16.21 to 16.23 show the timing when bits mst and trx change.
16. multi-master i 2 c bus interface page 273 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 16.21 the bit reset timing (the stop condition detection) figure 16.22 the bit reset timing (the start condition detection) mst trx bb flag s da s cl bit reset signal related bits 1.5 v iic cycle bb flag s da s cl bit reset signal bc2 - bc0 trx (in slave mode) related bits figure 16.23 bit set/reset timing ( at the completion of data transfer) s cl bit set signal aaa 1v iic c y cle pin bit aa 2v iic cycle bit reset signal aaaaa aaaaa bc0 - bc2 mst(when in arbitration lost) trx(when in nack receive in slave transmit mode) the bits referring to reset aaaaa aaaaa trx(als=0 meanwhile the slave receive r/w bit = 1 the bits referring to set
16. multi-master i 2 c bus interface page 274 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m (2) generation of restart condition in order to generate a restart condition after 1-byte data transfer, write e0 16 to the s10 register, enter start condition standby mode and leave the sda mm open. generate a start condition trigger by setting the s00 register after inserting a sufficient software wait until the sda mm outputs a high-level ("h") signal. figure 16.24 shows the restart condition generation timing. figure 16.24 the time of generation of restart condition 8 clocks ack clock s cl s10 writing signal (start condition setting standby) s da s00 writing signal (start condition triger generati on) insert software wait (3) iimitation of cpu clock when the cm07 bit in the cm0 register is set to 1 (subclock), each register of the i 2 c bus interface circuit cannot be read or written. read or write data when the cm07 bit is set to 0 (main clock, pll clock, or on-chip oscillator clock).
17. crc calculation circuit page 275 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 17. crc calculation circuit the cyclic redundancy check (crc) calculation detects an error in data blocks. the microcomputer uses a generator polynomial of crc_ccitt (x 16 + x 12 + x 5 + 1) or crc-16 (x 16 + x 15 + x 2 + 1) to generate crc code. the crc code is a 16-bit code generated for a block of a given data length in multiples of bytes. the code is updated in the crc data register everytime one byte of data is transferred to a crc input register. the data register must be initialized before use. generation of crc code for one byte of data is completed in two machine cycles. figure 17.1 shows the block diagram of the crc circuit. figure 17.2 shows the crc-related registers. figure 17.3 shows the calculation example using the crc_ccitt operation. 17.1 crc snoop the crc circuit includes the ability to snoop reads and writes to certain sfr addresses. this can be used to accumulate the crc value on a stream of data without using extra bandwidth to explicitly write data into the crcin register. all sfr addresses after 0020 16 are subject to the crc snoop. the crc snoop is useful to snoop the writes to a uart tx buffer, or the reads from a uart rx buffer. to snoop an sfr address, the target address is written to the crc snoop address register (crcsar). the two most significant bits of this register enable snooping on reads or writes to the target address. if the target sfr is written to by the cpu or dma, and the crc snoop write bit is set (crcsw=1), the crc will latch the data into the crcin register. the new crc code will be set in the crcd register. similarly, if the target sfr is read by the crc or dma, and the crc snoop read bit is set (crcsr=1), the crc will latch the data from the target into the crcin register and calculate the crc. the crc circuit can only calculate crc codes on data byte at a time. therefore, if a target sfr is accessed in word (16 bit), only one low-order byte data is stored into the crcin register. figure 17.1 crc circuit block diagram aaaaa eight low-order bits aaaaa eight high-order bits data bus high-order data bus low-order aaaaaaaaaa aaaaaaaaaa aaaaaa aaaaaa crcd register (16) crc input register (8) aaaaaaaaaa aaaaaaaaaa crc code generating circuit x 16 + x 12 + x 5 + 1 or x 16 + x 15 + x 2 + 1 address bus snoopb lock snoop enable snoop address aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa equal? (address 03bd 16 , 03bc 16 ) (address 03be 16 )
17. crc calculation circuit page 276 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 17.2 crcd, crcin, crcmr, crcsar register symbol address after reset crcd 03bd 16 to 03bc 16 undefined b7 b0 b7 b0 (b15) (b8) crc data register function setting range 0000 16 to ffff 16 rw rw symbol address after reset crcin 03be 16 undefined b7 b0 crc input register data input function 00 16 to ff 16 rw rw setting range crc calculation result output symbol address after reset crcmr 03b6 16 0xxxxxx0 2 b7 b0 crc mode register crc mode polynomial selection bit function 0: lsb first 1: msb first rw rw bit name bit symbol crc mode selection bit crcps crcms rw nothing is assigned. write "0" when writing to this bit. the value is indeterminate if read. 0: x 16 +x 12 +x 5 +1 (crc-ccitt) 1: x 16 +x 15 +x 2 +1 (crc-16) crc mode polynomial selection bit function 0: lsb first 1: msb first rw rw bit name bit symbol crc mode selection bit crcps crcms rw nothing is assigned. if necessary, set to 0. when read, the content is undefined 0: x 16 +x 12 +x 5 +1 (crc-ccitt) 1: x 16 +x 15 +x 2 +1 (crc-16) (b6-b1) symbol address after reset crcsar 03b5 16 to 03b4 16 00xxxxxx xxxxxxxx 2 b7 b0 b7 b0 (b15) (b8) sfr snoop address register crc mode polynomial selection bit function rw rw bit name bit symbol crcsr rw nothing is assigned. if necessary, set to 0. when read, the content is undefined sfr address to snoop function 0: disabled 1: enabled (1) rw crcsw crcsar9-0 crc snoop on read enable bit crc snoop on write enable bit 0: disabled 1: enabled (1) rw (b13-b10) note: 1. set bits crcsr and crcsw to 0 if the plc07 bit in the plc0 register is set to 1 (pll on) and the pm20 bit in the pm2 register is set to 0 (sfr access 2 wait).
17. crc calculation circuit page 277 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 17.3 crc calculation (1) setting 0000 16 (initial value) b15 b0 1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000 1000 1000 0001 0000 1 1000 0001 0000 1000 0 1000 1000 0001 0000 1 1001 0001 1000 1000 1000 1000 msb modulo-2 operation is operation that complies with the law given below. 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 -1 = 1 the code resulting from sending 01 16 in lsb first mode is (10000 0000).this the crc code in the generating polynomial, (x 16 + x 12 + x 5 + 1), becomes the remainder resulting from dividing (1000 0000)x 16 by ( 1 0001 0000 0010 0001) in conformity with the modulo-2 operation. (2) setting 01 16 b0 b7 b15 b0 1189 16 2 cycles after crc calculation is complete thus the crc code becomes ( 1001 0001 1000 1000). since the operation is in lsb first mode, the (1001 0001 1000 1000) corresponds to 1189 16 in hexadecimal notation. if the crc operation in msb first mode is necessary, set the crc mode selection bit to 1. crc data register stores crc code for msb first mode. crd data register crcd [03bd 16 , 03bc 16 ] crc input register crcin [03be 16 ] crd data register crcd [03bd 16 , 03bc 16 ] crc input register crcin [03be 16 ] (3) setting 23 16 b0 b7 b15 b0 0a41 16 after crc calculation is complete crd data register crcd [03bd 16 , 03bc 16 ] 98 11 msb lsb lsb stores crc code stores crc code
18. programmable i/o ports page 278 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 18. programmable i/o ports note ports p0 4 to p0 7 , p1 0 to p1 4 , p3 4 to p3 7 and p9 5 to p9 7 are not available in 64-pin package. the programmable input/output ports (hereafter referred to simply as ? i/o ports ? ) consist of 71 lines p0, p1, p2, p3, p6, p7, p8, p9, p10 (except p9 4 ) for the 80-pin package, or 55 lines p0 0 to p0 3 , p1 5 to p1 7 , p2, p3 0 to p3 3 , p6, p7, p8, p9 0 to p9 3 , p10 for the 64-pin package. each port can be set for input or output every line by using a direction register, and can also be chosen to be or not be pulled high in sets of 4 lines. figures 18.1 to 18.4 show the i/o ports. figure 18.5 shows the i/o pins. each pin functions as an i/o port, a peripheral function input/output. for details on how to set peripheral functions, refer to each functional description in this manual. if any pin is used as a peripheral function input, set the direction bit for that pin to 0 (input mode). any pin used as an output pin for peripheral functions is directed for output no matter how the corresponding direction bit is set. 18.1 port pi direction register (pdi register, i = 0 to 3, 6 to 10) figure 18.6 shows the direction registers. this register selects whether the i/o port is to be used for input or output. the bits in this register corre- spond one for one to each port. 18.2 port pi register (pi register, i = 0 to 3, 6 to 10) figure 18.7 shows the pi registers. data input/output to and from external devices are accomplished by reading and writing to the pi register. the pi register consists of a port latch to hold the output data and a circuit to read the pin status. for ports set for input mode, the input level of the pin can be read by reading the corresponding pi register, and data can be written to the port latch by writing to the pi register. for ports set for output mode, the port latch can be read by reading the corresponding pi register, and data can be written to the port latch by writing to the pi register. the data written to the port latch is output from the pin. the bits in the pi register correspond one for one to each port. 18.3 pull-up control register 0 to 2 (pur0 to pur2 registers) figure 18.8 shows registers pur0 to pur2. registers pur0 to pur2 select whether the pins, divided into groups of four pins, are pulled up or not. the pins, selected by setting the bits in registers pur0 to pur2 to 1 (pull-up), are pulled up when the direction registers are set to 0 (input mode). the pins are pulled up regardless of the pins ? function. 18.4 port control register (pcr register) figure 18.9 shows the port control register. when the p1 register is read after setting the pcr0 bit in the pcr register to 1, the corresponding port latch can be read no matter how the pd1 register is set.
18. programmable i/o ports page 279 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 18.5 pin assignment control register (pacr) figure 18.10 shows the pacr register. after reset, set bits pacr2 to pacr0 in the pacr register before a signal is input or output to each pin. when bits pacr2 to pacr0 are not set, some pins do not function as i/o ports. bits pacr2 to pacr0: control pins to be used value after reset: 000 2 . to select the 80-pin package, set the bits to 011 2 . to select the 64-pin package, set the bits to 010 2 . u1map bit: controls pin assignments for the uart1 function. to assign the uart1 function to p6 4 /cts 1 /rts 1 , p6 5 /clk 1 , p6 6 /rxd 1 , and p6 7 /txd 1 , set the u1map bit to 0 (p6 7 to p6 4 ). to assign the function to p7 0 /cts 1 /rts 1 , p7 1 /clk 1 , p7 2 /rxd 1 , and p7 3 /txd 1 , set the u1map bit to 1 (p7 3 to p7 0 ) the prc2 bit in the prcr protects the pacr register. set the pacr register after setting the prc2 bit in the prcr register. 18.6 digital debounce function two digital debounce function circuits are provided. level is determined when level is held, after applying either a falling edge or rising edge to the pin, longer than the programmed filter width time. this enables noise reduction. ________ _______ _____ this function is assigned to int5/inpc17 and nmi/sd. digital filter width is set in the nddr register and the p17ddr register respectively. figure 18.11 shows the nddr register and the p17ddr register. additionally, a digital debounce function is disabled to the port p1 7 input and the port p8 5 input. filter width : (n+1) x 1/f8 n: count value set in the nddr register and p17ddr register the nddr register and the p17ddr register decrement count value with f8 as the count source. the nddr register and the p17ddr register indicate count time. count value is reloaded if a falling edge or a rising edge is applied to the pin. the nddr register and the p17ddr register can be set 00 16 to ff 16 when using the digital debounce function. setting to ff 16 disables the digital filter. see figure 18.12 for details.
18. programmable i/o ports page 280 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 18.1 i/o ports (1) p1 0 to p1 3 p1 5 , p1 6 p2 2 to p2 7 , p3 0 , p6 0 , p6 1 , p6 4 , p6 5 , p7 4 to p7 6 , p8 0 , p8 1 p0 0 to p0 7 , p10 0 to p10 3 p3 0 to p3 7 (inside dotted-line included) (inside dotted-line not included) data bus data bus (1) analog input pull-up selection direction register port latch p1 4 (inside dotted-line not included) (inside dotted-line included) p1 7 (inside dotted-line not included) (inside dotted-line included) p3 2 (inside dotted-line not included) (inside dotted-line included) data bus direction register port latch pull-up selection (1) port p1 control register analog input direction register port latch pull-up selection (1) port p1 control register input to respective peripheral functions digital debounce inpc1 7 /int5 "1" output data bus direction register port latch pull-up selection (1) input to respective peripheral functions note: 1. symbolizes a parasitic diode. make sure the input voltage on each port will not exceed vcc.
18. programmable i/o ports page 281 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 18.2 i/o ports (2) p8 2 to p8 4 p3 1 , p6 2 , p6 6 , p7 7 data bus pull-up selection direction register port latch data bus pull-up selection direction register port latch input to respective peripheral functions input to respective peripheral functions p2 0 , p2 1 , p7 0 to p7 3 "1" output data bus direction register port latch pull-up selection (1) input to respective peripheral functions switching between cmos and nch (1) (1) note: 1. symbolizes a parasitic diode. make sure the input voltage on each port will not exceed vcc.
18. programmable i/o ports page 282 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 18.3 i/o ports (3) p8 5 p6 3 , p6 7 output ? 1 ? data bus pull-up selection direction register port latch switching between cmos and nch note: 1. symbolizes a parasitic diode. make sure the input voltage on each port will not exceed vcc. data bus pull-up selection direction register port latch nmi interrupt input nmi enable digital debounce nmi enable sd (1) (1) data bus direction register pull-up selection port latch analog input input to respective peripheral functions p9 1 , p9 2 , p9 7 , p10 4 to p10 7 (1)
18. programmable i/o ports page 283 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 18.4 i/o ports (4) 1 output direction register data bus port latch analog input pull-up selection (1) p8 7 p8 6 fc rf rd data bus direction register pull-up selection port latch direction register pull-up selection port latch data bus (1) (1) input to respective peripheral functions p9 0 , p9 5 (inside dotted-line included) p9 3 , p9 6 (inside dotted-line not included) note: 1. symbolizes a parasitic diode. make sure the input voltage on each port will not exceed vcc.
18. programmable i/o ports page 284 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 18.5 i/o pins cnv ss cnv ss signal input reset reset signal input (1) (1) note: 1. symbolizes a parasitic diode. make sure the input voltage on each port will not exceed vcc.
18. programmable i/o ports page 285 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 18.6 pd0 to pd3 and pd6 to pd10 registers port pi direction register (i=0 to 3, 6 to 8, and 10) (1) symbol address after reset bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 pdi_0 port pi 0 direction bit pdi_1 port pi 1 direction bit pdi_2 port pi 2 direction bit pdi_3 port pi 3 direction bit pdi_4 port pi 4 direction bit pdi_5 port pi 5 direction bit pdi_6 port pi 6 direction bit pdi_7 port pi 7 direction bit port p9 direction register (1,2) symbol address after reset pd9 03f3 16 000x0000 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 pd9_0 port p9 0 direction bit pd9_1 port p9 1 direction bit pd9_2 port p9 2 direction bit pd9_3 port p9 3 direction bit rw rw rw rw rw rw rw rw rw rw rw rw rw pd9_5 port p9 5 direction bit rw pd9_6 port p9 6 direction bit rw pd9_7 port p9 7 direction bit rw nothing is assigned. if necessary, set to 0. when read, the content is undefined (b4) 03e2 16 , 03e3 16 , 03e6 16 , 03e7 16 03ee 16 , 03ef 16 , 03f2 16 , 03f6 16 pd0 to pd3 pd6 to pd8 pd10 00 16 00 16 00 16 0: input mode (functions as an input port) 1: output mode (functions as an output port) (i = 0 to 3, 6 to 8, and 10) 0: input mode (functions as an input port) 1: output mode (functions as an output port) 0: input mode (functions as an input port) 1: output mode (functions as an output port) notes: 1. make sure the pd9 register is written to by the next instruction after setting the prc2 bit in the prcr register to 1(write enabled). 2. set the pacr register. in 80-pin package, set bits pacr2, pacr1, pacr0 to 011 2 . in 64-pin package, set bits pacr2, pacr1, pacr0 to 010 2 . note: 1. set the pacr register. in 80-pin package, set bits pacr2, pacr1, pacr0 to 011 2 . in 64-pin package, set bits pacr2, pacr1, pacr0 to 010 2 .
18. programmable i/o ports page 286 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 18.7 p0 to p3 and p6 to p10 registers port pi register (i=0 to 3, 6 to 8 and 10) (1) after reset undefined undefined undefined bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 pi_0 port pi 0 bit pi_1 port pi 1 bit pi_2 port pi 2 bit pi_3 port pi 3 bit pi_4 port pi 4 bit pi_5 port pi 5 bit pi_6 port pi 6 bit pi_7 port pi 7 bit port p9 register (1) symbol address after reset p9 03f1 16 undefined bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 p9_0 port p9 0 bit p9_1 port p9 1 bit p9_2 port p9 2 bit p9_3 port p9 3 bit (b4) nothing is assigned (2) p9_5 port p9 5 bit p9_6 port p9 6 bit p9_7 port p9 7 bit rw rw rw rw rw rw rw rw rw rw rw rw - rw rw rw rw the pin level on any i/o port which is set for input mode can be read by reading the corresponding bit in this register. the pin level on any i/o port which is set for output mode can be controlled by writing to the corresponding bit in this register 0: ? l ? level 1: ? h ? level (1) (i = 0 to 3, 6 to 8 and 10) the pin level on any i/o port which is set for input mode can be read by reading the corresponding bit in this register. the pin level on any i/o port which is set for output mode can be controlled by writing to the corresponding bit in this register (except for p8 5 ) 0: ? l ? level 1: ? h ? level address 03e0 16 , 03e1 16 , 03e4 16 , 03e5 16 03ec 16 , 03ed 16 , 03f0 16 03f4 16 symbol p0 to p3 p6 to p8 p10 note: 1. set the pacr register. in 80-pin package, set bits pacr2, pacr1, pacr0 to 011 2 . in 64-pin package, set bits pacr2, pacr1, pacr0 to 010 2 . notes: 1. set the pacr register. in 80-pin package, set bits pacr2, pacr1, pacr0 to 011 2 . in 64-pin package, set bits pacr2, pacr1, pacr0 to 010 2 . 2. nothing is assigned. if necessary, set to 0. when read, the content is 0.
18. programmable i/o ports page 287 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 18.8 pur0 to pur2 registers pull-up control register 0 (1) symbol address after reset pur0 03fc 16 00 16 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 pu00 p0 0 to p0 3 pull-up pu01 p0 4 to p0 7 pull-up pu02 p1 0 to p1 3 pull-up pu03 p1 4 to p1 7 pull-up pu04 p2 0 to p2 3 pull-up pu05 p2 4 to p2 7 pull-up pu06 p3 0 to p3 3 pull-up pu07 p3 4 to p3 7 pull-up 0: not pulled up 1: pulled up (1) pull-up control register 1 symbol address after reset pur1 03fd 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 pu14 p6 0 to p6 3 pull-up pu15 p6 4 to p6 7 pull-up pu16 p7 0 to p7 3 pull-up pu17 p7 4 to p7 7 pull-up 0: not pulled high 1: pulled high (1) note: 1. the pin for which this bit is 1 (pulled up) and the direction bit is 0 (input mode) is pulled up. rw rw rw rw rw rw rw rw rw rw rw rw rw note: 1. the pin for which this bit is 1 (pulled up) and the direction bit is 0 (input mode) is pulled up. pull-up control register 2 symbol address after reset pur2 03fe 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 pu20 p8 0 to p8 3 pull-up pu21 p8 4 to p8 7 pull-up pu22 p9 0 to p9 3 pull-up pu23 p9 5 to p9 7 pull-up pu24 p10 0 to p10 3 pull-up pu25 p10 4 to p10 7 pull-up nothing is assigned. if necessary, set to 0. when read, the content is 0 0: not pulled up 1: pulled up (1) rw rw rw rw rw rw rw (b7-b6) note: 1. the pin for which this bit is 1 (pulled up) and the direction bit is 0 (input mode) is pulled up. nothing is assigned. if necessary, set to 0. when read, the content is 0 (b3-b0)
18. programmable i/o ports page 288 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 18.9 pcr register figure 18.10 pacr register pin assignment control register (1) symbpl address after reset pacr 025d 16 00 16 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 pin enabling bit nothing is assigned. if necessary, set to 0. when read, the content is 0 rw (b6-b3) 010 : 64 pin 011 : 80 pin all other values are reserved. do not use. pacr0 pacr1 pacr2 rw rw reserved bits u1map uart1 pin remapping bit uart1 pins assigned to 0 : p6 7 to p6 4 1 : p7 3 to p7 0 rw note: 1. set the pacr register by the next instruction after setting the prc2 bit in the prcr register to 1 (write enable). port control register symbpl address after reset pcr 03ff 16 00 16 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 pcr0 port p1 control bit rw (b7-b1) operation performed when the p1 register is read 0: when the port is set for input, the input levels of p1 0 to p1 7 pins are read. when set for output, the port latch is read. 1: the port latch is read regardless of whether the port is set for input or output. nothing is assigned. if necessary, set to 0. when read, the content is 0
18. programmable i/o ports page 289 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 18.11 nddr and p17ddr registers nmi digital debounce register (1,2) symbol address after reset nddr 033e 16 ff 16 rw b7 b0 functio n rw setting range 00 16 to ff 16 if the set value =n, - n = 0 to fe 16 ; a signal with pulse width, greater than (n+1)/f8, is input into nmi / sd - n = ff 16 ; the digital debounce filter is disabled and all signals are input p1 7 digital debounce register (1) symbol address after reset p17ddr 033f 16 ff 16 rw b7 b0 functio n rw setting range 00 16 to ff 16 if the set value =n, - n = 0 to fe 16 ; a signal with pulse width, greater than (n+1)/f8, is input into inpc17/ int5 - n = ff 16 ; the digital debounce filter is disabled and all signals are input notes: 1. set the pacr register by the next instruction after setting the prc2 bit in the prcr register to 1 (write enable). 2. when using the nmi interrupt to exit from stop mode, set the nddr registert to ff 16 before entering stop mode. note: 1. when using the int5 interrupt to exit from stop mode, set the p17ddr registert to ff 16 before entering stop mode.
18. programmable i/o ports page 290 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 18.12 functioning of digital debounce filter f 8 p1 7 data bus 1. (condition after reset). p17ddr=ff 16 . pin input signal will be output directly. 2. set the p17ddr register to 03 16 . the p17ddr register starts decrement along the f8 as a counter source, if the pin input level (e.g.,"l") and the signal output level (e.g.,"h") are not matched. 3. the p17ddr register will stops counting when the pin input level and the signal output level are matched (e.g., both levels are "h") while counting. 4. if the pin input level (e.g.,"l") and the signal output level (e.g.,"h") are not matched the p17ddr register will start decrement again after the setting value is reloaded. 5. when the p17ddr register is underflow, it stops counting and the signal output will output the same as pin input level (e.g."l"). 6. if the pin input level (e.g.,"h") and the signal output level (e.g., "l") are not matched again, the p17ddr register will start decrement again after the setting value is reloaded. 7. when the p17ddr register is underflow, it stops counting and the signal output will output the same as pin input level (e.g."h"). 8. if the pin input level (e.g.,"h") and the signal output level (e.g., "l") are not matched again, the p17ddr register will start decrement again after the setting value is reloaded. 9. set the p17ddr register to ff 16 . the p17ddr register starts counting after the setting value is reloaded. pin input signal will be output directly. clock port in reload value (write) digital debounce filter signal out count value (read) to int5 data bus f 8 reload value port in signal out count value reload value (continued) port in (continued) signal out (continued) count value (continued) ff 03 ff 03 02 01 03 02 01 00 ff 03 ff 03 02 01 00 ff ff 03 02 ff 1 2 3 4 5 6 7 8 9 ? example of int5 digital debounce function (if p17ddr = 03 16 )
18. programmable i/o ports page 291 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m table 18.1 unassigned pin handling in single-chip mode figure 18.13 unassigned pins handling (input mode) (input mode) (output mode) x out av cc av ss v ref mcu v cc v ss in single-chip mode open open (1) port p0 to p3, p6 to p10 x in note: 1. when using the 64-pin package, set bits pacr2, pacr1, and pacr0 to 010 2 . when using the 80-pin package, set bits pacr2, pacr1, and pacr0 to 011 2 . e m a n n i pg n i t t e s 0 1 p o t 6 p , 3 p o t 0 p s t r o p v o t n i p h c a e t c e n n o c d n a e d o m t u p n i r e t n e s s ; ) n w o d - l l u p ( r o t s i s e r a a i v n e p o s n i p e h t e v a e l d n a e d o m t u p t u o r e t n e r o ) 4 , 2 , 1 ( x t u o n e p o n i p e v a e l ) 3 ( x n i v o t n i p t c e n n o c c c ) p u - l l u p ( r o t s i s e r a a i v ) 5 ( v a c c v o t n i p t c e n n o c c c v a s s v , f e r v o t n i p t c e n n o c s s notes: 1. if the port enters output mode and is left open, it is in input mode before output mode is entered by program after reset. while the port is in input mode, voltage level on the pins is indeterminate and power consumption may increase. direction register setting may be changed by noise or failure caused by noise. configure direction register settings regulary to increase the reliability of the program. 2. use the shortest possible wiring to connect the mcu pins to unassigned pins (within 2 cm). 3. when the external clock is applied to the xin pin, set the pin as written above. 4. in the 64-pin package, set bits pacr2, pacr1, and pacr0 in the pacr register to 010 2 . in the 80-pin package, set bits pacr2, pacr1, and pacr0 to 011 2 . 5. when the main clock oscillation is not used, set the cm05 bit in the cm0 register to 1 (main clock stops) to reduce power consumption.
19. flash memory version page 292 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 19. flash memory version 19.1 flash memory performance in the flash memory version, rewrite operation to the flash memory can be performed in three modes: cpu rewrite mode, standard serial i/o mode, and parallel i/o mode. table 19.1 lists specifications of the flash memory version. (refer to table 1.1 or table 1.2 for the items not listed in table 19.1. table 19.1 flash memory version specifications item flash memory operating mode erase block program method erase method program, erase control method protect method number of commands program/erase endurance (1) rom code protection specification 3 modes (cpu rewrite, standard serial i/o, parallel i/o) see figure 19.1 and 19.2 flash memory block diagram in units of word block erase program and erase controlled by software command blocks 0 to 4 are write protected by bit fmr16. in addition, the block 0 and block 1 are write protected by bit fmr02. 5 commands 100 times 1,000 times (see table 1.5 to 1.8 ) 100 times 10,000 times (see table 1.5 to 1.8 ) parallel i/o and standard serial i/o modes are supported. data retention 20 years (topr = 55 o c) block 0 to 4 (program area) block a and b (data are) (2) notes: 1. program and erase endurance definitionprogram and erase endurance are the erase endurance of each block. if the program and erase endurance are n times (n=100,1000,10000), each block can be erased n times. for example, if a 2-kbyte block a is erased after writing 1 word data 1024 times, each to different addresses, this is counted as one program and erasure. however, data cannot be written to the same address more than once without erasing the block. (rewrite disabled) 2. to use the limited number of erasure efficiently, write to unused address within the block instead of rewrite. erase block only after all possible address are used. for example, an 8-word program can be written 128 times before erase is necessary. maintaining an equal number of erasure between block a and b will also improve efficiency. we recommend keeping track of the number of times erasure is used.
19. flash memory version page 293 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m table 19.2 flash memory rewrite modes overview flash memory cpu rewrite mode standard serial i/o mode parallel i/o mode rewrite mode function software command execution a dedicated serial programmer a dedicated parallel program- by cpu rewrites the user rom rewrites the user rom area. mer rewrites the user rom area. standard serial i/o mode 1: area. ew mode 0: clock synchronous serial i/o rewritable in area other than standard serial i/o mode 2: flash memory uart ew mode 1: rewritable in flash memory areas which user rom area user rom area user rom area can be rewritten operation mode single chip mode boot mode parallel i/o mode rom none serial programmer parallel programmer programmer 19.1.1 boot mode the mcu enters boot mode when a hardware reset is performed while a high-level ("h") signal is applied to pins cnv ss and p8 6 or while an "h" signal is applied to pins cnv ss and p1 6 and a low-level ("l") signal is applied to the p8 5 . a program in the boot rom area is executed. the boot rom area is reserved. the boot rom area stores the rewrite control program for a standard serial i/o mode before shipping. do not rewrite the boot rom area.
19. flash memory version page 294 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 19.2 memory map the flash memory contains the user rom area and the boot rom area (reserved area). figures 19.1 and 19.2 show a block diagram of the flash memory. the user rom area has space to store the mcu operation program in single-chip mode and two 2-kbyte spaces: the block a and b. the user rom area is divided into several blocks. the user rom area can be rewritten in cpu rewrite, standard serial input/output, or parallel input/output mode. however, to rewrite program in block 0 and 1 in cpu rewrite mode, set the fmr02 bit in the fmr0 register to 1 (block 0, 1 rewrite enabled) and the fmr16 bit in the fmr1 register to 1 (blocks 0 to 4 rewrite enabled). also, to rewrite program in blocks 2 to 4 in cpu rewrite mode, set the fmr16 bit in the fmr1 register to 1 (blocks 0 to 4 rewrite enabled). when the pm10 bit in the pm1 register is set to 1 (data space access enabled), block a and b can be available for use. the boot rom area (4-byte) is a reserved area. this boot rom area has a standard serial i/o mode control program stored before shipping. do not rewrite the boot rom area. 00ffff 16 block b :2k bytes (2) 00f000 16 4k bytes (4) 0ff000 16 0fffff 16 boot rom area 0fe000 16 0fc000 16 0fdfff 16 0f8000 16 block 2 : 16k bytes 0fbfff 16 0f7fff 16 0f0000 16 0fffff 16 user rom area block a :2k bytes (2) block 2 : 16k bytes (5) block 3 : 32k bytes (5) block 1 : 8k bytes (3) block 0 : 8k bytes (3) 00f7ff 16 00f800 16 notes: 1. to specify a block, use the maximum even address in the block. 2. blocks a and b are enabled to use when the pm10 bit in the pm1 register is set to 1. 3. blocks 0 and 1 are enabled for programs and erases when the fmr02 bit in the fmr0 register is set to 1 and the fmr16 bit in the fmr1 register is set to 1. (cpu rewrite mode only) 4. the boot rom area is reserved. do not access. 5. blocks 2 and 3 are enabled for programs and erases when the fmr16 bit in the fmr1 register is set to 1. (cpu rewrite mode only) (data space) (program space) figure 19.1 flash memory block diagram (rom capacity 64 kbytes)
19. flash memory version page 295 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 00ffff 16 block b :2k bytes (2) 00f000 16 4k bytes (4) 0ff000 16 0fffff 16 boot rom area 0fe000 16 0fc000 16 0fdfff 16 0f8000 16 block 2 : 16k bytes 0fbfff 16 0f7fff 16 0f0000 16 0effff 16 0fffff 16 user rom area 0e8000 16 block a :2k bytes (2) block 2 : 16k bytes (5) block 4 : 32k bytes (5) block 3 : 32k bytes (5) block 1 : 8k bytes (3) block 0 : 8k bytes (3) 00f7ff 16 00f800 16 notes: 1. to specify a block, use the maximum even address in the block. 2. blocks a and b are enabled for use when the pm10 bit in the pm1 register is set to 1. 3. blocks 0 and 1 are enabled for programs and erasure when the fmr02 bit in the fmr0 register is set to 1 and the fmr16 bit in the fmr1 register is set to 1. (cpu rewrite mode only) 4. the boot rom area is reserved. do not rewrite. 5. blocks 2 to 4 are enabled for programs and erasure when the fmr16 bit in the fmr1 register is set to 1. (cpu rewrite mode only) (data space) (program space) figure 19.2 flash memory block diagram (rom capacity 96 kbytes)
19. flash memory version page 296 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 19.3 functions to prevent flash memory from rewriting the flash memory has a built-in rom code protect function for parallel i/o mode and a built-in id code check function for standard input/output mode to prevent the flash memory from reading or rewriting. 19.3.1 rom code protect function the rom code protect function disables reading or changing the contents of the on-chip flash memory in parallel i/o mode. figure 19.3 shows the romcp address. the romcp address is located in a user rom area. to enable rom code protect, set the romcp1 bit to 00 2 , 01 2 , or 10 2 and set the bits 5 to 0 to 111111 2 . to cancel rom code protect, erase the block including the the romcp register in cpu rewrite mode or standard serial i/o mode. 19.3.2 id code check function use the id code check function in standard serial input/output mode. unless the flash memory is blank, the id code sent from the programmer and the 7-byte id code written in the flash memory are compared for match. if the id codes do not match, the commands sent from the programmer are not acknowledged. the id code consists of 8-bit data, starting with the first byte, into addresses, 0fffdf 16 , 0fffe3 16 , 0fffeb 16 , 0fffef 16 , 0ffff3 16 , 0ffff7 16 , and 0ffffb 16 . the flash memory must have a program with the id code set in these addresses.
19. flash memory version page 297 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m symbol address factory setting romcp 0fffff 16 ff 16 (4) rom code protect control address (5) bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 00: 01: 10: 11: disables protect rom code protect level 1 set bit (1, 2, 3, 4 ) romcp1 b7 b6 1 1 reserved bit set to 1 enables protect } 1 1 rw rw rw rw (b5-b0) notes: 1. when the rom code protect is active by the romcp1 bit setting, the flash memory is protected against reading or rewriting in parallel i/o mode. 2. set the bit 5 to bit 0 to 111111 2 when the romcp1 bit is set to a value other than 11 2 . when the bit 5 to bit 0 are set to values other than 111111 2 , the rom code protection may not become active by setting the romcp1 bit to a value other than 11 2 . 3. to make the rom code protection inactive, erase a block including the romcp address in standard serial i/o mode or cpu rewrite mode. 4. the romcp address is set to ff 16 when a block, including the romcp address, is erased. 5. when a value of the romcp address is 00 16 or ff 16 , the rom code protect function is disabled. reset vector watchdog timer vector single step vector address match vector brk instruction vector overflow vector undefined instruction vector id7 id6 id5 id4 id3 id2 id1 dbc vector nmi vector 0fffff 16 to 0ffffc 16 0ffffb 16 to 0ffff8 16 0ffff7 16 to 0ffff4 16 0ffff3 16 to 0ffff0 16 0fffef 16 to 0fffec 16 0fffeb 16 to 0fffe8 16 0fffe7 16 to 0fffe4 16 0fffe3 16 to 0fffe0 16 0fffdf 16 to 0fffdc 16 4 bytes address romcp figure 19.3 romcp address figure 19.4 address for id code stored
19. flash memory version page 298 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m item ew mode 0 ew mode 1 operation mode single chip mode single chip mode areas in which a user rom area user rom area rewrite control program can be located areas where the rewrite control program must be the rewrite control program can be rewrite control transferred to any other than the flash excuted in the user rom area program can be memory (e.g., ram) before being executed (2) executed areas which can be user rom area user rom area rewritten however, this excludes blocks with the rewrite control program software command none ? program, block erase command restrictions cannot be executed in a block having the rewite control program ? read status register command cannot be executed mode after programming read status register mode read array mode or erasing cpu state during auto- operating in a hold state (i/o ports retain the state write and auto-erase before the command is excuted (1) flash memory status ? read bits fmr00, fmr06, and read bits fmr00, fmr06, and fmr07 detection fmr07 in the fmr0 register by in the fmr0 registerby program program ? execute the read status register command to read bits sr7, sr5, and sr4. condition for transferring set bits fmr40 and fmr41 in the fmr40 bit in the fmr4 register is to erase-suspend (3) the fmr4 register to 1 by program. set to 1 and the interruput request of an acknowledged interrupt is generated notes: 1. do not generate a dma transfer. 2. block 1 and block 0 are enabled for rewrite by setting fmr02 bit in the fmr0 register to 1 and setting fmr16 bit in the fmr1 register to 1. block 2 to block 4 are enabled for rewrite by setting fmr16 bit in the fmr1 register to 1. 3. the time, until entering erase suspend and reading flash is enabled, is maximum td(sr-es) after satisfying the conditions. 19.4 cpu rewrite mode in cpu rewrite mode, the user rom area can be rewritten when the cpu executes software commands. the user rom area can be rewritten with mcu mounted on a board without using the rom writer. the program and block erase commands are executed only in the user rom area. when the interrupt requests are generated during the erase operation in cpu rewirte mode, the flash memory offers an erase suspend function to suspend the erase operation and process the interrupt opera- tion. during the erase suspend function is operated, the user rom area can be read by program. erase-write(ew) 0 mode and erase-write 1 mode are provided as cpu rewrite mode. table 19.3 lists differences between ew mode 0 and ew mode 1. one wait is required for the cpu erase-write control. table 19.3 ew mode 0 and ew mode 1
19. flash memory version page 299 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 19.4.1 ew mode 0 the mcu enters cpu rewrite mode by setting the fmr01 bit in the fmr0 register to 1 (cpu rewrite mode enabled) and is ready to accept software commands. ew mode 0 is selected by setting the fmr11 bit in the fmr1 register to 0. to set the fmr01 bit to 1, set to 1 after first writing 0. the software commands control programming and erasing. the fmr0 register or the status register indicates whether a programming or erasing operations is completed. when entering the erase-suspend during the auto-erasing, set the fmr40 bit to 1 (erase-suspend en- abled) and the fmr41 bit to 1 (suspend request). after waiting for td(sr-es) and verifying the fmr46 bit is set to 1 (auto-erase stop), access to the user rom area. when setting the fmr41 bit to 0 (erase restart), auto-erasing is restarted. 19.4.2 ew mode 1 ew mode 1 is selected by setting the fmr11 bit to 1 after the fmr01 bit is set to 1 (set to 1 after first writing 0). the fmr0 register indicates whether or not a programming or an erasing operation is completed. read status register cannot be read in ew mode 1. when an erase/program command is initiated, the cpu halts all program execution until the command operation is completed or erase-suspend request is generated. when enabling an erase-suspend function, set the fmr40 bit to 1 (erase suspend enabled) and execute block erase commands. also, the interrupt to transfer to erase-suspend must be set enabled preliminar- ily. when entering erase-suspend after td(sr-es) from an interrupt is requested, interrupts can be ac- cepted. when an interrupt request is generated, the fmr41 bit is automatically set to 1 (suspend request) and an auto-erasing is suspended. if an auto-erasing has not completed (when the fmr00 bit is 0) after an interrupt process is completed, set the fmr41 bit to 0 (erase restart) and execute block erase commands again.
19. flash memory version page 300 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 19.5 register description figure 19.5 shows the flash memory control register 0 and flash memory control register 1. figure 19.6 shows the flash memory control register 4. 19.5.1 flash memory control register 0 (fmr0) ? fmr 00 bit the fmr00 bit indicates the operating state of the flash memory. its value is 0 while the program, erase, or erase-suspend command is being executed, otherwise, it is 1. ? fmr01 bit the mcu can accept commands when the fmr01 bit is set to 1 (cpu rewrite mode). to set the fmr01 bit to 1, first set it to 0 and then 1. the fmr01 bit is set to 0 only by writing 0. ? fmr02 bit the combined settings of bits fmr02 and fmr16 enable program and erase in the user rom area. see table 19.4 for setting details. to set the fmr02 bit to 1, first set it to 0 and then 1. the fmr02 bit is valid only when the fmr01 bit is set to 1 (cpu rewrite mode enable). ? fmstp bit the fmstp bit initializes the flash memory control circuits and minimizes power consumption in the flash memory. access to the on-chip flash memory is disabled when the fmstp bit is set to 1. set the fmstp bit by program in a space other than the flash memory. set the fmstp bit to 1 if one of the following occurs: ? a flash memory access error occurs during erasing or programming in ew mode 0 (fmr00 bit does not switch back to 1 (ready)). ? low-power consumption mode or on-chip oscillator low-power consumption mode is entered. figure 19.9 shows a flow chart illustrating how to start and stop the flash memory before and after entering low power mode. follow the procedure in this flow chart. when entering stop or wait mode while the cpu rewrite mode is disabled, do not set the fmr0 register because the on-chip flash memory is automatically turned off and turned back on when exiting. ? fmr06 bit the fmr06 bit is a read-only bit indicating an auto-program operation state. the fmr06 bit is set to 1 when a program error occurs; otherwise, it is set to 0. for details, refer to 19.8.4 full status check . ? fmr07 bit the fmr07 bit is a read-only bit indicating an auto-erase operation status. the fmr07 bit is set to 1 when an erase error occurs; otherwise, it is set to 0. for details, refer to 19.8.4 full status check . figure 19.7 shows a ew mode 0 set/reset flowchart, figure 19.8 shows a ew mode 1 set/reset flow- chart.
19. flash memory version page 301 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 19.5.2 flash memory control register 1 (fmr1) ? fmr11 bit ew mode 1 is entered by setting the fmr11 bit to 1 (ew mode 1). the fmr11 bit is valid only when the fmr01 bit is set to 1. ? fmr16 bit the combined setting of bits fmr02 and fmr16 enables program and erase in the user rom area. to set the fmr16 bit to 1, first set it to 0 and then 1. the fmr16 bit is valid only when the fmr01 bit is set to 1 (cpu rewrite mode enable). ? fmr17 bit if the fmr17 bit is set to 1 (with wait state), 1 wait state is inserted when blocks a and b are accessed, regardless of the content of the pm17 bit in the pm1 register. the pm17 bit setting is reflected to access other blocks and internal ram, regardless of the fmr17 bit setting. set the fmr17 bit to 1 (with wait state) to rewrite more than 100 times. table 19.4 protection using fmr16 and fmr02 fmr16 fmr02 block a, block b block 0, block 1 other user block 0 0 write enabled write disabled write disabled 0 1 write enabled write disabled write disabled 1 0 write enabled write disabled write enabled 1 1 write enabled write enabled write enabled 19.5.3 flash memory control register 4 (fmr4) ? fmr40 bit the erase-suspend function is enabled when the fmr40 bit is set to 1 (enabled). ? fmr41 bit when the fmr41 bit is set to 1 by program during auto-erasing in ew mode 0, erase-suspend mode is entered. in ew mode 1, the fmr41 bit is automatically set to 1 (suspend request) to enter erase- suspend mode when an enabled interrupt request is generated. set the fmr41 bit to 0 (erase restart) to restart an auto-erasing operation. ? fmr46 bit the fmr46 bit is set to 0 during auto-erasing. it is set to 1 in erase-suspend mode. do not access to flash memory when the fmr46 bit is set to 0.
19. flash memory version page 302 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 19.5 fmr0 and fmr1 registers notes: flash memory control register 0 symbol address after reset fmr0 01b7 16 00000001 2 b7 b6 b5 b4 b3 b2 b1 b0 fmr00 bit symbol bit name function rw 0: busy (during writing or erasing) 1: ready cpu rewrite mode select bit (1) 0: disables cpu rewrite mode (disables software command) 1: enables cpu rewrite mode (enables software commands) fmr01 block 0, 1 rewrite enable bit (2) set write protection for user rom area (see table 19.4 ) flash memory stop bit (3, 5) fmr02 fmstp 0 ry/by status flag reserved bit set to 0 0: successfully completed 1: completion error program status flag fmr06 0: successfully completed 1: completion error erase status flag fmr07 rw rw rw rw ro ro ro (b5-b4) 0: starts flash memory operation 1: stops flash memory operation (enters low-power consumption state and flash memory reset) 0 (4) (4 ) flash memory control register 1 symbol address after reset fmr1 01b5 16 000xxx0x 2 b7 b6 b5 b4 b3 b2 b1 b0 bit symbol bit name function ew mode 1 select bit (1) 0: ew mode 0 1: ew mode 1 fmr11 block a, b access wait bit (3) reserved bit when read, the content is undefined reserved bit set to 0 nothing is assigned. if necessary, set to 0. when read, the content is undefined rw ro rw rw rw (b0) (b4) reserved bit (b3-b2) ro notes: 1. set the fmr11 bit to 1 immediately after setting it first to 0 while the fmr01 bit is set to 1. do not generate an interrupt or a dma transfer between setting the bit to 0 and setting it to 1. set this bit while the p8 5 /nmi/sd pin is held "h" when the nmi function is selected. if the fmr01 bit is set to 0, bits fmr01 and fmr11 are both set to 0. (b5) fmr16 rw block 0 to 5 rewrite enable bit (2 ) fmr17 set write protection for user rom space (see table 19.4 ) 0: disable 1: enable 0: pm17 enabled 1: with wait state (1 wait) when read, the content is undefined 0 2. set this bit to 1 immediately after setting it first to 0 while the fmr01 bit is set to 1. do not generate an interrupt or a dma transfer between setting this bit to 0 and setting it to 1. 3. when rewriting more than 100 times, set this bit to 1 (with wait state). when the fmr17 bit is set to1(with wait state), regardless of the pm17 bit setting, 1 wait state is inserted when accessing to blocks a and b. the pm17 bit setting is enabled, regardless of the fmr17 bit setting, as to the access to other block and the internal ram. 1. set the fmr01 bit to 1 immediately after setting it first to 0. do not generate an interrupt or a dma transfer between setting the bit to 0 and setting it to 1. set this bit while the p8 5 /nmi/sd pin is held ?h? when selecting the nmi function. set by program in a space other than the flash memory in ew mode 0. set this bit to read alley mode and 0. 2. set this bit to 1 immediately after setting it first to 0 while the fmr01 bit is set to 1. do not generate an interrupt or a dma transfer between setting this bit to 0 and setting it to 1. 3. set this bit in a space other than the flash memory by program. when this bit is set to 1, access to flash memory will be denied. to set this bit to 0 after setting it to 1, wait for 10 usec. or more after setting it to 1. to read data from flash memory after setting this bit to 0, maintain tps wait time before accessing flash memory. 4. this bit is set to 0 by executing the clear status command. 5. this bit is enabled when the fmr01 bit is set to 1 (cpu rewrite mode). if the fmr01 bit is set to 0, this bit can be set to 1 by writing 1 to the fmr01 bit. however, the flash memory does not enter low-power consumption status and it is not initialized.
19. flash memory version page 303 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 19.6 fmr4 register flash memory control register 4 symbol address after reset fmr4 01b3 16 01000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit symbol bit name function erase suspend request bit (2) 0: erase restart 1: suspend request fmr41 0 reserved bit set to 0 erase suspend function enable bit (1) 0: disabled 1: enabled reserved bit set to 0 0 0 rw rw rw ro rw fmr40 (b5-b2) (b7) ro fmr46 00 erase status 0: during auto-erase operation 1: auto-erase stop (erase suspend mode) notes: 1. set the fmr40 bit to 1 immediately after setting it first to 0. do not generate an interrupt or a dma transfer between setting the bit to 0 and setting it to 1. set by program in a space other than the flash memory in ew mode 0. 2. the fmr41 bit is valid only when the fmr40 bit is set to 1. the fmr41 bit can be written only between executing an erase command and completing erase (this bit is set to 0 other than the above duration). the fmr41 bit can be set to 0 or 1 by program in ew mode 0. in ew mode 1, the fmr41 bit is automatically set to 1 when the fmr40 bit is 1 and a maskable interrupt is generated during erasing. the fmr41 bit cannot be set to 1 by program (it can be set to 0 by program).
19. flash memory version page 304 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 19.7 setting and resetting of ew mode 0 figure 19.8 setting and resetting of ew mode 1 execute the read array command (3) single-chip mode set cm0, cm1, and pm1 registers (1) execute software commands jump to the rewrite control program transfered to an internal ram area (in the following steps, use the rewrite control program internal ram area) transfer a rewrite control program to internal ram area write 0 to the fmr01 bit (cpu rewrite mode disabled) set the fmr01 bit to 1 after writing 0 (cpu rewrite mode enabled) (2) ew mode 0 operation procedure rewrite control program jump to a specified address in the flash memory notes: 1. select 10 mhz or below for cpu clock using the cm06 bit in the cm0 register and bits cm17 to 16 in the cm1 register. also, set the pm17 bit in the pm1 register to 1 (with wait state). 2. set the fmr01 bit to 1 immediately after setting it to 0. do not generate an interrupt or a dma transfer between setting the bit to 0 and setting it to 1. set the fmr01 bit in a space other than the internal flash memory. also, set only when the p8 5 /nmi/sd pin is ? h ? at the time of the nmi function selected. 3. disables the cpu rewrite mode after executing the read array command. single-chip mode set cm0, cm1, and pm1 registers (1) set the fmr01 bit to 1 (cpu rewrite mode enabled) after writing 0 set the fmr11 bit to 1 (ew mode 1) after writing 0 (2, 3) program in rom ew mode 1 operation procedure execute software commands set the fmr01 bit to 0 (cpu rewrite mode disabled) notes: 1. select 10 mhz or below for cpu clock using the cm06 bit in the cm0 register and bits cm17 to 16 in the cm1 register. also, set the pm17 bit in the pm1 register to 1 (with wait state). 2. set the fmr01 bits to 1 immediately after setting it to 0. do not generate an interrupt or a dma transfer between setting the bit to 0 and setting the bit to 1. set the fmr01 bit in a space other than the internal flash memory. set only when the p8 5 /nmi/sd pin is ? h ? at the time of the nmi function selected. 3. set the fmr11 bit to 1 immediately after setting it to 0 while the fmr01 bit is set to 1. do not generate an interrupt or a dma transfer between setting the fmr11 bit to 0 and setting it to 1.
19. flash memory version page 305 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 19.9 processing before and after low power dissipation mode start main clock oscillation transfer a low power internal consumption mode program to ram area switch the clock source of cpu clock. turn main clock off (2) jump to the low power consumption mode program transferred to internal ram area. (in the following steps, use the low-power consumption mode program or internal ram area) wait until the flash memory circuit stabilizes ( tps ) (3) set the fmstp bit to 0 (flash memory operation) set the fmstp bit to 1 (flash memory stopped. low power consumption state) (1) process of low power consumption mode or on-chip oscillator low power consumption mode switch the clock source of the cpu clock (2) low power consumption mode program set the fmr01 bit to 0 (cpu rewrite mode disabled) set the fmr01 bit to 1 after setting 0 (cpu rewrite mode enabled) (2) jump to a desired address in the flash memory wait until oscillation stabilizes notes: 1. set the fmrstp bit to 1 after setting the fmr01 bit to 1 (cpu rewrite mode). 2. wait until the clock stabilizes to switch the clock source of the cpu clock to the main clock or the sub clock. 3. add a tps wait time by a program. do not access the flash memory during this wait time.
19. flash memory version page 306 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 19.6 precautions in cpu rewrite mode described below are the precautions to be observed when rewriting the flash memory in cpu rewrite mode. 19.6.1 operation speed when the cpu clock source is the main clock, set the cpu clock frequency at 10 mhz or less with the cm06 bit in the cm0 register and bits cm17 and cm16 in the cm1 register, before entering cpu rewrite mode (ew mode 0 or ew mode 1). also, when selecting f 3 (roc) of a on-chip oscillator as a cpu clock source, set bits rocr3 and rocr2 in the rocr register to the cpu clock division rate at ? divide-by-4 ? or ? divide-by-8 ? , before entering cpu rewrite mode (ew mode 0 or ew mode 1). in both cases, set the pm17 bit in the pm1 register to 1 (with wait state). 19.6.2 prohibited instructions the following instructions cannot be used in ew mode 0 because the cpu tries to read data in the flash memory: und instruction, into instruction, jmps instruction, jsrs instruction, and brk instruction 19.6.3 interrupts ew mode 0 ? to use interrupts having vectors in a relocatable vector table, the vectors must be relocated to the ram area. _______ ? the nmi and watchdog timer interrupts are available since registers fmr0 and fmr1 are forcibly reset when either interrupt occurs. however, the interrupt program, which allocates the jump addresses for each interrupt routine to the fixed vector table, is needed. flash memory rewrite _______ operation is aborted when the nmi or watchdog timer interrupt occurs. set the fmr01 bit to 1 and execute the rewrite and erase program again after exiting the interrupt routine. ? the address match interrupt can not be used since the cpu tries to read data in the flash memory. ew mode 1 ? do not acknowledge any interrupts with vectors in the relocatable vector table or the address match interrupt during the auto program period or auto erase period with erase-suspend function disabled. 19.6.4 how to access to set bit fmr01, fmr02, fmr11 or fmr16 to 1, write 1 immediately after setting to 0. do not generate an interrupt or a dma transfer between the instruction to set the bit to 0 and the instruction to set it to 1. _______ _______ _____ when the nmi function is selected, set the bit while an ? h ? signal is applied to the p8 5 /nmi/sd pin. 19.6.5 writing in the user rom area 19.6.5.1 ew mode 0 ? if the supply voltage drops while rewriting the block where the rewrite control program is stored, the flash memory can not be rewritten, because the rewrite control program is not correctly rewrit- ten. if this error occurs, rewrite the user rom area in standard serial i/o mode or parallel i/o mode. 19.6.5.2 ew mode 1 ? do not rewrite the block where the rewrite control program is stored.
19. flash memory version page 307 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 19.6.6 dma transfer in ew mode 1, do not generate a dma transfer while the fmr00 bit in the fmr0 register is set to 0. (during the auto-programming or auto-erasing). 19.6.7 writing command and data write the command codes and data to even addresses in the user rom area. 19.6.8 wait mode when entering wait mode, set the fmr01 bit to 0 (cpu rewrite mode disabled) before executing the wait instruction. 19.6.9 stop mode when entering stop mode, the following settings are required: ? set the fmr01 bit to 0 (cpu rewrite mode disabled) and disable the dma transfer before setting the cm10 bit to 1 (stop mode). 19.6.10 low power consumption mode and on-chip oscillator-low power consumption mode if the cm05 bit is set to 1 (main clock stopped), do not execute the following commands. ? program ? block erase
19. flash memory version page 308 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m command program clear status register read array read status register first bus cycle second bus cycle block erase write write write write write mode read write write mode x wa ba address srd wd xxd0 16 data (d 15 to d 0 ) xxff 16 xx70 16 xx50 16 xx40 16 xx20 16 data (d 15 to d 0 ) x x x wa x address srd: status register data (d 7 to d 0 ) wa : write address (however,even address) wd : write data (16 bits) ba : highest-order block address (however,even address) x : any even address in the user rom area xx : 8 high-order bits of command code (ignored) 19.7 software commands read or write 16-bit commands and data from or to even addresses in the user rom area. when writing a command code, 8 high-order bits (d 15 ? d 8 ) are ignored. table 19.5 software commands 19.7.1 read array command (ff 16 ) the read array command reads the flash memory. read array mode is entered by writing command code xxff 16 in the first bus cycle. content of a speci- fied address can be read in 16-bit unit after the next bus cycle. the mcu remains in read array mode until an another command is written. therefore, contents of multiple addresses can be read consecutively. 19.7.2 read status register command (70 16 ) the read status register command reads the status register. by writing command code xx70 16 in the first bus cycle, the status register can be read in the second bus cycle (refer to 19.8 status register ). read an even address in the user rom area. do not execute this command in ew mode 1. 19.7.3 clear status register command (50 16 ) the clear status register command clears the status register to 0. by writing xx50 16 in the first bus cycle, and bits fmr06 to fmr07 in the fmr0 register and bits sr4 to sr5 in the status register are set to 0.
19. flash memory version page 309 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 19.7.4 program command (40 16 ) the program command writes 2-byte data to the flash memory. auto program operation (data program and verify) start by writing xx40 16 in the first bus cycle and data to the write address specified in the second bus cycle. the address value specified in the first bus cycle must be the same even address as the write address secified in the second bus cycle. the fmr00 bit in the fmr0 register indicates whether an auto-programming operation has been com- pleted. the fmr00 bit is set to 0 during the auto-program and 1 when the auto-program operation is completed. after the completion of auto-program operation, the fmr06 bit in the fmr0 register indicates whether or not the auto-program operation has been successfully completed. (refer to 19.8.4 full status check ). also, each block can disable programming command (refer to table 19.4 ). an address that is already written cannot be altered or rewritten. when commands other than the program command are executed immediately after executing the pro- gram command, set the same address as the write address specified in the second bus cycle of the program command, to the specified address value in the first bus cycle of the following command. in ew mode 1, do not execute this command on the blocks where the rewrite control program is allo- cated. in ew mode 0, the mcu enters read status register mode as soon as the auto-program operation starts and the status register can be read. the sr7 bit in the status register is set to 0 as soon as the auto- program operation starts. this bit is set to 1 when the auto-program operation is completed. the mcu remains in read status register mode until the read array command is written. after completion of the auto-program operation, the status register indicates whether or not the auto-program operation has been successfully completed. figure 19.10 flow chart of program command start program completed yes no notes: 1. write the command code and data at even address. 2. refer to figure 19.13 . write command code xx40 16 to the write address (1 ) write data to the write address (1) fmr00=1? full status check (2)
19. flash memory version page 310 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 19.7.5 block erase auto erase operation (erase and verify) start in the specified block by writing xx20 16 in the first bus cycle and xxd0 16 to the highest-order even addresse of a block in the second bus cycle. the fmr00 bit in the fmr0 register indicates whether the auto-erase operation has been completed. the fmr00 bit is set to 0 (busy) during the auto-erase and 1 (ready) when the auto-erase operation is completed. when using the erase-suspend function in ew mode 0, verify whether a flash memory has entered erase suspend mode, by the fmr46 bit in the fmr4 register. the fmr46 bit is set to 0 during auto-erase operation and 1 when the auto-erase operation is completed (entering erase-suspend). after the completion of an auto-erase operation, the fmr07 bit in the fmr0 register indicates whether or not the auto-erase operation has been successfully completed. (refer to 19.8.4 full status check ). also, each block can disable erasing. (refer to table 19.4 ). figure 19.11 shows a flow chart of the block erase command programming when not using the erase- suspend function. figure 19.12 shows a flow chart of the block erase command programming when using an erase-suspend function. in ew mode 1, do not execute this command on the block where the rewrite control program is allocated. in ew mode 0, the mcu enters read status register mode as soon as the auto-erase operation starts and the status register can be read. the sr7 bit in the status register is set to 0 at the same time the auto- erase operation starts. this bit is set to 1 when the auto-erase operation is completed. the mcu remains in read status register mode until the read array command is written. when the erase error occurs, execute the clear status register command and block erase command at leaset three times until an erase error does not occur. figure 19.11 flow chart of block erase command (when not using erase suspend function) write xxd0 16 to the highest-order block address (1) start block erase completed yes no write command code xx20 16 (1) fmr00 = 1? full status check (2,3) notes: 1. write the command code and data at even address. 2. refer to figure 19.13 . 3. execute the clear status register command and block erase command at least 3 times until an erase error is not generated when an erase error is generated.
19. flash memory version page 311 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 19.12 block erase command (at use erase suspend) start block erase completed write the command code xx20 16 (1) write xxd0 16 to the highest-order block address (1 ) yes no fmr00=1? full status check (2,4 ) fmr40=1 interrupt service routine (3 ) fmr41=1 yes no fmr46=1? access flash memory return (interrupt service routine end) fmr41=0 (ew mode 0) (ew mode 1) start block erase completed write the command code xx20 16 (1) write xxd0 16 to the highest-order block address (1 ) yes no fmr00=1? full status check (2,4 ) fmr40=1 fmr41=0 interrupt service routine access flash memory return (interrupt service routine end) notes: 1. write the command code and data to even address. 2. execute the clear status register command and block erase command at least 3 times until an erase error is not generated when an erase error is occured. 3. in ew mode 0, allocate an interrupt vector table of an interrupt, to be used, to the ram area. 4. refer to figure 19.13 .
19. flash memory version page 312 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 19.8 status register the status register indicates the operating status of the flash memory and whether or not erase or pro- gram operation is successfully completed. bits fmr00, fmr06, and fmr07 in the fmr0 register indi- cate the status of the status register. table 19.6 lists the status register. in ew mode 0, the status register can be read in the following cases: (1) any even address in the user rom area is read after writing the read status register command (2) any even address in the user rom area is read from when the program or block erase command is executed until when the read array command is executed. 19.8.1 sequence status (sr7 and fmr00 bits ) the sequence status indicates the flash memory operating status. it is set to 0 (busy) while the auto- program and auto-erase operation is being executed and 1 (ready) as soon as these operations are completed. this bit indicates 0 (busy) in erase-suspend mode. 19.8.2 erase status (sr5 and fmr07 bits) refer to 19.8.4 full status check . 19.8.3 program status (sr4 and fmr06 bits) refer to 19.8.4 full status check . table 19.6 status register ? d 7 to d 0 : indicates the data bus which is read out when executing the read status register command. ? the fmr07 bit (sr5) and fmr06 bit (sr4) are set to 0 by executing the clear status register command. ? when the fmr07 bit (sr5) or fmr06 bit (sr4) is set to 1, the program and block erase command are not accepted. bits in the srd register sr4 (d 4 ) sr5 (d 5 ) sr7 (d 7 ) sr6 (d 6 ) status name contents sr1 (d 1 ) sr2 (d 2 ) sr3 (d 3 ) sr0 (d 0 ) program status erase status sequence status reserved reserved reserved reserved 1 ready terminated by error terminated by error - - - - - 0 busy completed normally completed normally - - - - - reserved bits in the fmr0 register fmr00 fmr07 fmr06 value after reset 1 0 0
19. flash memory version page 313 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 19.8.4 full status check if an error occurs, bits fmr06 to fmr07 in the fmr0 register are set to 1, indicating a specific error. therefore, execution results can be comfirmed by verifying these status bits (full status check). table 19.7 lists errors and fmr0 register state. figure 19.13 shows a flow chart of the full status check and handling procedure for each error. table 19.7 errors and fmr0 register status fmr0 register (srd register) status error error occurrence condition fmr07 fmr06 (sr5) (sr4) 1 1 command ? an incorrect commands is written sequence error ? a value other than xxd0 16 or xxff 16 is written in the second bus cycle of the block erase command (1) ? when the block erase command is executed on an protected block ? when the program command is executed on protected blocks 1 0 erase error ? the block erase command is executed on an unprotected block but the program operation is not successfully completed 0 1 program error ? the program command is executed on an unprotected block but the program operation is not successfully completed note: 1. the flash memory enters read array mode by writing command code xxff 16 in the second bus cycle of these commands. the command code written in the first bus cycle becomes invalid.
19. flash memory version page 314 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m figure 19.13 full status check and handling procedure for each error full status check fmr06 =1 and fmr07=1? no command sequence error yes fmr07=0? yes erase error no (1) execute the clear status register command and set the status flag to 0 whether the command is entered. (2) execute the command again after checking that the correct command is entered or the program command or the block erase command is not executed on the protected blocks. (1) execute the clear status register command and set the erase status flag to 0. (2) execute the block erase command again. (3) execute (1) and (2) at least 3 times until an erase error does not occur. note 3: if bits fmr06 or fmr07 is 1, any of the program or block erase command cannot be accepted. execute the clear status register command before executing those commands. fmr06=0? yes program error no full status check completed note 1: if the error still occurs, the block can not be used. (1) execute the clear status register command and set the program status flag to 0. (2) execute the program command again. note 2: if the error still occurs, the block can not be used. [during programming]
19. flash memory version page 315 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 19.9 standard serial i/o mode in standard serial i/o mode, the serial programmer supporting the m16c/28 group (t-ver./v-ver.) can be used to rewrite the flash memory user rom area, while the mcu is mounted on a board. for more informa- tion about the serial programmer, contact your serial programmer manufacturer. refer to the user ? s manual included with your serial programmer for instruction. table 19.8 lists pin description (flash memory standard serial input/output mode). figures 19.14 and 19.15 show pin connections for standard serial input/output mode. 19.9.1 id code check function the id code check function determines whether or not the id codes sent from the serial programmer matches those written in the flash memory. (refer to 19.3 functions to prevent flash memory from rewriting .)
19. flash memory version page 316 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m table 19.8 pin descriptions (flash memory standard serial i/o mode) notes: ___________ 1. when using standard serial i/o mode 1, to input ? h ? to the txd pin is necessary while the reset pin is held ? l ? . therefore, connect this pin to v cc via a resistor. adjust the pull-up resistor value on a system not to affect a data transfer after reset, because this pin changes to a data-output pin 2. set the following, either or both. _____ -connect the ce pin to v cc . _____ -connect the rp pin to vss and p1 6 pin to v cc . pin descriptio n v cc ,v ss apply the voltage guaranteed for program and erase to vcc pin and 0 v to vss pin. cnv ss connect to vcc pin. reset x in connect a ceramic resonator or crystal oscillator between x in and x out pins. to input an externally generated clock, input it to x in pin and open x out pin. x out av cc , av ss v ref connect avss to vss and avcc to vcc, respectively. enter the reference voltage for ad conversion. p0 0 to p0 7 input "h" or "l" level signal or leave open. p1 0 to p1 5 , p1 7 input "h" or "l" level signal or leave open. p3 0 to p3 7 input "h" or "l" level signal or leave open. p6 0 to p6 3 input "h" or "l" level signal or leave open. p6 4 standard serial i/o mode 1: busy signal output pin standard serial i/o mode 2: monitor signal output pin for boot program operation check p6 5 p6 6 serial data input pin p6 7 serial data output pin p7 0 to p7 7 input "h" or "l" level signal or leave open. p8 0 to p8 4 , p8 7 input "h" or "l" level signal or leave open. p9 0 to p9 3 , p9 5 to p9 7 input "h" or "l" level signal or leave open. name power input cnv s s reset input clock input clock output analog power supply input reference voltage input input port p0 input port p1 input port p3 input port p6 busy output sclk input rxd input txd output input port p7 input port p8 input port p9 i/o i i i o i i i i i o i i o i i i p8 5 rp input i connect this pin to vss while reset pin is ? l ? . (note 2) standard serial i/o mode 1: serial clock input pin standard serial i/o mode 2: input "l". reset input pin. while reset pin is "l" level, wait for td(roc). (note 1) p2 0 to p2 7 input port p2 input "h" or "l" level signal or leave open. i p8 6 ce input i connect this pin to vcc while reset pin is ? l ? . (note 2) p1 6 input port p1 i connect this pin to vcc while reset pin is ? l ? . (note 2) p10 0 to p10 7 input "h" or "l" level signal or leave open. input port p10 i
19. flash memory version page 317 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 21 2 2 23 24 2 5 26 27 2 8 29 30 31 32 33 34 35 36 37 38 39 40 6 0 5 9 58 57 5 6 5 5 54 53 52 51 50 49 48 47 46 45 44 43 42 41 6 4 63 62 61 17 18 19 2 0 busy sclk rxd txd vcc vss reset connect oscillator circuit ce (1) notes: 1. set the following, either or both, in serial i/o mode, while the reset pin is applied a low-level ("l") signal. -connect the ce pin to vcc. -connect the rp pin to vss and the p16 pin to vcc. rp (1) p1 6 (1) mode setup method signal cnvss reset p1 6 ce rp value vcc vss to vcc vcc (note) vcc (note) vss (note) m16c/28 group (t-ver./v-ver.) (64-pin package) (flash memory version) (plqp0064kb-a (64p6q-a)) figure 19.14 pin connections for serial i/o mode (1)
19. flash memory version page 318 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2 1 2 2 23 24 2 5 2 6 2 7 28 29 3 0 31 3 2 3 3 3 4 35 36 37 3 8 3 9 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 8 0 79 78 7 7 7 6 7 5 7 4 73 7 2 7 1 70 6 9 68 6 7 6 6 6 5 64 6 3 62 61 busy sclk rxd txd connect oscillator circuit vcc vss reset ce (1) rp (1) notes: 1. set the following, either or both, in serial i/o mode, while the reset pin is applied a low-level ("l") signal. -connect the ce pin to vcc. -connect the rp pin to vss and the p16 pin to vcc. p1 6 (1) mode setup method signal cnvss reset p1 6 ce rp value vcc vss to vcc vcc (note) vcc (note) vss (note) m16c/28 group (t-ver./v-ver.) (80-pin package) (flash memory version) (plqp0080kb-a (80p6q-a)) figure 19.15 pin connections for serial i/o mode (2)
19. flash memory version page 319 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m sclk input busy output txd output rxd input busy sclk t x d cnvss p8 6 (ce) reset rxd reset input user reset singnal mcu (1) controlling pins and external circuits vary with the serial programmer. for more information, refer to the user's manual included with the serial programmer. (2) in this example, a selector controls the input voltage applied to cnvss to switch between single-chip mode and standard serial i/o mode. (3) in standard serial input/output mode 1, if the user reset signal becomes ? l ? while the mcu is communicating with the serial programmer, break the connection between the user reset signal and the reset pin using a jumper switch. p8 5 (rp) (1) (1) note: 1. set the following, either or both. - connect the ce pin to vcc - connect the rp pin to vss and the p1 6 pin to vcc (1) p1 6 19.9.2 example of circuit application in standard serial i/o mode figure 19.16 shows an example of a circuit application in standard serial i/o mode 1 and figure 19.17 shows an example of a circuit application in standard serial i/o mode 2. refer to the user's manual of your serial programmer to handle pins controlled by the serial programmer. figure 19.16 circuit application in standard serial i/o mode 1
19. flash memory version page 320 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m monitor output rxd input txd output busy sclk txd cnvss p8 6 (ce) rxd mcu (1) in this example, a selector controls the input voltage applied to cnvss to switch between single-chip mode and standard serial i/o mode. p8 5 (rp) (1) (1) note: 1. set the following, either or both. - connect the ce pin to vcc - connect the rp pin to vss and the p1 6 pin to vcc p1 6 (1) figure 19.17 circuit application in standard serial i/o mode 2
19. flash memory version page 321 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 19.10 parallel i/o mode in parallel input/output mode, the user rom can be rewritten by a parallel programmer supporting the m16c/28 group (t-ver./v-ver.). contact your parallel programmer manufacturer for more information on the parallel programmer. refer to the user ? s manual included with your parallel programmer for instruc- tions. 19.10.1 rom code protect function the rom code protect function prevents the flash memory from being read or rewritten. (refer to 19.3 functions to prevent flash memory from rewriting ).
20. electrical characteristics (t-version) page 322 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r l o b m y sr e t e m a r a pn o i t i d n o ce u l a vt i n u v c c e g a t l o v y l p p u sv c c v a = c c 5 . 6 o t 3 . 0 - v v a c c e g a t l o v y l p p u s g o l a n av c c v a = c c 5 . 6 o t 3 . 0 - v v i e g a t l o v t u p n i0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 , 3 p 0 3 p o t 7 6 p , 0 6 p o t 7 7 p , 0 7 p o t 7 , 8 p 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 , 0 1 p 0 0 1 p o t 7 , x n i v , f e r v n c , t e s e r , s s v o t 3 . 0 - c c 3 . 0 +v v o e g a t l o v t u p t u o0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 , 3 p 0 3 p o t 7 6 p , 0 6 p o t 7 7 p , 0 7 p o t 7 , 8 p 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 , 0 1 p 0 0 1 p o t 7 , x t u o v o t 3 . 0 - c c 3 . 0 +v d pn o i t a p i s s i d r e w o p0 4 -< r p o t< c 5 80 0 3w m r p o t g n i t a r e p o t n e i b m a e r u t a r e p m e t n o i t a r e p o u p c g n i r u d 5 8 o t 0 4 -c y r o m e m h s a l f g n i r u d e s a r e d n a m a r g o r p n o i t a r e p o e c a p s m a r g o r p ) 4 k c o l b o t 0 k c o l b ( 0 6 o t 0c e c a p s a t a d ) b k c o l b , a k c o l b ( 5 8 o t 0 4 -c g t s te r u t a r e p m e t e g a r o t s 0 5 1 o t 5 6 -c 20. electrical characteristics 20.1 t version table 20.1 absolute maximum ratings
20. electrical characteristics (t-version) page 323 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. p y t. x a m v c c e g a t l o v y l p p u s 0 . 35 . 5v v a c c e g a t l o v y l p p u s g o l a n a v c c v v s s e g a t l o v y l p p u s 0v v a s s e g a t l o v y l p p u s g o l a n a 0v v h i ) " h " ( h g i h t u p n i e g a t l o v 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 v 7 . 0 c c v c c v s s v n c , t e s e r , n i x v 8 . 0 c c v c c v a d s m m l c s , m m i n e h w 2 d e t c e l e s s i l e v e l t u p n i s u b c v 7 . 0 c c v c c v d e t c e l e s s i l e v e l t u p n i s u b m s n e h w4 . 1v c c v v l i ) " l " ( w o l t u p n i e g a t l o v 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 0v 3 . 0 c c v s s v n c , t e s e r , n i x 0v 2 . 0 c c v a d s m m l c s , m m i n e h w 2 d e t c e l e s s i l e v e l t u p n i s u b c 0 3 . 0v c c v d e t c e l e s s i l e v e l t u p n i s u b m s n e h w06 . 0v i ) k a e p ( h o h g i h t u p t u o k a e p t n e r r u c ) " h " ( 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 0 . 0 1 -a m i ) g v a ( h o t u p t u o e g a r e v a t n e r r u c ) " h " ( h g i h 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 0 . 5 -a m i ) k a e p ( l o w o l t u p t u o k a e p t n e r r u c ) " l " ( 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 0 . 0 1a m i ) g v a ( l o t u p t u o e g a r e v a t n e r r u c ) " l " ( w o l 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 0 . 5a m x ( f n i )y c n e u q e r f t u p n i k c o l c n i a m ) 4 ( 00 2z h m x ( f n i c )y c n e u q e r f k c o l c b u s 8 6 7 . 2 30 5z h k f 1 ) c o r (1 y c n e u q e r f r o t a l l i c s o p i h c - n o 5 . 012z h m ) c o r ( 2 f2 y c n e u q e r f r o t a l l i c s o p i h c - n o 12 4 z h m ) c o r ( 3 f3 y c n e u q e r f r o t a l l i c s o p i h c - n o 86 16 2z h m ) l l p ( fy c n e u q e r f k c o l c l l p ) 4 ( 0 10 2z h m ) k l c b ( fy c n e u q e r f k c o l c n o i t a r e p o u p c 00 2s m t u s ) l l p (r e z i s e h t n y s y c n e u q e r f l l p e z i l i b a t s o t e m i t t i a w v c c v 0 . 5 =0 2s m v c c v 0 . 3 =0 5s m : s e t o n v o t d e c n e r e f e r . 1 c c . d e i f i c e p s e s i w r e h t o s s e l n u c 5 8 o t 0 4 - = r p o t t a v 5 . 5 o t 0 . 3 = . s m 0 0 1 n i h t i w e u l a v n a e m e h t s i t n e r r u c t u p t u o n a e m e h t . 2 i l a t o t e h t . 3 ) k a e p ( l o i l a t o t e h t . s s e l r o a m 0 8 e b t s u m s t r o p l l a r o f ) k a e p ( h o . s s e l r o a m 0 8 - e b t s u m s t r o p l l a r o f . e g a t l o v y l p p u s d n a y c n e u q e r f n o i t a l l i c s o k c o l c l l p , y c n e u q e r f n o i t a l l i c s o k c o l c n i a m g n o m a p i h s n o i t a l e r . 4 table 20.2 recommended operating conditions (1) main clock input oscillation frequency f(x in ) operating maximum frequency [mh z ] v cc [v] (main clock: no division) pll clock oscillation frequency f(pll) operating maximum frequency [mh z ] v cc [v] (pll clock oscillation) 20.0 0.0 5.5 3.0 10.0 20.0 mh z 20.0 0.0 5.5 10.0 3.0 20.0 mh z aaaa a aa a a aa a a aa a a aa a a aa a aaaa aaaaa a aaa a a aaa a aaaaa
20. electrical characteristics (t-version) page 324 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r table 20.3 a/d conversion characteristics (1) l o b m y sr e t e m a r a pn o i t i d n o c t n e m e r u s a e m d r a d n a t s t i n u . n i m. p y t. x a m -n o i t u l o s e rv f e r v = c c 0 1s t i b l n i y t i r a e n i l n o n l a r g e t n i r o r r e t i b 0 1 v f e r v = c c v 5 =3 b s l v f e r v = c c v 3 . 3 =5 b s l t i b 8v f e r v = c c v 3 . 3 =2 b s l -y c a r u c c a e t u l o s b a t i b 0 1 v f e r v = c c v 5 =3 b s l v f e r v = c c v 3 . 3 =5 b s l t i b 8v f e r v = c c v 3 . 3 =2 b s l l n dr o r r e y t i r a e n i l n o n l a i t n e r e f f i d 1 b s l -r o r r e t e s f f o 3 b s l -r o r r e n i a g 3 b s l r r e d d a l r e d d a l r o t s i s e rv = f e r v c c 0 10 4k ? t v n o c e m i t n o i s r e v n o c t i b - 0 1 e l b a l i a v a n o i t c n u f d l o h & e l p m a s v f e r v = c c z h m 0 1 = d a ? , v 5 =3 . 3 s t v n o c e m i t n o i s r e v n o c t i b - 8 e l b a l i a v a n o i t c n u f d l o h & e l p m a s v f e r v = c c z h m 0 1 = d a ? , v 5 =8 . 2 s v f e r e g a t l o v e c n e r e f e r 0 . 2v c c v v a i e g a t l o v t u p n i g o l a n a 0v f e r v : s e t o n v o t d e c n e r e f e r . 1 c c v a = c c v = f e r v , v 5 . 5 o t 3 . 3 = s s v a = s s e s i w r e h t o s s e l n u c 5 8 o t 0 4 - = r p o t t a v 0 = . d e i f i c e p s p e e k . 2 f e h t e d i v i d , y l l a n o i t i d d a . s s e l r o z h m 0 1 t a y c n e u q e r f d a d a v f i c c e k a m d n a , v 2 . 4 n a h t s s e l s i d a f n a h t r e w o l r o o t l a u q e y c n e u q e r f d a . 2 / . 3p e e k , d e l b a s i d s i n o i t c n u f d l o h & e l p m a s n e h w . 2 e t o n n i n o i t a t i m i l e h t o t n o i t i d d a n i e r o m r o z h k 0 5 2 t a y c n e u q e r f d a p e e k , d e l b a n e s i n o i t c n u f d l o h & e l p m a s n e h w . 2 e t o n n i n o i t a t i m i l e h t o t n o i t i d d a n i e r o m r o z h m 1 t a y c n e u q e r f d a / 3 s i e m i t g n i l p m a s , d e l b a n e s i n o i t c n u f d l o h & e l p m a s n e h w . 4 . y c n e u q e r f d a / 2 s i e m i t g n i l p m a s , d e l b a s i d s i n o i t c n u f d l o h & e l p m a s n e h w . y c n e u q e r f d a
20. electrical characteristics (t-version) page 325 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. p y t ) 2 ( . x a m - e c n a r u d n e e s a r e d n a m a r g o r p ) 9 , 8 , 3 ( 0 0 0 0 1 ) 0 1 , 4 ( s e l c y c -v ( e m i t m a r g o r p d r o w c c 5 2 = r p o t , v 0 . 5 =c )0 0 1 s - e m i t e s a r e k c o l bv ( c c 5 2 = r p o t , v 0 . 5 =c ) ) k c o l b e t y b k - 2 ( 3 . 0s ) s e - r s ( d td n e p s u s e s a r e d n a t s e u q e r d n e p s u s n e e w t e b n o i t a r u d 8s m t s p t i u c r i c y r o m e m h s a l f e z i l i b a t s o t e m i t t i a w 5 1 s -e m i t d l o h a t a d ) 5 ( 0 2s r a e y : s e t o n 0 6 o t 0 = r p o t t a v 5 . 5 o t 0 . 3 = c c v o t d e c n e r e f e r . 1 s s e l n u , ) e c a p s a t a d ( c 5 8 o t 0 4 - = r p o t / ) e c a p s m a r g o r p ( c . d e i f i c e p s e s i w r e h t o c 5 2 = r p o t ; v 5 = c c v . 2 . k c o l b r e p s e l c y c e s a r e - m a r g o r p f o r e b m u n s a d e n i f e d s i e c n a r u d n e e s a r e d n a m a r g o r p . 3 s i e c n a r u d n e e s a r e d n a m a r g o r p f i n ( e l c y c n d e m m a r g o r p d n a d e s a r e e b n a c k c o l b h c a e , ) 0 0 0 0 1 , 0 0 0 1 , 0 0 1 = n . s e l c y c , s e m i t 4 2 0 , 1 s s e r d d a h c a e o t a t a d d r o w - e n o g n i m m a r g o r p r e t f a d e s a r e s i a k c o l b e t y b k - 2 a f i , e l p m a x e r o f n a h t e r o m s s e r d d a e m a s e h t o t d e m m a r g o r p e b t o n n a c a t a d . e c n a r u d n e e s a r e d n a m a r g o r p e n o s a s t n u o c s i h t . ) d e t i b i h o r p e t i r w e r ( . k c o l b e h t g n i s a r e t u o h t i w e c n o . ) d e e t n a r a u g e r a e u l a v m u m i n i m o t 1 ( d e e t n a r u g s i n o i t a r e p o h c i h w r o f s e l c y c w / e f o r e b m u n . 4 c 5 5 = r p o t . 5 . d e i f i c e p s e s i w r e h t o s s e l n u c 5 8 o t 0 4 - = r p o t t a v 5 . 5 o t 0 . 3 = c c v o t d e c n e r e f e r . 6 . 7 5 . 0 2 e l b a t . s e l c y c 0 0 0 , 1 n a h t e r o m s i e c n a r u d n e e s a r e d n a m a r g o r p n e h w 7 u d n a 7 b n i e c a p s a t a d r o f s e i l p p a e s u , e s i w r e h t o 4 . 0 2 e l b a t . , s e t i r w e r s u o r e m u n g n i r i u q e r s m e t s y s h t i w g n i k r o w n e h w e c n a r u d n e e s a r e d n a m a r g o r p f o r e b m u n e h t e c u d e r o t . 8 s e s s e r d d a e l b i s s o p l l a r e t f a y l n o k c o l b e s a r e . e t i r w e r f o d a e t s n i k c o l b e h t n i h t i w s e s s e r d d a d r o w d e s u n u o t e t i r w . y r a s s e c e n s e m o c e b e s a r e e r o f e b m u m i x a m s e m i t 8 2 1 n e t t i r w e b n a c m a r g o r p d r o w - 8 n a , e l p m a x e r o f . d e s u e r a s i t i . y c n e i c i f f e e v o r p m i o s l a l l i w b k c o l b d n a a k c o l b n e e w t e b e r u s a r e s e m i t f o r e b m u n l a u q e n a g n i n i a t n i a m . e r u s a r e f o r e b m u n e h t t i m i l o t d n a k c o l b r e p d e m r o f r e p e r u s a r e f o r e b m u n l a t o t e h t k c a r t o t d e d n e m m o c e r d n a m m o c e s a r e k c o l c d n a d n a m m o c r e t s i g e r s u t a t s r a e l c m r o f r e p , e s a r e k c o l b g n i r u d d e r u c c o e r a s r o r r e e s a r e f i . 9 . r a e p p a s i d s r o r r e e s a r e l i t n u , s e m i t e e r h t t s a e l t a , r e d r o l a i t n e u q e s n i n i t i b 7 1 r m f e h t g n i t t e s y b s s e c c a k c o l b r e p e t a t s t i a w e n o t e s , s e t i r w e r s e m i t 0 0 1 n a h t e r o m g n i t u c e x e n e h w . 0 1 t e s e b n a c e t a t s t i a w , m a r l a n r e t n i d n a s k c o l b r e h t o l l a o t g n i s s e c c a n e h w . ) e t a t s t i a w ( 1 o t r e t s i g e r 1 r m f e h t . e u l a v g n i t t e s t i b 7 1 r m f e h t f o s s e l d r a g e r , t i b 7 1 m p e h t y b s e l c y c 0 0 0 , 1 ; 3 u n i e c a p s a t a d d n a e c a p s m a r g o r p r o f s e l c y c 0 0 1 s i e c n a r u d n e e s a r e d n a m a r g o r p e h t . 1 1 . 7 u n i e c a p s m a r g o r p r o f . e v i t a t n e s e r p e r t r o p p u s l a c i n h c e t s a s e n e r r i e h t t c a t n o c d l u o h s n o i t a m r o f n i e t a r e r u l i a f w / e g n i r i s e d s r e m o t s u c . 2 1 table 20.4 flash memory version electrical characteristics (1) for 100/1000 e/w cycle products [program space and data space in u3; program space in u7] table 20.5 flash memory version electrical characteristics (6) for 10000 e/w cycle products [data space in u7 (7) ] erase suspend request (interrupt request) fmr46 td(sr-es) l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. p y t ) 2 ( . x a m - e c n a r u d n e e s a r e d n a m a r g o r p ) 3 ( 0 0 0 1 / 0 0 1 ) 1 1 , 4 ( s e l c y c -v ( e m i t m a r g o r p d r o w c c 5 2 = r p o t , v 0 . 5 =c )5 70 0 6 s -e m i t e s a r e k c o l b v ( c c 5 2 = r p o t , v 0 . 5 =c ) k c o l b e t y b k - 2 2 . 09s k c o l b e t y b k - 8 4 . 09s k c o l b e t y b k - 6 1 7 . 09s k c o l b e t y b k - 2 3 2 . 19s ) s e - r s ( d td n e p s u s e s a r e d n a t s e u q e r d n e p s u s n e e w t e b n o i t a r u d 8s m t s p t i u c r i c y r o m e m h s a l f e z i l i b a t s o t e m i t t i a w 5 1 s -e m i t d l o h a t a d ) 5 ( 0 2s r a e y
20. electrical characteristics (t-version) page 326 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r table 20.6 power supply circuit timing characteristics l o b m y sr e t e m a r a pn o i t i d n o c t n e m e r u s a e m d r a d n a t s t i n u . n i m. p y t. x a m ) r - p ( d t n e h w e g a t l o v y l p p u s l a n r e t n i e z i l i b a t s o t e m i t t i a w n o - r e w o p v c c v 5 . 5 o t 0 . 3 = 2s m ) c o r ( d t n e h w r o t a l l i c s o p i h c - n o l a n r e t n i e z i l i b a t s o t e m i t t i a w n o - r e w o p 0 4 s ) s - r ( d te m i t e s a e l e r p o t s 0 5 1 s ) s - w ( d t e s a e l e r e d o m t i a w e d o m n o i t a p i s s i d r e w o p w o l e m i t 0 5 1 s t d(p-r) wait time to stabilize internal supply voltage when power-on cpu clock t d(r-s ) (a) (b) t d(w-s) t d(r-s) stop release time t d(w-s) low power dissipation mode wait mode release tim e interrupt for (a) stop mode release or (b) wait mode release t d(roc) wait time to stabilize internal on-chip oscillator when power- on roc reset vcc td(p-r) td(roc )
20. electrical characteristics (t-version) page 327 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r v cc = 5v table 20.7 electrical characteristics (1) l o b m y sr e t e m a r a pn o i t i d n o c d r a d n a t s t i n u . n i m. p y t. x a m v h o h g i h t u p t u o e g a t l o v ) " h " ( 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 i h o a m 5 - = v c c - 0 . 2 v c c v v h o h g i h t u p t u o e g a t l o v ) " h " ( 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 i h o 0 0 2 - = a v c c - 3 . 0 v c c v v h o e g a t l o v ) " h " ( h g i h t u p t u ox t u o r e w o p h g i h i h o a m 1 - = v c c - 0 . 2 v c c v r e w o p w o l i h o a m 5 . 0 - = v c c - 0 . 2 v c c e g a t l o v ) " h " ( h g i h t u p t u ox t u o c r e w o p h g i h d e i l p p a d a o l o n5 . 2 v r e w o p w o l d e i l p p a d a o l o n6 . 1 v l o w o l t u p t u o e g a t l o v ) " l " ( 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 i l o a m 5 =0 . 2v v l o w o l t u p t u o e g a t l o v ) " l " ( 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 i l o 0 0 2 = a5 4 . 0v v l o e g a t l o v ) " l " ( w o l t u p t u ox t u o r e w o p h g i h i l o a m 1 =0 . 2 v r e w o p w o l i l o a m 5 . 0 =0 . 2 e g a t l o v ) " l " ( w o l t u p t u ox t u o c r e w o p h g i h d e i l p p a d a o l o n0 v r e w o p w o l d e i l p p a d a o l o n0 v + t v - - t s i s e r e t s y h 0 a t n i 4 a t - n i 0 b t , n i 2 b t - n i t n i , 0 t n i - 5 d a , i m n , g r t s t c , 0 - s t c 2 k l c , a d s , l c s , 0 k l c - 2 2 a t , t u o 4 a t - t u o i k , 0 i k - 3 r , 0 d x - r 2 d x s , 3 n i s , 4 n i 2 . 00 . 1v v + t v - - t s i s e r e t s y h t e s e r 2 . 05 . 2v v + t v - - t s i s e r e t s y h x n i 2 . 08 . 0 v i h i h g i h t u p n i t n e r r u c ) " h " ( 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 x n i v n c , t e s e r , s s v i v 5 =0 . 5 a i l i w o l t u p n i t n e r r u c ) " l " ( 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 x n i v n c , t e s e r , s s v i v 0 =0 . 5 - a r p u l l u p p u - l l u p e c n a t s i s e r 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 v i v 0 =0 30 50 7 1k ? f r n i x e c n a t s i s e r k c a b d e e fx n i 5 . 1m ? f r n i c x e c n a t s i s e r k c a b d e e fx n i c 5 1m ? v m a r e g a t l o v y b d n a t s m a r e d o m p o t s n i0 . 2v : e t o n o t d e c n e r e f e r . 1v c c v , v 5 . 5 o t 2 . 4 = s s . d e i f i c e p s e s i w r e h t o s s e l n u z h m 0 2 = ) k l c b ( f , c 5 8 o t 0 4 - = r p o t t a v 0 =
20. electrical characteristics (t-version) page 328 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r v cc = 5v table 20.8 electrical characteristics (2) (1) l o b m y sr e t e m a r a pn o i t i d n o c t n e m e r u s a e m d r a d n a t s t i n u . n i m. p y t. x a m i c c y l p p u s r e w o p t n e r r u c v ( c c ) v 5 . 5 o t 2 . 4 = e r a s n i p t u p t u o d n a n e p o t f e l e r a s n i p r e h t o v o t d e t c e n n o c s s m o r k s a m, z h m 0 2 = ) k l c b ( f n o i s i v i d o n , k c o l c n i a m 8 15 2a m n o i t a l l i c s o p i h c - n o f ) c o r ( 2 z h m 1 = ) k l c b ( f , d e t c e l e s 2a m y r o m e m h s a l f, z h m 0 2 = ) k l c b ( f n o i s i v i d o n , k c o l c n i a m 8 15 2a m f , n o i t a l l i c s o p i h c - n o ) c o r ( 2 , d e t c e l e s z h m 1 = ) k l c b ( f 2a m y r o m e m h s a l f m a r g o r p v 0 . 5 = c c v , z h m 0 1 = ) k l c b ( f 1 1a m y r o m e m h s a l f e s a r e v 0 . 5 = c c v , z h m 0 1 = ) k l c b ( f 1 1a m m o r k s a mx ( f n i c , z h k 2 3 = ) , e d o m n o i t p m u s n o c r e w o p - w o l n i m o r n o g n i n n u r m a r g o r p ) 3 ( 5 2 a n o i t a l l i c s o p i h c - n o f ) c o r ( 2 , z h m 1 = ) k l c b ( f , d e t c e l e s e d o m t i a w n i 0 5 a y r o m e m h s a l fz h k 2 3 = ) k l c b ( f, e d o m n o i t p m u s n o c r e w o p - w o l n i, m a r n o g n i n n u r m a r g o r p ) 3 ( 5 2 a , z h k 2 3 = ) k l c b ( f , e d o m n o i t p m u s n o c r e w o p - w o l n i y r o m e m h s a l f n o g n i n n u r m a r g o r p ) 3 ( 0 5 4 a , n o i t a l l i c s o p i h c - n o f ) c o r ( 2 , z h m 1 = ) k l c b ( f , d e t c e l e s e d o m t i a w n i 0 5 a , m o r k s a m y r o m e m h s a l f e d o m t i a w n i , z h k 2 3 = ) k l c b ( f ) 2 ( , h g i h y t i c a p a c n o i t a l l i c s o 5 . 8 a , z h k 2 3 = ) k l c b ( fe d o m t i a w n i ) 2 ( , w o l y t i c a p a c n o i t a l l i c s o 3 a , s p o t s k c o l c e l i h w5 2 = r p o tc 8 . 03 a : s e t o n o t d e c n e r e f e r . 1v c c v , v 5 . 5 o t 2 . 4 = s s . d e i f i c e p s e s i w r e h t o s s e l n u z h m 0 2 = ) k l c b ( f , c 5 8 o t 0 4 - = r p o t t a v 0 = f g n i s u , s e t a r e p o r e m i t e n o h t i w . 2 2 3 c . . s t s i x e d e t u c e x e e b o t m a r g o r p e h t h c i h w n i y r o m e m e h t s e t a c i d n i s i h t . 3
20. electrical characteristics (t-version) page 329 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r v cc = 5v timing requirements (v cc = 5v, v ss = 0v, at topr = 40 to 85 o c unless otherwise specified) table 20.9 external clock input (x in input) max. external clock rise time ns t r min. external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time ns ns ns ns t c t w(h ) t w(l) t f parameter symbol unit standard 50 20 20 9 9
20. electrical characteristics (t-version) page 330 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r v cc = 5v timing requirements (v cc = 5v, v ss = 0v, at topr = 40 to 85 o c unless otherwise specified) table 20.11 timer a input (gating input in timer mode) table 20.12 timer a input (external trigger input in one-shot timer mode) table 20.13 timer a input (external trigger input in pulse width modulation mode) table 20.14 timer a input (counter increment/decrement input in event counter mode) table 20.10 timer a input (counter input in event counter mode) table 20.15 timer a input (two-phase pulse input in event counter mode) standard max. ns tai in input low pulse width t w(tal) min. ns ns unit tai in input high pulse width t w(tah) parameter symbol t c(ta) tai in input cycle time 40 100 40 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 400 200 200 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 200 100 100 standard max. min. ns ns unit t w(tah) t w(tal) symbol parameter tai in input high pulse width tai in input low pulse width 100 100 standard max. min. ns ns ns unit ns ns symbol parameter tai out input cycle time tai out input high pulse width tai out input low pulse width tai out input setup time tai out input hold time t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in- up) 2000 1000 1000 400 400 standard max. min. ns ns ns unit symbol parameter tai in input cycle time tai out input setup time tai in input setup time t c(ta) t su(ta in -ta out ) t su(ta out -ta in ) 800 200 200
20. electrical characteristics (t-version) page 331 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r timing requirements (v cc = 5v, v ss = 0v, at topr = 40 to 85 o c unless otherwise specified) table 20.16 timer b input (counter input in event counter mode) table 20.17 timer b input (pulse period measurement mode) table 20.18 timer b input (pulse width measurement mode) table 20.19 a/d trigger input table 20.20 serial i/o _______ table 20.21 external interrupt inti input v cc = 5v ns ns ns ns ns ns ns standard max. min. tbi in input cycle time (counted on one edge) tbi in input high pulse width (counted on one edge) tbi in input low pulse width (counted on one edge) ns ns ns t c(tb) t w(tbh) t w(tbl) parameter symbol unit t c(tb) t w(tbl) t w(tbh) ns ns ns tbi in input high pulse width (counted on both edges) tbi in input low pulse width (counted on both edges) tbi in input cycle time (counted on both edges) standard max. min. ns ns t c(tb) t w(tbh) symbol parameter unit t w(tbl) ns tbi in input high pulse width tbi in input cycle time tbi in input low pulse width standard max. min. ns ns t c(tb) symbol parameter unit t w(tbl) ns t w(tbh) tbi in input cycle time tbi in input high pulse width tbi in input low pulse width standard max. min. ns ns t c(ad) t w(adl) symbol parameter unit ad trg input cycle time (trigger able minimum) ad trg input low pulse width standard max. min. ns ns t w(inh) t w(inl) symbol parameter unit inti input low pulse width inti input high pulse width standard max. min. clki input cycle time clki input high pulse width clki input low pulse width t c(ck) t w(ckh) t w(ckl) parameter symbol unit t d(c-q) t su(d-c) t h(c-q) txdi hold time rxdi input setup time txdi output delay time t h(c-d) rxdi input hold time 100 40 40 80 80 200 400 200 200 400 200 200 1000 125 250 250 200 100 100 0 70 90 80
20. electrical characteristics (t-version) page 332 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r timing requirements (v cc = 5v, v ss = 0v, at topr = 40 to 85 o c unless otherwise specified) table 20.22 multi-master i 2 c bus line v cc = 5v high-speed clock mode max. min. bus free time the hold time in start condition the hold time in scl clock "0" status s s s tbuf thd;sta tlow parameter symbol unit tr thigh thd;dat ns s s data hold time the hold time in scl clock "1" status scl, sda signals' rising time 1.3 0.6 1.3 0 0.6 20+0.1cb tf scl, sda signals' falling time t su ;dat data setup time t su ;sta the setup time in restart condition t su ;sto stop condition setup time standard clock mode max. min. 4.7 4.0 4.7 0 4.0 250 4.7 4.0 1000 300 100 0.6 20+0.1cb 0.6 300 300 0.9 ns ns s s
20. electrical characteristics (t-version) page 333 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r v cc = 5v figure 20.1 timing diagram (1) taiin input taiout input during event counter mode tbiin input adtrg input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t h(tin-up) t su(up-tin) taiin input (when count on falling edge is selected) taiin input (when count on rising edge is selected) taiout input (up/down input) taiin input two-phase pulse input in event counter mode t c(ta) t su(tain-taout) t su(taout-tain) t su(tain-taout) t su(taout-tain) taiout input xin input t w(h) t w(l) t r t f t c
20. electrical characteristics (t-version) page 334 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r v cc = 5v figure 20.2 timing diagram (2) figure 20.3 timing diagram (3) v cc = 5v t su(d ? c) clki txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c ? q) t h(c ? d) t h(c ? q) inti input t buf t hd:sta t hd:dta t low t r t f t high tsu :dat tsu :sta t hd:sta tsu :sto scl p s sr p sda
20. electrical characteristics (t-version) page 335 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r v cc = 3v table 20.23 electrical characteristics (1) l o b m y sr e t e m a r a pn o i t i d n o c d r a d n a t s t i n u . n i m. p y t. x a m v h o h g i h t u p t u o e g a t l o v ) " h " ( 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 i h o a m 1 - = v c c - 5 . 0 v c c v v h o e g a t l o v ) " h " ( h g i h t u p t u ox t u o r e w o p h g i h i h o a m 1 . 0 - = v c c - 5 . 0 v c c v r e w o p w o l i h o 0 5 - = a v c c - 5 . 0 v c c e g a t l o v ) " h " ( h g i h t u p t u ox t u o c r e w o p h g i h d e i l p p a d a o l o n5 . 2 v r e w o p w o l d e i l p p a d a o l o n6 . 1 v l o w o l t u p t u o e g a t l o v ) " l " ( 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 i l o a m 1 =5 . 0v v l o e g a t l o v ) " l " ( w o l t u p t u ox t u o r e w o p h g i h i l o a m 1 . 0 =5 . 0 v r e w o p w o l i l o 0 5 = a5 . 0 e g a t l o v ) " l " ( w o l t u p t u ox t u o c r e w o p h g i h d e i l p p a d a o l o n0 v r e w o p w o l d e i l p p a d a o l o n0 v + t v - - t s i s e r e t s y h 0 a t n i 4 a t - n i 0 b t , n i 2 b t - n i t n i , 0 t n i - 5 d a , i m n , g r t s t c , 0 - s t c 2 k l c , a d s , l c s , 0 k l c - 2 2 a t , t u o 4 a t - t u o i k , 0 i k - 3 r , 0 d x - r 2 d x s , 3 n i s , 4 n i 8 . 0v v + t v - - t s i s e r e t s y h t e s e r 8 . 1v v + t v - - t s i s e r e t s y h x n i 8 . 0 v i h i h g i h t u p n i t n e r r u c ) " h " ( 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 x n i v n c , t e s e r , s s v i v 3 =0 . 4 a i l i w o l t u p n i t n e r r u c ) " l " ( 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 x n i v n c , t e s e r , s s v i v 0 =0 . 4 - a r p u l l u p p u - l l u p e c n a t s i s e r 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 v i v 0 =0 50 0 10 0 5k ? f r n i x e c n a t s i s e r k c a b d e e fx n i 0 . 3m ? f r n i c x e c n a t s i s e r k c a b d e e fx n i c 5 2m ? v m a r e g a t l o v y b d n a t s m a r e d o m p o t s n i0 . 2v : e t o n o t d e c n e r e f e r . 1v c c v , v 6 . 3 o t 0 . 3 = s s . d e i f i c e p s e s i w r e h t o s s e l n u z h m 0 2 = ) k l c b ( f , c 5 8 o t 0 4 - = r p o t t a v 0 =
20. electrical characteristics (t-version) page 336 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r table 20.24 electrical characteristics (2) (1) v cc = 3v l o b m y sr e t e m a r a pn o i t i d n o c t n e m e r u s a e m d r a d n a t s t i n u . n i m. p y t. x a m i c c y l p p u s r e w o p t n e r r u c v ( c c ) v 6 . 3 o t 0 . 3 = e r a s n i p t u p t u o d n a n e p o t f e l e r a s n i p r e h t o v o t d e t c e n n o c s s m o r k s a m, z h m 0 1 = ) k l c b ( f n o i s i v i d o n , d e t a r e p o l l p 83 1a m , n o i t a l l i c s o p i h c - n o z h m 1 = ) k l c b ( f , d e t c e l e s ) c o r ( 2 f 1a m y r o m e m h s a l f( fk l c bn o i s i v i d o n , z h m 0 1 = )83 1a m y r o m e m h s a l f m a r g o r p v 0 . 3 = c c v , z h m 0 1 = ) k l c b ( f 1 1a m y r o m e m h s a l f e s a r e v 0 . 3 = c c v , z h m 0 1 = ) k l c b ( f 1 1a m m o r k s a mx ( f n i c , z h k 2 3 = ) , e d o m n o i t p m u s n o c r e w o p - w o l n i m o r ) 3 ( 0 2 a , n o i t a l l i c s o p i h c - n o , z h m 1 = ) k l c b ( f , d e t c e l e s ) c o r ( 2 f e d o m t i a w n i 5 2 a y r o m e m h s a l fz h k 2 3 = ) k l c b ( f, e d o m n o i t p m u s n o c r e w o p - w o l n i, m a r n o g n i n n u r m a r g o r p ) 3 ( 0 2 a , z h k 2 3 = ) k l c b ( f , e d o m n o i t p m u s n o c r e w o p - w o l n i y r o m e m h s a l f n o g n i n n u r m a r g o r p ) 3 ( 0 5 4 a , n o i t a l l i c s o p i h c - n o f ) c o r ( 2 , z h m 1 = ) k l c b ( f , d e t c e l e s e d o m t i a w n i 5 4 a , m o r k s a m y r o m e m h s a l f e d o m t i a w n i , z h k 2 3 = ) k l c b ( f ) 2 ( , h g i h y t i c a p a c n o i t a l l i c s o 6 . 6 a , z h k 2 3 = ) k l c b ( fe d o m t i a w n i ) 2 ( , w o l y t i c a p a c n o i t a l l i c s o 2 . 2 a , s p o t s k c o l c e l i h w5 2 = r p o tc 7 . 03 a : s e t o n o t d e c n e r e f e r . 1v c c v , v 6 . 3 o t 0 . 3 = s s . d e i f i c e p s e s i w r e h t o s s e l n u z h m 0 2 = ) k l c b ( f , c 5 8 o t 0 4 - = r p o t t a v 0 = f g n i s u , s e t a r e p o r e m i t e n o h t i w . 2 2 3 c . . s t s i x e d e t u c e x e e b o t m a r g o r p e h t h c i h w n i y r o m e m e h t s e t a c i d n i s i h t . 3
20. electrical characteristics (t-version) page 337 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r timing requirements (v cc = 3v, v ss = 0v, at topr = 40 to 85 o c unless otherwise specified) table 20.25 external clock input (x in input) v cc = 3v max. external clock rise time ns t r min. external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time ns ns ns ns t c t w(h ) t w(l) t f parameter symbol unit standard 100 40 40 18 18
20. electrical characteristics (t-version) page 338 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r v cc = 3v timing requirements (v cc = 3v, v ss = 0v, at topr = 40 to 85 o c unless otherwise specified) table 20.26 timer a input (counter input in event counter mode) table 20.27 timer a input (gating input in timer mode) table 20.28 timer a input (external trigger input in one-shot timer mode) table 20.29 timer a input (external trigger input in pulse width modulation mode) table 20.30 timer a input (counter increment/decrement input in event counter mode) table 20.31 timer a input (two-phase pulse input in event counter mode) standard max. ns tai in input low pulse width t w(tal) min. ns ns unit tai in input high pulse width t w(tah) parameter symbol t c(ta) tai in input cycle time 60 150 60 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 600 300 300 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 300 150 150 standard max. min. ns ns unit t w(tah) t w(tal) symbol parameter tai in input high pulse width tai in input low pulse width 150 150 standard max. min. ns ns ns unit ns ns symbol parameter tai out input cycle time tai out input high pulse width tai out input low pulse width tai out input setup time tai out input hold time t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in- up) 3000 1500 1500 600 600 standard max. min. s ns ns unit symbol parameter tai in input cycle time tai out input setup time tai in input setup time t c(ta) t su(ta in -ta out ) t su(ta out -ta in ) 2 500 500
20. electrical characteristics (t-version) page 339 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r v cc = 3v table 20.32 timer b input (counter input in event counter mode) table 20.33 timer b input (pulse period measurement mode) table 20.34 timer b input (pulse width measurement mode) table 20.35 a/d trigger input table 20.36 serial i/o _______ table 20.37 external interrupt inti input timing requirements (v cc = 3v, v ss = 0v, at topr = 40 to 85 o c unless otherwise specified) ns ns ns ns ns ns ns standard max. min. tbi in input cycle time (counted on one edge) tbi in input high pulse width (counted on one edge) tbi in input low pulse width (counted on one edge) ns ns ns t c(tb) t w(tbh) t w(tbl) parameter symbol unit t c(tb) t w(tbl) t w(tbh) ns ns ns tbi in input high pulse width (counted on both edges) tbi in input low pulse width (counted on both edges) tbi in input cycle time (counted on both edges) standard max. min. ns ns t c(tb) t w(tbh) symbol parameter unit t w(tbl) ns tbi in input high pulse width tbi in input cycle time tbi in input low pulse width standard max. min. ns ns t c(tb) symbol parameter unit t w(tbl) ns t w(tbh) tbi in input cycle time tbi in input high pulse width tbi in input low pulse width standard max. min. ns ns t c(ad) t w(adl) symbol parameter unit ad trg input cycle time (trigger able minimum) ad trg input low pulse width standard max. min. ns ns t w(inh) t w(inl) symbol parameter unit inti input low pulse width inti input high pulse width standard max. min. clki input cycle time clki input high pulse width clki input low pulse width t c(ck) t w(ckh) t w(ckl) parameter symbol unit t d(c-q) t su(d-c) t h(c-q) txdi hold time rxdi input setup time txdi output delay time t h(c-d) rxdi input hold time 150 60 60 120 120 300 600 300 300 600 300 300 1500 200 380 380 300 150 150 0 90 160 100
20. electrical characteristics (t-version) page 340 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r v cc = 3v timing requirements (v cc = 3v, v ss = 0v, at topr = 40 to 85 o c unless otherwise specified) table 20.38 multi-master i 2 c bus line high-speed clock mode max. min. bus free time the hold time in start condition the hold time in scl clock "0" status s s s tbuf thd;sta tlow parameter symbol unit tr thigh thd;dat ns s s data hold time the hold time in scl clock "1" status scl, sda signals' rising time 1.3 0.6 1.3 0 0.6 20+0.1cb tf scl, sda signals' falling time t su ;dat data setup time t su ;sta the setup time in restart condition t su ;sto stop condition setup time standard clock mode max. min. 4.7 4.0 4.7 0 4.0 250 4.7 4.0 1000 300 100 0.6 20+0.1cb 0.6 300 300 0.9 ns ns s s
20. electrical characteristics (t-version) page 341 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r v cc = 3v figure 20.4 timing diagram (1) taiin input taiout input during event counter mode tbiin input adtrg input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t h(tin-up) t su(up-tin) taiin input (when count on falling edge is selected) taiin input (when count on rising edge is selected) taiout input (up/down input) taiin input two-phase pulse input in event counter mode t c(ta) t su(tain-taout) t su(taout-tain) t su(tain-taout) t su(taout-tain) taiout input xin input t w(h) t w(l) t r t f t c
20. electrical characteristics (t-version) page 342 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r v cc = 3v figure 20.5 timing diagram (2) figure 20.6 timing diagram (3) v cc = 3v t su(d ? c) clki txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c ? q) t h(c ? d) t h(c ? q) inti input t buf t hd:sta t hd:dta t low t r t f t high tsu :dat tsu :sta t hd:sta tsu :sto scl p s sr p sda
20. electrical characteristics (v-version) page 343 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r 20.2 v version table 20.39 absolute maximum ratings l o b m y sr e t e m a r a pn o i t i d n o ce u l a vt i n u v c c e g a t l o v y l p p u sv c c v a = c c 5 . 6 o t 3 . 0 - v v a c c e g a t l o v y l p p u s g o l a n av c c v a = c c 5 . 6 o t 3 . 0 - v v i e g a t l o v t u p n i0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 , 3 p 0 3 p o t 7 6 p , 0 6 p o t 7 7 p , 0 7 p o t 7 , 8 p 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 , 0 1 p 0 0 1 p o t 7 , x n i v , f e r v n c , t e s e r , s s v o t 3 . 0 - c c 3 . 0 +v v o e g a t l o v t u p t u o0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 , 3 p 0 3 p o t 7 6 p , 0 6 p o t 7 7 p , 0 7 p o t 7 , 8 p 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 , 0 1 p 0 0 1 p o t 7 , x t u o v o t 3 . 0 - c c 3 . 0 +v d pn o i t a p i s s i d r e w o p 0 4 -< r p o t< c 5 80 0 3w m 5 8< r p o t< c 5 2 10 0 2w m r p o t g n i t a r e p o t n e i b m a e r u t a r e p m e t n o i t a r e p o u p c g n i r u d 5 2 1 o t 0 4 -c y r o m e m h s a l f g n i r u d e s a r e d n a m a r g o r p n o i t a r e p o e c a p s m a r g o r p ) 4 k c o l b o t 0 k c o l b ( 0 6 o t 0c e c a p s a t a d ) b k c o l b , a k c o l b ( 5 2 1 o t 0 4 -c g t s te r u t a r e p m e t e g a r o t s 0 5 1 o t 5 6 -c
20. electrical characteristics (v-version) page 344 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r table 20.40 recommended operating conditions (1) l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. p y t. x a m v c c e g a t l o v y l p p u s 2 . 45 . 5v v a c c e g a t l o v y l p p u s g o l a n a v c c v v s s e g a t l o v y l p p u s 0v v a s s e g a t l o v y l p p u s g o l a n a 0v v h i ) " h " ( h g i h t u p n i e g a t l o v 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 v 7 . 0 c c v c c v s s v n c , t e s e r , n i x v 8 . 0 c c v c c v v l i ) " l " ( w o l t u p n i e g a t l o v 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 0v 3 . 0 c c v s s v n c , t e s e r , n i x 0v 2 . 0 c c v i ) k a e p ( h o t u p t u o k a e p ) " h " ( h g i h t n e r r u c 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 0 . 0 1 -a m i ) g v a ( h o t u p t u o e g a r e v a ) " h " ( h g i h t n e r r u c 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 0 . 5 -a m i ) k a e p ( l o t u p t u o k a e p ) " l " ( w o l t n e r r u c 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 0 . 0 1a m i ) g v a ( l o t u p t u o e g a r e v a ) " l " ( w o l t n e r r u c 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 0 . 5a m x ( f n i )y c n e u q e r f t u p n i k c o l c n i a m ) 3 ( 5 0 1 o t 0 4 - = r p o tc 00 2z h m 5 2 1 o t 0 4 - = r p o tc 0 6 1z h m x ( f n i c )y c n e u q e r f k c o l c b u s 8 6 7 . 2 30 5z h k f 1 ) c o r (1 y c n e u q e r f r o t a l l i c s o p i h c - n o 5 . 012z h m ) c o r ( 2 f2 y c n e u q e r f r o t a l l i c s o p i h c - n o 12 4 z h m ) c o r ( 3 f3 y c n e u q e r f r o t a l l i c s o p i h c - n o 86 16 2z h m ) l l p ( fy c n e u q e r f k c o l c l l p ) 3 ( 5 0 1 o t 0 4 - = r p o tc 0 10 2z h m 5 2 1 o t 0 4 - = r p o tc 0 16 1z h m ) k l c b ( fy c n e u q e r f k c o l c n o i t a r e p o u p c 5 0 1 o t 0 4 - = r p o tc 0 0 2s m 5 2 1 o t 0 4 - = r p o tc 0 6 1s m t u s ) l l p (r e z i s e h t n y s y c n e u q e r f l l p e z i l i b a t s o t e m i t t i a wv c c v 0 . 5 =0 2s m : s e t o n v o t d e c n e r e f e r . 1 c c . d e i f i c e p s e s i w r e h t o s s e l n u c 5 2 1 o t 0 4 - = r p o t t a v 5 . 5 o t 2 . 4 = . s m 0 0 1 n i h t i w e u l a v n a e m e h t s i t n e r r u c t u p t u o n a e m e h t . 2 . e g a t l o v y l p p u s d n a y c n e u q e r f n o i t a l l i c s o k c o l c l l p , y c n e u q e r f n o i t a l l i c s o k c o l c n i a m g n o m a p i h s n o i t a l e r . 3 i l a t o t e h t . 4 ) k a e p ( l o i l a t o t e h t . s s e l r o a m 0 8 e b t s u m s t r o p l l a r o f ) k a e p ( h o . s s e l r o a m 0 8 - e b t s u m s t r o p l l a r o f main clock input oscillation frequency f(x in ) operating maximum frequency [mh z ] v cc [v] (main clock: no division) pll clock oscillation frequency f(pll) operating maximum frequency [mh z ] v cc [v] (pll clock oscillation) 20.0 0.0 5.5 10.0 20.0 0.0 5.5 10.0 16.0 4.2 aaa a a a a a a a a a aaa aa aa aa aa aa aa 20.0 mhz (topr = -40 c to 105 c) 16.0 mhz (topr = -40 c to 125 c) 20.0 mhz (topr = -40 c to 105 c) 16.0 mhz (topr = -40 c to 125 c) aaa aaa 4.2 16.0
20. electrical characteristics (v-version) page 345 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r table 20.41 a/d conversion characteristics (1) l o b m y sr e t e m a r a pn o i t i d n o c t n e m e r u s a e m d r a d n a t s t i n u . n i m. p y t. x a m -n o i t u l o s e rv f e r v = c c 0 1s t i b l n i y t i r a e n i l n o n l a r g e t n i r o r r e t i b 0 1v f e r v = c c v 5 =3 b s l t i b 8v f e r v = c c v 5 =2 b s l -y c a r u c c a e t u l o s b a t i b 0 1v f e r v = c c v 5 =3 b s l t i b 8v f e r v = c c v 5 =2 b s l l n dr o r r e y t i r a e n i l n o n l a i t n e r e f f i d 1 b s l -r o r r e t e s f f o 3 b s l -r o r r e n i a g 3 b s l r r e d d a l r e d d a l r o t s i s e rv = f e r v c c 0 10 4k ? t v n o c e m i t n o i s r e v n o c t i b - 0 1 e l b a l i a v a n o i t c n u f d l o h & e l p m a s v f e r v = c c z h m 0 1 = d a ? , v 5 =3 . 3 s t v n o c e m i t n o i s r e v n o c t i b - 8 e l b a l i a v a n o i t c n u f d l o h & e l p m a s v f e r v = c c z h m 0 1 = d a ? , v 5 =8 . 2 s v f e r e g a t l o v e c n e r e f e r 0 . 2v c c v v a i e g a t l o v t u p n i g o l a n a 0v f e r v : s e t o n v o t d e c n e r e f e r . 1 c c v a = c c v = f e r v , v 5 . 5 o t 2 . 4 = s s v a = s s . d e i f i c e p s e s i w r e h t o s s e l n u c 5 2 1 o t 0 4 - = r p o t t a v 0 = p e e k . 2 . s s e l r o z h m 0 1 t a y c n e u q e r f d a . 3p e e k , d e l b a s i d s i n o i t c n u f d l o h & e l p m a s n e h w . 2 e t o n n i n o i t a t i m i l e h t o t n o i t i d d a n i e r o m r o z h k 0 5 2 t a y c n e u q e r f d a p e e k , d e l b a n e s i n o i t c n u f d l o h & e l p m a s n e h w . 2 e t o n n i n o i t a t i m i l e h t o t n o i t i d d a n i e r o m r o z h m 1 t a y c n e u q e r f d a / 3 s i e m i t g n i l p m a s , d e l b a n e s i n o i t c n u f d l o h & e l p m a s n e h w . 4 . y c n e u q e r f d a / 2 s i e m i t g n i l p m a s , d e l b a s i d s i n o i t c n u f d l o h & e l p m a s n e h w . y c n e u q e r f d a
20. electrical characteristics (v-version) page 346 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r table 20.42 flash memory version electrical characteristics (1) for 100/1000 e/w cycle products [program space and data space in u3; program space in u7] table 20.43 flash memory version electrical characteristics (6) for 10000 e/w cycle products [data space in u7 (7) ] l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. p y t ) 2 ( . x a m - e c n a r u d n e e s a r e d n a m a r g o r p ) 3 ( 0 0 0 1 / 0 0 1 ) 1 1 , 4 ( s e l c y c -v ( e m i t m a r g o r p d r o w c c 5 2 = r p o t , v 0 . 5 =c )5 70 0 6 s -e m i t e s a r e k c o l b v ( c c 5 2 = r p o t , v 0 . 5 =c ) k c o l b e t y b k - 2 2 . 09s k c o l b e t y b k - 8 4 . 09s k c o l b e t y b k - 6 1 7 . 09s k c o l b e t y b k - 2 3 2 . 19s ) s e - r s ( d td n e p s u s e s a r e d n a t s e u q e r d n e p s u s n e e w t e b n o i t a r u d 8s m t s p t i u c r i c y r o m e m h s a l f e z i l i b a t s o t e m i t t i a w 5 1 s -e m i t d l o h a t a d ) 5 ( 0 2s r a e y l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. p y t ) 2 ( . x a m - e c n a r u d n e e s a r e d n a m a r g o r p ) 9 , 8 , 3 ( 0 0 0 0 1 ) 0 1 , 4 ( s e l c y c -v ( e m i t m a r g o r p d r o w c c 5 2 = r p o t , v 0 . 5 =c )0 0 1 s - e m i t e s a r e k c o l bv ( c c 5 2 = r p o t , v 0 . 5 =c ) ) k c o l b e t y b k - 2 ( 3 . 0s ) s e - r s ( d td n e p s u s e s a r e d n a t s e u q e r d n e p s u s n e e w t e b n o i t a r u d 8s m t s p t i u c r i c y r o m e m h s a l f e z i l i b a t s o t e m i t t i a w 5 1 s -e m i t d l o h a t a d ) 5 ( 0 2s r a e y : s e t o n 0 6 o t 0 = r p o t t a v 5 . 5 o t 2 . 4 = c c v o t d e c n e r e f e r . 1 s s e l n u , ) e c a p s a t a d ( c 5 2 1 o t 0 4 - = r p o t / ) e c a p s m a r g o r p ( c . d e i f i c e p s e s i w r e h t o c 5 2 = r p o t ; v 5 = c c v . 2 . k c o l b r e p s e l c y c e s a r e - m a r g o r p f o r e b m u n s a d e n i f e d s i e c n a r u d n e e s a r e d n a m a r g o r p . 3 s i e c n a r u d n e e s a r e d n a m a r g o r p f i n ( e l c y c n d e m m a r g o r p d n a d e s a r e e b n a c k c o l b h c a e , ) 0 0 0 0 1 , 0 0 0 1 , 0 0 1 = n . s e l c y c , s e m i t 4 2 0 , 1 s s e r d d a h c a e o t a t a d d r o w - e n o g n i m m a r g o r p r e t f a d e s a r e s i a k c o l b e t y b k - 2 a f i , e l p m a x e r o f n a h t e r o m s s e r d d a e m a s e h t o t d e m m a r g o r p e b t o n n a c a t a d . e c n a r u d n e e s a r e d n a m a r g o r p e n o s a s t n u o c s i h t . ) d e t i b i h o r p e t i r w e r ( . k c o l b e h t g n i s a r e t u o h t i w e c n o . ) d e e t n a r u g e r a e u l a v m u m i n i m o t 1 ( d e e t n a r u g s i n o i t a r e p o h c i h w r o f s e l c y c w / e f o r e b m u n . 4 c 5 5 = r p o t . 5 . d e i f i c e p s e s i w r e h t o s s e l n u c 5 2 1 o t 0 4 - = r p o t t a v 5 . 5 o t 2 . 4 = c c v o t d e c n e r e f e r . 6 . 7 2 4 . 0 2 e l b a t . s e l c y c 0 0 0 , 1 n a h t e r o m s i e c n a r u d n e e s a r e d n a m a r g o r p n e h w 7 u d n a 7 b n i e c a p s a t a d r o f s e i l p p a e s u , e s i w r e h t o 3 4 . 0 2 e l b a t . , s e t i r w e r s u o r e m u n g n i r i u q e r s m e t s y s h t i w g n i k r o w n e h w e c n a r u d n e e s a r e d n a m a r g o r p f o r e b m u n e h t e c u d e r o t . 8 s e s s e r d d a e l b i s s o p l l a r e t f a y l n o k c o l b e s a r e . e t i r w e r f o d a e t s n i k c o l b e h t n i h t i w s e s s e r d d a d r o w d e s u n u o t e t i r w . y r a s s e c e n s e m o c e b e s a r e e r o f e b m u m i x a m s e m i t 8 2 1 n e t t i r w e b n a c m a r g o r p d r o w - 8 n a , e l p m a x e r o f . d e s u e r a s i t i . y c n e i c i f f e e v o r p m i o s l a l l i w b k c o l b d n a a k c o l b n e e w t e b e r u s a r e s e m i t f o r e b m u n l a u q e n a g n i n i a t n i a m . e r u s a r e f o r e b m u n e h t t i m i l o t d n a k c o l b r e p d e m r o f r e p e r u s a r e f o r e b m u n l a t o t e h t k c a r t o t d e d n e m m o c e r d n a m m o c e s a r e k c o l c d n a d n a m m o c r e t s i g e r s u t a t s r a e l c m r o f r e p , e s a r e k c o l b g n i r u d d e r u c c o e r a s r o r r e e s a r e f i . 9 . r a e p p a s i d s r o r r e e s a r e l i t n u , s e m i t e e r h t t s a e l t a , r e d r o l a i t n e u q e s n i n i t i b 7 1 r m f e h t g n i t t e s y b s s e c c a k c o l b r e p e t a t s t i a w e n o t e s , s e t i r w e r s e m i t 0 0 1 n a h t e r o m g n i t u c e x e n e h w . 0 1 t e s e b n a c e t a t s t i a w , m a r l a n r e t n i d n a s k c o l b r e h t o l l a o t g n i s s e c c a n e h w . ) e t a t s t i a w ( 1 o t r e t s i g e r 1 r m f e h t . e u l a v g n i t t e s t i b 7 1 r m f e h t f o s s e l d r a g e r , t i b 7 1 m p e h t y b s e l c y c 0 0 0 , 1 ; 3 u n i e c a p s a t a d d n a e c a p s m a r g o r p r o f s e l c y c 0 0 1 s i e c n a r u d n e e s a r e d n a m a r g o r p e h t . 1 1 . 7 u n i e c a p s m a r g o r p r o f . e v i t a t n e s e r p e r t r o p p u s l a c i n h c e t s a s e n e r r i e h t t c a t n o c d l u o h s n o i t a m r o f n i e t a r e r u l i a f w / e g n i r i s e d s r e m o t s u c . 2 1 erase suspend request (interrupt request) fmr46 td(sr-es)
20. electrical characteristics (v-version) page 347 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r table 20.44 power supply circuit timing characteristics l o b m y sr e t e m a r a pn o i t i d n o c t n e m e r u s a e m d r a d n a t s t i n u . n i m. p y t. x a m ) r - p ( d t n e h w e g a t l o v y l p p u s l a n r e t n i e z i l i b a t s o t e m i t t i a w n o - r e w o p v c c v 5 . 5 o t 2 . 4 = 2s m ) c o r ( d t n e h w r o t a l l i c s o p i h c - n o l a n r e t n i e z i l i b a t s o t e m i t t i a w n o - r e w o p 0 4 s ) r - s ( d te m i t e s a e l e r p o t s 0 5 1 s ) s - w ( d t e s a e l e r e d o m t i a w e d o m n o i t a p i s s i d r e w o p w o l e m i t 0 5 1 s t d(p-r) wait time to stabilize internal supply voltage when power-on cpu clock t d(r-s ) (a) (b) t d(w-s) t d(r-s) stop release time t d(w-s) low power dissipation mode wait mode release tim e interrupt for (a) stop mode release or (b) wait mode release t d(roc) wait time to stabilize internal on-chip oscillator when power- on roc reset vcc td(p-r) td(roc )
20. electrical characteristics (v-version) page 348 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r table 20.45 electrical characteristics (1) v cc = 5v l o b m y sr e t e m a r a pn o i t i d n o c d r a d n a t s t i n u . n i m. p y t. x a m v h o h g i h t u p t u o e g a t l o v ) " h " ( 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 i h o a m 5 - = v c c - 0 . 2 v c c v v h o h g i h t u p t u o e g a t l o v ) " h " ( 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 i h o 0 0 2 - = a v c c - 3 . 0 v c c v v h o e g a t l o v ) " h " ( h g i h t u p t u ox t u o r e w o p h g i h i h o a m 1 - = v c c - 0 . 2 v c c v r e w o p w o l i h o a m 5 . 0 - = v c c - 0 . 2 v c c e g a t l o v ) " h " ( h g i h t u p t u ox t u o c r e w o p h g i h d e i l p p a d a o l o n5 . 2 v r e w o p w o l d e i l p p a d a o l o n6 . 1 v l o w o l t u p t u o e g a t l o v ) " l " ( 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 i l o a m 5 =0 . 2v v l o w o l t u p t u o e g a t l o v ) " l " ( 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 i l o 0 0 2 = a5 4 . 0v v l o e g a t l o v ) " l " ( w o l t u p t u ox t u o r e w o p h g i h i l o a m 1 =0 . 2 v r e w o p w o l i l o a m 5 . 0 =0 . 2 e g a t l o v ) " l " ( w o l t u p t u ox t u o c r e w o p h g i h d e i l p p a d a o l o n0 v r e w o p w o l d e i l p p a d a o l o n0 v + t v - - t s i s e r e t s y h 0 a t n i 4 a t - n i 0 b t , n i 2 b t - n i t n i , 0 t n i - 5 d a , i m n , g r t s t c , 0 - s t c 2 k l c , a d s , l c s , 0 k l c - 2 2 a t , t u o 4 a t - t u o i k , 0 i k - 3 r , 0 d x - r 2 d x s , 3 n i s , 4 n i 2 . 00 . 1v v + t v - - t s i s e r e t s y h t e s e r 2 . 05 . 2v v + t v - - t s i s e r e t s y h x n i 2 . 08 . 0 v i h i h g i h t u p n i t n e r r u c ) " h " ( 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 x n i v n c , t e s e r , s s v i v 5 =0 . 5 a i l i w o l t u p n i t n e r r u c ) " l " ( 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 x n i v n c , t e s e r , s s v i v 0 =0 . 5 - a r p u l l u p p u - l l u p e c n a t s i s e r 0 p 0 0 p o t 7 1 p , 0 1 p o t 7 2 p , 0 2 p o t 7 3 p , 0 3 p o t 7 6 p , 0 6 p o t 7 , 7 p 0 7 p o t 7 8 p , 0 8 p o t 7 9 p , 0 9 p o t 3 9 p , 5 9 p o t 7 0 1 p , 0 0 1 p o t 7 v i v 0 =0 30 50 7 1k ? f r n i x e c n a t s i s e r k c a b d e e fx n i 5 . 1m ? f r n i c x e c n a t s i s e r k c a b d e e fx n i c 5 1m ? v m a r e g a t l o v y b d n a t s m a r e d o m p o t s n i0 . 2v : s e t o n o t d e c n e r e f e r . 1v c c v , v 5 . 5 o t 2 . 4 = s s v / z h m 0 2 = ) k l c b ( f , c 5 0 1 o t 0 4 - = r p o t t a v 0 = c c v , v 5 . 5 o t 2 . 4 = s s 0 4 - = r p o t t a v 0 = . d e i f i c e p s e s i w r e h t o s s e l n u , z h m 6 1 = ) k l c b ( f , c 5 2 1 o t
20. electrical characteristics (v-version) page 349 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r table 20.46 electrical characteristics (2) (1) v cc = 5v l o b m y sr e t e m a r a pn o i t i d n o c t n e m e r u s a e m d r a d n a t s t i n u . n i m. p y t. x a m i c c y l p p u s r e w o p t n e r r u c v ( c c ) v 5 . 5 o t 2 . 4 = e r a s n i p t u p t u o d n a n e p o t f e l e r a s n i p r e h t o v o t d e t c e n n o c s s m o r k s a m, z h m 0 2 = ) k l c b ( f n o i s i v i d o n , k c o l c n i a m 8 15 2a m n o i t a l l i c s o p i h c - n o f ) c o r ( 2 z h m 1 = ) k l c b ( f , d e t c e l e s 2a m y r o m e m h s a l f( fk l c b, z h m 0 2 = ) n o i s i v i d o n , k c o l c n i a m 8 15 2a m ( fk l c b, z h m 6 1 = ) n o i s i v i d o n , k c o l c n i a m 4 10 2a m f , n o i t a l l i c s o p i h c - n o ) c o r ( 2 , d e t c e l e s z h m 1 = ) k l c b ( f 2a m y r o m e m h s a l f m a r g o r p v 0 . 5 = c c v , z h m 0 1 = ) k l c b ( f 1 1a m y r o m e m h s a l f e s a r e v 0 . 5 = c c v , z h m 0 1 = ) k l c b ( f 1 1a m m o r k s a mx ( f n i c , z h k 2 3 = ) , e d o m n o i t p m u s n o c r e w o p - w o l n i m o r n o g n i n n u r m a r g o r p ) 3 ( 5 2 a n o i t a l l i c s o p i h c - n o f ) c o r ( 2 , z h m 1 = ) k l c b ( f , d e t c e l e s e d o m t i a w n i 0 5 a y r o m e m h s a l fz h k 2 3 = ) k l c b ( f, e d o m n o i t p m u s n o c r e w o p - w o l n i, m a r n o g n i n n u r m a r g o r p ) 3 ( 5 2 a , z h k 2 3 = ) k l c b ( f , e d o m n o i t p m u s n o c r e w o p - w o l n i y r o m e m h s a l f n o g n i n n u r m a r g o r p ) 3 ( 0 5 4 a f , n o i t a l l i c s o p i h c - n o ) c o r ( 2 , d e t c e l e s e d o m t i a w n i , z h m 1 = ) k l c b ( f 0 5 a , m o r k s a m y r o m e m h s a l f e d o m t i a w n i , z h k 2 3 = ) k l c b ( f ) 2 ( , h g i h y t i c a p a c n o i t a l l i c s o 5 . 8 a , z h k 2 3 = ) k l c b ( fe d o m t i a w n i ) 2 ( , w o l y t i c a p a c n o i t a l l i c s o 3 a , s p o t s k c o l c e l i h w5 2 = r p o tc 8 . 03 a : s e t o n o t d e c n e r e f e r . 1v c c v , v 5 . 5 o t 2 . 4 = s s v / z h m 0 2 = ) k l c b ( f , c 5 0 1 o t 0 4 - = r p o t t a v 0 = c c v , v 5 . 5 o t 2 . 4 = s s v 0 = . d e i f i c e p s e s i w r e h t o s s e l n u , z h m 6 1 = ) k l c b ( f , c 5 2 1 o t 0 4 - = r p o t t a f g n i s u , s e t a r e p o r e m i t e n o h t i w . 2 2 3 c . . s t s i x e d e t u c e x e e b o t m a r g o r p e h t h c i h w n i y r o m e m e h t s e t a c i d n i s i h t . 3
20. electrical characteristics (v-version) page 350 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r timing requirements (vcc=5v, vss=0v, at topr=-40 to 125 c unless otherwise specified) table 20.47 external clock input (xin input) v cc = 5v l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m c te m i t e l c y c t u p n i k c o l c l a n r e t x e 0 4 - = r p o tc 5 0 1 o tc 0 5s n 0 4 - = r p o tc 5 2 1 o tc 5 . 2 6s n w t ) h ( h t d i w ) " h " ( h g i h t u p n i k c o l c l a n r e t x e 0 4 - = r p o tc 5 0 1 o tc 0 2s n 0 4 - = r p o tc 5 2 1 o tc 5 2s n w t ) l ( h t d i w ) " l " ( w o l t u p n i k c o l c l a n r e t x e 0 4 - = r p o tc 5 0 1 o tc 0 2s n 0 4 - = r p o tc 5 2 1 o tc 5 2s n r te m i t e s i r k c o l c l a n r e t x e 0 4 - = r p o tc 5 0 1 o tc 9s n 0 4 - = r p o tc 5 2 1 o tc 5 1s n f te m i t l l a f k c o l c l a n r e t x e 0 4 - = r p o tc 5 0 1 o tc 9s n 0 4 - = r p o tc 5 2 1 o tc 5 1s n
20. electrical characteristics (v-version) page 351 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m c t ) a t ( i a t n i e m i t e l c y c t u p n i 0 0 1s n w t ) h a t ( i a t n i h t d i w ) " h " ( h g i h t u p n i 0 4s n w t ) l a t ( i a t n i h t d i w ) " l " ( w o l t u p n i 0 4s n l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m c t ) a t ( i a t n i e m i t e l c y c t u p n i 0 0 4s n w t ) h a t ( i a t n i h t d i w ) " h " ( h g i h t u p n i 0 0 2s n w t ) l a t ( i a t n i h t d i w ) " l " ( w o l t u p n i 0 0 2s n l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m c t ) a t ( i a t n i e m i t e l c y c t u p n i 0 0 2s n w t ) h a t ( i a t n i h t d i w ) " h " ( h g i h t u p n i 0 0 1s n w t ) l a t ( i a t n i h t d i w ) " l " ( w o l t u p n i 0 0 1s n l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m w t ) h a t ( i a t n i h t d i w ) " h " ( h g i h t u p n i 0 0 1s n w t ) l a t ( i a t n i h t d i w ) " l " ( w o l t u p n i 0 0 1s n l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m c t ) p u ( i a t t u o e m i t e l c y c t u p n i0 0 0 2s n w t ) h p u ( i a t t u o h t d i w ) " h " ( h g i h t u p n i0 0 0 1s n w t ) l p u ( i a t t u o h t d i w ) " l " ( w o l t u p n i0 0 0 1s n u s t ) n i t - p u ( i a t t u o e m i t p u t e s t u p n i0 0 4s n h t ) p u - n i t ( i a t t u o e m i t d l o h t u p n i0 0 4s n l o b m y sr e t e m a r a p d r a d n a t st i n u . n i m. x a m c t ) a t ( i a t n i e m i t e l c y c t u p n i 0 0 8s n u s t a t ( n i a t - t u o ) i a t t u o e m i t p u t e s t u p n i0 0 2s n u s t a t ( - t u o a t n i ) i a t n i e m i t p u t e s t u p n i 0 0 2s n timing requirements (v cc =5v, v ss =0v, at topr=-40 to 125 c unless otherwise specified) table 20.48 timer a input (counter input in event counter mode) table 20.49 timer a input (gating input in timer mode) table 20.50 timer a input (external trigger input in one-shot timer mode) table 20.51 timer a input (external trigger input in pulse width modulation mode) table 20.52 timer a input (counter increment/decrement input in event counter mode) table 20.53 timer a input (two-phase pulse input in event counter mode) v cc = 5v
20. electrical characteristics (v-version) page 352 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r timing requirements (v cc =5v, v ss =0v, at topr=-40 to 125 c unless otherwise specified) table 20.54 timer b input (counter input in event counter mode) l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m c t ) b t ( i b t n i ) e g d e e n o n o d e t n u o c ( e m i t e l c y c t u p n i 0 0 1s n w t ) h b t ( i b t n i ) e g d e e n o n o d e t n u o c ( h t d i w ) " h " ( h g i h t u p n i 0 4s n w t ) l b t ( i b t n i ) e g d e e n o n o d e t n u o c ( h t d i w ) " l " ( w o l t u p n i 0 4s n c t ) b t ( i b t n i ) s e g d e h t o b n o d e t n u o c ( e m i t e l c y c t u p n i 0 0 2s n w t ) h b t ( i b t n i ) s e g d e h t o b n o d e t n u o c ( h t d i w ) " h " ( h g i h t u p n i 0 8s n w t ) l b t ( i b t n i ) s e g d e h t o b n o d e t n u o c ( h t d i w ) " l " ( w o l t u p n i 0 8s n l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m c t ) b t ( i b t n i e m i t e l c y c t u p n i 0 0 4s n w t ) h b t ( i b t n i h t d i w ) " h " ( h g i h t u p n i 0 0 2s n w t ) l b t ( i b t n i h t d i w ) " l " ( w o l t u p n i 0 0 2s n l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m c t ) b t ( i b t n i e m i t e l c y c t u p n i 0 0 4s n w t ) h b t ( i b t n i h t d i w ) " h " ( h g i h t u p n i 0 0 2s n w t ) l b t ( i b t n i h t d i w ) " l " ( w o l t u p n i 0 0 2s n l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i mx a m c t ) d a ( d a g r t ) r e g g i r t r o f d e r i u q e r ( e m i t e l c y c t u p n i0 0 0 1s n w t ) l d a ( d a g r t h t d i w ) " l " ( w o l t u p n i5 2 1s n l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m c t ) k c ( e m i t e l c y c t u p n i i k l c 0 0 2s n w t ) h k c ( h t d i w ) " h " ( h g i h t u p n i i k l c 0 0 1s n w t ) l k c ( h t d i w ) " l " ( w o l t u p n i i k l c 0 0 1s n d t ) q - c ( e m i t y a l e d t u p t u o i d x t 0 8s n h t ) q - c ( e m i t d l o h i d x t 0s n u s t ) c - d ( e m i t p u t e s t u p n i i d x r 0 7s n h t ) q - c ( e m i t d l o h t u p n i i d x r 0 9s n l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m w t ) h n i ( h t d i w ) " h " ( h g i h t u p n i i t n i 0 5 2s n w t ) l n i ( h t d i w ) " l " ( w o l t u p n i i t n i 0 5 2s n table 20.55 timer b input (pulse period measurement mode) table 20.56 timer b input (pulse width measurement mode) table 20.57 a/d trigger input table 20.58 serial i/o table 20.59 external interrupt inti input v cc = 5v
20. electrical characteristics (v-version) page 353 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r timing requirements (v cc =5v, v ss =0v, at topr=-40 to 125 c unless otherwise specified) table 20.60 multi-master i 2 c bus line high-speed clock mode max. min. bus free time the hold time in start condition the hold time in scl clock "0" status s s s tbuf thd;sta tlow parameter symbol unit tr thigh thd;dat ns s s data hold time the hold time in scl clock "1" status scl, sda signals' rising time 1.3 0.6 1.3 0 0.6 20+0.1cb tf scl, sda signals' falling time t su ;dat data setup time t su ;sta the setup time in restart condition t su ;sto stop condition setup time standard clock mode max. min. 4.7 4.0 4.7 0 4.0 250 4.7 4.0 1000 300 100 0.6 20+0.1cb 0.6 300 300 0.9 ns ns s s v cc = 5v
20. electrical characteristics (v-version) page 354 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 20.7 timing diagram (1) v cc = 5v tai in input tai out input in event counter mode t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t h(t in ? up) t su(up ? t in ) tai in input (when count on falling edge) tai in input (when count on rising edge) tai out input (counter increment/ decrement input) tbi in input t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) ad trg input t c(ta) t su(ta in -ta out ) t su(ta out -ta in ) t su(ta out -ta in ) two-phase pulse input in event counter mode tai in input tai out input t su(ta in -ta out ) xin input tw(h) tw(l) tr tf tc
20. electrical characteristics (v-version) page 355 ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r figure 20.8 timing diagram (2) figure 20.9 timing diagram (3) v cc = 5v v cc = 5v t su(d ? c) clki txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c ? q) t h(c ? d) t h(c ? q) inti input t buf t hd:sta t hd:dta t low t r t f t high tsu :dat tsu :sta t hd:sta tsu :sto scl p s sr p sda
page 356 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions 21. precautions 21.1 sfr 21.1.1 for 80-pin package set the ifsr20 bit in the ifsr2a register to 1 after reset and set bits pacr2 to pacr0 in the pacr register to 011 2 . 21.1.2 for 64-pin package set the ifsr20bit in the ifsr2a register to 1 after reset and set bits pacr2 to pacr0 in the pacr register to 010 2 . 21.1.3 register setting immediate values should be set in the registers containing write-only bits. when establishing a new value by modifying a previous value, write the previous value into ram as well as the register. change the contents of the ram and then transfer the new value to the register.
page 357 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions 21.2 clock generation circuit 21.2.1 pll frequency synthesizer stabilize supply voltage so that the standard of the power supply ripple is met. figure 21.1 voltage fluctuation timing 10 typ. max. u n i t p a r a m e t e r f ( r i p p l e ) p o w e r s u p p l y r i p p l e a l l o w a b l e f r e q u e n c y ( v c c ) s y m b o l min. standa rd k h z p o w e r s u p p l y r i p p l e a l l o w a b l e d a m p l i t u d e v o l t a g e p o w e r s u p p l y r i p p l e r i s i n g / f a l l i n g g r a d i e n t ( v c c = 5 v ) ( v c c = 3 v ) ( v c c = 5 v ) ( v c c = 3 v ) v p - p ( r i p p l e ) v c c ( | d v / d t | ) 0.5 0.3 0.3 0.3 v v / m s v / m s v v p - p ( r i p p l e ) f (ripple) v c c f ( r i p p l e ) p o w e r s u p p l y r i p p l e a l l o w a b l e f r e q u e n c y ( v c c ) v p - p ( r i p p l e ) p o w e r s u p p l y r i p p l e a l l o w a b l e a m p l i t u d e v o l t a g e
page 358 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions 21.2.2 power control 1. when exiting stop mode by hardware reset, the device will startup using the on-chip oscillator. 2. set the mr0 bit in the taimr register(i=0 to 4) to 0 (pulse is not output) to use the timer a to exit stop mode. 3. when entering wait mode, insert a jmp.b instruction before a wait instruction. do not excute any instructions which can generate a write to ram between the jmp.b and wait instructions. disable the dma transfers, if a dma transfer may occur between the jmp.b and wait instructions. after the wait instruction, insert at least 4 nop instructions. when entering wait mode, the instruction queue reads ahead the instructions following wait, and depending on timing, some of these may execute before the mcu enters wait mode. program example when entering wait mode program example: jmp.b l1 ; insert jmp.b instruction before wait instruction l1: fset i ; wait ; enter wait mode nop ; more than 4 nop instructions nop nop nop 4. when entering stop mode, insert a jmp.b instruction immediately after executing an instruction which sets the cm10 bit in the cm1 register to 1, and then insert at least 4 nop instructions. when entering stop mode, the instruction queue reads ahead the instructions following the instruction which sets the cm10 bit to 1 (all clock stops), and, some of these may execute before the mcu enters stop mode or before the interrupt routine for returning from stop mode. program example when entering stop mode program example: fset i bset cm10 ; enter stop mode jmp.b l2 ; insert jmp.b instruction l1: nop ; more than 4 nop instructions nop nop nop
page 359 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions 5. wait until the main clock oscillation stabilization time, before switching the cpu clock source to the main clock. similarly, wait until the sub clock oscillates stably before switching the cpu clock source to the sub clock. 6. suggestions to reduce power consumption (a) ports the processor retains the state of each i/o port even when it goes to wait mode or to stop mode. a current flows in active i/o ports. a dash current may flow through the input ports in high impedance state, if the input is floating. when entering wait mode or stop mode, set non-used ports to input and stabilize the potential. (b) a/d converter when a/d conversion is not performed, set the vcut bit in adicon1 register to 0 (no vref connec- tion). when a/d conversion is performed, start the a/d conversion at least 1 s or longer after setting the vcut bit to 1 (vref connection). (c) stopping peripheral functions use the cm0 register cm02 bit to stop the unnecessary peripheral functions during wait mode. however, because the peripheral function clock (f c32 ) generated from the sub-clock does not stop, this measure is not conducive to reducing the power consumption of the chip. if low speed mode or low power dissipation mode is to be changed to wait mode, set the cm02 bit to 0 (do not peripheral function clock stopped when in wait mode), before changing wait mode. (d) switching the oscillation-driving capacity set the driving capacity to ? low ? when oscillation is stable. (e)low power consumption control register follow the procedure below to set the lpcc0 and lpcc1 registers in order to reduce power consumtion. 1) set the lpcc0 register to 0021 16 2) set the prc0 bit in the prcr register to 1 3) set the lpcc13 bit in the lpcc1 register to 1 4) set the prc0 bit to 0 example: mov.b #00100001b, lpcc0 ; bset prc0 ; write enabled mov.b #00001000b, lpcc1 ; bclr prc0 ; write disabled
page 360 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions low-power consumption control register 0 low-power consumption control register 1 (1) b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 bit symbol bit name function rw lpcc00 reserved bit set to 1 rw (b4 - b1) reserved bit set to 0 rw lpcc05 reserved bit set to 1 rw (b7 - b6) reserved bit set to 0 rw bit symbol bit name function rw (b2 - b0) reserved bit set to 0 rw lpcc13 reserved bit set to 1 rw nothing is assigned. if necessary, set to 0. (b7 - b4) when read, the content is 0 note: 1. rewrite the lpcc1 register after setting the prc0 bit in the prcr register to 1 (wirte enabled). symbol address after reset lpcc1 025f 16 00 16 symbol address after reset lpcc0 0210 16 x0000000 2 figure 21.2 lpcc0 register and lpcc1 register
page 361 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions 21.3 protection set the prc2 bit to 1 (write enabled) and then write to any address, and the prc2 bit will be cleared to 0 (write protected). the registers protected by the prc2 bit should be changed in the next instruction after setting the prc2 bit to 1. make sure no interrupts or dma transfers will occur between the instruction in which the prc2 bit is set to 1 and the next instruction.
page 362 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions 21.4 interrupts 21.4.1 reading address 00000 16 do not read the address 00000 16 in a program. when a maskable interrupt request is accepted, the cpu reads interrupt information (interrupt number and interrupt request priority level) from the address 00000 16 during the interrupt sequence. at this time, the ir bit for the accepted interrupt is cleared to 0. if the address 00000 16 is read in a program, the ir bit for the interrupt which has the highest priority among the enabled interrupts is cleared to 0. this causes a problem that the interrupt is canceled, or an unexpected interrupt request is generated. 21.4.2 setting the sp set any value in the sp(usp, isp) before accepting an interrupt. the sp(usp, isp) is cleared to 0000 16 after reset. therefore, if an interrupt is accepted before setting any value in the sp(usp, isp), the pro- gram may go out of control. _______ 21.4.3 nmi interrupt _______ _______ 1. the nmi interrupt is invalid after reset. the nmi interrupt becomes effective by setting the pm24 bit in _______ the pm2 register to ? 1 ? . set the pm24 bit to "1" when a high-level signal ("h") is applied to the nmi pin. _______ _______ if the pm24 bit is set to "1" when a low-level signal ("l") is applied, nmi interrupt is generated. once nmi interrupt is enabled, it will not be disabled unless a reset is applied. _______ 2. the input level of the nmi pin can be read by accessing the p8_5 bit in the p8 register. _______ _______ 3. when selecting nmi function, stop mode cannot be entered into while input on the nmi pin is low. this _______ is because while input on the nmi pin is low the cm1 register ? s cm10 bit is fixed to 0. _______ _______ 4. when selecting nmi function, do not go to wait mode while input on the nmi pin is low. this is because _______ when input on the nmi pin goes low, the cpu stops but cpu clock remains active; therefore, the current consumption in the chip does not drop. in this case, normal condition is restored by an interrupt gener- ated thereafter. _______ _______ 5. when selecting nmi function, the low and high level durations of the input signal to the nmi pin must each be 2 cpu clock cycles + 300 ns or more. _______ 6. when using the nmi interrupt for exiting stop mode, set the nddr register to ff 16 (disable digital debounce filter) before entering stop mode. 21.4.4 changing the interrupt generate factor if the interrupt generate factor is changed, the ir bit in the interrupt control register for the changed interrupt may inadvertently be set to 1 (interrupt requested). if you changed the interrupt generate factor for an interrupt that needs to be used, be sure to clear the ir bit for that interrupt to 0 (interrupt not requested). ? changing the interrupt generate factor ? referred to here means any act of changing the source, polarity or timing of the interrupt assigned to each software interrupt number. therefore, if a mode change of any peripheral function involves changing the generate factor, polarity or timing of an interrupt, be sure to clear the ir bit for that interrupt to 0 (interrupt not requested) after making such changes. refer to the description of each peripheral function for details about the interrupts from peripheral functions. figure 21.3 shows the procedure for changing the interrupt generate factor.
page 363 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions ______ 21.4.5 int interrupt 1. either an ? l ? level of at least t w ( inh ) or an ? h ? level of at least t w ( inl ) width is necessary for the signal input to pins int 0 through int 5 regardless of the cpu operation clock. 2. if the pol bit in registers int0ic to int5ic or bits ifsr7 to ifsr0 in the ifsr register are changed, the ir bit may inadvertently set to 1 (interrupt requested). be sure to clear the ir bit to 0 (interrupt not requested) after changing any of those register bits. 3. when using the int 5 interrupt for exiting stop mode, set the p17ddr register to ff 16 (disable digital debounce filter) before entering stop mode. figure 21.3 procedure for changing the interrupt generate factor notes: 1.the above settings must be executed individually. do not execute two or more settings simultaneously (using one instruction). 2. use the i flag for the inti interrupt (i = 0 to 5). for the interrupts from peripheral functions other than the inti interrupt, turn off the peripheral function that is the source of the interrupt in order not to generate an interrupt request before changing the interrupt generate factor. in this case, if the maskable interrupts can all be disabled without causing a problem, use the i flag. otherwise, use the corresponding bits ilvl2 to ilvl0 for the interrupt whose interrupt generate factor is to be changed. 3. refer to 21.4.6 rewrite the interrupt control register for details about the instructions to use and the notes to be taken for instruction execution. changing the interrupt source disable interrupts (2,3) use the mov instruction to clear the ir bit to 0 (interrupt not requested) (3) change the interrupt generate factor (including a mode change of peripheral function) enable interrupts (2,3) end of change ir bit: a bit in the interrupt control register for the interrupt whose interrupt generate factor is to be changed
page 364 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions 21.4.7 watchdog timer interrupt initialize the watchdog timer after the watchdog timer interrupt occurs. 21.4.6 rewrite the interrupt control register (1) the interrupt control register for any interrupt should be modified in places where no requests for that interrupt may occur. otherwise, disable the interrupt before rewriting the interrupt control register. (2) to rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with the instruction to be used. changing any bit other than the ir bit if while executing an instruction, a request for an interrupt controlled by the register being modified occurs, the ir bit in the register may not be set to 1 (interrupt requested), with the result that the interrupt request is ignored. if such a situation presents a problem, use the instructions shown below to modify the register. usable instructions: and, or, bclr, bset changing the ir bit depending on the instruction used, the ir bit may not always be cleared to 0 (interrupt not requested). therefore, be sure to use the mov instruction to clear the ir bit. (3) when using the i flag to disable an interrupt, refer to the sample program fragments shown below as you set the i flag. (refer to (2) for details about rewrite the interrupt control registers in the sample program fragments.) examples 1 through 3 show how to prevent the i flag from being set to 1 (interrupts enabled) before the interrupt control register is rewrited, due to the internal bus and the instruction queue buffer. example 1: using the nop instruction to keep the program waiting until the interrupt control register is modified int_switch1: fclr i ; disable interrupts and.b #00h, 0055h ;set the ta0ic register to 00 16 nop ; nop fset i ; enable interrupts the number of nop instruction is as follows. pm20 = 1 (1 wait) : 2, pm20 = 0 (2 waits): 3 example 2:using the dummy read to keep the fset instruction waiting int_switch2: fclr i ; disable interrupts and.b #00h, 0055h ; set the ta0ic register to 00 16 mov.w mem, r0 ; dummy read fset i ; enable interrupts example 3:using the popc instruction to changing the i flag int_switch3: pushc flg fclr i ; disable interrupts and.b #00h, 0055h ; set the ta0ic register to 00 16 popc flg ; enable interrupts
page 365 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions 21.5 dmac 21.5.1 write to dmae bit in dmicon register when both of the conditions below are met, follow the steps below. (a) conditions ? the dmae bit is set to 1 again while it remains set (dmai is in an active state). ? a dma request may occur simultaneously when the dmae bit is being written. (b) procedure (1) write 1 to the dmae bit and dmas bit in dmicon register simultaneously (1) . (2) make sure that the dmai is in an initial state (2) in a program. if the dmai is not in an initial state, the above steps should be repeated. notes: 1. the dmas bit remains unchanged even if 1 is written. however, if 0 is written to this bit, it is set to 0 (dma not requested). in order to prevent the dmas bit from being modified to 0, 1 should be written to the dmas bit when 1 is written to the dmae bit. in this way the state of the dmas bit immediately before being written can be maintained. similarly, when writing to the dmae bit with a read-modify-write instruction, 1 should be written to the dmas bit in order to maintain a dma request which is generated during execution. 2. read the tcri register to verify whether the dmai is in an initial state. if the read value is equal to a value which was written to the tcri register before dma transfer start, the dmai is in an initial state. (if a dma request occurs after writing to the dmae bit, the value written to the tcri register is 1.) if the read value is a value in the middle of transfer, the dmai is not in an initial state.
page 366 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions 21.6 timer 21.6.1 timer a 21.6.1.1 timer a (timer mode) 1. the timer remains idle after reset. set the mode, count source, counter value, etc. using the taimr (i = 0 to 4) register and the tai register before setting the tais bit in the tabsr register to 1 (count starts). always make sure the taimr register is modified while the tais bit remains 0 (count stops) regard- less whether after reset or not. 2. while counting is in progress, the counter value can be read out at any time by reading the tai register. however, if the tai register is read at the same time the counter is reloaded, the read value is always ffff 16 . if the tai register is read after setting a value in it, but before the counter starts counting, the read value is the one that has been set in the register. _____ 3. if a low-level signal is applied to the sd pin when the ivpcr1 bit in the tb2sc register is set to 1 _____ (three-phase output forcible cutoff by input on sd pin enabled), the ta1 out , ta2 out and ta4 out pins go to a high-impedance state. 21.6.1.2 timer a (event counter mode) 1. the timer remains idle after reset. set the mode, count source, counter value, etc. using the taimr (i = 0 to 4) register, the tai register, the udf register, bits tazie, ta0tgl, and ta0tgh in the onsf register and the trgsr register before setting the tais bit in the tabsr register to 1 (count starts). always make sure bits tazie, ta0tgl, and ta0tgh in the taimr register, the udf register, the onsf register, and the trgsr register are modified while the tais bit remains 0 (count stops) regardless whether after reset or not. 2. while counting is in progress, the counter value can be read out at any time by reading the tai register. however, if the tai register is read at the same time the counter is reloaded, the read value is always ffff 16 when the timer counter underflows and 0000 16 when the timer counter overflows. if the tai register is read after setting a value in it, but before the counter starts counting, the read value is the one that has been set in the register. _____ 3. if a low-level signal is applied to the sd pin when the ivpcr1 bit in the tb2sc register is set to 1 _____ (three-phase output forcible cutoff by input on sd pin enabled), the ta1 out , ta2 out and ta4 out pins go to a high-impedance state.
page 367 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions 21.6.1.3 timer a (one-shot timer mode) 1. the timer remains idle after reset. set the mode, count source, counter value, etc. using the taimr (i = 0 to 4) register, the tai register, bits ta0tgl and ta0tgh in the onsf register and the trgsr register before setting the tais bit in the tabsr register to 1 (count starts). always make sure bits ta0tgl and ta0tgh in the taimr register, the onsf register, and the trgsr register are modified while the tais bit remains 0 (count stops) regardless whether after reset or not. 2. when setting tais bit to 0 (count stop), the followings occur: ? a counter stops counting and a content of reload register is reloaded. ? tai out pin outputs ? l ? . ? after one cycle of the cpu clock, the ir bit in taiic register is set to 1 (interrupt request). 3. output in one-shot timer mode synchronizes with a count source internally generated. when the external trigger has been selected, a maximun delay of one cycle of the count source occurs be- tween the trigger input to tai in pin and output in one-shot timer mode. 4. the ir bit is set to 1 when timer operation mode is set with any of the following procedures: ? select one-shot timer mode after reset. ? change an operation mode from timer mode to one-shot timer mode. ? change an operation mode from event counter mode to one-shot timer mode. to use the timer ai interrupt (the ir bit), set the ir bit to 0 after the changes listed above have been made. 5. when a trigger occurs while the timer is counting, the counter reloads the reload register value, and continues counting after a second trigger is generated and the counter is decremented once. to generate a trigger while counting, space more than one cycle of the timer count source from the first trigger and generate again. 6. when selecting the external trigger for the count start conditions in timer a one-shot timer mode, do not generate an external trigger 300ns before the count value of timer a is set to 0000 16 . the one- shot timer may stop counting. 7. _____ if a low-level signal is applied to the sd pin when the ivpcr1 bit in the tb2sc register is set to 1 _____ (three-phase output forcible cutoff by input on sd pin enabled), the ta1 out , ta2 out and ta4 out pins go to a high-impedance state.
page 368 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions 21.6.1.4 timer a (pulse width modulation mode) 1. the timer remains idle after reset. set the mode, count source, counter value, etc. using bits ta0tgl and ta0tgh in the taimr (i = 0 to 4) register, the tai register, the onsf register and the trgsr register before setting the tais bit in the tabsr register to 1 (count starts). always make sure bits ta0tgl and ta0tgh in the taimr register, the onsf register and the trgsr register are modified while the tais bit remains 0 (count stops) regardless whether after reset or not. 2. the ir bit is set to 1 when setting a timer operation mode with any of the following procedures: ? select the pwm mode after reset. ? change an operation mode from timer mode to pwm mode. ? change an operation mode from event counter mode to pwm mode. to use the timer ai interrupt (interrupt request bit), set the ir bit to 0 by program after the above listed changes have been made. 3. when setting tais register to 0 (count stop) during pwm pulse output, the following action occurs: ? stop counting. ? when tai out pin is output ? h ? , output level is set to ? l ? and the ir bit is set to 1. ? when tai out pin is output ? l ? , both output level and the ir bit remains unchanged. _____ 4. if a low-level signal is applied to the sd pin when the ivpcr1 bit in the tb2sc register is set to 1 _____ (three-phase output forcible cutoff by input on sd pin enabled), the ta1 out , ta2 out and ta4 out pins go to a high-impedance state.
page 369 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions 21.6.2 timer b 21.6.2.1 timer b (timer mode) 1. the timer remains idle after reset. set the mode, count source, counter value, etc. using the tbimr (i = 0 to 2) register and tbi register before setting the tbis bit in the tabsr register to 1 (count starts). always make sure the tbimr register is modified while the tbis bit remains 0 (count stops) regard- less whether after reset or not. 2. the counter value can be read out at any time by reading the tbi register. however, if this register is read at the same time the counter is reloaded, the read value is always ffff 16 . if the tbi register is read after setting a value in it but before the counter starts counting, the read value is the one that has been set in the register. 21.6.2.2 timer b (event counter mode) 1. the timer remains idle after reset. set the mode, count source, counter value, etc. using the tbimr (i = 0 to 2) register and tbi register before setting the tbis bit in the tabsr register to 1 (count starts). always make sure the tbimr register is modified while the tbis bit remains 0 (count stops) regard- less whether after reset or not. 2. the counter value can be read out at any time by reading the tbi register. however, if this register is read at the same time the counter is reloaded, the read value is always ffff 16 . if the tbi register is read after setting a value in it but before the counter starts counting, the read value is the one that has been set in the register. 21.6.2.3 timer b (pulse period/pulse width measurement mode) 1. the timer remains idle after reset. set the mode, count source, etc. using the tbimr (i = 0 to 2) register before setting the tbis bit in the tabsr or the tbsr register to 1 (count starts). always make sure the tbimr register is modified while the tbis bit remains 0 (count stops) regard- less whether after reset or not. to clear the mr3 bit to 0 by writing to the tbimr register while the tbis bit is set to 1 (count starts), be sure to write the same value as previously written to bits tm0d0, tm0d1, mr0, mr1, tck0, and tck1 and a 0 to the mr2 bit. 2. the ir bit in tbiic register (i=0 to 2) goes to 1 (interrupt request), when an effective edge of a measurement pulse is input or timer bi is overflowed. the factor of interrupt request can be deter- mined by use of the mr3 bit in tbimr register within the interrupt routine. 3. if the source of interrupt cannot be identified by the mr3 bit such as when the measurement pulse input and a timer overflow occur at the same time, use another timer to count the number of times timer b has overflowed. 4. to set the mr3 bit to 0 (no overflow), set tbimr register with setting the tbis bit to 1 and counting the next count source after setting the mr3 bit to 1 (overflow). 5. use the ir bit in tbiic register to detect only overflows. use the mr3 bit only to determine the interrupt factor within the interrupt routine.
page 370 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions 6. when a count is started and the first effective edge is input, an undefined value is transferred to the reload register. at this time, timer bi interrupt request is not generated. 7. a value of the counter is undefined at the beginning of a count. mr3 may be set to 1 and timer bi interrupt request may be generated between a count start and an effective edge input. 8. for pulse width measurement, pulse widths are successively measured. use program to check whether the measurement result is an ? h ? level width or an ? l ? level width. 21.6.3 three-phase motor control timer function when the ivpcr1 bit in the tb2sc register is set to 1 (three-phase output forced cutoff by sd pin input (high-impedance) enabled), the inv03 bit in the invc0 register is set to 1 (three-phase motor control _____ timer output enabled), and a low-level ("l") signal is applied to the sd pin while a three-phase pwm ___ ___ ___ signal is output, the mcu is forced to cutoff and pins u, u, v, v, w, and w are placed in a high-impedance state and the inv03 bit is set to 0 (three-phase motor control timer output disabled). ___ ___ ___ to resume the three-phase pwm signal output from pins u, u, v, v, w, and w, set the inv03 bit to 1 and _____ the ivpcr1 bit to 0 (three-phase output forced cutoff disabled) after the sd pin level becomes "h". then set the ivpcr1 bit to 1 (three-phase output forced cutoff enabled) in order to enable the three-phase output forced cutoff function by input to the sd pin again. _____ the inv03 bit cannot be set to 1 while an "l" signal is input to the sd pin. to set the inv03 bit to 1 after forcible cutoff, write 1 to the inv03 bit and read the bit to ensure that it is set to 1 by program. then set the ivpcr1 bit to 1 after setting it to 0.
page 371 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions 21.7 timer s 21.7.1 rewrite the g1ir register bits in the g1ir register are not automatically set to 0 (no interrupt requested) even if a requested inter- rupt is acknowledged. set each bit to 0 by program after the interrupt requests are verified. the ic/oc interrupt is generated when any bit in the g1ir register is set to 1 (interrupt requested) after all the bits are set to 0. if conditions to generate an interrupt are met when the g1ir register holds the value other than 00 16 , the ic/oc interrupt request will not be generated. in order to enable an ic/oc interrupt request again, clear the g1ir register to 00 16 . use the following instructions to set each bit in the g1ir register to 0. subject instructions: and, bclr figure 21.4 shows an example of ic/oc interrupt i processing. figure 21.4 ic/oc interrupt i flow chart interrupt (1) set the g1iri bit to "0" set the g1irj bit to "0" process channel i waveform generating interrupt process channel j time measurement interrupt interrupt completed notes: 1. example for the interrupt operation when using the channel i waveform generating interrupt and channel j time measurement interrupt. g1iri=1 ? g1irj=1 ? g1ir=0 ? no no no yes yes yes
page 372 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions 21.7.2 rewrite the icociic register when the interrupt request to the icociic register is generated during the instruction process, the ir bit may not be set to 1 (interrupt requested) and the interrupt request may not be acknowledged. at that time, when the bit in the g1ir register is held to 1 (interrupt requested), the following ic/oc interrupt request will not be generated. when changing the icociic register settiing, use the following instruction. subject instructions: and, or, bclr, bset when initializing timer s, change the icociic register setting with the request again after setting the iociic and g1ir registers to 00 16 . 21.7.3 waveform generating function 1. if the bts bit in the g1bcr1 register is set to 0 (base timer is reset) when the waveform is generating and the base timer is stopped counting, the waveform output pin keeps the same output level. the output level will be changed when the base timer and the g1poj register match the setting value next time after the base timer starts counting again. 2. if the g1pocrj register is set when the waveform is generated, the same setting value of the ivl bit is applied to the waveform generating pin. do not set the g1pocrj register when the waveform is generat- ing. 3. when the rst1 bit in the g1bcr1 register is set to 1 (the base timer is reset by matching the g1po0 register), the base timer is reset after two clock cycles of f bt1 when the base timer value matches the g1po0 register value. a high-level ("h") signal is applied to the outc10 pin between the base timer value match to the base timer reset. 21.7.4 ic/oc base timer interrupt if the mcu is operated in the combination selected from tabl e 1 for use when the rst4 bit in the g1bcr0 register is set to 1 (reset the base timer that matches the g1btrr register) to reset the base timer, an ic/oc base timer interrupt request is generated twice. r e t s i g e r 0 r c b 1 g e h t n i t i b t ir e t s i g e r r r t b 1 g ) s w o l f r e v o r e m i t e s a b e h t n i 5 1 t i b ( 0 f f f 7 0 6 1 e f f f 0 o t 6 1 ) s w o l f r e v o r e m i t e s a b e h t n i 4 1 t i b ( 1 f f f 3 0 6 1 e f f f 0 o t 6 1 r o f f f b 0 6 1 e f f f 0 o t 6 1 table 21.1 uses of it bit in the g1bcr0 register and g1btrr register the second ic/oc base timer interrupt request is generated because the base timer overflow request is generated after one fbt1 clock cycle as soon as the base timer is reset. one of the following conditions must be met in order not to generate the ic/oc base timer interrupt request twice: 1) when the rst4 bit is set to 1, set the g1btrr register with a combination other than what is listed in table 21.1 . 2) do not reset the base timer by matching the g1btrr register. reset the base timer by matching the g1p00 register. in other words, do not set the rst4 bit to 1 to reset the base timer. set the rst1 bit in the g1bcr1 register to 1 (reset the base timer that matches the g1p00 register).
page 373 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions 21.8 serial i/o 21.8.1 clock-synchronous serial i/o 21.8.1.1 transmission/reception _______ ________ 1. with an external clock selected, and choosing the rts function, the output level of the rtsi pin goes to ? l ? when the data-receivable status becomes ready, which informs the transmission side ________ that the reception has become ready. the output level of the rtsi pin goes to ? h ? when reception ________ ________ starts. so if the rtsi pin is connected to the ctsi pin on the transmission side, the circuit can _______ transmission and reception data with consistent timing. with the internal clock, the rts function has no effect. _____ 2. i f a low-level signal is applied to the sd pin when the ivpcr1 bit in the tb2sc register is set to 1 _____ (three-phase output forcible cutoff by input on sd pin enabled), the p7 3 /rts 2 /txd1(when the u1map bit in pacr register is 1) and clk 2 pins go to a high-impedance state. 21.8.1.2 transmission when an external clock is selected, the conditions must be met while if the ckpol bit in the uic0 register is set to 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the high state; if the ckpol bit in the uic0 register is set to 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state. ? the te bit in uic1 register is set to 1 (transmission enabled) ? the ti bit in uic1 register is set to 0 (data present in uitb register) _______ _______ ? if cts function is selected, input on the ctsi pin is set to ? l ? 21.8.1.3 reception 1. in operating the clock-synchronous serial i/o, operating a transmitter generates a shift clock. fix settings for transmission even when using the device only for reception. dummy data is output to the outside from the txdi pin when receiving data. 2. when an internal clock is selected, set the te bit in the uic1 register (i = 0 to 2) to 1 (transmission enabled) and write dummy data to the uitb register, and the shift clock will thereby be generated. when an external clock is selected, set the te bit in the uic1 register (i = 0 to 2) to 1 and write dummy data to the uitb register, and the shift clock will be generated when the external clock is fed to the clki input pin. 3. when successively receiving data, if all bits of the next receive data are prepared in the uarti receive register while the re bit in the uic1 register (i = 0 to 2) is set to 1 (data present in the uirb register), an overrun error occurs and the uirb register oer bit is set to 1 (overrun error occurred). in this case, because the content of the uirb register is undefined, a corrective measure must be taken by programs on the transmit and receive sides so that the valid data before the overrun error occurred will be retransmitted. note that when an overrun error occurred, the siric register ir bit does not change state. 4. to receive data in succession, set dummy data in the lower-order byte of the uitb register every time reception is made. 5. when an external clock is selected, make sure the external clock is in high state if the ckpol bit is set to 0, and in low state if the ckpol bit is set to 1 before the following conditions are met: ? the re bit in the uic1 register is set to 1 (reception enabled) ? the te bit in the uic1 register is set to 1 (transmission enabled) ? the ti bit in the uic1 register= 0 (data present in the uitb register)
page 374 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions 21.8.2 uart mode 21.8.2.1 special mode 1 (i 2 c bus mode) when generating start, stop and restart conditions, set the stspsel bit in the u2smr4 register to 0 and wait for more than half cycle of the transfer clock before setting each condition generate bit (stareq, rstareq and stpreq) from 0 to 1. 21.8.2.2 special mode 2 _____ if a low-level signal is applied to the sd pin when the ivpcr1 bit in the tb2sc register is set to 1 _____ (three-phase output forcible cutoff by input on sd pin enabled), the rts 2 and clk 2 pins go to a high- impedance state. 21.8.2.3 special mode 4 (sim mode) a transmit interrupt request is generated by setting the u2c1 register u2irs bit to 1 (transmission complete) and u2ere bit to 1 (error signal output) after reset. therefore, when using sim mode, be sure to clear the ir bit to 0 (no interrupt request) after setting these bits. 21.8.3 si/o3, si/o4 the souti default value which is set to the souti pin by the smi7 bit approximately 10ns may be output when changing the smi3 bit from 0 (i/o port) to 1 (souti output and clkfunction) while the smi2 bit in the sic (i=3 and 4) to 0 (souti output) and the smi6 bit is set to 1 (internal clock). and then the souti pin is held high-impedance. if the level which is output from the souti pin is a problem when changing the smi3 bit from 0 to 1, set the default value of the souti pin by the smi7 bit.
page 375 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions mcu v cc v ss av cc av ss v ref ani c4 c1 c2 c3 v cc v cc ani: ani, an0i, an2i (i = 0 to 7), and an3i ( i= 0 to 2) notes: 1. c1 0.47 f, c2 0.47 f, c3 100 pf, c4 0.1 f (reference) 2. use thick and shortest possible wiring to connect capacitors. 21.9 a/d converter 1. set registers adcon0 (except bit 6), adcon1, adcon2 and adtrgcon when a/d conversion is stopped (before a trigger occurs). 2. when the vcut bit in adcon1 register is changed from 0 (vref not connected) to 1 (vref connected), start a/d conversion after passing 1 s or longer. 3. to prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert capacitors between the av cc , v ref , and analog input pins (an i , an0 i , an2 i (i=0 to 7), and an3 i (i=0 to 2)) each and the av ss pin. similarly, insert a capacitor between the v cc1 pin and the v ss pin. figure 21.5 is an example connection of each pin. 4. make sure the port direction bits for those pins that are used as analog inputs are set to 0 (input mode). also, if the tgr bit in the adcon0 register is set to 1 (external trigger), make sure the port direction bit ___________ for the ad trg pin is set to 0 (input mode). 5. when using key input interrupts, do not use any of the four an 4 to an 7 pins as analog inputs. (a key input interrupt request is generated when the a/d input voltage goes low.) 6. the ad frequency must be 10 mhz or less. without sample-and-hold function, limit the ad frequency to 250kh z or more. with the sample and hold function, limit the ad frequency to 1mh z or more. 7. when changing an a/d operation mode, select analog input pin again in bits ch2 to ch0 in the adcon0 register and bits scan1 to scan0 in the adcon1 register. figure 21.5 use of capacitors to reduce noise
page 376 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions 8. if the cpu reads the adi register (i = 0 to 7) at the same time the conversion result is stored in the adi register after completion of a/d conversion, an incorrect value may be stored in the adi register. this problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for cpu clock. ? when operating in one-shot, single-sweep mode, simultaneous sample sweep mode, delayed trig- ger mode 0 or delayed trigger mode 1: check to see that a/d conversion is completed before reading the target adi register. (check the ir bit in the adic register to see if a/d conversion is completed.) ? when operating in repeat mode or repeat sweep mode 0 or 1: use the main clock for cpu clock directly without dividing it. 9. if a/d conversion is forcibly terminated while in progress by setting the adst bit in the adcon0 register to 0 (a/d conversion halted), the conversion result of the a/d converter is undefined. the contents of adi registers irrelevant to a/d conversion may also become undefined. if while a/d conver- sion is underway the adst bit is cleared to 0 in a program, ignore the values of all adi registers. 10. when setting the adst bit in the adcon register to 0 and terminating forcefully by a program in single sweep conversion mode, a/d delayed trigger mode 0 and a/d delayed trigger mode 1 during a/d converting operation, the a/d interrupt request may be generated. if this causes a problem, set the adst bit to 0 after an interrupt is disabled.
page 377 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions 21.10 multi-master i 2 c bus interface 21.10.1 writing to the s00 register when the start condition is not generated, the scl pin may output the short low-signal ("l") by setting the s00 register. set the register when the scl pin outputs an "l" signal. 21.10.2 al flag when the arbitration lost is generated and the al flag in the s10 register is set to 1 (detected), the al flag can be cleared to 0 (not detected) by writing a transmit data to the s00 register. the al flag should be cleared at the timing when master geneates the start condition to start a new transfer.
page 378 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions 21.11 programmable i/o ports _____ 1. if a low-level signal is applied to the sd pin when the ivpcr1 bit in the tb2sc register is set to 1 _____ (three-phase output forcible cutoff by input on sd pin enabled), the p7 2 to p7 5 , p8 0 and p8 1 pins go to a high-impedance state. 2. the input threshold voltage of pins differs between programmable input/output ports and peripheral functions. therefore, if any pin is shared by a programmable input/output port and a peripheral function and the input level at this pin is outside the range of recommended operating conditions v ih and v il (neither ? high ? nor ? low ? ), the input level may be determined differently depending on which side ? the program- mable input/output port or the peripheral function ? is currently selected. 3.when the sm32 bit in the s3c register is set to 1, the p3 2 pin goes to high-impedance state. when the sm42 bit in the s4c register is set to 1, the p9 6 pin goes to high-imepdance state. 4. when the inv03 bit in the invc0 register is 1(three-phase motor control timer output enabled), an "l" _______ _____ input on the p8 5 /nmi/sd pin, has the following effect. ? when the tb2sc register ivpcr1 bit is set to 1 (three-phase output forcible cutoff by input on _____ __ __ ___ sd pin enabled), the u/ u/ v/ v/ w/ w pins go to a high-impedance state. ? when the tb2sc register ivpcr1 bit is set to 0 (three-phase output forcible cutoff by input on _____ __ __ ___ sd pin disabled), the u/ u/ v/ v/ w/ w pins go to a normal port. therefore, the p8 5 pin can not be used as programmable i/o port when the inv03 bit is set to 1. _____ _______ _____ when the sd function isn't used, set to 0 (input) in pd8 5 and pullup to h in the p8 5 /nmi/sd pin from outside.
page 379 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions 21.12 electric characteristic differences between mask rom and flash memory version flash memory version and mask rom version may have different characteristics, operating margin, noise tolerated dose, noise width dose in electrical characteristics due to internal rom, different layout pattern, etc. when switching to the mask rom version, conduct equivalent tests as system evaluation tests con- ducted in the flush memory version.
page 380 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions 21.13 mask rom version 21.13.1 internal rom area in the masked rom version, do not write to internal rom area. writing to the area may increase power consumption. 21.13.2 reserved bit the b3 to b0 in addresses 0fffff 16 are reserved bits. set these bits to 1111 2 .
page 381 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions 21.14 flash memory version 21.14.1 functions to inhibit rewriting flash memory rewrite id codes are stored in addresses 0fffdf 16 , 0fffe3 16 , 0fffeb 16 , 0fffef 16 , 0ffff3 16 , 0ffff7 16 , and 0ffffb 16 . if wrong data are written to theses addresses, the flash memory cannot be read or written in standard serial i/o mode. the romcp register is mapped in address 0fffff 16 . if wrong data is written to this address, the flash memory cannot be read or written in parallel i/o mode. in the flash memory version of mcu, these addresses are allocated to the vector addresses ("h") of fixed vectors. the b3 to b0 in address 0fffff 16 are reserved bits. set these bits to 1111 2 . 21.14.2 stop mode when the mcu enters stop mode, execute the instruction which sets the cm10 bit to 1 (stop mode) after setting the fmr01 bit to 0 (cpu rewrite mode disabled) and disabling the dma transfer. 21.14.3 wait mode when the mcu enters wait mode, excute the wait instruction after setting the fmr01 bit to 0 (cpu rewrite mode disabled). 21.14.4 low power dissipation mode, on-chip oscillator low power dissipation mode if the cm05 bit is set to 1 (main clock stop), the following commands must not be executed. ? program ? block erase 21.14.5 writing command and data write the command code and data at even addresses. 21.14.6 program command write xx40 16 in the first bus cycle and write data to the write address in the second bus cycle, and an auto program operation (data program and verify) will start. make sure the address value specified in the first bus cycle is the same even address as the write address specified in the second bus cycle. 21.14.7 operation speed when cpu clock source is main clock, before entering cpu rewrite mode (ew mode 0 or 1), select 10 mhz or less for bclk using the cm06 bit in the cm0 register and bits cm17 to cm16 in the cm1 register. also, when cpu clock is f 3 (roc) on-chip oscillator clock, before entering cpu rewrite mode (ew mode 0 or 1), set the rocr3 to rocr2 bits in the rocr register to ? divied by 4 ? or ? divide by 8 ? . on both cases, set the pm17 bit in the pm1 register to 1 (with wait state). 21.14.8 instructions inhibited against use the following instructions cannot be used in ew mode 0 because the flash memory ? s internal data is referenced: und instruction, into instruction, jmps instruction, jsrs instruction, and brk instruction
page 382 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions 21.14.9 interrupts ew mode 0 ? any interrupt which has a vector in the variable vector table can be used providing that its vector is transferred into the ram area. _______ ? the nmi and watchdog timer interrupts can be used because the fmr0 register and fmr1 register are initialized when one of those interrupts occurs. the jump addresses for those interrupt service routines should be set in the fixed vector table. _______ because the rewrite operation is halted when a nmi or watchdog timer interrupt occurs, the rewrite program must be executed again after exiting the interrupt service routine. ? the address match interrupt cannot be used because the flash memory ? s internal data is referenced. ew mode 1 ? make sure that any interrupt which has a vector in the variable vector table or address match inter- rupt will not be accepted during the auto program period or auto erase period with erase-suspend function disabled. _______ ? the nmi interrupt can be used because the fmr0 register and fmr1 register are initialized when this interrupt occurs. the jump address for the interrupt service routine should be set in the fixed vector table. _______ because the rewrite operation is halted when a nmi interrupt occurs, the rewrite program must be executed again after exiting the interrupt service routine. 21.14.10 how to access to set the fmr01, fmr02, fmr11 or fmr16 bit to 1, set the subject bit to 1 immediately after setting to 0. do not generate an interrupt or a dma transfer between the instruction to set the bit to 0 and the _______ instruction to set the bit to 1. set the bit when the pm24 bit is set to 1 (nmi funciton) and a high-level ( ? h ? ) _______ signal is applied to the nmi pin. 21.14.11 writing in the user rom area ew mode 0 ? if the power supply voltage drops while rewriting any block in which the rewrite control program is stored, a problem may occur that the rewrite control program is not correctly rewritten and, conse- quently, the flash memory becomes unable to be rewritten thereafter. in this case, standard serial i/ o or parallel i/o mode should be used. ew mode 1 ? avoid rewriting any block in which the rewrite control program is stored. 21.14.12 dma transfer in ew mode 1, make sure that no dma transfers will occur while the fmr00 bit in the fmr0 register is set to 0(during the auto program or auto erase period). 21.14.13 regarding programming/erasure times and execution time as the number of programming/erasure times increases, so does the execution time for software com- mands (program command and block erase command). _______ the software commands are aborted by hardware reset 1, nmi interrupt, and watchdog timer interrupt. if a software command is aborted by such reset or interrupt, the affected block must be erased before reexecuting the aborted command.
page 383 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions 21.14.14 definition of programming/erasure times "number of programs and erasure" refers to the number of erasure per block. if the number of program and erasure is n (n=100 1,000 10,000) each block can be erased n times. for example, if a 2k byte block a is erased after writing 1 word data 1024 times, each to a different address, this is counted as one program and erasure. however, data cannot be written to the same adrress more than once without erasing the block. (rewrite prohibited) 21.14.15 flash memory version electrical characteristics 10,000 e/w cycle product (u7) when block a or b e/w cycles exceed 100, set the fmr17 bit in the fmr1 register to 1 (1 wait) to select one wait state per block access for u7. when fmr17 is set to 1, one wait state is inserted per access to block a or b - regardless of the value of pm17. wait state insertion during access to all other blocks, as well as to internal ram, is controlled by pm17 - regardless of the fmr17 bit setting. to use the limited number of erasure efficiently, write to unused address within the block instead of rewite. erase block only after all possible addresses are used. for example, an 8-word program can be written 128 times before erase becomes necessary. maintaining an equal number of erasure between block a and b will also improve efficiency. we recommend keeping track of the number of times erasure is used. 21.14.16 boot mode an undefined value is sometimes output in the i/o port until the internal power supply becomes stable _____________ when "h" is applied to the cnv ss pin and "l" is applied to the reset pin. when setting the cnv ss pin to "h", the following procedure is required: ____________ (1) apply an "l" signal to the reset pin and the cnv ss pin. (2) bring v cc to more than 2.7v, and wait at least 2msec. (internal power supply stable waiting time) (3) apply an "h" signal to the cnv ss pin. ____________ (4) apply an "h" signal to the reset pin. when the cnv ss pin is ? h ? and reset pin is ? l ? , p6 7 pin is connected to the pull-up resister.
page 384 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions 21.15 noise connect a bypass capacitor (approximately 0.1 f) across the v cc and v ss pins using the shortest and thicker possible wiring. figure 21.6 shows the bypass capacitor connection. figure 21.6 bypass capacitor connection m16c/28 group (t-ver./v-ver.) bypass capacitor connecting pattern connecting pattern vss vcc
page 385 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m 21. precautions 21.16 instruction for a device use when handling a device, extra attention is necessary to prevent it from crashing during the electrostatic discharge period.
page 386 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m appendix 1. package dimensions appendix 1. package dimensions t e rmin a l c r oss sec ti on c 1 p c 2 . 1. * 2" note ) in c l u de trim o ff s et. f * 1 * 2 h e e h d d z z e de t a il f a c a 2 a 1 l 1 l p-l q fp64-10x10-0.5 0 0.3 g mass[t y p. ] 64p6 q -a / fp-64k / fp-64k v pl q p0064kb- a rene s a s c od e jeita packa g e cod e previous c od e 1. 0 0 .12 5 0 .1 8 1.2 5 1.2 5 0 . 08 0 .2 0 0 .14 5 0 . 09 0 .2 0 0 .1 5 m ax n o m min s y mbo l r e f e r e n ce 1 0 . 1 1 0 . 0 9 . 9 d 1 0 . 1 1 0 . 0 9 . 9 e a 12 .2 12. 0 11. 8 12. 0 11. 8 1 .7 a 0 .1 5 0 . 1 0 . 05 0 . 65 0 . 5 0 . 35 l x 8 0 c 0 . 5 e 0 . 08 y h d e a 1 p b 1 c 1 z d z e l 1 de t a il f c a l 1 l a 1 a 2 * 2 * 1 f 41 0 2 0 z e e h e d h d 2 . 1. dimen s i o n s " * 1 " and " * 2" note ) dimen s i o n " * 3 " d o e s n ot in c l u de trim o ff s et . previous c od e jeita packa g e cod e rene s a s c od e pl q p0080kb- a 80p6 q - a mass[t y p. ] 0.5 g p-l q fp80-12x12-0.5 0 1. 0 0 .12 5 0 .1 8 1.2 5 1.2 5 0 . 08 0 .2 0 0 .14 5 0 . 09 0 .2 5 0 .2 0 0 .1 5 m ax n om min d imension in millimeter s sy mbo l r e f e r e n ce 12 .1 12. 0 11. 9 d 12 .1 12. 0 11. 9 e 1 .4 a 1 4.2 14. 0 1 3 . 8 1 4.2 14. 0 1 3 . 8 1 .7 0 . 2 0 . 1 0 0 . 7 0 . 5 0 . 3 l x 1 0 0 c 0 . 5 e 0.0 8 y h d e a 1 p b 1 c 1 z d z e l 1 t e rmin a l c r oss sec ti on c 1 1
page 387 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m appendix 2. functional comparison appendix 2. functional comparison appendix 2.1 difference between m16c/28 group normal-ver. and m16c/28 group t-/v-ver. (1 ) m e t in o i t p i r c s e d) . r e v - l a m r o n ( 8 2 / c 6 1 m) . r e v - v / . r e v - t ( 8 2 / c 6 1 m k c o l c n o i t a r e n e g t i u c r i c n o i t c n u f ( n o i t c n u f t u p t u o k c o l c 0 m c e h t n i s t i b 0 b o t 1 b f o ) r e t s i g e r ) t i b d e v r e s e r ( e l b a l i a v a t o n t c e l e s n o i t c n u f t u p t u o k c o l c ( e l b a l i a v a ) t i b t e s e rt i u c r i c t c e t e d e g a t l o v w o l 9 1 0 0 f o n o i t c n u f ( 6 1 a 1 0 0 , 6 1 , f 1 0 0 6 1 ) , 1 r e t s i g e r t c e t e d e g a t l o v ( e l b a l i a v a e g a t l o v w o l , 2 r e t s i g e r t c e t e d e g a t l o v ) r e t s i g e r t p u r r e t n i t c e t e d ) r e t s i g e r d e v r e s e r ( e l b a l i a v a t o n e s a h p - e e r h t l o r t n o c r o t o m r e m i t g n i h c t i w s t r o p e s a h p - e e r h t 8 5 3 0 f o n o i t c n u f ( n o i t c n u f 6 1 ) ) r e t s i g e r d e v r e s e r ( e l b a l i a v a t o n t c e l e s n o i t c n u f t r o p ( e l b a l i a v a ) r e t s i g e r d / a n i p t u p n i d / a f o r e b m u n3 n a g n i d u l c x e ( s l e n n a h c 4 2 0 3 n a o t 2 )3 n a g n i d u l c n i ( s l e n n a h c 7 2 0 3 n a o t 2 ) 0 e d o m r e g g i r t d e y a l e d n o i s r e v p i h c t s 1 e h t n i e l b a l i a v a t o n a n o i s r e v p i h c d n a e l b a l i a v a 1 e d o m r e g g i r t d e y a l e d n o i s r e v p i h c t s 1 e h t n i e l b a l i a v a t o n a n o i s r e v p i h c d n a e l b a l i a v a c r c n o i t a l u c l a c - c r c o t e l b i t a p m o c ( e l b a l i a v a ) s d o h t e m 6 1 - c r c d n a t t i c c e r a s r e t s i g e r d e t a l e r l l a ( e l b a l i a v a t o n ) s r e t s i g e r d e v r e s e r ) t i u c r i c 1 ( e l b a l i a v a n o i t c n u f n i p, ) e g a k c a p n i p - 5 8 / n i p - 0 8 ( s n i p 3 ) . e g a k c a p n i p - 4 6 ( s n i p 4 6 9 p 2 2 b t / n i 9 p 2 3 n a / 2 2 b t / n i , ) e g a k c a p n i p - 0 8 ( s n i p 4 ) e g a k c a p n i p - 4 6 ( n i p 1 9 p 1 1 b t / n i 9 p 1 3 n a / 1 1 b t / n i , ) e g a k c a p n i p - 0 8 ( s n i p 5 ) e g a k c a p n i p - 4 6 ( s n i p 2 9 p 0 0 b t / n i 9 p 0 3 n a / 0 0 b t / n i k l c / t u o h s a l f y r o m e m 9 p 3 e d o m o / i l a i r e s d r a d n a t s n i ) n o i s r e v e t y b k 8 2 1 n a h t r e h t o ( i ) n o i s r e v e t y b k 8 2 1 ( o / i o / i t u p t u o d n a t u p n i : o / i t u p t u o : o t u p n i : i : e t o n r o f e l b a l i a v a e r a s n o i t c n u f e h t l l a , p u o r g 9 2 / c 6 1 m e h t n i d e s u r o t a l u m e n o m m o c e h t s e s u p u o r g 8 2 / c 6 1 m e h t e c n i s . 1 . p u r o g 8 2 / c 6 1 m e h t n i - t l i u b t o n s i h c i h w r f s e h t o t s s e c c a t o n o d , p u o r g 8 2 / c 6 1 m g n i t a u l a v e n e h w . 8 2 / c 6 1 m . s c i t s i r e t c a r a h c l a c i r t c e l e d n a s l i a t e d r o f l a u n a m e r a w d r a h o t e r e f e r
page 388 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m appendix 2. functional comparison m e t in o i t p i r c s e d) . r e v - v / . r e v - t ( 8 2 / c 6 1 m) . r e v - v / . r e v - t ( 9 2 / c 6 1 m n o i t c e t o r p t i b 0 c r p e h t f o n o i t c n u f , 2 m c , 1 m c , 0 m c e h t t e s o t e l b a n e s r e t s i g e r r k l c p d n a 0 c l p , r c o p , 2 m c , 1 m c , 0 m c e h t t e s o t e l b a n e r k l c c d n a r k l c p , 0 c l p , r c o p s r e t s i g e r t p u r r e t n ie h t n i g n i t t e s t i b 0 2 r s f i e h t r e t s i g e r a 2 r s f i 1 o t t e s0 o t t e s a 2 r s f i e h t n i t i b 1 b e h t r e t s i g e r ) t i b d e v r e s e r ( e l b a l i a v a t o n d / a : 0 ( t i b g n i h c t i w s e s u a c t p u r r e t n i ) t u p n i y e k : 1 , n o i s r e v n o c a 2 r s f i e h t n i t i b 2 b e h t r e t s i g e r ) t i b d e v r e s e r ( e l b a l i a v a t o n 0 n a c : 0 ( t i b g n i h c t i w s e s u a c t p u r r e t n i ) r o r r e / p u - e k a w t p u r r e t n i e h t n i e s u a c t p u r r e t n i 3 1 r e b m u n t p u r r e t n i t u p n i y e kr o r r e 0 n a c t p u r r e t n i e h t n i e s u a c t p u r r e t n i 4 1 r e b m u n t p u r r e t n i t u p n i y e kt p u r r e t n i t u p n i y e k , d / a e l u d o m n a c b 0 . 2 o t e l b i t a p m o c e r a s r e t s i g e r d e t a l e r l l a ( e l b a l i a v a t o n ) s r e t s i g e r d e v r e s e r ) l e n n a h c 1 ( e l b a l i a v a n o i t c n u f n i p, ) e g a k c a p n i p - 5 8 / n i p - 0 8 ( s n i p 2 ) e g a k c a p n i p - 4 6 ( s n i p 2 6 9 p 3 2 n a / 4 9 p 3 2 n a / 4 x t c / , ) e g a k c a p n i p - 5 8 / n i p - 0 8 ( s n i p 3 ) e g a k c a p n i p - 4 6 ( s n i p 4 6 9 p 2 2 b t / n i 9 p 2 3 n a / 2 2 b t / n i x r c / h s a l f y r o m e m 9 p 3 o / i l a i r e s d r a d n a t s n i e d o m o / it u p t u o x t c t u p t u o d n a t u p n i : o / i t u p t u o : o t u p n i : i : e t o n r o f e l b a l i a v a e r a s n o i t c n u f e h t l l a , p u o r g 9 2 / c 6 1 m e h t n i d e s u r o t a l u m e n o m m o c e h t s e s u p u o r g 8 2 / c 6 1 m e h t e c n i s . 1 . p u r o g 8 2 / c 6 1 m e h t n i - t l i u b t o n s i h c i h w r f s e h t o t s s e c c a t o n o d , p u o r g 8 2 / c 6 1 m g n i t a u l a v e n e h w . 8 2 / c 6 1 m . s c i t s i r e t c a r a h c l a c i r t c e l e d n a s l i a t e d r o f l a u n a m e r a w d r a h o t e r e f e r appendix 2.2 difference between m16c/28 group t-/v-ver. and m16c/29 group t-/v-ver. (1 )
page 389 register index 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m register index a ad0 to ad7 215 adcon0 to adcon2 213 adic 65 adstat0 215 adtrgcon 214 aier 77 b bcnic 65 btic 65 c c01erric 65 c01wkic 65 c0recic 65 c0trmic 65 cm0 38 cm1 39 cm2 40 cpsrf 94 , 107 crcd 277 crcin 277 crcmr 277 crcsar 277 d dar0 84 dar1 84 dm0con 83 dm0ic 65 dm0sl 82 dm1con 83 dm1ic 65 dm1sl 83 dtt 118 f fmr0 303 fmr1 303 fmr4 304 g g1bcr0 131 g1bcr1 132 g1bt 131 g1btrr 133 g1dv 132 g1fe 137 g1fs 137 g1ie0 139 g1ie1 139 g1ir 138 g1po0 to g1po7 136 g1pocr0 to g1pocr7 135 g1tm0 to g1tm7 135 g1tmcr0 to g1tmcr7 134 g1tpr6 to g1tpr7 134 i icoc0ic 65 icoc1ic 65 ictb2 118 , 119 idb0 118 idb1 118 ifsr 66, 74 ifsr2a 66 iicic 65 int0ic to int2ic 65 int3ic 65 int4ic 65 int5ic 65 invc0 116 invc1 117 k kupic 65 l lpcc0 361 lpcc1 361 n nddr 290
page 390 register index 0 9 3 f o 7 0 0 2 , 0 3 . r a m 0 1 . 1 . v e r 0 1 1 0 - 7 8 2 0 b 9 0 j e r ) . r e v - v / . r e v - t ( p u o r g 8 2 / c 6 1 m o onsf 94 p p0 to p3 287 p17ddr 290 p6 to p10 287 pacr 166 , 289 pclkr 41 pcr 289 pd0 to pd3 286 pd6 to pd10 286 pdrf 126 pfcr 128 plc0 42 pm0 34 pm1 34 pm2 35 , 41 prcr 58 pur0 to pur2 288 r rmad0 77 rmad1 77 rocr 39 romcp 298 s s00 247 s0d0 246 s0ric to s2ric 65 s0tic to s2tic 65 s10 249 s1d0 248 s20 247 s2d0 252 s31c 65 s3brg 207 s3c 207 s3d0 250 s3trr 207 s4brg 207 s4c 207 s4d0 251 s4ic 65 s4trr 207 sar0 84 sar1 84 scldaic 65 t ta0 to ta4 93 ta0ic to ta4ic 65 ta0mr to ta4mr 92 ta11 119 ta1mr 122 ta2 119 ta21 119 ta2mr 122 ta4 119 ta41 119 ta4mr 122 tabsr 93 , 107 , 121 tb0 to tb2 107 tb0ic to tb2ic 65 tb0mr to tb2mr 106 tb2 121 tb2mr 122 tb2sc 120 , 216 tcr0 84 tcr1 84 tprc 128 trgsr 94 , 121 u u0brg to u2brg 163 u0c0 to u2c0 165 u0c1 to u2c1 166 u0mr to u2mr 164 u0rb to u2rb 163 u0tb to u2tb 163 u2smr 167 u2smr2 167 u2smr3 168 u2smr4 168 ucon 165 udf 93 w wdc 79 wdts 79
revision history rev. date description page summary c- 1 m16c/28 group(t-ver./v-ver.) hardware manual new document all pages word standardized: mcu, cpu clock overview 1 ? 1.1 features description modified 2, 3 ? tables 1.1 and 1.2 performance overviews note on trademark modified 4, 5 ? figures 1.1 and 1.2 m16c/28 group (t-ver./ v-ver.) block diagrams notes are added 6 ? tables 1.3 and 1.4 product lists updated 7 ? figure 1.3 product numbering system updated 8 ? tables 1.5 and 1.6 product code modified ? tables 1.7 and 1.8 product code mask version newly added 10 ? figure 1.6 marking diagram of mask rom version is newly added 12, 13 ? table 1.9 pin characteristics for 80-pin package is newly added 15, 16 ? table 1.10 pin characteristics for 64-pin package is newly added 17 to 19 ? table 1.11 to 1.12 pin description is modified memory 22 ? figure 3.1 memory map internal ram memory size is modified sfr 25 ? table 4.3 sfr information (3) registers lpcc0 and lpcc1 are added, values after reset for rocr register and fmr4 register are modified 27 table 4.5 sfr information (5) value after reset for ifsr2a register is modified reset 32 ? figure 5.2 reset sequence vcc and roc timing lines modified processor mode 33 ? description added ? figure 6.1 bus block diagram added 34 ? figure 6.2 pm2 register added 35 ? figure 6.3 bus block diagram and table 6.1 accessible area and bus cycles newly added clock generation circuits 36 ? table 7.1 clock generation circuit specifications ? oscillation stop, restart function ? is modified 37 ? figure 7.1 clock generation circuits partially modified 41 figure 7.6 pm2 register notes 4 to 5 partially modified 48 ? 7.6.1 normal operation mode description is modified 52 ? figure 7.11 state transition to stop mode and wait mode figure partially modified 53 ? figure 7.12 state transition in normal mode figure partially modified 54 ? table 7.7 allowed transition and setting table contents partially modified 1.00 dec. 05 1.10 mar.30,07
revision history rev. date description page summary c- 2 m16c/28 group(t-ver./v-ver.) hardware manual 55 7.8 osillation stop and re-oscillation detect function description modified protection 58 ? description partially modified, lpcc1 register added ? figure 8.1 prcr register prc0 bit is modified interrupts 76 ? table 9.6 value of the pc that is saved to the stack area when an address match interrupt request is accepted modified, note added watchdog timer 78 ? description partially added ? figure 10.1 watchdog timer block diagram partially modified 79 ? figure 10.2 wdts register note deleted timer 106 12.2 timer b description of a/d trigger mode modified figure 12.15 timer b block diagram a/d trigger mode added 112 12.2.4 a/d trigger mode description modified 118 ? figure 12.28 ictb2 register bits 7 and 6 modified 120 ? figure 12.30 tb2sc register note 4 is added, contents modified 123 ? figure 12.33 triangular wave modulation operation description modified 124 ? figure 12.34 sawtooth wave modulation operation description modified 128 ? figure 12.38 tprc register bit map modified timer s 131 ? figure 13.2 g1bt register description patially modified, g1bcr0 register bit name partially modified 144 ? figure 13.15 base timer reset operation by base timer reset register note 1 is added, figures partially modified 149 ? figure 13.21 prescaler function and gate function note 1 modified 155 ? table 13.10 sr waveform output mode specifications specification modi- fied 157 ? table 13.11 pin setting for time measurement and waveform generating functions port direction modified serial i/o 160 ? figure 14.1 block diagram of uarti figure modified 169 table 14.1 clock synchronous serial i/o mode specifications note 2 modi- fied 177 table 14.5 uart mode specifications note 1 modified 185 table 14.10 i 2 c bus mode specifications note 2 modified 195 ? table 14.15 special mode 2 specifications note 2 modifed 201 ? table 14.18 sim mode specifications note 1 modified 206 ? 14.2 si/o3 and si/o4 note is added
revision history rev. date description page summary c- 3 m16c/28 group(t-ver./v-ver.) hardware manual 207 ? figure 14.36 s3brg and s4brg registers register name modified 210 ? 14.2.3 functions for setting an souti initial value description modified multi-master i 2 c bus interface 245 ? figure 16.1 block diagram of multi-master i 2 c bus interface s30 register deleted, system clock select circuit partially modified 247 ? figure 16.3 s00 register bit name in note 1 modified 268 ? 16.11 stop condition generation method description added crc calculation circuit 276 17.1 crc snoop description partially modified programmable i/o ports 281 figure 18.1 i/o ports (1) partially modified 283 figure 18.3 i/o ports (3) partially modified 291 ? figure 18.12 functioning of digital debounce filter figure partially modified flash memory version 295 ? 19.2 memory map description modified ? figure 19.1 flash memory block diagram (rom capacity 64k) added 297 ? 19.3.1 rom code protect function description is modified 301 ? 19.5.1 flash memory control register 0 fmr01 bit and fmr02 bit : descrip- tions are modified 302 ? 19.5.2 flash memory control register 1 fmr16 bit : description is modified 303 ? figure 19.5 fmr1 register note 1 and note 3 modified 314 ? table 19.7 errors and fmr0 register status register name modified electrical characteristics 325 table 20.3 a/d conversion characteristics unit for t conv is modified 326 ? table 20.5 flash memory version electrical characteristics for 10000 e/w cycle products note 1, 4, 10, and 11 are modified 327 ? td(p-r) and td(roc) timing lines modified 329 ? table 20.8 electrical characteristics table is modified 336 ? table 20.23 electrical characteristics note 1 is modified 337 table 20.24 electrical characteristics table is modified 346 ? table 20.41 a/d conversion characteristics modified 347 ? table 20.42 and 20.43 flash memory version electrical characteristics note 4, 10, and 11 are modified 348 ? td(p-r) and td(roc) timing lines modified 350 ? table 20.46 electrical characteristics table is modified, note 4 is added precaution - ? reset section deleted 357 ? 21.1.3 register setting newly added 360, 361 ? (e)low power consumption control register newly added
revision history rev. date description page summary c- 4 m16c/28 group(t-ver./v-ver.) hardware manual 365 21.4.6 rewrite the interrupt control register example 1 modified 371 ? 21.6.3 three-phase motor control timer function newly added 372 ? 21.7.1 rewrite the g1ir register description modified 373 21.7.4 ic/oc base timer interrupt section newly added 381 ? 21.13.1 internal rom area partially added 383 ? 21.14.9 interrupts ew mode 1 description about watchdog timer interrupt deleted ? 21.14.10 how to access partially deleted ? 21.14.13 regarding programming/erasure times and execution time de- scription partially modified functional comparison - ? difference between m16c/28 group and m16c/29 group (normal-ver.) is deleted 388 ? appendix 2.1 difference between m16c/28 group normal-ver. and m16c/28 group t-ver./v-ver. flash memory added
renesas 16-bit single-chip microcomputer hardware manual m16c/28 group (t-ver./v-ver.) publication data : rev.1.00 dec. 26, 2005 rev.1.10 mar. 30, 2007 published by : sales strategic planning div. renesas technology corp. ? 2007. renesas technology corp., all rights reserved. printed in japan.
m16c/28 group (t-ver./v-ver.) hardware manual 2-6-2, ote-machi, chiyoda-ku, tokyo, 100-0004, japan

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