k6t4016c3c family cmos sram revision 1.0 april 1999 1 document title 256kx16 bit low power cmos static ram revision history the attached datasheets are provided by samsung electronics. samsung electronics co., ltd. reserve the right to change the speci fications and products. samsung electronics will answer to your questions about device. if you have any questions, please contact the samsung branch offices. revision no. 0.0 1.0 remark preliminary finalize history initial draft finalize draft data december 17, 1998 april 17, 1999
k6t4016c3c family cmos sram revision 1.0 april 1999 2 256kx16 bit low power cmos static ram general description the k6t4016c3c families are fabricated by samsung s advanced cmos process technology. the families support various operating temperature ranges and small package types for user flexibility of system design. the families also support low data retention voltage for battery back-up opera- tion with low data retention current. features process technology: tft organization: 256kx16 power supply voltage : 4.5~5.5v low data retention voltage: 2v(min) three state output and ttl compatible package type: 44-tsop2-400f/r pin description name function name function cs chip select input vcc power oe output enable input vss ground we write enable input ub upper byte(i/o 9~16 ) a 0 ~a 17 address inputs lb lower byte (i/o 1~8 ) i/o 1 ~i/o 16 data inputs/outputs n.c no connection product family 1. the parameter is measured with 50pf test load. product family operating temperature vcc range speed(ns) power dissipation pkg type standby (i sb1 , max) operating (i cc2 , max) k6t4016c3c-b commercial(0~70 c) 4.5~5.5v 55 1) /70 20 m a 90ma 44-tsop2-f/r k6t4016c3c-f industrial(-40~85 c) 50 m a functional block diagram samsung electronics co., ltd. reserves the right to change products and specifications without notice. a4 a3 a2 a1 a0 cs i/oi i/o2 i/o3 i/o4 vcc vss i/o5 i/o6 i/o7 i/o8 we a17 a16 a15 a14 a5 a6 a7 oe ub lb i/o16 i/o15 i/o14 i/o13 vss vcc i/o12 i/o11 i/o10 i/o9 n.c a8 a9 a10 44-tsop2 forward 44-tsop2 reverse 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a5 a6 a7 oe ub lb i/o16 i/o15 i/o14 i/o13 vss vcc i/o12 i/o11 i/o10 i/o9 n.c a8 a9 a10 a11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a13 a12 a11 a12 a4 a3 a2 a1 a0 cs i/oi i/o2 i/o3 i/o4 vcc vss i/o5 i/o6 i/o7 i/o8 we a17 a16 a15 a14 a13 clk gen. row select a8 a9 a10 a5 a6 a4 a7 a13 a14 a0 a1 a15 a16 a17 a2 i/o 1 ~i/o 8 a3 data cont data cont data cont i/o 9 ~i/o 16 vcc vss a4 a12 precharge circuit. memory array 1024 rows 256 16 columns i/o circuit column select we oe ub cs lb control logic
k6t4016c3c family cmos sram revision 1.0 april 1999 3 product list commercial temperature product(0~70 c) industrial temperature products(-40~85 c) part name function part name function k6t4016c3c-tb55 k6t4016c3c-tb70 k6t4016c3c-rb55 k6t4016c3c-rb55 44-tsop2-f, 55ns, ll-pwr 44-tsop2-f, 70ns, ll-pwr 44-tsop2-r, 55ns, ll-pwr 44-tsop2-r, 70ns, ll-pwr K6T4016C3C-TF55 k6t4016c3c-tf70 k6t4016c3c-rf55 k6t4016c3c-rf70 44-tsop2-f, 55ns, ll-pwr 44-tsop2-f, 70ns, ll-pwr 44-tsop2-r, 55ns, ll-pwr 44-tsop2-r, 70ns, ll-pwr absolute maximum ratings 1) 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. functional oper ation should be restricted to recommended operating condition. exposure to absolute maximum rating conditions for extended periods may affect r eliability. item symbol ratings unit remark voltage on any pin relative to vss v in ,v out -0.5 to 7.0 v - voltage on vcc supply relative to vss v cc -0.5 to7.0 v - power dissipation p d 1.0 w - storage temperature t stg -65 to 150 c - operating temperature t a 0 to 70 c k6t4016c3c-b -40 to 85 c k6t4016c3c-f functional description 1. x means don t care. (must be in low or high state) cs oe we lb ub i/o 1~8 i/o 9~16 mode power h x 1) x 1) x 1) x 1) high-z high-z deselected standby l h h x 1) x 1) high-z high-z output disabled active l x 1) x 1) h h high-z high-z output disabled active l l h l h dout high-z lower byte read active l l h h l high-z dout upper byte read active l l h l l dout dout word read active l x 1) l l h din high-z lower byte write active l x 1) l h l high-z din upper byte write active l x 1) l l l din din word write active
k6t4016c3c family cmos sram revision 1.0 april 1999 4 recommended dc operating conditions 1) note: 1. commercial product : t a =0 to 70 c, otherwise specified industrial product : t a =-40 to 85 c, otherwise specified 2. overshoot : v cc +3.0v in case of pulse width 30ns 3. undershoot : -3.0v in case of pulse width 30ns 4. overshoot and undershoot are sampled, not 100% tested. item symbol min typ max unit supply voltage vcc 4.5 5.0 5.5 v ground vss 0 0 0 v input high voltage v ih 2.2 - vcc+0.5 2) v input low voltage v il -0.5 3) - 0.8 v capacitance 1) (f=1mhz, t a =25 c) 1. capacitance is sampled, not 100% tested item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/output capacitance c io v io =0v - 10 pf dc and operating characteristics 1. industrial product = 50 m a item symbol test conditions min typ max unit input leakage current i li v in =vss to vcc -1 - 1 m a output leakage current i lo cs =v ih or oe =v ih or we =v il, v io =vss to vcc -1 - 1 m a operating power supply i cc i io =0ma, cs =v il , v in =v il or v ih , read - - 10 ma average operating current i cc1 cycle time=1 m s, 100% duty, i io =0ma, cs 0.2v, v in 0.2v or v in 3 vcc-0.2v - - 15 ma i cc2 cycle time=min, 100% duty, i io =0ma, cs =v il, v in =v ih or v il - - 90 ma output low voltage v ol i ol =2.1ma - - 0.4 v output high voltage v oh i oh =-1.0ma 2.4 - - v standby current (ttl) i sb cs =v ih, other inputs=v il or v ih - - 3 ma standby current(cmos) i sb1 cs 3 vcc-0.2v, other inputs=0~vcc - - 20 1) m a
k6t4016c3c family cmos sram revision 1.0 april 1999 5 c l 1) 1. including scope and jig capacitance ac operating conditions test conditions (test load and test input/output reference) input pulse level : 0.8 to 2.4v input rising and falling time : 5ns input and output reference voltage : 1.5v output load (see right) : c l =100pf+1ttl 50pf+1ttl 1) 1. for 55ns product ac characteristics (k6t4016c3c family : vcc=4.5~5.5v, commercial product : t a= 0 to 70 c, industrial product : t a =-40 to 85 c) parameter list symbol speed bins units 55ns 70ns min max min max read read cycle time t rc 55 - 70 - ns address access time t aa - 55 - 70 ns chip select to output t co - 55 - 70 ns output enable to valid output t oe - 25 - 35 ns chip select to low-z output t lz 10 - 10 - ns output enable to low-z output t olz 5 - 5 - ns lb , ub enable to low-z output t blz 5 - 5 - ns chip disable to high-z output t hz 0 20 0 25 ns oe disable to high-z output t ohz 0 20 0 25 ns output hold from address change t oh 10 - 10 - ns lb , ub valid to data output t ba - 25 - 35 ns ub , lb disable to high-z output t bhz 0 20 0 25 ns write write cycle time t wc 55 - 70 - ns chip select to end of write t cw 45 - 60 - ns address set-up time t as 0 - 0 - ns address valid to end of write t aw 45 - 60 - ns write pulse width t wp 45 - 55 - ns write recovery time t wr 0 - 0 - ns write to output high-z t whz 0 20 0 25 ns data to write time overlap t dw 25 - 30 - ns data hold from write time t dh 0 - 0 - ns end write to output low-z t ow 5 - 5 - ns lb , ub valid to end of write t bw 45 - 60 - ns data retention characteristics 1. industrial product : 20 m a item symbol test condition min typ max unit vcc for data retention v dr cs 3 vcc-0.2v 2.0 - 5.5 v data retention current i dr vcc=3.0v - - 15 1) m a data retention set-up time t sdr see data retention waveform 0 - - ms recovery time t rdr 5 - -
k6t4016c3c family cmos sram revision 1.0 april 1999 6 address data out previous data valid data valid timming diagrams timing waveform of read cycle(1) (address controlled , cs = oe =v il , we =v ih , ub or/and lb =v il ) timing waveform of read cycle(2) ( we =v ih ) data valid high-z t rc cs address ub , lb oe data out t aa t rc t oh t oh t aa t co t ba t oe t olz t blz t lz t ohz t bhz t hz notes ( read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection.
k6t4016c3c family cmos sram revision 1.0 april 1999 7 timing waveform of write cycle(1) ( we controlled) address cs data undefined ub , lb we data in data out timing waveform of write cycle(2) ( cs controlled) address cs data valid ub , lb we data in data out high-z high-z t wc t cw(2) t wr(4) t aw t bw t wp(1) t as(3) t dh t dw t whz t ow t wc t cw(2) t aw t bw t wp(1) t dh t dw t wr(4) high-z high-z data valid t as(3)
k6t4016c3c family cmos sram revision 1.0 april 1999 8 address cs data valid ub , lb we data in data out high-z high-z timing waveform of write cycle(3) ( ub , lb controlled) notes (write cycle) 1. a wri t e occurs during the overlap(t wp ) of low cs and low we . a write begins when cs goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest transi- tion when cs goes high and we goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs going low to end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end or write to the address change. t wr applied in case a write ends as cs or we going high. t wc t cw(2) t bw t wp(1) t dh t dw t wr(4) t aw data retention wave form cs controlled v cc 4.5v 2.2v v dr cs gnd data retention mode cs 3 v cc - 0.2v t sdr t rdr t as(3)
k6t4016c3c family cmos sram revision 1.0 april 1999 9 44 pin thin small outline package type ii (400f) units: millimeter(inch) 0 . 0 0 2 #1 0 . 0 5 #22 #44 #23 0.35 0.10 0.014 0.004 0.80 0.0315 m i n . 0.047 1.20 max. 0.741 18.81 max. 18.41 0.10 0.725 0.004 11.76 0.20 0.463 0.008 + 0 . 1 0 - 0 . 0 5 0.50 + 0 . 0 0 4 - 0 . 0 0 2 0 . 1 5 0 . 0 0 6 0.020 1 0 . 1 6 0 . 4 0 0 0.10 0.004 package dimensions 0~8 0.45 ~0.75 0.018 ~ 0.030 0.25 ( ) 0.010 ( ) 0.805 0.032 ( ) max 1.00 0.10 0.039 0.004 44 pin thin small outline package type ii (400r) 0 . 0 0 2 #1 0 . 0 5 #22 #44 #23 0.35 0.10 0.014 0.004 0.80 0.0315 m i n . 0.047 1.20 max. 0.741 18.81 max. 18.41 0.10 0.725 0.004 11.76 0.20 0.463 0.008 + 0 . 1 0 - 0 . 0 5 0.50 + 0 . 0 0 4 - 0 . 0 0 2 0 . 1 5 0 . 0 0 6 0.020 1 0 . 1 6 0 . 4 0 0 0.10 0.004 0~8 0.45 ~0.75 0.018 ~ 0.030 0.25 ( ) 0.010 ( ) 0.805 0.032 ( ) max 1.00 0.10 0.039 0.004
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