integrated circuit systems, inc. icssstv32852 preliminary product preview 0513b?04/03/02 recommended application: ddr memory modules product features: ? differential clock signals meets sstl_2 signal data supports sstl_2 class ii specifications on outputs low-voltage operation - vdd = 2.3v to 2.7v available in 114 ball bga package. ddr 24-bit to 48-bit registered buffer truth table 1 block diagram notes: 1. h = high signal level l = low signal level = transition low-to-high = transition high -to low x = irrelevant 2. output level before the indicated steady state input conditions were established. clk clk# d1 vref reset# to 23 other channels q1a q1b clk r d1 a b 123456 c d e f g h j k l m n p r t u v w pin configuration 114-pin ball bga s t u p n is t u p t u o q # t e s e rk l c# k l cdq l r o x g n i t a o l f r o x g n i t a o l f r o x g n i t a o l f l h hh h ll hh r o lh r o lxq 0 ) 2 ( pin configuration assignments 1234 5 6 a q2a q1a clk clk# q1b q2b b q3a vddq gnd gnd vddq q3b c q5a q4a vddq vddq q4b q5b d q7a q6a gnd gnd q6b q7b e q8a gnd vddq vddq gnd q8b f q10a q9a vddq vddq q9b q10b g q12a q11a gnd gnd q11b q12b h q13a vdd vddq vddq vdd q13b j q14a q15a gnd gnd q15b q14b k q17a q16a vddq vddq q16b q17b l q18a q19a gnd gnd q19b q18b m q20a vddq gnd gnd vddq q20b n q22a q21a vddq vddq q21b q22b p q23a vddq gnd gnd vddq q23b r q24a vdd reset# vref vdd q24b t d2 d1 d6 d18 d13 d14 u d4 d3 d10 d22 d15 d16 v d5 d7 d11 d23 d19 d17 w d8 d9 d12 d24 d21 d20 product preview documents contain information on new products in the sampling or preproduction phase of development. characteristic data and o ther specifications are subject to change without notice.
2 icssstv32852 preliminary product preview third party brands and names are the property of their respective owners. general description pin configuration the 24-bit to 48-bit icssstv32852 is a universal bus driver designed for 2.3v to 2.7v vdd operation and sstl_2 i/o levels except for the reset# input which is lvcmos. data flow from d to q is controlled by the differential clock, clk, clk# and reset#. data is triggered on the positive edge of clk. clk# must be used to maintain noise margins. reset# must be supported with lvcmos levels as vref may not be stable during power-up. reset# is asynchronous and is intended for power-up only and when low assures that all of the registers reset to the low sta te, q outputs are low, and all input receivers, data and clock are switched off. the icssstv32852 supports low-power standby operation. when reset# is low, the differential input receivers are disabled, and are allowed. in addition, when reset# is low, all registers are reset, and all outputs are forced low. the lvcmos reset# input must always be held at a valid logic high or low level. to ensure defined outputs from the register before a stable clock has been supplied, reset# must be held in the low state during power up. in the ddr dimm application reset# is specified to be completely asynchronous with respect to ck and ck#. therefore, no timing relationship can be guaranteed between the two. when entering reset#, the register will be cleared and the outputs will be driven low quickly, relati ve to the time to disable the differential input receivers, thus ensuring no glitches on the output. however, when coming out of reset#, the register will become active quickly, relative to the time to ena ble the differential input receivers. when the data inputs are low, and the clock is stable, during the time from the low-to-high transition of reset# until the input receivers are fully enabled, the design must ensure that the outputs will remain low. r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d , 1 k , 1 l , 2 l , 1 m , 2 n , 1 n , 1 p , 1 r , 2 f , 1 f , 2 g , 1 g , 1 h , 1 j , 2 j , 2 k 2 a , 1 a , 1 b , 2 c , 1 c , 2 d , 1 d , 1 e a ) 1 : 4 2 ( qt u p t u ot u p t u o a t a d , 6 k , 6 l , 5 l , 6 m , 5 n , 6 n , 6 p , 6 r , 5 f , 6 f , 5 g , 6 g , 6 h , 6 j , 5 j , 5 k 5 a , 6 a , 6 b , 5 c , 6 c , 5 d , 6 d , 6 e b ) 1 : 4 2 ( qt u p t u ot u p t u o a t a d , 3 p , 3 m , 3 l , 3 j , 3 g , 3 d , 3 b , 2 e 5 e , 4 p , 4 m , 4 l , 4 j , 4 g , 4 d , 4 b d n gr w pd n u o r g , 3 k , 3 h , 3 f , 3 e , 3 c , 2 p , 2 m , 2 b , 5 b , 4 n , 4 k , 4 h , 4 f , 4 e , 4 c , 3 n 5 p , 5 m q d d vr w pl a n i m o n v 5 . 2 , e g a t l o v y l p p u s t u p t u o , 4 t , 5 v , 6 w , 5 w , 4 u , 4 v , 4 w , 3 u , 3 v , 3 w , 5 t , 6 t , 5 u , 6 u , 6 v , 2 u , 1 u , 1 v , 3 t , 2 v , 1 w , 2 w 2 t , 1 t ) 1 : 4 2 ( dt u p n it u p n i a t a d 3 ak l ct u p n it u p n i k c o l c r e t s a m e v i t i s o p 4 a# k l ct u p n it u p n i k c o l c r e t s a m e v i t a g e n 5 r , 2 r , 5 h , 2 hd d vr w pl a n i m o n v 5 . 2 , e g a t l o v y l p p u s e r o c 3 r# t e s e rt u p n i) w o l e v i t c a ( t e s e r 4 rf e r vt u p n il a n i m o n v 5 2 . 1 , e g a t l o v e c n e r e f e r t u p n i
3 icssstv32852 preliminary product preview third party brands and names are the property of their respective owners. absolute maximum ratings storage temperature . . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.6v input voltage 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to vdd +0.5 output voltage 1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to vddq +0.5 input clamp current . . . . . . . . . . . . . . . . . . . . . . . 50 ma output clamp current . . . . . . . . . . . . . . . . . . . . . 50ma continuous output current . . . . . . . . . . . . . . . . . 50ma vdd, vddq or gnd current/pin . . . . . . . . . . . . 100ma package thermal impedance 3 . . . . . . . . . . . . . . . . . . . . ??c/w stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. notes: 1. the input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. this current will flow only when the output is in the high state level v 0 >v ddq . 3. the package thermal impedance is calculated in accordance with jesd 51. recommended operating conditions parameter min typ max units v dd 2.3 2.5 2.7 v ddq 2.3 2.5 2.7 v ref 1.15 1.25 1.35 v tt v ref -0.04 v ref v ref -0.04 v i input voltage 0 v dd v ih (dc) dc input high voltage v ref +0.15 v ih (ac) ac input high voltage v ref +0.31 v il (dc) dc input low voltage v ref -0.15 v il (ac) ac input low voltage v ref -0.31 v ih input high voltage level 1.7 v il input low voltage level 0.7 v icr common mode input range 0.97 1.53 v id differential input voltage 0.36 v ix (v ddq /2) -0.2 (v ddq /2) +0.2 i oh tbd i ol tbd t a 070c 1 guarenteed by design, not 100% tested in production. operating free-air temperature reset# clk, clk# v termination voltage cross point voltage of differential clock pair high-level output current low-level output current data inputs ma description supply voltage i/o supply voltage reference voltage v ref = 0.5x v ddq
4 icssstv32852 preliminary product preview third party brands and names are the property of their respective owners. electrical characteristics - dc t a = 0 - 70o c; v dd = 2.5 v +/-200mv, v ddq =2.5v +/-200mv; (unless otherwise stated) symbol parameters v dd min typ max units v ik i i = -18ma 2.3v -1.2 i oh = -100a 2.3v-2.7 v d d -0.2 i oh = -16ma 2.3v 1.95 i ol = 100a 2.3-2.7v 0.2 i ol = 16ma 2.3v 0.35 i i all inputs v i = v d d or gnd 2.7v 5 a standb y (static) reset# = gnd .01 a operating (static) v i = v ih (ac#) or v il (ac), reset# = v d d 45 ma dynamic operating clock only reset = v dd , v i = v ih(ac) or v il (ac) , ck and ck# switching 50% duty cycle. ck, ck# @ 200mhz. 35 /clock mhz dynamic operating per each data input reset# = v dd , v i = v ih(ac) or vil (ac), ck and ck# switching 50% duty cycle. one data i nput switching at half clock frequency, 50% duty c y cle tbd a/ clock mhz/data r oh output high 2.3-2.7v ? r ol output low 2.3-2.7v ? r o(d) [r oh - r ol ] each separate bit 2.5v ? data inputs 2.5 3.5 ck and ck# 2.5 3.5 notes: 1 - guaranteed by design, not 100% tested in production. c i i ol = 20ma i o = 20ma, t a = 25 c v oh v ol i dd i ddd i o = 0 conditions 2.7v 2.5v v i = v ref 350mv v ic r = 1.25v, v i ( pp ) = 360mv pf i oh = 20ma v
5 icssstv32852 preliminary product preview third party brands and names are the property of their respective owners. timing requirements (over recommended operating free-air temperature range, unless otherwise noted) min max f clock clock frequency 200 mhz t pd clock to output time 2.6 ns t rst reset to output time 4 ns t sl output slew rate 1 4 v/ns setup time, fast slew rate 2, 4 0.75 ns setup time, slow slew rate 3, 4 0.9 ns hold time , fast slew rate 2, 4 0.50 ns hold time, slow slew rate 3, 4 0.70 ns 1 - guaranteed by design, not 100% tested in production. 2 - for data signal input slew rate 3 1v/ns. 4 - clk, clk# signals input slew rates are 3 1v/ns. symbol t su t h notes: 3 - for data signal input slew rate 3 0.5v/ns and < 1v/ns. v dd = 2.5v 0.2v units parameters data before ck- , ck# data after ck- , ck# switching characteristics (over recommended operating free-air temperature range, unless otherwise noted) min typ max fmax 200 mhz t pd clk, clk# q 1.1 2.6 ns t ph1 clk, clk# q 5 ns symbol v dd = 2.5v 0.2v units from (input) to (output)
6 icssstv32852 preliminary product preview third party brands and names are the property of their respective owners. notes: 1. cl incluces probe and jig capacitance. 2. i dd tested with clock and data inputs held at v dd or gnd, and io = 0ma. 3. all input pulses are supplied by generators having the following chareacteristics: prr 10 mhz, zo=50 ? , input slew rate = 1 v/ns 20% (unless otherwise specified). 4. the outputs are measured one at a time with one transition per measurement. 5. v tt = v ref = v ddq /2 6. v ih = v ref + 310mv (ac voltage levels) for differential inputs. v ih = v dd for lvcmos input. 7. v il = v ref -310mv (ac voltage levels) for differential inputs. v il = gnd for lvcmos input. 8. t plh and t phl are the same as t pd test point load circuit from output under test c = 30 pf (see note 1) l v tt r = l 50? lvcmos reset# input lvcmos reset# input v/2 dd t inact t act i (see note 2) dd i ddh i ddl 10% 90% voltage and current waveforms inputs active and inactive times voltage waveforms - propagation delay times voltage waveforms - propagation delay times parameter measurement information (v = 2.5v 0.2v) dd voltage waveforms - pulse duration voltage waveforms - setup and hold times v/2 dd v dd 0v t w t su t h v ih v ih v oh v tt v tt v tt v oh v ih v il v il v ol v ol v i(pp) v i(pp) v il v ref v ref v ref v ref v icr v icr t phl t phl t phl v/2 dd v icr input input timing input timing input output output
7 icssstv32852 preliminary product preview third party brands and names are the property of their respective owners. registered company 9001 for more information on integrated circuit systems inc. or any of our products please visit our web site at: http://www.icst.com d e t min/max e horiz vert total d hmin/max b c 16.00 bsc 5.50 bsc 1.30/1.50 0.80 bsc 6 19 114 0.46 0.31/0.41 0.80 0.75 10-0055 all dimensions in millimeters ref. dimension s ----- ball grid ----- ordering information icsstv32852 y ft designation for tape and reel packaging package type h = bga revision designator (will not correlate with datasheet revision) device type prefix ics = standard device example: ics xxxx y h - t
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