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scdct1820 rev f description the aeroflex plainv iew ct1820 bit processor unit (bpu) is an adva nced hybrid microcircuit that provides the interface between a mil-std-1553 tr ansceiver such as ct3231m or ct 3232m, and the subsystem internal parallel data bus. the unit can be employed as the mux bus interface for remote subsystems or master terminal bus controllers, thus providing a common interface for all systems communicating over the bus. the unit places no restrictions on command, response or polling operation s as it transfers all command, status and data words from the bus to parallel output line s, together with error in formation, bus status and handshaking signals. it also contains 5 bit address recognition, broadcast and mode code decode, terminal fail safe signal and self test. in the transmit mode, it accepts parallel data from th e user and transmits command, status and data words, under subsystem control, to the data bus. positive handshaking signals provide logic control synchronisation between the unit and the subs ystem for direct data flow. the hybrid is completely compatible with all the electrical and functi onal specification requirements of mil-std-1553 a & b. features ? performs encoder, decoder, logic and control func tions of a data bus terminal to mil-std-1553 specifications, including address, mode code and broadcast decoding and terminal fail safe ? flexibility - all control lines accessible ? parallel tri-state subsystem l/o bus compatible with both 16 bit and 8 bit systems ? dual rank l/o registers for versatile subsystem tlmlng ? operates from +5vdc @ 50ma ? self-contained +5vdc oscillator and clock driver @ 13 ma ? look-ahead serial receive data output ? self-test, on-line wraparound, plus off-line capability ? full military (-55c to +125c) temperature range ? designed for commercial, industri al and aerospace applications ? mil-prf-38534 compliant ? packaging C metal hermetic - 56 pin, plug-in, 1.155"w x 2.155"l x .200"ht - 60 lead, flat-pack, 1.015"w x 1.59"l x .147"ht ? desc standard microcircuit drawing (smd): 5962-90636 ct1820 data terminal bit processor www.aeroflex.com/avionics april 10, 2008 for mil-std-1553 a & b
2 scdct1820 rev f 4/10/08 aeroflex plainview figure 1 C functional diagram 43 36 12 serial data out 32 8 9 10 13 14 16 33 31 37 7 45 46 47 48 50 44 42 41 2 3 4 5 6 54 56 56 43 43 43 53 11 34 20 21 22 19 25 26 15 27 28 24 23 38 35 30 29 18 17 1 first rank rec?v reg d0 - d7 second rank rec?v reg d0 - d7 first rank rec?v reg d8 - d15 second rank rec?v reg d8 - d15 first rank xmt reg do - d7 second rank xmt reg do - d7 first rank xmt reg d8 - d15 second rank xmt reg d8 - d15 manchester decoder & control logic manchester encoder & control logic osc & clock driver 39 40 broad- cast decode rt enable (msb) a4 a3 a2 a1 (lsb) a0 5 bit address { broadcast mode code valid word comm/data sync mode code decode dec rst take data dsc out d1 (lsb) d0 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 (msb) d15 (optional) serial input latch data 2 latch data 1 load data 2 load data 1 gnd gnd vcc +5v case data in data in bit select data out data out fail safe send data escout sync sel enc ena output inh mrst +5v osc / clock power xtal clock out clock in data select 1 data select 2 built in test select address decode fail safe timer & control (plug-in pins shown)
3 scdct1820 rev f 4/10/08 aeroflex plainview absolute maximum ratings parameter range units supply voltage +7.0 v logic input voltage -0.3 to +5.5 v clock output current (pin 18 - plug-in) 15 ma clock in (pin 17 - plug-in) -0.3 to vcc +0.3v v storage temperature range -65 to +150 c operating case temperature range -55 to +125 c electrical characteristics (v cc = 5.0v 10%, t c = -55c to +125c) sym parameter / conditions min typ max units v ih logic "1" input voltage 2.0 - - v v il logic "0" input voltage --0.7v v oh logic "1" output voltage see pin assignments and loading v ol logic "0" output voltage see pin assignments and loading v ihc logic "1" input voltage (clock) v cc -0.5 - v v ilc logic "0" input voltage (clock) -gnd+0.5v v ohc logic "1" output voltage (clock) v cc -0.3 - v v olc logic "0" output voltage (clock) -gnd+0.3v l oc logic supply current --50ma l osc oscillator / clock supply current 813ma data bus rx data in rx data in tx data out tx data out tx data in tx data in rx data out rx data out data in data in data data out tx inhibit out xtal 12 mhz control data 16 bit or 8 bit sub- sysyem 22 21 26 25 29 ct1820 bit processor 1 25 2 26 10 7 33 32 31 ct3231 t/r hybrid figure 2 C typical mil-std-1553 data terminal
4 scdct1820 rev f 4/10/08 aeroflex plainview electrical characteristics C pin assignments and loading in the following table, the sy mbols are defined as follows: i ih = maximum input high current with v ih = 2.5 volts i il = maximum input low current with v il = 0.4 volts i oh = maximum output high current for v oh = 2.5 volts minimum i ol = maximum output low current for v ol = 0.4 volts maximum * indicates use of an in ternal pull-up resistor pin no name ct1820 ct1820-2 description plug in flat pack i ih (a) i il (ma) i oh (a) i ol (ma i ol (ma) 16 vcc -- -- - +5v power input 27 d8 20 -0.4 -1000 6.0 10.0 part of 16 bit tri-state l/o 38 d9 49 d10 510 d11 611 d12 712 data select 1 20 -0.4 a low on this input applies the co ntents of the second rank recv reg to the d8-d15 i/o pins 813 a3* 20 -0.4 part of 5 bit address input 914 a2* 10 15 a1* 11 16 ground logic and power return 12 17 a4* 20 -0.4 msb of 5 bit address input 13 18 a0* lsb of 5 bit address input 14 19 valid word -400 4.0 4.0 a low on this output indica tes receipt of avalid word 15 20 fail safe -400 4.0 4.0 a high on this output indicates termination of a transmitted message that exceeds 768s. 16 21 comm / data sync -400 4.0 4.0 a high on this output indicates command (or status) word reception. a low indicates data word reception. 17 22 clock in +100 +0.1 input for 12mhz clock (20pf load). 18 23 clock out -1000 1.0 1.0 output of oscillator and clock driver. 19 24 s/t select 20 -0.4 a high on this input sets the unit in the self test mode. 20 25 case case connection 21 26 data in 20 -0.4 a high on this input represents a positive state on the bus. 22 27 data in 20 -0.4 a high on this input represents a negative state on the bus. (pins 21 and 22 must both be high when the bus is inactive.) 23 28 enc ena 20 -0.4 a low on this input initiates a transmit cycle. 24 29 sync sel 20 -0.4 actuates command (or status) sync for an input low and data sync for an input high. 25 32 data out -400 4.0 4.0 a high on this output produces a positive state on the bus. 26 33 data out -400 4.0 4.0 a high on this output produces a negative state on the bus. 27 34 send data -400 4.0 4.0 a hlgh on this output indicates data shifting during the transmit cycle. 28 35 esc out -1000 1.2 1.2 low to high transitions on thls ou tput during high send data cause the transmit cycle data shifting to occur. 29 36 xtal a 12mhz (parallel resonant) crys tal is connected between this pin and ground. 30 37 +5v (osc/clock) +5v power for osci llator and clock power driver. 31 38 dsc out -1000 1.2 1.2 low to high transitions on this output during low take data cause receive cycle data shifting to occur. 32 39 rt enable -400 4.0 4.0 a high on this output indicates reception of a valid command (or status) word containing the terminals address. it also resets the fail safe.
5 scdct1820 rev f 4/10/08 aeroflex plainview 33 40 dec rst 20 -0.4 a low on this input (for 1s minimum) resets the decoder to a condition ready for a new word, resets the comm / data sync output low, and resets the valid word output high. 34 41 ground logic and power return. 35 42 output inh 20 -0.4 a low on this input holds output pins 25 and 26 low. 36 43 serial data out -400 4.0 4.0 the received serial data in nrz format is available at this pin during low take data . 37 44 take data -400 4.0 4.0 a low on this output indicates da ta shifting during the receive cycle. 38 45 mrst 20 -0.4 a low on this input (for 1s minimum) interrupts and clears the transmit cycle, resets the fail safe, and also performs the same functions as dec rst . 39 46 broadcast * -400 4.0 4.0 a high on this output indicates reception of a valid command (or status) word containing all ones in the address field. 40 47 mode code * -600 6.0 6.0 a low on this output indicates reception of a valid command (or status) word containing all ones or all zeros in the sub-address field. 41 48 d6 20 -0.4 -1000 6.0 10.0 part of 16 bit tri-state l/o 42 49 d7 43 50 data select 2 20 -0.4 a low on this input applies the co ntents of the second rank recv reg to the d0-d7 i/o pins. 44 51 d5 20 -0.4 -1000 6.0 10.0 part of 16 bit tri-state l/o 45 52 d0 lsb of 16bit tri-state i/o 46 53 d1 part of 16 bit tri-state l/o 47 54 d2 part of 16 bit tri-state l/o 48 55 d3 part of 16 bit tri-state l/o 49 56 latch data 2 -0.4 a high on this input allows the l/o data on d0-d7 to appear at the output of the first rank xmt reg. a low on this input holds the register outputs in their last state. 50 57 d4 -0.4 -1000 6.0 10.0 part of 16 bit trl-state l/o 51 58 load data 2 -0.4 a low on this input loads the d0-d7 data into the second rank xmt reg. a high on this input then locks out the data inputs to permit serial shifting. 52 59 latch data 1 a high on this input allows the l/o data on d8-d15 to appear at the output of the first rank xmt reg. a low on this input holds the register outputs in their last state. 53 2 load data 1 20 -0.4 a low on this input loads the d8-d15 data into the second rank xmt reg. a high on this input then locks out the data inputs to permit serial shifting. 54 3 d13 -0.4 -1000 6.0 10.0 part of 16 bit trl-state l/o. optional serial input. 55 4 d14 56 5 d15 -1 nc -- -- - no contact -30 nc -- -- - -31 nc -- -- - -60 nc -- -- - electrical characteristics C pin assignments and loading cont in the following table, the sy mbols are defined as follows: i ih = maximum input high current with v ih = 2.5 volts i il = maximum input low current with v il = 0.4 volts i oh = maximum output high current for v oh = 2.5 volts minimum i ol = maximum output low current for v ol = 0.4 volts maximum * indicates use of an in ternal pull-up resistor pin no name ct1820 ct1820-2 description plug in flat pack i ih (a) i il (ma) i oh (a) i ol (ma i ol (ma)
6 scdct1820 rev f 4/10/08 aeroflex plainview transmit cycle operation encoder shift clock (esc) (s ee figure 3) operates at the data rate (1mhz). a low at encoder enable (enc ena ) during a falling edge of esc starts the transmit cycle, which lasts for twenty esc clock periods. the sync select (sync sel) input is valid at the next low-to-high transition of esc . a high at sync sel will produce a data sync, or a low will produce a command sync for that word. parallel data must be stable at the second rank transmit register before send data goes high . since enc ena is not synchronous with esc, the minimum time to is 3sec from enc ena leading edge. the first-rank transmit register may be operated transparently (latch data always high), or may be used to hold data ready for transmissi on, independent of the activity on the 16-line subsystem l/o bus. as long as latch data is held high, data present on the subsystem l/o bus appears at the output of the first rank transmit register. stable data may be latched and held at the first rank register output by bringing latch data low. data to be transmitted may be latched any time before the lo w-to high transition of send data (send data, when appled to the load data inputs, locks out the data inputs to the second rank transmit register.) for multiple word transmissions, the next word may be inputted and la tched any time after , but before the next low to-high transition of send data. send data remains high for 16 esc periods, during which the parallel transmit data is clocked to the manchester encoder to . after the sync and manchester coded data are transmitted through the data out and data out outputs, the encoder adds on the parity bit for that word . if the transmitted word is to be the last word of the transmission, enc ena must go high by to prevent initiation of another transmit cycle. at any time, a low applied to output inhibit will force both data out and data out to a low state without affecting any other operations. the entire transmit cycle may be interrupted and cleared by applying a minimum of 1sec negative pulse to the master reset (mrst ) input. for 8-blt i/o subsystems, d0 is tied to d8, d1 tied to d9, etc., through d7 tied to d15, and data is inputted in 8-blt bytes by using latch data 1 and latch data 2 and/or load data 1 and load data 2 independently. for serial data applications, d15 input serves as the serial transmit input. with load data 1 held low and latch data 1 held high, d15 input is applied to the encoders serial data input. in putted data must be at the esc rate with the msb starting at the low-to-h igh transition of send data. if a message length ever exceeds 768sec, the 768sec time out (fail safe) flag go es high, and data out and data out are both forced to a low state. this condition will remain until a valid command word (containing the terminals address) is received or until mrst goes low. 2 ? sync? sync151413 210p? sync? sync151413 210p ? sync ? sync 15 14 13 2 1 0 p ? sync ? sync 15 14 13 2 1 0 p 4 5 012345 161718190123 45 16 17 18 19 3 2 1 valid don?t care don?t care don?t care don?t care valid see text see text don?t care esc sync sel enc ena latch data data select send data & load data data out data out if used depends on "latch" timing optional next-word latch depends on "latch" timing optional next-word latch figure 3 C transmit cycle timing
7 scdct1820 rev f 4/10/08 aeroflex plainview symbol description min max units t e 1 encoder enable set-up time 100 - ns t e 2 encoder enable hold time 80 - ns t e 3 sync select set-up time 125 - ns t e 4 sync select hold time 150 - ns t e 5 send data delay time -75ns t e 6 latch data hold time 25 - ns t e 7 latch data set-up time 50 - ns t e 8, t e 12 1 / parallel data set-up time 40 - ns t e 9, t e 13 1 / parallel data hold time 60 - ns t e 10 data select disable time 30 - ns t e 11 data select hold time 0-ns note: 1 / t e 12 and t e 13 apply when latch data is not used. figure 4 C encoder timing detail
8 scdct1820 rev f 4/10/08 aeroflex plainview receive cycle operation decoder shift clock (dsc) (see figure 5) operates at the data rate (1mhz). when the decoder recognises a valid sync and two vali d manchester data bits , a receive cycle is initiated. the new sync is indicated at the command/data sync (c/d sync) output and the take data output goes low . the c/d sync output will remain in its valid state until a new sync is detected on a subsequent word or until decoder reset (dec rst ) or mrst goes low. a low at dec rst or mrst causes c/d sync to go low. take data remains low for 16 ds c periods during which time the 16 serial data bits appear at the serial data output (sdo). this data is si multaneously loaded into the first-rank receive register. the low-to-high transition of take data makes the new data available at the output of the second-rank receive re gister. this data remains available until the next low- to-high transitions of take data . it is not reset or cleared by any other signals. this data is applied to the d0 to d15 i/o bus by setting data select lines low. after all data has been loaded into the receive registers, the data is checked for odd parity. a low on valid word (vw ) output , indicates successful reception of a word without any manchester or parity errors. for consecutive word receptions, vw will go high again in 3 to 3.5s. in the absence of succeeding valid syncs, vw will return high in 20s. a dec rst (low) at any time will reset vw high. all decoded commands, incl uding rt enable (address recognition), broadc ast and mode code are enabled internally by vw and remain valid only as long as vw is low. for 8-bit l/o subsystems (d0 ti ed to d8, through d7 tied to d15), data may be extracted in 8 bit bytes by selectively activating data select 1 and data select 2 . for serial data systems, seri al data output is available at the dsc rate from to . . 2 2 012345 16171819012345 16171819 ? sync ? sync 15 14 13 2 1 0 p ? sync ? sync 15 14 13 2 1 0 p ? sync ? sync 15 14 13 2 1 0 p ? sync ? sync 15 14 13 2 1 0 p from previous word 15 43210 15 4321 0 4 3 2 1 from previous word undefined valid for current word valid for current word undefined not valid from previous word optional?high = tristate hi-z at d0 to d15 optional?high = tristate hi-z at d0 to d15 new data valid not valid valid new data osc data in data in take data c/d sync sdo vw decode commands second-rank rec?v data select (see text) register content figure 5 C receive cycle timing
9 scdct1820 rev f 4/10/08 aeroflex plainview symbol description min max units t d 1 take data delay on time -125ns t d 2 take data delay off time -125ns t d 3 sync delay time -60ns t d 4 valid word delay time -125ns t d 5 broadcast delay time -70ns t d 6 rt enable delay time -100ns t d 7 mode code delay time -100ns t d 8 data select input delay time 1 / 0-ns t d 9 parallel data output delay time -60ns note: 1 / data select may be applied at any tlme that the 16 line i/o is otherwise free. the parallel data out, however, is not new da ta until after take data goes high. figure 6 C decoder timing detail
10 scdct1820 rev f 4/10/08 aeroflex plainview self test function a high on the s/t select input sets the hybrid in the self test mode. in this m ode, the data and data output lines are connected to the decoder inputs so that the unit may operate in the "wraparound" mode without actually going through the data bus transceiver. note that the data and data output lines are active in this mode and the s/t select command must also be used to inhibit the data bus transmitter to prevent arbitr ary transmission on the data bus. terminal fail safe in order to satisfy the termina l fail safe requirements of mil-std-1553b, the data and data output lines are continuously monitored for length of message. a transmitted message in excess of 768s sets the fail safe output high and terminates the transmission by setting both data and data output lines low. as a redundant safety factor, the fallsafe output ma y be applied to the lnhlblt input of the data bus transmit ter (if so equipped). further transmissions are prevented until the fail safe flag is reset either by reception of a vali d command word containing the terminal address or by a ne gative pulse on the mrst input. note: transmissions containing gaps of 3s or less are considered continuous, even if the gap is caused by a mrst pulse. terminal address lines the five-bit terminal address is set by hard wiring the 5-blt address lines. the hybrid contains internal pull-up resistors so that logic "1" li nes may be left open circuited. logic "0" lines must be grounded. in operation, rt enable goes high when a valid command word containing the hard-wired address is received. see "receive cycle operation" for timing. oscillator and clock driver the hybrid may be operated wit h either the internal clock or an external clock source. for internal clock operation , a 12mhz parallel-resonant fundamental-mode crystal must be connected from xtal to ground. power (+5v) must be applied to +5v osc/clock power and clock out must be connected to clock in. for external clock operation, no power is applied to +5v osc/clock power and the exte rnal clock is applied to clock in (clock out not connected). the external clock must be capable of driving a 20 picofarad load to within 0.5 volts of vcc and within 0.5 volts of ground with rise and fall times of less than 10 nanoseconds. standard ttl levels are not satisfactory. for a normal 1mhz data rate, the clock frequency must be 12mhz. false rt enable terminals that continuously monitor their own transmissions are subject to "end-around" operation due to a false rt enable. the terminal can erroneously interpret its own status word as a new command word. if no measures are taken to prevent or re-set rt enable, it will remain high for 20s or until the decoder recognises a new valid sync (whichever time is shorter). rt enable may be inhibited by interrupting the receive cycle during a status word transmission. inverted send data applied to dec rst will prevent reception of the status word. if continuous monitoring is required, rt enable may be reset immediately after it goes high by a 1s (minimum) low at dec rst . the status word will th en be available at the second-rank receive register.
11 scdct1820 rev f 4/10/08 aeroflex plainview pin out description (flat pack) pin # function pin # function 1nc 31nc 2load data 1 32 data out 3d13 33data out 4d14 34send data 5d15 35esc out 6vcc 36 xtal 7 d8 37 +5v (osc/clock) 8d9 38dsc out 9d10 39rt enable 10 d11 40 dec rst 11 d 12 41 g r o u n d 12 data s e l ec t 1 42 output inh 13 a3 43 serial data out 14 a2 44 take data 15 a1 45 mrst 16 ground 46 broadcast 17 a 4 47 m o d e c o d e 18 a0 48 d6 19 valid word 49 d7 20 fail safe 50 data select 2 21 com m/data sync 51 d5 22 clock in 52 d0 23 clock out 53 d1 24 s/t select 54 d2 25 case 55 d3 26 data in 56 latch data 2 27 data in 57 d4 28 enc ena 58 load data 2 29 sync sel 59 latch data 1 30 nc 60 nc pin out descript ion (plug-in) pin # function pin # function 1 vcc 29 xtal 2 d8 30 +5v (osc/clock) 3d9 31dsc out 4 d10 32 rt enable 5d11 33dec rst 6d12 34ground 7data select 1 35 output inh 8a3 36 serial data out 9a2 37take data 10 a1 38 mrst 11 g r o u n d 3 9 b r o a d c a s t 12 a4 40 mode code 13 a0 41 d6 14 va li d w o rd 42 d7 15 fai l safe 43 data select 2 16 comm/data sync 44 d5 17 clock in 45 d0 18 clock out 46 d1 19 s/t select 47 d2 20 case 48 d3 21 data in 49 l atch data 2 22 data in 50 d4 23 enc ena 51 loa d data 2 24 sync sel 52 latch data 1 25 data out 53 load data 1 26 data out 54 d13 27 send data 55 d14 28 esc out 56 d15
12 scdct1820 rev f 4/10/08 aeroflex plainview plug-in package outline m m s e h c n i 5 0 . 2 0 0 . 6 4 . 8 1 0 . 4 5 . 2 0 0 1 . 8 0 . 5 0 0 2 . 3 4 . 1 1 0 5 4 . 6 8 . 2 2 0 0 9 . 4 3 . 9 2 5 5 1 . 1 6 2 . 8 4 0 0 9 . 1 4 7 . 4 5 5 5 1 . 2 : s e t o n . s e h c n i n i e r a s n o i s n e m i d . 1 . y l n o n o i t a m r o f n i l a r e n e g r o f n e v i g e r a s t n e l a v i u q e c i r t e m . 2 c e p s e s i w r e h t o s s e l n u . 3 ified, tolerances are . 005 (0.13 mm) for three place decimals. top view
13 scdct1820 rev f 4/10/08 aeroflex plainview flat package outline m m s e h c n i 5 0 . 2 0 0 . 3 1 . 5 0 0 . 8 3 . 5 1 0 . 9 8 . 8 0 5 3 . 8 7 . 5 2 5 1 0 . 1 3 8 . 6 3 0 5 4 . 1 9 3 . 0 4 0 9 5 . 1 : s e t o n . s e h c n i n i e r a s n o i s n e m i d . 1 . y l n o n o i t a m r o f n i l a r e n e g r o f n e v i g e r a s t n e l a v i u q e c i r t e m . 2 top view .065 .065 .005 .147 .147 1.65 3.73 .010 .254 max
14 plainview, new york toll free: 800-the-1553 fax: 516-694-6715 se and mid-atlantic tel: 321-951-4164 fax: 321-951-4254 international tel: 805-778-9229 fax: 805-778-1980 west coast tel: 949-362-2260 fax: 949-362-2266 northeast tel: 603-888-3975 fax: 603-888-4585 central tel: 719-594-8017 fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com aeroflex microelectronic solutions reserves the right to change at any time without notice the specifications, design, function, or form of its products described herein. all parameters must be validated for each customer's application by engineering. no liability is assumed as a result of use of this product. no patent licenses are implied. scdct1820 rev f 4/10/08 our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused export control: export warning: this product is controlled for expor t under the international traffic in arms regulations (itar). a license from the u.s. department of state is required prior to the export of this product from the united states. aeroflex?s military and space pr oducts are controlled for export under the international traffic in arms regulations (itar) and may not be sold or proposed or offered for sale to certain countries. (see itar 126.1 for complete information.) ordering information aeroflex part # dscc smd # screening package ct1820 - military temperature, -55c to +125c screened in accordance with mil-prf-38534, class h plug-in ct1820-fp - flat pack ct1820-2 - plug-in ct1820-2-fp - flat pack ct1820-001-1 ct1820-001-2 5962-9063601hxc 5962-9063601hxa per dscc smd 5962-90636 plug-in ct1820-2-001-1 CT1820-2-001-2 5962-9063602hxc 5962-9063602hxa ct1820-201-1 5962-9063601hyc flat pack ct1820-2-201-1 5962-9063602hyc

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