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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is grante d by implication or otherwise under any patent or patent rights of anal og devices. a adm9240 one technology way, p.o. box 9106, norwood, ma 0206 2-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.an alog.com fax: 781/326-8703 ? analog devices, inc., 1998 low cost microprocessor system hardware monitor functional block diagram bandgap temperature sensor fan1 scl sda a1 ntest_out/a0 fan2 ci int ntest_in/aout reset vid0 vid1 vid2 vid3 vid4 +v ccp1 +2.5v in +3.3v in +5v in +12v in +v ccp2 vid0 - 3 and fan divisor registers vid4 and device id register input attenuators and analog multiplexer fan speed counter address pointer register temperature configuration register 9-bit adc serial bus address register adm9240 limit comparators interrupt status registers int mask registers chassis intrusion clear register serial bus interface analog output register and 8-bit dac value and limit registers v cc configuration register gnda gndd features six direct voltage measurement inputs (including two processor core voltages) with on-chip attenuators on-chip temperature sensor five digital inputs for vid bits fully supports intels landesk client manager (ldcm ) register-compatible with lm7x products two fan speed monitoring inputs i 2 c ? compatible system management bus (smbus) chassis intrusion detect interrupt output programmable reset i/o pin shutdown mode to minimize power consumption limit comparison of all monitored values applications network servers and personal computers microprocessor-based office equipment test equipment and measuring instruments product description the adm9240 is a complete system hardware monitor f or microprocessor-based systems, providing measurement and limit comparison of up to four power supplies and t wo proces- sor core voltages, plus temperature, two fan speeds and chassis intrusion. measured values can be read out via an i 2 c-compat- ible serial system management bus, and values for l imit com- parisons can be programmed in over the same serial bus. the high speed successive approximation adc allows freq uent sampling of all analog channels to ensure a fast in terrupt response to any out-of-limit measurement. the adm9240s 2.85 v to 5.75 v supply voltage range , low supply current and i 2 c compatible interface, make it ideal for a wide range of applications. these include hardware monitoring and protection applications in personal computers, electronic test equipment and office electronics. i 2 c is a registered trademark of philips corporation. ?2010 scillc. all rights reserved. publication order number: may 2010 - rev. 2 adm9240/d adm9240 low cost microprocessor system hardware monitor fu fu fu fu nc nc nc nc ti on on on on al al al al block d d d ia ia ia ia gr gr gr gr am am am am bandgap temperatu re sen sor fan1 scl sda a1 ntest_out/a0 fan2 ci int ntest_in/aout reset vid0 vid1 vid2 vid3 vid4 +v ccp1 +2.5v in +3.3v in +5v in +12v in +v ccp2 vid vid vid vid vid vid 0 - 0 - 0 - 0 - 3 3 3 3 3 3 3 and and and and fan fan fan fan fan fan fan divisor reg reg reg reg reg reg reg ist ers vid 4 a 4 a 4 a 4 a 4 a 4 a 4 a nd nd nd nd nd nd nd device id id id id id id id regist er input attenuato rs and analog multiplexer fan sp sp sp sp sp sp sp eed eed eed eed eed eed eed cou cou cou cou cou cou cou nte nte nte nte nte nte nte r r r address pointer register temperature configuration register 9-bit adc ser ial ial ial ial ial ial ial bu bu bu bu bu bu bu s s s s s add add add add add add add res res res res res res res s s s s s s s reg reg reg reg reg reg reg ist ist ist ist ist ist ist er er er er er adm9240 limit comparato rs interr upt sta tus registers int mask int registers chassis int rus ion clear register serial bus interface analog output register and 8-bit dac value and limit registers v v v v v v cc cc cc cc cc cc cc configuration reg ist er gnd a gnd d features six direct voltage measurement inputs (including two processor core voltages) with on-chip attenuators on-chip temperature sensor five d ig ital i np uts for vid bits fully supports intels landesk client manager (ldc m) register-compatible with lm7x products two fan speed monitoring inputs i 2 c ? compatible system management bus (smbus) chassis intrusion detect interr up t ou tp ut pr og rammable reset i/o pin shutdown mode to minimize power consumption limit comparison of all monitored values applications network servers and personal computers microprocessor-based office equipment test equipment and measuring instrumen ts ts ts ts pr od uc t de sc ript io n the adm9240 is a complete system hardware monitor f o r microprocessor-based systems, providing measurement and limit comparison of up to four power supplies and t wo proces- sor core voltages, p p p lus temperature, two fan speeds and chassis intrusion. m ea su su su re re d d d values can be read out via an i 2 c-compat- ible serial sy sy sy st st st em em em m m m an an an an ag ag ag ag ement bus, and values for limit com- parisons c c an an an b b b e pr pr pr og og og ra ra ra mm mm mm mm ed ed in over the same serial bus. the high s pe pe pe ed ed ed s s s uc ce ce ce ss ss ss iv iv iv iv e ap ap ap pr pr pr ox ox ox imation adc allows frequent sa mp mp mp li li li ng ng ng o o o f f f all an an an al al al og og og c c c ha ha ha nnels to ensure a fast interrupt re re re sp sp sp on on on se t t t o o o an an an y y y ou t- t- t- of of of -limit measurement. th th th e ad ad ad m9 24 24 24 0 0 s s s 2.85 v to 5.75 v s s s s up up up up pl pl pl pl y voltage range, low su su su pp pp pp ly ly ly c c c ur ur re re nt and i 2 c compat ib ib ib ib le le le i i i nt nt nt nt er er er face, make it ideal for a wi de de de r an an an ge ge ge o o o f applications. th th th th es es es es e e e e in in in in cl cl ude hardware monitoring an an an d d d pr pr pr ot ot ot ec ec ec tion a pp pp pp li li li li ca ca ca tion s s s in in in in p p p p er er er er so so so so na na na na l computers, electronic te te st st st e e e qu qu qu ipment a a a a nd nd nd nd o o o ff ff ff ic e e e e el el el el ec ec ec tr tr tr on on on on ic ic ic ic s. s. s. s. i 2 c is a registered trademark of philips corporati on. ?2010 scillc. all rights reserved. pub lic ation ord er num ber : may 2010 - rev. 2 adm9240/d
C2C rev. 0 adm9240Cspecifications 1, 2 parameter min typ max units test conditions/comments power supply supply voltage, v cc 2.85 5 5.75 v supply current, i cc 1.4 2.0 ma interface inactive, adc active 1.0 ma adc inactive, dac active 25 100 a shutdown mode temperature-to-digital converter accuracy 3 c C40 c t a +125 c 2 c t a = +25 c resolution 0.5 c analog-to-digital converter (including mux and attenuators) total unadjusted error, tue 2 % note 3 differential nonlinearity, dnl 1 lsb power supply sensitivity 1 %/v total monitoring cycle time 311 331 s +25 c t a +125 c (note 4) 311 353 s C40 c t a +125 c (note 4) input resistance 100 140 200 k analog output output voltage range 0 1.25 v total unadjusted error, tue 3 % i l = 2 ma full-scale error 1 3 % zero error 2 lsb no load differential nonlinearity, dnl 1 lsb integral nonlinearity 1 lsb monotonic by design output source current 2 ma output sink current 1 ma fan rpm-to-digital converter accuracy 6 % +25 c t a +125 c 12 % C40 o c t a +125 c full-scale count 255 fan1 and fan2 nominal input rpm 8800 rpm divisor = 1, fan count = 153 (note 5) 4400 rpm divisor = 2, fan count = 153 (note 5) 2200 rpm divisor = 3, fan count = 153 (note 5) 1100 rpm divisor = 4, fan count = 153 (note 5) internal clock frequency 21.1 22.5 23.9 khz +25 c t a +125 c 19.8 22.5 25.2 khz C40 o c t a +125 c digital output ntest_out output high voltage, v oh 2.4 v i out = 5.0 ma, v cc = 4.25 vC5.75 v 2.4 v i out = 3.0 ma, v cc = 2.85 vC3.45 v output low voltage, v ol 0.4 v i out = C5.0 ma, v cc = 4.25 vC5.75 v 0.4 v i out = C3.0 ma, v cc = 2.85 vC3.45 v open-drain digital outputs ( int , reset , ci) output low voltage, v ol 0.4 v i out = C5.0 ma, v cc = 5.75 v 0.4 v i out = C3.0 ma, v cc = 3.45 v high level output current, i oh 0.1 100 a v out = v cc reset and ci pulsewidth 20 45 ms (t a = t min to t max , v cc = v min to v max , unless otherwise noted) rev. 2 | page 2 of 22 | www.onsemi.com adm9240Cspecifications 1, 2 parameter m in typ m ax units test conditions/comment s power supply supply voltage, v cc 2.85 5 5.75 v supply current, i cc 1.4 2.0 ma interface inactive, adc active 1.0 ma adc inactiv e, dac active 25 100 a shutdown mode temperature-to-digital converter accuracy 3 c C40 c t a t t +125 c 2 c t a = + 25 a a c resolution 0.5 c an al og -t o- di gi ta l co nv er te r (including m ux and attenuators) total unadjusted error, tue 2 % 2 % 2 % no no no no te 3 differential nonlinearity, dnl 1 l 1 l 1 l sb sb sb power supply sensitivity 1 % 1 % 1 % /v /v /v total monitoring cycle time 311 33 33 33 1 s +25 c t a a a t t + + + + 125 c (n ote 4) 31 31 1 3 1 3 1 3 53 53 53 s C s C s C 40 c t t t t a a a t t t t t t + + + + 125 c (note 4) input resistance 10 0 1 0 1 40 40 40 20 20 20 0 k 0 k 0 k 0 k analog output output voltage range 0 1 0 1 0 1 .2 .2 .2 5 v 5 v total unadjusted error, tue 3 % 3 % 3 % i i i l l l = 2 2 2 2 m m m m a a a a full-scale error 1 1 1 3 % 3 % 3 % 3 % 3 % zero error 2 l 2 l 2 l 2 l sb sb sb sb no no no no l l l l oad differential nonlinearity, dnl 1 l 1 l 1 l 1 l sb sb sb sb integral nonlinearity 1 l 1 l 1 l 1 l sb sb sb monotonic by design output source curren t 2 t 2 t 2 t 2 t 2 ma ma ma ma output sink curren t 1 t 1 t 1 t 1 ma ma ma ma fan rpm-to-digital con ve ve ve rt rt rt rt er er er er accuracy 6 % 6 % 6 % 6 % +25 c t a t t +125 c 12 12 12 % C40 o c t a +125 c full-scale count 25 25 25 25 5 fan1 and fan2 no mi mi mi mi na na na na l in pu pu t t t t rp rp rp rp m 8 m 8 m 8 m 8 80 80 80 80 0 r 0 r 0 r 0 r pm divisor = 1, fan count = 153 (n ote 5) 44 44 44 44 00 00 00 00 rpm divisor = 2, fan count = 153 (note 5) 2200 rpm divisor = 3, fan count = 153 (note 5) 1100 rpm divisor = 4, fan count = 153 (n ote 5) internal clock frequency 21.1 22.5 23.9 khz + 25 c t a t t +125 c 19.8 22.5 25.2 khz C40 o c t a +125 c digital output ntest_out output high voltage, v oh 2.4 v i out = 5.0 ma, v cc = 4.25 vC5.75 v cc cc 2.4 v i out = 3.0 ma, v cc = 2.85 vC3.45 v cc cc output low voltage, v ol 0.4 v i out = C5.0 ma, v cc = 4.25 vC5.75 v cc cc 0.4 v i out = C3.0 ma, v cc = 2.85 vC3.45 v cc cc open-drain digital outpu ts ( int , reset , ci) output low voltage, v ol 0.4 v i out = C5.0 ma, v cc = 5.75 v 0. 4 v i out = C3.0 ma, v cc = 3 .4 5 v high level output current, i oh 0. 1 1 00 a v out = v cc reset and ci pulsewidth 20 45 ms t (t a = t min to t max , v cc = v cc cc min to v max , unless otherwise noted ) rev. 2 | page 2 of 22 | www.onsemi.com
C3C rev. 0 adm9240 parameter min typ max units test conditions/comments open-drain serial data bus output (sda) output low voltage, v ol 0.4 v i out = C3.0 ma, v cc = 4.25 vC5.75 v 0.4 v i out = C3.0 ma v cc = 2.85 vC3.45 v high level output current, i oh 0.1 100 a v out = v cc serial bus digital inputs (scl, sda) input high voltage, v ih 0.7 v cc v input low voltage, v il 0.3 v cc v hysteresis 500 mv digital input logic levels (a0, a1, ci, reset , vid0 C vid4, fan1, fan2) input high voltage, v ih 2.4 v v cc = 4.25 vC5.75 v input low voltage, v il 0.8 v v cc = 4.25 vC5.75 v input high voltage, v ih 2.0 v v cc = 2.85 vC3.45 v input low voltage, v il 0.4 v v cc = 2.85 vC3.45 v ntest_in input high voltage, v ih 2.4 v v cc = 4.25 vC5.75 v input high voltage, v ih 2.0 v v cc = 2.85 vC3.45 v digital input current input high current, i ih C1 a v in = v cc input high current, a0, a1, i ih C200 75 a v in = v cc (note 6) input low current, i il 1 a v in = 0 input capacitance, c in 20 pf serial bus timing 7 clock frequency, f sclk 400 khz see figure 1 glitch immunity, t sw 50 ns see figure 1 bus free time, t buf 1.3 s see figure 1 start setup time, t su;sta 600 ns see figure 1 start hold time, t hd;sta 600 ns see figure 1 scl low time, t low 1.3 s see figure 1 scl high time, t high 0.6 s see figure 1 scl, sda rise time, t r 300 ns see figure 1 scl, sda fall time, t f 300 s see figure 1 data setup time, t su;dat 100 ns see figure 1 data hold time, t hd;dat 900 ns see figure 1 notes 1 all voltages are measured with respect to gnd, unle ss otherwise noted. 2 typicals are at t a = +25 c and represent most likely parametric norm. shutdo wn current typ is measured with v cc = 3.3 v. 3 tue (total unadjusted error) includes offset, gain and linearity errors of the adc, multiplexer and on -chip input attenuators, including an external seri es input protection resistor value between zero and 1 k . 4 total monitoring cycle time is the time taken to me asure all six analog inputs plus the temperature se nsor. 5 the total fan count is based on 2 pulses per revolu tion of the fan tachometer output. 6 a0 and a1 have internal 75 k pull-down. 7 timing specifications are tested at logic levels of v il = 0.3 v cc for a falling edge and v ih = 0.7 v cc for a rising edge. specifications subject to change without notice. rev. 2 | page 3 of 22 | www.onsemi.com parameter m in typ m ax units test conditions/comments open-drain serial data bus output (sda) output low voltage, v ol 0.4 v i out = C3.0 ma, v cc = 4.25 vC5.75 v cc cc 0.4 v i out = C3.0 ma v cc = 2.85 vC3.45 v cc cc high level output current, i oh 0.1 100 a v out = v cc serial bus digital inputs (scl, sda) input high voltage, v ih 0. 7 v cc v v v input low voltage, v il input low voltage, v input low voltage, v 0.3 v cc v v v hysteresis 50 0 m 0 m 0 m v v v digital input logic leve ls (a0, a1, ci, reset , vid0 C vid4, fan1, fan2) input high voltage, v ih 2. 4 v 4 v 4 v 4 v v cc = 4 .2 .2 .2 5 5 5 5 5 vC vC vC vC 5. 5. 5. 5. 75 v cc cc input low voltage, v il input low voltage, v input low voltage, v 0. 0. 0. 0. 8 v 8 v 8 v v cc = 4 4 4 4 .2 .2 .2 .2 5 5 5 vC vC vC vC 5.75 v cc cc input high voltage, v ih 2. 0 v 0 v 0 v v cc = = = = 2 2 2 2 .8 .8 .8 .8 5 5 5 vC3.45 v cc cc input low voltage, v il input low voltage, v input low voltage, v 0. 0. 0. 4 v 4 v 4 v v v v cc cc cc = = = = 2 2 2 2 .8 .8 .8 5 5 5 5 vC vC vC vC 3.45 v cc cc ntest_in input high voltage, v ih 2. 4 v 4 v 4 v 4 v v v v v cc cc cc cc = = = = 4 4 4 .2 .2 .2 5 vC 5. 75 v cc cc cc cc cc cc input high voltage, v ih 2. 2. 2. 2. 0 v 0 v 0 v 0 v v v v v cc cc cc cc = = = = 2 2 2 .8 5 vC 3. 45 v cc cc cc cc cc cc cc cc digital input current input high current, i ih C1 a v a v a v a v in = v in in cc input high current, a0, a1, i ih C2 C2 C2 00 00 00 00 75 a v a v a v a v in = v in in cc (note 6) input low current, i il 1 1 1 a v a v a v a v in = 0 in in input capacitance, c in 20 pf pf pf pf serial bus tim ing 7 clock frequency, f sclk clock frequency, f clock frequency, f 40 40 40 0 k 0 k 0 k 0 k hz see figure 1 glitch immunity, t sw 50 50 50 50 ns see figure 1 bus free time, t buf 1. 1. 1. 3 3 3 s see figure 1 start setup time, t su; sta sta sta sta 60 60 60 0 n 0 n 0 n 0 n s see figure 1 start hold tim e, t hd;sta 60 0 n 0 n 0 n 0 n s see figure 1 scl low time , t low 1. 3 3 3 3 s see f ig ure 1 scl hi gh time, t high 0. 0. 0. 0. 6 6 6 6 s see f ig ure 1 scl, sda rise time, t r 300 ns see figure 1 scl, sda fall time, t f scl, sda fall time, t scl, sda fall time, t 300 s see figure 1 data setup time, t su; dat 10 10 10 10 0 n 0 n 0 n s see figure 1 data hold time , t hd;dat 900 ns see figure 1 notes all voltages are measured with respect to gnd, unle ss otherwise noted. typicals are at t a = + 25 c and represent most likely parametric norm. shutdo wn current typ is measured with v cc = 3.3 v. tue (total unadjusted error) includes offset, gain and linearity errors of the adc, multiplexer and on -chip input attenuators, including an external series input protection resistor value between zero and 1 k . total monitoring cycle time is the time taken to me asure all six analog inputs plus the temperature se nsor. the total fan count is based on 2 pulses per revolu tion of the fan tachometer output . a0 and a1 ha ve int ern al 75 k pull-down. timing specifications are tested at logic levels of v il = 0.3 v cc for a falling edge and v cc cc ih = 0.7 v cc for a rising edge. specifications subject to change without notice. adm9240 rev. 2 | page 3 of 22 | www.onsemi.com
adm9240 C4C rev. 0 absolute maximum ratings* positive supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . 6.5 v voltage on any input or output pin . . C0.3 v to (v cc + 0.3 v) (except analog inputs) 16 v v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +16 v all other analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . +7.5 v ground difference (gnddCgnda) . . . . . . . . . . . . 300 mv input current at any pin . . . . . . . . . . . . . . . . . . . . . . . 5 ma package input current . . . . . . . . . . . . . . . . . . . . . . . . 20 ma maximum junction temperature (t j max) . . . . . . . . . . 150 c storage temperature range . . . . . . . . . . . . . C65 c to +150 c lead temperature, soldering vapor phase 60 (sec) . . . . . . . . . . . . . . . . . . . . . . . . +215 c infrared 15 (sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +200 c esd rating all pins except pin 15 . . . . . . . . . . . . . . . . 2000 v esd rating pin 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 v *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. expos ure to absolute maximum rating conditions for extended periods may affect device r eliability. thermal characteristics 24-lead small outline package: ja = 50 c/watt, jc = 10 c/watt ordering guide temperature package package model range description option adm9240aru C40 c to +125 c 24-lead tssop ru-24 sda protocol scl start condition (s) bit 7 msb (a7) bit 6 (a6) t su;sta t low t high 1/f scl protocol scl sda bit 0 lsb (r/w) acknowledge (a) stop condition (p) t vd;dat t su;sto t hd;sta t su;dat t hd;dat t r t f t buf figure 1. diagram for serial bus timing pin configuration top view (not to scale) 24 23 22 21 20 19 18 17 16 15 14 13 12 3 4 5 6 7 8 9 10 11 12 adm9240 reset ntest_in/aout int v cc gndd ntest_out/a0 a1 sda scl ci fan2 fan1 gnda +v ccp2 +12v in +5v in +3.3v in vid0 vid1 vid2 vid3 +2.5v in +v ccp1 vid4 rev. 2 | page 4 of 22 | www.onsemi.com absolute m axim um ratings* positive supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . 6.5 v voltage on any input or output pin . . C0.3 v to (v cc + 0.3 v) (except analog inputs) 16 v v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +16 v all other anal og i np uts . . . . . . . . . . . . . . . . . . . . . . . . . +7.5 v ground difference (gnddCgnda) . . . . . . . . . . . . 300 mv input current at any pin . . . . . . . . . . . . . . . . . . . . . . . 5 ma package input current . . . . . . . . . . . . . . . . . . . . . . . . 20 m a maximum junction temperature (t j maximum junction temperature ( t maximum junction temperature ( t max) . . . . . . . . . . 150 c storage temperature range . . . . . . . . . . . . . C65 c to +150 c lead temperature, soldering vapor phase 60 (sec) . . . . . . . . . . . . . . . . . . . . . . . . +215 c infrared 15 (sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +200 c esd rating all pins except pin 15 . . . . . . . . . . . . . . . . 2 000 v esd rating pin 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 v *stresses above those listed under absolute m aximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. expos ure to absolute maximum rating conditions for extended periods may affect device r eliability. th er ma l ch ar ac te ri st ic s 24-lead small outline package: ja = 5 0 c/watt, jc = 10 c/watt sda prot ocol scl start conditio n (s) bit 7 msb (a7) bit 6 (a6) t su;sta t low t high 1/f scl protocol scl sda bit 0 lsb (r/w ) acknowle dge dge dge dge dge dge dge (a) (a) (a) (a) (a) stop stop stop stop stop stop stop cond cond cond cond cond cond cond itio itio itio itio itio n (p) (p) (p) (p) (p) (p) (p) t vd;d vd;d vd;d vd;d vd;d vd;d vd;d at at at at at t su;s to to to to to to t hd;sta t t su;d su;d su;d su;d su;d su;d at at at at at at t hd;d hd;d hd;d hd;d hd;d hd;d hd;d at t r t f t buf figure 1. diagram for serial bus ti mi mi mi mi ng ng ng ng pi pi pi n configur at at at at at io io io io n n n top view (not to scale) 24 23 23 22 21 20 19 18 17 16 15 14 13 1 2 2 2 2 2 3 3 3 3 3 3 3 4 5 5 5 5 5 5 6 6 6 6 6 6 6 7 8 9 10 11 12 adm adm adm adm 9240 reset ntes ntes ntes ntes ntes ntes t_in/aout int v cc gndd gndd gndd gndd gndd gndd gndd ntes t_ou t_ou t_ou t_ou t_ou t_ou t/a0 t/a0 a1 a1 a1 a1 a1 sda sda sda sda sda sda sda scl scl scl scl scl scl scl ci ci ci ci ci ci ci fan2 fan2 fan2 fan2 fan2 fan2 fan2 fan1 fan1 fan1 fan1 fan1 fan1 gnda +v ccp2 +12v in +5v in +3.3v in vid0 vid1 vid2 vid3 +2.5v in +v ccp1 vid4 adm9240 rev. 2 | page 4 of 22 | www.onsemi.com
adm9240 C5C rev. 0 pin function descriptions pin number mnemonic description 1 ntest_out/a0 digital i/o. dual function pin. the lo west order programmable bit of the serial bus addre ss. this pin functions as an output when doing a nand t ree test. 2 a1 digital input. the highest order programmable bi t of the serial bus address. 3 sda digital i/o. serial bus bidirectional data. ope n-drain output. 4 scl digital input. serial bus clock. 5 fan1 digital input. 0 to v cc amplitude fan tachometer input. 6 fan2 digital input. 0 to v cc amplitude fan tachometer input. 7 ci digital i/o. an active high input from an extern al circuit that latches a chassis intrusion event. this line can go high without any clamping a ction regardless of the powered state of the adm9240. the adm9240 provides an internal open drain on this line, controlled by bit 6 of register 40h or bit 7 of register 46h, to p rovide a minimum 20 ms pulse on this line, to reset the external chassis intrusion latch. 8 gndd digital ground. internally connected to all of the digital circuitry. 9 v cc power (+2.85 v to +5.75 v). typically powered from +3.3 v or +5 v power rail. bypass with the parallel combination of 10 f (electrolytic or tantalum) and 0.1 f (ceramic) bypass capacitors. 10 int digital output. interrupt request (open drain). the output is enabled when bit 1 of the configuration register is set to 1. the default sta te is disabled. 11 ntest_in/aout digital input/analog output. an acti ve-high input that enables nand tree mode board- level connectivity testing. refer to section on nan d tree testing. also functions as a pro- grammable analog output when nand tree is not selec ted 12 reset digital i/o. master reset, 5 ma driver (open drain) , active low output with a 20 ms minimum pulsewidth. available when enabled via bit 7 in reg ister 44h, and set using bit 4 in register 40h. also acts as reset input when pulled low (e.g. , power-on reset). 13 gnda analog ground. internally connected to all an alog circuitry. the ground reference for all analog inputs. 14 +v ccp2 analog input. monitors processor core voltage +v ccp2 (0 vC3.6 v). can also be used to monitor the C12 v supply by adding two external res istors. 15 +12 v in analog input. monitors +12 v supply. 16 +5 v in analog input. monitors +5 v supply. 17 +3.3 v in analog input. monitors +3.3 v supply. 18 +2.5 v in analog input. monitors +2.5 v supply. 19 +v ccp1 analog input. monitors processor core voltage +v ccp1 (0 vC3.6 v). 20 vid4 digital input. core voltage id readouts from the processor. this value is read into the vid4 status register. 21 vid3 digital input. core voltage id readouts from the processor. this value is read into the vid0Cvid3 status register. 22 vid2 digital input. core voltage id readouts from the processor. this value is read into the vid0Cvid3 status register. 23 vid1 digital input. core voltage id readouts from the processor. this value is read into the vid0Cvid3 status register. 24 vid0 digital input. core voltage id readouts from the processor. this value is read into the vid0Cvid3 status register. rev. 2 | page 5 of 22 | www.onsemi.com adm9240 pin function descriptions pin number mnemonic description 1 ntest_out/a0 digital i/o. dual function pin. the lowest order programmable bit of the serial bus ad dress. the lowest order programmable bit of the serial bus ad the lowest order programmable bit of the serial bus ad this pin functions as an output when doing a nand t ree test. 2 a1 digital input. the highest order programmable bi t of the serial bus address. 3 sda digital i/o. serial bus bidirectional data. ope n-drain output. 4 scl digital input. serial bus clock. 5 fan1 digital input. 0 to v cc amplitude fan tachometer inpu t. cc cc 6 fan2 digital input. 0 to v cc amplitude fan tachometer inpu t. cc cc 7 ci digital i/o. an active high input from an e xt xt xt er er er na na na l circuit that latches a chassis intrusion event. this line can go high without any c c c la la la mp mp mp in in in g g g ac ac ac ac tion regardless of the powered state o f the adm9240. the adm 9240 provi de de de s s s an an an i i i nt nt nt er er er na na na l op op op op en en en drain on this line, controlled by bit 6 of register 40h or bit 7 of r eg eg eg is is is te te te r r r 46 46 h, h, h, t t o o o pr pr pr ov ov ov id id id e e e a minimum 20 ms pulse on this line, to reset the external chassis intr us us us io io io n n n la la la tc h. 8 gndd digital ground. internally co nn nn nn ec ec ec te te te d to to to a a a ll ll ll o o o f the di di di gital circuitry. 9 v cc power (+2.85 v to +5.75 v) v) v) . ty ty ty pi pi pi ca ca ca lly po we we we re re re d from +3.3 v or or or or + + + + + 5 5 5 5 v v v v power rail. bypass with the parallel combinati on on o o o f 10 10 10 f f f (e (e (e le le le ct ct ct rolytic or tantalu m) m) m) m) a a a a nd nd nd nd 0 0 0 0 .1 f (ceramic) bypass capacitors . 10 int digital output. in in in te te te rr rr rr up up up t requ es es es t (o (o (o pe pe pe n drai n) n) n) . . . th th th e e e ou ou ou tp tp tp tp ut ut ut ut i i i i s en en en en ab ab ab ab led when bit 1 of the configuration re gi gi gi st st st er i i i s s s set to to to 1 1 1 . th th th e defa ul ul ul t t t t st st st at at at e is is is is d d d d is is is is ab ab ab le le le d. d. d. d. 11 ntest_in/aout digital i np np np np ut ut ut ut /a /a /a /a na na na na lo lo lo lo g g g g ou ou ou tp tp tp ut ut ut . an an an active- hi hi hi hi hi gh gh gh gh i i i i np np np np ut ut ut ut t t t t ha ha ha ha t t t t en en en en ab ab ab ab le le le le s nand tree mode board- level co nn nn nn nn ec ec ec ec ti ti ti ti vity t t t es es es es ti ti ti ng ng ng ng . re re re fe fe fe r to sec ti ti ti ti on on on on o o o o n na na na na nd nd nd nd t t t t re re re re e e e e te te te sting. also functions as a pro- gramma bl bl bl bl e e e e an an an an alog o ut ut ut ut pu pu pu pu t when n an an an an d d d d tr tr tr tr ee ee ee ee i i i i s s s no no no t se se se se le le le le ct ct ct ed 12 reset di di di gi gi gi gi ta ta ta l l i/ i/ i/ i/ o. o. o. o. m m m m as as as as te te te te r r r re re re re set, 5 ma dr dr dr dr iv iv iv iv er er er ( ( ( ( op op op op en en en en d d d ra ra ra ra in in in in ), ), ), ), active low output with a 20 ms minimum pu pu pu pu pu ls ls ls ls ew ew ew ew id id id id th th th th . av av av av ai ai ai la la la la bl bl bl bl e when e e na na na na bl bl bl bl bl ed ed ed ed v v v ia ia ia ia b b b b it it it it 7 i i i i n n n n re re re gister 44h, and set using bit 4 in register 40 40 40 40 h. h. h. h. a a a a ls ls ls ls o o o ac ac ac ac ts a a a s reset in pu pu pu t t t wh wh wh wh en en en en p p p p ul ul ul ul le le le le d d d d lo lo lo lo w w w (e (e (e (e .g., power-on reset). 13 gnda an an an an al og og og og g g g g ro ro ro ro un un un un d. inter na na na ll ll ll ll y y y co co co co nn nn nn ec ec ec te te te te d d d d to to to to a a a a ll ll ll ll a a a nalog circuitry. the ground reference for all an an an al al og og og og i i i i np ut ut ut ut s. 14 +v ccp2 an an an al al al al og og og og input. mo mo mo mo ni ni ni ni to to to to rs rs rs p p p ro ro ro ro ce ce ce ce ss or or or or c c c or or or e e e voltage +v ccp2 (0 vC3.6 v). can also be used to mo mo mo ni ni ni ni tor the C1 C1 C1 C1 2 2 2 2 v v v v su su su pp pp pp pp ly ly ly ly b b b b y ad ad ad ad di di di ng ng ng ng two external resistors. 15 +12 v in in in an an an alog i np np np ut ut ut . . . mo mo mo mo ni ni ni to to to to rs rs rs rs + + + + 12 12 12 12 v v v v s s s upply. 16 +5 v in analog i np np np ut ut ut . mo mo mo mo ni ni ni to to to rs rs rs + + + + 5 5 5 5 v v v v supply. 17 +3.3 v in analog inp ut ut ut ut . . . . mo mo mo mo ni ni ni ni ni to to to to rs rs rs + + + + 3. 3. 3. 3 v supply. 18 +2.5 v in analog i i i np np np np ut ut ut . . . mo mo mo mo ni ni ni ni to to to to rs rs rs +2.5 v supply. 19 +v ccp1 anal og og og og i i i i np np np np ut ut ut . . . . mo mo mo mo ni ni ni tors processor core voltage +v ccp1 ( 0 vC3.6 v) . 20 vid4 di di di gi gi gi gi ta ta ta ta l l l in in in in pu pu pu pu pu t. t. t. c c c c ore voltage id readouts from the processor. this va lue is read into the vi vi vi d4 d4 d4 d4 s s ta ta ta tu tu tu tu s s s s re re re re gister . 21 vid3 di di di gital input. core voltage id readouts from the proc essor. this value is read into the vid0Cvid3 status register. 22 vid2 digital input. core voltage id readouts from the processor. this value is read into the vid0Cvid3 status register. 23 vid1 digital input. core voltage id readouts from the processor. this value is read into the vid0Cvid3 status register. 24 vid0 digital input. core voltage id readouts from the processor. this value is read into the vid0Cvid3 status register. rev. 2 | page 5 of 22 | www.onsemi.com
adm9240 C6C rev. 0 general description the adm9240 is a complete system hardware monitor f or microprocessor-based systems. the device communicat es with the system via a serial system management bus. the serial bus controller has two hardwired address lines for devi ce selection (pin 1 and pin 2), a serial data line for reading a nd writing addresses and data (pin 3), and an input line for t he serial clock (pin 4). all control and programming functions of the adm924 0 are performed over the serial bus. an on-chip analog-to-digital converter with six mul tiplexed analog inputs measures power supply voltages (+12 v , +5 v, +3.3 v, +2.5 vpins 15 to 18) and processor core vo ltages (+v ccp1 and +v ccp2 pins 19 and 14). the adc also accepts input from an on-chip bandgap temperature sensor th at moni- tors system ambient temperature. two count inputs (pins 5 and 6) are provided for mo nitoring the speed of fans with tachometer outputs. to accom modate fans with different speeds and different tacho outp uts, a divisor of 1, 2, 4 or 8 can be programmed into the counter. five digital inputs (vid4 to vid0pins 20 to 24) re ad the processor voltage id code, while a chassis intrusio n input (pin 7) is provided to detect unauthorized tampering with the equipment. when the adm9240 monitoring sequence is started, it cycles sequentially through the measurement of analog inpu ts and the temperature sensor, while at the same time the fan speed inputs are independently monitored. measured values from t hese in- puts are stored in value registers. these can be re ad out over the serial bus, or can be compared with programmed limi ts stored in the limit registers. the results of out-of-limit comparisons are stored in the interrupt status registers and will g enerate an inter- rupt on the int line (pin 10). any or all of the interrupt status bits can be mask ed by appro- priate programming of the interrupt mask register. a reset input/output (pin 12) is provided. pulling this pi n low will reset all adm9240 internal registers to de fault values. the adm9240 can also be programmed to give a low-go ing 20 ms reset pulse at this pin. the adm9240 contains an on-chip, 8-bit digital-to-a nalog converter with an output range of zero to 1.25 v (p in 11). this is typically used to implement a temperature-contro lled fan by controlling the speed of a fan dependent upon the t emperature measured by the on-chip temperature sensor. testing of board level connectivity is simplified b y providing a nand tree test function. the aout (pin 11) also dou bles as a nand test input, while pin 1 doubles as a nand tr ee output. internal registers of the adm9240 a brief description of the adm9240s principal inte rnal regis- ters is given below. more detailed information on t he function of each register is given in tables v to xvii. configuration register: provides control and configuration. serial address register: stores the serial bus address of the adm9240. address pointer register: contains the address that selects one of the other internal registers. when writing t o the adm9240, the first byte of data is always a register address , which is written to the address pointer register. interrupt (int) status registers: two registers to provide status of each interrupt event. interrupt (int) mask registers: allow masking of indi- vidual interrupt sources. temperature configuration register: the configuration of the temperature interrupt is controlled by the lowe r three bits of this register. vid/fan divisor registers: the status of the vid0 to vid4 pins of the processor can be written to and read fr om these registers. divisor values for fan-speed measurement are also stored in one of these registers. value and limit registers: the results of analog voltage inputs, temperature and fan speed measurements are stored in these registers, along with their limit values. analog output register: the code controlling the analog output dac is stored in this register. chassis intrusion clear register: a signal latched on the chassis intrusion pin can be cleared by writing to this register. rev. 2 | page 6 of 22 | www.onsemi.com general description the adm9240 is a complete system hardware monitor f or microprocessor-based systems. the device communicat es with the system via a serial system m anagement bus. the serial bus co nt ro ll er h as t wo h ar dw ir ed a dd re ss l in es f or d ev ic e se le ct io n (pin 1 and pin 2), a serial data line for readin g and writin g addresses and data (pin 3), and an i np ut line for the serial clock (pin 4). all control and programming functions of the adm9 24 0 are performed over the serial bus. an on-ch ip analo g- to-d ig ital converter with six mult ip lexed anal og i np uts measures p ower s up pl y volt ag es (+12 v, +5 v, +3.3 v, +2.5 vpins 15 to 18) and processor core vo ltage s (+v ccp1 and +v ccp2 pins 19 and 14). the adc also accep ts input from an on-chip bandgap temperature sensor th at moni- tors system ambient temperature. two count inputs (pins 5 and 6) are provided for mo nitoring the speed of fans with tachometer outputs. to accom modate fans with different speeds and different tacho outp uts, a divisor of 1, 2, 4 or 8 can be programmed into the counter. five digital inputs (vid4 to vid0 pins 20 to 24) read the processor voltage id code, while a chassis intrusio n inp ut ut ut (pin 7) is provided to detect unauthorized tampering wi wi wi th th th th th t t t t he he he he equipment. when the adm 9240 monitoring sequence is starte d, d, d, d, i t t t t cycles sequentially through the measurement of anal og og og og i i i i np np np np ut ut ut ut ut s s an an an an d th th th e e e e temperature sensor, while at the same time t t t t he he he he f f f an an an an s s s s pe pe pe ed ed ed ed i i i np np np np ut ut ut ut s s s are independently monitored. m easured va lu lu lu lu es es es es f f f f ro ro ro m m m m th th th th es es es es e in- puts are stored in value registers. th es es es es e e e ca ca ca ca n n n n be be be be r r r ea ea ea ea d d ou ou ou ou t ov ov ov ov er the serial bus, or can be compared wit h h h pr pr pr pr og og og og ra ra ra ra mm mm mm mm ed ed ed ed l l l l im it it it it s s s s stored in the limit registers. the results of of of o o o ut ut ut -o -o -o -o f- f- f- li li li li mi mi mi t co co co co mparisons ar ar ar e e e stored in the interrupt status r r r r eg eg eg eg is is is is te te te te rs rs rs a a a nd nd nd w il il il l l l l ge ge ge ge nerate an in in in in te te te te r- r- r- rupt on the int line (pin 1 1 1 1 0) 0) 0) 0) . . . t any or all of the interrup t t t st st st st atus b it it it it s s s s ca ca ca ca n be be be maske d d d by by by a a a pp pp pp ro ro ro - - - priate programming of th e e e in in in in te te te te rr rr rr up up up t t t ma ma ma ma sk registe r. r. a reset input/output (pin 1 1 1 1 2) 2) 2) 2) i i i i s s s s pr pr pr ovided. pulling th th th th is is is is p p p p in in in in t low will reset all adm 9240 internal registers to d ef ef ef au au au lt lt lt v v v al al al ue ue ue ue s. s. s. the adm9240 can also be programmed to give a a a a l l l l ow ow ow ow -g -g -g -g oi oi oi oi ng ng ng ng 20 ms reset pulse at this pin. the adm9240 contains an on-chip, 8-b it it it it d d d d ig ig ig ig it it it it al al al -t o- o- o- an an an an al al al al og converter with an output range of zero t o o o 1. 1. 1. 25 25 25 v (pin 11). this is typically used to implement a temperature-contro lled fan by controlling the speed of a fan dependent upon the t emperature measured by the on-chip temperature sensor. testing of board level connectivity is simplified b y providing a nand tree test function. the aout (pin 11) also dou bles as a nand test input, w hile pin 1 doubles as a nand tree output. internal registers of the adm9240 a brief description of the adm 9240s principal internal regis- ters is given below. m ore detailed information on the function of each register is given in tables v to xvi i. configuration register : provides control and configuration. serial address register: st or es t he s er ia l bu s ad dr es s of t he adm9240. address pointer register: contains the address that selects one of the other internal registers. w hen writing to the adm 9240, the first byte of data i i i s always a register address, which is writte n to the address p oi oi oi nt nt nt er er er register. interrupt (i nt nt nt ) st st st at at at us us us r r r r egisters: two registers to provide status of ea ea ea ch ch ch i i i nt nt nt er er ru ru ru pt pt pt e ve ve ve nt nt nt . . interr up up up t (i (i (i nt nt nt ) ma ma ma sk sk sk r r r eg eg eg isters : allow maskin g of indi- vi du du al al al i i i nt nt nt er er er ru ru ru pt pt pt s s s ourc es es es . te te te mp mp mp er er er at at at ure co co co nf nf nf iguration regi st st st st er er er er : : : : th th th th e configuration of th th th e e e te te te mp mp mp er er er ature in in in terrupt is control le le le d d d d by by by by the lower three bits of th th th is is is r eg eg eg is is te te te r. r. r. vi d/ d/ d/ fa fa fa n di di di visor re re re gi gi gi st st st er er s: s: s: th th th th th e e e e st st st st at at at at us us us us of the vid0 to vid4 pi ns ns ns o o o f f f th th th e proces so so so so r r r ca ca ca n n n be be be be w w w w ri ri ri ri tt tt tt en en en en t t t t o o o o an an an an d read from these re re re gi gi gi st st st er er er s. divis or or or or v v v al al al ue ue ue s s s s fo fo fo fo r r r r fa fa fa fa n- n- n- n- sp sp sp sp ee ee ee d d d d measurement are al so st st st or or or ed in one of of of of t t t t he he he he se se se r r r eg eg eg eg is is is is te te te rs rs rs rs . . . . value an an an d d d d li li li li mi mi mi mi t t t t re re re re gi gi gi gi st st st er er er er s: s: s: s: th th e results of analog voltage inputs , , , , te te te te mp mp mp mp er er er at at at at ur ur ur ur e e e an an an an d d d d fa fa fa fa n n n speed measurements are stored in th es es es es e e e e re re re re re gi gi gi gi st st st er er er er s, s, s, s, a a a a lo ng ng ng ng w w w it it it h their limit values. an an an an al al al al og og og og o o o o ut ut ut ut pu pu pu pu t t t t re re re re gi gi gi gi ster: the code controlling the analog ou ou ou ou tp tp tp ut ut ut d d d d ac ac ac ac i i i i s s s s st st st st or or or ed in this register. ch ch ch ch as as as as si si si s s s s in in in in tr tr tr tr usion clear register : a signal latched on the ch ch ch ch as as as si si si s s s s in in in in tr tr tr us us us ion pin can be cleared by writing to this register. adm9240 rev. 2 | page 6 of 22 | www.onsemi.com
adm9240 C7C rev. 0 serial bus interface control of the adm9240 is carried out via the seria l bus. the adm9240 is connected to this bus as a slave device, under the control of a master device, e.g., the piix4. the adm9240 has a 7-bit serial bus address. when th e device is powered up, it will do so with a default serial bus address. the five msbs of the address are set to 01011, the two lsbs are determined by the logical states of pin 1(ntest _out/a0) and pin 2 (a1) at power-up. these pins have interna l 75 k pull-down resistors, so if they are left open-circu it the default address will be 0101100. the facility to make hardwired changes to a1 and a0 allows the user to avoid conflicts with other devices sharing the same serial bus, for example if more than one adm9240 is used i n a sys- tem. once the adm9240 has been powered up, the five msbs of the serial bus address may be changed by writing a 7-bit word to the serial address pointer register (the hardwir ed values of a0 and a1 cannot be overwritten). thereafter, the n ew serial bus address must be used to select the adm9240, unt il it is changed again, or the device is powered off. the serial bus protocol operates as follows: 1. the master initiates data transfer by establishin g a start condition, defined as a high-to-low transition on t he serial data line sda while the serial clock line scl remai ns high. this indicates that an address/data stream will fol low. all slave peripherals connected to the serial bus respo nd to the start condition, and shift in the next eight bits, consisting of a 7-bit address (msb first) plus an r/ w bit, which deter- mines the direction of the data transfer, i.e., whe ther data will be written to or read from the slave device. the peripheral whose address corresponds to the tra nsmitted address responds by pulling the data line low durin g the low period before the ninth clock pulse, known as the a cknowl- edge bit. all other devices on the bus now remain i dle while the selected device waits for data to be read from or written to it. if the r/ w bit is a 0, the master will write to the slave device. if the r/ w bit is a 1, the master will read from the slave device. 2. data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an acknowled ge bit from the slave device. transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low-to-high tra nsition when the clock is high may be interpreted as a stop signal. the number of data bytes that can be transmitted ov er the serial bus in a single read or write operation is l imited only by what the master and slave devices can handl e. 3. when all data bytes have been read or written, st op condi- tions are established. in write mode, the master wi ll pull the data line high during the tenth clock pulse to assert a stop condition. in read mode, the master device wil l override the acknowledge bit by pulling the data li ne high during the low period before the ninth clock pulse. this is known as no acknowledge. the master will then take the data line low during the low period before the tent h clock pulse, then high during the tenth clock pulse to as sert a stop condition. any number of bytes of data may be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation, because the type of operation is determined at the beginning and cannot subsequently be changed wi thout starting a new operation. in the case of the adm9240, write operations contai n either one or two bytes, and read operations contain one b yte and perform the following functions: to write data to one of the device data registers o r read data from it, the address pointer register must be set s o that the correct data register is addressed, then data can b e written into that register or read from it. the first byte of a write operation always contains an address that is stored in the ad dress pointer register. if data is to be written to the device, t hen the write operation contains a second data byte that is writt en to the register selected by the address pointer register. this is illustrated in figure 2a. the device addres s is sent over the bus followed by r/ w set to 0. this is followed by two data bytes. the first data byte is the address of the in ternal data register to be written to, which is stored in the a ddress pointer register. the second data byte is the data to be wr itten to the internal data register. figure 2a. writing a register address to the address pointer register, then writing data to the selecte d register adm9240 C7C rev. 0 serial bus interface control of the adm9240 is carried out via the seria l bus. the adm9240 is connected to this bus as a slave device, under the control of a master device, e.g., the piix4. the adm9240 has a 7-bit serial bus address. when th e device is powered up, it will do so with a default serial bus address. the five msbs of the address are set to 01011, the two lsbs are determined by the logical states of pin 1(ntest _out/a0) and pin 2 (a1) at power-up. these pins have interna l 75 k pull-down resistors, so if they are left open-circu it the default address will be 0101100. the facility to make hardwired changes to a1 and a0 allows the user to avoid conflicts with other devices sharing the same serial bus, for example if more than one adm9240 is used i n a sys- tem. once the adm9240 has been powered up, the five msbs of the serial bus address may be changed by writing a 7-bit word to the serial address pointer register (the hardwir ed values of a0 and a1 cannot be overwritten). thereafter, the n ew serial bus address must be used to select the adm9240, unt il it is changed again, or the device is powered off. the serial bus protocol operates as follows: 1. the master initiates data transfer by establishin g a start condition, defined as a high-to-low transition on t he serial data line sda while the serial clock line scl remai ns high. this indicates that an address/data stream will fol low. all slave peripherals connected to the serial bus respo nd to the start condition, and shift in the next eight bits, consisting of a 7-bit address (msb first) plus an r/ bit, whic h deter- mines the direction of the data transfer, i.e., whe ther data will be written to or read from the slave device. the peripheral whose address corresponds to the tra nsmitted address responds by pulling the data line low durin g the low period before the ninth clock pulse, known as the a cknowl- edge bit. all other devices on the bus now remain i dle while the selected device waits for data to be read from or written to it. if the r/ bit is a 0, the master will write to the slave device. if the r/ bit is a 1, the master will read from the slave device. 2. data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an acknowled ge bit from the slave device. transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low-to-high tra nsition when the clock is high may be interpreted as a stop signal. the number of data bytes that can be transmitted ov er the serial bus in a single read or write operation is l imited only by what the master and slave devices can handl e. 3. when all data bytes have been read or written, st op condi- tions are established. in write mode, the master wi ll pull the data line high during the tenth clock pulse to assert a stop condition. in read mode, the master device wil l override the acknowledge bit by pulling the data li ne high during the low period before the ninth clock pulse. this is known as no acknowledge. the master will then take the data line low during the low period before the tent h clock pulse, then high during the tenth clock pulse to as sert a stop condition. any number of bytes of data may be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation, because the type of operation is determined at the beginning and cannot subsequently be changed wi thout starting a new operation. in the case of the adm9240, write operations contai n either one or two bytes, and read operations contain one b yte and perform the following functions: to write data to one of the device data registers o r read data from it, the address pointer register must be set s o that the correct data register is addressed, then data can b e written into that register or read from it. the first byte of a write operation always contains an address that is stored in the ad dress pointer register. if data is to be written to the device, t hen the write operation contains a second data byte that is writt en to the register selected by the address pointer register. this is illustrated in figure 2a. the device addres s is sent over the bus followed by r/ set to 0. this is followed b y two data bytes. the first data byte is the address of the in ternal data register to be written to, which is stored in the a ddress pointer register. the second data byte is the data to be wr itten to the internal data register. r/ w 0 scl sda 1 0 1 1 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 ack. by adm9240 start by master frame 1 serial bus address byte frame 2 address pointer register byte 1 9 1 ack. by adm9240 9 d7 d6 d5 d4 d3 d2 d1 d0 ack. by adm9240 stop by master frame 3 data byte 1 9 scl (continued) sda (continued) figure 2a. writing a register address to the address pointer register, then writing data to the selecte d register rev. 2 | page 7 of 22 | www.onsemi.com adm9240 serial bus interface control of the adm 9240 is carried out via the serial bus. the adm9240 is connected to this bus as a slave device, under the control of a master device, e.g., the piix4. the adm9240 has a 7-bit serial bus address. when th e device is powered up, it will do so with a default serial bus address. the five m sbs of the address are set to 01011, the two lsbs are determined by the logical states of pin 1(ntest _out/a0) and pin 2 (a1) at power-up. these pins have interna l 75 k and pin 2 (a1) at power-up. these pins have interna l 75 k and pin 2 (a1) at power-up. these pins have interna l 75 k pull-down resistors, so if they are left open-circu it the default ad dr ess wi ll b e 01 01 10 0. the facility to make hardwired changes to a1 and a0 allows t he user to avoid conflicts with other devices sharing the same serial bus, for example if more than one adm9240 is used i n a sys- tem. once the adm9240 has been powered up, the five msbs of the serial bus address may be changed by writing a 7-bit word to the serial address pointer register (the hardwir ed values of a0 and a1 cannot be overwritten). thereafter, the n ew serial bus address must be used to select the adm 9240, until it is changed again, or the device is powered off. the serial bus protocol operates as follows: 1. the master initiates data transfer by establishi ng ng ng ng a a a a s s s ta ta ta ta ta rt rt rt condition, defined as a high-to-low transition o o o o n th th th th e se se se se ri ri ri al al al al data line sda while the serial clock line scl re re re ma ma ma ma ins hi hi hi hi gh gh gh gh . this indicates that an address/data stre am am am am w w w w il il il l fo fo fo fo fo ll ll ll ll ow ow ow . al al al al l l l l slave peripherals connected to the ser ia ia ia ia l bu bu bu s s s s re re re re sp sp sp on on on on d d to t t t t he he he start condition, and shift in the ne ne ne ne xt xt xt e e e e ig ig ig ig ht ht ht ht b b b b it it it s, s, s, s, c c c c onsisting of a 7-bit address (msb first) p p p lu lu lu lu s s s an an an an r r r r / / / w w w w of a 7-bit address (msb first) plus an r / / / of a 7-bit address (msb first) plus an r / / / b b b it, wh wh wh wh ic ic ic ic h dete r- mines the direction of the d at at at a a a tr tr tr an an an an sf sf sf er er er er , , , , i. e. e. e. e. , wh wh wh wh et et et et he he he r data will be written to or read f ro ro ro m m m th th th e e e sl sl sl av av av av e e e de de de de vice. the peripheral who se se a a a a dd dd dd dd re re re re ss ss ss ss c c c or or or re re re sp sp sp on on on ds ds ds ds to the tr an an an sm sm sm sm it it it te te te te d d d d address responds b y y y y pu pu pu pu ll ll ll ll in in in in g g g th th th e e e e da da da ta ta ta l in in in e low du ri ri ri ng ng ng ng ng t t t t he he he l ow ow ow ow period before the ni ni ni nt h h h h clock pu pu pu pu ls ls ls ls e, k k k nown as th th th th e e e ac ac ac kn kn kn ow ow ow l- l- l- edge bit. all other de de de de vi vi vi ce ce ce ce s s on t t t t he he he he b b b b us now rem ai ai ai n n n id id id id le le le le w w w hi hi hi le le le le the selected device wa it it it it s s s for da da da da ta ta ta to be read fr om om om o o o o r r r wr wr wr wr it it it it te te te te n n n n to it. if the r/ w to it. if the r/ to it. if the r/ bit is a 0, the master will wri te te te t t t t o o o th th th th e e sl sl sl av av av av e e e e device. if the r/ w device. if the r / device. if the r / bit is a 1, the master wi ll ll ll ll r r r r ea ea ea ea d d d d fr fr fr om om om om t t t t he he he he slave device. 2. data is sent over the serial bus in se se se qu qu qu qu en en en en ce ce ce s s s of of of of n n n n ine clock pulses, eight bits of data followed by by by by a a a n n n acknowledge bit from the slave device. transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low-to-high tra nsiti on when the clock is high may be interpreted as a stop signal. the number of data bytes that can be transmitted ov er the serial bus in a single read or w rite operation is limited only by what the master and slave devices can handl e. 3. when all data bytes have been read or written, st op condi- tions are established. in write mode, the master wi ll pull the data line high during the tenth clock pulse to assert a stop condi ti ti ti on on on . in read mode, the master device will override t he he he a a a ck ck ck nowledge bit by pulling the data line high during t t t he he he l l l ow ow ow p p p er er er io io io io d before the ninth clock pulse. this is kn ow ow ow n n n as as as n n n o o o ac ac ac kn kn kn ow ow ow le le le le dg dg dg e. the master will then take the da da da ta ta ta l in in in e lo w w w du du du ri ri ri ng ng ng t t t he he he low period before the tenth clock pu pu pu ls ls ls ls e, e, e, t t t he he he n hi gh gh gh d d d ur ur ur ing the tenth clock pulse to assert a st st st op op op c c c on on on di di di tion. an an an y y y nu nu nu nu mber o o o f f f by by by tes of data ma y y y be be be be be t t t t ra ra ra ra nsferred over the serial bu bu bu bu s s s in in in o ne ne ne o o o peration, but it is no no no no t t t po po po ssible to mix read and write in in in o o o ne ne ne o o o pe pe pe ration, because th th th e e e ty ty ty ty pe pe pe pe of operation is determined at th th th e e e be be be gi gi gi nning an d d d d ca ca ca nn nn nn ot ot ot s s s ub ub ub ub se qu qu qu qu qu en en en en tl tl tl tl y be changed witho ut st st st ar ar ar ti ti ti ng a n ew ew ew o o o pe pe pe ra ra ra ti ti ti on on on on . . . in in in the cas e e e e of of of of of t t t t he he he he a a a a dm dm dm dm 92 92 92 40 40 40 40 , , , wr wr wr wr ite operations contain either one or t t t wo wo wo wo wo b b b b yt yt yt yt es es es , , , , an an an an d d d re re re ad ad ad ad o o o o pe pe pe rations contain one byte and perf or or or m m m m th th th th e fo fo fo ll ll ll ow ow ow ow in in in g g g g fu fu fu fu nc nc nc nc ti ons: to to to to w w w w ri ri ri ri te te te d d d d at at at a a a a to to to to o o o o ne ne ne ne o o o o f f f f the device data registers or read data fr fr fr fr om om om om i t, t, t, t, t t t t he he he he a a a a dd dd dd dd re re re re ss ss ss ss p p p ointer register must be set so that the co co co rr rr rr rr ec ec ec ec t t t t da da da ta ta ta ta r r r r eg eg eg eg is is is is ter is addressed, then data can be written into th th th th at at at r r r r eg eg eg is is is is te te te te te r r r r or or or or read from it. the first byte of a write operation al al al al wa wa wa wa ys ys ys ys c c c on on on on tains an address that is stored in the address poin ter re re gi gi gi gi st st st er er er . if data is to be written to the device, then the write op op op op er er er er at at at at ion contains a second data byte that is written to the re re re re gi gi gi gi ster selected by the address pointer registe r. this is illustrated in figure 2a. the device addres s is sent ove r the bus followed by r/ w the bus followed by r/ the bus followed by r/ set to 0. this is followed by two data bytes. the first data byte is the address of the in ternal data register to be written to, which is stored in the a ddress pointer register. the second data byte is the data to be wr itten to the internal data register . r/ w r/ 0 scl sda 1 0 1 1 a1 a0 d7 1 0 1 1 a1 a0 r/ w r/ r/ d6 d5 d4 d3 d5 d4 d2 d1 d0 ack. by adm9240 star t by master frame 1 serial bus address byte frame 2 address pointer register byte 1 9 1 ack. by adm9240 9 d7 d6 d7 d6 d5 d4 d3 d5 d4 d2 d1 d0 d1 d0 ack. by adm9 240 stop by mast er fram e 3 data byte 1 9 scl (continued) sda (continued) figure 2a. writing a register address to the address pointer register, then w riting data to the selected register rev. 2 | page 7 of 22 | www.onsemi.com
adm9240 C8C rev. 0 when reading data from a register there are two pos sibilities: 1. if the adm9240s address pointer register value i s un- known or not the desired value, it is first necessa ry to set it to the correct value before data can be read from the desired data register. this is done by performing a write t o the adm9240 as before, but only the data byte containin g the register address is sent, as data is not to be writ ten to the register. this is shown in figure 2b. a read operation is then performed consisting of th e serial bus address, r/ w bit set to 1, followed by the data byte read from the data register. this is shown in figure 2c. 2. if the address pointer register is known to be al ready at the desired address, data can be read from the correspo nding data register without first writing to the address pointer register, so figure 2b can be omitted. notes: 1. although it is possible to read a data byte from a data register without first writing to the address pointer regist er, if the address pointer register is already at the correct value, it is not possible to write data to a register without wr iting to the address pointer register, because the first data by te of a write is always written to the address pointer regi ster. 2. in figures 2a to 2c, the serial bus address is sh own as the default value 01011(a1)(a0), where a1 and a0 are hardwired to either logic 0 or logic 1. analog inputs the adm9240 has six analog inputs. four of these ar e dedi- cated to monitoring the following power supply volt ages: +12 v, +5 v, +3.3 v, +2.5 v. these inputs are multiplexed into the on-chip, succ essive ap- proximation, analog-to-digital converter. this has a resolution of ten bits, but only eight bits are used for the v oltage measure- ment and limit comparison. the basic input range of the adc is 0 v to 2.5 v, and the power supply inputs are sc aled by on- chip attenuators such that the adc produces an outp ut of 3/4 full scale or 192 decimal, when the input voltage i s at its nomi- nal value. the use of on-chip scaling guarantees ac curacy and removes the need for precision external resistors. r/ w 0 scl sda 1 0 1 1 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 ack. by adm9240 stop by master start by master frame 1 serial bus address byte frame 2 address pointer register byte 1 9 1 ack. by adm9240 9 figure 2b. writing to the address pointer register o nly r/ w 0 scl sda 1 0 1 1 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 no ack. by master stop by master start by master frame 1 serial bus address byte frame 2 data byte from adm9240 1 9 1 ack. by adm9240 9 figure 2c. reading data from a previously selected r egister rev. 2 | page 8 of 22 | www.onsemi.com when reading data from a register there are two pos sibilities: 1. if the adm 9240s address pointer register value is un- known or not the desired value, it is first necessa ry to set it to the correct value before data can be read from the desired data register. this is done by performing a write t o the adm9240 as before, but only the data byte containin g the register address is sent, as data is not to be writ ten to the register. this is shown in figure 2b. a read operation is then performed consisting of th e seria l bus address, r/ w bus address, r / bus address, r / bit set to 1, followed by the data byte read from the data register. this is shown in figure 2c. 2. if the address pointer register is known to be al ready at the desired address, data can be read from the correspo nding data register without first writing to the address pointer register, so figure 2b can be omitted. notes: 1. although it is possible to read a data byte from a data register without first writing to the address pointer regist er, if the address pointer register is already at the correct value, it is not possible to write data to a register without wr iting to th th th e address pointer register, because the first data by te of of of of of a a a a write is always written to the address pointer reg is is is is te te te te r. r. r. r. 2. in figures 2a to 2c, the serial bus address is sh own as the default value 01011(a1)(a0), where a1 and a0 are hardwired to either logic 0 or logic 1. an al og i np ut s the adm9240 has six analog inputs. four of these ar e dedi- cated to monitorin g the followin g po wer su pp ly volta ge s: +12 v, +5 v, +3.3 v, +2.5 v. these inputs are multiplexed into the on-chip, succ essive ap- proximation, analog-to-digital converter. this has a resolution of ten bits, but onl y y y ei ei ei gh gh gh t bits are used for the volt ag e measure- ment and limit c c om om om pa pa pa ri so so n. the basic i np ut ran ge of the adc is 0 v to 2.5 v, v, v, a a nd nd nd t he he he p p p p ow ow ow ow er supply inputs are scaled by on- chip atten ua ua ua to to to rs rs rs s s s uc uc uc h h h th th th at t t t he he he he a a a a dc produces an output of 3/4 full sca le le le o o o r 19 19 19 2 de de de ci ci ci ma ma ma l, l, l, w w w he he he n the input voltage is at its nomi - nal va lu lu lu e. e. e. t t t he he he u u u se o f f f on on on -c -c -c hi hi hi p scaling guarantees accuracy and re mo mo mo ve ve ve s the ne ne ne ed ed ed f f f or precision external re re re re si si si si stors. r/ w 0 scl sda 1 0 1 0 1 1 1 a1 a1 a1 a1 a1 a0 d7 a0 d7 a0 d7 a0 d7 a0 d7 a0 d7 a0 d7 a0 d7 a0 d7 a0 d7 a0 d7 a0 d7 a0 d7 r/ w d6 d6 d6 d6 d6 d6 d5 d4 d3 d4 d3 d4 d3 d4 d3 d4 d3 d4 d3 d4 d3 d2 d1 d4 d3 d2 d1 d0 ack. by adm9240 stop by mast er start by mast er fram fram fram fram fram fram fram e 1 e 1 e 1 e 1 e 1 seri seri seri seri seri seri al b al b al b al b al b al b al b us a us a us a us a us a us a us a ddre ddre ddre ddre ddre ddre ss b ss b ss b ss b ss b yte fram e 2 addr addr addr addr addr addr ess poin ter regi ster byt e 1 9 1 1 9 1 1 9 1 1 9 1 1 9 1 1 9 1 1 9 1 ack. ack. ack. ack. ack. ack. ack. by by by by by by by adm9 adm9 adm9 adm9 adm9 adm9 adm9 240 240 240 240 240 9 fi fi fi fi gu gu gu gu re 2b. wr wr wr it it it it in in in g g g to to to t t t he he he a a a dd dd dd dd re re re re re ss ss ss ss ss p p p p ointer register only r/ w 0 scl sda 1 0 1 0 1 1 1 1 1 1 a1 a0 d7 a0 d7 r/ w a0 d7 d6 d5 d6 d5 d4 d3 d2 d1 d4 d3 d2 d1 d0 no ack. by master stop by master star t by master frame 1 serial bus address byte frame 2 data byte from adm9240 1 9 1 1 9 1 1 9 1 1 9 1 1 9 1 1 9 1 1 9 1 ack. by adm9240 9 figure 2c. reading data from a previously selected r egister adm9240 rev. 2 | page 8 of 22 | www.onsemi.com
adm9240 C9C rev. 0 table i. a/d output code vs. v in input voltage a/d output +12 v in +5 v in +3.3 v in +2.5 v in +v ccp1 +v ccp2 decimal binary <0.062 <0.026 <0.0172 <0.013 <0.014 <0.014 0 00000000 0.062C0.125 0.026C0.052 0.017C0.034 0.013C0.026 0.014C0 .028 0.014C0.028 1 00000001 0.125C0.187 0.052C0.078 0.034C0.052 0.026C0.039 0.028C0 .042 0.028C0.042 2 00000010 0.188C0.250 0.078C0.104 0.052C0.069 0.039C0.052 0.042C0 .056 0.042C0.056 3 00000011 0.250C0.313 0.104C0.130 0.069C0.086 0.052C0.065 0.056C0 .070 0.056C0.070 4 00000100 0.313C0.375 0.130C0.156 0.086C0.103 0.065C0.078 0.070C0 .084 0.070C0.084 5 00000101 0.375C0.438 0.156C0.182 0.103C0.120 0.078C0.091 0.084C0 .098 0.084C0.098 6 00000110 0.438C0.500 0.182C0.208 0.120C0.138 0.091C0.104 0.098C0 .112 0.098C0.112 7 00000111 0.500C0.563 0.208C0.234 0.138C0.155 0.104C0.117 0.112C0 .126 0.112C0.126 8 00001000 l l l 4.000C4.063 1.666C1.692 1.100C1.117 0.833C0.846 0.900C0 .914 0.900C0.914 64 (1/4 scale) 01000000 l l l 8.000C8.063 3.330C3.560 2.200C2.217 1.667C1.680 1.800C1 .814 1.800C1.814 128 (1/2 scale) 10000000 l l l 12.000C12.063 5.000C5.026 3.300C3.317 2.500C2.513 2.700 C2.714 2.700C2.714 192 (3/4 scale) 11000000 l l l 15.313C15.375 6.380C6.406 4.210C4.230 3.190C3.203 3.445 C3.459 3.445C3.459 245 11110101 15.375C15.438 6.406C6.432 4.230C4.245 3.203C3.216 3.459 C3.473 3.459C3.473 246 11110110 15.438C15.500 6.432C6.458 4.245C4.263 3.216C3.229 3.473 C3.487 3.473C3.487 247 11110111 15.500C15.563 6.458C6.484 4.263C4.280 3.229C3.242 3.487 C3.501 3.487C3.501 248 11111000 15.563C15.625 6.484C6.510 4.280C4.300 3.242C3.255 3.501 C3.515 3.501C3.515 249 11111001 15.625C15.688 6.510C6.536 4.300C4.314 3.255C3.268 3.515 C3.529 3.515C3.529 250 11111010 15.688C15.750 6.536C6.562 4.314C4.331 3.268C3.281 3.529 C3.543 3.529C3.543 251 11111011 15.750C15.813 6.562C6.588 4.331C4.348 3.281C3.294 3.543 C3.558 3.543C3.558 252 11111100 15.813C15.875 6.588C6.615 4.348C4.366 3.294C3.307 3.558 C3.572 3.558C3.572 253 11111101 15.875C15.938 6.615C6.640 4.366C4.383 3.307C3.320 3.572 C3.586 3.572C3.586 254 11111110 >15.938 >6.640 >4.383 >3.320 >3.586 >3.586 255 111111 11 the input ranges of the analog inputs are shown in more detail in table i. the +v ccp1 and +v ccp2 inputs are used to measure processor core voltages, and have an input range from 0 v to 3.6 v. if only a single processor core voltage is being monit ored, the v ccp2 input may be used to monitor the C12 v supply. this is achieved by using a resistive divider network refer enced to a known positive dc voltage. this is illustrated in f igure 4. input circuits the internal structure for the analog inputs is sho wn in figure 3. each input circuit consists of an input protecti on diode, an attenuator, plus a capacitor to form a first order low-pass filter which gives the input immunity to high frequency no ise. mux +v ccp2 97.3k v 50pf 42.7k v +5v 22.7k v 35pf 122.2k v 55.2k v 25pf 91.6k v 80.9k v 25pf 61.1k v 111.2k v 25pf 36.7k v 97.3k v 50pf 42.7k v +12v +3.3v +2.5v +v ccp1 figure 3. internal structure of analog inputs adm9240 C9C rev. 0 table i. a/d output code vs. v in input voltage a/d output +12 v in +5 v in +3.3 v in +2.5 v in +v ccp1 +v ccp2 decimal binary <0.062 <0.026 <0.0172 <0.013 <0.014 <0.014 0 00000000 0.062C0.125 0.026C0.052 0.017C0.034 0.013C0.026 0.014C0 .028 0.014C0.028 1 00000001 0.125C0.187 0.052C0.078 0.034C0.052 0.026C0.039 0.028C0 .042 0.028C0.042 2 00000010 0.188C0.250 0.078C0.104 0.052C0.069 0.039C0.052 0.042C0 .056 0.042C0.056 3 00000011 0.250C0.313 0.104C0.130 0.069C0.086 0.052C0.065 0.056C0 .070 0.056C0.070 4 00000100 0.313C0.375 0.130C0.156 0.086C0.103 0.065C0.078 0.070C0 .084 0.070C0.084 5 00000101 0.375C0.438 0.156C0.182 0.103C0.120 0.078C0.091 0.084C0 .098 0.084C0.098 6 00000110 0.438C0.500 0.182C0.208 0.120C0.138 0.091C0.104 0.098C0 .112 0.098C0.112 7 00000111 0.500C0.563 0.208C0.234 0.138C0.155 0.104C0.117 0.112C0 .126 0.112C0.126 8 00001000 l l l 4.000C4.063 1.666C1.692 1.100C1.117 0.833C0.846 0.900C0 .914 0.900C0.914 64 (1/4 scale) 01000000 l l l 8.000C8.063 3.330C3.560 2.200C2.217 1.667C1.680 1.800C1 .814 1.800C1.814 128 (1/2 scale) 10000000 l l l 12.000C12.063 5.000C5.026 3.300C3.317 2.500C2.513 2.700 C2.714 2.700C2.714 192 (3/4 scale) 11000000 l l l 15.313C15.375 6.380C6.406 4.210C4.230 3.190C3.203 3.445 C3.459 3.445C3.459 245 11110101 15.375C15.438 6.406C6.432 4.230C4.245 3.203C3.216 3.459 C3.473 3.459C3.473 246 11110110 15.438C15.500 6.432C6.458 4.245C4.263 3.216C3.229 3.473 C3.487 3.473C3.487 247 11110111 15.500C15.563 6.458C6.484 4.263C4.280 3.229C3.242 3.487 C3.501 3.487C3.501 248 11111000 15.563C15.625 6.484C6.510 4.280C4.300 3.242C3.255 3.501 C3.515 3.501C3.515 249 11111001 15.625C15.688 6.510C6.536 4.300C4.314 3.255C3.268 3.515 C3.529 3.515C3.529 250 11111010 15.688C15.750 6.536C6.562 4.314C4.331 3.268C3.281 3.529 C3.543 3.529C3.543 251 11111011 15.750C15.813 6.562C6.588 4.331C4.348 3.281C3.294 3.543 C3.558 3.543C3.558 252 11111100 15.813C15.875 6.588C6.615 4.348C4.366 3.294C3.307 3.558 C3.572 3.558C3.572 253 11111101 15.875C15.938 6.615C6.640 4.366C4.383 3.307C3.320 3.572 C3.586 3.572C3.586 254 11111110 >15.938 >6.640 >4.383 >3.320 >3.586 >3.586 255 111111 11 the input ranges of the analog inputs are shown in more detail in table i. the +v ccp1 and +v ccp2 inputs are used to measure processor core voltages, and have an input range from 0 v to 3.6 v. if only a single processor core voltage is being monit ored, the v ccp2 input may be used to monitor the C12 v supply. this is achieved by using a resistive divider network refer enced to a known positive dc voltage. this is illustrated in f igure 4. input circuits the internal structure for the analog inputs is sho wn in figure 3. each input circuit consists of an input protecti on diode, an attenuator, plus a capacitor to form a first order low-pass filter which gives the input immunity to high frequency no ise. figure 3. internal structure of analog inputs rev. 2 | page 9 of 22 | www.onsemi.com adm924 0 the input ranges of the analog inputs are shown in more detail in table i. the +v ccp 1 and +v ccp 2 inputs are used to measure processor core voltages, and have an input range from 0 v to 3.6 v. if only a single processor core voltage is being monit ored, the v ccp2 input may be used to monitor the C12 v supply. this is achieved by using a resistive divider network refer enced to a known positive dc voltage. this is illustrated in f igure 4. input ci rc ui ts the internal structure for the analog inputs is sho wn in figure 3. each input circuit consists of an input protecti on diode, an attenuator, plus a capacitor to form a first order low-pass filter which gives the input immunity to high frequency no ise. mux +v ccp2 97.3k v 50pf 42.7 k v +5v 22.7k v 35pf 122.2k v 55.2 k v 25pf 91.6 k v 80.9k v 25pf 61.1k v 111. 111. 111. 111. 111. 111. 2k v 25pf 36.7k v 97.3k v 50pf 50pf 50pf 50pf 50pf 50pf 42.7k v +12v +3.3v +2.5 +2.5 +2.5 +2.5 +2.5 +2.5 v v v v +v +v +v +v +v ccp1 ccp1 ccp1 ccp1 fi fi fi gu gu re 3 . i . i . i nt nt nt er na na l l l st st st st ru ru ru ru ct ct ct ur ur ur ur e e e e of analog inputs table i. a/ a/ a/ d d d ou ou ou tp ut ut ut c c c od od od e vs. v in input vo vo vo vo lt lt lt lt ag ag e a e a e a e a e a /d output +12 v in +5 v in +3.3 v in +2.5 v v v v in in in +v ccp ccp ccp ccp 1 1 1 +v +v +v +v ccp ccp ccp ccp ccp 2 2 2 decimal binary <0.062 <0.026 <0.0 17 17 17 17 2 < 2 < 2 < 2 < 2 < 0. 0. 0. 0. 01 01 01 01 3 < 3 < 3 < 3 < 0. 0. 0. 0. 0. 01 01 01 01 4 < 4 < 4 < 4 < 0. 0. 0. 0. 01 01 01 4 0 00000000 0.062C0.125 0.026C0.052 0.01 7C 7C 7C 7C 0. 0. 0. 0. 03 03 03 03 4 0 4 0 4 0 4 0 .0 .0 .0 .0 13 13 13 13 C0 C0 C0 C0 .026 0. 0. 0. 0. 01 01 01 01 4C 4C 4C 4C 4C 0. 0. 0. 02 02 02 02 02 8 0 8 0 8 0 8 0 .0 .0 .0 14C0.028 1 00000001 0. 12 5C 0. 18 7 0 .0 52 C0 .0 78 0. 03 4C 4C 4C 4C 0. 0. 0. 0. 05 05 05 2 0 2 0 2 0 2 0 .0 26 C0 .0 39 0. 0. 0. 0. 02 02 02 02 8C 8C 8C 8C 0. 0. 0. 0. 04 04 04 04 2 0 2 0 2 0 2 0 .0 .0 .0 28 C0 .0 42 2 0 00 00 01 0 0. 18 8C 0. 25 0 0 .0 78 C0 .1 04 0. 0. 0. 0. 05 05 05 05 2C 2C 2C 0. 0. 0. 06 06 06 06 9 0 9 0 9 0 9 0 .0 39 C0 .0 52 52 52 52 0. 0. 04 04 04 2C 2C 2C 2C 0. 0. 0. 0. 05 05 05 05 6 0 6 0 6 0 6 0 .0 42 C0 .0 56 3 0 00 00 01 1 0.250C0.313 0.104C0.1 30 30 30 0. 0. 0. 06 06 06 06 9C 9C 9C 9C 0. 0. 0. 0. 08 08 08 08 6 0 6 0 6 0 6 0 .052 C0 C0 C0 .0 .0 .0 .0 65 65 65 65 0. 0. 0. 0. 05 05 05 05 6C 6C 6C 0. 0. 0. 0. 07 07 07 07 07 0 0 0 0 0 0 0 0 .056C0.070 4 0000010 0 0.313C0.375 0.130C0.1 56 56 56 0. 0. 0. 08 08 08 6C 6C 6C 6C 0. 0. 0. 0. 10 10 10 10 3 0.065 C0 C0 C0 C0 .0 .0 .0 .0 78 78 78 0. 0. 0. 0. 07 07 07 0C 0C 0C 0C 0. 0. 0. 08 08 08 08 4 0.070C0.084 5 00000101 0.375C0.438 0.156 C0 C0 C0 C0 .1 .1 .1 .1 82 82 82 82 0. 10 10 10 3C 3C 3C 0. 0. 0. 0. 12 12 12 12 0 0.0 78 78 78 78 C0 C0 C0 C0 .0 .0 .0 91 91 91 91 0. 0. 0. 08 08 08 08 4C 4C 4C 4C 0. 0. 0. 098 0.084C0.098 6 0000011 0 0.438C0.500 0.1 82 82 82 82 C0 C0 C0 C0 .2 .2 .2 .2 08 08 08 08 0. 0. 0. 12 12 12 0C 0C 0C 0. 0. 0. 13 8 0 8 0 8 0 .0 .0 .0 .0 .0 91 91 91 91 C0 C0 C0 .1 .1 .1 .1 04 04 04 04 0. 0. 0. 0. 09 09 09 8C 8C 8C 0.112 0.098C0.112 7 00000111 0.500C0.563 0.2 08 08 08 C0 C0 C0 C0 .234 0. 0. 0. 0. 13 13 13 8C 8C 8C 0.15 5 0 5 0 5 0 5 0 .1 .1 .1 .1 04 04 04 C0 C0 C0 C0 .1 .1 .1 17 17 17 17 0. 0. 0. 0. 112C0.126 0.112C0.126 8 0000100 0 l l l l l l l l l l l 4.000C4.063 1.666C1.692 1.100C1. 11 11 11 11 7 0 7 0 7 0 7 0 .8 .8 .8 33 33 33 33 C0 C0 C0 C0 .846 0.900C0.914 0.900C0.914 64 (1/4 scale) 01000000 l l l 8.000C8.063 3.330C3.560 2. 20 20 20 0C2.217 1.667C1.680 1.800C1.814 1.800C1.814 128 (1/2 sc ale) 10000000 l l l 12.000C12.063 5.000C5.026 3.300C3.317 2.500C2.513 2.700 C2.714 2.700C2.714 192 (3/4 scale) 11000000 l l l 15.313C15.375 6.380C6.406 4.210C4.230 3.190C3.203 3.445 C3.459 3.445C3.459 245 11110101 15.375C15.438 6.406C6.432 4.230C4.245 3.203C3.216 3.459 C3.473 3.459C3.473 246 1111011 0 15 .4 38 C1 5. 50 0 6 .4 32 C6 .4 58 4. 24 5C 4. 26 3 3 .2 16 C3 .2 29 3. 47 3C 3. 48 7 3 .4 73 C3 .4 87 24 7 1 11 10 11 1 15 .5 00 C1 5. 56 3 6 .4 58 C6 .4 84 4. 26 3C 4. 28 0 3 .2 29 C3 .2 42 3. 48 7C 3. 50 1 3 .4 87 C3 .5 01 24 8 1 11 11 00 0 15.563C15.625 6.484C6.510 4.280C4.300 3.242C3.255 3.501 C3.515 3.501C3.515 249 11111001 15.625C15.688 6.510C6.536 4.300C4.314 3.255C3.268 3.515 C3.529 3.515C3.529 250 1111101 0 15.688C15.750 6.536C6.562 4.314C4.331 3.268C3.281 3.529 C3.543 3.529C3.543 251 11111011 15.750C15.813 6.562C6.588 4.331C4.348 3.281C3.294 3.543 C3.558 3.543C3.558 252 1111110 0 15.813C15.875 6.588C6.615 4.348C4.366 3.294C3.307 3.558 C3.572 3.558C3.572 253 11111101 15.875C15.938 6.615C6.640 4.366C4.383 3.307C3.320 3.572 C3.586 3.572C3.586 254 1111111 0 >15.938 >6.640 >4.383 >3.320 >3.586 >3.586 255 111111 11 rev. 2 | page 9 of 22 | www.onsemi.com
adm9240 C10C rev. 0 setting other input ranges if any of the inputs is unused, and there is a requ irement for monitoring another power supply such as C12 v, the i nput range of the unused input can easily be scaled and offset to accommo- date this. for example, if only one processor core voltage is to be monitored, the unused v ccp input can be used to monitor another supply voltage. if the voltage to be monitored is positive, it is s imply a matter of using an input with a lower full scale than the vol tage to be measured and adding an external input attenuator, b ut bear in mind that the input resistance ( 140 k ) of the on-chip attenua- tor will load the external attenuator. this can be accounted for in the calculation, but the values of the on-chip a ttenuator resis- tors are not precise and vary with temperature. the refore, the external attenuator should have a much lower output resistance to minimize the loading. if this is not acceptable, a buffer ampli- fier can be used. if the input voltage range is negative, it must fir st be converted to a positive voltage. the simplest way to do this is simply to attenuate and offset the voltage, as shown in figur e 4, which shows the +v ccp2 input scaled to measure a C12 v input. using the values shown, the input range is zero to C13.5 v , which will accommodate a +12.5% tolerance on the nominal value . r1 2.7k v r2 1k v ?13.2v to 0v in +v ccp2 < 140k v r3 39k v 0v to 3.6v +5v figure 4. scaling v ccp2 to C12 v (+10%) the resistor ratios are calculated as follows: r 1/ r 2 = | v C|( max )/ v + (to give zero volts at the input for the most negat ive value of vC. r 2 has no effect under this condition as the voltage across it is zero) and: ( v + C v fs )/ v fs = r 2/ r p = ( r 1 and r 2 in parallel ) (to give a voltage v fs at the input when vC is zero, where v fs is the normal full-scale voltage of the input used). this is a simple and cheap solution, but the follow ing points should be noted. 1. since the input signal is not inverted, an increa se in the mag- nitude of the C12 v supply (going more negative), wi ll cause the input voltage to fall and give a lower output c ode from the adc. conversely, a decrease in the magnitude of the C12 v supply will cause the adc code to increase. th is means that the upper and lower limits will be trans posed. 2. since the offset voltage is derived from the +5 v supply, variations in this supply will affect the adc code. it is therefore a good idea to read the value of th e +5 v sup- ply and adjust the limits for the C12 v supply accor dingly. the 5 v supply is attenuated by a factor r p /(r2+r p ), where r p is the parallel combination of r1 and r3. an incre ase in the 5 v supply increases the adc input by the dv r p / (r2+r p ), while a decrease in the 5 v supply correspondingl y decreases the input to the adc. 3. the on-chip input attenuators will load the exter nal attenua- tor, as mentioned earlier. this technique can be applied to any other unused i nput. by suitable choice of v+ and the input resistors, a va riety of nega- tive and/or bipolar input ranges can be obtained. temperature measurement system the adm9240 contains an on-chip bandgap temperature sen- sor. the on-chip adc performs 9-bit conversions on the output of this sensor and outputs the temperature data in 9-bit twos complement format, but only the eight most signific ant bits are used for temperature limit comparison. the full 9-b it tempera- ture data can be obtained by reading the 8 msbs fro m the tem- perature value register (address 27h) and the lsb f rom bit 7 of the temperature configuration register (address 4bh). the format of the temperature data is shown in tabl e ii. theo- retically, the temperature sensor and adc can measu re tem- peratures from C128 c to +127 c with a resolution of 0.5 c, although temperatures below C40 c and above +125 c are outside the operating temperature range of the devi ce. table ii. temperature data format temperature digital output C128 c 1 0000 0000 C125 c 1 0000 0110 C100 c 1 0011 1000 C75 c 1 0110 1010 C50 c 1 1001 1100 C25 c 1 1100 1110 C0.5 c 1 1111 1111 0 c 0 0000 0000 +0.5 c 0 0000 0001 +10 c 0 0001 0100 +25 c 0 0011 0010 +50 c 0 0110 0100 +75 c 0 1001 0110 +100 c 0 1100 1000 +125 c 0 1111 1010 +127 c 0 1111 1111 limit values limit values for analog measurements are stored in the appro- priate limit registers. in the case of voltage meas urements, high and low limits can be stored so that an interrupt r equest will be generated if the measured value goes above or below acceptable values. in the case of temperature, a hot temperatu re limit can be programmed, and a hot temperature hysteresis limit, which will usually be some degrees lower. this can be useful as it allows the system to be shut down when the hot l imit is ex- ceeded, and automatically restarted when it has coo led down to a safe temperature. rev. 2 | page 10 of 22 | www.onsemi.com setting other input ranges if any of the inputs is unused, and there is a requ irement for monitoring another power supply such as C12 v, the i nput range of the unused input can easily be scaled and offset to accommo- date this. for exa mp le, if onl y one pr ocessor core volta ge is to be monitored, the unused v ccp i np ut can be used to monito r another supply voltage . if the voltage to be monitored is positive, it is s imply a matter of usin g an i np ut with a lower full scale than the volt ag e to be measured and addin g an external in pu t attenuator, but bear in mind that the input resistance ( mind that the input resistance ( mind that the input resistance ( 140 k ) of the on-chip attenua- tor will load the external attenuator. this can be accounted f or in the calculation, but the values of the on-chip a ttenuator resis- tors are not precise and vary with temperature. the refore, the external attenuator should have a much lower output resistance to minimize the loading. if this is not acceptable, a buffer ampli - fier can be used. if the input voltage range is negative, it must fir st be converted to a positive voltage. the simplest way to do this is simply to attenuate and offset the voltage, as shown in figur e 4, which shows the +v ccp2 input scaled to measure a C12 v input. u si si si ng ng ng the values shown, the input range is zero to C13.5 v , which w il il il l l l ac co mm od at e a +1 2. 5% t ol er an ce o n th e no mi na l va lu lu lu lu e. e. e. e. r1 2.7k v r2 1k v ?13.2v to 0v in +v ccp2 < 140k 140k 140k 140k 140k 140k 140k v v v v r3 r3 r3 r3 r3 r3 r3 39k 39k 39k 39k v 0v to 3.6v +5v figure 4. scali ng ng ng ng v v v v ccp ccp ccp ccp 2 2 2 2 t t t o o o C1 C1 C1 2 v 2 v 2 v ( ( ( ( +1 +1 +1 +1 0%) ccp 2 2 2 ccp 2 2 2 the resistor ratios are ca lc lc lc ul ul ul ul at at at ed ed ed ed as fo fo fo fo ll ll ll ll ow ow s: r 1/ r 2 = | | | r r v v v v C| C| C| ( ( ( ( v v v v v v ma ma ma x )/ ma x ma x v + v v (to give zero volts at the input for the most negat i ve ve ve v v v v al al al ue ue ue o o o o f f f vC vC vC vC . r 2 has no effect under this condition as the vo lt lt lt ag ag ag ag e e e e ac ac ac ro ro ro ro ss ss ss ss i i i i t t t t is is is r r zero) an d: ( v + C v v v fs v v )/ fs fs v fs v v = fs fs r 2/ r p r r = ( r 1 an d d d r r r 2 in p ar al le l ) in paralle l in paralle l (to give a voltage v fs v v at the input when vC is zero, where fs fs v fs v v is fs fs the normal full-scale voltage of the input used). this is a simple and cheap solution, but the follow ing points should be noted. 1. since the input signal is not inverted, an increa se in the mag- nitude of the C12 v supply (going more negative), wi ll cause the input voltage to fall and give a lower output c ode from the adc. conversely, a decrease in the magnitude of the C12 v supply will cause the adc code to increase. th is means that the upper and lower limits will be trans posed. 2. since the offset voltage is derived from the +5 v supply, variations in this supply will affect the adc code. it is therefore a good idea to read the value of th e +5 v sup - ply and adjust the limits for the C12 v supply accor dingly. the 5 v supply is attenuated by a factor r p /(r2+r p p p ), where r p is the parallel combination of r1 and r3. an incre ase in p p the 5 v supply increases the adc input by the dv r p / p p (r2+r p ), while a decrease in the 5 v supply correspondingl y decreases the input to the adc . 3. the on-chip input attenuators will load the exter nal attenua- tor, as mentioned earlier. this technique can be applied to any other unused i nput. by suitable choice of v+ and the input resistors, a va riety of nega- tive and/or bipolar input ranges can be obtained. temperature measurem ent system the adm9240 co nt nt nt ai ai ai ns an on-chip bandgap temperature se n- sor. the on-ch ip ip ip a a a dc dc dc p p p p erforms 9-bit conversions on the output of this sensor a a a nd nd nd o o o ut ut ut pu pu pu ts ts ts the tem pe rature data in 9-bit twos co mp leme nt nt nt f f f or or or ma ma ma t, b b b ut ut ut o o o nl nl nl y y y th th th th e eight most s ig nificant bits are used f or or or t t t em em em pe pe pe ra tu tu tu re re re l l l im im im it it it c c c om parison. the full 9-bit temper a- ture d d d at at at a a a ca ca ca n n n be be be o o bt ai ai ai ne ne ne d d d by reading the 8 m sbs from the tem - pe pe pe ra ra ra tu tu tu re re re val ue ue ue r r r eg eg eg ister (address 27h) an an an d d d d th th th th e lsb from bit 7 of of of t t t he he he t t t em em em em pera tu tu tu re re re c c c onfiguration r eg eg eg eg eg is is is is te te te te r r r (address 4bh). th th th e e e e fo fo fo rm rm rm at at at o o o f f f the temperature da da da da ta ta ta ta i i i i s s s sh sh sh own in table ii. theo- re ti ti ti ca ca ca ll ll ll y, y, y, t t t he he he t t t empera tu tu tu re re sen so so so r r r r an an an an d d d d ad ad ad c can measure tem- pera tu tu tu re re re s s s fr fr fr om C12 8 8 8 c c c to to to + + + + 12 12 12 7 7 7 c c c wi wi wi wi wi th th th th a a a a r es ol ut io n of 0 .5 c, al th th th ou ou ou gh gh gh tempe ra ra ra tu tu tu re re re s s s be be be be lo lo lo lo w w w w C4 C4 C4 C4 0 0 0 0 c c c c an an an an d above +125 c are ou ou ou ts ts ts id id id e the op op op op er er er er er at at at at in in in in g g g te te te te mp mp mp mp er er er at at at at ur ur ur ur e e e e ra ra ra ra nge of the device. ta ta ta ta bl bl bl bl e e e ii ii ii ii . t . t . t . t em em em em pe pe pe pe rature data format te te te mp mp mp mp er er er at at at ur ur ur e d e d e d e d igital output C1 C1 C1 C1 28 28 28 28 c 1 c 1 c 1 c 1 0000 0000 C1 C1 C1 C1 25 25 25 25 c 1 c 1 c 1 c 1 0000 0110 C1 C1 C1 00 00 00 00 c 1 c 1 c 1 0011 1000 C7 C7 C7 C7 5 5 5 c 1 0110 1010 C5 C5 C5 0 c 1 1001 1100 C25 c 1 1100 1110 C0.5 c 1 1111 1111 0 c 0 0000 0000 +0 .5 c 0 0000 0001 +10 c 0 0001 0100 +25 c 0 0011 0010 +50 c 0 0110 0100 +75 c 0 1001 0110 +100 c 0 1100 1000 +125 c 0 1111 1010 +127 c 0 1111 11 11 limit values limit values for analog measurements are stored in the appro- priate limit registers. in the case of voltage meas urements, high and low limits can be stored so that an interrupt r equest will be ge nerated if the measured value go es above or below acce pt able values. in the case of tem pe rature, a hot te mp erature limit can be programmed, and a hot temperature hysteresis limi t, which will usually be some degrees lower. this can be useful as it allows the system to be shut down when the hot l imit is ex- ceeded, and automatically restarted when it has coo led down to a safe temperature. adm9240 rev. 2 | page 10 of 22 | www.onsemi.com
adm9240 C11C rev. 0 monitoring cycle time the monitoring cycle begins when a one is written t o the start bit (bit 0), and a zero to the int _clear bit (bit 3) of the con- figuration register. int _enable (bit 1) should be set to one to enable the int output. the adc measures each analog input in turn, starting with v ccp2 and finishing with the on-chip tem- perature sensor. as each measurement is completed t he result is automatically stored in the appropriate value re gister. this round-robin monitoring cycle continues until it i s disabled by writing a 0 to bit 0 of the configuration register. the counter controlling the multiplexer is driven b y an on-chip clock of nominally 22.5 khz, so the entire measurement sequence takes (nominally): 44.4 s 7 = 310.8 s this rapid sampling of the analog inputs ensures a quick re- sponse in the event of any input going out of limit s, unlike other monitoring chips that employ slower adcs. when a monitoring cycle is started, monitoring of t he fan speed inputs begins at the same time as monitoring of the analog in- puts. however, the two monitoring cycles are not sy nchronized in any way, and the monitoring cycle time for the f an inputs is dependent on fan speed and much slower than for the analog inputs. for more details see the fan speed measureme nt section. input safety scaling of the analog inputs is performed on-chip, so external attenuators are normally not required. however, sin ce the power supply voltages will appear directly at the p ins, it is advis- able to add small external resistors in series with the supply traces to the chip to prevent damaging the traces o r power sup- plies should an accidental short such as a probe co nnect two power supplies together. as the resistors will form part of the input attenu ators, they will affect the accuracy of the analog measurement if th eir value is too high. the analog input channels are calibrated assuming an external series resistor of 500 , and the accuracy will remain within specification for any value from zero to 1 k , so a stan- dard 510 resistor is suitable. the worst such accident would be connecting C12 v t o +12 v a total of 24 v difference, with the series resisto rs this would draw a maximum current of approximately 24 ma. analog output the adm9240 has a single analog output from an unsi gned 8-bit dac which produces 0 vC1.25 v. the analog out put register defaults to ff during power-on reset, whic h produces maximum fan speed. the analog output may be amplifi ed and buffered with external circuitry such as an op amp and transistor to provide fan speed control. a suitable drive circuit is given in figure 5. care must be taken when choosing the op amp to ensu re that its input common-mode range and output voltage swing ar e suitable. the op amp may be powered from the +12 v rail alone or from 12 v. if it is powered from +12 v then the input co mmon- mode range should include ground to accommodate the mini- mum output voltage of the dac, and the output volta ge should swing below 0.6 v to ensure that the transistor can be turned fully off. if the op amp is powered from C12 v, precautions su ch as a clamp diode to ground may be needed to prevent the base- emitter junction of the transistor being reverse-bi ased in the unlikely event that the output of the op amp should swing nega- tive for any reason. the positive output swing of the op amp should be a s close to +12 v as possible so that the maximum voltage can b e obtained from the transistor. even if the op amp swings to t he rail, the maximum voltage from the emitter of the transistor will be about 11.4 v. typical values for this condition wou ld be: gain = 11.4/1.25 = 9.12 = 1 + r 1/ r 2 r 1 = 82 k , r 2 = 10 k ( nearest preferred valu e) giving an actual gain of 9.2. the transistor should have a reasonably high h fe to avoid its base current pulling down the output of the op amp, it must have an i cmax greater than the maximum fan current and be capable of dissipating power due to the voltage dro pped across it when the fan is not operating at full speed. depend ing on the fan parameters, some suitable devices would be 2n22 19a, 2n3019 or ztx450. +12v r1 ntest_in/aout r2 figure 5. analog output driving fan layout and grounding analog inputs will provide best accuracy when refer red to the gnda pin. a separate, low impedance ground plane fo r analog ground, which provides a ground point for the volta ge dividers and analog components, will provide best performanc e but is not mandatory. the power supply bypass, the parallel combination o f 10 f (electrolytic or tantalum) and 0.1 f (ceramic) bypass capaci- tors connected between pin 9 and ground, should als o be lo- cated as close as possible to the adm9240. rev. 2 | page 11 of 22 | www.onsemi.com adm9240 monitoring cycle tim e the monitoring cycle begins when a one is written t o the start bit (bit 0), and a zero to the in t _clear bit (bit 3) of the con- t figuration register. in t _enable (bit 1) should be set to one to t enable the int output. the adc measures each analog input in turn, starting with v ccp 2 and finishing with the on-chip tem- perature sensor. as each measurement is completed t he result is automatically stored in the appropriate value re gister. this round-robin monitoring cycle continues until it i s disabled by writing a 0 to bit 0 of the configuration register. the counter controlling the multiplexer is driven b y an on-chip clock of nominally 22.5 khz, so the entire measurement sequence takes (nominally): 44 .4 s 7 = 31 0. 8 s this rapid sampling of the analog inputs ensures a quick re- sponse in the event of any input going out of limit s, unlike oth er monitoring chips that employ slower adcs. when a monitoring cycle is started, monitoring of t he fan speed inputs begins at the same time as monitoring of the analog in- puts. however, the two monitoring cycles are not sy nch ro ro ro ni ni ni ze ze ze d in any way, and the monitoring cycle time for the f an in pu pu pu ts ts ts i i i s s s dependent on fan speed and much slower than for th th th th e e e e an an an an al al al al al og og og og inputs. for more details see the fan speed m easu re re re re me me me me nt nt nt nt s s s ec ec ec ec ti on on on on . input safety scaling of the analog inputs is performe d d d d on on on -c -c -c hi hi hi hi p, p, p, p, s o o o o ex ex ex te rn rn rn al al al attenuators are normally not required. h h h h ow ow ow ow ev ev ev er er er , , , , si si si si nc nc nc nc e the power supply voltages will appear di di di di re re re ct ct ct ct ly ly ly a a a a t t t th th th th e pi pi pi ns ns ns ns , , , , it is advis- able to add small external resis to to to rs rs rs i i i n n n n se se se se ri ri ri ri es es w w w w it it it it h h h h th th th th e e e e supply traces to the chip to prevent da da da ma ma ma gi gi gi ng ng ng ng t he he he he t t t ra ra ra ra ce ce s or power s s s up up up up - - plies should an accidental s s s s ho ho ho ho rt rt rt rt s uc uc uc h as as as a p p p p ro ro ro ro be be be be conne ct ct t t t t wo wo wo wo power supplies togethe r. r. r. r. as the resistors will fo rm rm rm p p p p art of of t t t t he he he he i i i i np np np ut ut ut atten ua ua ua to to to rs rs rs , , , th th th th ey ey ey w w w w il il il il l l l affect the accuracy of t he he he he a a a na na na na lo g g g me me me me as as urement if if if t t t he he he ir ir ir v v v v al al al al ue ue ue i i i s too high. the analog inp ut ut ut ut c c c ha ha ha ha nn nn nn nn el el el el s are calibrated a ss ss ss ss um um um um in in in g g g g an an an an external series resistor of 50 0 , and the accura cy cy cy w w w il il il l l l re ma ma ma ma in in in in within specification for any value from zero t o o o 1 1 1 1 k k k , so so so a a a s s s s ta ta ta ta n- dard 510 resistor is suita bl e. the worst such accident would be con ne ne ne ct ct ct ct in in in in g g g C1 C1 C1 2 2 2 2 v v v v to to to +12 v a total of 24 v difference, with the s er er er er ie ie ie ie s s s re re re si si si stors th th th is would draw a maximum current of approxim at at at ely 24 ma. an al og o utput the adm9240 has a single analog output from an unsi gned 8-bit dac which produces 0 vC1.25 v. the analog out put register defaults to ff during power-on reset, whic h pro duces maximum fan speed. the analog output may be amplifi ed and buffered with external circuitry such as an op amp and transistor to provide fan speed control. a suitable drive circuit is given in figure 5. care must be taken when choosing the op amp to ensu re that its input common-mode range and output voltage swing ar e suitable. the op amp may be powered from the +12 v rail alone or from 12 v. if it is powered from +12 v then the input co mmon- mode range should include ground to accommodate the mini- mum output voltage of the dac, and the output volta ge should swing below 0.6 v to ensure that the transistor can be turned fully off. if the op amp is powered from C12 v, precautions su ch as a clamp diode to ground may be needed to prevent the base- emitter junction of the transistor being reverse-bi ased in t he unlikely event that the output of the op amp should swing nega- tive for any reason. the positive output swing of the op amp should be a s close to +12 v as possible so that the maximum voltage can b e obtained from the transistor. even if the op amp swings to t he rail, the maximum voltage from the emitter of the transistor will be about 11.4 v. ty pi cal values for this condition would be: ga ga ga in in in = = = 11.4/1.25 = 9.12 = 1 + ga in in in ga in in in r 1/ r 2 r 1 = = = 82 82 82 k k , r r r r 2 = 10 r r k k k ( nearest pr eferred valu e) nearest preferred va lu nearest preferred va lu giving a n n n ac ac ac tu tu tu al al al g g g ai ai ai n n n of 9 9 9 .2 .2 .2 .2 . th e e tr tr tr an si si si st st st or s ho ho ho ul ul ul d d d ha ha ha ve ve a reasonabl y hi gh h fe the transistor should have a reasonably high h the transistor should have a reasonably high h to avoid its ba ba ba se se se c c c ur ur ur re re re nt nt nt p p p ulli ng ng ng d d d own the ou tp ut of the op a mp , it must ha ha ha ve ve ve an i cma cma cma x g g g re re re ater than the maxi mu mu mu mu m m m m fan current and be cma x cma x ca ca ca pa pa pa bl bl bl e e e e of d is is is si si si pa pa pa ting power due t t t o o o o o th th th th e e e e voltage dropped across it wh wh wh wh en en en t t he he he f f f an an an is not operating at at at at f f f f ul ul ul ul l l l speed. depending on the fa fa fa n n n pa pa pa ra ra ra me me me ters, some suita bl bl bl e e e de de de de vi vi vi vi ce ce ce s would be 2n2219a, 2n 2n 2n 30 30 30 19 19 19 or zt x4 x4 x4 x4 50 50 50 50 . . . +12v r1 ntes ntes ntes ntes ntes ntes ntes t_in t_in t_in t_in t_in t_in t_in /aou /aou /aou /aou /aou /aou /aou t t t t t t t r2 figure 5. analog output driving fan layout and grounding analog inputs will provide best accuracy when refer red to the gnda pin. a separate, low impedance ground plane fo r analog ground, which provides a ground point for the volta ge dividers and analog components, will provide best performanc e but is not mandator y. the power supply bypass, the parallel combination o f 10 f (electrolytic or tantalum) and 0.1 f (ceramic) bypass capaci- tors connected between pin 9 and ground, should als o be lo- cated as close as po ssible to the adm9240. rev. 2 | page 11 of 22 | www.onsemi.com
adm9240 C12C rev. 0 fan inputs two inputs are provide for monitoring the condition of cooling fans. signal conditioning in the adm9240 accommodat es the slow rise and fall times typical of fan tachometer outputs. the maximum input signal range is 0 to v cc . in the event that these inputs are supplied from fan outputs that exceed 0 to v cc , either resistive attenuation of the fan signal or d iode clamping must be included to keep inputs within an acceptabl e range. figures 6a to 6c show circuits for most common fan tacho outputs. if the fan tacho output has a resistive pull-up to v cc it can be connected directly to the fan input, as shown in fi gure 6a. +12v fan1 or fan2 pull-up 4.7k v typ. tacho output v cc fan speed counter figure 6a. fan with tachometer pull-up to +v cc if the fan output has a resistive pull-up to +12 v (or other voltage greater than v cc ), the fan output can be clamped with a zener diode, as shown in figure 6b. the zener vol tage should be chosen so that it is greater than v ih but less than v cc , allowing for the voltage tolerance of the zener. a value of about 0.8 v cc is suitable. +12v fan1 or fan2 pull-up 4.7k v typ. tacho output v cc zd1* zener *choose zd1 voltage approx. 0.8 3 v cc fan speed counter figure 6b. fan with tachometer pull-up to voltage >v cc (e.g., 12 v) clamped with zener diode if the fan has a strong pull-up (less than 1 k ) to +12 v, or a totem-pole output, a series resistor can be added t o limit the zener current, as shown in figure 6c. alternatively , a resistive attenuator may be used, as shown in figure 6d. r1 and r2 should be chosen such that: 2 v < v pull-up r 2/( r pull-up + r 1 + r 2) < v cc if the value of the pull-up resistor is not known, the value of r 1 and r 2 should be made fairly large, but not so large tha t the input leakage current will cause a large voltage dr op across them. with a pull-up voltage of 12 v and pull-up resistor less than 1 k , suitable values for r1 and r2 would be 100 k and 47 k . this will give a high input voltage of 3.83 v. +12v fan1 or fan2 pull-up typ. < 1k v or totem-pole tacho output v cc fan speed counter zd1* zener *choose zd1 voltage approx. 0.8 3 v cc r1 10k v figure 6c. fan with strong tachometer pull-up to >v cc or totem-pole output, clamped with zener and resistor +12v fan1 or fan2 < 1k v tacho output v cc fan speed counter *see text r1* r2* figure 6d. fan with strong tachometer pull-up to >v cc or totem-pole output, attenuated with r1/r2 input current limiting if the fans are powered while the adm9240 is unpowe red, the inputs of the adm9240 will try to clamp the fan out put volt- age. in this case the input current must be limited to less than the maximum value in the absolute maximum ratings t able. the pull-up resistor of the fan tacho output may pr ovide this current limiting but, if its value is too low, it m ay be necessary to add additional resistance in series with the fan input pins. fan speed measurement the fan counter does not count the fan tacho output pulses directly, because the fan speed may be less than 10 00 rpm and it would take several seconds to accumulate a reaso nably large and accurate count. instead, the period of the fan revolution is measured by gating an on-chip 22.5 khz oscillator i nto the input of an 8-bit counter for two periods of the fa n tacho out- put, as shown in figure 7, so the accumulated count is actually proportional to the fan tacho period and inversely proportional to the fan speed. the monitoring cycle begins when a one is written t o the start bit (bit 0), and a zero to the int _clear bit (bit 3) of the con- figuration register int _enable (bit 1) should be set to one to enable the int output. the measurement begins on the rising edge of a fan tacho pulse, and ends on the next-but -one rising edge. once the fan speeds have been measured, they will be stored in the fan speed value registers and can be read at any time. the measurements will be updated as long as t he moni- toring cycle continues. 22.5khz clock config reg. bit 0 fan1 input fan1 measurement period fan2 measurement period start of monitoring cycle fan2 input figure 7. fan speed measurement rev. 2 | page 12 of 22 | www.onsemi.com fan inpu ts two inputs are provide for monitoring the condition of cooling fans. signal conditioning in the adm 9240 accommodates the slow rise and fall times typical of fan tachometer outputs. th e maximum in pu t si gn al ran ge is 0 to v cc . in the event that these in pu ts are s up pl ied from fan out pu ts that exceed 0 to v cc inputs are supplied from fan outputs that exceed 0 to v inputs are supplied from fan outputs that exceed 0 to v , either resistive attenuation of the fan signal or d iode clamping must be included to keep inputs within an acceptabl e range. fi gu res 6a to 6c show circuits for most common fan tach o outputs. if the fan tacho output has a resistive pull-up to v cc i t ca n be connected directly to the fan input, as shown in fi gure 6a. +12v fan1 or f an2 pull-up 4.7k v typ. tacho output v cc fan spee d counter figure 6a. fan with tachometer pull-up to +v cc if the fan output has a resistive pull-up to +12 v (or other voltage greater than v cc ), the fan output can be cla mp mp mp ed ed ed ed ed w w w w it it h h h a zener diode, as shown in figure 6b. the zener vo vo lt lt lt lt ag ag ag ag e e e e should be chosen so that it is greater than v ih should be chosen so that it is greater than v should be chosen so that it is greater than v but l es es es es s th th th an v cc , allowing for the voltage tolerance of the zene r. r. r. r. a a a a v v v v alue o f f f f about 0.8 v cc is suitable. +12v fan1 fan1 fan1 fan1 fan1 or f or f or f or f or f an2 an2 an2 an2 an2 an2 an2 pull -up 4.7k v typ. tacho outp ut v v v v v cc zd1* zd1* zd1* zd1* zd1* zd1* zd1* zd1* zene zene zene zene zene zene r r r r r *choose zd1 voltage approx. 0.8 3 3 3 3 3 3 3 v cc cc cc cc fan fan fan fan fan fan fan speed coun coun coun coun coun coun coun ter figure 6b. fan with t t t ac ac ac ac ho ho ho me te te te te r pu pu pu pu ll-up to v v v ol ol ol ta ta ta ge ge ge ge > > > > v v v cc cc cc cc (e.g., 12 v) clamped wi wi wi th th th th z z z en er er er er d d d d iode if the fan has a strong pull-up (less than 1 k ) to + + + 12 12 12 v v v , or or or a a a totem-pole output, a series resistor can be adde d d d to to to to l l l l im im im im it it it t t t t he he he he zener current, as shown in figure 6c. altern at at at iv iv iv iv el el el el y, y, y, y, a a a r r r es es es es is is is is tive attenuator may be used, as shown in fi gu gu re re re 6 6 6 6 d. d. d. d. r1 and r2 should be chosen such that: 2 v < v v v pull-up v v r 2/( r r r pull-up r r + pull-u p pull-u p r 1 + r 2) < v cc v v if the value of the pull-up resistor is not known, the value of r 1 and r 2 should be made fairly large, but not so large tha t the input leakage current will cause a large voltage dr op across them. with a pull-up voltage of 12 v and pull-up resistor less than 1 k , suitable values for r1 and r2 would be 100 k and 47 k . this will give a high input voltage of 3. 83 v . +12v fan1 or fan2 pull-up typ. < 1k v or totem-pole tacho outp ut v cc fan spee d counter zd1* zener *choose zd1 voltage approx. 0.8 3 v cc r1 10k v figure 6c. fan with strong tachometer pull-up to >v cc or totem-pole output, clamped with zener and cc cc re si st or +12v fan1 or f an2 < 1k v tacho outp ut v cc fan spee d counter *see text r1* r2* fi gu re 6d. fan with stron g tachometer pull-up to >v cc or tote m- m- m- po po po le out pu t, attenuated with r1/r2 cc cc input cu rr rr rr en en en t t t li li li mi mi mi mi ting if the fans ar ar ar e e e po po po we we we re re re d d d wh wh wh il il il e e e th th th e adm9240 is unpowered, the inputs o o f f f th th th e e e ad ad ad m9 m9 m9 24 24 24 0 0 0 wi wi wi ll ll ll t t t ry to clamp the fan output volt- age. i n n n th th th is is is c c c as as as e e e the in in in pu pu pu t t t current must be limited to less than th e e e ma ma ma xi xi xi mu m m m va va va lu lu lu e in the absolute ma xi xi xi xi mu mu mu mu m ratings table. th th th e e e pu pu pu ll ll ll -u -u -u p re si si si st st st or or or of the fan tacho ou ou ou ou ou tp tp tp tp ut ut ut ut may provide thi s cu cu cu rr rr rr en en en t t li li li mi ti ti ti ng ng ng but, if its value is to to to to o o o lo lo lo lo w, w, w, w, it may be necessary to to to a a a dd dd dd a dd dd dd it it it io io io na na na l resistance in se se se se ri ri ri ri es es es es w w w w ith the fan input pins. fa n n n sp sp sp ee ee ee d me me as as as as ur ur ur em em em em en en en en t t t th th th e fa fa fa n coun te te r r r do do do es es es n n n n ot ot ot ot c c c c ou ou ou ou nt nt nt nt t t t t he he he he f f f f an an an tacho out pu t pu lses di di di re re re ctly, be ca ca ca ca us us us us e e e e th th th th e e e fa fa fa fa n n n n sp sp sp sp ee ee ee d d d d ma ma ma ma y y be less than 1000 rpm and it it it would t t ak ak ak ak e e e e e se se se se ve ve ve ve ra ra ra ra l l l l se se se se co co co nd nd nd nd nd s s s s to to to to accumulate a reasonably large and ac cu cu cu cu cu ra ra ra ra te te te te c ou ou ou ou nt nt nt . . . in in in st st st st ea ea ea ea d, d, d, d, t t t he period of the fan revolution is me as as as as ur ur ur ur ed ed ed ed b b b b y y y y ga ga ga ga ti ti ti ti ng ng ng ng a a a a n n n on on on on -c -c hip 22.5 khz oscillator into the in pu pu pu pu t t t t of of of of of a a a a n n n n 8- 8- 8- 8- bi bi bi bi t co co co co un un un un te te te r for two periods of the fan tacho out- pu pu pu t, t, t, a a s s s sh sh sh sh ow ow ow n in in in in f f f f ig ig ig ig ure 7, so the accumulated count is actually pr pr pr pr op op op op or or or ti ti ti ti on on on al al al al t t t t o o o o th th th th e fan tacho period and inversely proportional to to to t t t t he he he he f f f f an an an s s s pe pe pe pe ed ed ed ed . th th th th e mo mo mo mo ni ni ni to to to ring cycle begins when a one is written to the star t bi bi t t t (b (b (b (b it it it 0 0 0 0 ), and a zero to the int _clear bit (bit 3) of the con- t fi fi fi fi gu gu gu gu gu ra ra ra tion register int _enable (bit 1) should be set to one t o t en en en ab ab ab ab le the int output. the measurement begins on the risin g edge of a fan tacho pulse, and ends on the next-but -one rising edge. once the fan speeds have been measured, they will be stored in the fan sp eed value re gi sters and can be read at a ny time. the measurements will be u pd ated as lo ng as the moni- toring cycle continues. 22.5khz clock conf ig reg. bit 0 fan1 input fan1 measurem ent peri od fan2 measurem ent peri od star t of monitoring cycle fan2 input figure 7. fan speed measurement adm9240 rev. 2 | page 12 of 22 | www.onsemi.com
adm9240 C13C rev. 0 to accommodate fans of different speed and/or diffe rent num- bers of output pulses per revolution, a prescaler ( divisor) of 1, 2, 4 or 8 may be added before the counter. the default value is 2, which gives a count of 153 for a fan running at 440 0 rpm pro- ducing two output pulses per revolution. the count is calculated by the equation: count = (22.5 10 3 60) /( rpm divisor ) for constant speed fans, fan failure is normally co nsidered to have occurred when the speed drops below 70% of nom inal, which would correspond to a count of 219. full scal e (255) would be reached if the fan speed fell to 60% of it s nominal value. for temperature controlled variable speed fa ns the situa- tion will be different. table iii shows the relationship between fan speed and time per revolution at 60%, 70% and 100% of nominal rpm for fan speeds of 1100 rpm, 2200 rpm, 4400 rpm and 8800 rpm , and the divisor that would be used for each of these fa ns, based on two tacho pulses per revolution. table iii. fan speeds and divisors time per time per time per nominal 70% rev 60% rev 60% rev divisor rpm (ms) rpm (ms) rpm (ms) 1 8800 6.82 6160 9.74 5280 11.36 2 4400 13.64 3080 19.48 2640 22.73 4 2200 27.27 1540 38.96 1320 45.45 8 1100 54.54 770 77.92 660 90.9 note that fan 1 and fan 2 divisors are programmed i nto bits 4 to 7 of the vid0Cvid3/fan divisor register. limit values fans in general will not overspeed if run from the correct volt- age, so the failure condition of interest is unders peed due to electrical or mechanical failure. for this reason o nly low speed limits are programmed into the limit registers for the fans. it should be noted that, since fan period rather than speed is being measured, a fan failure interrupt will occur when t he measure- ment exceeds the limit value. monitoring cycle time the monitoring cycle time depends on the fan speed and num- ber of tacho output pulses per revolution. two comp lete periods of the fan tacho output (three rising edges) are re quired for each fan measurement. therefore, if the start of a fan m easurement just misses a rising edge, the measurement can take almost three tacho periods. in order to read a valid result from the fan value registers, the total monitoring time allowed after starting the monitoring cycle should therefore be three tacho pe riods of fan1 plus three tacho periods of fan2 at the lowest normal fan speed. although the fan monitoring cycle and the analog in put moni- toring cycle are started together, they are not syn chronized in any other way. fan manufacturers manufacturers of cooling fans with tachometer outpu ts are listed below: nmb tech 9730 independence ave. chatsworth, california 91311 818-341-3355 818-341-8207 airflow model frame size cfm 2408nl 2.36 in sq. 0.79 in (60 mm sq. 20 mm) 9C16 2410ml 2.36 in sq. 0.98 in (60 mm sq. 25 mm) 14C25 3108nl 3.15 in sq. 0.79 in (80 mm sq. 20 mm) 25C42 3110kl 3.15 in sq. 0.98 in (80 mm sq. 25 mm) 25C40 mechatronis inc. p.o. box 613 preston, wa 98050 800-453-4569 modelsvarious sizes available with tach output opt ion. sanyo denki/keymarc electronics 468 amapola ave. torrance, ca 90501 310-783-5400 models109p series chassis intrusion input the chassis intrusion (ci) input is an active high input/open- drain output intended for detection and signalling of unautho- rized tampering with the system. an external circui t powered from the systems cmos backup battery is used to de tect and latch a chassis intrusion event, whether the system is powered up or not. once a chassis intrusion has been detected and latched, the ci input will generate an interrupt when the sy stem is pow- ered up. the actual detection of chassis intrusion is perfor med by an external circuit that will, for example, detect whe n the cover has been removed. a wide variety of techniques may be u sed for the detection: C microswitch that opens or closes when the cover is removed. C reed switch operated by magnet fixed to the cover. C hall-effect switch operated by magnet fixed to the cover. C phototransistor that detects light when cover is r emoved. the chassis intrusion interrupt will remain asserte d until the external detection circuit is reset. this can be ac hieved by set- ting bit 6 of the configuration register, or bit 7 of the chassis intrusion clear register to one, which will cause t he ci pin to be pulled low for at least 20 ms. these register bits are self-clearing. rev. 2 | page 13 of 22 | www.onsemi.com adm9240 to accommodate fans of different speed and/or diffe rent num- bers of output pulses per revolution, a prescaler ( divisor) of 1, 2, 4 or 8 may be added before the counter. the default value is 2, which gives a count of 153 for a fan running at 440 0 rpm pro- ducing two output pulses per revolution. the count is calculated by the equation: count = ( 22.5 coun t coun t 10 3 6 0) / ( rpm diviso r ) diviso r diviso r for constant speed fans, fan failure is normally co nsidered to have occurred when the speed drops below 70% of nom inal, which would correspond to a count of 219. full scal e (255) would be reached if the fan speed fell to 60% of it s nominal value. for temperature controlled variable speed fa ns the situa- tion will be different. table iii shows the relationship between fan speed and time per revolution at 60%, 70% and 100% of nominal rpm for fan speeds of 1100 rpm, 2200 rpm, 4400 rpm and 8800 rpm , and the divisor that would be used for each of these fa ns, based on two tacho pulses per revolution. table iii. fan speeds and divisors time per time per tim tim tim e p e p e p e p er er er nominal 70% rev 60% rev 60% 60% 60% 60% re re re re v v v v divisor rpm (ms) rpm (ms) rpm rpm rpm (ms) 1 8800 6.82 6160 9. 74 5 74 5 74 5 74 5 280 280 280 280 280 11. 11. 11. 11. 36 36 36 36 2 4400 13.64 3080 1 9.4 9.4 9.4 9.4 8 26 8 26 8 26 8 26 40 2 40 2 40 2 40 2 2.7 2.7 2.7 2.7 3 3 3 3 4 2200 27.27 1540 3 8.9 8.9 8.9 8.9 6 13 6 13 6 13 6 13 20 4 20 4 20 4 20 4 5.45 8 1100 54.54 77 0 77 0 77 0 77 0 77 .92 .92 .92 660 660 660 660 90.9 note that fan 1 and fan 2 di vi vi vi so so so rs rs rs a a a re re re p p p p ro ro ro ro gr gr gr gr am am am med into b b b it it it s s s 4 4 4 4 to 7 of the vid0Cvid3/ fa fa fa fa n n n n di di di di vi vi vi vi so so so r re re re gi gi gi st st st st er er . . . limit values fans in general will n ot ot ot o o o o ve ve ve rspe ed ed ed ed i f f f f run from t he he he c c c or or or re re re ct ct ct ct v v v ol ol ol t- t- t- t- age, so the failure cond it it io io io n n of of of of i i i i nt nt nt er er er er est is underspee d d d du du du du e e e e to to to to electrical or mechanical fai lu lu lu lu re. fo fo fo fo r this reason on ly ly ly ly l l l l ow ow ow ow s s s pe pe pe pe ed ed ed ed limits are programmed into the limit registers f f or or or t t t t he he he he f f f f an an an an s. s. s. i i i i t t t should be noted that, since fan period rathe r r r th th th th an an an an s s s pe pe pe pe ed ed ed ed i i i s s s being measured, a fan failure interrupt will occ ur ur ur w w w w he he he he n n th th th th th e e e me me me asure- ment exceeds the limit value. monitoring cycle tim e the monitoring cycle time depends on the fan speed and num- ber of tacho output pulses per revolution. two comp lete periods of the fan tacho output (three rising edges) are re quired for each fan measurement. therefore, if the start of a fan m easurement just misses a rising edge, the measurement can take almost three tacho periods. in order to read a valid result from the fan value registers, the total monitoring time allowed after starting the monitoring cycle should therefore be three tacho pe riods of fan1 plus three tacho periods of fan2 at the lowest normal fan speed. although the fan monitoring cycle and the analog in put moni- toring cycle are started together, they are not syn chronized in any other way. fan manufacturers manufacturers of cooling fans with tachometer outpu ts are listed below: nm b tech 9730 independence ave. chatsworth, california 91311 818-341-3355 81 8- 34 1- 82 07 airf lo w mo de l f ra me s iz e c fm 2408nl 2. 36 36 36 i i i n sq sq sq . 0.79 in (60 mm sq. 20 mm) 9C16 2410ml 2. 2. 2. 36 36 36 i i i n n n sq sq sq . 0.98 in (60 mm sq. 25 mm) 14C 25 3108nl 3. 3. 3. 15 15 15 i i i n n n sq sq sq . 0 0 0 .7 .7 .7 .7 9 in (80 mm sq. 20 mm) 25C 42 3110 kl kl kl 3. 3. 3. 15 15 15 i i i n n n sq sq sq . 0 0 0 .9 .9 .9 .9 8 in (80 mm sq. 25 mm) 25C40 me me me ch ch ch at at at ro ro ro ni ni ni s s s in c. p. p. p. o. o. o. box 6 6 6 13 13 13 pr pr pr es es es to to to n, n, n, n, w a a a 98 98 98 05 05 05 0 80 80 80 80 0- 0- 0- 45 45 45 3- 3- 3- 45 45 45 69 mo mo mo de de de ls ls ls v v v arious sizes avail ab ab ab ab le le le le w w w w ith tach output option. sa sa sa ny ny ny o o o de de de nki/ ke ke ke ym ym ym ym ar ar ar c c c el el el el ec ec ec tr tr tr on on on ic ic ic ic ic s s s s 46 46 46 8 8 8 amapola av av av e. e. e. to to to rrance, ca ca ca ca ca 9 9 9 9 05 05 05 01 01 01 01 310-78 3- 3- 3- 3- 3- 54 54 54 54 00 00 00 00 mo de de de ls ls ls ls 1 1 1 1 09 09 09 09 p p p p se se se se ri ri ri es es es es ch ch ch ch ch as as as as si si si si s s s s in in in in tr tr tr tr us us us us io io io n input th th th th e e e ch ch ch ch as as as as si si si si s s s in in in in tr tr tr tr us us us us ion (ci) input is an active high input/open- dr dr dr ai ai ai n n n ou ou ou ou tp tp tp tp ut ut ut ut i i i i nt nt nt ended for detection and signalling of unautho- ri ri ri ri ze ze ze ze d d d d ta ta ta mp mp mp er er er er ing with the system. an external circuit powered fr fr fr fr om om om om t t t t he he he he systems cm os backup battery is used to detect and la la la la tc tc tc h h h h a a c hassis intrusion event, whether the system is power ed up or or or or n n n n ot ot . once a chassis intrusion has been detected and latc hed, th th th e ci input will generate an interrupt when the syst em is pow- ered up. the actual detection of chassis intrusion is perfor med by an external circuit that will, for example, detect whe n the cover has been removed. a wide variety of techniques may be u sed for the detection: C m icroswitch that opens or closes when the cover is r emoved. C reed switch operated by magnet fixed to the cover . C hall-effect switch operated by magnet fixed to the cover. C phototransistor that detects light when cover is r emoved. the chassis intrusion interrupt will remain asserte d until the external detection circuit is reset. this can be ac hieved by set- ting bit 6 of the configuration register, or bit 7 of the chassis intrusion clear register to one, which will cause the ci pin to be pulled low for at least 20 ms. these register bits are self-cl earing. rev. 2 | page 13 of 22 | www.onsemi.com
adm9240 C14C rev. 0 the chassis intrusion circuit should be designed so that it can be reset by pulling its output low. a suitable chassis intrusion cir- cuit using a phototransistor is shown in figure 8. light falling on the phototransistor when the pc cover is removed will cause it to turn on and pull up the input of n1, thus set ting the latch n3/n4. after the cover is replaced, a low reset on the ci output will pull down the input of n4, resetting the latch . +5v cmos backup battery 1n914 1n914 ci 74hc132 470k v mrd901 100k v 10k v figure 8a. chassis intrusion detector and latch the chassis intrusion input can also be used for ot her types of alarm input. figure 8b shows a temperature alarm ci rcuit using an ad22105 temperature switch sensor. this produces a low- going output when the preset temperature is exceede d, so the output is inverted by q1 to make it compatible with the ci input. q1 can be almost any small-signal npn transi stor, or a ttl or cmos inverter gate may be used if one is ava ilable. see the ad22105 data sheet for information on selecting r set . configuration register int _enable int _clear int ci (chassis intrusion) data demultiplexer high and low limit comparators +v ccp2 +12v +5v +3.3v +2.5v +v ccp1 fan1 fan2 temp high limit low limit value from value and limit registers 1 = out of limit masking data from bus interrupt status registers status bit mask bit mask gating 3 10 interrupt mask registers figure 9. interrupt register structure r1 10k v v c ci ad22105 temp. sensor r set q1 figure 8b. using the ci input with a temperature sen sor note: the chassis intrusion input does not have a p rotective clamp diode to v cc , as this could pull down the chassis intru- sion latch and reset it when the adm9240 was powere d down. the adm9240 interrupt structure the interrupt structure of the adm9240 is shown in figure 9. as each measurement value is obtained and stored in the appropriate value register, the value and the limit s from the corresponding limit registers are fed to the high a nd low limit comparators. the result of each comparison (1 = out of limit, 0 = in limit) is routed to the corresponding bit in put of the interrupt status registers via a data demultiplexer and used to set that bit high or low as appropriate. the interrupt mask registers have bits correspondin g to each of the interrupt status register bits. setting an inte rrupt mask bit high forces the corresponding status bit output low , while set- ting an interrupt mask bit low allows the correspon ding status bit to be asserted. after masking, the status bits are all ored together to produce the int output, which will pull low if any unmasked status bit goes high, i.e., when any measu red value goes out of limit. the int output is enabled when bit 1 of the configuration register ( int _enable) is high, and bit 3 ( int _clear) is low. rev. 2 | page 14 of 22 | www.onsemi.com the chassis intrusion circuit should be designed so that it can be reset by pulling its output low. a suitable chassis intrusion cir- cuit using a phototransistor is shown in figure 8. light falling on the phototransistor when the pc cover is removed will cause it to turn on and pull up the input of n1, thus set ting the latc h n3/n4. after the cover is re pl aced, a low reset on the ci ou tp ut will p ull down the i np ut of n4, resettin g the latch. +5v cmos backup battery 1n914 1n914 ci 74hc132 470k v mrd901 100k v 10k v figure 8a. chassis intrusion detector and lat ch ch ch ch ch the chassis intrusion input can also be used for ot h er er er er t t t yp yp yp yp es es es es o o o o f f f alarm input. figure 8b shows a temperature alarm c ir ir ir cu cu cu cu it usi ng ng ng ng an ad22105 temperature switch sensor. this p p p p ro ro ro ro du du du du ce ce ce ce ce s a a a a low- going output when the preset temperature i s s s s ex ex ex ce ce ce ed ed ed ed ed, so so so so t he he he he output is inverted by q1 to make it compat ib ib ib ib ib le le le le w w w w it it it it h h th e e e e ci ci input. q1 can be almost any small-si gn gn gn gn al al al n n n n pn pn pn pn t t t ra ra ra ra ns ns ns ns is to to to to r, r, r, r, or a ttl or cmos inverter gate may be be be u u u se se se se d d d d if if if if o ne ne ne ne i i i i s av av av av ai ai ai ai la la la la ble. see the ad22105 data sheet for inf or or ma ma ma ti ti ti on on on o o o o n n n n se se se le le le le ct ct ct ct in in in in g r r set . configuration register int _enable int int _clear int int ci (chassis intrusion) data data data data data data data demu demu demu demu demu demu demu ltip ltip ltip ltip ltip ltip ltip lexe lexe lexe lexe lexe lexe r high and low limit comp arat ors +v +v +v +v +v +v ccp2 ccp2 ccp2 ccp2 ccp2 ccp2 ccp2 +12v +12v +12v +12v +12v +12v +12v +5v +3.3 +3.3 +3.3 +3.3 +3.3 +3.3 v +2.5v +v ccp1 fan1 fan2 temp high limit low limit value from value and limit registers 1 = out of limit mask ing data from bus interrupt status registers status bit mask bit mask gating 3 10 interrupt mask registers figure 9. interrupt register structure r1 10k v v c ci ad2 210 5 temp. sensor r r set q1 q1 figure 8b. using the ci input with a temperature sen sor note: the chassis intrusion in pu t does not have a pr otective clam p diode to v cc cc cc , , , as as as this could pu ll down the chassis intru- sion latch and r es es es et et et i i i t t t wh wh wh en the adm 9240 was powered down. th e ad m9 m9 m9 24 24 24 0 0 0 in in in te te te rr rr rr up up up up t t t t st ru ct ur e the in te te te rr rr rr up up up t t t st ru ru ru ct ct ct ur ur ur e e e of of of t t t he he he adm 9240 is shown in figure 9. as e ac ac ac h h h me me me as as as ur ur ur em en en en t t t va va va lu lu lu e is obtained and stored in the ap ap pr pr pr op op op ri ri ri ate va va va lu lu lu e e e register, the value an an an d d d d th th th th e limits from the co co co rr rr rr e e e sp sp sp on on on ding l l l im im im it it it r r egisters are fed t t o o o o o th th th th e e e e hi hi hi gh and low lim it co co co mp mp mp ar ar ar at at at or s. s. s. t t t he result of each co co co mp mp mp mp ar ar ar ar is is is is on (1 = out of limit, 0 0 0 = = = in in in l l l im im im it it it ) ) ) is is is routed to the c or or or or re re re re sp sp sp sp onding bit input of the in te te te rr rr rr up up up t t t st st st at at at us reg is is is te te te rs rs rs v ia ia a a a a d d d d at at at at a a a de de de de mu mu mu mu ltiplexer and used to set th th th at at at b b b it it h ig h or or l l l l ow ow ow ow a a a s s s ap ap ap ap pr pr pr pr op op op ri ri at at at at e. e. e. e. th th th e e e in in in terrupt ma ma ma ma sk sk sk sk r r r eg eg eg eg is is is is te te te te rs rs rs rs h h h h av av av av e e e e bi bi bi ts corresponding to each of th th th e e e interr up up up t t t st st st st at at at at us us us r r r r eg eg eg eg is is is is te te te r r r r bi bi bi bi ts ts ts ts . setting an interrupt m ask bit high for ce ce ce ce s s s s th th th th e e e e co co co co rr rr rr es es es es po po po po nd nd nd in in in in in g g g g st st st st atus bit output low, while set- ti ng a n n n n in in in in in te te te te rr rr rr rr up up up up t t t t ma ma ma ma sk sk sk b b b b it it it it l l l ow ow allows the corres po ndin g status bit to to to to to b b b b b e e e as as as se se se se rt rt rt rt ed ed ed ed . af af af af te te te r r r maskin g, the status bits are all ored to to to ge ge ge ge th th th th er er er er t o o o o pr pr pr pr od od od uc uc uc e e e th th th th e e int output, which will pull low if any t un un un ma ma ma sk sk sk sk ed ed ed ed s s s s ta ta ta tu tu tu tu s s s s bi bi bi bi t goes high, i.e., when any measured value go go go go es es es es o o o o ut ut ut ut o o o f f f li li li li mi mi mi mi mi t. t. t. t. th th th th e e e e in in in in t t t t o o o o ut ut ut ut pu t is enabled when bit 1 of the confi gu ration t t t re re re gi gi gi gi st st st er er er er ( ( ( ( in in in t register ( ( ( register ( ( ( _enable) is high, and bit 3 ( int _enable) is high, and bit 3 ( _enable) is high, and bit 3 ( _clear) is low. adm9240 rev. 2 | page 14 of 22 | www.onsemi.com
adm9240 C15C rev. 0 interrupt clearing reading an interrupt status register will output th e contents of the register, then clear it. it will remain cleared until the moni- toring cycle updates it, so the next read operation should not be performed on the register until this has happened, or the result will be invalid. the time taken for a complete moni toring cycle is mainly dependent on the time taken to measure th e fan speeds, as described earlier. the int output is cleared with the int _clear bit, which is bit 3 of the configuration register, without affecting the contents of the interrupt (int) status registers. when this bit is high, the adm9240 monitoring loop will stop. it will resu me when the bit is low. temperature interrupt modes as mentioned earlier, two limit values can be progr ammed for the temperature measurement, a hot temperature limi t (t hot ), and a hot temperature hysteresis limit (t hothyst ), which is normally some degrees lower. the interrupt function of the temperature sensor di ffers from the interrupt operation of the other inputs in that there are three interrupt modes, called one-time interrupt mode, default interrupt mode and comparator mode. default interrupt mode exceeding t hot causes an interrupt that will remain active indefinitely until reset by reading interrupt statu s register 1 or cleared by the int _clear bit in the configuration register. once an interrupt event has occurred by crossing t hot , then reset, an interrupt will occur again once the next temperature conversion has completed. the interrupts will conti nue to occur in this manner until the temperature goes below t hothyst . operation in the default interrupt mode is illustra ted in figure 10. for clarity, in this illustration the interval between read operations is shown as considerably longer than the monitoring cycle time, so that the interrupt is always reasser ted after being reset, before the next read operation occurs. temp read read read read read read read int t hot t hothyst figure 10. temperature int output in default interrupt mode one-time interrupt mode exceeding t hot causes an interrupt that will remain active indefinitely until reset by reading interrupt statu s register 1 or cleared by the int _clear bit in the configuration register. once an interrupt event has occurred by crossing t hot , then reset, an interrupt will not occur again until the temperature goes below t hothyst . operation in the one-time interrupt mode is illustrated in figure 11. again, the interv al between read operations is shown as being longer than the m onitoring cycle time. read read read read read read read int t hot t hothyst temp figure 11. int output in one-time interrupt mode comparator mode exceeding t hot causes the int output to go low. int will remain low until the temperature goes below t hot . once the temperature goes below t hot , int will go high. t hothyst is ignored. in other words, comparator mode operates l ike a thermostat with no hysteresis. operation in the com parator mode is illustrated in figure 12. int t hot temp figure 12. int output in comparator mode reset input/output reset (pin 12) is an i/o pin that can function as an ope n- drain output, providing a low going 20 ms output pu lse when bit 4 of the configuration register is set to 1, pr ovided the reset function has first been enabled by setting bit 7 of interrupt mask register #2 to 1. the bit is automatically cle ared when the reset pulse is output. pin 11 can also function as a reset input by pulling this pin low to reset the internal registers of the adm9240 to default values. only those registers tha t have power on default values as listed in table vi are a ffected by this function. the dac register, value and limit registe rs are not affected. nand tree tests a nand tree is provided in the adm9240 for automate d test equipment (ate) board level connectivity testing. t he device is placed into nand test mode by powering up with p in 11 held high. this pin is sampled automatically after power-up and if it connected high, then the nand test mode is in voked. in nand test mode, all digital inputs may be tested as illus- trated below. a0/ntest_out will become the nand tre e output pin. to perform a nand tree test, all pins i ncluded in the nand tree should be driven high. rev. 2 | page 15 of 22 | www.onsemi.com adm9240 interrupt clearing reading an interrupt status register will output th e contents of the register, then clear it. it will remain cleared until the moni- toring cycle updates it, so the next read operation should not be performed on the register until this has happened, or the result will be invalid. the time taken for a complete moni toring cycle is mainly dependent on the time taken to measure th e fan speeds, as described earlier. the int output is cleared with the t int _clear bit, which is bit t 3 of the configuration register, without affecting the contents of the interrupt (int) status registers. w hen this bit is high, the adm9240 monitoring loop will stop. it will resu me when the bit is low . temperature interrupt modes as mentioned earlier, two limit values can be progr ammed for the temperature measurement, a hot temperature limi t (t hot the temperature measurement, a hot temperature limi t ( t the temperature measurement, a hot temperature limi t ( t ), hot hot and a hot temperature hysteresis limit ( t hot hys t and a hot temperature hysteresis limit ( t and a hot temperature hysteresis limit ( t ), which is normally some degrees lower. the interrupt function of the temperature sensor di ffers from the interrupt operation of the other inputs in that there ar ar ar e e e th th th ree interrupt modes, called one-time interrupt mode, de de de fa fa fa ul ul ul t t t interrupt mode and comparator mode. default interrupt mode exceeding t hot causes an interrupt that wi wi wi wi ll ll ll ll r r r r em em em ai ai ai ai ai n n ac ac ac ti ve ve ve indefinitely until reset by reading interr up up up up t st st st at at at at us r r r eg eg eg eg ister 1 1 1 or cleared by the int _clear bit in the co nf nf nf nf nf ig ig ig ig ur ur ur ur at at at at io n n n n re re re re gi gi gi gi ster. once an interrupt event has occu rr rr rr rr ed ed ed b b b b y y y y cr cr cr cr os os os os si si si si ng t t t t hot hot hot hot once an interrupt event has occurred by crossing t once an interrupt event has occurred by crossing t , then reset, an interrupt will occur a ga ga ga in in in o o o o nc nc nc nc e th th e ne ne ne ne xt xt xt xt t t t t em em em em peratu re re re conversion has completed. th th th e e e in in in te te te rr rr rr up up up up ts ts ts ts w w w il il il il l l continue to oc oc oc cu cu cu cu r r r in this manner until the t em em em em pe pe pe pe ra tu tu tu re g g g oes be be be be lo lo lo lo w t hot hys hys hys hys t t t t . operation in the defau lt lt lt lt i i i nt nt nt nt er er er er ru ru ru ru pt pt pt m m m od od od e e e is is i i i ll ll ll ll ustrated i i i i n n n n fi fi fi fi gu gu gu re re re re 10. for clarity, in this i i i i ll us us us us trat io io io n n n n th th th th e in in in te te te rval bet we we we en en en r r r r ea ea ea d d d operations is shown as c c c on on on sidera bl bl bl bl y y y y longer than th th th e e e mo mo mo ni ni ni ni to to to ri ri ri ri ng ng ng ng cycle time, so that the in in in in te te te rr rr up up up up t t t t is is is a a a a lways reassert ed ed ed a a a a ft ft ft ft er er er er b b b b ei ei ei ng ng ng ng reset, before the next read op op op op er er er er at at at at ion occurs. temp read read read read read read read int t hot t hothyst figure 10. temperature int output in default interrupt t mode one-time interrupt m ode exceeding t hot causes an interrupt that will remain active indefinitely until reset by reading interrupt statu s register 1 or cleared by the int _clear bit in the configuration register. once an interrupt event has occurred by crossing t hot once an interrupt event has occurred by crossing t once an interrupt event has occurred by crossing t , then reset, an interrupt will not occur again until the temperature goes below t hothyst . operation in the one-time interrupt mode is illustrated in figure 11. again, the interv al between read operations is shown as being longer than the m onitoring cycle time. read read read read read read read read read read read read read read read int t hot t hothyst temp fi fi fi gu gu gu re re re 11. in in in t t t o o o ut ut ut put in one-time interrupt mode t co co co mp mp ar ar at at at or or or m ode ex ex ex ce ce ce ed ed ed ed ing t hot causes th e in t t t o o o ut ut ut ut pu pu pu pu t to go low. t t t int w il l t re ma ma ma in in l l l ow ow ow until the tempe ra ra ra ra tu tu tu tu re re re re g g g oes below t hot . on ce t he te te te mp mp mp er er er at at at ur ur e goes b b b el el el ow t hot hot hot hot , , , in in in in t t t will go high. t t hothyst is ig ig ig no no no re re re d. d. d. in ot he he he r r r r wo wo wo rd rd rd s, s, s, s, c c c om om om pa pa pa pa ra ra ra ra ra to to to to r r r r mode operates like a th th th er er er mostat w it it it h h h no no no h ys ys ys ys te te te te re re re si si si s. s. s. s. o o o o pe pe pe pe ration in the comparator mo mo mo de is il lu lu lu st st st st ra ra ra ra te te te te d d d in in in in f f f f ig ig ig ur ur ur ur e e e e 12 12 12 12 . int int int int t hot hot hot hot hot temp temp temp temp temp temp temp figure 12. int output in comparator mode t reset input/output reset (pin 12) is an i/o pin that can function as an ope n- t drain output, providing a low going 20 ms output pu lse when bit 4 of the configuration register is set to 1, pr ovided the reset function has first been enabled by setting bit 7 of interrupt mask register #2 to 1. the bit is automatically cle ared when the reset pu lse is out pu t. pin 11 can also function as a reset in pu t by p ulli ng this pi n low to reset the internal re gi sters of t he adm9240 to default values. only those registers tha t have power on default values as listed in table vi are a ffected by this function. the dac register, value and limit registe rs are not affected. nand tree test s a nand tree is provided in the adm 9240 for automated test equipment (ate) board level connectivity testing. t he device is placed into nand test m ode by powering up with pin 11 held high. this pin is sampled automatically after power-up and if it connected hi gh , then the nand test mode is invoked. in nand test mode, all digital inputs may be tested as illus- trated below. a0/ntest_out will become the nand tre e output pin. to perform a nand tree test, all pins i ncluded in the nand tree should be driven h ig h. rev. 2 | page 15 of 22 | www.onsemi.com
adm9240 C16C rev. 0 the structure of the nand tree is shown in figure 1 3. beginning with a1 and working clockwise around the chip, each pin can be toggled and a resulting toggle can be ob served on ntest_out/a0. allow for a typical propagation delay of 500 ns. sda scl fan1 fan2 vid0 vid1 vid2 vid3 vid4 a1 ntest_out figure 13. nand tree note: if any of the inputs shown in figure 9 are un used, they should not be connected directly to ground, but via a resistor such as 10 k . this will allow the ate (automatic test equip- ment) to drive every input high so that the nand tr ee test can be properly carried out. using the adm9240 power-on reset when power is first applied, the adm9240 performs a power- on reset on several of its registers. registers wh ose power-on values are not shown have power-on conditions that are indeter- minate (this includes the value and limit registers ). the adc is inactive. in most applications, usually the firs t action after power-on would be to write limits into the limit re gisters. power-on reset clears or initializes the following registers (the initialized values are shown in table vi: C configuration register C serial address register C interrupt (int) status registers #1 and #2 C interrupt (int) mask registers #1 and #2 C vid /fan divisor register C vid4 register C chassis intrusion clear register C temperature configuration register C test register C compatibility register C analog output register initialization configuration register initialization performs a si milar, but not identical, function to power-on reset. the test register and analog output register are not initialized. configuration register initialization is accomplish ed by setting bit 7 of the configuration register high. t his bit auto- matically clears after being set. using the configuration register control of the adm9240 is provided through the conf iguration register. the adc is stopped upon power-up, and the int _clear signal is asserted, clearing the int output. the configuration register is used to start and stop the adm9240; ena ble or dis- able interrupt outputs and modes, and provide the i nitialization function described above. bit 0 of the configuration register controls the mo nitoring loop of the adm9240. setting bit 0 low stops the monitor ing loop and puts the adm9240 into a low power mode thereby reduc- ing power consumption. serial bus communication is still pos- sible with any register in the adm9240 while in low power mode. setting bit 0 high starts the monitoring loop . bit 1 of the configuration register enables or disa bles the int interrupt output. setting bit 1 high enables the int output, setting bit 1 low disables the output. bit 3 of the configuration register is used to clea r the int interrupt output when set high. the adm9240 monitor ing function will stop until bit 3 is set low. interrup t status register contents will not be affected. bit 4 of the configuration register is used to init iate a mini- mum 20 ms reset signal on the reset output if the function is enabled by bit 7 in register 44. bit 6 of the configuration register is used to rese t the chassis intrusion (ci) output pin when set high. bit 7 of the configuration register is used to star t a configura- tion register initialization when taken high. starting conversion the monitoring function (analog inputs, temperature and fan speeds) in the adm9240 is started by writing to the configura- tion register and setting start (bit 0), high, int _enable (bit 1) high and int _clear (bit 3) low. apart from initially starting together, the analog measurements and fan speed mea surements proceed independently and are not synchronized in a ny way. the analog measurements will be completed in no mor e than 353 s. the time taken to complete the fan speed measure ments depends on the fan speed and the number of tacho ou tput pulses per revolution. once the measurements have been completed, the resu lts can be read from the value registers at any time. table iv shows the measurement sequence for the ana log inputs. table iv. measurement sequence measurement # parameter 1 analog +v ccp2 2 analog +12 v in 3 analog +5 v in 4 analog +3.3 v in 5 analog +2.5 v in 6 analog +v ccp1 7 temperature reading low power and shutdown mode the adm9240 can be placed in a low power mode by se tting bit 0 of the configuration register to 0. this disa bles the inter- nal adc. full shutdown mode may then be achieved by setting bit 0 of the test register to 1. this turns off the analog output and stops the monitoring cycle, if running, but it does not affect the condition of any of the registers. the device w ill return to its previous state when this bit is reset to zero. rev. 2 | page 16 of 22 | www.onsemi.com the structure of the nand tree is shown in figure 1 3. beginning with a1 and working clockwise around the chip, eac h pin can be toggled and a resulting toggle can be ob served on ntest_out/a0. allow for a typical propagation delay of 500 ns. sda scl fan1 fan2 vid0 vid1 vid2 vid3 vid4 a1 ntes t_ou t figure 13. nand tree note: if any of the inputs shown in figure 9 are un used, they should not be connected directly to ground, but via a resistor su ch a s 10 k . this will allow the ate (automatic test equip- ment) to drive every input high so that the nand tr ee test can be properly carried out. using the adm9240 power-on reset when power is first applied, the adm 9240 perfo rm rm s s s s a a p p p ow ow ow er er er - on reset on several of its registers. registers wh ose p p p p ow ow ow ow er-on values are not shown have po wer-on conditi on on on on s s s s th th th th at at at at a a a a re re re re i i i nd nd nd nd et et et et er er er er - minate (this includes the value and limit re re re re re gi gi gi gi st st st er er er er s) s) s) s) . th th th th e e e ad ad ad ad c c c c is inactive. in most applications, usually t he he he he f f f f ir ir ir ir st st st st a ct ct ct ct io io io io n n n af af af af ter power-on would be to write limits in to to to to t t t t he he he he l l l l im im im it it it r r r r eg eg eg eg is is is te te te te rs rs rs rs . power-on reset clears or initializ es es es t t t he he he he f f f f ol ol ol ol lo lo lo wi wi wi ng ng ng ng r r r eg eg eg eg is is is is te te te te rs (the initialized values are shown in ta bl bl bl e e e vi vi vi : C configuration register C serial address register C interru pt (int) status re re re gi gi gi sters #1 #1 #1 #1 a a a a nd #2 C interru pt (int) m ask re re re re gi gi gi gi st st st er er er er s s s #1 #1 #1 a a a a nd #2 C vid /fan divisor register C vid4 register C chassis intrusion clear register C temperature configuration register C test register C compatibility register C analog output registe r in it ia li za ti on configuration register initialization performs a si milar , but not identical, function to p ower-on reset. the test re gi ster and anal og out pu t re gi ster are not initialized. configuration register initialization is accomplish ed by setting bit 7 of the configuration register high. t his bit auto- maticall y clears after bei ng set . using the configuration register control of the adm 9240 is provided through the configuration register. the adc is stopped upon power-up, and the int _c lear t si gn al is asserted, cleari ng the int out pu t. the confi gu ration t re gi ster is used to start and st op the adm 9240; enable or dis- able interrupt outputs and modes, and provide the i nitialization function described above. bit 0 of the configuration register controls the mo nitoring loop of the adm 9240. setting bit 0 low stops the monitoring loop and puts the adm 9240 into a low power mode thereby reduc - in g po wer consum pt ion. serial bus communication is still p os- sible with a ny r eg ister in the adm 9240 while in low po wer mode. setting bit 0 high starts the monitoring loop . bit 1 of the configuration register enables or disa bles the int interr up t ou tp ut. settin g bit 1 hi gh enables the int out pu t, settin g bit 1 low disables the out pu t. bit 3 of the configuration register is used to clea r the int interrupt output w he he he n n n set high. the adm9240 monitoring function will st op op op u u u nt nt nt il il b b b b it 3 is set low. interru pt status re gi ster contents w il l no no no t be be be a a a ff ff ff ec ec ec te te te te d. bit 4 of t he he he c c c on on on fi fi fi gu gu gu ra ra ra ra ti ti ti on on on r r r eg eg eg ister is used to initiate a mini- mu m 20 20 20 m m m s re re re se t t t s s s ig ig ig na na na l l l on the t t t reset output if the function t is e na na na bl bl bl ed ed ed b b b y y y bi bi bi t t t 7 in r r r eg eg eg ister 44 . bi bi bi t 6 6 6 of of of t t t he he he c on on on fi fi fi gu gu gu ration register is u u u u se se se se d d d d to to to to reset the chassis in in in tr tr tr us us us io io io n n n (c i) i) i) output pin when s et et et h h h h ig ig ig h. h. h. h. bi bi bi t t t 7 of of of t he he he c c c on on on figuration reg is is is te te te te r r r r is is is is u u u sed to start a configura- tion r r r eg eg eg is is is te te te r initiali za za za ti ti ti on on on w w w he he he he n n n n ta ta ta ta ke ke ke ke n n n n hi hi hi hi gh gh gh gh . st st st ar ar ar ti ng c on on on on ve ve ve rs rs rs rs io io io io n n n n th th th e monito ri ri ri ng ng ng ng f f f f un un un ct ct ct ct io io io n n n n (a (a (a (a na na na na lo lo lo lo g g g g in in in puts, temperature and fan sp eeds) in in in in t t t t he he he he he a a a a dm dm dm dm 92 92 92 92 40 40 40 i i i s s s s s st st st st ar ar ar ted by writi ng to the conf ig ura- tion r eg eg eg eg eg is is is is te te te te r r r an an an an d d d d se se se se tt tt tt in in in in g g g g st st st st ar ar ar t (bit 0), hi gh , int _enable (bit 1) t hi gh gh gh gh a a a a a nd nd nd nd nd in in in in t t t t _c _c _c _c le le le le ar ar ar ( ( ( ( bi bi bi bi t t t t 3) 3) 3) 3) low. apart from initially starting to to to ge ge ge ge th th th th er er er er , th th th th e e e e an an an al og og og m m m m ea ea surements and fan speed measurements pr pr pr oc oc oc ee ee ee ee d d d d in in in in de de de pe pe pe pe nd nd nd nd en en en en tl tl tl y and are not synchronized in any way. th th th th e e e e an an an an al al al al og og og m m m m ea ea ea ea surements will be co mp leted in no more than 35 35 35 35 3 3 3 3 s. s. s. t t t t he he he he t t t t ime taken to complete the fan speed measurements de pe pe pe pe nd nd nd s s s s on on on the fan speed and the number of tacho output pulse s pe pe pe pe r r r re re re re vo vo vo lution. on on on on on ce ce ce the measurements have been co mp leted, the results can b e re re re re ad from the value registers at any time. ta bl e iv s h ows the measurement sequence for the analog inputs. table iv. m easurement s eq uence measurement # parameter 1 analog +v ccp2 2 analog +12 v in 3 analog +5 v in 4 analog +3.3 v in 5 analog +2.5 v in 6 analog +v ccp1 7 temperature reading lo w po we r an d sh ut do wn m od e the adm9240 can be placed in a low power mode by se tting bit 0 of the configuration register to 0. this disa bles the inte r- nal adc. full shutdown mode may then be achieved by setting bit 0 of the test register to 1. this turns off the analog output and stops the monitoring cycle, if running, but it does not affect the condition of any of the registers. the device w ill return to its previous state when this bit is reset to zer o. adm9240 rev. 2 | page 16 of 22 | www.onsemi.com
adm9240 C17C rev. 0 + +12v sda scl serial bus +3.3v +3.3v +12v reset +3.3v +v ccp2 +12v in +5v in +3.3v in +2.5v in +v ccp1 vid0 vid1 vid2 vid3 vid4 from vid pins of processor ntest_out/a0 a1 ci fan1 fan2 gndd v cc int ntest_in/aout gnda 510 v adm9240 10 m f 0.1 m f 2n2219a +3.3v cmos backup battery 1n914 1n914 74hc132 470k v mrd901 100k v 10k v op295 10k v 82k v 510 v 510 v 510 v 510 v 510 v figure 14. application circuit application circuit figure 14 shows a generic application circuit using the ad9240. the analog monitoring inputs are connected to the power supplies including two processor core voltage inputs. the vid inputs are connected to the processor voltage i d pins. there are two tacho inputs from fans, and the analo g output is used to control the speed of a third fan. a chassis intrusion latch with an opto-sensor is connected to the ci in put. of course, in an actual application, every input and o utput may not be used, in which case unused analog and digital in puts should be tied to analog or digital ground as appropriate. rev. 2 | page 17 of 22 | www.onsemi.com adm9240 + +12v +12v +12v +12v +12v +12v sda sda sda sda sda sda scl scl scl scl seri seri seri seri seri al b al b al b al b al b us us us us us +3.3v +3.3v +12v reset +3.3 +3.3 +3.3 +3.3 +3.3 +3.3 v +v ccp2 +12v in +5v in +3.3v in +2.5v in +v ccp1 vid0 vid1 vid2 vid3 vid4 from vid pins of processor ntes ntes ntes ntes ntes t_ou t_ou t_ou t_ou t_ou t_ou t_ou t/a0 t/a0 t/a0 t/a0 t/a0 t/a0 a1 ci ci ci ci ci ci ci fan1 fan1 fan1 fan1 fan1 fan1 fan1 fan2 fan2 fan2 fan2 fan2 fan2 fan2 gndd gndd gndd gndd gndd gndd v cc int ntes t_in /aou t gnda 510 v adm 924 0 10 10 10 10 10 m m m m m f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 m f 2n2219a +3.3 +3.3 +3.3 +3.3 +3.3 +3.3 v v v v cmos backup battery 1n914 1n914 74hc132 470k v mrd901 100k 100k 100k 100k 100k 100k 100k v v v v v 10k v v v v v v v op295 10k v 82k v v v v v 510 v 510 v 510 v 510 v 510 v figure 14. application circuit application circui t figure 14 shows a generic application circuit using the ad9240. the analog monitoring inputs are connected to the power supplies including two processor core voltage inputs. the vid inputs are connected to the processor voltage i d pins. there are two tacho inputs from fans, and the analo g output is used to control the speed of a third fan. a chassis intrusion latch with an opto-sensor is connected to the ci in put. of course, in an actual application, every input and o utput may not be used, in which case unused analog and digital in puts should be tied to analog or digital ground as appropriate. rev. 2 | page 17 of 22 | www.onsemi.com
adm9240 C18C rev. 0 table v. address pointer register bit name r/ w description 7C0 address pointer write address of adm9240 registers . see the tables below for detail. table vi. list of registers notes address description power on value a7Ca0 (binary bit 7C0) 15h test register 0000 0000 setting bit 0 of this regi ster to 1 selects shutdown mode. caution : do not write to any other bits in this register. 19h programmed value of analog output 1111 1111 20h +2.5 v measured value indeterminate read only 21h +v ccp1 measured value indeterminate read only 22h +3.3 v measured value indeterminate read only 23h +5 v measured value indeterminate read only 24h +12 v measured value indeterminate read only 25h v ccp2 measured value indeterminate read only 26h reserved indeterminate 27h temperature reading indeterminate read only 28h fan1 reading indeterminate read only 29h fan2 reading indeterminate read only 2ah reserved indeterminate 2bh +2.5 v high limit indeterminate 2ch +2.5 v low limit indeterminate 2dh +v ccp1 high limit indeterminate 2eh +v ccp1 low limit indeterminate 2fh +3.3 v high limit indeterminate 30h +3.3 v low limit indeterminate 31h +5 v high limit indeterminate 32h +5 v low limit indeterminate 33h +12 v high limit indeterminate 34h +12v low limit indeterminate 35h v ccp2 high limit indeterminate 36h v ccp2 low limit indeterminate 37h reserved indeterminate 38h reserved indeterminate 39h hot temperature limit (high) indeterminate 3ah hot temperature hysteresis limit (low) indetermin ate 3bh fan1 fan count limit indeterminate 3ch fan2 fan count limit indeterminate 3dh reserved indeterminate 3eh company id number 0010 0011 this location will con tain the company identification number (read only). 3fh revision number die revision this location will co ntain the revision number of the part. (read only). 40h configuration register 0000 1000 see table vii 41h interrupt int status register 1 0000 0000 see table viii 42h interrupt int status register 2 0000 0000 see table ix 43h int mask register 1 0000 0000 see table x 44h int mask register 2 0000 0000 see table xi 45h compatibility register 0000 0000 see table xii 46h chassis intrusion clear register 0000 0000 see tab le xiii 47h vid0C3/fan divisor register 0101 (vid3Cvid0) see t able xiv 48h serial address register 0010 11(a1)(a0) see table xv 49h vid4 register 1000 000(vid4) see table xvi 4bh temperature configuration register 0000 0001 see t able xvii rev. 2 | page 18 of 22 | www.onsemi.com table v. address pointer re gi ster bit name r/ w bit name r / bit name r / description 7C0 address pointer write address of adm9240 registers . see the tables below for detail. table vi. list of registers notes address description power on value a7Ca0 (binary bit 7C0) 15h test register 0000 000 0 s 0 s 0 s et et et ting bit 0 of this register to 1 selects sh sh sh ut ut ut down mode. caution : do not write to an an an y y y ot ot ot ot her bits in this register. 19h programmed value of analog output 1111 1111 20h +2.5 v measured value indeterminat e r e r e r e r ea ea ea ea d d d on on on ly ly ly 21h +v ccp1 m easured value indeterminate re re re ad ad ad o o o nl y 22h +3.3 v measured value indetermin at at at e r e r e r ea ea ea d d d only 23h +5 v measured value indete rm rm rm in in in at at at e r e r e r ead only 24h +12 v m easured value indet er er er mi mi mi na na na te te te read onl y 25h v ccp2 m easured value indeter mi mi mi na te te te read onl y 26h reserve d i d i d i nd nd nd etermi na na na te te te 27h temperature reading in in in de de de terminat e r e r e r e r ea ea ea ea d d d on on on on ly ly ly ly 28h fan1 readin g i g i g i g i g i nd nd nd et er er er mi mi na na na te te te re re re ad ad ad o o o o nl nl nl nl y y y 29h fan2 readin g i g i g i g i nd nd nd nd et et et er er er mi mi mi na na na te te te re re re re ad ad ad ad o o o o nl nl nl y y y 2ah reserve d i d i d i d i nd nd nd nd et et et et er mi mi mi na te 2bh +2.5 v high limit in in in in de de de te te te te rminat e 2ch +2.5 v low limi t i t i t i t i nd nd nd nd et et et et ermina te 2dh +v ccp1 high limi t i t i t i t i t i nd nd nd nd etermi na na na na te te te te te 2e h + v ccp1 l ow l im it in de te rm rm rm in in in in at at at at e e e e 2fh +3.3 v high limit inde te te te te rm rm rm rm in in in at at at e e e 30h +3.3 v low limi t i t i t i t i nd nd nd et et et et er er er er mi mi mi na na na na te te te te 31h +5 v hi gh limit in in in in de de de te te te rm rm rm rm in in in in at at at at e e e e 32h +5 v low li mi mi mi mi t i t i t i t i nd nd nd nd et et et et er er er er mi mi mi na na na te te te 33h +12 v high li li li li mi mi mi mi t i t i t i t i t i nd nd nd nd et et et et er er er er mi mi mi na na na na te te te te 34 h + 12 v lo w li li li mi mi mi mi t i t i t i t i nd nd nd nd et et et er er er er mi mi mi mi na na na na na te te te 35h v ccp2 high li li li li mi mi mi mi t i t i t i t i nd nd nd et et et et er er er er mi mi mi mi na te 36h v ccp2 low lim it it it it in in in in in de de de de te te te te rm rm rm inat e 37h reserve d i d i d i d i nd nd nd nd et et et ermina te 38h reserve d i d i d i d i nd nd nd nd etermina te 39h hot temperature limit (high ) i ) i ) i ) i ndetermina te 3ah hot temperature hysteresis li li li mi mi mi mi t t t t (l (l (l ow ow ow ow ) i ) i ) i ) i ndeterminate 3b h f an 1 fa n co un t li mi t i t i t i t i nd et er mi na te 3ch fan2 fan count limi t i t i t i ndetermina te 3dh reserved indetermina te 3eh company id number 0010 0011 this location will con tain the company identification number (read only). 3f h r ev is io n nu mb er di e re vi si on th is l oc at io n wi ll c on ta in t he r ev is io n number of the part. (read only). 40h configuration register 0000 1000 see table vii 41h interrupt int status register 1 0000 0000 see table viii 42h interrupt int status register 2 0000 0000 see table ix 43h int m ask register 1 0000 0000 see table x t 44 h int m ask register 2 0000 0000 see table xi t 45h compatibility register 0000 0000 see table xi i 46h chassis intrusion clear r eg ister 0000 0000 see table xiii 47h vid0C3/fan divisor re gi ster 0101 (vid3Cvid0) see table xiv 48h serial address register 0010 11(a1)(a0) see table xv 49h vid4 register 1000 000(vid4) see table xvi 4bh temperature configuration register 0000 0001 see t able xv ii adm9240 rev. 2 | page 18 of 22 | www.onsemi.com
adm9240 C19C rev. 0 table vii. register 40h, configuration register (power-on default = 08h) bit name r/ w description 0 start r/ w logic 1 enables startup of adm9240, logic 0 places it in standby mode. caution: the out- puts of the interrupt pins will not be cleared if t he user writes a zero to this location after an interrupt has occurred (see int _clear bit). at startup, limit checking functions and scan- ning begins. note, all high and low limits should b e set into the adm9240 prior to turning on this bit. (power-up default = 0.) 1 int _enable r/ w logic 1 enables the int output. 1 = enabled 0 = disabled (power-up default = 0). 2 reserved default = 0. 3 int _clear r/ w during interrupt service routine (isr) this bit is asserted logic 1 to clear int output without affecting the contents of the interrupt sta tus register. the device will stop monitor- ing. it will resume upon clearing of this bit. (pow er-up default = 1.) 4 reset r/ w creates a reset (active low) signal for 20 ms minimum (power-up de fault = 0). this bit is cleared once the pulse goes active. 5 reserved r/ w default = 0. 6 ci_reset r/ w a 1 outputs a minimum 20 ms active low pulse on t he chassis intrusion pin. (power-up default = 0.) (note: this bit performs the same fun ction as bit 7 in register 46h). 7 initialization r/ w logic 1 restores power-up default values to the con figuration register, interrupt status regis- ters, interrupt mask registers, fan divisor registe r and the temperature configuration register. this bit automatically clears itself sinc e the power-on default is zero. table viii. register 41h, interrupt status register 1 (power-on default = 00h) bit name r/ w description 0 +2.5 v_error read only a 1 indicates a high or low limit has been exceeded. 1 v ccp _error read only a 1 indicates a high or low limit has been exceeded. 2 +3.3 v_error read only a 1 indicates a high or low limit has been exceeded. 3 +5 v_error read only a 1 indicates a high or low l imit has been exceeded. 4 temp_error read only a 1 indicates that a temperat ure interrupt has been set. 5 reserved read only undefined. 6 fan1_error read only a 1 indicates that a fan coun t limit has been exceeded. 7 fan2_error read only a 1 indicates that a fan coun t limit has been exceeded. table ix. register 42h, interupt status register 2 (power-on default = 00h) bit name r/ w description 0 +12 v_error read only a 1 indicates a high or low limit has been exceeded. 1 v ccp2 _error read only a 1 indicates a high or low limit has been exceeded. 2 reserved read only undefined. 3 reserved read only undefined. 4 chassis_error read only a 1 indicates chassis intr usion has gone high. 5 reserved read only undefined. 6 reserved read only undefined. 7 reserved read only undefined. note: any time the status register is read out, the cond itions (i.e., register) that are read are automatic ally reset. in the case of the channel priority ind ication, if two or more channels were out of limits, another in dication would automatically be generated if it wer e not handled during the isr. in the mask register, the errant voltage interrupt may be disabled until the operato r has time to clear the errant condition or set the limit higher/lower. rev. 2 | page 19 of 22 | www.onsemi.com adm9240 table vii. register 40h, configuration register (power-on default = 08h) bit name r/ w bit name r / bit name r / description 0 start r/ w 0 start r/ 0 start r/ logic 1 enables startup of adm 9240, logic 0 places it in standby mode. caution: t he out- puts of the interrupt pins will not be cleared if t he user writes a zero to this location after an interrupt has occurred (see int _clear bit). at startup, limit checking functions and scan- t ning begins. note, all high and low limits should b e set into the adm9240 prior to turning on this bit. (power-up default = 0.) 1 int _enable r/ t w _enable r / _enable r / logic 1 enables the int output. 1 = enabled 0 = disabled (power-up default = 0). t 2 reserved default = 0 . 3 int _clear r/ t w _clear r/ _clear r/ during interrupt service routine (isr) this bi bi bi t t t is is is asserted logic 1 to clear int output t without affecting the contents of the inte rr rr rr up up up t t t st st st at at at at us register. the device will stop monitor- ing. it will resume upon clearing of thi s s bi bi bi t. ( ( ( po po po we we we r- r- r- up up up up default = 1.) 4 reset r/ w r/ r/ creates a reset (active low) si gn gn gn al al al f f f or or or 2 2 2 0 0 0 ms ms ms ms m in in in im im im um um um (power-up default = 0). t this bit is cleared once the pul se se se g g g oe oe s ac ac ac tive. 5 reserved r/ w 5 reserved r / 5 reserved r / default = 0. 6 ci_reset r/ w 6 ci_reset r / 6 ci_reset r / a 1 outputs a minimu m m m 20 20 20 m m m s ac ac ac tive l l l ow ow ow p p p ul ul se on the chas si si si s s s s in in in in tr tr tr tr usion pin. (power-up default = 0.) (note: t hi hi hi s s s bi bi bi t t t pe pe pe rf rf rf or or or ms t t he same function as bi bi bi bi t t t 7 7 7 7 in in in in register 46h) . 7 initialization r/ w 7 initialization r / 7 initialization r / logic 1 restores power-up de de de fa ul ul ul t va va va lu lu lu es es es to the configur at at at io io io io n n n n re re re re gister, interrupt status regis- ters, interrupt ma ma ma sk sk sk r r r egisters, fa fa fa n di di di visor re gi gi gi st st st er a nd nd nd nd t t t t he he he he t t t t em em em em pe pe pe pe rature configurati on register. this bit a a a ut ut ut om om om atic al al ly ly ly c c c le le le ars itself s s s in in in in ce ce ce t t t he he he p p p p ow ow ow ow er er er -o -o -o -o n n n n de de de de fault is zero. table viii. register 41 41 41 41 h, h, h, i i i i nter ru ru ru ru pt pt pt s s s s ta ta ta tu tu tu s regist er er er er 1 1 1 1 ( ( ( ( po po po po we we we we r- r- r- r- on on on on d d d d ef ef ef ef au au au au lt = 00h) bit name r/ w bit name r / bit name r / de de de de sc sc sc sc ri ri ri ri pt pt pt pt io io io io io n n n 0 +2.5 v_error read only a a a a a 1 1 1 1 in in in in di ca ca ca te te te te s a hi hi gh or lo w w w li li li li mi mi mi mi mi t ha ha ha ha s s s s be be be be en en en e e e e xc xc xc xc ee ee ee ee ded. 1 v ccp _error read onl y a y a y a y a 1 1 1 1 i i i i nd nd nd nd ic ic ic ic at es es es a high or l l l ow ow ow ow l l l im im im im it it it it h h h h as as as as b b b b ee ee ee ee n n n n ex ex ex ex ceeded. 2 +3.3 v_error read on on on ly ly ly a a a a 1 in in in in di di di di ca ca ca ca te te te te s a hi gh gh gh gh o o o o r r r lo lo lo lo w w w li li li mi mi mi t t t ha ha ha ha s s s be be be be en en en en exceeded. 3 +5 v_error read on on on ly ly ly ly a a a a 1 1 1 1 in in in in di di di di cates a hi hi hi gh gh gh gh o o o o r r r r lo lo lo w w w w li li li li mi mi mi mi t ha ha ha s s s be be be be en exceeded. 4 temp_error r ea ea d d on on on ly ly ly a 1 1 1 1 indicates th th th th at at at at a a a t t t t em em em em pe pe pe pe ra ra ra tu tu tu re re re re i i i i nt nt nt nt errupt has been set. 5 reserve d r d r d r d r ea ea ea ea d d d d on on on on ly ly ly un un un de de de de fined. 6 fan1_erro r r r r r r r r ead on on on on ly ly ly ly a a a 1 indi ca ca ca te te te te s s s th th th th at at at a a a a f f f f an an an an c c c ou ou ou ou nt nt nt nt l l l im im it has been exceeded. 7 fan2_erro r r r r r r r r ea ea ea d on on on on ly ly ly ly a 1 in in in di di di ca ca ca te te te s th th th th at at at a a a a f f f an an an an c c c c ou ou ou ou ou nt limit has been exceeded. ta ta ta bl bl bl e ix. register 42 h, h, h, i i i i nt nt nt nt er er er up up up up t t t t st st st st at at us register 2 (power-on default = 00h) bit name r/ w bit name r / bit name r / de sc sc sc ri ri ri ri pt pt pt pt io io io n n n n 0 +12 v_error read onl y a y a y a 1 1 1 1 i nd nd nd nd ic ic ic ic ic at at at at es es es a high or low limit has been exceeded. 1 v ccp2 _error read onl y a y a y a y a 1 i nd nd nd ic ic ic ates a h ig h or low limit has been exceeded. 2 reserved read on ly undefined. 3 reserved read only undefined. 4 chassis_error read only a 1 indicates chassis intr usion has gone high. 5 reserved read only undefined. 6 reserved read only undefined. 7 reserved read only undefined. note: any time the status register is read out, the cond itions (i.e., register) that are read are automatic ally reset. in the case o f the channel priority indication, if two or more channels were out of limits, another in dication would automatically be generated if it wer e not handled during the isr. in the mask register, the errant voltage interrupt may be disabled until the operato r has time to clear the errant condition or set the limit higher/lower. rev. 2 | page 19 of 22 | www.onsemi.com
adm9240 C20C rev. 0 table x. register 43h, int interrupt mask register 1 (power-on default = 00h) bit name r/ w description 0 +2.5 v read/ write a 1 disables the corresponding interrupt status b it for int interrupt. 1 +v ccp1 read/ write a 1 disables the corresponding interrupt status b it for int interrupt. 2 +3.3 v read/ write a 1 disables the corresponding interrupt status b it for int interrupt. 3 +5 v read/ write a 1 disables the corresponding interrupt status b it for int interrupt. 4 temp read/ write a 1 disables the corresponding interrupt status b it for int interrupt. 5 reserved read/ write power-on default = 0. 6 fan1 read/ write a 1 disables the corresponding interrupt status b it for int interrupt. 7 fan2 read/ write a 1 disables the corresponding interrupt status b it for int interrupt. table xi. register 44h, int mask register 2 (power-on default = 00h) bit name r/ w description 0 +12 v read/ write a 1 disables the corresponding interrupt status b it for int interrupt. 1 v ccp2 read/ write a 1 disables the corresponding interrupt status b it for int interrupt. 2 reserved read/ write power-up default set to low. 3 reserved read/ write power-up default set to low. 4 ci read/ write a 1 disables the corresponding interrupt status b it for int interrupt. 5 reserved read/ write undefined. 6 reserved read/ write undefined. 7 reset enable read/ write a 1 enables the reset function in the configuration register. table xii. register 45h, reserved compatibility (power-on default = 00h) bit name r/ w description 0C7 reserved read/ write reserved for compatibility. table xiii. register 46h, chassis intrusion clear (power-on default = 00h) bit name r/ w description 0C6 reserved read/ write undefined (power on default = 00h) 7 chassis int. clear read/ write a 1 outputs a minimum 20 ms active low pulse on t he chassis intrusion pin. the register bit clears itself after the pulse has been output. table xiv. register 47h, vid0C3/fan divisor register (power-on default 0101(vid3Cvid0)) bit name r/ w description 0C3 vid read the vid[3:0] inputs from processor core p ower supplies to indicate the operating voltage (e.g., 1.3 v to 3.5 v). 4C5 fan1 divisor read/ write sets counter prescaler for fan1 speed measurement <5:4> = 00 C divide by 1 <5:4> = 01 C divide by 2 <5:4> = 10 C divide by 4 <5:4> = 11 C divide by 8 6C7 fan2 divisor read/ write sets counter prescaler for fan2 speed measurement <7:6> = 00 C divide by 1 <7:6> = 01 C divide by 2 <7:6> = 10 C divide by 4 <7:6> = 11 C divide by 8 rev. 2 | page 20 of 22 | www.onsemi.com table x. register 43h, int interrupt m ask register 1 (power-on default = 00h) t bit name r/ w bit name r / bit name r / descriptio n 0 +2.5 v read/ write 0 +2.5 v rea d/ 0 +2.5 v rea d/ a 1 disables the corresponding interrupt status b it for int interrupt . 1 + v ccp1 read/ write read / read / a 1 disables the corresponding interrupt status b it for int interrupt . 2 +3.3 v read/ write 2 +3.3 v rea d/ 2 +3.3 v rea d/ a 1 disables the corresponding interrupt status b it for int interrupt . 3 + 5 v r ea d/ write 3 +5 v rea d/ 3 +5 v rea d/ a 1 disables the corresponding interrupt status b it for int interrupt . 4 temp read/ write 4 temp rea d/ 4 temp rea d/ a 1 disables the corresponding interrupt status b it for int interrupt . 5 reserved read/ write 5 reserved rea d/ 5 reserved rea d/ power-on default = 0. 6 fan1 read/ write 6 fan1 rea d/ 6 fan1 rea d/ a 1 disables the corre sp ondi ng interru pt status bit for int interru pt . 7 fan2 read/ write 7 fan2 rea d/ 7 fan2 rea d/ a 1 disables the correspondi ng ng ng interrupt status bit for int interrupt . table xi. register 44h, int m ask register 2 (po we we r- r- r- on on on d d d ef ef ef au au au lt = = = 00h) bit name r/ w bit name r / bit name r / descriptio n 0 + 12 v re ad / write 0 +12 v read / 0 +12 v read / a 1 disables t t t he he he c c c or or re re re sp sp sp on on on ding i i i nt nt nt errupt status bit fo fo fo fo r int interrupt . 1 v ccp2 read/ write read / read / a 1 disa bl bl es es es t t t he he he c c orre sp sp sp on on on di di di ng ng ng interru pt status bi bi bi bi t t t t fo fo fo fo r r r r int interru pt . 2 reserved read/ write 2 reserved rea d/ 2 reserved rea d/ power- up d d d ef ef ef au au au lt lt lt s s s et et et t t t t o lo w. w. w. 3 reserved read/ write 3 reserved rea d/ 3 reserved rea d/ power-up d d d ef ef ef au au au au lt lt lt s s s et et et t t o o o lo lo lo w. 4 ci read/ write 4 ci rea d/ 4 ci rea d/ a 1 1 1 disabl es es es t t t he he he c c c or or or re re re sp sp sp ondi ng ng i i i nt nt erru pt pt pt pt s s s s ta ta ta ta tu tu tu tu s bi bi bi t for int interrupt . 5 r es er ve d r ea d/ write 5 reserved rea d/ 5 reserved rea d/ un un un de de de fi fi fi ne ne ne d. 6 reserved read/ write 6 reserved rea d/ 6 reserved rea d/ un un un un de de de fi fi fi ne ne ne d. d. d. 7 reset enable read/ t write enable rea d/ enable rea d/ a a a a 1 1 1 1 en en en ab ab ab le le le s th th th e rese t t t f f f f un un un un ct ct ct ct io io io io n n n n in in in in t t t he he he c c c c on on on on fi fi fi fi guration register. t t table xii. regi st st er er er er 4 4 4 4 5h 5h 5h 5h , re re re re re se se se rv ed ed ed c c c c om om om om patibi li li ty ty ty ty ty ( ( ( ( po po po po we we we we r- r- r- r- on on on on d d d d ef ef ef ef au au au au lt lt lt = 00h) bit name r/ w bit name r / bit name r / de de de de scriptio n 0C7 reserve d r d r d r d r ea d/ d/ d/ d/ wr wr wr wr it it it it e e e e 0C7 reserved rea d/ 0C7 reserved rea d/ reserved f f f f or or or or c c c om om om om pa pa pa pa ti ti ti ti bi bi bi li li li ty ty ty ty . . ta ta ta ta bl bl bl e e e xi xi xi xi ii ii ii . r . r . r eg eg eg is is is te te te te r r 46h, c ha ha ha ha ss ss ss is is is i i i i nt nt nt ru ru ru ru si si si si on on c c c c le le le ar ar ar ar ( ( ( power-on default = 00h ) bit nam e r e r e r e r / w w w bit name r / bit name r / de de de sc sc sc ri ri ri ri pt pt pt pt io io io io n n n n 0C6 reserve d r d r d r d r ead/ write 0C6 reserved rea d/ 0C6 reserved rea d/ un un un un de de de de fi fi fi ne ne ne ne d d d d (p (p (p (p ower on default = 00 h) 7 chassis int. clea r r r r r r r r ead/ write 7 chassis int. clear rea d/ 7 chassis int. clear rea d/ a a a a a 1 1 1 1 ou ou ou ou tp tp uts a minimum 20 ms active low pulse on the chassis intrusion pi pi pi pi n. n. n. t t t t he register bit clears itself after the pulse has b een output. table xiv. register 47h, vi vi vi vi d0 d0 d0 d0 C3 C3 C3 /f /f /f /f /f an an an an d d d ivisor register (power-on default 0101(vid3Cvid0)) bi t n am e r / / / w w w bit name r / / / bit name r / / / descriptio n 0C3 vid read the vid[3:0] inputs from processor core p ower supplies to indicate the operating voltage (e.g., 1.3 v to 3.5 v). 4C5 fan1 divisor read/ write 4C5 fan1 divisor rea d/ 4C5 fan1 divisor rea d/ sets counter prescaler for fan1 speed measurement <5:4> = 00 C divide by 1 <5:4> = 01 C divide by 2 <5:4> = 10 C divide by 4 <5:4> = 11 C divide by 8 6C7 fan2 divisor read/ write 6C7 fan2 divisor rea d/ 6C7 fan2 divisor rea d/ sets counter prescaler for fan2 speed measurement <7:6> = 00 C divide by 1 <7:6> = 01 C divide by 2 <7:6> = 10 C divide by 4 <7:6> = 11 C divide by 8 adm9240 rev. 2 | page 20 of 22 | www.onsemi.com
adm9240 C21C rev. 0 table xv. register 48h, serial address register (power-on default = 0010 11(a1)(a0)) bit name r/ w description 0C6 serial bus address read/ write serial bus address (bits 0 and 1 are set by a0, a1 and bit 7 is read only) table xvi. register 49h, vid 4/device id register (power-on default 1000000(vid4)) bit name r/ w description 0 vid4 read vid4 input from pentium ? 1C7 reserved read/ write table xvii. register 4bh, temperature configuration register (power-on default = 01h) bit name r/ w description 0C1 hot temperature read/ write if bit 0 and bit 1 of this register are both zero o r one, this selects the default interrupt mode interrupt mode, which gives the user an interrupt if the temperature goes above select bits the hot limit. the interrupt will be cle ared once the status register is read, but it will again be generated when the next conversion ha s completed. it will continue to do so until the temperature goes below the hysteres is limit. a 0 on bit 1 and a 1 on bit 0 selects the one-time interrupt mode, which gives the user an interrupt when the temperature goes above t he hot limit. the interrupt will be cleared once the status register is read. anothe r interrupt will not be generated until the temperature first goes below the hysteres is limit. no more interrupts will be generated until the temperature again goes above the hot limit. the correspond- ing bit will be cleared in the status register ever y time it is read, but may not set again when the next conversion is done. note that this is the power-up default mode. a 1 on bit 1 and a 0 on bit 0 selects the comparato r mode. this gives an int when the temperature exceeds the hot limit. this int remains active until the temperature goes below the hot limit (no hysteresis ), when the int will become inactive. 2C6 reserved read/ write default = 00000 7 temp read only lsb of temperature reading = 0.5 c pentium is a registered trademark of intel corp. rev. 2 | page 21 of 22 | www.onsemi.com adm9240 table xv. register 48h, serial address register (power-on default = 0010 11(a1)(a0)) bi t n am e r / w bit name r / bit name r / description 0C6 serial bus address read/ write 0C6 serial bus address rea d/ 0C6 serial bus address rea d/ serial bus address (bits 0 and 1 are set by a0, a1 and bit 7 is read only) table xvi. register 49h, vid 4/device id register (power-on default 1000000(vid4)) bit name r / w bit name r / bit name r / description 0 vid4 read vid4 input from pentium ? 1C7 reserved read/ write 1C7 reserved rea d/ 1C7 reserved rea d/ table xvii. register 4bh, temperature configuration re re re gi gi gi st st er er er ( ( ( po po po we we we r- r- r- r- on on on default = 01h) bit name r / w bit name r / bit name r / description 0C1 hot temperature read/ write 0C1 hot temperature read / 0C1 hot temperature read / if bit 0 and bit 1 o f f f th th th is is is r r r eg is is is te te te r r r ar ar ar e bo bo bo th th th zero or one, th is is is is s s s s elects the default interrupt mode interrupt mode, wh wh wh ic ic ic h h h gi gi gi ves th th th e e e us us er er er an interrupt if t he he he he t t t t em em em em pe pe pe pe rature goes above select bits the hot limit. th th th e in in in te te te rr rr rr up up up up t will b b b e e e cleared once the s s s ta ta ta ta tu tu tu tu s s s re gi ster is read, but it will a ga in be ge ne ne ne ra te te te te d d d wh wh wh en en en t t t he he he next conversi on on on h h h h as as as as c c c om om om pl eted. it will continue to do so un un un ti ti ti l the te mp mp mp er er er at at at ur ur ur e e e go go go es bel ow ow ow t t t he h ys ys ys ys te te te te re re re re si si si si s li li li mi mi mi mi t. a 0 on b b b it it it 1 1 1 a a a nd a 1 o o o n n n bi bi bi t 0 sele ct ct ct ct s s s s th th th th e e e on on on e- e- e- e- ti ti ti me me me i i i i nt nt nt nt nt er er er er ru ru ru ru pt mode, which g ives t he us us us us er er er er a a a a a n n n n in in in in te te te rr rr rr up up up t wh wh wh en en en the tem pe pe pe pe ra ra ra tu tu tu re re g g g g oe oe oe oe s s s s ab ab ab ov ov ov ov e e e th th th th e e hot limit. the interrupt will be be be be c c c c le le le le ar ar ar ar ed ed ed ed o o o o nc nc nc e e e th th th e e e st st atus r eg eg eg eg is is is is is te te te te te r r r r is is is is r r r ea ea ea ea d. d. d. d. a a a no no no th th th th er er er er i i i i nterrupt will not be generated un un un til the te te te te mp mp mp mp er er er at at at ure first go go go go es es es es es b b b b el el el ow ow ow ow t t t t he he he h h h h ys ys ys ys te te te te re re re re sis limit. no more interrupts will be be be be g g g g en en en er at at at at ed ed ed ed u u ntil the t t t em em em em em pe pe pe pe ra ra ra ra tu tu tu tu re re re re a a a a ga ga ga in in in in g g g g oe oe oe oe s s s above the hot limit. the correspond- in in in g g g g bi bi bi bi t t t t wi wi wi wi ll ll ll b b b e cleare d d d in in in in t t t t he he he he s s s ta ta ta ta tu tu tu tu s s s s re re re re gi gi gi gi st st st st er er er er e e e e very time it is read, but may not set ag ag ag ag ai ai ai ai n wh wh wh wh en the n ex ex ex t t t t co co co co co nv nv er er er er si si si si on on on on i i i s s do do do do ne ne ne ne . note that this is the power-up default mo mo mo de de de . a a a a 1 1 1 1 on bit 1 1 1 1 a a a a nd nd nd nd a a a a 0 0 0 o o o n n n n bi bi bi t t t 0 0 0 0 0 se se se se le le le le cts the comparator mode. this gives an int a 1 on bit 1 and a 0 on bit 0 selects the comparato r mode. this gives an a 1 on bit 1 and a 0 on bit 0 selects the comparato r mode. this gives an when t he he he t t t em em em em pe pe pe pe ra ra ra tu tu tu tu re re re re e xc xc xc xc ee ee ee ds ds ds ds the hot limit. this int remains active until the t temp er er er at at at at ur ur ur ur e e e go go go es es es es b b b b el ow ow ow ow t t t he he he h h h ot limit (no hysteresis), when the int will become t in ac ac ac ac ti ti ti ti ve ve ve ve . 2C6 reserve d r d r d r d r ea ea ea ea d/ d/ wr wr wr ite 2C6 reserved rea d/ d/ 2C6 reserved rea d/ d/ de de de fa fa fa ul ul ul ul t = = = = 00 00 00 00 00 00 00 00 0 0 0 7 tem p r p r p r p r ea ea ea ea d only ls ls ls b b b of of of of t t t em em em pe pe pe pe ra ra ra ra tu tu tu tu re re reading = 0.5 c rev. 2 | page 21 of 22 | www.onsemi.com
adm9240 C22C rev. 0 24-lead tssop (ru-24) 24 13 12 1 0.311 (7.90) 0.303 (7.70) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 outline dimensions dimensions shown in inches and (mm). c3295C8C3/98 printed in u.s.a. model temperature range package description package option adm9240aru -40c to +125c 24-lead tssop ru-24 ADM9240ARU-REEL -40c to +125c 24-lead tssop ru-24 ADM9240ARU-REEL7 -40c to +125c 24-lead tssop ru-24 adm9240aruz 1 -40c to +125c 24-lead tssop ru-24 adm9240aruz-reel 1 -40c to +125c 24-lead tssop ru-24 adm9240aruz-r7 1 -40c to +125c 24-lead tssop ru-24 1 z = pb-free part on semiconductor and the on logo are registered trademarks o f semiconductor components industries, llc (scillc). scil lc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suita bility of its products for any particular purpose, nor doe s scillc assume any liability arising out of the applicati on or use of any product or circuit, and speci? cally discl aims any and all liability, including without limitation special, c onsequential or incidental damages. ?typical? parameter s which may be provided in scillc data sheets and/or speci? cations can and do vary in different applications and actua l performance may vary over time. all operating parameter s, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc do es not convey any license under its patent rights nor the ri ghts of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surg ical implant into the body, or other applications intended t o support or sustain life, or for any other application in which the failure of the scillc product could create a situat ion where personal injury or death may occur. should buye r purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of? cers, employees, subsidiaries, af? liates, and distributors harmless against all claims, cos ts, damages, and expenses, and reasonable attorney fees ar ising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized us e, even if such claim alleges that scillc was negligent regar ding the design or manufacture of the part. scillc is an equal opportunity/af? rmative action employer. this literature is subject to all applicable copyright laws and is not for resal e in any manner. literature fulfillment: literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303-675-2175 or 800-344-3860 toll free usa/canada fax : 303-675-2176 or 800-344-3867 toll free usa/canada email : orderlit@onsemi.com n. american technical support : 800-282-9855 toll free usa/canada. europe, middle east and africa technical support : phone: 421 33 790 2910 japan customer focus cente r phone: 81-3-5773-3850 on semiconductor website: www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative publication ordering information ordering guide rev. 2 | page 22 of 22 | www.onsemi.com 24-lead tssop (ru-24) 24 13 12 1 0.311 (7.90) 0.303 (7.70) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 seating plan e 0.006 (0.15) 0.00 2 (0 .05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.00 0.00 0.00 0.00 0.00 0.00 79 ( 79 ( 79 ( 79 ( 0.20 0.20 ) 0.00 0.00 0.00 0.00 35 ( 35 ( 35 ( 35 ( 0.09 0.09 0.09 0.09 0.09 0) 0.02 0.02 0.02 0.02 0.02 8 (0 .70) .70) .70) .70) .70) 0.02 0.02 0.02 0.02 0 (0.50) 8 8 8 0 outline dimensions dimensions shown in inches and (mm). adm9240 mo de l te te te te te mp mp mp mp mp mp mp er er er at at at at at ur ur ur ur e range pa pa pa pa pa ck ck ck ck ck ck ag ag ag ag ag ag e e e e e e e de de de de de de de sc sc sc sc sc sc ri ri ri ri ri ri pt pt pt pt pt pt pt io io io io io io n n n n n n package option adm9240aru -4 -4 -4 0 0 0 0 0 0 c c c c c to + + + + + + 12 12 12 12 12 12 12 5 c 24 24 24 24 24 24 24 -l -l -l -l -l -l -l ea ea ea ea ea d d d d d ts ts ts ts ts ts ts so so so so so so so p ru-24 adm9240a ru ru ru ru -r -r -r -r -r -r ee ee ee ee ee l l l l l l l -4 -4 -4 -4 -4 -4 0 0 0 0 0 0 c c c c c c to +125 c 24 24 24 24 24 24 24 -l -l -l -l ea ea ea ea ea ea d d d d d ts ts ts ts ts ts sop ru-24 adm9 24 24 24 24 24 24 24 0a 0a 0a 0a ru ru ru -r -r -r -r -r -r -r ee ee ee ee ee ee l7 l7 l7 l7 -4 -4 -4 -4 0 0 0 0 0 0 c to +12 5 5 5 5 5 5 c c c c c 24 24 24 24 24 24 24 -l -l -l -l -l -l -l ea ea ea ea ea d tssop ru-24 ad m9 m9 m9 m9 m9 m9 24 24 24 24 24 24 24 0a ru z z z z z z z 1 -4 0 c to + + + + + + + 12 12 12 12 12 12 12 5 5 5 5 5 5 c c c c c c c 24 24 24 24 24 24 24 -l ea d ts so p ru -2 4 ad m9 m9 m9 m9 m9 m9 24 24 24 24 24 24 24 0a 0a 0a 0a 0a 0a 0a ru z- z- z- z- z- z- re re re re re re el el el el el el el 1 -40c to to to to to to to + + + + + + + 12 12 12 12 12 12 5 5 5 5 5 c c c c c c c 24-lead tssop ru-24 adm924 0a 0a 0a 0a 0a 0a 0a ru ru ru ru ru ru z- z- z- z- z- z- z- r7 r7 r7 r7 r7 r7 r7 1 -40c to + + + + + + 12 12 12 12 12 12 12 5 5 5 5 5 5 5 c c c c c c c 24-lead tssop ru-24 1 z = pb-free part on semiconductor and the on logo are registered tradem arks of semiconductor components industries, llc (scillc) . scillc reserves the right to make changes without furth er notice to any products herein. scillc makes no warr anty , re pres entation or guar antee re gard ing the suitabil ity of i ts p roducts for any part icul ar p urpo se, nor does scillc assume a ny l iabi lity ari sing out of the appl ication or use of an y pr oduct or circuit , an d sp eci? cal ly d isclaims any and all liability, including without limitation special , consequential or incidental damages. ?typical? para meters which may be provided in scillc data sheets and/o r speci? cations can and do vary in different applicatio ns and actual performance may vary over time. all operating paramete rs, including ?typicals? must be validated for each custo mer application by customer?s technical experts. scill c does not convey any license under its patent rights no r the rights of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for sur gical implant into the body, or other applications inten ded to support or sustain life, or for any other applicati on in which the failure of the scillc product could create a situ ation where personal injury or death may occur. should b uyer purchase or use scillc products for any such unin tended or unauthorized application, buyer shall indemni fy and hold scillc and its of? cers , em ploy ees, subsidiarie s, a f? liate s, a nd distributors harmless aga inst all cla ims, cos ts, dama ges, and exp ense s, a nd reasonable attorn ey f ees aris ing out of, dire ctly or indirect ly, any claim of per sonal in jury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglige nt regarding the design or manufacture of the part. scillc i s an equal opportunity/af? rmative action employer. th is literature is subject to all applicable copyright laws and is not for re sale in any manner. lit era tur e f ulf ill men t: literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303-675-2175 or 800-344-3860 toll free usa/canada fax : 303-675-2176 or 800-344-3867 toll free usa/canada ema il : orderlit@onsemi.com n. american technical support : 8 00- 282 -98 55 tol l f ree usa/canada. europe, middle east and africa technical support : phone: 421 33 790 291 0 japan customer focus cente r pho ne: 81 -3- 577 3-3 850 on sem ico ndu cto r w ebs ite : w ww. ons emi .co m order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative publication ordering information ordering gui de rev. 2 | page 22 of 22 | www.onsemi.com

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