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femtoclocks? vcxo based frequency translator/jitter attenuator ics843002-31 idt ? / ics ? vcxo frequency translator/jitter attenuator 1 ics843002cy-31 rev. b november 8, 2006 preliminary p in a ssignment f eatures ? outputs: ? two high frequency differential lvpecl outputs output frequency: up to 700mhz ? one lvcmos/lvttl vcxo pll output with output enable ? one reference clock output with output enable ? one lock detect output ? input mux supports 3 selectable inputs: one differential input pair and two lvcmos/lvttl input clocks ? 13-bit vcxo pll feedback and reference dividers provide wide range of frequency translation ratio options ? femtoclock frequency multiplier supports rate of: 560mhz - 700mhz ? ?lock detect? output reports lock status of vcxo pll ? vcxo pll circuit provides jitter attenuation with loop bandwidth of 250hz and below (user adjustable) ? rms phase jitter, random at 12khz to 20mhz: <1ps (design target) ? 3.3v supply voltage ? 0c to 70c ambient operating temperature ? industrial temperature information available upon request ? available in both standard (rohs 5) and lead-free (rohs 6) packages 64-lead tqfp, epad 10mm x 10mm x 1.0mm package body y package top view 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ics843002-31 v ee ref_clk vclk lock v cco _ cmos nqb qb v ee nqa qa v cco _ pecl mp npb0 npb1 npb2 v cca lf1 lf0 iset v ee nv1 nv0 v cc mr clk0 nclk0 oe_ref clk1 v cc sel1 sel0 clk2 xoin12 xoin11 xoin10 xoin9 xoin8 xoin7 xoin6 xoin5 xoin4 xoin3 xoin2 xoin1 xoin0 npa2 npa1 npa0 v cca _ xo xtal_in xtal_out xofb0 xofb1 xofb2 xofb3 xofb4 xofb5 xofb6 xofb7 xofb8 xofb9 xofb10 xofb11 xofb12 the preliminary information presented herein represents a product in pre-production. the noted characteristics are based on ini tial product characterization and/or qualification. integrated device technology, incorporated (idt) reserves the right to change any circuitry or specificat ions without notice. g eneral d escription the ics843002-31 is a member of the hiperclocks? family of high performance clock solutions from idt. this monolithic device is a high- performance, pll-based synchronous clock generator and jitter attenuation circuit. the ics843002-31 contains two clock multiplication stages that are cascaded in series. the first stage is a vcxo-based pll that is optimized to provide reference clock jitter attenuation, to be jitter tolerant, and to provide a stable reference clock for the second multiplication stage. the second stage is the proprietary idt femtoclock? circuit which is a high-frequency, sub- picosecond clock multiplier. the vcxo pll has an on-chip vcxo circuit that uses an external, inexpensive pullable crystal in the 17.5 to 25mhz range. the pll includes 13 bit reference and feedback dividers supporting complex pll multiplication ratios and input reference clock rates as low as 2.3khz. external loop filter components are used (two resistors and two capacitors) to achieve the low loop bandwidth needed for jitter atten- uation of a recovered data clock. the femtoclock circuit can multiply the vcxo crystal frequency by a factor of 28 or 32 (selectable) and provide a clock output of up to 700mhz. clock input/output configuration: clock inputs - one differential pair, two singled ended (mux selected) differential input pair can support lvpecl, lvds, lvhstl, sstl, hcsl or single-ended lvcmos or lvttl levels singled ended inputs can support lvcmos or lvttl levels clock outputs, femtoclocks two lvpecl pairs (selectable output dividers) clock output, vcxo ? one single ended output (at vcxo crystal frequency) clock output, other ? vcxo reference clock example applications: sonet/sdh line card clock generator (up to 622.08mhz for oc-48) using 8khz frame clock as input reference jitter attenuation of a recovered communications clock complex-ratio clock frequency translation between various communication protocols, such as: for telecom, oc-12 to e3 rate conversion, 622.08mhz to 34.368mhz, pll ratio of 179/32 for digital video, itu-r601 to smpte 252m/59.94, 27mhz to 74.17582mhz, pll ratio of 250/91 hiperclocks? ic s
idt ? / ics ? vcxo frequency translator/jitter attenuator 2 ics843002cy-31 rev. b november 8, 2006 ics843002-31 femtoclocks? vcxo based frequency translator/ jitter attenua tor preliminary b lock d iagram - n ominal s ystem c onfiguration 00 01 10 11 bypass input divider xoin[12:0] 1 to 8191 vcxo pll femtoclock? frequency multiplier vcxo pll feedback divider xofb[12:0] 1 to 8191 vcxo pll output divider nv[1:0] 00: 1 01: 12 10: 16 11: disabled drive low qa output divider npa[2:0] 000: 1 001: 2 010: 4 011: 8 100: 12 101: 14 110: 16 111: disabled drive low qb output divider npb[2:0] 000: qa 1 001: qa 2 010: qa 4 011: qa 8 100: xoin output 101: ofb output 110: mp output 111: disabled drive low lock detect 3 3 2 13 13 iset charge pump current 17.5 - 25mhz external loop filter connection xtal_in xtal_out lf0 lf1 >1 1 0: x32 1: x28 npb[2:0] npa[2:0] nv[1:0] clk0 nclk0 clk1 clk2 sel1 sel0 xoin[12:0] xofb[12:0] mp oe_ref vclk qa nqa qb nqb ref_clk lock note 1: for application configuration (non-test/bypass modes). note 2: bold lines are primary clock paths (non-control/non-feedback lines). not all control lines and signal paths are shown in this simplified block diagram.
idt ? / ics ? vcxo frequency translator/jitter attenuator 3 ics843002cy-31 rev. b november 8, 2006 ics843002-31 femtoclocks? vcxo based frequency translator/ jitter attenua tor preliminary s implified b lock d iagram - c lock s ignal p aths in b ypass m ode 1 1 bypass 0 1 1 0 input divider xoin[12:0] 1 to 8191 iset charge pump current 17.5 - 25mhz external loop filter connection lf0 lf1 xtal_out xtal_in vcxo pll vcxo pll output divider nv[1:0] 00: 1 01: 12 10: 16 11: disabled drive low vcxo pll feedback divider xofb[12:0] 1 to 8191 qa output divider npa[2:0] npa[2:0] 000: 1 001: 2 010: 4 011: 8 100: 12 101: 14 110: 16 111: disabled drive low femtoclock? feedback divider mp 0: 32 1: 28 000: 1 001: 2 010: 4 011: 8 111: disabled 110: mp 101: xofb 100: xoin femtoclock? frequency multiplier vclk qa nqa qb nqb clk0 nclk0 clk1 clk2 npb2 npb1 npb0 note 1: setting sel1:sel0 = 11 enables bypass mode. only clock signals on the clk0/nclk0 input pair are routed to the device in bypass mode. note 2: bold lines show clock bypass paths. not all control lines and signal paths are shown in this simplified block diagram.
idt ? / ics ? vcxo frequency translator/jitter attenuator 4 ics843002cy-31 rev. b november 8, 2006 ics843002-31 femtoclocks? vcxo based frequency translator/ jitter attenua tor preliminary t able 1. p in d escriptions ( continued on next page ) r e b m u ne m a ne p y tn o i t p i r c s e d 2 , 10 f l , 1 f l g o l a n a t u p t u o / t u p n i . s n i p n o i t c e n n o c r e t l i f p o o l 3t e s i g o l a n a t u p t u o / t u p n i . n i p g n i t t e s t n e r r u c p m u p e g r a h c 8 4 , 1 4 , 4v e e r e w o p . d n u o r g o t d e t c e n n o c y l l a m r o n . s n i p y l p p u s e v i t a g e n 6 , 50 v n , 1 v nt u p n ip u l l u p . s n i p l o r t n o c r e d i v i d t u p t u o l l p o x c v . s l e v e l e c a f r e t n i l t t v l / s o m c v l 3 1 , 7v c c r e w o p. s n i p y l p p u s r e w o p e r o c 8r mt u p n in w o d l l u p d n a s r e d i v i d l a n r e t n i l l a s t e s e r , h g i h n e h w . t e s e r r e t s a m . e c n a d e p m i h g i h n i e r a s t u p t u o s o m c v l . s l e v e l e c a f r e t n i l t t v l / s o m c v l 90 k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 0 10 k l c nt u p n i / p u l l u p n w o d l l u p . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i v c c . g n i t a o l f t f e l n e h w e g a t l o v s a i b 2 / 1 1f e r _ e ot u p n in w o d l l u p , w o l c i g o l n e h w . t u p t u o k c o l c e c n e r e f e r r o f l o r t n o c e l b a n e t u p t u o , h g i h c i g o l n e h w . e c n a d e p m i h g i h n i s i t u p t u o k c o l c e c n e r e f e r e h t . s l e v e l e c a f r e t n i l t t v l / s o m c v l . d e l b a n e s i t u p t u o e h t 2 11 k l ct u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p n i k c o l c 5 1 , 4 10 l e s , 1 l e st u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . t c e l e s k c o l c t u p n i 6 12 k l ct u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p n i k c o l c , 8 1 , 7 1 , 0 2 , 9 1 , 2 2 , 1 2 , 4 2 , 3 2 , 6 2 , 5 2 8 2 , 7 2 1 n i o x : 2 1 n i o xt u p n in w o d l l u p . t u p n i l o r t n o c r e d i v i d t u p n i l l p o x c v . s l e v e l e c a f r e t n i l t t v l / s o m c v l 9 20 n i o xt u p n ip u l l u p . t u p n i l o r t n o c r e d i v i d t u p n i l l p o x c v . s l e v e l e c a f r e t n i l t t v l / s o m c v l , 1 3 , 0 3 2 3 , 1 a p n , 2 a p n 0 a p n t u p n in w o d l l u p . s t u p t u o a q n / a q r o f l o r t n o c r e d i v i d t u p t u o l c e p v l . s l e v e l e c a f r e t n i l t t v l / s o m c v l 3 3v a c c r e w o p. n i p y l p p u s g o l a n a , 5 3 , 4 3 6 3 , 1 b p n , 2 b p n 0 b p n t u p n in w o d l l u p . s t u p t u o b q n / b q r o f l o r t n o c r e d i v i d t u p t u o l c e p v l . s l e v e l e c a f r e t n i l t t v l / s o m c v l 7 3p mt u p n in w o d l l u p . t u p n i l o r t n o c n o i t a c i l p i t l u m k c o l c t i u c r i c ? k c o l c o t m e f . 2 3 s t c e l e s , w o l n e h w . 8 2 s t c e l e s , h g i h n e h w . s l e v e l e c a f r e t n i l t t v l / s o m c v l , 8 3v l c e p _ o c c r e w o p. s t u p t u o k c o l c l c e p v l r o f n i p y l p p u s r e w o p t u p t u o 0 4 , 9 3a q n , a qt u p t u o . s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o k c o l c l a i t n e r e f f i d 3 4 , 2 4b q n , b qt u p t u o . s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o k c o l c l a i t n e r e f f i d 4 4v s o m c _ o c c r e w o p. s t u p t u o s o m c v l r o f n i p y l p p u s r e w o p t u p t u o 5 4k c o lt u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p t u o t c e t e d k c o l 6 4k l c vt u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p t u o k c o l c l l p o x c v 7 4k l c _ f e rt u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p t u o k c o l c e c n e r e f e r : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r
idt ? / ics ? vcxo frequency translator/jitter attenuator 5 ics843002cy-31 rev. b november 8, 2006 ics843002-31 femtoclocks? vcxo based frequency translator/ jitter attenua tor preliminary t able 2. p in c haracteristics r e b m u ne m a ne p y tn o i t p i r c s e d , 0 5 , 9 4 , 2 5 , 1 5 , 4 5 , 3 5 , 6 5 , 5 5 , 8 5 , 7 5 0 6 . 9 5 1 b f o x : 2 1 b f o xt u p n in w o d l l u p . t u p n i l o r t n o c r e d i v i d k c a b d e e f o x c v . s l e v e l e c a f r e t n i l t t v l / s o m c v l 1 60 b f o xt u p n ip u l l u p . t u p n i l o r t n o c r e d i v i d k c a b d e e f o x c v . s l e v e l e c a f r e t n i l t t v l / s o m c v l 3 6 , 2 6 , t u o _ l a t x n i _ l a t x t u p n i . t u p n i e h t s i n i _ l a t x . e c a f r e t n i r o t a l l i c s o l a t s y r c o x c v . t u p t u o e h t s i t u o _ l a t x 4 6v o x _ a c c r e w o p. o x c v r o f n i p y l p p u s r e w o p g o l a n a : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r t able 1. p in d escriptions ( continued from previous page ) l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p c d p e c n a t i c a p a c n o i t a p i s s i d r e w o p ) t u p t u o s o m c v l r e p ( v , c c v , a c c v , o x _ a c c v , s o m c _ o c c v l c e p _ o c c v 5 6 4 . 3 = d b tf p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k ? r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k ? r t u o e c n a d e p m i t u p t u o 7 ?
idt ? / ics ? vcxo frequency translator/jitter attenuator 6 ics843002cy-31 rev. b november 8, 2006 ics843002-31 femtoclocks? vcxo based frequency translator/ jitter attenua tor preliminary s ection 1. f requency t ranslation the ics843002-31 is a two stage device, a vcxo pll stage followed by a low phase noise femtoclock multiplier stage. the vcxo uses a pullable crystal to lock to the reference clock and can provide an output frequency up to 25mhz on the single- ended vclk output. for higher frequencies, the low phase noise femtoclock can multiply the vcxo pll output clock up to 700mhz on 2 differential lvpecl output pairs (qa/nqa, qb/ nqb). the vcxo pll stage has a 13-bit input divider and a 13-bit feedback divider to generate large integer ratios needed for some frequency translation applications. when configuring the device is to use pullable crystals in the 17.5mhz ? 25mhz range on the vcxo pll stage, and ensure that the femtoclock pll is kept within its range of 560mhz to 700mhz. below are 3 examples: 1. 8khz to 622.08mhz and 155.52mhz this frequency translation requires use of both the vcxo pll and the femtoclock circuit. the vcxo pll can be used to multiply up to 19.44mhz for use as a reference clock for the femtoclock which will do the multiplication from 19.44mhz to 622.08mhz. ? using a 19.44mhz pullable crystal on xtal_in/ xtal_out, set the vcxo pll feedback divider pins, xofb[12:0], to 2430. this multiplies the 8khz refer- ence clock to 19.44mhz. ? set the f emtoclock multi plication control pin, mp, to 0 which sets the multiplication factor to 32. this sets the femtoclock vco to 622.08mhz. ? set the qa/nqa output divider control pins, npa[2:0] = 000 for divide by 1. this sets the qa/nqa lvpecl output pair for 622.08mhz. ? set the qb/nqb output divider control pins, npb[2:0] = 010 for divide by 4. this sets the qb/nqb lvpecl output pair for 155.52mhz. 2. t1 to t3. (1.544mhz to two 44.736mhz outputs) since 44.736mhz is slightly higher than the maximum vcxo output frequency, the femtoclock circuit will have to be used. ? using a pullable 22.368mhz on xtal_in/xtal_out, set the vcxo pll feedback divider pins, xofb[12:0] to 2796 and the input divider pins, xoin[12:0] to 193. this multiplies the 1.544mhz reference to 22.368mhz (1.544mhz * 2796/193 = 22.368mhz). ? set the f emtoclock multi plication control pin, mp, to 28 which sets the vco at 626.304mhz. ? set the qa/nqa output divider control pins, npa[2:0] = 101 for divide by 14. this sets the qa/nqa lvpecl output pair for 44.736mhz. ? set the qb/nqb output divider control pins, npb[2:0] = 000 for divide by 1. this sets the qb/nqb lvpecl output pair for 44.736mhz 3. t1 to e1. (1.544mhz to two 2.048mhz outputs) the 2.048mhz output frequency requirement is low enough that the femtoclock circuit is not required. only the vcxo stage is used for this frequency translation. ? using a pullable 24.576mhz on xtal_in/xtal_out, set the vcxo pll feedback divider pins, xofb[12:0] to 3072 and the input divider pins, xoin[12:0] to 193. this multiplies the 1.544mhz reference to 2.048mhz (1.544mhz * 3072/193 = 24.576mhz). ? set the vcxo pll output divider control pins, nv[1:0] = 01 for /12. this divides the 24.576mhz vcxo pll frequency down to 2.048mhz. the frequency configuration table examples (see the following pages) are intended to show the most common frequency translation requirements. it is sorted in order of descending input frequency. it is not intended to be an exhaustive configur- ation table because that would be impractical with almost 3 billion possible configurations. as far as configuration is concerned, frequencies <= 25mhz can be generated with the vcxo pll while frequencies > 25mhz require the use of the downstream femtoclock which can multiply the vcxo pll output up to 700mhz. complex integer ratios are handled with the vcxo pll stage and the femtoclock circuit can be configured to multiply the vcxo pll output by 32 or 28. the following example will illustrate the configuration process. assume you have a 1.544mhz t1 clock which needs to be multiplied up to 622.08mhz (oc12). obviously, the femtoclock multiplier will be needed to achieve 622.08mhz. since the femtoclock has a selectable multiplication factor of 28 or 32, this means there are 2 viable vcxo pll crystal choices which fall within its 17.5mhz ? 15mhz range: 22.217143mhz (/28 feedback divider) or 19.44mhz (/32 feedback divider). use of the /28 feedback divider for the femtoclock multiplier will give slightly better phase noise, but in this case 22.217143/1.544 cannot be exactly achieved with the 13-bit input and feedback vcxo pll dividers. using the x32 setting of the femtoclock allows a ratio of 19.44/1.544 = 2430/193 which is easily achievable. so the femtoclock would be set for x32 and a 19.44mhz crystal would be used. the vcxo pll input divider would be set for 193 and the vcxo pll feedback divider would be set for 2430. to double check the solution, perform the following calculation: 1.544 * 2430 * 32/193 = 622.08mhz. the 2 nd femtoclock multiplier output, qb/nqb, can be set to equal the qa/nqa output frequency or a fraction of its frequency. the following fractional values are available: /1, /2, /4, /8. s ection 2. f requency c onfiguration
idt ? / ics ? vcxo frequency translator/jitter attenuator 7 ics843002cy-31 rev. b november 8, 2006 ics843002-31 femtoclocks? vcxo based frequency translator/ jitter attenua tor preliminary t able 3a. f requency c onfiguration e xamples , continued on next pag e t u p n i y c n e u q e r f ) z h m ( t u p t u o y c n e u q e r f ) z h m ( r o o x c v t u p t u o k c o l c o t m e f o x c v d e r i u q e r y c n e u q e r f l a t s y r c ) z h m ( o x c v t u p n i r e d i v i d o x c v k c a b d e e f r e d i v i d o x c v t u p t u o r e d i v i d k c o l c o t m e f n o i t a c i l p i t l u m ? r o t c a f k c o l c o t m e f y c n e u q e r f t u p t u o ) z h m ( k c o l c o t m e f t u p t u o r e d i v i d n o i t a c i l p p a 8 0 . 2 2 68 0 . 2 2 6t u p t u o k c o l c o t m e f4 4 . 9 12 31a / n2 38 0 . 2 2 61 ) 2 1 c o ( 8 0 . 2 2 6 > - 8 0 . 2 2 6 8 0 . 2 2 64 0 . 1 1 3t u p t u o k c o l c o t m e f4 4 . 9 12 31a / n2 38 0 . 2 2 62 ) t e n o s ( 4 0 . 1 1 3 > - 8 0 . 2 2 6 8 0 . 2 2 62 5 . 5 5 1t u p t u o k c o l c o t m e f4 4 . 9 12 31a / n2 38 0 . 2 2 64 ) 3 c o o t 2 1 c o ( 2 5 . 5 5 1 > - 8 0 . 2 2 6 8 0 . 2 2 66 7 . 7 7t u p t u o k c o l c o t m e f4 4 . 9 12 31a / n2 38 0 . 2 2 68 ) t e n o s ( 6 7 . 7 7 > - 8 0 . 2 2 6 8 0 . 2 2 64 8 . 1 5t u p t u o k c o l c o t m e f4 4 . 9 12 31a / n2 38 0 . 2 2 62 1) 1 c o o t 2 1 c o ( 4 8 . 1 5 > - 8 0 . 2 2 6 8 0 . 2 2 68 8 . 8 3t u p t u o k c o l c o t m e f4 4 . 9 12 31a / n2 38 0 . 2 2 66 1) t e n o s ( 8 8 . 8 3 > - 8 0 . 2 2 6 8 0 . 2 2 64 4 . 9 1t u p t u o o x c v4 4 . 9 12 311 a / na / na / n) t e n o s ( 4 4 . 9 1 > - 8 0 . 2 2 6 8 0 . 2 2 66 3 7 . 4 4t u p t u o k c o l c o t m e f8 6 3 . 2 20 8 4 63 3 2a / n8 24 0 3 . 6 2 64 1) 3 t o t 2 1 c o ( 6 3 7 . 4 4 > - 8 0 . 2 2 6 8 0 . 2 2 68 6 3 . 4 3t u p t u o o x c v8 6 3 . 4 30 4 2 39 7 11 a / na / na / n) 3 e o t 2 1 c o ( 8 6 3 . 4 3 > - 8 0 . 2 2 6 8 0 . 2 2 64 6 0 . 2 3t u p t u o o x c v4 6 0 . 2 30 4 2 37 6 11 a / na / na / n) 3 j o t 2 1 c o ( 4 6 0 . 2 3 > - 8 0 . 2 2 6 8 0 . 2 2 68 4 0 . 2t u p t u o o x c v6 7 5 . 4 25 0 46 12 1a / na / na / n) 1 e o t 2 1 c o ( 8 4 0 . 2 > - 8 0 . 2 2 6 8 0 . 2 2 64 4 5 . 1t u p t u o o x c v4 0 7 . 4 20 6 8 43 9 16 1a / na / na / n) 1 j / 1 t o t 2 1 c o ( 4 4 5 . 1 > - 8 0 . 2 2 6 4 0 . 1 1 34 0 . 1 1 3t u p t u o k c o l c o t m e f4 4 . 9 16 11a / n2 38 0 . 2 2 62 ) t e n o s ( 4 0 . 1 1 3 > - 4 0 . 1 1 3 4 0 . 1 1 32 5 . 5 5 1t u p t u o k c o l c o t m e f4 4 . 9 16 11a / n2 38 0 . 2 2 64 ) t e n o s ( 2 5 . 5 5 1 > - 4 0 . 1 1 3 4 0 . 1 1 36 7 . 7 7t u p t u o k c o l c o t m e f4 4 . 9 16 11a / n2 38 0 . 2 2 68 ) t e n o s ( 6 7 . 7 7 > - 4 0 . 1 1 3 4 0 . 1 1 34 8 . 1 5t u p t u o k c o l c o t m e f4 4 . 9 16 11a / n2 38 0 . 2 2 62 1) t e n o s ( 4 8 . 1 5 > - 4 0 . 1 1 3 4 0 . 1 1 38 8 . 8 3t u p t u o k c o l c o t m e f4 4 . 9 16 11a / n2 38 0 . 2 2 66 1) t e n o s ( 8 8 . 8 3 > - 4 0 . 1 1 3 4 0 . 1 1 34 4 . 9 1t u p t u o o x c v4 4 . 9 16 111 a / na / na / n) t e n o s ( 4 4 . 9 1 > - 4 0 . 1 1 3 4 0 . 1 1 38 0 . 2 2 6t u p t u o k c o l c o t m e f4 4 . 9 16 111 2 38 0 . 2 2 61 ) t e n o s ( 8 0 . 2 2 6 > - 4 0 . 1 1 3 4 0 . 1 1 38 0 . 2 2 6t u p t u o k c o l c o t m e f4 4 . 9 16 111 2 38 0 . 2 2 61 ) t e n o s ( 8 0 . 2 2 6 > - 4 0 . 1 1 3 4 0 . 1 1 36 3 7 . 4 4t u p t u o k c o l c o t m e f8 6 3 . 2 20 4 2 33 3 21 8 24 0 3 . 6 2 64 1) 3 t o t t e n o s ( 6 3 7 . 4 4 > - 4 0 . 1 1 3 4 0 . 1 1 38 6 3 . 4 3t u p t u o o x c v8 6 3 . 4 30 2 6 19 7 11 a / na / na / n) 3 e o t t e n o s ( 8 6 3 . 4 3 > - 4 0 . 1 1 3 4 0 . 1 1 34 6 0 . 2 3t u p t u o o x c v4 6 0 . 2 30 2 6 17 6 11 a / na / na / n) 3 j o t t e n o s ( 4 6 0 . 2 3 > - 4 0 . 1 1 3 4 0 . 1 1 38 4 0 . 2t u p t u o o x c v6 7 5 . 4 25 0 42 32 1a / na / na / n) 1 e o t t e n o s ( 8 4 0 . 2 > - 4 0 . 1 1 3 4 0 . 1 1 34 4 5 . 1t u p t u o o x c v4 0 7 . 4 20 3 4 23 9 16 1a / na / na / n) 1 j / 1 t o t t e n o s ( 4 4 5 . 1 > - 4 0 . 1 1 3 2 5 . 5 5 12 5 . 5 5 1t u p t u o k c o l c o t m e f4 4 . 9 181a / n2 38 0 . 2 2 64 ) 3 c o ( 2 5 . 5 5 1 > - 2 5 . 5 5 1 2 5 . 5 5 16 7 . 7 7t u p t u o k c o l c o t m e f4 4 . 9 181a / n2 38 0 . 2 2 68 ) t e n o s ( 6 7 . 7 7 > - 2 5 . 5 5 1 2 5 . 5 5 14 8 . 1 5t u p t u o k c o l c o t m e f4 4 . 9 181a / n2 38 0 . 2 2 62 1) 1 c o o t 3 c o ( 4 8 . 1 5 > - 2 5 . 5 5 1 2 5 . 5 5 18 8 . 8 3t u p t u o k c o l c o t m e f4 4 . 9 181a / n2 38 0 . 2 2 66 1) t e n o s ( 8 8 . 8 3 > - 2 5 . 5 5 1 2 5 . 5 5 14 4 . 9 1t u p t u o o x c v4 4 . 9 1811a / na / na / n) t e n o s ( 4 4 . 9 1 > - 2 5 . 5 5 1 2 5 . 5 5 14 0 . 1 1 3t u p t u o k c o l c o t m e f4 4 . 9 181a / n2 38 0 . 2 2 62 ) t e n o s ( 4 0 . 1 1 3 > - 2 5 . 5 5 1
idt ? / ics ? vcxo frequency translator/jitter attenuator 8 ics843002cy-31 rev. b november 8, 2006 ics843002-31 femtoclocks? vcxo based frequency translator/ jitter attenua tor preliminary t able 3a. f requency c onfiguration e xamples , continued on next page t u p n i y c n e u q e r f ) z h m ( t u p t u o y c n e u q e r f ) z h m ( r o o x c v t u p t u o k c o l c o t m e f o x c v d e r i u q e r y c n e u q e r f l a t s y r c ) z h m ( o x c v t u p n i r e d i v i d o x c v k c a b d e e f r e d i v i d o x c v t u p t u o r e d i v i d k c o l c o t m e f n o i t a c i l p i t l u m ? r o t c a f k c o l c o t m e f t u p t u o y c n e u q e r f ) z h m ( k c o l c o t m e f t u p t u o r e d i v i d n o i t a c i l p p a 2 5 . 5 5 18 0 . 2 2 6t u p t u o k c o l c o t m e f4 4 . 9 181a / n2 38 0 . 2 2 61 ) 2 1 c o o t 3 c o ( 8 0 . 2 2 6 > - 2 5 . 5 5 1 2 5 . 5 5 16 3 7 . 4 4t u p t u o k c o l c o t m e f8 6 3 . 2 20 2 6 13 3 2a / n8 24 0 3 . 6 2 64 1) 3 t o t 3 c o ( 6 3 7 . 4 4 > - 2 5 . 5 5 1 2 5 . 5 5 18 6 3 . 4 3t u p t u o o x c v8 6 3 . 4 30 1 89 7 11 a / na / na / n) 3 e o t 3 c o ( 8 6 3 . 4 3 > - 2 5 . 5 5 1 2 5 . 5 5 14 6 0 . 2 3t u p t u o o x c v4 6 0 . 2 30 1 87 6 11 a / na / na / n) 3 j o t 3 c o ( 4 6 0 . 2 3 > - 2 5 . 5 5 1 2 5 . 5 5 18 4 0 . 2t u p t u o o x c v6 7 5 . 4 25 0 44 62 1a / na / na / n) 1 e o t 3 c o ( 8 4 0 . 2 > - 2 5 . 5 5 1 2 5 . 5 5 14 4 5 . 1t u p t u o o x c v4 0 7 . 4 25 1 2 13 9 16 1a / na / na / n) 1 j / 1 t o t 3 c o ( 4 4 5 . 1 > - 2 5 . 5 5 1 6 7 . 7 76 7 . 7 7t u p t u o k c o l c o t m e f4 4 . 9 141a / n2 38 0 . 2 2 68 ) t e n o s ( 6 7 . 7 7 > - 6 7 . 7 7 6 7 . 7 74 8 . 1 5t u p t u o k c o l c o t m e f4 4 . 9 141a / n2 38 0 . 2 2 62 1) t e n o s ( 4 8 . 1 5 > - 6 7 . 7 7 6 7 . 7 78 8 . 8 3t u p t u o k c o l c o t m e f4 4 . 9 141a / n2 38 0 . 2 2 66 1) t e n o s ( 8 8 . 8 3 > - 6 7 . 7 7 6 7 . 7 74 4 . 9 1t u p t u o o x c v4 4 . 9 1411a / na / na / n) t e n o s ( 4 4 . 9 1 > - 6 7 . 7 7 6 7 . 7 72 5 . 5 5 1t u p t u o k c o l c o t m e f4 4 . 9 141a / n2 38 0 . 2 2 64 ) t e n o s ( 2 5 . 5 5 1 > - 6 7 . 7 7 6 7 . 7 74 0 . 1 1 3t u p t u o k c o l c o t m e f4 4 . 9 141a / n2 38 0 . 2 2 62 ) t e n o s ( 4 0 . 1 1 3 > - 6 7 . 7 7 6 7 . 7 78 0 . 2 2 6t u p t u o k c o l c o t m e f4 4 . 9 141a / n2 38 0 . 2 2 61 ) t e n o s ( 8 0 . 2 2 6 > - 6 7 . 7 7 6 7 . 7 76 3 7 . 4 4t u p t u o k c o l c o t m e f8 6 3 . 2 20 1 83 3 2a / n8 24 0 3 . 6 2 64 1) 3 t o t t e n o s ( 6 3 7 . 4 4 > - 6 7 . 7 7 6 7 . 7 78 6 3 . 4 3t u p t u o o x c v8 6 3 . 4 35 0 49 7 11 a / na / na / n) 3 e o t t e n o s ( 8 6 3 . 4 3 > - 6 7 . 7 7 6 7 . 7 74 6 0 . 2 3t u p t u o o x c v4 6 0 . 2 35 0 47 6 11 a / na / na / n) 3 j o t t e n o s ( 4 6 0 . 2 3 > - 6 7 . 7 7 6 7 . 7 78 4 0 . 2t u p t u o o x c v6 7 5 . 4 25 0 48 2 12 1a / na / na / n) 1 e o t t e n o s ( 8 4 0 . 2 > - 6 7 . 7 7 6 7 . 7 74 4 5 . 1t u p t u o o x c v4 0 7 . 4 25 1 2 16 8 36 1a / na / na / n) 1 e / 1 t o t t e n o s ( 4 4 5 . 1 > - 6 7 . 7 7 4 8 . 1 54 8 . 1 5t u p t u o k c o l c o t m e f4 4 . 9 183a / n2 38 0 . 2 2 62 1) t e n o s ( 4 8 . 1 5 > - 4 8 . 1 5 4 8 . 1 58 8 . 8 3t u p t u o k c o l c o t m e f4 4 . 9 183a / n2 38 0 . 2 2 66 1) t e n o s ( 8 8 . 8 3 > - 4 8 . 1 5 4 8 . 1 54 4 . 9 1t u p t u o o x c v4 4 . 9 1831a / na / na / n) t e n o s ( 4 4 . 9 1 > - 4 8 . 1 5 4 8 . 1 56 7 . 7 7t u p t u o k c o l c o t m e f4 4 . 9 183a / n2 38 0 . 2 2 68 ) t e n o s ( 6 7 . 7 7 > - 4 8 . 1 5 4 8 . 1 52 5 . 5 5 1t u p t u o k c o l c o t m e f4 4 . 9 183a / n2 38 0 . 2 2 64 ) 3 c o o t 1 c o ( 2 5 . 5 5 1 > - 4 8 . 1 5 4 8 . 1 54 0 . 1 1 3t u p t u o k c o l c o t m e f4 4 . 9 183a / n2 38 0 . 2 2 62 ) t e n o s ( 4 0 . 1 1 3 > - 4 8 . 1 5 4 8 . 1 58 0 . 2 2 6t u p t u o k c o l c o t m e f4 4 . 9 183a / n2 38 0 . 2 2 61 ) 2 1 c o o t 1 c o ( 8 0 . 2 2 6 > - 4 8 . 1 5 4 8 . 1 56 3 7 . 4 4t u p t u o k c o l c o t m e f8 6 3 . 2 20 4 53 3 2a / n8 24 0 3 . 6 2 64 1) 3 t o t 1 c o ( 6 3 7 . 4 4 > - 4 8 . 1 5 4 8 . 1 58 6 3 . 4 3t u p t u o o x c v8 6 3 . 4 30 7 29 7 11 a / na / na / n) 3 e o t 1 c o ( 8 6 3 . 4 3 > - 4 8 . 1 5 4 8 . 1 54 6 0 . 2 3t u p t u o o x c v4 6 0 . 2 30 7 27 6 11 a / na / na / n) 3 j o t 1 c o ( 4 6 0 . 2 3 > - 4 8 . 1 5 4 8 . 1 58 4 0 . 2t u p t u o o x c v6 7 5 . 4 25 3 14 62 1a / na / na / n) 1 e o t 1 c o ( 8 4 0 . 2 > - 4 8 . 1 5 4 8 . 1 54 4 5 . 1t u p t u o o x c v4 0 7 . 4 25 0 43 9 16 1a / na / na / n) 1 j / 1 t o t 1 c o ( 4 4 5 . 1 > - 4 8 . 1 5 6 3 7 . 4 46 3 7 . 4 4t u p t u o k c o l c o t m e f8 6 3 . 2 22118 24 0 3 . 6 2 64 1) 3 t ( 6 3 7 . 4 4 > - 6 3 7 . 4 4
idt ? / ics ? vcxo frequency translator/jitter attenuator 9 ics843002cy-31 rev. b november 8, 2006 ics843002-31 femtoclocks? vcxo based frequency translator/ jitter attenua tor preliminary t able 3a. f requency c onfiguration e xamples , continued on next pag e t u p n i y c n e u q e r f ) z h m ( t u p t u o y c n e u q e r f ) z h m ( r o o x c v t u p t u o k c o l c o t m e f o x c v d e r i u q e r y c n e u q e r f l a t s y r c ) z h m ( o x c v t u p n i r e d i v i d o x c v k c a b d e e f r e d i v i d o x c v t u p t u o r e d i v i d k c o l c o t m e f n o i t a c i l p i t l u m ? r o t c a f k c o l c o t m e f t u p t u o y c n e u q e r f ) z h m ( k c o l c o t m e f t u p t u o r e d i v i d n o i t a c i l p p a 6 3 7 . 4 44 4 5 . 1t u p t u o o x c v4 0 7 . 4 29 9 66 8 36 1a / na / na / n) 1 j / 1 t o t 3 t ( 4 4 5 . 1 > - 6 3 7 . 4 4 6 3 7 . 4 48 4 0 . 2t u p t u o o x c v6 7 5 . 4 23 3 28 2 12 1a / na / na / n) 1 e o t 3 t ( 8 4 0 . 2 > - 6 3 7 . 4 4 6 3 7 . 4 44 4 . 9 1t u p t u o o x c v4 4 . 9 12 3 95 0 41 a / na / na / n) t e n o s o t 3 t ( 4 4 . 9 1 > - 6 3 7 . 4 4 6 3 7 . 4 44 6 0 . 2 3t u p t u o o x c v4 6 0 . 2 33 3 27 6 11 a / na / na / n) 3 j o t 3 t ( 4 6 0 . 2 3 > - 6 3 7 . 4 4 6 3 7 . 4 48 6 3 . 4 3t u p t u o o x c v8 6 3 . 4 33 3 29 7 11 a / na / na / n) 3 e o t 3 t ( 8 6 3 . 4 3 > - 6 3 7 . 4 4 6 3 7 . 4 48 8 . 8 3t u p t u o k c o l c o t m e f4 4 . 9 12 3 95 0 4a / n2 38 0 . 2 2 66 1) t e n o s o t 3 t ( 8 8 . 8 3 > - 6 3 7 . 4 4 6 3 7 . 4 44 8 . 1 5t u p t u o k c o l c o t m e f4 4 . 9 12 3 95 0 4a / n2 38 0 . 2 2 62 1) 1 c o o t 3 t ( 4 8 . 1 5 > - 6 3 7 . 4 4 6 3 7 . 4 46 7 . 7 7t u p t u o k c o l c o t m e f4 4 . 9 12 3 95 0 4a / n2 38 0 . 2 2 68 ) t e n o s o t 3 t ( 6 7 . 7 7 > - 6 3 7 . 4 4 6 3 7 . 4 42 5 . 5 5 1t u p t u o k c o l c o t m e f4 4 . 9 12 3 95 0 4a / n2 38 0 . 2 2 64 ) 3 c o o t 3 t ( 2 5 . 5 5 1 > - 6 3 7 . 4 4 6 3 7 . 4 44 0 . 1 1 3t u p t u o k c o l c o t m e f4 4 . 9 12 3 95 0 4a / n2 38 0 . 2 2 62 ) t e n o s o t 3 t ( 4 0 . 1 1 3 > - 6 3 7 . 4 4 6 3 7 . 4 48 0 . 2 2 6t u p t u o k c o l c o t m e f4 4 . 9 12 3 95 0 4a / n2 38 0 . 2 2 61 ) 2 1 c o o t 3 t ( 8 0 . 2 2 6 > - 6 3 7 . 4 4 8 8 . 8 38 8 . 8 3t u p t u o k c o l c o t m e f4 4 . 9 121a / n2 38 0 . 2 2 66 1) t e n o s ( 8 8 . 8 3 > - 8 8 . 8 3 8 8 . 8 34 4 . 9 1t u p t u o o x c v4 4 . 9 1211a / na / na / n) t e n o s ( 4 4 . 9 1 > - 8 8 . 8 3 8 8 . 8 36 7 . 7 7t u p t u o k c o l c o t m e f4 4 . 9 121a / n2 38 0 . 2 2 68 ) t e n o s ( 6 7 . 7 7 > - 8 8 . 8 3 8 8 . 8 32 5 . 5 5 1t u p t u o k c o l c o t m e f4 4 . 9 121a / n2 38 0 . 2 2 64 ) 3 c o o t t e n o s ( 2 5 . 5 5 1 > - 8 8 . 8 3 8 8 . 8 34 0 . 1 1 3t u p t u o k c o l c o t m e f4 4 . 9 121a / n2 38 0 . 2 2 62 ) t e n o s ( 4 0 . 1 1 3 > - 8 8 . 8 3 8 8 . 8 38 0 . 2 2 6t u p t u o k c o l c o t m e f4 4 . 9 121a / n2 38 0 . 2 2 61 ) 2 1 c o o t t e n o s ( 8 0 . 2 2 6 > - 8 8 . 8 3 8 8 . 8 36 3 7 . 4 4t u p t u o k c o l c o t m e f8 6 3 . 2 25 0 43 3 2a / n8 24 0 3 . 6 2 64 1) 3 t o t t e n o s ( 6 3 7 . 4 4 > - 8 8 . 8 3 8 8 . 8 38 6 3 . 4 3t u p t u o o x c v8 6 3 . 4 35 0 48 5 31 a / na / na / n) 3 e o t t e n o s ( 8 6 3 . 4 3 > - 8 8 . 8 3 8 8 . 8 34 6 0 . 2 3t u p t u o o x c v4 6 0 . 2 35 0 44 3 31 a / na / na / n) 3 j o t t e n o s ( 4 6 0 . 2 3 > - 8 8 . 8 3 8 8 . 8 38 4 0 . 2t u p t u o o x c v6 7 5 . 4 25 0 46 5 22 1a / na / na / n) 1 e o t t e n o s ( 8 4 0 . 2 > - 8 8 . 8 3 8 8 . 8 34 4 5 . 1t u p t u o o x c v4 0 7 . 4 25 1 2 12 7 76 1a / na / na / n) 1 j / 1 s d o t t e n o s ( 4 4 5 . 1 > - 8 8 . 8 3 8 6 3 . 4 38 6 3 . 4 3t u p t u o o x c v8 6 3 . 4 3 111 a / na / na / n) 3 e ( 8 6 3 . 4 3 > - 8 6 3 . 4 3 8 6 3 . 4 36 3 7 . 4 4t u p t u o k c o l c o t m e f8 6 3 . 2 28 5 33 3 2a / n8 24 0 3 . 6 2 64 1) 3 t o t 3 e ( 6 3 7 . 4 4 > 8 6 3 . 4 3 8 6 3 . 4 34 6 0 . 2 3t u p t u o o x c v4 6 0 . 2 39 7 17 6 11 a / na / na / n) 3 j o t 3 e ( 4 6 0 . 2 3 > - 8 6 3 . 4 3 8 6 3 . 4 34 4 . 9 1t u p t u o o x c v4 4 . 9 16 1 75 0 41 a / na / na / n) t e n o s o t 3 e ( 4 4 . 9 1 > - 8 6 3 . 4 3 8 6 3 . 4 38 4 0 . 2t u p t u o o x c v6 7 5 . 4 29 7 18 2 12 1a / na / na / n) 1 e o t 3 e ( 8 4 0 . 2 > - 8 6 3 . 4 3 8 6 3 . 4 34 4 5 . 1t u p t u o o x c v4 0 7 . 4 27 3 56 8 36 1a / na / na / n) 1 t o t 3 e ( 4 4 5 . 1 > - 8 6 3 . 4 3 4 6 0 . 2 34 6 0 . 2 3t u p t u o o x c v4 6 0 . 2 3 111 a / na / na / n) 3 j ( 4 6 0 . 2 3 > - 4 6 0 . 2 3 4 6 0 . 2 38 6 3 . 4 3t u p t u o o x c v8 6 3 . 4 37 6 19 7 11 a / na / na / n) 3 e o t 3 j ( 8 6 3 . 4 3 > - 4 6 0 . 2 3 4 6 0 . 2 36 3 7 . 4 4t u p t u o k c o l c o t m e f8 6 3 . 2 24 3 33 3 2a / n8 24 0 3 . 6 2 64 1) 3 t o t 3 j ( 6 3 7 . 4 4 > - 4 6 0 . 2 3
idt ? / ics ? vcxo frequency translator/jitter attenuator 10 ics843002cy-31 rev. b november 8, 2006 ics843002-31 femtoclocks? vcxo based frequency translator/ jitter attenua tor preliminary t able 3a. f requency c onfiguration e xamples , continued on next page t u p n i y c n e u q e r f ) z h m ( t u p t u o y c n e u q e r f ) z h m ( r o o x c v k c o l c o t m e f t u p t u o o x c v d e r i u q e r l a t s y r c y c n e u q e r f ) z h m ( o x c v t u p n i r e d i v i d o x c v k c a b d e e f r e d i v i d o x c v t u p t u o r e d i v i d k c o l c o t m e f n o i t a c i l p i t l u m ? r o t c a f k c o l c o t m e f t u p t u o y c n e u q e r f ) z h m ( k c o l c o t m e f t u p t u o r e d i v i d n o i t a c i l p p a 4 6 0 . 2 38 4 0 . 2t u p t u o o x c v6 7 5 . 4 27 6 18 2 12 1a / na / na / n) 1 e o t 3 j ( 8 4 0 . 2 > - 4 6 0 . 2 3 4 6 0 . 2 34 4 5 . 1t u p t u o o x c v4 0 7 . 4 21 0 56 8 36 1a / na / na / n) 1 t o t 3 j ( 4 4 5 . 1 > - 4 6 0 . 2 3 4 4 . 9 14 4 . 9 1t u p t u o o x c v4 4 . 9 1111a / na / na / n) t e n o s ( 4 4 . 9 1 > - 4 4 . 9 1 4 4 . 9 18 8 . 8 3t u p t u o k c o l c o t m e f4 4 . 9 111a / n2 38 0 . 2 2 66 1) t e n o s ( 8 8 . 8 3 > - 4 4 . 9 1 4 4 . 9 14 8 . 1 5t u p t u o k c o l c o t m e f4 4 . 9 111a / n2 38 0 . 2 2 62 1) 1 c o o t t e n o s ( 4 8 . 1 5 > - 4 4 . 9 1 4 4 . 9 16 7 . 7 7t u p t u o k c o l c o t m e f4 4 . 9 111a / n2 38 0 . 2 2 68 ) t e n o s ( 6 7 . 7 7 > - 4 4 . 9 1 4 4 . 9 12 5 . 5 5 1t u p t u o k c o l c o t m e f4 4 . 9 111a / n2 38 0 . 2 2 64 ) 3 c o o t t e n o s ( 2 5 . 5 5 1 > - 4 4 . 9 1 4 4 . 9 14 0 . 1 1 3t u p t u o k c o l c o t m e f4 4 . 9 111a / n2 38 0 . 2 2 62 ) t e n o s ( 4 0 . 1 1 3 > - 4 4 . 9 1 4 4 . 9 18 0 . 2 2 6t u p t u o k c o l c o t m e f4 4 . 9 111a / n2 38 0 . 2 2 61 ) 2 1 c o o t t e n o s ( 8 0 . 2 2 6 > - 4 4 . 9 1 4 4 . 9 16 3 7 . 4 4t u p t u o k c o l c o t m e f8 6 3 . 2 25 0 46 6 4a / n8 24 0 3 . 6 2 64 1) 3 t o t t e n o s ( 6 3 7 . 4 4 > - 4 4 . 9 1 4 4 . 9 18 6 3 . 4 3t u p t u o o x c v8 6 3 . 4 35 0 46 1 71 a / na / na / n) 3 e o t t e n o s ( 8 6 3 . 4 3 > - 4 4 . 9 1 4 4 . 9 14 6 0 . 2 3t u p t u o o x c v4 6 0 . 2 35 0 48 6 61 a / na / na / n) 3 j o t t e n o s ( 4 6 0 . 2 3 > - 4 4 . 9 1 4 4 . 9 18 4 0 . 2t u p t u o o x c v6 7 5 . 4 25 0 42 1 52 1a / na / na / n) 1 e o t t e n o s ( 8 4 0 . 2 > - 4 4 . 9 1 4 4 . 9 14 4 5 . 1t u p t u o o x c v4 0 7 . 4 25 1 2 14 4 5 16 1a / na / na / n) 1 j / 1 t o t t e n o s ( 4 4 5 . 1 > - 4 4 . 9 1 4 4 . 9 17 5 8 2 4 1 5 . 6 6 6t u p t u o k c o l c o t m e f3 4 1 7 5 8 2 8 . 0 24 15 1a / n2 37 5 8 2 4 1 5 . 6 6 61 ) c e f 8 3 2 / 5 5 2 ( 7 5 8 2 4 1 5 . 6 6 6 > - 4 4 . 9 1 4 4 . 9 13 2 8 5 6 2 3 . 9 6 6t u p t u o k c o l c o t m e f7 5 5 4 6 1 9 . 0 29 75 8a / n2 33 2 8 5 6 2 3 . 9 6 61 ) c e f 7 3 2 / 5 5 2 ( 3 2 8 5 6 2 3 . 9 6 6 > - 4 4 . 9 1 4 4 . 9 19 1 1 7 2 6 1 . 2 7 6t u p t u o k c o l c o t m e f5 7 4 8 0 5 0 0 . 1 26 3 25 5 2a / n2 39 1 1 7 2 6 1 . 2 7 61 ) c e f 6 3 2 / 5 5 2 ( 9 1 1 7 2 6 1 . 2 7 6 > - 4 4 . 9 1 8 4 0 . 28 4 0 . 2t u p t u o o x c v6 7 5 . 4 212 12 1a / na / na / n) 1 e ( 8 4 0 . 2 > - 8 4 0 . 2 8 4 0 . 24 4 5 . 1t u p t u o o x c v4 0 7 . 4 26 13 9 16 1a / na / na / n) 1 j / 1 t o t 1 e ( 4 4 5 . 1 > - 8 4 0 . 2 8 4 0 . 28 6 3 . 4 3t u p t u o o x c v8 6 3 . 4 32 37 3 51 a / na / na / n) 3 e o t 1 e ( 8 6 3 . 4 3 > - 8 4 0 . 2 8 4 0 . 24 6 0 . 2 3t u p t u o o x c v4 6 0 . 2 32 31 0 51 a / na / na / n) 3 j o t 1 e ( 4 6 0 . 2 3 > - 8 4 0 . 2 8 4 0 . 26 3 7 . 4 4t u p t u o k c o l c o t m e f8 6 3 . 2 24 69 9 6a / n8 24 0 3 . 6 2 64 1) 3 t o t 1 e ( 6 3 7 . 4 4 > - 8 4 0 . 2 4 4 5 . 14 4 5 . 1t u p t u o o x c v4 0 7 . 4 216 16 1a / na / na / n) 1 j / 1 t ( 4 5 . 1 > - 4 4 5 . 1 4 4 5 . 18 4 0 . 2t u p t u o o x c v6 7 5 . 4 23 9 12 7 0 32 1a / na / na / n) 1 e o t 1 t ( 8 4 0 . 2 > - 4 4 5 . 1 4 4 5 . 14 6 0 . 2 3t u p t u o o x c v4 6 0 . 2 33 9 18 0 0 41 a / na / na / n) 3 j o t 1 j / 1 t ( 4 6 0 . 2 3 > - 4 4 5 . 1 4 4 5 . 18 6 3 . 4 3t u p t u o o x c v8 6 3 . 4 33 9 16 9 2 41 a / na / na / n) 3 e o t 1 j / 1 t ( 8 6 3 . 4 3 > - 4 4 5 . 1 4 4 5 . 16 3 7 . 4 4t u p t u o k c o l c o t m e f8 6 3 . 2 23 9 16 9 7 2a / n8 24 0 3 . 6 2 64 1) 3 t o t 1 j / 1 t ( 6 3 7 . 4 4 > - 4 4 5 . 1 8 0 0 . 04 4 5 . 1t u p t u o o x c v4 0 7 . 4 218 8 0 36 1a / na / na / n) 1 t o t k c o l c e m a r f ( z h m 4 4 5 . 1 > - z h k 8 8 0 0 . 08 4 0 . 2t u p t u o o x c v6 7 5 . 4 212 7 0 32 1a / na / na / n) 1 e o t k c o l c e m a r f ( z h m 8 4 0 . 2 > - z h k 8 8 0 0 . 04 4 . 9 1t u p t u o o x c v4 4 . 9 110 3 4 21 a / na / na / n) t e n o s o t k c o l c e m a r f ( z h m 4 4 . 9 1 > - z h k 8 8 0 0 . 04 6 0 . 2 3t u p t u o o x c v4 6 0 . 2 318 0 0 41 a / na / na / n) 3 j o t k c o l c e m a r f ( z h m 4 6 0 . 2 3 > - z h k 8
idt ? / ics ? vcxo frequency translator/jitter attenuator 11 ics843002cy-31 rev. b november 8, 2006 ics843002-31 femtoclocks? vcxo based frequency translator/ jitter attenua tor preliminary t able 3a. f requency c onfiguration e xamples t u p n i y c n e u q e r f ) z h m ( t u p t u o y c n e u q e r f ) z h m ( r o o x c v k c o l c o t m e f t u p t u o o x c v d e r i u q e r l a t s y r c y c n e u q e r f ) z h m ( o x c v t u p n i r e d i v i d o x c v k c a b d e e f r e d i v i d o x c v t u p t u o r e d i v i d k c o l c o t m e f n o i t a c i l p i t l u m ? r o t c a f k c o l c o t m e f t u p t u o y c n e u q e r f ) z h m ( k c o l c o t m e f t u p t u o r e d i v i d n o i t a c i l p p a 8 0 0 . 08 6 3 . 4 3t u p t u o o x c v8 6 3 . 4 316 9 2 41 a / na / na / n) 3 e o t k c o l c e m a r f ( z h m 8 6 3 . 4 3 > - z h k 8 8 0 0 . 06 3 7 . 4 4t u p t u o k c o l c o t m e f8 6 3 . 2 216 9 7 21 8 24 0 3 . 6 2 64 1) 3 t o t k c o l c e m a r f ( z h m 6 3 7 . 4 4 > - z h k 8 8 0 0 . 08 8 . 8 3t u p t u o k c o l c o t m e f4 4 . 9 110 3 4 2a / n2 38 0 . 2 2 66 1) t e n o s o t k c o l c e m a r f ( z h m 8 8 . 8 3 > - z h k 8 8 0 0 . 06 7 . 7 7t u p t u o k c o l c o t m e f4 4 . 9 110 3 4 2a / n2 38 0 . 2 2 68 ) t e n o s o t k c o l c e m a r f ( z h m 6 7 . 7 7 > - z h k 8 8 0 0 . 02 5 . 5 5 1t u p t u o k c o l c o t m e f4 4 . 9 110 3 4 2a / n2 38 0 . 2 2 64 ) 3 c o o t k c o l c e m a r f ( z h m 2 5 . 5 5 1 > - z h k 8 8 0 0 . 04 0 . 1 1 3t u p t u o k c o l c o t m e f4 4 . 9 110 3 4 2a / n2 38 0 . 2 2 62 ) t e n o s o t k c o l c e m a r f ( z h m 4 0 . 1 1 3 > - z h k 8 8 0 0 . 08 0 . 2 2 6t u p t u o k c o l c o t m e f4 4 . 9 110 3 4 2a / n2 38 0 . 2 2 61 ) 2 1 c o o t k c o l c e m a r f ( z h m 8 0 . 2 2 6 > - z h k 8
idt ? / ics ? vcxo frequency translator/jitter attenuator 12 ics843002cy-31 rev. b november 8, 2006 ics843002-31 femtoclocks? vcxo based frequency translator/ jitter attenua tor preliminary a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, v o (lvcmos) -0.5v to v cco + 0.5v outputs, i o (lvpecl) contin uous current 50ma surge current 100ma package thermal impedance, ja 22.3c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. t able 4a. p ower s upply dc c haracteristics , v cc = v cca = v cca_xo = v cco_cmos = v cco_pecl = 3.3v5%, t a = 0c to 70c t able 4b. lvcmos / lvttl dc c haracteristics , v cc = v cca = v cca_xo = v cco_cmos = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i t u p n ie g a t l o v h g i h2v c c 3 . 0 +v v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v i h i t u p n i t n e r r u c h g i h , 1 l e s , 0 l e s , f e r _ e o , r m , p m , ] 0 : 2 [ b p n , ] 0 : 2 [ a p n , ] 1 : 2 1 [ n i o x ] 1 : 2 1 [ b f o x , 2 k l c , 1 k l c v c c v = n i v 5 6 4 . 3 =0 5 1a 0 b f o x , 0 n i o x , 1 v n , 0 v nv c c v = n i v 5 6 4 . 3 =5a i l i t u p n i t n e r r u c w o l , 1 l e s , 0 l e s , f e r _ e o , r m , p m , ] 0 : 2 [ b p n , ] 0 : 2 [ a p n , ] 1 : 2 1 [ n i o x ] 1 : 2 1 [ b f o x , 2 k l c , 1 k l c v c c , v 5 6 4 . 3 = v n i v 0 = 5 -a 0 b f o x , 0 n i o x , 1 v n , 0 v n v c c , v 5 6 4 . 3 = v n i v 0 = 0 5 1 -a v h o t u p t u o e g a t l o v h g i h ; k c o l , k l c v , k l c _ f e r 1 e t o n 6 . 2v v l o t u p t u o e g a t l o v w o l ; k c o l , k l c v , k l c _ f e r 1 e t o n 5 . 0v note 1: outputs terminated with 50 ? to v cco_cmos /2. l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a c c v , o x _ a c c e g a t l o v y l p p u s g o l a n a 5 3 1 . 33 . 35 6 4 . 3v v , s o m c _ o c c v l c e p _ o c c e g a t l o v y l p p u s t u p t u o5 3 1 . 33 . 35 6 4 . 3v i e e t n e r r u c y l p p u s r e w o p 5 9 3a m i a c c t n e r r u c y l p p u s g o l a n a 5 1a m
idt ? / ics ? vcxo frequency translator/jitter attenuator 13 ics843002cy-31 rev. b november 8, 2006 ics843002-31 femtoclocks? vcxo based frequency translator/ jitter attenua tor preliminary t able 4d. lvpecl dc c haracteristics , v cc = v cca = v cca_xo = v cco_pecl = 3.3v5%, t a = 0c to 70c t able 5. c rystal c haracteristics t able 4c. d ifferential dc c haracteristics , v cc = v cca = v cca_xo = v cco_cmos = v cco_pecl = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i 0 k l cv n i v = c c v 5 6 4 . 3 =0 5 1a 0 k l c nv n i v = c c v 5 6 4 . 3 =5a i l i t n e r r u c w o l t u p n i 0 k l cv n i v , v 0 = c c v 5 6 4 . 3 =0 5 1 -a 0 k l c nv n i v , v 0 = c c v 5 6 4 . 3 =5 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c 2 , 1 e t o n ; e g a t l o v t u p n i e d o m n o m m o cv e e 5 . 0 +v c c 5 8 . 0 -v v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 1 e t o n h i . v s i 0 k l c n , 0 k l c r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 2 e t o n c c . v 3 . 0 + l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f n y c n e u q e r f l a n i m o n 4 4 . 9 1z h m f t e c n a r e l o t y c n e u q e r f d b t m p p f s y t i l i b a t s y c n e u q e r f d b t m p p e g n a r e r u t a r e p m e t g n i t a r e p o 00 7c c l e c n a t i c a p a c d a o l 2 1f p c o e c n a t i c a p a c t n u h s 4f p c o c / 1 o i t a r y t i l i b a l l u p 0 2 20 4 2 r s ee c n a t s i s e r s e i r e s t n e l a v i u q e 0 5 ? l e v e l e v i r d 1w m n o i t a r e p o f o e d o m l a t n e m a d n u f l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov o c c 4 . 1 -v o c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov o c c 0 . 2 -v o c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p 6 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n ? v o t l c e p _ o c c , n o i t c e s " n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p " e e s . v 2 - . " t i u c r i c t s e t d a o l t u p t u o v 3 . 3 "
idt ? / ics ? vcxo frequency translator/jitter attenuator 14 ics843002cy-31 rev. b november 8, 2006 ics843002-31 femtoclocks? vcxo based frequency translator/ jitter attenua tor preliminary t able 6. ac c haracteristics , v cc = v cca = v cca_xo = v cco_cmos = v cco_pecl = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a p s n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o a q n / a q 5 30 0 7z h m b q n / b q 5 7 3 . 40 0 7z h m k l c v 5 7 8 1 . 15 2z h m k l c _ f e r 0 0 2z h m t ( j )r e t t i j g n i m i t ) z h m 0 2 - z h k 2 1 ( k s a m 8 4 - c o 0 k l c o t n i , t u p n i z h m 4 4 . 9 1 ; t u p t u o z h m 8 0 . 2 2 6 2 , 1 e t o n r e t t i j m o d n a r3 . 1s p r e t t i j c i t s i n i m r e t e d5 7 . 0s p r e t t i j l a t o t 5 . 1s p 5 . 3i u m ) z h m 5 - z h k 0 5 2 ( k s a m 2 1 - c o 0 k l c o t n i , t u p n i z h m 4 4 . 9 1 ; t u p t u o z h m 2 5 . 5 5 1 3 , 1 e t o n r e t t i j m o d n a r1s p r e t t i j c i t s i n i m r e t e d5 . 0s p r e t t i j l a t o t 1 . 1s p 7 . 0i u m ) z h m 0 2 - z h k 2 1 ( k s a m 8 4 - c o 2 k l c o t n i , t u p n i z h k 8 ; t u p t u o z h m 8 0 . 2 2 6 2 , 1 e t o n r e t t i j m o d n a r1s p r e t t i j c i t s i n i m r e t e d3 . 0s p r e t t i j l a t o t 1 . 1s p 7 . 2i u m ) z h m 5 - z h k 0 5 2 ( k s a m 2 1 - c o 2 k l c o t n i , t u p n i z h k 8 ; t u p t u o z h m 2 5 . 5 5 1 3 , 1 e t o n r e t t i j m o d n a r9 . 0s p r e t t i j c i t s i n i m r e t e d9 1 . 0s p r e t t i j l a t o t 9 . 0s p 6 . 0i u m t ( o i ) t u p t u o o t t u p n i w e k s k c o l c ) e g d e k c o l c g n i s i r ( ) b q r o a q ( o t 0 k l c n / 0 k l c z h m 4 4 . 9 1 = 0 k l c n / 0 k l c z h m 6 7 . 7 7 = b / a q ; z h m 4 4 . 9 1 = k l c _ f e r = k l c v 4 , 2 , 1 s e t o n 2s n k l c v o t 0 k l c n / 0 k l c 2s n k l c _ f e r o t 0 k l c n / 0 k l c 5 . 2s n b q r o a q o t 2 k l c r o 1 k l c z h k 8 = 2 / 1 k l c z h m 6 7 . 7 7 = b / a q ; z h m 4 4 . 9 1 = k l c _ f e r = k l c v 5 , 3 , 1 s e t o n 1s n k l c v o t 2 k l c r o 1 k l c 5 . 1s n k l c _ f e r o t 2 k l c r o 1 k l c 3s n t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 20 0 7s p c d oe l c y c y t u d t u p t u o z h m 8 0 . 2 2 6 @ b q / a q 0 5% z h m 4 4 . 9 1 @ k l c _ f e r , k l c v 0 5% t k c o l e m i t k c o l l l p 0 0 1s m . n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . 1 5 4 5 - x c e k e t p i l e z h m 4 4 . 9 1 s i l a t s y r c l a n r e t x e : 1 e t o n , e u l a v t n e n o p m o c r e t l i f p o o l e l p m a x e , n o i t c e s s n o i t a c i l p p a e e s ( 3 . 5 = r o t c a f g n i p m a d p o o l ; z h 0 8 1 = ) b d 3 - ( h t d i w d n a b p o o l : 2 e t o n . ) 4 # e s a c e l p m a x e e u l a v t n e n o p m o c r e t l i f p o o l e l p m a x e , n o i t c e s s n o i t a c i l p p a e e s ( 8 . 2 = r o t c a f g n i p m a d p o o l ; z h 9 1 = ) b d 3 - ( h t d i w d n a b p o o l : 3 e t o n . ) 2 # e s a c e l p m a x e . 1 = v n ; ) 2 3 x ( 0 = p m , 8 = b p n = a p n = b f o x = n i o x : 4 e t o n . 1 = v n ; ) 2 3 x ( 0 = p m , 8 = b p n = a p n ; 0 3 4 2 = b f o x ; 1 = n i o x : 5 e t o n
idt ? / ics ? vcxo frequency translator/jitter attenuator 15 ics843002cy-31 rev. b november 8, 2006 ics843002-31 femtoclocks? vcxo based frequency translator/ jitter attenua tor preliminary p arameter m easurement i nformation lvpecl o utput r ise /f all t ime 3.3v lvcmos o utput l oad ac t est c ircuit 3.3v lvpecl o utput l oad ac t est c ircuit t sk(o) clock outputs 20% 80% 80% 20% t r t f v sw i n g lvcmos o utput r ise /f all t ime lvpecl o utput s kew lvcmos o utput s kew scope qx nqx lvpecl v ee 2v -1.3v 0.165v v cc , v cca , v cca_xo, v cco_pecl scope qx lvcmos gnd 1.65v 5% -1.65v 5% v cc , v cca , v cca_xo, v cco_cmos t sk(o) v ddo 2 v ddo 2 vclk ref_clk nqa qa nqb qb clock outputs 20% 80% 80% 20% t r t f
idt ? / ics ? vcxo frequency translator/jitter attenuator 16 ics843002cy-31 rev. b november 8, 2006 ics843002-31 femtoclocks? vcxo based frequency translator/ jitter attenua tor preliminary lvcmos o utput d uty c ycle /p ulse w idth /tp eriod lvpecl o utput d uty c ycle /p ulse w idth /tp eriod p hase j itter phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power t pw t period t pw t period odc = x 100% qa, qb nqa, nqb t period t pw t period odc = x 100% v cco_lvcmos 2 t pw vclk, ref_clk
idt ? / ics ? vcxo frequency translator/jitter attenuator 17 ics843002cy-31 rev. b november 8, 2006 ics843002-31 femtoclocks? vcxo based frequency translator/ jitter attenua tor preliminary a pplication i nformation d escription of the pll s tages the ics843002-31 is a two stage frequency multiplication device, a vcxo pll followed by a low phase noise femtoclock frequency multiplier. the vcxo uses an external pullable crystal which can be pulled 100ppm by the vcxo pll circuitry to phase lock it to the input reference frequency. the output frequency of the vcxo pll is equal to that of the external pullable crystal, which is in the range of 17.5mhz to 25mhz. the loop bandwidth vcxo pll is typically set in the range of 10-250hz which provides attenuation of input reference clock jitter. since the vcxo is a high-q oscillator circuit, it has low intrinsic output jitter and phase noise. the vcxo pll output clock is available from the vclk pin. the femtoclock frequency multiplier has an effective control bandwidth of about 800khz which means it will track the vcxo pll clock output. vcxo pll l oop r esponse c onsiderations loop response characteristics of the vcxo pll is affected by the setting of the vcxo feedback divider value (xofb) and by the external loop filter components. a practical range of loop bandwidth for many applications is 25hz to 1khz. a bandwidth of less than 10hz requires careful component selection and possible metal shielding to prevent clock output wander. a damp- ing factor of 0.7 or greater should be used to ensure loop stability. when a passband peaking of <0.1db is desired for sonet/sdh loop timing application, the damping factor should be 6 or higher. a pc base pll bandwidth calculator is also under development. for assistance with loop filter bandwidth and component selec- tion suggestions, please contact your idt sales representative. nbw (vcxo pll) ? (phase detector) 20 df (vclk) = x r s 2 i cp x c s x k o xofb divider nbw (vcxo pll) = r s x i cp x k o 32 s etting the vcxo pll l oop r esponse the vcxo pll loop response is determined both by fixed device characteristics and by other characteristics set by the user. this includes the values of r s , c s , c p and r set as shown in the external vcxo pll components figure on this page. the vcxo pll loop bandwidth is approximated by: w here : r s = value of resistor r s in loop filter in ohms i cp = charge pump current in amps (see table on page 17) k o = vcxo gain in hz/v (see table on page 18) xofb divider = 1 to 8191 the above equation calculates the ?normalized? loop bandwidth (denoted as ?nbw?) which is approximately equal to the -3db bandwidth. nbw does not take into account the effects of damp- ing factor or the second pole imposed by c p . it does, however, provide a useful approximation of filter performance. to prevent jitter on vclk due to modulation of the vcxo pll by the phase detector frequency, the following general rule should be observed: ? (phase detector) = input frequency xoin the pll loop damping factor is determined by: w here : c s = value of capacitor c s in loop filter in farads 1 2 3 64 63 62 lfr lf iset c s r s c p r set optional optional f igure 1. e xternal vcxo pll c omponents
idt ? / ics ? vcxo frequency translator/jitter attenuator 18 ics843002cy-31 rev. b november 8, 2006 ics843002-31 femtoclocks? vcxo based frequency translator/ jitter attenua tor preliminary n otes on s etting the v alue of c p as another general rule, the following relationship should be maintained between components c s and c p in the loop filter: c p establishes a second pole in the vcxo pll loop filter. for higher damping factors (> 1), calculate the value of c p based on a c s value that would be used for a damping factor of 1. this will minimize baseband peaking and loop instability that can lead to output jitter. c p also dampens vcxo pll input voltage modulation by the charge pump correction pulses. a c p value that is too low will result in increased output phase noise at the phase detector frequency due to this. in extreme cases where input jitter is high, charge pump current is high, and c p is too small, the vcxo pll input voltage can hit the supply or ground rail resulting in non- linear loop response. c p = c s 20 the best way to set the value of c p is to use the filter response software under development from ics (please refer to the follow- ing section). c p should be increased in value until it just starts affecting the passband peak. n otes on e xternal c rystal l oad c apacitors in the loop filter schematic diagram, capacitors are shown between pins 62 to ground and between pins 63 to ground. these are optional crystal load capacitors which can be used to center tune the external pullable crystal (the crystal frequency can only be lowered by adding capacitance, it cannot be raised). note that the addition of external load capacitors will decrease the crystal pull range and the kvco value. n otes on s etting c harge p ump c urrent the recommended range for the charge pump current is 50 a to 500 a. below 50 a, loop filter charge leakage, due to pcb or capacitor leakage, can become a problem. this loop filter leakage can cause locking problems, output clock cycle slips, or low frequency phase noise. as can be seen in the loop bandwidth and damping factor equations or by using the filter response software available from ics, increasing charge pump current (i cp ) increases both bandwidth and damping factor. r t e s i ( t n e r r u c p m u p e g r a h c p c ) k 6 . 7 1a 5 . 2 6 k 8 . 8a 5 2 1 k 4 . 4a 0 5 2 k 2 . 2a 0 0 5 1e-3 100e-6 10e-6 1k 10k 100 k r set , ? i cp , amps f igure 2. c harge p ump c urrent vs . v alue of r set ( external resistor ) g raph c harge p ump c urrent , e xample s ettings
idt ? / ics ? vcxo frequency translator/jitter attenuator 19 ics843002cy-31 rev. b november 8, 2006 ics843002-31 femtoclocks? vcxo based frequency translator/ jitter attenua tor preliminary vcxo g ain (k o ) vs . xtal f requency e l p m a x e e s a c r e b m u n n o i t a r u g i f n o c e c i v e d n o i t c e l e s t n e n o p m o c r e t l i f p o o le c n a m r o f r e p l l p o x c v t u p n i e c n e r e f e r k c o l c l a t x y c n e u q e r f ) z h m ( n i o x r e d i v i d b f o x r e d i v i d p m r e d i v i d r t e s r o t s i s e r k ( ? ? ? ? ? ) r s r o t s i s e r k ( ? ? ? ? ? ) c s p a c ) f ( c p p a c ) f ( w b p o o l ) b d 3 - ( ) z h m ( p o o l g n i p m a d r o t c a f d n a b s s a p g n i k a e p ) b d ( 1z h k 84 4 . 9 110 3 4 205 . 40 5 10 11 0 . 08 18 . 51 . 0 2z h k 84 4 . 9 110 3 4 205 . 40 5 12 . 21 0 . 09 18 . 23 . 0 3z h k 4 4 . 9 14 4 . 9 12 32 30 9 0 . 91 10 11 0 . 05 67 . 23 . 0 4z h m 4 4 . 9 14 4 . 9 18809 0 . 91 10 11 0 . 00 8 13 . 51 . 0 e xample l oop f ilter c omponent v alue 8000 7000 6000 5000 4000 16 18 20 22 24 26 9000 xtal frequency (mhz) k vco (hz/v)
idt ? / ics ? vcxo frequency translator/jitter attenuator 20 ics843002cy-31 rev. b november 8, 2006 ics843002-31 femtoclocks? vcxo based frequency translator/ jitter attenua tor preliminary as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics843002-31 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc , v cca , v cca_xo , and v cco_x should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 3 illustrates how a 10 ? resistor along with a 10 f and a .01 f bypass capacitor should be connected to each v cca pin. p ower s upply f iltering t echniques f igure 3. p ower s upply f iltering 10 ? v cca 10 f .01 f 3.3v .01 f v cc f igure 4c. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river f igure 4b. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river f igure 4d. h i p er c lock s clk/nclk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk0 /nclk0 accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 4a to 4d show interface examples for the hiperclocks clk0/nclk0 input driven by the most common driver types. the input interfaces suggested here f igure 4a. h i p er c lock s clk/nclk i nput d riven by idt h i p er c lock s lvhstl d river are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example in figure 4a, the input termination applies for idt hiperclocks lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v
idt ? / ics ? vcxo frequency translator/jitter attenuator 21 ics843002cy-31 rev. b november 8, 2006 ics843002-31 femtoclocks? vcxo based frequency translator/ jitter attenua tor preliminary f igure 5. s ingle -e nded c lock i nput i nterface 3.3v clk nclk 3.3v 51k 51k 51k (no connection) differential input stage lvttl or lvcmos logic output series termination optional series filter resistor nclk0 clk0 internal device circuitry external circuitry d ifferential c lock i nput c ircuit u sing the d ifferential i nterface for s ingle -e nded c locks the differential interface (clk0/nclk0) can be used as a third single-ended input to support an lvcmos or lvttl clock driver. the clock input is connected to the clk0 input pin, and the nclk0 pin is left unconnected. to help reduce interfer- ence with the internal vco circuits, an external resistor can be placed in series with the clock signal near the clk0 input pin. combined with the input pin capacitance, this resistor acts as a low pass signal filter. the typical value of this optional series filter resistor is 100 ? . this will lower both the amplitude and edge rate of the clock input signal. in the case of a very short clock trace a series termination register may not be needed. i nputs : c rystal i nput : for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from xtal_in to ground. clk i nput : for applications not requiring the use of a clock input, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the clk input to ground. clk/nclk i nput : for applications not requiring the use of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvcmos o utput : all unused lvcmos output can be left floating. we recommend that there is no trace attached. lvpecl o utput all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated.
idt ? / ics ? vcxo frequency translator/jitter attenuator 22 ics843002cy-31 rev. b november 8, 2006 ics843002-31 femtoclocks? vcxo based frequency translator/ jitter attenua tor preliminary v cc - 2v 50 ? 50 ? rtt z o = 50 ? z o = 50 ? fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 ? 125 ? 84 ? 84 ? z o = 50 ? z o = 50 ? fout fin the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that gen- erate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? f igure 7b. lvpecl o utput t ermination f igure 7a. lvpecl o utput t ermination transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal dis- tortion. figures 7a and 7b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board design- ers simulate to guarantee compatibility across all printed circuit and clock component process variations. t ermination for 3.3v lvpecl o utputs exposed pad expose metal pad (ground pad) ground plane solder signal trace signal trace therm al via solder m ask f igure 6. p.c. b oard for e xposed p ad t hermal r elease p ath e xample t hermal r elease p ath the exposed metal pad provides heat transfer from the device to the p.c. board. the exposed metal pad is ground pad connected to ground plane through thermal via. the exposed pad on the device to the exposed metal pad on the pcb is contacted through solder as shown in figure 6. for further information, please refer to the application note on surface mount assembly of amkor?s thermally /electrically enhance leadframe base package, amkor technology.
idt ? / ics ? vcxo frequency translator/jitter attenuator 23 ics843002cy-31 rev. b november 8, 2006 ics843002-31 femtoclocks? vcxo based frequency translator/ jitter attenua tor preliminary p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics843002-31. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics843002-31 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. power (core) max = v cc_max * i ee_max = 3.465v * 395ma = 1368.67mw power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 2 * 30mw = 60mw total power _max (3.465v, with all outputs switching) = 1368.67mw + 60mw = 1428.67mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 17.2c/w per table 7 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 1.429w * 17.2c/w = 94.6c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) t able 7. t hermal r esistance ja for 64- pin tqfp, e-p ad f orced c onvection 0 200 500 multi-layer pcb, jedec standard test boards 22.3c/w 17.2c/w 15.1c/w
idt ? / ics ? vcxo frequency translator/jitter attenuator 24 ics843002cy-31 rev. b november 8, 2006 ics843002-31 femtoclocks? vcxo based frequency translator/ jitter attenua tor preliminary 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 8. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cco - 2v. for logic high, v out = v oh_max = v cco_max ? 0.9v (v cco_max - v oh_max ) = 0.9v for logic low, v out = v ol_max = v cco_max ? 1.7v (v cco_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max - 2v))/r l ] * (v cco_max - v oh_max ) = [(2v - (v cco_max - v oh_max )) /r l ] * (v cco_max - v oh_max ) = [(2v - 0.9v)/50 ? ) * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cco_max - 2v))/r l ] * (v cco_max - v ol_max ) = [(2v - (v cco_max - v ol_max )) /r l ] * (v cco_max - v ol_max ) = [(2v - 1.7v)/50 ? ) * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 8. lvpecl d river c ircuit and t ermination q1 v out v cco rl 50 v cco - 2v
idt ? / ics ? vcxo frequency translator/jitter attenuator 25 ics843002cy-31 rev. b november 8, 2006 ics843002-31 femtoclocks? vcxo based frequency translator/ jitter attenua tor preliminary r eliability i nformation t ransistor c ount the transistor count for ics843002-31 is: 10,095 t able 7. ja vs . a ir f low t able for 64 l ead tqfp, e-p ad ja vs. 0 air flow (linear feet per minute) 0 200 500 multi-layer pcb, jedec standard test boards 22.3c/w 17.2c/w 15.1c/w
idt ? / ics ? vcxo frequency translator/jitter attenuator 26 ics843002cy-31 rev. b november 8, 2006 ics843002-31 femtoclocks? vcxo based frequency translator/ jitter attenua tor preliminary p ackage o utline - y s uffix for 64 l ead tqfp, epad (32 pin package depicted to define table 9 dimension symbols) t able 9. p ackage d imensions for 64 l ead tqfp, epad reference document: jedec publication 95, ms-026 n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s d h - d c a m u m i n i ml a n i m o nm u m i x a m n 4 6 a - -- -0 2 . 1 1 a 5 0 . 00 1 . 05 1 . 0 2 a 5 9 . 00 . 15 0 . 1 b 7 1 . 02 2 . 07 2 . 0 c 9 0 . 0- -0 2 . 0 d c i s a b 0 0 . 2 1 1 d c i s a b 0 0 . 0 1 2 d . f e r 0 5 . 7 e c i s a b 0 0 . 2 1 1 e c i s a b 0 0 . 0 1 2 e . f e r 0 5 . 7 e c i s a b 0 5 . 0 l 5 4 . 00 6 . 05 7 . 0 0 - - 7 c c c - -- -8 0 . 0 3 e & 3 d 5 . 40 . 55 . 5
idt ? / ics ? vcxo frequency translator/jitter attenuator 27 ics843002cy-31 rev. b november 8, 2006 ics843002-31 femtoclocks? vcxo based frequency translator/ jitter attenua tor preliminary while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature ranges, high reliability or other extraordina ry environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or w arrant any idt product for use in life support devices or critical medical instruments. t able 10. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 1 3 - y c 2 0 0 3 4 8 s c i1 3 y c 2 0 0 3 4 8 s c id a p e , p f q t d a e l 4 6y a r tc 0 7 o t c 0 t 1 3 - y c 2 0 0 3 4 8 s c i1 3 y c 2 0 0 3 4 8 s c id a p e , p f q t d a e l 4 6l e e r & e p a t 0 0 5c 0 7 o t c 0 f l 1 3 - y c 2 0 0 3 4 8 s c id b td a p e , p f q t " e e r f - d a e l " d a e l 4 6y a r tc 0 7 o t c 0 t f l 1 3 - y c 2 0 0 3 4 8 s c id b td a p e , p f q t " e e r f - d a e l " d a e l 4 6l e e r & e p a t 0 0 5c 0 7 o t c 0 . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 corporate headquarters integrated device t echnology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 fax: +44 (0) 1372 378851 ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa ics843002-31 femtoclocks? vcxo based frequency translator/ jitter attenua tor preliminary

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