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cmos, low voltage, 3 - wire serially - controlled, matrix switches data sheet adg738 / adg739 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibili ty is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any pa tent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2000 C 2012 ana log devices, inc. all rights reserved. technical support www.analog.com features 3 - wire serial interface 2.7 v to 5.5 v single supply 2.5 on resistance 0.75 on - resistance flatness 100 pa leakage currents single 8 - to - 1 multiplexer adg738 dual 4 - to - 1 multiplexer adg739 power - on reset ttl/cmos - compatible qualified for automotive applications applications data acquisition systems communication syst ems relay replacement audio and video switching general description the adg738 and adg739 are cmos analog matrix switches with a serially - controlled 3 - wire interface. the adg738 is an 8 - channel matrix switch, while the adg739 is a dual 4 - channel matrix switch. on re sistance is closely matched between switches and very flat over the full signal range. functional block dia gram s figure 1. figure 2. the adg738 and adg739 utilize a 3 - wire serial interface that is compatible with s pi?, qspi?, microwire ? , and some dsp interface standards. the output of the input shift register , dout , enables a number of these parts to be daisy - chained. on power - up, the internal input shift register contains all zeros and all switches are in the off s tate. each switch conducts equally well in both directions when on, making these parts suitable for both multiplexing and demulti - plexing applications. as each switch is turned on or off by a separate bit, these parts can also be configured as a type of sw itch array, where any, all, or none of the eight switches may be closed at any time. the input signal range extends to the supply rails. all channels exhibit break - before - make switching action, preventing momentary shorting when switching channels. the adg738 and adg739 are available in 16 - lead tssop packages. product highlights 1. 3 - wire serial interface. 2. single supply operation. the adg738 / adg739 are fully specified and guaranteed with 3 v and 5 v supply rails. 3. low on resistance, 2.5 typical . 4. any configuration of switches may be on or off at any one time. 5. guaranteed break - before - make switching action. 6. small 16 - lead tssop package. s1 s8 sclk d din sync adg738 reset dout input shift register 10758-001 s1a sclk da din s4a s1b s4b db adg739 dout sync input shift register 10758-002
adg738/adg739 data sheet rev. a | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagrams ............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing charact eristics ................................................................ 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configurations and function descriptions ........................... 7 typical performance characteristics ............................................. 9 test circuits ..................................................................................... 12 terminology .................................................................................... 14 theory of operation ...................................................................... 15 power - on reset .......................................................................... 15 serial interface ............................................................................ 15 microprocessor interfacing ....................................................... 15 adsp - 21xx to adg738/adg739 ........................................... 15 8051 interface to adg738/adg739 ....................................... 16 mc68hc 11 interface to adg738/adg739 .......................... 16 applications information .............................................................. 17 expand the number of selectable serial devices using an adg739 ....................................................................................... 17 daisy - chaining multiple adg738s ........................................ 17 outline dimensions ....................................................................... 18 ordering guide .......................................................................... 18 automotive products ................................................................. 18 re vision history 1 1 / 12 rev. 0 to rev. a updated format .................................................................. universal changes to features section ............................................................ 1 added w version specifications to table 1 .................................. 3 added w version specifications to table 2 .................................. 4 changes to table 4 ............................................................................ 6 changes to figure 7 , figure 8 , and figure 11 ............................... 9 changes to figure 12 ...................................................................... 10 deleted figure 22 ............................................................................ 12 updated outline dimensions ....................................................... 1 9 changes to ordering guide .......................................................... 1 9 4 /0 0 rev ision 0: initial versi on
data sheet adg738/adg739 rev. a | page 3 of 20 specifications v dd = 5 v 10%, gnd = 0 v, unless otherwise noted. table 1 . b version w version parameter 25c ?40c to +85c ?40c to + 10 5c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on ) 2.5 ? typ v s = 0 v to v dd , i s = 10 ma; see figure 19 4.5 5 6 ? max on - resistance match between channels (?r on ) 0.4 ? typ v s = 0 v to v dd , i s = 10 ma 0.8 1 ? max on - resistance flatness (r flat(on) ) 0.75 ? typ v s = 0 v to v dd , i s = 10 ma 1.2 1.5 ? max leakage currents v dd = 5.5 v source off leakage i s ( off ) 0.01 na typ v d = 4.5 v/1 v, v s = 1 v/4.5 v; see figure 20 0.1 0.3 0. 6 na max drain off leakage i d ( off ) 0.01 na typ v d = 4.5 v/1 v, v s = 1 v/4.5 v 0.1 1 1 .3 na max channel on leakage i d , i s ( on ) 0.01 na typ v d = v s = 1 v/4.5 v, see figure 21 0.1 1 1 .3 na max digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 0.1 a max c in , digital input capacitance 3 pf typ digital output output low voltage 0.4 max i sink = 6 ma c out , digital output capacitance 4 pf typ dynamic characteristics 1 t on 20 ns typ r l = 300 ?, c l = 35 pf, see figure 22 ; v s1 = 3 v 32 35 ns max t off 10 ns typ r l = 300 ?, c l = 35 pf, see figure 22 ; v s1 = 3 v 17 20 ns max break - before - make time delay, t d 9 ns typ r l = 300 ?, c l = 35 pf; 1 1 ns min v s1 = v s8 = 3 v, see figure 22 charge injection 3 pc typ v s = 2.5 v, r s = 0 ?, c l = 1 nf; see figure 23 off isolation ?55 db typ r l = 50 ?, c l = 5 pf, f = 10 mhz ?75 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 25 channel - to - channel crosstalk ?55 db typ r l = 50 ?, c l = 5 pf, f = 10 mhz ?75 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 24 ?3 db bandwidth adg738 65 mhz typ r l = 50 ?, c l = 5 pf, see figure 25 adg739 100 mhz typ c s ( off ) 13 pf typ c d ( off ) adg738 85 pf typ adg739 42 pf typ c d , c s ( on ) adg738 96 pf typ adg739 48 pf typ power requirements v dd = 5.5 v i dd 10 a typ digital inputs = 0 v or 5.5 v 20 20 a max 1 guaranteed by design, not subject to production test.
adg738/adg739 data sheet rev. a | page 4 of 20 v dd = 3 v 10%, gnd = 0 v, unless otherwise noted. table 2 . b version w version parameter 25c ?40c to +85c ?40c to + 105 c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on ) 6 ? typ v s = 0 v to v dd , i s = 10 ma; see figure 19 11 12 16 ? max on - resistance match between channels (?r on ) 0.4 ? typ v s = 0 v to v dd , i s = 10 ma 1.2 1.4 ? max on - resistance flatness (r flat(on) ) 3.5 ? typ v s = 0 v to v dd , i s = 10 ma leakage currents v dd = 3.3 v source off leakage i s ( off ) 0.01 na typ v s = 3 v/1 v, v d = 1 v/3 v; see figure 20 0.1 0.3 0.6 na max drain off leakage i d ( off ) 0.01 na typ v d = 3 v/1 v, v d = 1 v/3 v 0.1 1 1.3 na max channel on leakage i d , i s ( on) 0.01 na typ v d = v s = 3 v/1 v, see figure 21 0.1 1 1.3 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.4 v max input current, i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 0.1 a max c in , digital input capacitance 3 pf typ digital output output low voltage 0.4 max i sink = 6 ma c out , digital output capacitance 4 pf typ dynamic characteristics 1 t on 40 ns typ r l = 300 ?, c l = 35 pf, see figure 22 ; v s1 = 2 v 70 75 ns max t off 14 ns typ r l = 300 ?, c l = 35 pf, see figure 22 ; v s1 = 2 v 25 40 ns max break - before - make time delay, t d 12 ns typ r l = 300 ?, c l = 35 pf; 1 1 ns min v s = 2 v, see figure 22 charge injection 3 pc typ v s = 1.5 v, r s = 0 ?, c l = 1 nf; see figure 23 off isolation ?55 db typ r l = 50 ?, c l = 5 pf, f = 10 mhz ?75 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 25 channel - to - channel crosstalk ?55 db typ r l = 50 ?, c l = 5 pf, f = 10 mhz ?75 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 24 ?3 db bandwidth adg738 65 mhz typ r l = 50 ?, c l = 5 pf, see figure 25 adg739 100 mhz typ c s ( off ) 13 pf typ c d ( off ) adg738 85 pf typ adg739 42 pf typ c d , c s ( on ) adg738 96 pf typ adg739 48 pf typ power requirements v dd = 3.3 v i dd 10 a typ digital inputs = 0 v or 3.3 v 20 20 a max 1 guaranteed by design, not subject to production test.
data sheet adg738/adg739 rev. a | page 5 of 20 timing characteristi cs v dd = 2.7 v to 5.5 v. all specifications ? 40 c to + 105 c, unless otherwise noted. table 3 . parameter 1 , 2 limit at t min , t max unit test conditions/comments min max f sclk 30 mhz sclk cycle frequency t 1 33 ns sclk cycle time t 2 13 ns sclk high time t 3 13 ns sclk low time t 4 0 ns sync to sclk active edge setup time t 5 5 ns data setup time t 6 4.5 ns data hold time t 7 0 ns sclk fa lling edge to sync rising edge t 8 33 ns minimum sync high time t 9 3 20 ns min sclk rising edge to dout valid 1 see figure 3 . 2 all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. 3 c l = 20 pf, r l = 1 k ? . figure 3. 3- wire serial interface timing diagram sclk sync din db7 db0 db7 1 db0 1 dout 1 data from last write cycle. t 3 t 2 t 1 t 4 t 8 t 6 t 5 t 9 t 7 10758-003
adg738/adg739 data sheet rev. a | page 6 of 20 absolute maximum ratings t a = 25c unless otherwise noted. table 4. parameter rating v dd to gnd ?0.3 v to +7 v analog, digital inputs 1 ?0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, s or d 100 ma (pulsed at 1 ms, 10% duty cycle max) continuous current, each s 30 ma continuous current d adg739 80 ma adg738 120 ma operating temperature range industrial (b version) ?40c to +85c industrial (w version) ?40c to +105c storage temperature range ?65c to +150c junction temperature 150c tssop package ja thermal impedance 150.4c/w jc thermal impedance 27.6c/w lead temperature, soldering as per jedec j-std-020 1 overvoltages at in, s, or d are clamped by internal diodes. limit current to the maximum ratings given. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
data sheet adg738/adg739 rev. a | page 7 of 20 pin configuration s and function descrip tions figure 4. adg738 pin configuration table 5 . adg738 pin function descriptions pin no . neonic description 1 sclk serial clock input. data is clocked into the input shift register on the falling edge of the serial clock input. these devices can accommodate serial input rates of up to 30 mhz. 2 reset active low control input . t h is pin clears the input register and turns all switches to the off condition. 3 din serial data input. data is clocked into the 8 - bit input register on the falling edge of the serial clock input. 4, 5, 6, 7 s1, s2, s3, s4 source. may be an input or output. 8 d drain. may be an input or output. 9, 10, 11, 12 s 8, s7, s6, s5 source. may be an input or output. 13 v dd power supply input. these parts can be operated from a supply of 2.7 v to 5.5 v. 14 gnd ground reference. 15 dout data output. this allows a number a parts to be daisy - chained. data is clocked out of the input shift register on the rising edge of sclk. this is an open drain output, which should be pulled to the supply with an external resistor. 16 sync active low control input. this is the frame synchronization signal for the input data. when sync goes low, it powers on the sclk and din buffers and the input shift register is enabled. data is transferred on the falling edges of the following c locks. taking sync high updates the switch conditions. sclk reset s2 s3 s4 s1 d sync dout s5 s6 s7 gnd v dd s8 din 1 2 3 4 5 6 7 8 16 15 14 13 12 1 1 10 9 ad g738 t op view (not to scale) 10758-004
adg738/adg739 data sheet rev. a | page 8 of 20 figure 5. adg739 pin configuration table 6 . adg739 pin function descriptions pin no. mnemonic description 1 sclk serial clock input. data is clocked into the input shift register on the falling edge of the serial clock input. these devices can accommodate serial input rates of up to 30 mhz. 2 sync active low control input. this is the frame synchronization signal for the input data. when sync goes low, it powers on the sclk and din buffers and the input shift register is enabled. data is transferred on the falling edges of the following clocks. taking sync high updates the switch conditions. 3 din serial data input. data is c locked into the 8 - bit input register on the falling edge of the serial clock input. 4, 5, 6, 7 s1a, s2a, s3a, s4a source. may be an input or output. 8, 9 da, db drain. may be an input or output. 10, 11, 12, 13 s4b, s3b, s2b, s1b source. may be an input or output. 14 v dd power supply input. these parts can be operated from a supply of 2.7 v to 5.5 v. 15 gnd ground reference. 16 dout data output. this allows a number a parts to be daisy - chained. data is clocked out of the input shift register on the rising edge of sclk. this is an open drain output, which should be pulled to the supply with an external resistor. sclk s2a s3a s4a s1a da s1b dout s2b s3b s4b gnd v dd db din sync 1 2 3 4 5 6 7 8 16 15 14 13 12 1 1 10 9 ad g739 t op view (not to scale) 10758-005
data sheet adg738/adg739 rev. a | page 9 of 20 typical performance characteristics figure 6. on resistance as a function of v d (v s ) figure 7. on resistance as a function of v d (v s ) for different temperatures , v dd = 5 v figure 8. on resistance as a function of v d (v s ) for different temperatures , v dd = 3 v figure 9. leakage currents as a function of v d (v s ), v dd = 5 v figure 10 . leakage currents as a function of v d (v s ), v dd = 3 v figure 11 . leakage currents as a function of temperature , v dd = 5 v 8 0 1 2 3 4 7 6 5 4 3 2 1 0 on resis t ance ( ?) v dd = 3.3v v dd = 4.5v v dd = 5.5v v dd = 2.7v 5 v d or v s ? drain or source vo lt age (v) t a = 25c v ss = 0v 10758-006 10758-007 0 1 2 3 4 5 7 6 5 4 3 2 1 0 +85c +25c +125c ?40c v dd = 5v v ss = 0v 8 v d or v s ? drain or source voltage (v) 10758-008 +85c ?40c v dd = 3v v ss = 0v 7 6 5 4 3 2 1 0 8 0 0.5 1.0 1.5 2.0 3.0 2.5 v d or v s ? drain or source voltage (v) +25c +125c on resistance ( ?) 0 1 2 3 4 5 v d [v s ] (v) 0.12 current (na) 0.08 0.04 0 ?0.04 ?0.08 ?0.12 i d (on) i s (off) i d (off) v dd = 5v v ss = 0v t a = 25c 10758-009 v d [v s ] (v) 0.12 current (na) 0 0.5 1.0 1.5 2.0 2.5 3.0 0.08 0.04 0 0.04 0.08 0.12 i d (on) i s (off) i d (off) v dd = 3v v ss = 0v t a = 25c 10758-010 10758-0 1 1 0 0 20 40 60 80 100 120 current (na) temper a ture (c) 0.05 0.10 0.15 0.20 0.25 0.30 0.35 v dd = 5v v ss = 0v i d (off) i s (off) i d (on)
adg738/adg739 data sheet rev. a | page 10 of 20 figure 12 . leakage currents as a function of temperature , v dd = 3 v figure 13 . input currents vs. switching frequency figure 14 . charge injection vs. source voltage figure 15 . t on /t off times vs. temperature 10758-012 0 0 20 40 60 80 100 120 current (na) temper a ture (c) 0.05 0.10 0.15 0.20 0.25 0.30 0.35 v dd = 3v i d (off) i s (off) i d (on) frequenc y (hz) current (a) 1 10k 10 100 1m 10m 100k 1m 10m 100m t a = 25c v dd = 5v v dd = 3v 10758-013 volt age (v) q inj (pc) ?40 ?30 ?20 ?10 0 10 20 0 1 2 3 4 5 t a = 25c v dd = 3v v ss = 0v v dd = 5v v ss = 0v 10758-014 temper a ture (c) time (ns) 0 5 10 15 20 25 30 35 40 ?40 ?20 0 20 40 60 45 50 80 10758-015 t on , v dd = 3v t off , v dd = 3v t on , v dd = 5v t off , v dd = 5v
data sheet adg738/adg739 rev. a | page 11 of 20 figure 16 . off isolation vs. frequency figure 17 . crosstalk vs. frequency figure 18 . on response vs. frequency 100k 1m 10m 100m frequenc y (hz) 0 30k a ttenu a tion (db) ?20 ?40 ?60 ?80 ?100 ?120 v dd = 5v t a = 25c 10758-016 frequenc y (hz) 100k 1m 10m 100m 30k 0 ?20 ?40 ?60 ?80 ?100 ?120 a ttenu a tion (db) v dd = 5v t a = 25c 10758-017 frequenc y ( hz) 0 30k a ttenu a tion (db) ?5 100m 100k 1m 10m ?10 ?15 ?20 v dd = 5v t a = 25c adg738 adg739 10758-018
adg738/adg739 data sheet rev. a | page 12 of 20 test circuits figure 19. on resistance figure 20. i d (off), i s (off) figure 21. i s , i d (on) figure 22. switching times and break-before-make times figure 23. charge injection i ds sd v s v 10758-025 r on =v/i ds s1 d v s a a v d i s (off) i d (off) sn 10758-026 a 10758-028 s2 v d v d sn s1 a d i d (on) nc nc = no connect gnd v dd v dd 50% t off 90% 90% 50% v out d v s1 adg738* s1 s8 s2 thru s7 r l 300 ? c l 35pf v s1 80% 80% v s1 = v s8 v s8 v out v out sync t on t open *similar connection for adg739. 10758-029 sync gnd v dd adg738* 1nf input logic v out c l v s r s d *similar connection for adg739. s switch off switch on ? v out q inj = c l v out 10758-030 sync
data sheet adg738/adg739 rev. a | page 13 of 20 figure 24 . channel - to - channel crosstalk figure 25 . off isolation and bandwidth gnd adg738* s1 s2 s8 *similar connection for adg739. channel-to-channel crosstalk = 20log 10 (v out /v s ) v out vdd v dd 50? v s d 50? r l 10758-031 50? gnd adg738* s1 s8 v out v dd r l v dd v s d *similar connection for adg739. off isolation = 20log 10 (v out /v s ) v out without switch insertion loss = 20log 10 v out with switch s1 is switched off for off isolation measurements and on for bandwidth measurements 10758-032
adg738/adg739 data sheet rev. a | page 14 of 20 terminology v dd most positive power supply potential . i dd positive supply current . gnd ground (0 v) reference . s source terminal . may be an input or output. d drain terminal . may be an input or output. v d (v s ) analog voltage on terminal d, terminal s. r on ohmic resistance between d and s. ?r on on resist ance match b etween any two chan nels , that is , r on max ? r on min. r flat(on) flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. i s ( off) source leakage current with the switch off . i d ( off ) drain l eakage current with the switch off. i d , i s (o n ) channel leakage current with the switch on . v inl maximum input voltage for logic 0. v inh minimum input voltage for logic 1. i inl (i inh ) input current of the digital input . c s ( off ) off switch source capacitance . measured with reference to ground. c d ( off ) off switch drain capacitance . measured with reference to ground. c d , c s ( on ) on switch c apacitanc e. measured with refer ence to ground. c in digital input capacitance . t on delay time between the 50% and 90% points of the sync rising edge and the switch on condition. t off delay time between the 50% and 90% points of the sync rising edge and the switch off condition. t d off time measured between the 80% points of both switches when switching from one switch to another. charge injection a measure of the glitch impulse transferred from the digital input to the analog output during switching. off isolation a measure of unwan ted signal coupling through an off switch. crosstalk a measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. bandwidth the frequency at which the output is attenuated by 3 db. on response the frequency response of the on switch. insertion loss the loss due to the on resistance of the switch.
data sheet adg738/adg739 rev. a | page 15 of 20 theory of operation the adg738 and adg739 are serially controlled, 8 - channel and dual 4 - channel matrix switches , respectively. while provid - ing the normal multiplexing and demultiplexing functions, these parts also provide the user with more flexibility as to where their signal may be routed. each bit of the 8 - bit serial word corresponds to one swit ch of the part. a logic 1 in the particular bit position turns on the switch, while a logic 0 turns the switch off. because each switch is independently controlled by an individual bit, this provides the option of having any, all, or none of the switches on . this feature may be particularly useful in the demultiplexing application where the user may wish to direct one signal from the drain to a number of outputs (sources). take c are, however, in the multiplexing situation where a number of inputs may be shorted together (separated only by the small on resistance of the switch). when changing the switch conditions, a new 8 - bit word is written to the input shift register. some of the bits may be the same as the previous write cycle, as the user may not wish to change the state of some switches. to minimize glitches on the output of these switches, t he part cleverly compares the state of switches from the previous write cycle. if the switch is already in the on condition, and is required to stay on , there will be minimal glitches on the output of the switch. power - on reset during device power - up , all switches will be in the off condi - tion and the internal input shift register is filled with zeros and remain s so until a valid write takes place. serial interface the adg738 and adg739 have a 3 - wire serial interface ( sync , sclk, and din), which is compatible with spi, qspi, microwire interface standards and most dsps. figure 3 shows the timing diagram of a typical write sequence. data is written to the 8 - bit input shift register via din under the control of the sync and s clk signals. data may be written to the input shift register in more or less than eight bits. in each case , the input shift register retains the last eight bits that were written. when sync goes low, the input shift register is enabled. data from din is clocked into the input shift register on each falli ng edge of sclk. each bit of the 8 - bit word corresponds to one of the eight switches. figure 26 shows the contents of the input shift register. data appears on the dou t pin on the rising edge of sclk suitable for daisy - chaining, delayed, of course, by eight bits. when all eight bits have been written into the shift register, the sync line is brought high again. the switches are updated with the new con figuration and the input shift register is disabled. with sync held high, any further data or noise on the din line h as no effect on the shift register. figure 26 . input shift register contents microprocessor interfacing microprocessor interfacing to the adg738 / adg739 is via a serial bus that uses a standard protocol compatible with microcontrollers and dsp processors. th e communications channel is a 3 - wire (minimum) interface consisting of a clock signal, a data signal, and a synchronization signal. the adg738 / adg739 requires an 8 - bit data word with data valid on the falling edge of sclk. data from the previous write cycle is available on the dout pin. the following sections illustrate simple 3 - wire interfaces with popular microcontrollers and dsps. adsp - 21xx to adg738 / adg739 an interface between the adg738 / adg739 and the adsp - 21xx is shown in figure 27 . in the interface example shown, sport0 is used to transfer data to the matrix switch . the sport control register should be c onfigured as follows: internal c lock operation, alternate framing mode; active low framing signal. transmission is initiated by writing a word to the tx register after the sport has been enabled. as the data is clocked out of the dsp on the rising edge of sclk, no glue logic is required to interface the dsp to the matrix switch . the update of each switch condition takes place automatically when tfs is taken high. figure 27 . adsp - 21xx to adg738 / adg739 interface s8 s7 s6 s5 s4 s3 s2 s1 db0 (lsb) db7 (msb) data bits 10758-019 sclk din sync tfs dt sclk adsp-21xx* *additional pins omitted for clarity. adg738/ adg739 10758-020
adg738/adg739 data sheet rev. a | page 16 of 20 8051 interface to adg738 / adg739 a serial interface between the adg738 / adg739 and the 8051 is shown in figure 28 . txd of the 8051 drives sclk of the adg738 / adg739 , while rxd drives the serial data line, din. p3.3 i s a bit - programmable pin on the serial port and is used to drive sync . the 8051 provides the lsb of its sbuf register as the first bit in the data stream. the user ha s to ensure that the data in the sbuf register is arranged correctly as the switch expects msb first. when data is to be transmitted to the matrix switch , p3.3 is taken low. data on rxd is clocked out of the microcontroller on the rising edge of txd and is valid on the falling edge. as a result no glue logic is required betwee n the adg738 / adg739 and microcontroller interface. figure 28 . 8051 interface to adg738 / adg739 mc68hc11 interface t o adg738 / adg739 figure 29 shows an example of a serial interface between the adg738 / adg739 and the mc68hc11 microcontroller. sck of the 68hc11 drives the sclk of the matrix switch , while the mosi output drives the serial data line, din. sync is driven from one of the port lines, in this case pc7. figure 29 . mc68hc11 interface to adg738 / adg739 the 68hc11 is configured for master mode; mstr = 1, cpol = 0 , and cpha = 1. when data is transferred to the part, pc7 is taken low, data is transmitted msb first. data appearing on the mosi output is valid on the falling edge of sck. if the user wishes to verify the data previously written to the input shift registe r, the dout line could be connected to miso of the mc68hc11, and with sync low, the input shift register would clock data out on the rising edges of sclk. adg738/ adg739 sclk din p3.3 rxd txd 80c51/80l51* *additional pins omitted for clarity. sync 10758-021 adg738/ adg739 sclk din pc7 mosi sck mc68hc11* *additional pins omitted for clarity. sync 10758-022
data sheet adg738/adg739 rev. a | page 17 of 20 applications information expand the number of selectable serial devices using an adg739 the dual 4 - channel adg739 multiplexer can be used to multiplex a single chip select line to provide c hip selects for up to four devices on the spi bus. figure 30 illustrates the adg739 in such a typical configuration. all devices receive the same serial clock and serial data, but only one device receive s the sync signal at any one time. the adg739 is a serially controlled device also. one bit programmable pin o f the microcontroller is used to enable the adg739 via sync2 , while another bit programmable pin is used as the chip select for the other serial devices, sync1 . driving sync2 low enables changes to be made to the addressed serial devices. by bringing sync1 low, the selected serial device hanging from the spi bus is enabled and data will be clocked into its input shift register on the falli ng edges of sclk. the convenient design of the matrix switch allows for different combinations of the four serial devices to be addressed at any one time. if more devices need to be addressed via one chip select line, the adg738 is an 8 - channel device and would allow further expansion of the chip select scheme. there may be some digital feedthrough from the digital input lines because sclk and din are permanently connected to each device. using a burst clock mini mize s the effects of digital feedthrough on the analog channels. figure 30 . addressing multiple serial devices using an adg739 daisy - chaining multiple adg738 s a number of adg738 matrix switches may be daisy - chained simply by using the dout pin. dout is an open - drain output that should be pulled to the supply with an external resistor. figure 31 shows a typical implementation. the sync pin of all three parts in the example are tied together. when sync is brought low, the input shift registers of all parts are enabled, data is written to the parts via din, and clocked through the shift registers. when the transfer is complete, sync is brought high and all switches are updated simultaneously. furth er shift registers may be added in series. figure 31 . multiple adg739 devices in a daisy - chained configuration da 1/2 of adg739 v dd sclk din sync s1a s2a s3a s4a sync1 din sclk din sclk din sclk din sclk din sclk adg739 adg738 other spi device sync2 from micro- controller or dsp other spi device sync sync sync sync 10758-023 sclk din dout adg739 sclk din adg739 sclk din t u o d t u o d sclk din to other serial devices adg739 v dd r r r sync sync sync sync 10758-024
adg738/adg739 data sheet rev. a | page 18 of 20 outline dimensions figure 32. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters ordering guide model 1, 2 temperature range package description package option adg738bru ?40c to +85c 16-lead thin sh rink small outline package [tssop] ru-16 ADG738BRUZ ?40c to +85c 16-lead thin sh rink small outline package [tssop] ru-16 ADG738BRUZ-reel ?40c to +85c 16-lead thin shrink small outline package [tssop] ru-16 ADG738BRUZ-reel7 ?40c to +85c 16-lead thin shrink small outline package [tssop] ru-16 adg738wbruz-reel ?40c to +105c 16-lead thin shrink small outline package [tssop] ru-16 adg739bru ?40c to +85c 16-lead thin sh rink small outline package [tssop] ru-16 adg739bru-reel7 ?40c to +85c 16-lead thin shrink small outline package [tssop] ru-16 adg739bruz ?40c to +85c 16-lead thin sh rink small outline package [tssop] ru-16 adg739bruz-reel ?40c to +85c 16-lead thin shrink small outline package [tssop] ru-16 adg739bruz-reel7 ?40c to +85c 16-lead thin shrink small outline package [tssop] ru-16 1 z = rohs compliant part. 2 w = qualified for auto motive applications. automotive products the adg738w model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. note that this automotive model may have specifications that differ from the commercial models; therefore, design ers should review the specifications section of this data sheet carefully. only the automotive grade products shown are available f or use in automotive applications. contact your local analog devices account representative for specific product ordering information and to obtain the specific automotive reliability reports for these models. 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab
data sheet adg738/adg739 rev. a | page 19 of 20 notes
adg738/adg739 data sheet rev. a | page 20 of 20 notes ?2000C2012 analog devices, inc. all ri ghts reserved. trademarks and registered trademarks are the prop erty of their respective owners. d10758-0-11/12(a)

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