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843ag-106 www.icst.com/products/hiperclocks.html rev. a january 10, 2006 1 integrated circuit systems, inc. ics843-106 106.25mh z , lvcmos, lvpecl d ual o utput o scillator g eneral d escription the ics843-106 is a fibre channel dual output oscillator and a member of the hiperclocks tm family of high performance devices from ics. the ics843-106 uses a 25mhz crystal to synthesize 106.25mhz. the ics843-106 has excellent jitter performance. the ics843-106 is packaged in a small 8-pin tssop, making it ideal for use in systems with limited board space. f eatures ? one lvcmos/lvttl output, 15 output impedance one lvpecl output pair ? crystal oscillator interface designed for 25mhz, 18pf parallel resonant crystal ? output frequency: 106.25mhz ? random jitter: 3ps (typical) ? deterministic jitter: 0.24ps (typical) ? 3.3v operating supply ? 0c to 70c ambient operating temperature ? available in both standard and lead-free rohs-compliant packages hiperclocks? ic s ics843-106 8-lead tssop 4.40mm x 3.0mm x 0.925mm package body g package top view v cc xtal_in xtal_out v ee 1 2 3 4 q1 nq1 v cco q0 8 7 6 5 b lock d iagram p in a ssignment clock synthesizer xtal_in xtal_out q0 25mhz lvcmos 106.25mhz q1 nq1 lvpecl 106.25mhz ics843-106 8-lead soic 3.90mm x 4.92mm x 1.37mm body package m package top view
843ag-106 www.icst.com/products/hiperclocks.html rev. a january 10, 2006 2 integrated circuit systems, inc. ics843-106 106.25mh z , lvcmos, lvpecl d ual o utput o scillator t able 2. p in c haracteristics t able 1. p in d escriptions l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r t u o e c n a d e p m i t u p t u o0 q5 1 r e b m u ne m a ne p y tn o i t p i r c s e d 1v c c r e w o p. n i p y l p p u s e v i t i s o p 3 , 2 , n i _ l a t x t u o _ l a t x t u p n i , t u p n i e h t s i n i _ l a t x . e c a f r e t n i r o t a l l i c s o l a t s y r c . t u p t u o e h t s i t u o _ l a t x 4v e e r e w o p. n i p y l p p u s e v i t a g e n 50 qt u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p t u o k c o l c d e d n e - e l g n i s 5 1 . e c n a d e p m i t u p t u o 6v o c c r e w o p. n i p y l p p u s t u p t u o 8 , 71 q , 1 q nt u p t u o. r i a p t u p t u o l c e p v l l a i t n e r e f f i d
843ag-106 www.icst.com/products/hiperclocks.html rev. a january 10, 2006 3 integrated circuit systems, inc. ics843-106 106.25mh z , lvcmos, lvpecl d ual o utput o scillator t able 3a. p ower s upply dc c haracteristics , v cc = v cco = 3.3v0.3v, t a = 0c to 70c a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5 v outputs, v o (lvcmos) -0.5v to v cco + 0.5v outputs, i o (lvpecl) continuous current 50ma surge current 100ma package thermal impedance, ja 8 lead tssop 101.7c/w (0 mps) 8 lead soic 112.7c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. t able 3b. lvcmos/lvttl dc c haracteristics , v cc = v cco = 3.3v0.3v, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u o 6 . 2v v l o 1 e t o n ; e g a t l o v w o l t u p t u o 5 . 0v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t o c c , n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . 2 / . " t i u c r i c t s e t d a o l t u p t u o v 3 . 3 " t able 3c. lvpecl dc c haracteristics , v cc = v cco = 3.3v0.3v, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov o c c 4 . 1 -v o c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov o c c 0 . 2 -v o c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p6 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t o c c . v 2 - l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e v i t i s o p 0 . 33 . 36 . 3v v o c c e g a t l o v y l p p u s t u p t u o 0 . 33 . 36 . 3v i e e t n e r r u c y l p p u s r e w o p 6 1 1a m i c c t n e r r u c y l p p u s r e w o p 6 9a m i o c c t n e r r u c y l p p u s t u p t u o 4 2a m
843ag-106 www.icst.com/products/hiperclocks.html rev. a january 10, 2006 4 integrated circuit systems, inc. ics843-106 106.25mh z , lvcmos, lvpecl d ual o utput o scillator t able 4. c rystal c haracteristics (note 1) t able 5. ac c haracteristics , v cc = v cco = 3.3v0.3v, t a = 0c to 70c r e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a l l i c s o f o e d o m l a t n e m a d n u f y c n e u q e r f 5 2z h m e c n a r e l o t y c n e u q e r f 0 3 m p p g n i t a r e p o r e v o y t i l i b a t s y c n e u q e r f e g n a r e r u t a r e p m e t 0 3 m p p c ( e c n a t i c a p a c d a o l l 2 e t o n ; ) 8 1f p s r a e y 0 1 r o f g n i g a 5 1 m p p l e v e l e v i r d 1w m . y c a r u c c a m p p 0 0 1 t e g r a t e v o b a n w o h s s r e t e m a r a p e h t , e g a k c a p d m s s u / 9 4 c h n a g n i s u : 1 e t o n e e s : 2 e t o n e c a f r e t n i t u p n i l a t s y r c . n o i t c e s n o i t a m r o f n i n o i t a c i l p p a e h t n i l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 5 2 . 6 0 1z h m t j d 1 e t o n ; r e t t i j c i t s i n i m r e t e d 4 2 . 0s p t j r 1 e t o n ; r e t t i j m o d n a r 3s p t s m r ( n o i t u b i r t s i d l a t o t f o s m r ; ) 2 e t o n 2 1 . 3s p t p - p 1 e t o n ; r e t t i j k a e p - o t - k a e p 4 2s p t c s o e m i t p u t r a t s n o i t a l l i c s o 0 1s m t r t / f t u p t u o e m i t l l a f / e s i r 0 q % 0 8 o t % 0 2 0 0 10 0 5s p 1 q n / 1 q0 5 20 0 8s p c d oe l c y c y t u d t u p t u o 8 42 5% . 0 0 0 3 - a i s t s e r c e v a w g n i s u d e r u s a e m : 1 e t o n . 4 1 y b d e d i v i d t l u s e r r e b 2 1 - e 0 1 @ j t , 0 0 0 3 - a i s t s e r c e v a w g n i s u d e r u s a e m : 2 e t o n
843ag-106 www.icst.com/products/hiperclocks.html rev. a january 10, 2006 5 integrated circuit systems, inc. ics843-106 106.25mh z , lvcmos, lvpecl d ual o utput o scillator p arameter m easurement i nformation lvpecl o utput d uty c ycle /p ulse w idth /p eriod lvpecl o utput r ise /f all t ime 3.3v lvcmos o utput l oad ac t est c ircuit scope qx lvcmos 1.65v 0.15v -1.65v 0.15v clock outputs 20% 80% 80% 20% t r t f t period t pw t period odc = v cc 2 t pw x 100% q0 gnd v cc, v cco lvcmos o utput d uty c ycle /p ulse w idth /p eriod lvcmos o utput r ise /f all t ime q1 nq1 clock outputs 20% 80% 80% 20% t r t f v sw i n g t pw t period t pw t period odc = x 100% 3.3v lvpecl o utput l oad ac t est c ircuit scope qx nqx lvpecl 2v -1.3v 0.3v v ee v cc, v cco
843ag-106 www.icst.com/products/hiperclocks.html rev. a january 10, 2006 6 integrated circuit systems, inc. ics843-106 106.25mh z , lvcmos, lvpecl d ual o utput o scillator a pplication i nformation figure 1. c rystal i npu t i nterface c rystal i nput i nterface the ics843-106 has been characterized with 18pf parallel resonant crystals. the capacitor values, c1 and c2, shown in figure 1 below were determined using a 25mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. the optimum c1 and c2 values can be slightly adjusted for different board layouts. lvcmos o utput : an unused lvcmos output should be terminated with 100 to ground as close as possible to the device. lvpecl o utput all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. r ecommendations for u nused o utput p ins x1 18pf parallel cry stal c1 12p xtal _ou t xtal _i n c2 12p
843ag-106 www.icst.com/products/hiperclocks.html rev. a january 10, 2006 7 integrated circuit systems, inc. ics843-106 106.25mh z , lvcmos, lvpecl d ual o utput o scillator t ermination for 3.3v lvpecl o utput the clock layout topology shown below is a typical termina- tion for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, termi- nating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to f igure 2b. lvpecl o utput t ermination f igure 2a. lvpecl o utput t ermination drive 50 transmission lines.matched impedance techniques should be used to maximize operating frequency and mini- mize signal distortion. figures 2a and 2b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process varia- tions. v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin f requency s tability the table shown provides a basic guideline in selecting the proper quartz crystal that meets a timing budget of 100ppm. for more information on selecting the proper r e t e m a r a pl a c i p y ts t i n u e c n a r e l o t y c n e u q e r f 0 3 m p p y t i l i b a t s y c n e u q e r f 0 3 m p p s r a e y 0 1 r o f g n i g a5 1 m p p r o t a l l i c s o s c i f o y c a r u c c a0 1 m p p y c a r u c c a e c n a t i c a p a c d a o l3 m p p r o r r e g n i m i t l l a r e v o l a t o t 8 8 m p p crystal, see the application note, crystal timing budget and accuracy for femtoclock? .
843ag-106 www.icst.com/products/hiperclocks.html rev. a january 10, 2006 8 integrated circuit systems, inc. ics843-106 106.25mh z , lvcmos, lvpecl d ual o utput o scillator p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics843-106. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics843-106 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 0.3v = 3.6v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.6v * 116ma = 417.6mw ? power (outputs) max = 30mw/loaded output pair total power _max (3.465v, with all outputs switching) = 417.6mw + 30mw = 447.6mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5c/w per table 6a below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.448w * 90.5c/w = 110.5c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). t able 6a. t hermal r esistance ja for 8- pin tssop, f orced c onvection ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 101.7c/w 90.5c/w 89.8c/w t able 6b. t hermal r esistance ja for 8 l ead soic f orced c onvection ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard t est boards 153.3c/w 128.5c/w 115.5c/w multi-layer pcb, jedec standard t est boards 112.7c/w 103.3c/w 97.1c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
843ag-106 www.icst.com/products/hiperclocks.html rev. a january 10, 2006 9 integrated circuit systems, inc. ics843-106 106.25mh z , lvcmos, lvpecl d ual o utput o scillator 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 3. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cc - 2v. ? for logic high, v out = v oh_max = v cc_max ? 0.9v (v cco_max - v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cc_max ? 1.7v (v cco_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max - 2v))/r l ] * (v cc_max - v oh_max ) = [(2v - (v cc _max - v oh_max )) /r l ] * (v cc_max - v oh_max ) = [(2v - 0.9v)/50 ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cc_max - 2v))/r l ] * (v cc_max - v ol_max ) = [(2v - (v cc _max - v ol_max )) /r l ] * (v cc_max - v ol_max ) = [(2v - 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 3. lvpecl d river c ircuit and t ermination q1 v out v cc rl 50 v cc - 2v
843ag-106 www.icst.com/products/hiperclocks.html rev. a january 10, 2006 10 integrated circuit systems, inc. ics843-106 106.25mh z , lvcmos, lvpecl d ual o utput o scillator r eliability i nformation t ransistor c ount the transistor count for ics843-106 is: 2376 t able 7a. ja vs . a ir f low t able for 8 l ead tssop ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 101.7c/w 90.5c/w 89.8c/w t able 7b. ja vs . a ir f low t able 8 l ead soic ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 1 53.3c/w 128.5c/w 115.5c/w multi-layer pcb, jedec standard t est boards 1 12.7c/w 103.3c/w 97.1c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
843ag-106 www.icst.com/products/hiperclocks.html rev. a january 10, 2006 11 integrated circuit systems, inc. ics843-106 106.25mh z , lvcmos, lvpecl d ual o utput o scillator p ackage o utline - g s uffix for 8 l ead tssop t able 8a. p ackage d imensions reference document: jedec publication 95, mo-153 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n8 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 9 . 20 1 . 3 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0 p ackage o utline - m s uffix for 8 l ead soic t able 8b. p ackage d imensions reference document: jedec publication 95, ms-012 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n8 a5 3 . 15 7 . 1 1 a0 1 . 05 2 . 0 b3 3 . 01 5 . 0 c9 1 . 05 2 . 0 d0 8 . 40 0 . 5 e0 8 . 30 0 . 4 ec i s a b 7 2 . 1 h0 8 . 50 2 . 6 h5 2 . 00 5 . 0 l0 4 . 07 2 . 1 0 8
843ag-106 www.icst.com/products/hiperclocks.html rev. a january 10, 2006 12 integrated circuit systems, inc. ics843-106 106.25mh z , lvcmos, lvpecl d ual o utput o scillator t able 9. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. the aforementioned trademark, hiperclocks? is a trademark of integrated circuit systems, inc. or its subsidiaries in the united states and/or other countries. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 6 0 1 - g a 3 4 8 s c i6 0 1 a 3p o s s t d a e l 8e b u tc 0 7 o t c 0 t 6 0 1 - g a 3 4 8 s c i6 0 1 a 3p o s s t d a e l 8l e e r & e p a t 0 0 5 2c 0 7 o t c 0 f l 6 0 1 - g a 3 4 8 s c id b tp o s s t " e e r f - d a e l " d a e l 8e b u tc 0 7 o t c 0 t f l 6 0 1 - g a 3 4 8 s c id b tp o s s t " e e r f - d a e l " d a e l 8l e e r & e p a t 0 0 5 2c 0 7 o t c 0 6 0 1 - m a 3 4 8 s c id b tc i o s d a e l 8e b u tc 0 7 o t c 0 t 6 0 1 - m a 3 4 8 s c id b tc i o s d a e l 8l e e r & e p a t 0 0 5 2c 0 7 o t c 0 f l 6 0 1 - m a 3 4 8 s c id b tc i o s " e e r f - d a e l " d a e l 8e b u tc 0 7 o t c 0 t f l 6 0 1 - m a 3 4 8 s c id b tc i o s " e e r f - d a e l " d a e l 8l e e r & e p a t 0 0 5 2c 0 7 o t c 0 . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n

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