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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xrt86vl38 octal t1/e1/j1 framer/liu combo - hardware description january 2007 rev. v1.2.0 general description the xrt86vl38 is an eight-channel 1.544 mbit/s or 2.048 mbit/s ds1/e1/j1 framer and liu integrated solution featuring r 3 technology (relayless, reconfigurable, redundancy). the physical interface is optimized with internal impedance, and with the patented pad structure, the xrt86vl38 provides protection from power failures and hot swapping. the xrt86vl38 contains an integrated ds1/e1/j1 framer and liu which provide ds1/e1/j1 framing and error accumulation in accordance with ansi/itu_t specifications. each framer has its own framing synchronizer and transmit-receive slip buffers. the slip buffers can be independently enabled or disabled as required and can be configured to frame to the common ds1/e1/j1 signal formats. each framer block contains its own transmit and receive t1/e1/j1 framing function. there are 3 transmit hdlc controllers per channel which encapsulate contents of the transmit hdlc buffers into lapd message frames. there are 3 receive hdlc controllers per channel which extract the payload content of receive lapd message frames from the incoming t1/e1/j1 data stream and write the contents into the receive hdlc buffers. each framer also contains a transmit and overhead data input port, which permits data link terminal equipment direct access to the outbound t1/e1/j1 frames. likewise, a receive overhead output data port permits data link terminal equipment direct access to the data link bits of the inbound t1/e1/j1 frames. the xrt86vl38 fully meets all of the latest t1/e1/j1 specifications: ansi t1/e1.107-1988, ansi t1/ e1.403-1995, ansi t1/e1.231-1993, ansi t1/ e1.408-1990, at&t tr 62411 (12-90) tr54016, and itu g-703, g.704, g706 and g.733, at&t pub. 43801, and ets 300 011, 300 233, jt g.703, jt g.704, jt g706, i.431. extensive test and diagnostic functions include loop-backs, boundary scan, pseudo random bit sequence (prbs) test pattern generation, performance monitor, bit error rate (ber) meter, forced error insertion, and lapd unchannelized data payload processing according to itu-t standard q.921. applications and features (next page) f igure 1. xrt86vl38 8- channel ds1 (t1/e1/j1) f ramer /liu c ombo performance monitor prbs generator & analyser hdlc/lapd controllers liu & loopback control dma interface signaling & alarms jtag wr ale_as rd rdy_dtack p select a[14:0] d[7:0] microprocessor interface 4 3 tx serial clock rx serial clock 8khz sync osc back plane 1.544-16.384 mbit/s local pcm highway st-bus 2-frame slip buffer elastic store tx serial data in tx liu interface 2-frame slip buffer elastic store rx liu interface rx framer rx serial data out rtip rring ttip tring external data link controller tx overhead in rx overhead out xrt86vl38 1 of 8-channels tx framer llb lb system (terminal) side line side 1:1 turns ratio 1:2 turns ratio memory intel/motorola p configuration, control & status monitor rxlos txon int
xrt86vl38 2 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 applications ? high-density t1/e1/j1 interfaces for multiplexers, switches, lan routers and digital modems ? sonet/sdh terminal or add/drop multiplexers (adms) ? t1/e1/j1 add/drop multiplexers (mux) ? channel service units (csus): t1/e1/j1 and fractional t1/e1/j1 ? digital access cross-connect system (dacs) ? digital cross-connect systems (dcs) ? frame relay switches and access devices (frads) ? isdn primary rate interfaces (pra) ? pbxs and pcm channel bank ? t3 channelized access concentrators and m13 mux ? wireless base stations ? atm equipment with integrated ds1 interfaces ? multichannel ds1 test equipment ? t1/e1/j1 performance monitoring ? voice over packet gateways ? routers features ? eight independent, full duplex ds1 tx and rx framer/lius ? two 512-bit (two-frame) elastic store, pcm frame slip buffers (fifo) on tx and rx provide up to 8.192 mhz asynchronous back plane connections with jitter and wander attenuation ? supports input pcm and signaling data at 1.544, 2.048, 4.096 and 8.192 mbits. also supports 4-channel multiplexed 12.352/16.384 (hmvip/h.100) mbit/s on the back plane bus ? programmable output clocks for fractional t1/e1/j1 ? supports channel associated signaling (cas) ? supports common ch annel signalling (ccs) ? supports isdn primary rate interface (isdn pri) signaling ? extracts and inserts robbed bit signaling (rbs) ? 3 integrated hdlc controllers per channel for transmit and receive, each controller having two 96-byte buffers (buffer 0 / buffer 1) ? hdlc controllers support ss7 ? timeslot assignable hdlc ? v5.1 or v5.2 interface ? automatic performance report generation (pmon status) can be inserted into the transmit lapd interface every 1 second or for a single transmission ? alarm indication signal with customer installation signature (ais-ci) ? remote alarm indication with customer installation (rai-ci) ? gapped clock interface mode for transmit and receive.
xrt86vl38 3 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description ? intel/motorola and power pc interfaces for configuration, control and status monitoring ? parallel search algorithm for fast frame synchronization ? wide choice of t1 framing structures: sf/d4, esf, slc ? 96, t1dm and n-frame (non-signaling) ? direct access to d and e channels for fast transmission of data link information ? prbs, qrss, and network loop code generation and detection ? programmable interrupt output pin ? supports programmed i/o and dma modes of read-write access ? each framer block encodes and decodes the t1/e1/j1 frame serial data ? detects and forces red (sai), yellow (rai) and blue (ais) alarms ? detects oof, lof, los errors and cofa conditions ? loopbacks: local (llb) and line remote (lb) ? facilitates inverse multiplexing for atm ? performance monitor with one second polling ? boundary scan (ieee 1149.1) jtag test port ? accepts external 8khz sync reference ? 1.8v inner core voltage ? 3.3v i/o operation with 5v tolerant inputs ? 420-pin pbga package or 484-pin stbga package with -40 c to +85 c operation ordering information p art n umber p ackage o perating t emperature r ange xrt86vl38ib 420 plastic ball grid array -40 c to +85 c xrt86vl38ib484 484 shrink thin ball grid array -40 c to +85 c
xrt86vl38 4 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 420 ball - plastic ball grid array (bottom view, see pin list for description) 2625242322212019181716151413121110987654321 oooooooooooooooooooooooooo a oooooooooooooooooooooooooo b oooooooooooooooooooooooooo c oooooooooooooooooooooooooo d oooooooooooooooooooooooooo e ooooo ooooo f ooooo ooooo g ooooo ooooo h ooooo ooooo j ooooo ooooo k ooooo ooooo l ooooo ooooo m ooooo ooooo n ooooo ooooo p ooooo ooooo r ooooo ooooo t ooooo ooooo u ooooo ooooo v ooooo ooooo w ooooo ooooo y ooooo ooooo aa oooooooooooooooooooooooooo ab oooooooooooooooooooooooooo ac oooooooooooooooooooooooooo ad oooooooooooooooooooooooooo ae oooooooooooooooooooooooooo af
xrt86vl38 5 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description 484 ball - shrink thin ball grid array (bottom view - see pin list for description) 22212019181716151413121110987654321 oooooooooooooooooooooo a oooooooooooooooooooooo b oooooooooooooooooooooo c oooooooooooooooooooooo d oooooooooooooooooooooo e oooooooooooooooooooooo f oooooooooooooooooooooo g oooooooooooooooooooooo h oooooooooooooooooooooo j oooooooooooooooooooooo k oooooooooooooooooooooo l oooooooooooooooooooooo m oooooooooooooooooooooo n oooooooooooooooooooooo p oooooooooooooooooooooo r oooooooooooooooooooooo t oooooooooooooooooooooo u oooooooooooooooooooooo v oooooooooooooooooooooo w oooooooooooooooooooooo y oooooooooooooooooooooo aa oooooooooooooooooooooo ab
xrt86vl38 i octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 list of paragraphs 1.0 pin lists ................................................................................................................. ................................6 2.0 pin descriptions .......................................................................................................... ....................14
xrt86vl38 ii rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description list of figures figure 1.: xrt86vl38 8-channel ds1 (t1/e1/j1) framer/liu combo ................................................................ ............. 1 figure 2.: itu g.703 pulse template ........................................................................................... ................................... 58 figure 3.: dsx-1 pulse template (normalized amplitude) ........................................................................ ...................... 59
xrt86vl38 iii octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 list of tables table 1:: 420 ball list by ball number ........................................................................................ ....................................... 6 table 2:: 484 ball list by ball number ........................................................................................ ..................................... 10 table 3:: pin description structure ........................................................................................... ....................................... 14 table 4:: e1 receiver electrical characteristics .............................................................................. ................................ 55 table 5:: t1 receiver electrical characteristics .............................................................................. ................................ 56 table 6:: e1 transmitter electrical characteristics ........................................................................... ............................... 56 table 7:: e1 transmit return loss requirement ................................................................................. ............................ 57 table 8:: t1 transmitter electrical characteristics ........................................................................... ............................... 57 table 9:: transmit pulse mask specification ................................................................................... ................................ 58 table 10:: dsx1 interface isolated pulse mask and corner points ............................................................... ................... 59 table 11:: ac electrical characteristics ...................................................................................... ..................................... 60
xrt86vl38 6 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description 1.0 pin lists t able 1: 420 b all l ist by b all n umber p in p in n ame a1 dvdd18 a2 dgnd a3 agnd a4 mclkin a5 tms a6 rxserclk0 a7 tck a8 rxchclk0 a9 txsync0 a10 rxchn0_4 a11 txserclk0 a12 txchclk0 a13 txchn0_2 a14 rxchclk1 a15 rxchn1_2 a16 rxlos1 a17 txmsync1 a18 txoh1 a19 txohclk1 a20 txchn1_3 a21 txchn1_4 a22 rxchn2_0 a23 rxcasync2 a24 rxchclk2 a25 vdd a26 rxchn2_4 b1 vddpll18 b2 gndpll b3 nc b4 avdd18 b5 e1mclkout b6 tdo b7 trst b8 rxcrcsync0 b9 rxohclk0 b10 txmsync0 b11 test b12 txchn0_1 b13 rxserclk1 b14 rxser1 b15 rxoh1 b16 rxchn1_3 b17 vss b18 nc b19 txchn1_2 b20 rxlos2 b21 gpio1_3 b22 rxchn2_1 b23 nc b24 txsync2 b25 vss b26 txchclk2 c1 vddpll18 c2 vddpll18 c3 gndpll c4 nc c5 analog c6 vss c7 rxser0 c8 vdd c9 rxchn0_2 c10 rxchn0_3 c11 rxoh0 t able 1: 420 b all l ist by b all n umber p in p in n ame c12 txoh0 c13 vss c14 txchn0_4 c15 vdd c16 txsync1 c17 rxchn1_4 c18 txchn1_0 c19 txserclk1 c20 rxserclk2 c21 rxser2 c22 rxchn2_2 c23 rxchn2_3 c24 txmsync2 c25 vss c26 txchn2_2 d1 rtip0 d2 rvdd0 d3 vddpll18 d4 jtag_ring d5 rxtsel d6 t1mclkout d7 tdi d8 rxchn0_0 d9 rxsync0 d10 vss d11 txser0 d12 txchn0_0 d13 rxcrcsync1 d14 rxchn1_0 d15 rxsync1 d16 rxohclk1 d17 txser1 t able 1: 420 b all l ist by b all n umber p in p in n ame d18 txchn1_1 d19 rxsync2 d20 vss d21 rxoh2 d22 txserclk2 d23 nc d24 vdd18 d25 txchn2_1 d26 rxser3 e1 rring0 e2 rgnd0 e3 gndpll e4 gndpll e5 nc e6 sense e7 atest e8 rxlos0 e9 rxchn0_1 e10 rxcasync0 e11 txohclk0 e12 vdd18 e13 txchn0_3 e14 rxchn1_1 e15 rxcasync1 e16 nc e17 txchclk1 e18 vdd18 e19 nc e20 rxcrcsync2 e21 rxohclk2 e22 nc e23 txser2 t able 1: 420 b all l ist by b all n umber p in p in n ame
xrt86vl38 7 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 e24 txohclk2 e25 txchn2_4 e26 txoh2 f1 rtip1 f2 rvdd1 f3 ttip0 f4 tvdd0 f5 jtag_tip f22 txchn2_0 f23 txchn2_3 f24 vdd f25 rxchclk3 f26 rxoh3 g1 rring1 g2 rgnd1 g3 ttip1 g4 tring0 g5 nc g22 gpio1_2 g23 rxsync3 g24 rxohclk3 g25 rxcrcsync3 g26 rxchn3_0 h1 rtip2 h2 rvdd2 h3 tvdd1 h4 tring1 h5 tgnd0 h22 vss h23 rxcasync3 h24 rxlos3 h25 rxserclk3 t able 1: 420 b all l ist by b all n umber p in p in n ame h26 rxchn3_1 j1 rring2 j2 rgnd2 j3 ttip2 j4 tvdd2 j5 tgnd1 j22 txchclk3 j23 rxchn3_2 j24 vdd18 j25 txoh3 j26 rxchn3_3 k1 rtip3 k2 rvdd3 k3 ttip3 k4 tring2 k5 tgnd2 k22 txsync3 k23 txohclk3 k24 txserclk3 k25 rxchn3_4 k26 txser3 l1 rring3 l2 rgnd3 l3 tvdd3 l4 tring3 l5 tgnd3 l22 txchn3_0 l23 vss l24 txmsync3 l25 txchn3_1 l26 cs m1 rtip4 t able 1: 420 b all l ist by b all n umber p in p in n ame m2 rvdd4 m3 ttip4 m4 tring4 m5 tgnd4 m22 txchn3_2 m23 wr m24 txchn3_3 m25 data7 m26 txchn3_4 n1 rring4 n2 rgnd4 n3 tvdd4 n4 nc n5 tgnd5 n22 addr14 n23 addr13 n24 data6 n25 data5 n26 vdd p1 rtip5 p2 rvdd5 p3 ttip5 p4 tring5 p5 nc p22 addr11 p23 blast p24 data4 p25 addr12 p26 vss r1 rring5 r2 rgnd5 r3 tvdd5 t able 1: 420 b all l ist by b all n umber p in p in n ame r4 tring6 r5 tgnd6 r22 ale r23 addr9 r24 addr10 r25 ptype2 r26 int t1 rtip6 t2 rvdd6 t3 ttip6 t4 tvdd6 t5 tgnd7 t22 addr7 t23 vdd18 t24 addr8 t25 data2 t26 data3 u1 rring6 u2 rgnd6 u3 ttip7 u4 tring7 u5 nc u22 addr2 u23 addr3 u24 addr4 u25 addr5 u26 addr6 v1 rtip7 v2 rvdd7 v3 tvdd7 v4 nc v5 nc t able 1: 420 b all l ist by b all n umber p in p in n ame
xrt86vl38 8 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description v22 vss v23 dben v24 rdy v25 addr0 v26 addr1 w1 rring7 w2 rgnd7 w3 nc w4 nc w5 nc w22 iaddr w23 ptype0 w24 data1 w25 rd w26 ptype1 y1 vss y2 vdd y3 txon y4 reset y5 e1oscclk y22 rxohclk4 y23 ack0 y24 ack1 y25 pclk y26 data0 aa1 vss aa2 8kextosc aa3 nc aa4 nc aa5 nc aa22 rxoh4 aa23 vss t able 1: 420 b all l ist by b all n umber p in p in n ame aa24 req1 aa25 vdd aa26 faddr ab1 lop ab2 txchclk7 ab3 8ksync ab4 txchn7_4 ab5 txserclk7 ab6 rxserclk7 ab7 rxser7 ab8 rxchn7_0 ab9 txser6 ab10 txchn6_0 ab11 rxsync6 ab12 rxserclk6 ab13 rxchn6_1 ab14 txchn5_3 ab15 txser5 ab16 txohclk5 ab17 rxchn5_2 ab18 gpio0_2 ab19 vss ab20 vdd18 ab21 txser4 ab22 rxchn4_4 ab23 vss ab24 rxchclk4 ab25 rxcrcsync4 ab26 req0 ac1 t1oscclk ac2 txoh7 ac3 txchn7_3 t able 1: 420 b all l ist by b all n umber p in p in n ame ac4 vdd ac5 txchn7_0 ac6 rxsync7 ac7 rxchn7_1 ac8 txmsync6 ac9 rxcasync6 ac10 txohclk6 ac11 vdd ac12 rxlos6 ac13 rxchn6_0 ac14 txchn5_4 ac15 txchn5_0 ac16 vss ac17 rxchn5_3 ac18 rxser5 ac19 rxserclk5 ac20 txchn4_2 ac21 txmsync4 ac22 vss ac23 rxchn4_3 ac24 vdd18 ac25 rxser4 ac26 rxlos4 ad1 vdd18 ad2 txchn7_2 ad3 txchn7_1 ad4 rxlos7 ad5 rxcrcsync7 ad6 vss ad7 vdd18 ad8 txsync6 ad9 vss t able 1: 420 b all l ist by b all n umber p in p in n ame ad10 txchclk6 ad11 gpio0_0 ad12 rxchn6_3 ad13 gpio0_1 ad14 txoh5 ad15 txchn5_1 ad16 txmsync5 ad17 rxchn5_4 ad18 rxchn5_0 ad19 txchn4_4 ad20 gpio0_3 ad21 txchn4_0 ad22 txchclk4 ad23 vdd ad24 rxcasync4 ad25 rxchn4_0 ad26 rxserclk4 ae1 txohclk7 ae2 vss ae3 txser7 ae4 txsync7 ae5 rxchn7_3 ae6 txserclk6 ae7 rxohclk7 ae8 txchn6_4 ae9 txchn6_2 ae10 rxcrcsync6 ae11 rxchclk6 ae12 rxser6 ae13 rxohclk6 ae14 rxoh6 ae15 txchn5_2 t able 1: 420 b all l ist by b all n umber p in p in n ame
xrt86vl38 9 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 ae16 txchclk5 ae17 rxoh5 ae18 vdd ae19 rxcasync5 ae20 txchn4_3 ae21 rxchclk5 ae22 gpio1_0 ae23 txserclk4 ae24 gpio1_1 ae25 rxchn4_1 ae26 rxsync4 af1 nc af2 txmsync7 af3 rxchn7_4 af4 rxchn7_2 af5 rxchclk7 af6 rxcasync7 af7 rxoh7 af8 txchn6_3 af9 txchn6_1 af10 txoh6 af11 rxchn6_4 af12 rxchn6_2 af13 vss af14 vdd18 af15 txserclk5 af16 txsync5 af17 rxohclk5 af18 rxchn5_1 af19 rxsync5 af20 rxlos5 af21 rxcrcsync5 t able 1: 420 b all l ist by b all n umber p in p in n ame af22 txchn4_1 af23 txohclk4 af24 txsync4 af25 txoh4 af26 rxchn4_2 t able 1: 420 b all l ist by b all n umber p in p in n ame
xrt86vl38 10 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description t able 2: 484 b all l ist by b all n umber p in p in n ame a2 avdd_lv a4 e1mclkout a5 mclkin a6 trst a7 rxchn0_0 a8 rxsync0 a9 txmsync0 a10 txohclk0 a11 txchn0_1 a12 rxserclk1 a13 txchn0_4 a14 rxoh1 a15 rxchn1_3 a16 txchclk1 a17 txohclk1 a18 rxsync2 a19 gpio1_3 a20 rxcrcsync2 a21 rxohclk2 b1 vddpll18 b3 agnd b5 dgnd b6 tms b7 rxser0 b8 rxcrcsync0 b9 txsync0 b10 rxchn0_4 b11 txchn0_0 b12 rxcrcsync1 b13 rxchn1_0 b14 rxcasync1 b15 txmsync1 b16 txoh1 b17 txserclk1 b18 rxserclk2 b19 rxchn2_0 b20 rxchclk2 b21 rxchn2_4 b22 txohclk2 c1 vddpll18 c2 jtag_ring c6 rxtsel c7 atest c8 rxlos0 c9 rxchn0_1 c10 rxcasync0 c11 txserclk0 c12 txchclk0 c13 rxchn1_1 c14 rxlos1 c15 txser1 c16 txchn1_0 c17 txchn1_3 c18 rxcasync2 c19 rxchn2_1 c20 txsync2 c21 txchn2_0 c22 txchn2_4 d1 gndpll18 d2 vddpll18 d3 gndpll18 d4 analog d8 tdo t able 2: 484 b all l ist by b all n umber p in p in n ame d9 rxserclk0 d10 rxchn0_2 d11 rxoh0 d12 txchn0_2 d13 rxchn1_2 d14 rxohclk1 d15 txchn1_1 d16 rxlos2 d17 rxser2 d18 rxoh2 d19 rxchn2_3 d20 txser2 d21 txchn2_3 d22 rxsync3 e1 rvdd0 e2 gndpll18 e3 vddpll18 e4 gndpll18 e5 jtag_tip e6 sense e9 tdi e10 rxchclk0 e11 rxchn0_3 e12 test e13 txoh0 e14 rxser1 e15 rxchclk1 e16 rxsync1 e17 txserclk2 e18 txmsync2 e19 txchclk2 e20 txchn2_1 t able 2: 484 b all l ist by b all n umber p in p in n ame e21 txoh2 e22 rxohclk3 f1 tring0 f2 tvdd0 f3 ttip_0 f4 rgnd0 f5 dvdd18 f9 t1mclkout f10 tck f11 rxohclk0 f12 txser0 f13 txchn0_3 f14 txsync1 f15 txchn1_2 f16 rxchn1_4 f17 rxchn2_2 f19 txchn2_2 f20 rxser3 f21 rxcasync3 f22 rxlos3 g1 tvdd1 g2 rtip0 g3 rring0 g4 tgnd0 g17 txchn1_4 g18 gpio1_2 g19 rxchclk3 g20 rxcrcsync3 g21 rxchn3_1 g22 txchclk3 h1 rring1 h2 rtip1 t able 2: 484 b all l ist by b all n umber p in p in n ame
xrt86vl38 11 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 h3 rgnd1 h4 ttip1 h5 rvdd1 h18 rxoh3 h19 rxchn3_0 h20 rxserclk3 h21 rxchn3_3 h22 txohclk3 j1 tring2 j2 tvdd2 j3 ttip2 j4 rgnd2 j5 tring1 j6 tgnd1 j18 txoh3 j19 rxchn3_2 j20 txsync3 j21 txserclk3 j22 rxchn3_4 k1 ttip3 k2 rgnd3 k3 rring2 k4 rtip2 k5 tgnd2 k6 rvdd2 k17 txchn3_1 k18 txser3 k19 txchn3_0 k20 txmsync3 k21 cs k22 txchn3_2 l1 rring3 t able 2: 484 b all l ist by b all n umber p in p in n ame l2 rtip3 l3 tvdd3 l4 tring3 l5 tgnd3 l6 rvdd3 l17 txchn3_4 l18 addr13 l19 txchn3_3 l20 wr l21 data7 l22 addr14 m1 rring4 m2 rtip4 m3 tring4 m4 rgnd4 m5 ttip4 m6 tvdd4 m7 rvdd4 m17 blast m18 addr11 m19 addr12 m20 data5 m21 data6 m22 data4 n1 tvdd5 n2 ttip5 n3 rgnd5 n4 rvdd5 n5 tgnd4 n17 addr1 n18 data3 n19 addr9 t able 2: 484 b all l ist by b all n umber p in p in n ame n20 addr10 n21 ptype2 n22 int p1 rgnd6 p2 rring5 p3 rtip5 p4 tgnd5 p5 tring5 p18 addr0 p19 addr7 p20 addr8 p21 data2 p22 ale r1 tgnd6 r2 tring6 r3 tvdd6 r4 ttip6 r5 rvdd6 r18 iaddr r19 rdy r20 addr4 r21 addr5 r22 addr6 t1 ttip7 t2 rtip6 t3 rring6 t4 rgnd7 t5 rvdd7 t18 faddr t19 data0 t20 ptype1 t21 addr2 t able 2: 484 b all l ist by b all n umber p in p in n ame t22 addr3 u1 tvdd7 u2 tring7 u3 rring7 u4 rtip7 u5 8kextosc u7 txchn7_4 u8 rxlos7 u9 txserclk6 u10 txser6 u11 txoh6 u12 rxoh6 u13 txohclk5 u14 rxchn5_0 u15 txchn4_1 u16 gpio0_3 u17 txmsync4 u18 rxchclk4 u19 req0 u20 data1 u21 rd u22 dben v1 tgnd7 v2 lop v3 t1oscclk v4 e1oscclk v5 txchclk7 v6 txohclk7 v7 txserclk7 v8 txchn7_1 v9 rxcrcsync7 v10 rxoh7 t able 2: 484 b all l ist by b all n umber p in p in n ame
xrt86vl38 12 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description v11 txchclk6 v12 rxchn6_1 v13 txsync5 v14 rxchn5_3 v15 gpio0_2 v16 rxserclk5 v17 rxcasync4 v18 rxoh4 v19 rxohclk4 v20 ptype0 v21 ack1 v22 pclk w1 txon w2 8ksync w3 txser7 w4 txchn7_0 w5 txmsync7 w6 rxserclk7 w7 rxchn7_4 w8 rxchn7_1 w9 txchn6_4 w10 rxcasync7 w11 txchn6_0 w12 rxserclk6 w13 txchn5_2 w14 rxchn5_4 w15 rxlos5 w16 txchn4_0 w17 txoh4 w18 rxchn4_2 w19 rxser4 w20 rxserclk4 t able 2: 484 b all l ist by b all n umber p in p in n ame w21 rxlos4 w22 ack0 y1 reset y2 txchn7_3 y3 rxsync7 y4 rxchn7_2 y5 rxchclk7 y6 rxohclk7 y7 rxchn7_0 y8 rxcasync6 y9 rxcrcsync6 y10 rxlos6 y11 gpio0_1 y12 txchn5_3 y13 txchclk5 y14 rxoh5 y15 rxsync5 y16 txchn4_2 y17 txsync4 y18 txserclk4 y19 rxchn4_4 y20 rxsync4 y21 rxcrcsync4 y22 req1 aa1 txoh7 aa2 txsync7 aa3 rxchn7_3 aa4 txsync6 aa5 txchn6_2 aa6 rxsync6 aa7 txohclk6 aa8 rxchclk6 t able 2: 484 b all l ist by b all n umber p in p in n ame aa9 rxser6 aa10 rxchn6_0 aa11 txoh5 aa12 txserclk5 aa13 txser5 aa14 rxohclk5 aa15 rxser5 aa16 txchn4_4 aa17 rxcrcsync5 aa18 gpio1_0 aa19 txchclk4 aa20 gpio1_1 aa21 rxchn4_1 aa22 rxchn4_0 ab1 txchn7_2 ab2 rxser7 ab3 txmsync6 ab4 txchn6_3 ab5 txchn6_1 ab6 gpio0_0 ab7 rxchn6_4 ab8 rxchn6_3 ab9 rxchn6_2 ab10 rxohclk6 ab11 txchn5_4 ab12 txchn5_1 ab13 txchn5_0 ab14 txmsync5 ab15 rxchn5_2 ab16 rxchn5_1 ab17 rxcasync5 ab18 txchn4_3 t able 2: 484 b all l ist by b all n umber p in p in n ame ab19 rxchclk5 ab20 txohclk4 ab21 txser4 ab22 rxchn4_3 power pins pin pin name g11 vdd18 g14 vdd18 g16 vdd18 j17 vdd18 p17 vdd18 t8 vdd18 t10 vdd18 t12 vdd18 t14 vdd18 t17 vdd18 g10 vdd g12 vdd g15 vdd h17 vdd l16 vdd r17 vdd t7 vdd t9 vdd t11 vdd t13 vdd t15 vdd ground pins pin pin name f6 vss g6 vss g7 vss t able 2: 484 b all l ist by b all n umber p in p in n ame
xrt86vl38 13 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 g8 vss g9 vss g13 vss h6 vss h7 vss h16 vss j7 vss j16 vss k7 vss k16 vss l7 vss m16 vss n6 vss n7 vss n16 vss p6 vss p7 vss p16 vss r6 vss r7 vss r16 vss t6 vss t16 vss u6 vss h8 vss h9 vss h10 vss h11 vss h12 vss h13 vss h14 vss h15 vss t able 2: 484 b all l ist by b all n umber p in p in n ame j8 vss j9 vss j10 vss j11 vss j12 vss j13 vss j14 vss j15 vss k8 vss k9 vss k10 vss k11 vss k12 vss k13 vss k14 vss k15 vss l8 vss l9 vss l10 vss l11 vss l12 vss l13 vss l14 vss l15 vss m8 vss m9 vss m10 vss m11 vss m12 vss m13 vss m14 vss m15 vss t able 2: 484 b all l ist by b all n umber p in p in n ame n8 vss n9 vss n10 vss n11 vss n12 vss n13 vss n14 vss n15 vss p8 vss p9 vss p10 vss p11 vss p12 vss p13 vss p14 vss p15 vss r8 vss r9 vss r10 vss r11 vss r12 vss r13 vss r14 vss r15 vss no connect pins a1 nc a3 nc a22 nc b2 nc c3 nc c4 nc c5 nc t able 2: 484 b all l ist by b all n umber p in p in n ame d5 nc d6 nc d7 nc e7 nc e8 nc f7 nc f8 nc g5 nc b4 nc f18 nc t able 2: 484 b all l ist by b all n umber p in p in n ame
xrt86vl38 14 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description 2.0 pin descriptions there are six types of pins defined throughout this pin description and the corresponding symbol is presented in table below. the per-channel pin is indicated by the channel number or the letter ?n? which is appended at the end of the signal name, for example, txsern, where "n" indicates channels 0 to 7. all output pins are "tri- stated" upon hardware r eset. the structure of the pin description is divided into fourteen groups, as presented in the table below t able 3: p in d escription s tructure s ection p age n umber transmit system side inter - face page 15 transmit overhead inter - face page 23 receive overhead interface page 25 receive system side inter - face page 26 receive line interface page 34 transmit line interface page 35 timing interface page 36 gpio interface page 38 jtag interface page 39 microprocessor interface page 40 power pins (3.3v) page 49 power pins (1.8v) page 50 ground pins page 51 no connect pins page 53 s ymbol p in t ype i input ooutput i/o bidirectional gnd ground pwr power nc no connect
xrt86vl38 15 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 transmit system side interface s ignal n ame 420 p kg b all # 484 p kg b all # t ype o utput d rive ( m a) d escription txser0/ txpos0 txser1/ txpos1 txser2/ txpos2 txser3/ txpos3 txser4/ txpos4 txser5/ txpos5 txser6/ txpos6 txser7/ txpos7 d11 d17 e23 k26 ab21 ab15 ab9 ae3 f12 c15 d20 k18 ab21 aa13 u10 w3 i - transmit serial data input (txsern)/transmit positive digital input (txposn): the exact function of these pins depends on the mode of operation selected, as described below. ds1/e1 mode - txsern these pins function as the transmit serial data input on the system side interface, which are latched on the rising edge of the txserclkn pin. any payload data applied to this pin will be inserted into an outbound ds1/e1 frame and output to the line. in ds1 mode, the framing alignment bits, facility data link bits, crc-6 bits, and signaling information can also be inserted from this input pin if configured appropriately. in e1 mode, all data intended to be transported via time slots 1 through 15 and time slots 17 through 31 must be applied to this input pin. data intended for time slots 0 and 16 can also be applied to this input pin if configured accordingly. ds1 or e1 high-speed multiplexed mode* - txsern in this mode, these pins are used as the high-speed multi - plexed data input pin on the system side. high-speed multi - plexed data of channels 0-3 must be applied to txser0 and high-speed multiplexed data of channels 4-7 must be applied to txser4 in a byte or bit-interleaved way. the framer latches in the multiplexed data on txser0 and txser4 using txm - sync/txinclk and demultiplexes this data into 4 serial streams. the liu block will then output the data to the line interface using txserclkn. ds1 or e1 framer bypass mode - txposn in this mode, txsern is used for the positive digital input pin (txposn) to the liu. n ote : 1. *high-speed multiplexed modes include (for t1/e1) 16.384mhz hmvip, h.100, bit-multiplexed modes, and (for t1 only) 12.352mhz bit-multiplexed mode. 2. in ds1 high-speed modes, the ds-0 data is mapped into an e1 frame by ignoring every fourth time slot (don?t care). 3. these 8 pins are internally pulled ?high? for each channel.
xrt86vl38 16 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description txserclk0/ txlineclk0 txserclk1/ txlineclk1 txserclk2/ txlineclk2 txserclk3/ txlineclk3 txserclk4/ txlineclk4 txserclk5/ txlineclk5 txserclk6/ txlineclk6 txserclk7/ txlineclk7 a11 c19 d22 k24 ae23 af15 ae6 ab5 c11 b17 e17 j21 y18 aa12 u9 v7 i/o 12 transmit serial clock (txserclkn)/transmit line clock (txserclkn): the exact function of these pins depends on the mode of operation selected, as described below. in base-rate mode (1.544mhz/2.048mhz) - txserclkn: this clock signal is used by the transmit serial interface to latch the contents on the txsern pins into the t1/e1 framer on the rising edge of the txserclkn. these pins can be con - figured as input or output as described below. when txserclkn is configured as input: these pins will be inputs if the txserclk is chosen as the timing source for the transmit framer. users must provide a 1.544mhz clock rate to this input pin for t1 mode of operation, and 2.048mhz clock rate in e1 mode. when txserclkn is configured as output: these pins will be outputs if either the recovered line clock or the mclk pll is chosen as the timing source for the t1/e1 transmit framer. the transmit framer will output a 1.544mhz clock rate in t1 mode of operation, and a 2.048mhz clock rate in e1 mode. ds1/e1 high-speed backplane modes* - txserclkn as input only in this mode, txserclk is an optional clock signal input which is used as the timing source for the transmit line inter - face, and is only required if txserclk is chosen as the tim - ing source for the transmit framer. if txserclk is chosen as the timing source, system equipment should provide 1.544mhz (for t1 mode) or 2.048mhz (for e1 mode) to the txserclkn pins on each channel. txserclk is not required if either the recovered clock or mclk pll is chosen as the timing source of the device. high speed or multiplexed data is latched into the device using the txmsync/txinclk high-speed clock signal. ds1 or e1 framer bypass mode - txlineclkn in this mode, txserclkn is used as the transmit line clock (txlineclk) to the liu. n ote : *high-speed backplane modes include (for t1/e1) 2.048mvip, 4.096mhz, 8.192mhz, 16.384mhz hmvip, h.100, bit-multiplexed modes, and (for t1 only) 12.352mhz bit-multiplexed mode. n ote : in ds1 high-speed modes, the ds-0 data is mapped into an e1 frame by ignoring every fourth time slot (don?t care). n ote : these 8 pins are internally pulled ?high? for each channel. transmit system side interface s ignal n ame 420 p kg b all # 484 p kg b all # t ype o utput d rive ( m a) d escription
xrt86vl38 17 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 txsync0/ txneg0 txsync1/ txneg1 txsync2/ txneg2 txsync3/ txneg3 txsync4/ txneg4 txsync5/ txneg5 txsync6/ txneg6 txsync7/ txneg7 a9 c16 b24 k22 af24 af16 ad8 ae4 b9 f14 c20 j20 y17 v13 aa4 aa2 i/o 12 transmit single frame sync pulse (txsyncn) / transmit negative digital input (txnegn): the exact function of these pins depends on the mode of operation selected, as described below. ds1/e1 base rate mode (1.544mhz/2.048mhz) - txsyncn: these txsyncn pins are used to indicate the single frame boundary within an outbound t1/e1 frame. in both ds1 or e1 mode, the single frame boundary repeats every 125 microsec - onds (8khz). in ds1/e1 base rate, txsyncn can be configured as either input or output as described below. when txsyncn is configured as an input : users must provide a signal which must pulse "high" for one period of txserclk during the first bit of an outbound ds1/ e1 frame. it is imperative that the txsync input signal be syn - chronized with the txserclk input signal. when txsyncn is configured as an output: the transmit t1/e1 framer will output a signal which pulses "high" for one period of txserclk during the first bit of an outbound ds1/e1 frame. ds1/e1 high-speed backplane modes* - txsyncn as input only: in this mode, txsyncn must be an input regardless of the clock source that is chosen to be the timing source for the transmit framer. in 2.048mvip/4.096/8.192mhz high-speed modes, txsyncn pins must be pulsed ?high? for one period of txserclk during the first bit of the outbound t1/e1 frame. in hmvip mode, txsync0 and txsync4 must be pulsed ?high? for 4 clock cycles of the txmsync/txinclk signal in the position of the first two and the last two bits of a multiplexed frame. in h.100 mode, txsync0 and txsync4 must be pulsed ?high? for 2 clock cycles of the txmsync/txinclk sig - nal in the position of the first and the last bit of a multiplexed frame. ds1 or e1 framer bypass mode - txnegn in this mode, txsyncn is used as the negative digital input pin (txneg) to the liu. n ote : *high-speed backplane modes include (for t1/e1) 2.048mvip, 4.096mhz, 8.192mhz, 16.384mhz hmvip, h.100, bit-multiplexed modes, and (for t1 only) 12.352mhz bit-multiplexed mode. n ote : in ds1 high-speed modes, the ds-0 data is mapped into an e1 frame by ignoring every fourth time slot (don?t care). n ote : these 8 pins are internally pulled ?low? for each channel. transmit system side interface s ignal n ame 420 p kg b all # 484 p kg b all # t ype o utput d rive ( m a) d escription
xrt86vl38 18 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description txmsync0/ txinclk0 txmsync1/ txinclk1 txmsync2/ txinclk2 txmsync3/ txinclk3 txmsync4/ txinclk4 txmsync5/ txinclk5 txmsync6/ txinclk6 txmsync7/ txinclk7 b10 a17 c24 l24 ac21 ad16 ac8 af2 a9 b15 e18 k20 u17 ab14 ab3 w5 i/o 12 multiframe sync pulse (txmsyncn) / transmit input clock (txinclkn) the exact function of these pins depends on the mode of operation selected, as described below. ds1/e1 base rate mode (1.544mhz/2.048mhz) - txm - syncn in this mode, these pins are used to indicate the multi-frame boundary within an outbound ds1/e1 frame. in ds1 esf mode, txmsyncn repeats every 3ms. in ds1 sf mode, txmsyncn repeats every 1.5ms. in e1 mode, txmsyncn repeats every 2ms. if txmsyncn is configured as an input, txmsyncn must pulse "high" for one period of txserclk during the first bit of an outbound ds1/e1 multi-frame. it is imperative that the txmsync input signal be synchronized with the txserclk input signal. if txmsyncn is configured as an output, the transmit section of the t1/e1 framer will output and pulse txmsync "high" for one period of txserclk during the first bit of an outbound ds1/e1 frame. ds1/e1 high-speed backplane modes* - (txinclkn as input only) in this mode, this pin must be used as the high-speed input clock pin (txinclkn) for the backplane interface to latch in high-speed or multiplexed data on the txsern pin. the fre - quency of txinclk is presented in the table below. n otes : 1. *high-speed backplane modes include (for t1/e1) 2.048mvip, 4.096mhz, 8.192mhz, 16.384mhz hmvip, h.100, bit-multiplexed modes, and (for t1 only) 12.352mhz bit-multiplexed mode. 2. in ds1 high-speed modes, the ds-0 data is mapped into an e1 frame by ignoring every fourth time slot (don?t care). 3. these 8 pins are internally pulled ?low? for each channel. transmit system side interface s ignal n ame 420 p kg b all # 484 p kg b all # t ype o utput d rive ( m a) d escription o peration m ode f requency of t x inclk(mh z ) 2.048mvip non-multiplexed 2.048 4.096mhz non-multiplexed 4.096 8.192mhz non-multiplexed 8.192 12.352mhz bit-multiplexed (ds1 only) 12.352 16.384mhz bit-multiplexed 16.384 16.384 hmvip byte-multiplexed 16.384 16.384 h.100 byte-multiplexed 16.384
xrt86vl38 19 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 txchclk0 txchclk1 txchclk2 txchclk3 txchclk4 txchclk5 txchclk6 txchclk7 a12 e17 b26 j22 ad22 ae16 ad10 ab2 c12 a16 e19 g22 aa19 y13 v11 v5 o 8 transmit channel clock output signal (txchclkn): the exact function of this pin depends on whether or not the transmit framer enables the transmit fractional/signaling inter - face to input fractional data, as described below. if transmit fractional/signaling interface is disabled: this pin indicates the boundary of each time slot of an out - bound ds1/e1 frame. in t1 mode, each of these output pins is a 192khz clock which pulses "high" during the lsb of each 24 time slots. in e1 mode, each of these output pins is a 256khz clock which pulses "high" during the lsb of each 32 time slots. the terminal equipment can use this clock signal to sample the txchn0 through txchn4 time slot identifier pins to determine which time slot is being processed. if transmit fractional/signaling interface is enabled: txchclkn is the fractional interface clock which either out - puts a clock signal for the time slot that has been configured to input fractional data, or outputs an enable signal for the frac - tional time slot so that fractional data can be clocked into the device using the txserclk pin. n ote : transmit fractional interface can be enabled by programming to bit 4 - txfr1544/txfr2048 bit from register 0xn120 to ?1?. transmit system side interface s ignal n ame 420 p kg b all # 484 p kg b all # t ype o utput d rive ( m a) d escription
xrt86vl38 20 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description txchn0_0/ txsig0 txchn1_0/ txsig1 txchn2_0/ txsig2 txchn3_0/ txsig3 txchn4_0/ txsig4 txchn5_0/ txsig5 txchn6_0/ txsig6 txchn7_0/ txsig7 d12 c18 f22 l22 ad21 ac15 ab10 ac5 b11 c16 c21 k19 w16 ab13 w11 w4 i/o 8 transmit time slot octet identifier output 0 (txchnn_0) / transmit serial signaling input (txsign): the exact function of these pins depends on whether or not the transmit framer enables the transmit fractional/signaling interface, as described below: if transmit fractional/signaling interface is disabled - txchnn_0: these output pins (txchnn_4 through txchnn_0) reflect the five-bit binary value of the current time slot being processed by the transmit serial interface. terminal equipment can use the txchclk to sample the five output pins of each channel in order to identify the time slot being processed. this pin indi - cates the least significant bit (lsb) of the time slot channel being processed. if transmit fractional/signaling interface is enabled - txsign: these pins can be used to input robbed-bit signaling data to be inserted within an outbound ds1 frame or to input channel associated signaling (cas) data within an outbound e1 frame, as described below. t1 mode: signaling data (a,b,c,d) of each channel must be provided on bit 4,5,6,7 of each time slot on the txsig pin if 16- code signaling is used. if 4-code signaling is selected, signal - ing data (a,b) of each channel must be provided on bit 4, 5 of each time slot on the txsig pin. if 2-code signaling is selected, signaling data (a) of each channel must be provided on bit 4 of each time slot on the txsig pin. e1 mode: signaling data in e1 mode can be provided on the txsign pins on a time-slot-basis as in t1 mode, or it can be provided on time slot 16 only via the txsign input pins. in the latter case, signaling data (a,b,c,d) of channel 1 and channel 17 must be inserted on the txsign pin during time slot 16 of frame 1, signaling data (a,b,c,d) of channel 2 and channel 18 must be inserted on the txsign pin during time slot 16 of frame 2...etc. the cas multiframe alignments bits (0000 bits) and the extra bits/alarm bit (xyxx) must be inserted on the txsign pin during time slot 16 of frame 0. n ote : transmit fractional interface can be enabled by programming to bit 4 - txfr1544/txfr2048 bit from register 0xn120 to ?1?. n ote : these 8 pins are internally pulled ?low? for each channel. transmit system side interface s ignal n ame 420 p kg b all # 484 p kg b all # t ype o utput d rive ( m a) d escription
xrt86vl38 21 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 txchn0_1/ txfrtd0 txchn1_1/ txfrtd1 txchn2_1/ txfrtd2 txchn3_1/ txfrtd3 txchn4_1/ txfrtd4 txchn5_1/ txfrtd5 txchn6_1/ txfrtd6 txchn7_1/ txfrtd7 b12 d18 d25 l25 af22 ad15 af9 ad3 a11 d15 e20 k17 u15 ab12 ab5 v8 i/o 8 transmit time slot octet identifier output 1 (txchnn_1) / transmit serial fractional input (txfrtdn): the exact function of these pins depends on whether or not the transmit framer enables the transmit fractional/signaling interface, as described below: if transmit fractional/signaling interface is disabled - txchnn_1 these output signals (txchnn_4 through txchnn_0) reflect the five-bit binary value of the current time slot being pro - cessed by the transmit serial interface. terminal equipment can use the txchclk to sample the five output pins of each channel in order to identify the time slot being processed. this pin indicates bit 1 of the time slot channel being processed. if transmit fractional/signaling interface is enabled - txfrtdn these pins are used as the fractional data input pins to input fractional ds1/e1 payload data which will be inserted within an outbound ds1/e1 frame. in this mode, terminal equipment can use either txchclk or txserclk to clock in fractional ds1/e1 payload data depending on the framer configuration. n otes : 1. transmit fractional/signaling interface can be enabled by programming to bit 4 - txfr1544/ txfr2048 bit from register 0xn120 to ?1?. 2. these 8 pins are internally pulled ?low? for each channel. txchn0_2/ tx32mhz0 txchn1_2/ tx32mhz1 txchn2_2/ tx32mhz2 txchn3_2/ tx32mhz3 txchn4_2/ tx32mhz4 txchn5_2/ tx32mhz5 txchn6_2/ tx32mhz6 txchn7_2/ tx32mhz7 a13 b19 c26 m22 ac20 ae15 ae9 ad2 d12 f15 f19 k22 y16 w13 aa5 ab1 o 8 transmit time slot octet identifier output 2 (txchnn_2) / transmit 32.678mhz clock output (tx32mhz): the exact function of these pins depends on whether or not the transmit framer enables the transmit fractional/signaling interface, as described below: if transmit fractional/signaling interface is disabled - txchnn_2 these output signals (txchnn_4 through txchnn_0) reflect the five-bit binary value of the current time slot being pro - cessed by the transmit serial interface. terminal equipment can use the txchclk to sample the five output pins of each channel in order to identify the time slot being processed. this pin indicates bit 2 of the time slot channel being processed. if transmit fractional/signaling interface is enabled - tx32mhz these pins are used to output a 32.678mhz clock reference which is derived from the mclkin input pin. n ote : transmit fractional interface can be enabled by programming to bit 4 - txfr1544/txfr2048 bit from register 0xn120 to ?1?. transmit system side interface s ignal n ame 420 p kg b all # 484 p kg b all # t ype o utput d rive ( m a) d escription
xrt86vl38 22 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description txchn0_3/ txohsync0 txchn1_3/ txohsync1 txchn2_3/ txohsync2 txchn3_3/ txohsync3 txchn4_3/ txohsync4 txchn5_3/ txohsync5 txchn6_3/ txohsync6 txchn7_3/ txohsync7 e13 a20 f23 m24 ae20 ab14 af8 ac3 f13 c17 d21 l19 ab18 y12 ab4 y2 o o 8 transmit time slot octet identifier output 3 (txchnn_3) / transmit overhead synchronization pulse (txohsyncn): the exact function of these pins depends on whether or not the transmit framer enables the transmit fractional/signaling interface, as described below: if transmit fractional/signaling interface is disabled - txchnn_3 these output signals (txchnn_4 through txchnn_0) reflect the five-bit binary value of the current time slot being pro - cessed by the transmit serial interface. terminal equipment can use the txchclk to sample the five output pins of each channel in order to identify the time slot being processed. this pin indicates bit 3 of the time slot channel being processed. if transmit fractional/signaling interface is enabled - txohsyncn these pins are used to output an overhead synchronization pulse which indicates the first bit of each multi-frame. n ote : transmit fractional interface can be enabled by programming to bit 4 - txfr1544/txfr2048 bit from register 0xn120 to ?1?. txchn0_4 txchn1_4 txchn2_4 txchn3_4 txchn4_4 txchn5_4 txchn6_4 txchn7_4 c14 a21 e25 m26 ad19 ac14 ae8 ab4 a13 g17 c22 l17 aa16 ab11 w9 u7 o 8 transmit time slot octet identifier output-bit 4 (txchnn_4): these output signals (txchnn_4 through txchnn_0) reflect the five-bit binary value of the current time slot being pro - cessed by the transmit serial interface. terminal equipment can use the txchclk to sample the five output pins of each channel in order to identify the time slot being processed. this pin indicates the most significant bit (msb) of the time slot channel being processed. transmit system side interface s ignal n ame 420 p kg b all # 484 p kg b all # t ype o utput d rive ( m a) d escription
xrt86vl38 23 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 transmit overhead interface s ignal n ame 420 p kg b all # 484 p kg b all # t ype o utput d rive ( m a) d escription txoh0 txoh1 txoh2 txoh3 txoh4 txoh5 txoh6 txoh7 c12 a18 e26 j25 af25 ad14 af10 ac2 e13 b16 e21 j18 w17 aa11 u11 aa1 i - transmit overhead input (txohn): the exact function of these pins depends on the mode of operation selected, as described below. ds1 mode these pins operate as the source of datalink bits which will be inserted into the datalink bits within an outbound ds1 frame if the framer is configured accordingly. datalink equipment can provide data to this input pin using the txohclkn clock at either 2khz or 4khz depending on the transmit datalink bandwidth selected. n ote : this input pin will be disabled if the framer is using the transmit hdlc controller, or the txser input as the source for the data link bits. e1 mode these pins operate as the source of datalink bits or sig - naling bits depending on the framer configuration, as described below. sourcing datalink bits from txohn: the e1 transmit framer will output a clock edge on txo - hclkn for each sa bit that has been configured to carry datalink information. terminal equipment can then use txohclkn to provide datalink bits on txohn to be inserted into the sa bits within an outbound e1 frame. sourcing signaling bits from txohn: users must provide signaling data on txohn pins on time slot 16 only. signaling data (a,b,c,d) of channel 1 and channel 17 must be inserted on the txohn pin dur - ing time slot 16 of frame 1, signaling data (a,b,c,d) of channel 2 and channel 18 must be inserted on the txohn pin during time slot 16 of frame 2...etc. the cas multiframe alignments bits (0000 bits) and the extra bits/alarm bit (xyxx) must be inserted on the txohn pin during time slot 16 of frame 0. n ote : these 8 pins are internally pulled ?low? for each channel.
xrt86vl38 24 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description txohclk0 txohclk1 txohclk2 txohclk3 txohclk4 txohclk5 txohclk6 txohclk7 e11 a19 e24 k23 af23 ab16 ac10 ae1 a10 a17 b22 h22 ab20 u13 aa7 v6 o 8 transmit oh serial clock output signal(txohclkn) this pin functions as an overhead output clock signal for the transmit overhead interface, and its function is explained below. ds1 mode if the txoh pins have been configured to be the source for datalink bits, the ds1 transmit framer will provide a clock edge for each data link bit. in ds1 esf mode, the txohclk can either be a 2khz or 4khz output sig - nal depending on the selection of data link bandwidth (register 0xn10a). data link equipment can provide data to the txohn pin on the rising edge of txohclk. the framer latches the data on the falling edge of this clock signal. e1 mode if the txoh pins have been configured to be the source for data link bits, the e1 transmit framer will provide a clock edge for each national bit (sa bits) that has been configured to carry data link information. (register 0xn10a) transmit overhead interface s ignal n ame 420 p kg b all # 484 p kg b all # t ype o utput d rive ( m a) d escription
xrt86vl38 25 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 receive overhead interface s ignal n ame 420 p kg b all # 484 p kg b all # t ype o utput d rive ( m a) d escription rxoh0 rxoh1 rxoh2 rxoh3 rxoh4 rxoh5 rxoh6 rxoh7 c11 b15 d21 f26 aa22 ae17 ae14 af7 d11 a14 d18 h18 v18 y14 u12 v10 o 8 receive overhead output (rxohn): these pins function as the receive overhead output, or receive signaling output depending on the receive framer configuration, as described below. ds1 mode if the rxoh pins have been configured as the destina - tion for the data link bits within an inbound ds1 frame, datalink bits will be output to the rxohn pins at either 2khz or 4khz depending on the receive datalink band - width selected. (register 0xn10c). if configured appropriately, signaling information in the receive signaling array registers (registers 0xn500- 0xn51f) can also be output to the rxohn output pins. e1 mode these output pins will always output the contents of the national bits (sa4 through sa8) if these sa bits have been configured to carry data link information (register 0xn10c). the receive overhead output interface will provide a clock edge on rxohclkn for each sa bit car - rying data link information. if configured appropriately, signaling information in the receive signaling array registers (registers 0xn500- 0xn51f) can also be output to the rxohn output pins. rxohclk0 rxohclk1 rxohclk2 rxohclk3 rxohclk4 rxohclk5 rxohclk6 rxohclk7 b9 d16 e21 g24 y22 af17 ae13 ae7 f11 d14 a21 e22 v19 aa14 ab10 y6 o 8 receive overhead clock output (rxohclkn): this pin functions as an overhead output clock signal for the receive overhead interface, and its function is explained below. ds1 mode if the rxoh pins have been configured to be the desti - nation for datalink bits, the ds1 transmit framer will out - put a clock edge for each data link bit. in ds1 esf mode, the rxohclk can either be a 2khz or 4khz out - put signal depending on the selection of data link bandwidth (register 0xn10c). data link equipment can clock out datalink bits on the rxohn pin using this clock signal. e1 mode the e1 receive framer provides a clock edge for each national bit (sa bits) that is configured to carry data link information. data link equipment can clock out datalink bits on the rxohn pin using this clock signal.
xrt86vl38 26 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description receive system side interface s ignal n ame 420 p kg b all # 484 p kg b all # t ype o utput d rive ( m a) d escription rxsync0/ rxneg0 rxsync1/ rxneg1 rxsync2/ rxneg2 rxsync3/ rxneg3 rxsync4/ rxneg4 rxsync5/ rxneg5 rxsync6/ rxneg6 rxsync7/ rxneg7 d9 d15 d19 g23 ae26 af19 ab11 ac6 a8 e16 a18 d22 y20 y15 aa6 y3 i/o 12 receive single frame sync pulse (rxsyncn): the exact function of these pins depends on the mode of operation selected, as described below. ds1/e1 base rate mode (1.544mhz/2.048mhz) - rxsyncn: these rxsyncn pins are used to indicate the single frame boundary within an inbound t1/e1 frame. in both ds1 or e1 mode, the single frame boundary repeats every 125 microseconds (8khz). in ds1/e1 base rate, rxsyncn can be configured as either input or output depending on the slip buffer configu - ration as described below. when rxsyncn is configured as an input : users must provide a signal which must pulse "high" for one period of rxserclk and repeats every 125 s. the receive serial interface will output the first bit of an inbound ds1/e1 frame during the provided rxsync pulse. n ote : it is imperative that the rxsync input signal be synchronized with the rxserclk input signal. when rxsyncn is configured as an output: the receive t1/e1 framer will output a signal which pulses "high" for one period of rxserclk during the first bit of an inbound ds1/e1 frame. ds1/e1 high-speed backplane modes* - rxsyncn as input only: in this mode, rxsyncn must be an input regardless of the slip buffer configuration. in 2.048mvip/4.096/ 8.192mhz high-speed modes, rxsyncn pins must be pulsed ?high? for one period of rxserclk during the first bit of the inbound t1/e1 frame. in hmvip mode, rxsyncn must be pulsed ?high? for 4 clock cycles of the rxserclk signal in the position of the first two and the last two bits of a multiplexed frame. in h.100 mode, rxsyncn must be pulsed ?high? for 2 clock cycles of the rxserclk signal in the position of the first and the last bit of a multiplexed frame. ds1 or e1 framer bypass mode - rxnegn in this mode, rxsyncn is used as the receive negative digital output pin (rxneg) from the liu. n ote : *high-speed backplane modes include (for t1/ e1) 2.048mvip, 4.096mhz, 8.192mhz, 16.384mhz hmvip, h.100, bit-multiplexed modes, and (for t1 only) 12.352mhz bit- multiplexed mode. n ote : in ds1 high-speed modes, the ds-0 data is mapped into an e1 frame by ignoring every fourth time slot (don?t care). n ote : these 8 pins are internally pulled ?low? for each channel.
xrt86vl38 27 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 rxcrcsync0 rxcrcsync1 rxcrcsync2 rxcrcsync3 rxcrcsync4 rxcrcsync5 rxcrcsync6 rxcrcsync7 b8 d13 e20 g25 ab25 af21 ae10 ad5 b8 b12 a20 g20 y21 aa17 y9 v9 o 12 receive multiframe sync pulse (rxcrcsyncn): the rxcrcsyncn pins are used to indicate the receive multi-frame boundary. these pins pulse "high" for one period of rxserclk when the first bit of an inbound ds1/e1 multi-frame is being output on the rxcrcsyncn pin. ? in ds1 esf mode, rxcrcsyncn repeats every 3ms ? in ds1 sf mode, rxcrcsyncn repeats every 1.5ms ? in e1 mode, rxcrcsyncn repeats every 2ms. rxcasync0 rxcasync1 rxcasync2 rxcasync3 rxcasync4 rxcasync5 rxcasync6 rxcasync7 e10 e15 a23 h23 ad24 ae19 ac9 af6 c10 b14 c18 f21 v17 ab17 y8 w10 o 12 receive cas multiframe sync pulse (rxcasyncn): - e1 mode only the rxcasyncn pins are used to indicate the e1 cas multif-frame boundary. these pins pulse "high" for one period of rxserclk when the first bit of an e1 cas multi-frame is being output on the rxcasyncn pin. receive system side interface s ignal n ame 420 p kg b all # 484 p kg b all # t ype o utput d rive ( m a) d escription
xrt86vl38 28 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description rxserclk0/ rxlineclk0 rxserclk1/ rxlineclk1 rxserclk2/ rxlineclk2 rxserclk3/ rxlineclk3 rxserclk4/ rxlineclk4 rxserclk5/ rxlineclk5 rxserclk6/ rxlineclk6 rxserclk7/ rxlineclk7 a6 b13 c20 h25 ad26 ac19 ab12 ab6 d9 a12 b18 h20 w20 v16 w12 w6 i/o 12 receive serial clock signal (rxserclkn) / receive line clock (rxlineclkn): the exact function of these pins depends on the mode of operation selected, as described below. in base-rate mode (1.544mhz/2.048mhz) - rxser - clkn: these pins are used as the receive serial clock on the system side interface which can be configured as either input or output. the receive serial interface outputs data on rxsern on the rising edge of rxserclkn. when rxserclkn is configured as input: these pins will be inputs if the slip buffer on the receive path is enabled. system side equipment must provide a 1.544mhz clock rate to this input pin for t1 mode of oper - ation, and 2.048mhz clock rate in e1 mode. when rxserclkn is configured as output: these pins will be outputs if slip buffer is bypassed. the receive framer will output a 1.544mhz clock rate in t1 mode of operation, and a 2.048mhz clock rate in e1 mode. ds1/e1 high-speed backplane modes* - (rxserclk as input only) in this mode, this pin must be used as the high-speed input clock for the backplane interface to output high- speed or multiplexed data on the rxsern pin. the fre - quency of rxserclk is presented in the table below. n otes : 1. *high-speed backplane modes include (for t1/ e1) 2.048mvip, 4.096mhz, 8.192mhz, 16.384mhz hmvip, h.100, bit-multiplexed modes, and (for t1 only) 12.352mhz bit- multiplexed mode. 2. for ds1 high-speed modes, the ds-0 data is mapped into an e1 frame by ignoring every fourth time slot (don?t care). receive system side interface s ignal n ame 420 p kg b all # 484 p kg b all # t ype o utput d rive ( m a) d escription o peration m ode f requency of r x serclk(mh z ) 2.048mvip non-multiplexed 2.048 4.096mhz non-multiplexed 4.096 8.192mhz non-multiplexed 8.192 12.352mhz bit-multiplexed (ds1 only) 12.352 16.384mhz bit-multiplexed 16.384 16.384 hmvip byte-multiplexed 16.384 16.384 h.100 byte-multiplexed 16.384
xrt86vl38 29 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 rxserclk0/ rxlineclk0 rxserclk1/ rxlineclk1 rxserclk2/ rxlineclk2 rxserclk3/ rxlineclk3 rxserclk4/ rxlineclk4 rxserclk5/ rxlineclk5 rxserclk6/ rxlineclk6 rxserclk7/ rxlineclk7 a6 b13 c20 h25 ad26 ac19 ab12 ab6 d9 a12 b18 h20 w20 v16 w12 w6 i/o 12 (continued) ds1 or e1 framer bypass mode - rxlineclkn in this mode, rxserclkn is used as the receive line clock output pin (rxlineclk) from the liu. n ote : these 8 pins are internally pulled ?high? for each channel. rxser0/ rxpos0 rxser1/ rxpos1 rxser2/ rxpos2 rxser3/ rxpos3 rxser4/ rxpos4 rxser5/ rxpos5 rxser6/ rxpos6 rxser7/ rxpos7 c7 b14 c21 d26 ac25 ac18 ae12 ab7 b7 e14 d17 f20 w19 aa15 aa9 ab2 o 12 receive serial data output (rxsern): the exact function of these pins depends on the mode of operation selected, as described below. ds1/e1 mode - rxsern these pins function as the receive serial data output on the system side interface, which are updated on the rising edge of the rxserclkn pin. all the framing alignment bits, facility data link bits, crc bits, and signaling informa - tion will also be extracted to this output pin. ds1 or e1 high-speed multiplexed mode* - rxsern in this mode, these pins are used as the high-speed multi - plexed data output pin on the system side. high-speed multiplexed data of channels 0-3 will output on rxser0 and high-speed multiplexed data of channels 4-7 will out - put on rxser4 in a byte or bit-interleaved way. the framer outputs the multiplexed data on rxser0 and rxser4 using the high-speed input clock (rxserclkn). ds1 or e1 framer bypass mode in this mode, rxsern is used as the positive digital out - put pin (rxposn) from the liu. n ote : *high-speed multiplexed modes include (for t1/ e1) 16.384mhz hmvip, h.100, bit-multiplexed modes, and (for t1 only) 12.352mhz bit- multiplexed mode. n ote : in ds1 high-speed modes, the ds-0 data is mapped into an e1 frame by ignoring every fourth time slot (don?t care). receive system side interface s ignal n ame 420 p kg b all # 484 p kg b all # t ype o utput d rive ( m a) d escription
xrt86vl38 30 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description rxchn0_0/ rxsig0 rxchn1_0/ rxsig1 rxchn2_0/ rxsig2 rxchn3_0/ rxsig3 rxchn4_0/ rxsig4 rxchn5_0/ rxsig5 rxchn6_0/ rxsig6 rxchn7_0/ rxsig7 d8 d14 a22 g26 ad25 ad18 ac13 ab8 a7 b13 b19 h19 aa22 u14 aa10 y7 o 8 receive time slot octet identifier output (rxchnn_0) / receive serial signaling output (rxsign): the exact function of these pins depends on whether or not the receive framer enables the receive fractional/sig - naling interface, as described below: if receive fractional/signaling interface is disabled - rxchnn_0: these output pins (rxchnn_4 through rxchnn_0) reflect the five-bit binary value of the current time slot being output by the receive serial interface. system equipment can use the rxchclkn to sample the five out - put pins of each channel to identify the time slot being out - put on these pins. rxchnn_0 indicates the least significant bit (lsb) of the time slot channel being output. if receive fractional/signaling interface is enabled - rxsign: these pins can be used to output robbed-bit signaling data within an inbound ds1 frame or to output channel associated signaling (cas) data within an inbound e1 frame, as described below. t1 mode: signaling data (a,b,c,d) of each channel will be output on bit 4,5,6,7 of each time slot on the rxsig pin if 16-code signaling is used. if 4-code signaling is selected, signaling data (a,b) of each channel will be out - put on bit 4, 5 of each time slot on the rxsig pin. if 2- code signaling is selected, signaling data (a) of each channel will be output on bit 4 of each time slot on the rxsig pin. e1 mode: signaling data in e1 mode will be output on the rxsign pins on a time-slot-basis as in t1 mode, or it can be output on time slot 16 only via the rxsign output pins. in the latter case, signaling data (a,b,c,d) of channel 1 and channel 17 will be output on the rxsign pin during time slot 16 of frame 1, signaling data (a,b,c,d) of chan - nel 2 and channel 18 will be output on the rxsign pin during time slot 16 of frame 2...etc. the cas multiframe alignments bits (0000 bits) and the extra bits/alarm bit (xyxx) will be output on the rxsign pin during time slot 16 of frame 0. n ote : receive fractional/signaling interface can be enabled by programming to bit 4 - rxfr1544/ rxfr2048 bit from register 0xn122 to ?1?. receive system side interface s ignal n ame 420 p kg b all # 484 p kg b all # t ype o utput d rive ( m a) d escription
xrt86vl38 31 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 rxchn0_1/ rxfrtd0 rxchn1_1/ rxfrtd1 rxchn2_1/ rxfrtd2 rxchn13_1/ rxfrtd3 rxchn4_1/ rxfrtd4 rxchn5_1/ rxfrtd5 rxchn6_1/ rxfrtd6 rxchn7_1/ rxfrtd7 e9 e14 b22 h26 ae25 af18 ab13 ac7 c9 c13 c19 g21 aa21 ab16 v12 w8 o 8 receive time slot octet identifier output bit 1 (rxchnn_1) / receive serial fractional output (rxfrtdn): the exact function of these pins depends on whether or not the receive framer enables the receive fractional/sig - naling interface, as described below: if receive fractional/signaling interface is disabled - rxchnn_1: these output pins (rxchnn_4 through rxchnn_0) reflect the five-bit binary value of the current time slot being output by the receive serial interface. system equipment can use the rxchclkn to sample the five out - put pins of each channel to identify the time slot being out - put on these pins. rxchnn_1 indicates bit 1 of the time slot channel being output. if receive fractional/signaling interface is enabled - rxfrtdn: these pins are used as the fractional data output pins to output fractional ds1/e1 payload data within an inbound ds1/e1 frame. in this mode, system equipment can use either rxchclk or rxserclk to clock out fractional ds1/e1 payload data depending on the framer configura - tion. n ote : receive fractional/signaling interface can be enabled by programming to bit 4 - rxfr1544/ rxfr2048 bit from register 0xn122 to ?1?. rxchn0_2/ rxchn0 rxchn1_2/ rxchn1 rxchn2_2/ rxchn2 rxchn3_2/ rxchn3 rxchn4_2/ rxchn4 rxchn5_2/ rxchn5 rxchn6_2/ rxchn6 rxchn7_2/ rxchn7 c9 a15 c22 j23 af26 ab17 af12 af4 d10 d13 f17 j19 w18 ab15 ab9 y4 o 8 receive time slot octet identifier output-bit 2 (rxchnn_2) / receive time slot identifier serial out - put (rxchnn): the exact function of these pins depends on whether or not the receive framer enables the receive fractional/sig - naling interface, as described below: if receive fractional/signaling interface is disabled - rxchnn_2: these output pins (rxchnn_4 through rxchnn_0) reflect the five-bit binary value of the current time slot being output by the receive serial interface. system equipment can use the rxchclkn to sample the five out - put pins of each channel to identify the time slot being out - put on these pins. rxchnn_2 indicates bit 2 of the time slot channel being output. if receive fractional/signaling interface is enabled - rxchnn these pins serially output the five-bit binary value of the time slot being output by the receive serial interface. n ote : receive fractional/signaling interface can be enabled by programming to bit 4 - rxfr1544/ rxfr2048 bit from register 0xn122 to ?1?. receive system side interface s ignal n ame 420 p kg b all # 484 p kg b all # t ype o utput d rive ( m a) d escription
xrt86vl38 32 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description rxchn0_3/ rx8khz0 rxchn1_3/ rx8khz1 rxchn2_3/ rx8khz2 rxchn3_3/ rx8khz3 rxchn4_3/ rx8khz4 rxchn5_3/ rx8khz5 rxchn6_3/ rx8khz6 rxchn7_3/ rx8khz7 c10 b16 c23 j26 ac23 ac17 ad12 ae5 e11 a15 d19 h21 ab22 v14 ab8 aa3 o 8 receive time slot octet identifier output-bit 3 (rxchnn_3) / receive 8khz clock output (rx8khzn): the exact function of these pins depends on whether or not the receive framer enables the receive fractional/sig - naling interface, as described below: if receive fractional/signaling interface is disabled - rxchnn_3: these output pins (rxchnn_4 through rxchnn_0) reflect the five-bit binary value of the current time slot being output by the receive serial interface. system equipment can use the rxchclkn to sample the five out - put pins of each channel to identify the time slot being out - put on these pins. rxchnn_3 indicates bit 3 of the time slot channel being output. if receive fractional/signaling interface is enabled - rx8khzn: these pins output a reference 8khz clock signal derived from the mclkin input. n ote : receive fractional/signaling interface can be enabled by programming to bit 4 - rxfr1544/ rxfr2048 bit from register 0xn122 to ?1?. rxchn0_4/ rxsclk0 rxchn1_4/ rxsclk1 rxchn2_4/ rxsclk2 rxchn3_4/ rxsclk3 rxchn4_4/ rxsclk4 rxchn5_4/ rxsclk5 rxchn6_4/ rxsclk6 rxchn7_4/ rxsclk7 a10 c17 a26 k25 ab22 ad17 af11 af3 b10 f16 b21 j22 y19 w14 ab7 w7 o 8 receive time slot octet identifier output-bit 4 (rxchnn_4) / receive recovered line clock output (rxsclkn): the exact function of these pins depends on whether or not the receive framer enables the receive fractional/sig - naling interface, as described below: if receive fractional/signaling interface is disabled - rxchnn_4: these output pins (rxchnn_4 through rxchnn_0) reflect the five-bit binary value of the current time slot being output by the receive serial interface. system equipment can use the rxchclkn to sample the five out - put pins of each channel to identify the time slot being out - put on these pins. rxchnn_4 indicates the most significant bit (msb) of the time slot channel being out - put. if receive fractional/signaling interface is enabled - receive recovered line clock output (rxsclkn): these pins output the recovered t1/e1 line clock (1.544mhz in t1 mode and 2.048mhz in e1 mode) for each channel. n ote : receive fractional/signaling interface can be enabled by programming to bit 4 - rxfr1544/ rxfr2048 bit from register 0xn122 to ?1?. receive system side interface s ignal n ame 420 p kg b all # 484 p kg b all # t ype o utput d rive ( m a) d escription
xrt86vl38 33 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 rxchclk0 rxchclk1 rxchclk2 rxchclk3 rxchclk4 rxchclk5 rxchclk6 rxchclk7 a8 a14 a24 f25 ab24 ae21 ae11 af5 e10 e15 b20 g19 u18 ab19 aa8 y5 o 8 receive channel clock output (rxchclkn): the exact function of this pin depends on whether or not the receive framer enables the receive fractional/signaling interface to output fractional data, as described below. if receive fractional/signaling interface is disabled: this pin indicates the boundary of each time slot of an inbound ds1/e1 frame. in t1 mode, each of these output pins is a 192khz clock which pulses "high" during the lsb of each 24 time slots. in e1 mode, each of these out - put pins is a 256khz clock which pulses "high" during the lsb of each 32 time slots. system equipment can use this clock signal to sample the rxchn0 through rxchn4 time slot identifier pins to determine which time slot is being output. if receive fractional/signaling interface is enabled: rxchclkn is the fractional interface clock which either outputs a clock signal for the time slot that has been con - figured to output fractional data, or outputs an enable sig - nal for the fractional time slot so that fractional data can be clocked out of the device using the rxserclk pin. n ote : receive fractional interface can be enabled by programming to bit 4 - rxfr1544/rxfr2048 bit from register 0xn122 to ?1?. receive system side interface s ignal n ame 420 p kg b all # 484 p kg b all # t ype o utput d rive ( m a) d escription
xrt86vl38 34 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description receive line interface s ignal n ame 420 p kg b all # 484 p kg b all # t ype o utput d rive ( m a) d escription rtip0 rtip1 rtip2 rtip3 rtip4 rtip5 rtip6 rtip7 d1 f1 h1 k1 m1 p1 t1 v1 g2 h2 k4 l2 m2 p3 t2 u4 i - receive positive analog input (rtipn): rtip is the positive differential input from the line inter - face. this input pin, along with the rring input pin, func - tions as the ?receive ds1/e1 line signal? input for the xrt86vl38 device. the user is expected to connect this signal and the rring input signal to a 1:1 transformer for proper opera - tion. the center tap of the receive transformer should have a bypass capacitor of 0.1 f to ground (chip side) to improve long haul application receive capabilities. rring0 rring1 rring2 rring3 rring4 rring5 rring6 rring7 e1 g1 j1 l1 n1 r1 u1 w1 g3 h1 k3 l1 m1 p2 t3 u3 i - receive negative analog input (rringn): rring is the negative differential input from the line inter - face. this input pin, along with the rtip input pin, func - tions as the ?receive ds1/e1 line signal? input for the xrt86vl38 device. the user is expected to connect this signal and the rtip input signal to a 1:1 transformer for proper operation. the center tap of the receive transformer should have a bypass capacitor of 0.1 f to ground (chip side) to improve long haul application receive capabilities. rxlos_0 rxlos_1 rxlos_2 rxlos_3 rxlos_4 rxlos_5 rxlos_6 rxlos_7 e8 a16 b20 h24 ac26 af20 ac12 ad4 c8 c14 d16 f22 w21 w15 y10 u8 o 4 receive loss of signal output indicator (rlosn): the xrt86vl38 device will assert this output pin (i.e., toggle it ?high?) anytime (and for the duration that) the receive ds1/e1 framer or liu block declares the los defect condition. conversely, the xrt86vl38 device will negate this output pin (i.e., toggle it ?low?) anytime (and for the duration that) the receive ds1/e1 framer or liu block is not declaring the los defect condition. this output pin will toggle ?high? (declare los) if the receive framer or the receive liu block associated with channel n determines that an rlos condition occurs. in other words, this pin is or-ed with the liu rlos and the framer rlos bit. if either the liu rlos or the framer rlos bit associated with channel n pulses high, the cor - responding rlos pin of that particular channel will be set to ?high?.
xrt86vl38 35 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 rxtsel d5 c6 i - receive termination control (rxtsel): upon power up, the receivers are in "high" impedance. switching to internal termination can be selected through the microprocessor interface by programming the appro - priate channel register. however, to switch control to the hardware pin, rxtcntl must be programmed to "1" in the appropriate global register (0x0fe2). once control has been granted to the hardware pin, it must be pulled "high" to switch to internal termination. n ote : internally pulled "low" with a 50k resistor. transmit line interface s ignal n ame 420 p kg b all # 484 p kg b all # t ype d escription ttip0 ttip1 ttip2 ttip3 ttip4 ttip5 ttip6 ttip7 f3 g3 j3 k3 m3 p3 t3 u3 f3 h4 j3 k1 m5 n2 r4 t1 o transmit positive analog output (ttipn): ttip is the positive differential output to the line interface. this out - put pin, along with the corresponding tring output pin, function as the transmit ds1/e1 output signal drivers for the xrt86vl38 device. the user is expected to connect this signal and the corresponding tring output signal to a 1:2 step up transformer for proper opera - tion. this output pin will be tri-stated whenever the user sets the ?txon? input pin or register bit (0xnf02, bit 3) to ?0?. n ote : this pin should have a series line capacitor of 0.68 f for dc blocking purposes. tring0 tring1 tring2 tring3 tring4 tring5 tring6 tring7 g4 h4 k4 l4 m4 p4 r4 u4 f1 j5 j1 l4 m3 p5 r2 u2 o transmit negative analog output (tringn): tring is the negative differential output to the line interface. this output pin, along with the corresponding ttip output pin, function as the transmit ds1/e1 output signal drivers for the xrt86vl38 device. the user is expected to connect this signal and the corresponding tring output signal to a 1:2 step up transformer for proper opera - tion. n ote : this output pin will be tri-stated whenever the user sets the ?txon? input pin or register bit (0xnf02, bit 3) to ?0?. receive line interface s ignal n ame 420 p kg b all # 484 p kg b all # t ype o utput d rive ( m a) d escription rxtsel (pin) rx termination external internal 0 1 note: rxtcntl (bit) must be set to "1"
xrt86vl38 36 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description txon y3 w1 i transmitter on this input pin permits the user to either enable or disable the trans - mit output driver within the transmit ds1/e1 liu block. if the txon pin is pulled ?low?, all 8 channels are tri-stated. when this pin is pulled ?high?, turning on or off the transmitters will be determined by the appropriate channel registers (address 0x0fn2, bit 3) low = disables the transmit output driver within the transmit ds1/ e1 liu block. in this setting, the ttip and tring output pins of all 8 channels will be tri-stated. high = enables the transmit output driver within the transmit ds1/ e1 liu block. in this setting, the corresponding ttip and tring out - put pins will be e nabled or disabled by programming the appropriate channel register. (address 0x0fn2, bit 3) n ote : whenever the transmitters are turned off, the ttip and tring output pins will be tri-stated. timing interface s ignal n ame 420 p kg b all # 484 p kg b all # t ype o utput d rive ( m a) d escription mclkin a4 a5 i - master clock input: this pin is used to provide the timing reference for the inter - nal master clock of the device. the frequency of this clock is programmable from 8khz to 16.384mhz in register 0x0fe9. e1mclknout b5 a4 o 12 liu e1 output clock reference this output pin is defaulted to 2.048mhz, but can be pro - grammed to 4.096mhz, 8.192mhz, or 16.384mhz in regis - ter 0x0fe4. t1mclknout d6 f9 o 12 liu t1 output clock reference this output pin is defaulted to 1.544mhz, but can be pro - grammed to output 3.088mhz, 6.176mhz, or 12.352mhz in register 0x0fe4. e1oscclk y5 v4 o 8 framer e1 output clock reference this output pin is defaulted to 2.048mhz, but can be pro - grammed to 65.536mhz in register 0x011e. t1oscclk ac1 v3 o 8 framer t1 output clock reference this output pin is defaulted to 1.544mhz, but can be pro - grammed to output 49.408mhz in register 0x011e. 8ksync ab3 w2 o 8 8khz clock output reference this pin is an output reference of 8khz based on the mclkin input. therefore, the duty cycle of this output is determined by the time period of the input clock reference. transmit line interface s ignal n ame 420 p kg b all # 484 p kg b all # t ype d escription
xrt86vl38 37 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 8kextosc aa2 u5 i - external oscillator select for normal operation, this pin should not be used, or pulled ?low?. this pin is internally pulled ?low? with a 50k resistor. analog c5 d4 o factory test mode pin n ote : for internal use only lop ab1 v2 i - loss of power for e1 only this is a loss of power pin in the e1 application only. upon detecting lop in e1 mode, the device will automatically transmit the sa5 and sa6 bit to a different pattern, so that the receive terminal can detect a power failure in the net - work. please see register 0xn131 for the transmit sa control. sense e6 e6 o n ote : for internal use only timing interface s ignal n ame 420 p kg b all # 484 p kg b all # t ype o utput d rive ( m a) d escription
xrt86vl38 38 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description gpio interface s ignal n ame 420 p kg b all # 484p kg b all # t ype o utput d rive ( m a) d escription gpio1_3 gpio1_2 gpio1_1 gpio1_0 b21 g22 ae24 ae22 a19 g18 aa20 aa18 i/o 8 general purpose input/output pins each of these pins can be configured to function as either a general-purpose input or output pin. the exact function of these pins depend on whether these gpio pins are configured as input or output pins as follows. if gpio1_n pins are configured as input pins: the state of these input pins can be monitored by reading the gpio1_n control bits (bit 3-0) within the ?general pur - pose input/output 1 control register (address 0x4102). if gpio1_n pins are configured as output pins: the state of these output pins can be controlled by writing the appropriate value into the gpio1_n control bits (bit 3- 0) within the ?general purpose input/output 1 control register (address 0x4102). finally, users can configure a given gpio1_n pin to be an input pin by setting the corresponding gpio1_ndir bit (from bit 7-4), within the ?general purpose input/output 1 control register (address 0x4102) to ?0?. conversely, users can configure the gpio1_ n pin to be an output pin by setting the corresponding gpio1_ndir bit (from bit 7-4), within the ?general purpose input/out - put 1 control register (address 0x4102) to ?1?. gpio0_3 gpio0_2 gpio0_1 gpio0_0 ad20 ab18 ad13 ad11 u16 v15 y11 ab6 i/o 8 general purpose input/output pins each of these pins can be configured to function as either a general-purpose input or output pin. the exact function of these pins depend on whether these gpio pins are configured as input or output pins as follows. if gpio0_n pins are configured as input pins: the state of these input pins can be monitored by reading the gpio0_n control bits (bit 3-0) within the ?general pur - pose input/output 0 control register (address 0x0102). if gpio0_n pins are configured as output pins: the state of these output pins can be controlled by writing the appropriate value into the gpio0_n control bits (bit 3- 0) within the ?general purpose input/output 0 control register (address 0x0102). finally, users can configure a given gpio0_n pin to be an input pin by setting the corresponding gpio0_ndir bit (from bit 7-4), within the ?general purpose input/output 0 control register (address 0x0102) to ?0?. conversely, users can configure the gpio0_ n pin to be an output pin by setting the corresponding gpio0_ndir bit (from bit 7-4), within the ?general purpose input/out - put 0 control register (address 0x0102) to ?1?.
xrt86vl38 39 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 jtag interface the xrt86vl38 device?s jtag features comply with the i eee 1 149.1 standard. please refer to the industry specification for additional information on boundary scan operations. s ignal n ame 420 p kg b all # 484p kg b all # t ype o utput d rive ( m a) d escription tck a7 f10 i - test clock: boundary scan test clock input: the tclk signal is the clock for the tap controller, and it generates the boundary scan data register clocking. the data on tms and tdi is loaded on the positive edge of tck. data is observed at tdo on the falling edge of tck. tms a5 b6 i - test mode select: boundary scan test mode select input. the tms signal controls the transitions of the tap con - troller in conjunction with the rising edge of the test clock (tck). n ote : for normal operation this pin must be pulled ?high?. tdi d7 e9 i - test data in: boundary scan test data input the tdi signal is the serial test data input. n ote : this pin is internally pulled ?high?. tdo b6 d8 o 8 test data out: boundary scan test data output the tdo signal is the serial test data output. trst b7 a6 i - test reset input: the trst signal (active low) asynchronously resets the tap controller to the test-logic-reset state. n ote : this pin is internally pulled ?high? test b11 e12 i - factory test mode pin n ote : this pin is internally pulled ?low?, and should be pulled ?low? for normal operation. atest e7 c7 i - factory test mode pin n ote : this pin is internally pulled ?low?, and should be pulled ?low? for normal operation. jtag_ring d4 c2 i - jtag_ring test pin jtag_tip f5 e5 i - jtag_tip test pin
xrt86vl38 40 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description microprocessor interface s ignal n ame 420 p kg b all # 484p kg b all # t ype o utput d rive ( m a) d escription data0 data1 data2 data3 data4 data5 data6 data7 y26 w24 t25 t26 p24 n25 n24 m25 t19 u20 p21 n18 m22 m20 m21 l21 i/o 8 bidirectional microprocessor data bus these pins are used to drive and receive data over the bi- directional data bus, whenever the microprocessor per - forms read or write operations with the microprocessor interface of the xrt86vl38 device. when dma interface is enabled, these 8-bit bidirectional data bus is also used by the t1/e1 framer or the external dma controller for storing and retrieving information. req0 ab26 u19 o 8 dma cycle request output?dma controller 0 (write) : these output pins are used to indicate that dma transfers (write) are requested by the t1/e1 framer. on the transmit side (i.e., to transmit data from external dma controller to hdlc buffers within the xrt86vl38), dma transfers are only requested when the transmit buffer status bits indicate that there is space for a complete mes - sage or cell. the dma write cycle starts by t1/e1 framer asserting the dma request ( req0) ?low?, then the external dma control - ler should drive the dma acknowledge ( ack0) ?low? to indi - cate that it is ready to start the transfer. the external dma controller should place new data on the microprocessor data bus each time the write signal is strobed low if the wr is configured as a write strobe. if wr is configured as a direction signal, then the external dma controller would place new data on the microprocessor data bus each time the read signal (rd) is strobed low. the framer asserts this output pin (toggles it "low") when at least one of the transmit hdlc buffers are empty and can receive one more hdlc message. the framer negates this output pin (toggles it ?high?) when the hdlc buffer can no longer receive another hdlc mes - sage.
xrt86vl38 41 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 req1 aa24 y22 o 8 dma cycle request output?dma controller 1 (read): these output pins are used to indicate that dma transfers (read) are requested by the t1/e1 framer. on the receive side (i.e., to transmit data from hdlc buff - ers within the xrt86vl38 to external dma controller), dma transfers are only requested when the receive buffer contains a complete message or cell. the dma read cycle starts by t1/e1 framer asserting the dma request ( req1) ?low?, then the external dma control - ler should drive the dma acknowledge ( ack1) ?low? to indi - cate that it is ready to receive the data. the t1/e1 framer should place new data on the microprocessor data bus each time the read signal is strobed low if the rd is con - figured as a read strobe. if rd is configured as a direction signal, then the t1/e1 framer would place new data on the microprocessor data bus each time the write signal (wr) is strobed low. the framer asserts this output pin (toggles it "low") when one of the receive hdlc buffer contains a complete hdlc message that needs to be read by the c/p. the framer negates this output pin (toggles it ?high?) when the receive hdlc buffers are depleted. int r26 n22 o 8 interrupt request output: this active-low output signal will be asserted when the xrt86vl38 device is requesting interrupt service from the microprocessor. this output pin should typically be con - nected to the ?interrupt request? input of the microproces - sor. the framer will assert this active "low" output (toggles it "low"), to the local p, anytime it requires interrupt service. microprocessor interface s ignal n ame 420 p kg b all # 484p kg b all # t ype o utput d rive ( m a) d escription
xrt86vl38 42 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description pclk y25 v22 i - microprocessor clock input: this clock input signal is only used if the microprocessor interface has been configured to operate in the synchro - nous modes (e.g., power pc 403 mode). if the micropro - cessor interface is configured to operate in this mode, then it will use this clock si gnal to do the following. 1. to s a m p le t he cs , wr /r/ w , a[14:0], d[7:0], rd / ds and dben input pins, and 2. to update the state of the d[7:0] and the rdy/ dtack output signals. n otes : 1. the microprocessor interface can work with pclk frequencies ranging up to 33mhz. 2. this pin is inactive if the user has configured the microprocessor interface to operate in either the intel-asynchronous or the motorola- asynchronous modes. in this case, the user should tie this pin to gnd. when dma interface is enabled, the pclk input pin is also used by the t1/e1 framer to latch in or latch out receive or output data respectively. iaddr w22 r18 i - this pin must be tied ?low? for normal operation. this pin is internally pulled ?high? with a 50k resistor. faddr aa26 t18 i - this pin must be tied ?high? for normal operation. this pin is internally pulled ?low? with a 50k resistor. ptype0 ptype1 ptype2 w23 w26 r25 v20 t20 n21 i - microprocessor type input: these input pins permit the user to specify which type of microprocessor/microcontroller to be interfaced to the xrt86vl38 device. the following table presents the three different microprocessor types that the xrt86vl38 sup - ports. n ote : these pins are internally pulled ?low? with a 50k resistor. microprocessor interface s ignal n ame 420 p kg b all # 484p kg b all # t ype o utput d rive ( m a) d escription 0 1 1 ptype0 0 0 0 0 0 1 ptype1 ptype2 68hc11, 8051, 80c188 motorola 68k ibm power pc 403 microprocessor type
xrt86vl38 43 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 rdy v24 r19 o 12 ready/data transfer acknowledge output: the exact behavior of this pin depends upon the type of microprocessor/microcontroller the xrt86vl38 has been configured to operate in, as defined by the ptype[2:0] pins. intel asynchronous mode - rdy - ready output tis output pin will function as the ?active-low? ready out - put. during a read or write cycle, the microprocessor inter - face block will toggle this output pin to the logic low level, only when the microprocessor interface is ready to com - plete or terminate the current read or write cycle. once the microprocessor has determined that this input pin has toggled to the logic ?low? level, then it is now safe for it to move on and execute the next read or write cycle. if (during a read or write cycle) the microprocessor interface block is holding this output pin at a logic ?high? level, then the microprocessor is expected to extend this read or write cycle, until it detects this output pin being toggled to the logic low level. motorola asynchronous mode - dtack - data transfer acknowledge output tis output pin will function as the ?active-low? dtack out - put. during a read or write cycle, the microprocessor inter - face block will toggle this output pin to the logic low level, only when the microprocessor interface is ready to com - plete or terminate the current read or write cycle. once the microprocessor has determined that this input pin has toggled to the logic ?low? level, then it is now safe for it to move on and execute the next read or write cycle. if (during a read or write cycle) the microprocessor interface block is holding this output pin at a logic ?high? level, then the microprocessor is expected to extend this read or write cycle, until it detects this output pin being toggled to the logic low level. microprocessor interface s ignal n ame 420 p kg b all # 484p kg b all # t ype o utput d rive ( m a) d escription
xrt86vl38 44 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description rdy v24 r19 o 12 (con?t) power pc 403 mode - rdy ready output: this output pin will function as the ?active-high? ready output. during a read or write cycle, the microprocessor inter - face block will toggle this output pin to the logic high level, only when the microprocessor interface is ready to com - plete or terminate the current read or write cycle. once the microprocessor has sampled this signal being at the logic ?high? level upon the rising edge of pclk, then it is now safe for it to move on and execute the next read or write cycle. if (during a read or write cycle) the microprocessor interface block is holding this output pin at a logic ?low? level, then the microprocessor is expected to extend this read or write cycle, until it samples this output pin being at the logic low level. n ote : the microprocessor interface will update the state of this output pin upon the rising edge of pclk. addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 v25 v26 u22 u23 u24 u25 u26 t22 t24 r23 r24 p22 p25 n23 n22 p18 n17 t21 t22 r20 r21 r22 p19 p20 n19 n20 m18 m19 l18 l22 i - microprocessor interface address bus input these pins permit the microprocessor to identify on-chip registers and buffer/memory locations within the xrt86vl38 device whenever it performs read and write operations with the xrt86vl38 device. n ote : these pins are internally pulled ?low? with a 50k resistor, except addr[8:14]. dben v23 u22 i - data bus enable input pin. this active-low input pin permits the user to either enable or tri-state the bi-directional data bus pins (d[7:0]), as described below. ? setting this input pin ?low? enables the bi-directional data bus. ? setting this input pin ?high? tri-states the bi-directional data bus. microprocessor interface s ignal n ame 420 p kg b all # 484p kg b all # t ype o utput d rive ( m a) d escription
xrt86vl38 45 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 ale r22 p22 i - address latch enable input address strobe the exact behavior of this pin depends upon the type of microprocessor/microcontroller the xrt86vl38 has been configured to operate in, as defined by the ptype[2:0] pins. intel-asynchronous mode - ale this active-high input pin is used to latch the address (present at the microprocessor interface address bus pins (a[14:0]) into the xrt86vl38 microprocessor interface block and to indicate the start of a read or write cycle. pulling this input pin ?high? enables the input bus drivers for the address bus input pins (a[14:0]). the contents of the address bus will be latched into the xrt86vl38 micropro - cessor interface circuitry, upon the falling edge of this input signal. motorola-asynchronous (68k) mode - as this active-low input pin is used to latch the data residing on the address bus, a[14:0] into the microprocessor inter - face circuitry of the xrt86vl38 device. pulling this input pin ?low? enables the input bus drivers for the address bus input pins. the contents of the address bus will be latched into the microprocessor interface cir - cuitry, upon the rising edge of this signal. power pc 403 mode - no function -tie to gnd: this input pin has no role nor function and should be tied to gnd. cs l26 k21 i - microprocessor interface?chip select input: the user must assert this active low signal in order to select the microprocessor interface for read and write operations between the microprocessor and the xrt86vl38 on-chip registers and buffer/memory loca - tions. microprocessor interface s ignal n ame 420 p kg b all # 484p kg b all # t ype o utput d rive ( m a) d escription
xrt86vl38 46 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description rd w25 u21 i - microprocessor interface?read strobe input: the exact behavior of this pin depends upon the type of microprocessor/microcontroller the framer has been con - figured to operate in, as defined by the ptype[2:0] pins. intel-asynchronous mode - rd - read strobe input: this input pin will function as the rd (active low read strobe) input signal from the microprocessor. once this active-low signal is asserted, then the xrt86vl38 device will place the contents of the addressed register (or buffer location) on the microprocessor interface bi-directional data bus (d[7:0]). when this signal is negated, then the data bus will be tri- stated. motorola-asynchronous (68k) mode - ds - data strobe: this input pin will function as the ds (data strobe) input signal. power pc 403 mode - we - write enable input: this input pin will function as the we (write enable) input pin. anytime the microprocessor interface samples this active- low input signal (along with cs and wr /r/ w ) also being asserted (at a logic low level) upon the rising edge of pclk, then the microprocessor interface will (upon the very same rising edge of pclk) latch the contents on the bi-directional data bus (d[7:0]) into the ?target? on-chip register or buffer location within the xrt86vl38 device. wr m23 l20 i - microprocessor interface?write strobe input the exact behavior of this pin depends upon the type of microprocessor/microcontroller the xrt86vl38 has been configured to operate in, as defined by the ptype[2:0] pins. intel-asynchronous mode - wr - write strobe input: this input pin functions as the wr (active low write strobe) input signal from the microprocessor. once this active-low signal is asserted, then the input buffers (associ - ated with the bi-directional data bus pin, d[7:0]) will be enabled. the microprocessor interface will latch the contents on the bi-directional data bus (into the ?target? register or address location, within the xrt86vl38) upon the rising edge of this input pin. motorola-asynchronous mode - r/ w - read/write operation identification input pin: this pin is functionally equivalent to the ?r/ w ? input pin. in the motorola mode, a ?read? operation occurs if this pin is held at a logic ?1?, coincident to a falling edge of the rd/ ds (data strobe) input pin. similarly a write operation occurs if this pin is at a logic ?0?, coincident to a falling edge of the rd/ ds (data strobe) input pin. microprocessor interface s ignal n ame 420 p kg b all # 484p kg b all # t ype o utput d rive ( m a) d escription
xrt86vl38 47 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 wr m23 l20 i - (con?t) power pc 403 mode - r/ w - read/write operation iden - tification input: this input pin will function as the ?read/write operation identification input? pin. anytime the microprocessor interface samples this input signal at a logic "high" (while also sampling the cs input pin ?low?) upon the rising edge of pclk, then the micro - processor interface will (upon the very same rising edge of pclk) latch the contents of the address bus (a[14:0]) into the microprocessor interface circuitry, in preparation for this forthcoming read operation. at some point (later in this read operation) the microprocessor will also assert the dben/oe input pin, and the microprocessor interface will then place the contents of the ?target? register (or address location within the xrt86vl38 device) upon the bi-direc - tional data bus pins (d[7:0]), where it can be read by the microprocessor. anytime the microprocessor interface samples this input signal at a logic "low" (while also sampling the cs input pin a logic ?low?) upon the rising edge of pclk, then the microprocessor interface will (upon the very same rising edge of pclk) latch the contents of the address bus (a[14:0]) into the microprocessor interface circuitry, in preparation for the forthcoming write operation. at some point (later in this write operation) the microprocessor will also assert the rd/ds/we input pin, and the micropro - cessor interface will then latch the contents of the bi-direc - tional data bus (d[7:0]) into the contents of the ?target? register or buffer location (within the xrt86vl38). microprocessor interface s ignal n ame 420 p kg b all # 484p kg b all # t ype o utput d rive ( m a) d escription
xrt86vl38 48 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description ack0 ack1 y23 y24 w22 v21 i - dma cycle acknowledge input?dma controller 0 (write): the external dma controller will assert this input pin ?low? when the following two conditions are met: 1. after the dma controller, within the framer has asserted (toggled ?low?), the req_0 output signal. 2. when the external dma controller is ready to transfer data from external memory to the selected transmit hdlc buffer. at this point, the dma transfer between the external mem - ory and the selected transmit hdlc buffer may begin. after completion of the dma cycle, the external dma con - troller will negate this input pin after the dma controller within the framer has negated the req_0 output pin. the external dma controller must do this in order to acknowl - edge the end of the dma cycle. dma cycle acknowledge input?dma controller 1 (read): the external dma controller asserts this input pin ?low? when the following two conditions are met: 1. after the dma controller, within the framer has asserted (toggled "low"), the req_1 output signal. 2. when the external dma controller is ready to transfer data from the selected receive hdlc buffer to external memory. at this point, the dma transfer between the selected receive hdlc buffer and the external memory may begin. after completion of the dma cycle, the external dma con - troller will negate this input pin after the dma controller within the framer has negated the req_1 output pin. the external dma controller will do this in order to acknowl - edge the end of the dma cycle. n ote : this pin is internally pulled ?high? with a 50k resistor. microprocessor interface s ignal n ame 420 p kg b all # 484p kg b all # t ype o utput d rive ( m a) d escription
xrt86vl38 49 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 blast p23 m17 i - last cycle of burst indicator input: if the microprocessor interface is operating in the intel-i960 mode, then this input pin is used to indicate (to the micro - processor interface block) that the current data transfer is the last data transfer within the current burst operation. the microprocessor should assert this input pin (by tog - gling it ?low?) in order to denote that the current read or write operation (within a burst operation) is the last operation of this burst operation. n otes : 1. if the user has configured the microprocessor interface to operate in the intel-asynchronous, the motorola-asynchronous or the power pc 403 mode, then he/she should tie this input pin to gnd. 2. this pin is internally pulled ?high? with a 50k resistor. reset y4 y1 i - hardware reset input reset is an active low input. if this pin is pulled ?low? for more than 10 s, the device will be reset. when this occurs, all output will be ?tri-stated?, and all internal registers will be reset to their default values. power supply pins (3.3v) s ignal n ame 420 p kg b all # 484p kg b all # t ype d escription vdd y2 ac4 ac11 ae18 ad23 aa25 n26 f24 a25 c15 c8 g10 g12 g15 h17 l16 r17 t7 t9 t11 t13 t15 pwr framer block power supply (i/o) rvdd d2 f2 h2 k2 m2 p2 t2 v2 e1 h5 k6 l6 m7 n4 r5 t5 pwr receiver analog power supply for liu section microprocessor interface s ignal n ame 420 p kg b all # 484p kg b all # t ype o utput d rive ( m a) d escription
xrt86vl38 50 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description tvdd f4 h3 j4 l3 n3 r3 t4 v3 f2 g1 j2 l3 m6 n1 r3 u1 pwr transmitter analog power supply for liu section power supply pins (1.8v) s ignal n ame 420 p kg b all # 484p kg b all # t ype d escription vdd18 ad1 ad7 af14 ab20 ac24 t23 j24 d24 e18 e12 g11 g14 g16 j17 p17 t8 t10 t12 t14 t17 pwr framer block power supply dvdd18 a1 f5 pwr digital power supply for liu section avdd18 b4 a2 pwr analog power supply for liu section vddpll18 d3 c2 b1 c1 b1 c1 d2 e3 pwr analog power supply for pll power supply pins (3.3v) s ignal n ame 420 p kg b all # 484p kg b all # t ype d escription
xrt86vl38 51 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 ground pins s ignal n ame 420 p kg b all # 484p kg b all # t ype d escription vss y1 aa1 ae2 ad6 ad9 af13 ac16 ab19 ac22 ab23 aa23 v22 p26 l23 h22 c25 b25 d20 b17 c13 d10 c06 f6 g6 g7 g8 g9 g13 h6 h7 h16 j7 j16 k7 k16 l7 m16 n6 n7 n16 p6 p7 p16 r6 r7 r16 t6 t16 u6 h8-h15 j8-j15 k8-k15 l8-l15 m8-m15 n8-n15 p8-p15 r8-r15 gnd framer block ground dgnd a2 b5 gnd digital ground for liu section agnd a3 b3 gnd analog ground for liu section
xrt86vl38 52 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description rgnd e2 g2 j2 l2 n2 r2 u2 w2 f4 h3 j4 k2 m4 n3 p1 t4 gnd receiver analog ground for liu section tgnd h5 j5 k5 l5 m5 n5 r5 t5 g4 j6 k5 l5 n5 p4 r1 v1 gnd transmitter analog ground for liu section gndpll18 c3 e4 e3 b2 d3 e4 d1 e2 gnd analog ground for pll ground pins s ignal n ame 420 p kg b all # 484p kg b all # t ype d escription
xrt86vl38 53 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 no connect pins s ignal n ame 420 p kg b all # 484p kg b all # t ype d escription nc b3 b18 b23 c4 d23 e5 e16 e19 e22 g5 n4 p5 u5 v4 v5 w3 w4 w5 aa3 aa4 aa5 af1 a1 a3 a22 b2 c3 c4 c5 d5 d6 d7 e7 e8 f7 f8 g5 b4 f18 nc no connection
xrt86vl38 54 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description electrical characteristics absolute maximums power supply..................................................................... vdd io .. ................................................ - 0.5v to +3.465v vdd core............................................... - 0.5v to +1.890v power rating stbga and pbga package.................. 2.4 storage temperature ...............................-65c to 150c input logic signal voltage (any pin) .........-0.5v to + 5.5v operating temperature range.................-40c to 85c esd protection (hbm)...........................................>2000v supply voltage ...................... gnd-0.5v to +vdd + 0.5v input current (any pin) ...................................... + 100ma dc electrical characteristics test conditions: ta = 25c, vdd io = 3.3v + 5% , vdd core = 1.8v + 5% unless otherwise specified s ymbol p arameter m in . t yp . m ax . u nits c onditions i ll data bus tri-state bus leakage current -10 +10 a v il input low voltage 0.8 v v ih input high voltage 2.0 vdd v v ol output low voltage 0.0 0.4 v i ol = -1.6ma voh output high voltage tbd vdd v i oc open drain output leakage current a i ih input high voltage current -10 10 a v ih = vdd i il input low voltage current -10 10 a v il = gnd xrt86vl38 power consumption test conditions: ta = 25c, vdd io = 3.3v + 5% , vdd core = 1.8v + 5%, internal termination, unless otherwise specified mode i mpedance m in . t yp . m ax . u nits c onditions t1 100 2.21 w qrss pattern with all 8 channels on e1 75 2.07 w qrss pattern with all 8 channels on e1 120 1.93 w qrss pattern with all 8 channels on
xrt86vl38 55 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 t able 4: e1 r eceiver e lectrical c haracteristics vdd io = 3.3v + 5% , vdd core = 1.8v + 5% , t a = -40 to 85c, unless otherwise specified p arameter m in . t yp . m ax . u nit t est c onditions receiver loss of signal: number of consecutive zeros before rlos is set input signal level at rlos rlos de-asserted 15 12.5 32 20 db % ones cable attenuation @1024khz itu-g.775, etsi 300 233 receiver sensitivity (short haul with cable loss) 11 db with nominal pulse amplitude of 3.0v for 120 and 2.37v for 75 applica - tion. receiver sensitivity (long haul with cable loss) 0 43 db with nominal pulse amplitude of 3.0v for 120 and 2.37v for 75 applica - tion. input impedance 15 k input jitter tolerance: 1 hz 10khz-100khz 37 0.3 uipp uipp itu g.823 recovered clock jitter transfer corner frequency peaking amplitude - 20 0.5 khz db itu g.736 jitter attenuator corner fre - quency (-3db curve) (jabw=0) (jabw=1) - 10 1.5 - hz hz itu g.736 return loss: 51khz - 102khz 102khz - 2048khz 2048khz - 3072khz 12 8 8 - - db db db itu-g.703
xrt86vl38 56 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description t able 5: t1 r eceiver e lectrical c haracteristics vdd io = 3.3v + 5% , vdd core = 1.8v + 5%, t a =-40 to 85c, unless otherwise specified p arameter m in . t yp . m ax . u nit t est c onditions receiver loss of signal: number of consecutive zeros before rlos is set input signal level at rlos rlos clear 15 12.5 175 20 - - - db % ones cable attenuation @772khz itu-g.775, etsi 300 233 receiver sensitivity (short haul with cable loss) 12 - db with nominal pulse amplitude of 3.0v for 100 termination receiver sensitivity (long haul with cable loss) normal extended 0 0 - 36 45 db db with nominal pulse amplitude of 3.0v for 100 termination input impedance 15 - k jitter tolerance: 1hz 10khz - 100khz 138 0.4 - - - - uipp at&t pub 62411 recovered clock jitter transfer corner frequency peaking amplitude - - 10 - 0.1 khz db tr-tsy-000499 jitter attenuator corner frequency (-3db curve) - 6 hz at&t pub 62411 return loss: 51khz - 102khz 102khz - 2048khz 2048khz - 3072khz - - - 14 20 16 - - - db db db t able 6: e1 t ransmitter e lectrical c haracteristics vdd io = 3.3v + 5% , vdd core = 1.8v + 5%, t a =-40 to 85c, unless otherwise specified p arameter m in . t yp . m ax . u nit t est c onditions ami output pulse amplitude: 75 application 120 application 2.13 2.70 2.37 3.00 2.60 3.30 v v 1:2 transformer output pulse width 224 244 264 ns output pulse width ratio 0.95 - 1.05 - itu-g.703 output pulse amplitude ratio 0.95 - 1.05 - itu-g.703
xrt86vl38 57 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 jitter added by the transmitter output - 0.025 0.05 uipp broad band with jitter free tclk applied to the input. output return loss: 51khz -102khz 102khz-2048khz 2048khz-3072khz 15 9 8 - - - - - - db db db etsi 300 166 t able 7: e1 t ransmit r eturn l oss r equirement f requency r eturn l oss ets 300166 51-102khz 6db 102-2048khz 8db 2048-3072khz 8db t able 8: t1 t ransmitter e lectrical c haracteristics vdd io = 3.3v + 5% , vdd core = 1.8v + 5% , t a =-40 to 85c, unless otherwise specified p arameter m in . t yp . m ax . u nit t est c onditions ami output pulse amplitude: 2.4 3.0 3.60 v 1:2 transformer measured at dsx-1. output pulse width 338 350 362 ns ansi t1.102 output pulse width imbalance - - 20 - ansi t1.102 output pulse amplitude imbalance - - + 200 mv ansi t1.102 jitter added by the transmitter output - 0.025 0.05 uipp broad band with jitter free tclk applied to the input. output return loss: 51khz -102khz 102khz-2048khz 2048khz-3072khz - - - 17 12 10 - - - db db db t able 6: e1 t ransmitter e lectrical c haracteristics vdd io = 3.3v + 5% , vdd core = 1.8v + 5%, t a =-40 to 85c, unless otherwise specified p arameter m in .t yp .m ax .u nit t est c onditions
xrt86vl38 58 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description f igure 2. itu g.703 p ulse t emplate t able 9: t ransmit p ulse m ask s pecification test load impedance 75 resistive (coax) 120 resistive (twisted pair) nominal peak voltage of a mark 2.37v 3.0v peak voltage of a space (no mark) 0 + 0.237v 0 + 0.3v nominal pulse width 244ns 244ns ratio of positive and negative pulses imbalance 0.95 to 1.05 0.95 to 1.05 10% 10% 10% 10% 10% 10% 269 ns (244 + 25) 194 ns (244?50) 244 ns 219 ns (244 ? 25) 488 ns (244 + 244) 0% 50% 20% v = 100% nominal puls e note ? v corresponds to the nominal peak value. 20% 20%
xrt86vl38 59 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 f igure 3. dsx-1 p ulse t emplate ( normalized amplitude ) t able 10: dsx1 i nterface i solated pulse mask and corner points m inimum curve m aximum curve t ime (ui) n ormalized amplitude t ime (ui) n ormalized amplitude -0.77 -.05v -0.77 .05v -0.23 -.05v -0.39 .05v -0.23 0.5v -0.27 .8v -0.15 0.95v -0.27 1.15v 0.0 0.95v -0.12 1.15v 0.15 0.9v 0.0 1.05v 0.23 0.5v 0.27 1.05v 0.23 -0.45v 0.35 -0.07v 0.46 -0.45v 0.93 0.05v 0.66 -0.2v 1.16 0.05v 0.93 -0.05v 1.16 -0.05v
xrt86vl38 60 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description t able 11: ac e lectrical c haracteristics vdd io = 3.3v + 5% , vdd core = 1.8v + 5%, t a =25c, unless otherwise specified p arameter s ymbol m in . t yp . m ax . u nits mclkin clock duty cycle 40 - 60 % mclkin clock tolerance - 50 - ppm
xrt86vl38 61 octal t1/e1/j1 framer/liu combo - hardware description rev. v1.2.0 ordering information p roduct n umber p ackage o perating t emperature r ange xrt86vl38ib 420 plastic ball grid array -40 c to +85 c xrt86vl38ib484 484 shrink thin ball grid array -40 c to +85 c package dimensions for 420 plastic ball grid array symbol min max min max a 0.085 0.098 2.16 2.50 a1 0.020 0.028 0.50 0.70 a2 0.020 0.024 0.51 0.61 a3 0.045 0.047 1.15 1.19 d 1.370 1.386 34.80 35.20 d1 1.2500 bsc 31.75 bsc e 1.370 1.386 34.80 35.20 e1 1.2500 bsc 31.75 bsc b 0.024 0.035 0.60 0.90 e 0.0500 bsc 1.27 typ. inches mi llimeters note: the control dimension is in millimeter. e 420 plastic ball grid array (35.0 mm x 35.0 mm, pbga) rev. 1.00
xrt86vl38 62 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description package dimensions for 484 shrink thin ball grid array 4 e 484 shrink thin ball grid array (23.0 mm x 23.0 mm, stbga) rev. 1.00 symbol min max min max a 0.071 0.082 1.80 2.08 a1 0.019 0.022 0.47 0.57 a2 0.019 0.022 0.48 0.56 a3 0.033 0.037 0.85 0.95 d 0.898 0.913 22.80 23.20 d1 0.8268 bsc 21.00 bsc e 0.898 0.913 22.80 23.20 e1 0.8268 bsc 21.00 bsc b 0.024 0.028 0.60 0.70 e 0.0394 bsc 1.00 bsc inches millimeters note: the control dimension is in millimeter.
63 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the li fe support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c ) potential liability of exar corporation is adequately protected under the circumstances. copyright 2007 exar corporation datasheet january 2007. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. xrt86vl38 rev. v1.2.0 octal t1/e1/j1 framer/liu combo - hardware description p4 . revision history r evision # d ate d escription v1.2.0 january 29, 2007 released to production.

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