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d a t a sh eet preliminary speci?cation file under integrated circuits, ic01 1996 apr 25 integrated circuits saa7380 error correction and host interface ic for cd-rom (elm)
1996 apr 25 2 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 contents 1 features 2 general description 3 quick reference data 4 ordering information 5 block diagram 6 pinning 7 functional description 7.1 cd-dsp interface and data input 7.2 error correction and edc check 7.3 host interface 7.4 subcode channel q-to-w buffering 7.5 external buffer memory 7.6 sub-cpu registers 7.7 register descriptions 7.8 sub-cpu interface 7.9 host registers .10 cd-dsp timings 8 limiting values 9 thermal characteristics 10 characteristics 11 timing characteristics 11.1 q-to-w subcode interface timing 11.2 external memory sram timing 11.3 external memory dram timing 11.4 sub-cpu interface timing 11.5 atapi host interface timing 11.6 sanyo compatibility mode host interface timing 11.7 oak compatibility mode host interface timing 11.8 crystal oscillator 12 package outline 13 soldering 14 definitions 15 life support applications
1996 apr 25 3 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 1 features cd-rom (mode 1) and cd-i (mode 2 - form 1 and form 2) formats supported real-time error detection and correction in hardware suitable for 6 speed, n = 6 maximum host transfer burst rate of 11.1 mbyte/s corrects two errors per symbol with erasure correction 36 kbit of on-chip error correction buffer ram 12-byte command fifo and 12-byte status fifo compatible with the advanced technology attachment (ata) register set and the advanced technology attachment program interface (atapi) command set operates with popular memories. (up to 128 kbyte sram; 1 to 16 mbit dram, different speed grades, nibble or byte wide) interface to integrated drive electronics (ide) bus without external bus drivers q-to-w subcode buffering, de-interleaving and correction are supported device can operate with audio rams. a ram test allows bad segments to be identified. 2 general description the saa7380 decoder is a block decoder buffer manager for high-speed cd-rom applications that integrates real-time error correction and detection and host interface data transfer functions into a single chip. the saa7380 has an on-chip 36-kbit memory. this memory is used as a buffer memory for error and erasure corrections. the chip also has a buffer memory interface thus enabling the connection of sram up to 128 kbytes, or dram up to 16 mbits. the on-chip memory is sufficient to buffer 1 sector of data. the external memory can buffer many more, depending on memory size. the error corrector of the saa7380 can perform 2-pass error correction in real-time. buffer memory for this correction is integrated on-chip. the saa7380 has an host interface that is compatible with the sanyo lc89510 or oak oti-012 and also compatible with the ata/ide/atapi hard disc interface bus. (all atapi registers are present in hardware). supply of this compact disc ic does not convey an implied license under any patent right to use this ic in any compact disc application. 3 quick reference data 4 ordering information symbol parameter min. typ. max. unit v ddd1 digital supply voltage 1 3.0 3.3 3.6 v v ddd2 digital supply voltage 2 4.5 5 5.5 v i ddd supply current - 60 - ma f clk clock frequency 15.2 33.8688 35 mhz t amb operating ambient temperature 0 - +70 c t stg storage temperature - 55 - +125 c type number package name description version SAA7380GP qfp80 plastic quad ?at package; 80 leads; lead length 1.95 mm; body 14 20 2.8 mm sot318-2
1996 apr 25 4 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 5 block diagram fig.1 block diagram. handbook, full pagewidth mge190 decoder serial interface error corrector sram cache micro- controller interface host interface memory manager oscillator test v ddd2 v ddd1 sda scl int reset syn dmack da1 da2/eject cs2/selrq iocs16 sfsy dgnd 1, 14, 24, 41, 59, 68 rck sub bck ws data test2 c2po test1 cs1/hen hwr da0/cmd dmarq/dten scrst/sten hd0 to hd7 hd8 to hd15 irq/eop/hfbc iordy/wait/hfblb hrd ra0 to ra5 ra6 to ra14 ra16/cas ra15/ras rd0 to rd7 crin rwe crout 50, 74 28 32 36 37 38 39 40 45 70 71 72 73 42 43 44 69 46 47 48 49 26 27 15-22 13 11 12 2-10 75-80 51-58 60-67 29 30 31 33 34 35 23 25 saa7380
1996 apr 25 5 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 6 pinning symbol pin i/o description dgnd1 1 - digital ground 1 ra6 2 o buffer ram address bus output line 6 ra7 3 o buffer ram address bus output line 7 ra8 4 o buffer ram address bus output line 8 ra9 5 o buffer ram address bus output line 9 ra10 6 o buffer ram address bus output line 10 ra11 7 o buffer ram address bus output line 11 (sram) only ra12 8 o buffer ram address bus output line 12 (sram) only ra13 9 o buffer ram address bus output line 13 (sram) only ra14 10 o buffer ram address bus output line 14 (sram) only ra15/ras 11 o buffer ram address bus output line 15 (sram) or ras (dram) ra16/cas 12 o buffer ram address bus output line 16 (sram) or cas (dram) rwe 13 o buffer ram write enable output dgnd2 14 - digital ground 2 rd0 15 i/o buffer ram data bus bidirectional line 0 rd1 16 i/o buffer ram data bus bidirectional line 1 rd2 17 i/o buffer ram data bus bidirectional line 2 rd3 18 i/o buffer ram data bus bidirectional line 3 rd4 19 i/o buffer ram data bus bidirectional line 4 rd5 20 i/o buffer ram data bus bidirectional line 5 rd6 21 i/o buffer ram data bus bidirectional line 6 rd7 22 i/o buffer ram data bus bidirectional line 7 test2 23 i test input 2 dgnd3 24 - digital ground 3 test1 25 i test input 1 crout 26 o clock oscillator output crin 27 i clock oscillator input sfsy 28 i serial subcode input frame sync input rck 29 o serial subcode clock output (active low) sub 30 i serial input for q-to-w subcode input bck 31 i serial interface bit clock input v ddd1 32 - digital supply voltage 1 (3.3 v) ws 33 i serial interface word clock input data 34 i serial data input c2po 35 i serial interface ?ag input sda 36 i/o sub-cpu serial data input/output scl 37 i sub-cpu serial clock input int 38 o sub-cpu open-collector interrupt output reset 39 i power-on reset input (active low) syn 40 i sync signal input from sub-cpu
1996 apr 25 6 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 dgnd4 41 - digital ground 4 cs1/ hen 42 i host interface enable input (active low) hwr 43 i host interface write enable input (active low) hrd 44 i host interface read enable input (active low) dmack 45 i dma acknowledge input iordy/ w ait/ hfblb 46 o host interface wait output (active low); 3-state control scrst/ sten 47 o host interface status enable output atapi sub-cpu reset signal (active low) dmarq/ dten 48 o atapi dma request host interface data enable output (active low); 3-state control irq/ eop/ hfbc 49 o host interface end of process ?ag output atapi host interrupt request (active low); 3-state control v ddd2 50 - digital supply voltage 2 (5 v) hd0 51 i/o host interface data bus input/output line 0 hd1 52 i/o host interface database input/output line 1 hd2 53 i/o host interface database input/output line 2 hd3 54 i/o host interface data bus input/output line 3 hd4 55 i/o host interface data bus input/output line 4 hd5 56 i/o host interface data bus input/output line 5 hd6 57 i/o host interface data bus input/output line 6 hd7 58 i/o host interface data bus input/output line 7 dgnd5 59 - digital ground 5 hd8 60 i/o host interface data bus input/output line 8 hd9 61 i/o host interface data bus input/output line 9 hd10 62 i/o host interface data bus input/output line 10 hd11 63 i/o host interface data bus input/output line 11 hd12 64 i/o host interface data bus input/output line 12 hd13 65 i/o host interface data bus input/output line 13 hd14 66 i/o host interface data bus input/output line 14 hd15 67 i/o host interface data bus input/output line 15 dgnd6 68 - digital ground 6 da0/cmd 69 i host interface data input (active low)/command select input host interface address line 0 da1 70 i atapi address line input 1 da2/eject 71 i atapi address line input 2 cs2/selrq 72 i atapi chip select input 2 iocs16 73 o atapi 16-bit data select output v ddd2 74 - digital supply voltage 2 (5 v) ra0 75 o buffer ram address bus output line 0 ra1 76 o buffer ram address bus output line 1 ra2 77 o buffer ram address bus output line 2 symbol pin i/o description
1996 apr 25 7 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 ra3 78 o buffer ram address bus output line 3 ra4 79 o buffer ram address bus output line 4 ra5 80 o buffer ram address bus output line 5 symbol pin i/o description fig.2 pin configuration. handbook, full pagewidth saa7380 mge189 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 64 63 62 61 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 hd8 dgnd5 hd7 hd6 hd5 hd12 hd11 hd10 hd9 hd4 hd3 hd2 hd1 hd0 v ddd2 irq/eop/hfbc dmarq/dten scrst/sten iordy/wait/hfblb dmack hrd hwr cs1/hen dgnd4 ra9 ra10 ra11 ra12 ra13 dgnd1 ra6 ra7 ra8 ra14 ra15/ras ra16/cas rwe dgnd2 rd0 rd1 rd2 rd3 rd4 rd5 rd6 rd7 test2 dgnd3 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 test1 crout crin sfsy rck sub bck v ddd1 ws data c2po sda scl int reset syn ra5 ra4 ra3 ra2 ra1 ra0 v ddd2 iocs16 cs2/selrq da2/eject da1 da0/cmd dgnd6 hd15 hd14 hd13 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
1996 apr 25 8 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 6.1 pin functions 6.1.1 ra0 to ra14 external memory address signals. 6.1.2 ra16/cas external memory ra16 signal if sram or, cas signal if dram. 6.1.3 ra15/ras external memory ra15 signal if sram or, ras signal if dram. 6.1.4 rwe write output enable signal for external buffer memory. this is low when the saa7380 wants to write data into the external memory. 6.1.5 rd0 to rd7 external buffer memory bidirectional data signals. 6.1.6 sfsy frame sync for the q-to-w subcode, indicates when p-channel is available by a high-to-low transition. frame 0 is also indicated by no transition on this line. 6.1.7 rck in response to sfsy going low data is clocked into the saa7380 before each rising edge using this clock output. 6.1.8 sub q-to-w subcode is input in response to rck in 3-wire eiaj mode or ws in v4 mode compatible with the saa7345. 6.1.9 bck bit clock for the serial data input from the cd decoder. 6.1.10 ws word clock for the serial data input from the cd decoder. 6.1.11 data serial data input from the cd decoder. this may be either i 2 s-bus or eiaj 16-bit format. 6.1.12 c2po error flag from the cd decoder. a high indicates that a byte has not been corrected by the c2 error corrector and therefore is not valid. this is taken into account by the saa7380 error corrector. 6.1.13 sda sub-cpu bidirectional data signal. this signal forms part of the 3-wire serial interface between the saa7380 and the sub-cpu. 6.1.14 scl sub-cpu sync signal. this signal forms part of the 3-wire serial interface between the saa7380 and the sub-cpu. this signal is used to synchronize data transfers between the sub-cpu and the saa7380. 6.1.15 int sub-cpu interrupt signal. this active low output signals to the sub-cpu that the saa7380 has an interrupt request. 6.1.16 reset forcing this input low resets the saa7380. 6.1.17 syn sub-cpu clock signal. this signal forms part of the 3-wire serial interface between the saa7380 and the sub-cpu. this signal is the sub-cpu driven bit clock used to synchronize the signals on the sda line. 6.1.18 cs1/ hen in the atapi mode this is the host chip select 1 address signal. in the sanyo and oak compatibility modes setting this input low enables the host interface. 6.1.19 hwr this active low signal is the host write request. 6.1.20 hrd this active low signal is the host read request.
1996 apr 25 9 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 6.1.21 dmack this signal is used in the atapi and oak compatibility modes during dma transfers. the host pulls this signal low in response to a dmarq request to indicate that it is ready to transfer data. if this signal is not being used then it must be pulled high for saa7380 to operate correctly. 6.1.22 iordy/ w ait/ hfblb in the atapi mode this signal is negated to extend the host transfer cycle of any host register access. it is used in pio transfers. when iordy is not negated it is in a high-impedance state. in the sanyo compatibility mode the function of this signal depends on the selrq input. if selrq is high then wait is set low to extend the host transfer cycle. if selrq is low then wait acts as the drq signal in a dma transfer. in the oak compatibility mode this signal is the host first byte latch signal. a rising edge on this signal is used to latch the first byte in a pseudo 16-bit dma read. hfblb can only be high when pseudo 16-bit dma transfer mode is selected. 6.1.23 scrst/ sten in the atapi or oak compatibility mode this signal is pulled low to reset the sub-cpu in response to a reset command from the host. in the sanyo compatibility mode this signal is pulled low to signal to the host that status bytes are available for transfer. 6.1.24 dmarq/ dten in the atapi or oak compatibility mode this signal is asserted when the saa7380 is ready to transfer data between the host and itself. in atapi single word and oak dma transfers this occurs at every word. in atapi multi-word dma transfers this occurs at the start of the transfer. in the sanyo compatibility mode this signal is pulled low to signal to the host that data bytes are available for transfer. 6.1.25 irq/ eop/ hfbc in the atapi mode this active high signal indicates a host interrupt request. it is asserted when the sub-cpu writes to the itrg register and is negated when the host reads the status register or writes to the command register. in the sanyo compatibility mode this signal is set low when the last data byte is transferred to or from the host. in the oak compatibility mode this is the host first byte cycle output and is high while the first byte in the pseudo 16-bit dma transfer is accessed. it should be used to inhibit non-dma transactions while the first byte is latched. 6.1.26 hd0 to hd15 these are the bidirectional host data signals. in the sanyo and oak compatibility modes hd8 to hd15 are never used. 6.1.27 da0/cmd in the atapi mode this is the host data address 0 signal. in the sanyo and oak compatibility modes this input selects between command or data transfers. 6.1.28 da1 this is the atapi data address 1 signal. 6.1.29 da2/ eject in the atapi mode this is the data address 2 signal. in the oak compatibility mode this is the door switch input pin. its state is reflected in the tstat register. 6.1.30 cs2/selrq in the atapi mode this is the chip select 2 signal. in the oak and sanyo compatibility mode this is the data transfer mode select input. it is used to select between pio and dma transfers. 6.1.31 iocs16 this open-collector signal is used in the atapi mode to signal to the host that a 16-bit data port has been addressed. it is not activated during dma transfers.
1996 apr 25 10 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 7 functional description the saa7380 is comprised of four main blocks; a cd player interface, an error corrector, a host interface and a memory manager. these four blocks operate in parallel. all receive and send data to the buffer memory via the memory manager. a 36-kbit on-chip sram has been incorporated to allow high-speed data read operations for the error corrector. the saa7380 performs simultaneous data input buffering, error correction and host data transfer. 7.1 cd-dsp interface and data input the input data is synchronized, decoded, and written to the buffer ram. the input data format is software programmable. the synchronization is achieved using a sync detector and a sync interpolator. the sync detector detects the sync pattern in every sector while the interpolator avoids sync loss when no sync is found. the detector and interpolator can be individually enabled and disabled under software control. after decoding, each full sector of data (2352 bytes) comprising sync, header, sub-header and parity fields is written to the buffer ram. 7.2 error correction and edc check error correction and detection is performed on each sector after it is written to the buffer ram. the saa7380 buffers flag and data of sectors to be corrected in a 9-bit, 4096 words on-chip ram memory. for erasure correction, no external 9-bit memory is required. the standard error correction algorithm can be programmed, and supports mode 1 and mode 2, form 1 and form 2 discs. after error correction, an electronic data check is executed. when this edc check is also complete, the sector header and sub-header is written to 8 header registers, and a decode complete interrupt is generated. the microcontroller can then read the decoder status, the sector header and sub-header and the sector start address from the saa7380. 7.3 host interface the host interface controls data transfers between the saa7380 and an external microcontroller. the host interface can be programmed to operate in three modes. in the sanyo compatibility mode the host interface is functionally compatible with the sanyo lc89510 block decoder. in the oak compatibility mode the host interface is functionally compatible with the oak oti-012 controller chip in enhanced mode. in the atapi mode the interface meets the ata program interface specification. 7.4 subcode channel q-to-w buffering as well as buffering the main data, the saa7380 can also be used to buffer r-to-w subcode data in buffer memory. two buffer modes exist, raw mode and cooked mode. in the raw mode, data is written to an external ram without any processing being performed. in the cooked mode, the q-channel data is extracted, the q-channel crc is calculated, the r-to-w data is de-interleaved and the residues of each r-to-w frame are calculated. these residues make it easier to correct errors in the data. 7.5 external buffer memory it is possible to use the saa7380 with different external ram memories. from 0 to 128 kbyte srams or to 16-mbit drams are possible. memories may be nibble or byte wide (allowing 2, 8 or 16 mbits). selection is performed under software control. unique to the saa7380 is its ability to work with partly defective drams. the saa7380 offers the possibility to use a dram with bytes in error. a ram test is executed under microcontroller control. this ram test indicates defective segments to the microcontroller which keeps a list of which bad sectors to avoid. the list can be stored in the buffer memory and/or the microcontrollers own memory. 7.6 sub-cpu registers this section describes the registers in the saa7380. the operation of the registers varies depending on whether they are being read from or written to, and the host mode selected.
1996 apr 25 11 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 table 1 sub-cpu registers during write # ar name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 00000 adata/ sbout atapi data register/status byte output register 1 00001 ifctrl cmdien dteien decien cmdbk dtw ai stw ai douten souten 2 00010 dbcl data byte count register bits 7 to 0 3 00011 dbch data byte count register bits 15 to 8 4 00100 dacl data address counter register bits 7 to 0 5 00101 dach data address counter register bits 15 to 8 6 00110 dtrg data transfer trigger register 7 00111 dtack data transfer acknowledge register 8 01000 wal write address register bits 7 to 0 9 01001 wah write address register bits 15 to 8 10 01010 ctrl0 decen lookahead e01rq autoq eramrq wrrq eccrq encode 11 01011 ctrl1 syien syden dscren cowren modrq formrq mbckrq shdren 12 01100 ptl block pointer register bits 7 to 0 13 01101 pth block pointer register bits 15 to 8 14 01110 15 01111 reset reserved hsel 16 10000 dachh mem data address counter register bits 20 to 16 17 10001 wahh write address register bits 20 to 16 18 10010 pthh block pointer register bits 20 to 16 19 10011 sub_l subcode address register bits 7 to 0 20 10100 sub_h subcode address register bits 9 and 8 21 10101 22 10110 incnf iismode div 1 div 0 qwmode qwon qwcook ram test 0 23 10111 mems 0 priority 0 rfrsh width static cache 24 11000 astat atapi status register 25 11001 itrg host interrupt trigger register 26 11010 adradr atapi drive address register 27 11011 asamt atapi sam tag register 28 11100 dtctr res. dmamode udma subien rdrv trant 29 11101 adrsel atapi drive select register 30 11110 aintr atapi interrupt reason register 31 11111 aerr atapi error register
1996 apr 25 12 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 table 2 sub-cpu registers during read # ar name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 00000 apcmd/ comin atapi packet command data/command input register 1 00001 ifstat cmdi dtei deci subi dtbsy srsti/ stbsy dten sten 2 00010 dbcl data byte count register bits 7 to 0 3 00011 dbch data byte count register bits 15 to 8 4 00100 head0 minutes/ file number 5 00101 head1 seconds/ channel number 6 00110 head2 frames/ submode 7 00111 head3 mode/ coding information 8 01000 ptl block pointer register bits 7 to 0 9 01001 pth block pointer register bits 15 to 8 10 01010 wal write address register bits 7 to 0 11 01011 wah write address register bits 15 to 8 12 01100 stat0 crcok ilsync nosync lblk ushort sblk err uceb 13 01101 stat1 minerr secerr blkerr moderr sh0err sh1err sh2err sh3err 14 01110 stat2 rmod3 rmod2 rmod1 rmod0 mode form rform1 rform2 15 01111 stat3 valst cblk 16 10000 pthh block pointer register bits 20 to 16 17 10001 wahh write address register bits 20 to 16 18 10010 sub_l subcode address register bits 7 to 0 19 10011 sub_h subcode address register bits 9 and 8 20 10100 21 10101 22 10110 23 10111 24 11000 25 11001 hcon oak host con?guration register 26 11010 acmd atapi command register 27 11011 asamt atapi sam tag register 28 11100 adctr atapi device control register 29 11101 adrsel atapi drive select register 30 11110 aintr atapi interrupt reason register 31 11111 afeat atapi features register
1996 apr 25 13 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 7.7 register descriptions 7.7.1 sbout/adata this is a 12 byte fifo used to transfer data from the sub-cpu to the host. in the sanyo and oak compatibility mode writing to this register starts a status byte transfer. in this mode if the souten bit in the ifctrl register has been set to logic 1, writing to the sbout register sets the stbsy bit to logic 0. if the stwai bit is set to logic 0, sten is immediately set low to inform the host computer that the status byte is ready to be read from. if the stwai bit is set to logic 1 and the dten bit in the ifstat register is also set to logic 1, both the sten pin and the stbsy will go low. however, if the stwai bit is set to logic 0, and the dten bit is set to logic 0, then sten is held high until the dten bit goes high, thereafter it goes low. 7.7.2 comin/ apcmd during the atapi mode this register is used to read the program command sent by the host. the program command can only be received if the appropriate mode has been selected (see table 22) and a data transfer has been started (see dtrg register). during sanyo and oak compatibility modes this register is a 12 byte fifo which is used to transfer commands from the host to the sub-cpu. if reading this register empties the command fifo then cmdi is set to logic 1 and further reads from the register will return ffh. 7.7.3 ifctrl the ifctrl register provides control over the host interface. resetting the chip will clear all bits. in the atapi mode, only, bits 7 to 5 have any effect. table 3 ifctrl register bits bit name description 7 cmdien enable bits for cmdi, dtei and deci. these are interrupt masks, enabling/disabling the sub-cpu interrupt pin. they do not affect the bits in the ifstat register. if set to logic 1, the corresponding interrupt is enabled. it should be noted that these masks do not clear the interrupts. 6 dteien 5 decien 4 cmdbk command break enable. if set to logic 0 then the command break function is enabled and if the host writes to the comin fifo then any data or status byte transfers in progress will be terminated. if set to logic 1 then this operation is disabled. the data transfer interrupt dtei is not generated by a command break. 3 dtw ai data transfer w ait enable. setting this bit to logic 0 enables the data wait function. the data wait function allows the saa7380 to delay hardware execution of the data transfer until a status byte transfer has been completed. disabling the data wait function allows data transfers to take place independently of status byte transfers. 2 stw ai status byte transfer w ait enable. this bit acts in a similar way to the dtwai bit except it controls the status wait function. the status wait function allows the saa7380 to delay hardware execution of the status transfer until a data byte transfer has been completed. disabling the data wait function allows status transfers to take place independently of data transfers. 1 douten data output enable. douten enables/disables data transfers. when set to logic 0, all data transfers in progress are aborted. 0 souten status output enable. souten enables/disables status byte transfers. when set to logic 0, the status fifo register is reset to empty and all status byte transfers in progress are aborted.
1996 apr 25 14 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 7.7.4 ifstat the ifstat register indicates the state of the host interface. in the atapi mode, only bits 7 to 2 have any meaning. table 4 ifstat register bits bit name description 7 cmdi command interrupt. in the atapi mode this bit is asserted when the host has written to the atapi command register (see acmd register) and the drive is selected. it is also asserted when the host writes the execute drive diagnostic command (90h) to the atapi command register, regardless of whether the drive is selected. it is negated when the sub-cpu reads the acmd register. in the sanyo and oak compatibility modes this bit is asserted while there are command bytes waiting in the comin fifo. it is negated when the comin fifo is empty. 6 dtei data transfer end interrupt. this bit is asserted at the end of data transfer. it is negated when the sub-cpu writes to the dtack register. if the atapi mode is selected this bit is also asserted when a program command has been received and after a sub-cpu memory transfer. 5 deci decoder interrupt. this bit is asserted when a new sector is available. it is negated by reading the stat3 register. 4 subi subcode interrupt. this bit is asserted when a new subcode is available. it is negated by reading the sub_h register. 3 dtbsy data transfer busy. this bit indicates if a data transfer is taking place. it is asserted by writing to the dtrg register and is negated at the end of the transfer. 2 srsti/stbsy srst bit interrupt/status transfer busy. in the atapi mode this bit is asserted when the host writes to the atapi device control register and sets the srst bit. it is negated when the sub-cpu reads the adctr register. it should be noted that if this bit is asserted in the atapi mode then the sub-cpu interrupt will also be asserted. the srsti interrupt cannot be disabled. in the sanyo and oak compatibility modes this bit indicates if a status byte transfer is taking place. it is asserted by writing to the sbout register and is negated when the host has emptied the status fifo. 1 dten data transfer and status transfer. these bits reflect the state of the dten and sten pins in the sanyo and oak compatibility modes. they are updated at the end of a host read or write. 0 sten 7.7.5 dbcl and dbch the data byte counter is used by the sub-cpu to control the number of bytes that are transferred in a data transfer. in the atapi mode all 16 bits are available while in the sanyo and oak compatibility modes only 15 bits are available with bit 7 of dbch indicating the state of dtei (see table 4). during memory-to-host data transfers the data byte counter is decremented after every host read. during host-to-memory data transfers the data byte counter is decremented as data is written into external buffer memory. 7.7.6 dacl, dach and dachh this 21-bit write-only register is used to specify the external buffer address of the first byte of the data block to be transferred to the host. once the address has been set, it is incremented automatically as successive bytes are transferred with the host. it should be noted that pointer operation is asynchronous from host read/write operation. for this reason, counter increments are not coincident with host transfer operations.
1996 apr 25 15 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 bit 7 of the dachh register specifies which memory is accessed. if the bit is clear then the address refers to the external memory, if the bit is set then the address refers to the 4 kbyte internal memory. the internal memory should not be accessed during error correction. this register should be written to before each data transfer because its value will be undefined at the end of the previous transfer. 7.7.7 ptl, pth and pthh this register holds a 21-bit pointer to the external buffer memory address of the head of the current data block after correction. the saa7380 defines the minute byte in the header to be at the head of the block, and the 12 sync bytes at the tail of the block. each block contained in the buffer is taken to be 2352 bytes. the controller can transfer the decoded block back to the host by copying the address of this register to the dacl, dach and dachh pointers after a decoder interrupt. when the wrrq bit in the ctrl0 register is set to logic 1, this pointer is updated at the sync signal of every 2352 byte clocks. 7.7.8 wal, wah and wahh these registers contain a 21-bit address of where raw data from the drive is written to the external buffer memory. the pointer is automatically incremented during data transfer. the pointer should only be read while drive data writes to the buffer are disabled. if wahh is written to while drive data write is enabled, then the new wa value will be used for the first byte of the next sector. the new pointer value is temporarily stored in the pt register. this cannot be read after wa has been written to. 7.7.9 dtrg writing to this register starts a data transfer. the data written is discarded. 7.7.10 dtack writing to this register clears the dtei interrupt. the data written is discarded. 7.7.11 head0, head1, head2 and head3 these registers are used to hold the header and the sub-header data of the current block. to read the header data set, the shdren bit in the ctrl1 register is set to logic 0; to read the sub-header data, shdren is set to logic 1. if sub-header is selected, the registers will normally hold data from bytes 20 to 23. however, if the error flag for one of these bytes is set, then the byte is taken from the first sub-header field. (bytes 16 to 19.) the error flags for header and sub-header can be read from the stat1 register. no error correction is performed on header or sub-header. header and sub-header registers are valid directly after decoder interrupt, and as long as the valst bit in the stat3 register is low. in all write modes they contain information on the block whose header is pointed to by ptl, pth and pthh. table 5 head registers shdren register contents 0 head0 minutes (byte 12) 0 head1 seconds (byte 13) 0 head2 frames (byte 14) 0 head3 mode (byte 15) 1 head0 file number (byte 16 or 20) 1 head1 channel number (byte 17 or 21) 1 head2 submode number (byte 18 or 22) 1 head3 coding information (byte 19 or 23)
1996 apr 25 16 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 7.7.12 ctrl0 resetting the chip sets all the bits in this register to logic 0. table 6 ctrl0 register bit name function 7 decen disable decoding = 0; enable decoding = 1. this bit enables/disables decoding functions. disabling the decoding functions also disables the decoder interrupt. 6 lookahead at interrupt pt, header refer to current block = 0; at interrupt pt, header refer to next block = 1. when this bit is set to logic 1 at decoder interrupt, cma and header registers will give information on the next block instead of on the current block. the lookahead mode was included to provide support for bad rams, and to give the cpu better control on the blocks it wants to read. 5 e01rq disable error correction of bytes = 0; enable correction of circ mis-corrections = 1. setting this bit to logic 0 instructs the error corrector not to correct bytes flagged as reliable by the circ error corrector. 4 autorq disable automatic error correction = 0; enable automatic error correction = 1. requests automatic extraction of form bit during mode 2 correction from sub-header data. 3 eramrq disable erasure ?ag use = 0; enable erasure ?ag use = 1. when set to logic 1, the saa7380 will enable the use of erasure flag information for error correction. when set to logic 0, the saa7380 will disable the use of erasure flag information for error correction. use of erasure flags must be disabled when the cd-dsp does not output erasure flags and when the internal buffer ram is disabled (which is necessary for repeat correction). 2 wrrq disable data writes to the buffer and ptl updates = 0; enables data writes to the buffer and ptl updates = 1. this bit enables/disables writes from the cd drive into the buffer. it also enables/disables pointer (ptl, pth and pthh) updates each time a block is received. when wrrq is set to logic 1, data write will start from the first byte of the next block onwards. when wrrq is set to logic 0, repeat correction is enabled. with wrrq set to logic 0, the internal buffer ram is disabled. 1 eccrq disable ecc correction = 0; enable ecc correction = 1. when eccrq is set to logic 1 the blocks received by the saa7380 will be error corrected before a decoder interrupt is generated. when eccrq is set to logic 0 no corrections are performed. the algorithm used is a qd, pd, qe, pe algorithm. in a first step, errors are corrected; in a second step, erasures are corrected. correction data is read from the on-chip 36 kbit buffer memory. 0 encode normal operation = 0; test mode, do not use = 1, this bit must always be set to logic 0.
1996 apr 25 17 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 table 7 error correction modes note 1. where x = dont care. 7.7.13 ctrl1 the reset function clears all the flags in this register. table 8 ctrl1 register bits decen lookahead wrrq eccrq decoder mode 0 x x x decoder disable; note 1 1000 monitor only 1001 repeat correction 1010 write only 1011 real-time correct, normal mode 1110 write only, lookahead 1111 real-time correct, lookahead bit name function 7 syien disable sync interpolation = 0; enable sync interpolation = 1. enabling syien prevents loss of synchronization when an error occurs in a sync pattern during data read. 6 syden disable sync detection = 0; enable sync detection = 1. enabling syden synchronizes the decoder with the sync pattern detected in the input data. 5 dscren descramble disable (audio) = 0; descramble enable = 1. this bit enables/disables descrambling. setting this bit to logic 0 allows reading of raw data on disc, even audio signals. this bit should be set to logic 1 for crom data. 4 cowren crc with error correction disabled = 0; detection errors are corrected = 1. this bit enables/disables rewriting of error bytes in the buffer during error correction. setting the bit to logic 0 allows crc checks without error correction. 3 modrq mode 1 request = 0; mode 2 request = 1. this bit discriminates mode 1/mode 2. 2 formrq form 1 request = 0; form 2 request = 1. this bit discriminates mode 2/form 1 and mode 2/form 2. 1 mbckrq disable mode check function = 0; enable mode check function = 1. if the mode specified in the mode byte does not correspond with the raw data mode bit and this bit is set to logic 1 then error correction and detection is disabled. 0 shdren header data on registers head0 to head3 = 0; sub-header data on registers head0 to head3 = 1. this bit toggles header and sub-header data between registers head0 to head3.
1996 apr 25 18 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 7.7.14 stat0 resetting the chip clears all bits in this register. table 9 stat0 register bits 7.7.15 stat1 resetting the chip clears all bits in this register. the bits in this register indicate the reliability of data in the head0 to head3 registers. bits minerr, secerr, blkerr and moderr indicate errors in the minutes, seconds, frames and mode bytes in the header of the current block. bits sh0err to sh3err indicate errors in the respective bytes in the sub-header. table 10 stat1 register bits bit name function 7 crcok cyclic redundancy check not ok = 0; cyclic redundancy check ok = 1. set by the edc in accordance with the results of the crc check. 6 ilsync sync pattern detected at word count 0 to 1174 or 1176 onwards = 1. this bit is set to logic 1 if the sync pattern in the incoming data is detected between word counts 0 and 1174 or 1176 to infinity, and the decoder has been retimed. due to the presence of the cache ram, it is necessary to stop error correction also when long blocks have been detected. 5 nosync sync pattern inserted by sync interpolator not coincident with data sync = 1. this bit is set to logic 1, if the word counter reaches 1175 and no sync pattern has been detected in the input data. it indicates that the sync interpolator circuit inserted a sync. 4 lblk with syien = 0, no sync found. data block size has been extended = 1. this bit is set to logic 1, if the sync interpolator was switched off, and if the sync interpolator indicated that sync insertion was necessary. this condition causes the block length to be extended. 3 reserved 2 sblk short block indication = 1. this bit is set to logic 1 if the decoder is not retimed when a sync pattern is detected in an incorrect word location, and is ignored while the syden bit is set to logic 0. 1 erablk one or more bytes of the block are ?agged with c2 ?ags = 1. this bit is set to logic 1 if one or more bytes of the current block contain erasures as indicated by the c2po input. 0 uceblk uncorrectable errors in block = 1. this bit is set to logic 1 when one or more bytes of the current block remain in error after the error correction process. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 minerr secerr blkerr moder sh0err sh1err sh2err sh3err
1996 apr 25 19 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 7.7.16 stat2 the bits mode and form in this register indicate the mode, form and correction scheme of the current frame. table 11 stat2 register bits table 12 mode and form bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rmod3 rmod2 rmod1 rmod0 mode form rform1 rform2 mode form setting 0 0 mode 1 1 0 mode 2, form 1 x 1 mode 2, form 2 or ecc correction impossible the mode bit is always copied from the ctrl1 register. the form information is determined by the autorq bit in the ctrl0 register. when this bit is set to logic 0, the form information is copied from the ctrl1 register. when this bit is set to logic 1 the form information is copied from the mode header byte. if correction of the block was impossible, form will be set to logic 1 regardless of the requested correction. this will happen under the following circumstances: an illegally synchronized block (ilsync = 1 or lblk = 1) a data block specified as mode 2, form 2, or detected as mode 2, form 2 a mode 2 submode byte error detected during processing a mode mismatch detected by the mode check function (mchqrq = 1) a mode byte error detected by the mode check function (mchqrq = 1). the rform2, rform1 bits contain a preview of the form bit for the next frame table 13 rform2 and rform1 bits the rmod3, rmod2, rmod1 and rmod0 bits contain a preview of the next block mode byte. rmod3 = bit7 # bit6 # bit5 # bit4 # bit3 # c2flag rmod2 = bit2 # c2flag rmod1 = bit1 # c2flag rmod0 = bit0 # c2flag rform1 rform2 meaning 0 0 form 0 0 1 form 1 1 x error in form byte
1996 apr 25 20 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 table 14 rmod bits note 1. wher e x = dont care. 7.7.17 stat3 reading this register clears any deci interrupts. table 15 stat3 register bits 7.7.18 reset writing to this register resets the saa7380 and initializes all of the registers. the data written determines the host mode of saa7380. table 16 reset register bits the hsel bits in the reset register set the host interface mode. after a hardware reset the hsel bits become 111. the saa7380 will then wait until the sub-cpu writes to the reset register and selects the host mode. after hardware reset 3-statable pins will be 3-state unless hrd is driven low. rmod3 rmod2 rmod1 rmod0 meaning 0000 mode 0 0001 mode 1 0010 mode 2 0011 mode 3 0100 mode 4 0101 mode 5 0110 mode 6 0111 mode 7 1 x x x mode > 7 or error in mode byte (note 1) bit name meaning 7 valst registers associated with decoder interrupt valid = 0; registers invalid = 1. this bit is a valid/invalid flag for the registers related to the decoder interrupt. after decoder interrupt, the sub-cpu must read out of all decoder registers before valst goes high. 6 -- 5 cblk ecc not performed on current block = 0; ecc has been performed on current block = 1. this bit will go to logic 1 if ecc correction has been performed on the current block. 2 -- 1 -- 0 -- bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved hsel
1996 apr 25 21 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 table 17 hsel bits 7.7.19 sub_l, sub_h this 10-bit register specifies the memory address of the subcode data block. this address will always be in the first 1 kbyte of memory. 7.7.20 incnf this register is used to specify the configuration of the input data path. table 18 incnf register bits note 1. for subcode q-to-w recovery, the bck clock is used as a timing reference. it is possible to recover the q-to-w subcode using the saa7380, while at the same time the serial interface is programmed in oversampling mode for a dac. under such circumstances, it is necessary to tell the saa7380 the oversampling factor. hsel content selected host interface description bit 2 bit 1 bit 0 0 0 0 sanyo sanyo compatible mode 0 0 1 atapi atapi mode 0 1 0 oak oak compatible mode 0 1 1 unknown host all host bus pins 3-state, default after h/w reset others reserved for future enhancements bit name description 7 iismode i 2 s-bus mode = 0; eiaj serial interface mode = 1. 6 div1 (1) if div1 and div0 = logic 0 then no oversampling (normal cdrom modes); if div1 = logic 0 and div0 = logic 1 then 2 times oversampling; if div1 = logic 1 and div0 = logic 0 then 4 times oversampling. 5 div0 (1) if div1 and div0 = logic 0 then no oversampling (normal cdrom modes); if div0 = logic 1 and div1 = logic 0 then 2 times oversampling; if div1 = logic 0 and div1 = logic 0 then 4 times oversampling. 4 qwmode selection of q-to-w input format. logic 0 = v4 mode; logic 1 = eiaj mode. 3 qwon q-to-w interface enable. logic 0 = off; logic 1 = on. 2 qwcook q-to-w interface cooking enable. logic 0 = cooked mode; logic 1 = raw mode. 1 ramtest external ram test mode. logic 0 = normal operation; logi c 1 = ram test mode. 0 --
1996 apr 25 22 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 7.7.21 mems this register is used to specify the configuration of the external buffer memory. table 19 mems register bits table 20 host priority access bit name description 7 6 priority host priority access. these bits specify the external memory accesses priority. 5 priority 4 -- 3 rfrsh dram refresh rate. setting this bit specifies a dram refresh rate of clock frequency/400. clearing this bit specifies a rate of clock frequency/200. with a 33 mhz clock this bit should be set, while with a 16 mhz clock the bit should be clear. 2 width dram width select. this bit should be set if the external dram has a nibble wide data bus. if the data bus is byte wide then this bit should be clear. 1 static sram/dram select. if the external buffer memory is dram then this bit should be cleared. if the memory is sram this bit should be set. 0 cache cache memory select. if the internal cache is available then this bit should be clear. setting this bit to logic 1 indicates that there is no internal cache memory. priority bits access bit 6 bit 5 0 0 only one host access has highest priority 0 1 two successive host accesses have highest priority 1 0 three successive host accesses have highest priority 1 1 four successive host accesses have highest priority 7.7.22 itrg in the atapi mode writing to this register generates a host interrupt. this interrupt is cleared when the host reads the atapi status register or writes to the atapi command register. in the sanyo and oak compatibility modes writing to this register has no effect. 7.7.23 astat this write only register is only available in the atapi mode; it is the atapi status register and is used to transfer status information to the atapi host. bit 7 of this register is the bsy bit and this is set by the saa7380 whenever; saa7380 is the selected drive and the host writes to the command register (acmd) the host writes the execute drive diagnostic command (90h) to the command register the host writes to the device control register (adctr) and sets the srst bit there is a hardware reset. on reset this register is set to (80h).
1996 apr 25 23 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 7.7.24 acmd this read only register is only available in the atapi mode; it is the atapi command register and is used to transfer commands from the host to the saa7380. the cmdi interrupt is generated when; the host writes to this register while the saa7380 is the selected drive (the drv bit in the adrsel register is equal to the rdrv bit in the dtctr register) the host writes the execute drive diagnostic command (90h) to this register. the bsy bit in the astat register is also set under these conditions. if the sub-cpu reads this register while cmdi is asserted then it will be negated. 7.7.25 adradr this write only register is the atapi drive address register. 7.7.26 asamt this register is the atapi sector number register. 7.7.27 adctr this read only register is the atapi device control register. if the srsti interrupt is asserted then reading this register will negate it. 7.7.28 adrsel table 21 adrsel register bits bit 4 of this register is the drv bit. when this bit is the same as the rdrv bit in the dtctr register then the saa7380 will be the selected atapi drive and will respond to host commands and produce host interrupts. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 111drv ---- 7.7.29 aintr this register is the atapi interrupt reason register. 7.7.30 afeat this read only register is the atapi features register. 7.7.31 aerr this write only register is the atapi error register. 7.7.32 dtctr - d ata t ransfer c ontrol r egister the dtctr register controls data transfer flows in the host interface block. on reset this register is cleared to all zeros except for the rdrv bit which is set to logic 1. this means that the saa7380 will be set to drive 1 after a reset. there are several possible data transfers through the saa7380 host interface block and these are selected using the trant bits. the transfers are described in the table 23.
1996 apr 25 24 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 table 22 data transfer control register bits table 23 trant transfer bits in the sanyo and oak compatibility modes the only transfers are memory-to-host, host-to-memory, sub-cpu-to-memory, and memory-to-sub-cpu. setting the trant bits to any other settings while in these host modes will cause undefined results. bit flag verbose description 7 res. - reserved 6 dmamode dma mode select logi c 0 = single-word; logic 1 = multi-word 5 udma use dma logi c 1 = dma; logic 0 = pio 4 subien subi enable logi c 1 = interrupt enabled 3 rdrv real drive select atapi drive number 2 trant - see table 23 1 0 trant from to maximum bytes notes bit 2 bit 1 bit 0 0 0 0 memory host 65535 (atapi) dma and pio 32767 (sanyo) 0 0 1 host memory 65535 (atapi) dma and pio 32767 (sanyo) 0 1 0 sub-cpu memory -- 0 1 1 memory sub-cpu -- 1 0 0 host sub-cpu 12 pio; dbc not used, always 12 bytes 1 0 1 sub-cpu host 12 dma and pio 1 1 x reserved reserved reserved -
1996 apr 25 25 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 7.8 sub-cpu interface the sub-cpu interface is a 3-wire synchronous serial protocol. the interface uses three signals; syn is used as a synchronization signal, sda is the bidirectional open-collector data signal and scl is the bit clock. the start of a command is signalled by a pulse on the syn input. after this pulse an 8-bit address byte will be sent by the sub-cpu. the format of this address byte is given in table 24. table 24 address byte format bit name description 7 device select if this bit is clear then the command will be for the saa7380 otherwise the command is for another device and the saa7380 will not respond. 6 address mode this bit controls the auto-increment function. after every byte has been read from or written to the saa7380 the address register is updated so that it is not necessary to re-send the address to read or write the following byte. the way the address register is updated is determined by the address mode bit. if the address mode bit is logic 0 then the address register will increment by 1 if it is currently in the range 1 to 14 or 16 to 30. if the address register is currently 15 or 31 then it will update to 0, if the address register is at logic 0 then it will remain at address 0. if the address mode bit is logic 1 then the address register will update in the following sequences; read: apcmd/comin -> apcmd/comin, ifstat -> dbcl -> dbch -> head0 -> head1 -> head2 -> head3 -> ptl -> pth -> pthh -> wal -> wah -> wahh -> stat0 -> stat1 -> stat2 -> stat3 -> apcmd/comin, acmd -> asmat -> adctr -> adrsel -> aintr -> afeat -> apcmd/comin. write: adata/sbout -> adata/sbout, ifctrl -> dbcl -> dbch -> dacl -> dach -> dachh -> dtrg -> dtack -> wal -> wah -> wahh -> ctrl0 -> ctrl1 -> ptl -> pth -> pthh -> sub_l ->sub_h -> 21 -> incnf -> mems -> astat -> itrg -> adradr -> asamt -> dtctr -> adrsel -> aintr -> aerr -> adata/sbout. 5 register number this is the address that is loaded into the address register and determines which register is accessed. 4 3 2 1 0r/ w if this bit is set to logic 0 then the sub-cpu will send one or more data bytes after the address byte. this data will be loaded into the specified registers. if this bit is set to logic 1 then after sending the address byte the sub-cpu will clock out the contents of one or more registers.
1996 apr 25 26 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 7.9 host registers 7.9.1 s anyo compatibility mode table 25 sanyo compatibility mode note 1. where x = dont care. hen cmd hrd hwr operation 0010 write comin 0001 read sbout 0110 write data 0101 read data 1 x x x none (note 1) fig.3 sub-cpu interface r/ w timing diagram. handbook, full pagewidth mge191 0 sda (from sub-cpu) 123456 7 0123456 7 scl syn read/write = 0 read/write = 1 0 sda (from sub-cpu) 123456 7 sda (from elm) 0123456 7 scl syn 7.9.1.1 comin this is a 12-byte fifo used for sending commands from the host to the sub-cpu. when the host writes to the comin register a sub-cpu cmdi interrupt is generated to indicate there are bytes in the comin fifo. this is cleared when the sub-cpu empties the fifo. if the host writes to the register when the fifo is full then the command is ignored. if the host writes to this register when the cmdbk bit in the ifctrl register is asserted then this will terminate any data or status byte transfers that are in progress. 7.9.1.2 sbout this is a 12 byte fifo used to transfer status bytes from the sub-cpu to the host. the host should only access this register when the sten pin is low indicating that there are status bytes available.
1996 apr 25 27 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 7.9.1.3 data transfer the other registers are used for data transfers. these can only occur when the sub-cpu has enabled a data transfer. this will be indicated to the host by the dten pin being low. 7.9.2 o ak compatibility mode table 26 oak compatibility mode note 1. where x = dont care. data transfer is selected when the transfer type is non-dma, the sub-cpu has started a data transfer and the dts bit in the hcon register has not been asserted. dma transfer is selected using the hcon register. the comin and sbout registers are similar to the same registers in the sanyo compatibility mode. 7.9.2.1 reset sub-cpu writing to this register causes the scrst pin to go low for several clock periods. the saa7380 registers are not affected. 7.9.2.2 tstat table 27 tstat register bits this is the host transfer status register. the eject bit reflects the state of the eject pin. bits eop, sten and dten have the same operation as the equivalent pins in the sanyo compatibility mode. bit wait is the same as the sanyo mode wait pin when non-dma transfer is selected otherwise it is logic 1. bit drq is the same as the sanyo mode wait pin when dma transfer is selected otherwise it is logic 0. dmack hen (1) da1 (1) da0 (1) hrd (1) hwr (1) data transfer selected (1) operation 100010 no write comin 100001 no read sbout 100010 yes write data 100001 yes read data 100110 x reset sub-cpu 100101 x read tstat 101010 x write hcon 1 1xxxx x none 0 x x x 1 0 x write dma data 0 x x x 0 1 x read dma data bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 1 eject w ait eop sten dten drq
1996 apr 25 28 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 7.9.2.3 hcon table 28 hcon register bits note 1. where x = dont care. this is the host configuration register. resetting saa7380 clears this register. bit 7 (1) bit 6 (1) bit 5 (1) bit 4 (1) bit 3 bit 2 bit 1 bit 0 x x x x dts sdrq lohi dma16 bit dts is the suspend transfer bit. setting this bit high suspends non-dma transfers and allows the host to access the comin and sbout registers. during dma transfers this bit has no effect. if sdrq is low and the selrq pin is low then dma transfer is selected otherwise non-dma transfer is selected. the pseudo 16-bit dma read transfer is selected by setting bit dma16 high. dma transfer must also be selected for this mode to operate. host writes are always 8-bit and are not affected by this bit. the lohi bit when high causes the pseudo 16-bit dma transfer to be a low byte followed by a high byte. setting it low causes the sequence to be a high byte followed by a low byte. if the 16-bit dma mode is not selected then this bit has no effect. 7.9.3 atapi m ode the following registers are accessible by the atapi host. most of these registers are identical to the sub-cpu registers with the same name. table 29 atapi registers address write hwr read hrd width cs2 cs1 da2 da1 da0 10000datadata16 10001 afeat aerr 8 10010 aintr aintr 8 10011 asamt asamt 8 10100 dbcl dbcl 8 10101 dbch dbch 8 10110 adrsel adrsel 8 10111 acmd astat 8 01110 adctr alt status 8 01111 reserved adradr 8
1996 apr 25 29 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 table 30 description of registers table 31 adrsel register bits table 32 adctr register bits setting the srst bit high causes a srsti interrupt and the bsy bit to be set. bit nien is used to enable or disable the host interrupt. when nien is logic 0 and the drive is selected then the host interrupt pin will be enabled. if nien is logic 1 or the drive is not selected then the host interrupt pin will be in a high-impedance state. register description data this is a 16-bit register and is used for transferring data to and from the host. this should only be performed after the sub-cpu has initiated the data transfer. afeat this is the atapi features register. aerr this is the atapi error register. aintr this is the atapi interrupt reason register. asamt this is the atapi sector count register. dbcl and dbch these are the atapi byte count registers. adrsel this is the atapi drive select register (see table 31). bit 4 of this register is the drv bit. when this bit is the same as the rdrv bit in the dtctr register then saa7380 will be the selected atapi drive and will respond to commands and produce interrupts. the host interrupt pin will also be enabled when saa7380 is the selected drive. acmd this is the atapi command register. a cmdi interrupt is generated when the host writes to this register while saa7380 is the selected drive (the drv bit in adrsel is equal to the rdrv bit in dtctr) and when the host writes the execute drive diagnostic command (90h) to this register. if a host interrupt is asserted then it will be cleared by writing to this register. astat this is the atapi status register. bit 7 is the bsy bit and this will be set whenever the host writes to the acmd register and saa7380 is the selected drive, when the host writes the execute drive diagnostic command (90h) to the acmd register, when the host writes to the adctr register and sets the srst bit and when there is a hardware reset. if a host interrupt is asserted then it will be cleared by writing to this register. alt status this is the atapi alternative status register. this is identical to the astat register except reading this register does not negate the host interrupt. adctr this is the atapi device control register (see table 32) adradr this is the atapi drive address register. bit 7 of this register is high impedance. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 111drv ---- bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved 1 srst nien 0
1996 apr 25 30 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 7.10 cd-dsp timings the timings are for 8 times speed with a 33 mhz crystal. fig.4 cd-dsp interface timing. handbook, full pagewidth mge192 t po t lc t hc t st t ht bck ws data
1996 apr 25 31 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... mge193 bck data 0 lsb error msb error lsb error msb error 15 left channel data 15 0 ws c2po fig.5 philips i 2 s-bus data format. c2po is sampled coincident with bits 14 and 12 of the incoming data. mge194 bck data lsb error msb error lsb error msb error right channel data 15 015 0 ws c2po fig.6 eiaj data format. c2po is sampled coincident with bits 14 and 12 of the incoming data.
1996 apr 25 32 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 8 limiting values in accordance with the absolute maximum rating system (iec 134). note 1. all v dd and v ss connections must be made externally to the same associated power supply. 9 thermal characteristics symbol parameter conditions min. max. unit v ddd1 digital supply voltage 1 note 1 - 0.5 +4.5 v v ddd2 digital supply voltage 2 note 1 - 0.5 +6.5 v v i(max) maximum input voltage on any input - 0.5 v ddd + 0.5 v v o output voltage on any output - 0.5 +6.5 v i o output current (continuous) - 20 ma i ik dc input diode current (continuous) - 20 ma p diss power dissipation - 400 mw t stg storage temperature - 55 +125 c t amb operating ambient temperature 0 +70 c symbol description value unit r thj-a thermal resistance from junction to ambient in free air 55 k/w
1996 apr 25 33 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 10 characteristics v ddd1 = 3.0 to 3.6 v; v ddd2 = 4.5 to 5.5 v; v ssd = 0; t amb = 0 to 70 c; unless otherwise stated. symbol parameter conditions min. typ. max. unit supply v ddd1 digital supply voltage 1 3.0 3.3 3.6 v v ddd2 digital supply voltage 2 4.5 5.0 5.5 v i ddd supply current v ddd1 = 3.3 v; v ddd2 =5v - 60 - ma i dddq quiescent supply current v ddd1 = 3.3 v; v ddd2 =5v - 100 - ma digital inputs i nput : reset (cmos input ) v th(r) switching threshold rising -- 0.8v ddd2 v v th(f) switching threshold falling 0.2v ddd2 -- v v hys hysteresis voltage - 0.33v ddd2 - v c i input capacitance -- 10 pf t rw reset pulse width reset only 1 --m s i nputs : sfsy, sub, bck, ws, data, c2po, scl, cs1/ hen, hwr, hrd, da0/cmd, dmack/selrq, da1, da2/eject, cs2 and syn (cmos input ) v il low level input voltage - 0.3 - 0.3v ddd2 v v ih high level input voltage 0.7v ddd2 - v ddd2 + 0.3 v i li input leakage current v i =0 - v ddd2 - 10 - +10 m a c i input capacitance -- 10 pf i nputs : test1 and test2 (cmos input ) v il low level input voltage - 0.3 - 0.3v ddd2 v v ih high level input voltage 0.7v ddd2 - v ddd2 + 0.3 v r pd input pull-down resistance v i =v ddd2 - 50 - k w c i input capacitance -- 10 pf digital outputs o utputs : ra0, ra1 to ra14, ra15/ras, ra16/cas, rwe, rck and scrst/ sten v ol low level output voltage i ol = 1 ma 0 - 0.4 v v oh high level output voltage i oh = - 1ma v ddd2 - 0.4 - v ddd2 v c l load capacitance -- 25 pf t r output rise time c l = 20 pf; 0.8 to (v ddd2 - 0.8) -- 10 ns t f output fall time c l = 20 pf; (v ddd2 - 0.8) to 0.8 -- 10 ns
1996 apr 25 34 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 o pen - drain outputs ; int, iocs16 v ol low level output voltage v ddd2 = 4.5 to 5.5 v; i ol =1ma 0 - 0.4 v i ol low level output current -- 2ma c l load capacitance -- 25 pf t f output fall time c l = 20 pf; 0.8 - (v ddd2 - 0.8) -- 20 ns 3-state outputs o utputs : irq/ eop/ hfbc, iordy/ w ait/ hfblb and dmarq/ dten v ol low level output voltage i ol = 1 ma 0 - 0.4 v v oh high level output voltage i oh = - 1ma v ddd2 - 0.4 - v ddd2 v c l load capacitance -- 50 pf t r output rise time c l = 20 pf; 0.8 - (v ddd2 - 0.8) -- 15 ns t f output fall time c l = 20 pf; (v ddd2 - 0.8) - 0.8 -- 15 ns i lz 3-state leakage current v i =0 - v ddd2 - 10 - +10 m a digital inputs/outputs i nputs and outputs : rd0 to rd7 v ol low level output voltage i ol = 1 ma 0 - 0.4 v v oh high level output voltage i oh = - 1ma v ddd2 - 0.4 - v ddd2 v v il low level input voltage - 0.3 - 0.3v ddd2 v v ih high level input voltage 0.7v ddd2 - v ddd2 + 0.3 v c l load capacitance -- 50 pf t r output rise time c l = 20 pf; 0.8 - (v ddd2 - 0.8) -- 15 ns t f output fall time c l = 20 pf; (v ddd2 - 0.8) - 0.8 -- 15 ns i lz 3-state leakage current v i =0 - v ddd2 - 10 - +10 m a i nputs and outputs : hd0 to hd15 v ol low level output voltage i ol = 1 ma 0 - 0.4 v v oh high level output voltage i oh = - 1ma v ddd2 - 0.4 - v ddd2 v v il low level input voltage - 0.3 - 0.3v ddd2 v v ih high level input voltage 0.7v ddd2 - v ddd2 + 0.3 v c l load capacitance -- 100 pf t r output rise time c l = 20 pf; 0.8 - (v ddd2 - 0.8) -- 5ns t f output fall time c l = 20 pf; (v ddd2 - 0.8) - 0.8 -- 5ns i lz 3-state leakage current v i =0 - v ddd2 - 10 - +10 m a symbol parameter conditions min. typ. max. unit
1996 apr 25 35 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 i nput and output : sda v il low level input voltage - 0.3 - 0.3v ddd2 v v ih high level input voltage 0.7v ddd2 - v ddd2 + 0.3 v i lz 3-state leakage current v i =0 - v ddd2 - 10 - +10 m a c i input capacitance -- 10 pf v ol low level output voltage i ol = 1 ma 0 - 0.4 v v oh high level output voltage i oh = - 1ma v ddd2 - 0.4 - v ddd2 v i ol low level output current -- 4ma c l load capacitance -- 100 pf t r output rise time c l = 25 pf; 0.8 - (v ddd2 - 0.8) -- 5ns t f output fall time c l = 25 pf; (v ddd2 - 0.8) - 0.8 -- 5ns crystal oscillator i nput : crin ( external clock ) i li input leakage current - 10 - +10 m a c i input capacitance -- 10 pf o utput : crout f xtal crystal frequency 15.2 33.8688 35 mhz gm mutual conductance at start-up - 4 - ma/v r o output resistance at start-up - 11 - k w c fb feedback capacitance -- 5pf c o output capacitance -- 10 pf symbol parameter conditions min. typ. max. unit
1996 apr 25 36 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 11 timing characteristics symbol parameter conditions min. typ. max. unit cd-dsp timing; see figs 4, 5 and 6; note 1 i nput : bck t po input clock period 40 - 1050 ns t hc clock high time 14 -- ns t lc clock low time 14 -- ns i nputs :ws and data t st set-up time 8 -- ns t ht hold time 0 -- ns q-to-w subcode timing; see figs 7 and 8; note 1 i nput : sfsy t fw sync pulse width 244 272 800 m s t f frame cycle 122 136 150 m s t lw low level period 1.5 68 -m s t hw high level period 4 68 -m s o utput : rck t cd output delay time 5 20 30 m s t hpw high level period 0.6 4 6 m s t lpw low level period 2 4 9 m s i nput : sub t hd data hold time 0 --m s t ac data access time -- 0.8 m s t pac p data access time - 24 m s sram interface timing; see figs 9 and 10; note 2 t rc read cycle period 6t -- ns t ds data set-up time 30 -- ns t dh data hold time 5 -- ns t wc write cycle time 6t -- ns t wp write pulse time 2t -- ns t as address set-up time t -- ns t wr write recovery time t -- ns t do data output time -- 30 ns
1996 apr 25 37 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 dram interface timing; see figs 11 and 12; note 2 t rc read or write cycle period 10t -- ns t pc page mode cycle time 4t -- ns t cac access time from cas -- 3t - 10 ns t rac access time from ras -- 7t - 10 ns t off output disable time from cas 0 -- ns t rhcp ras hold time from cas precharge page mode 4t -- ns t caa column address access -- 4t ns t rp ras high time 4t -- ns t ras ras low time 6t -- ns t rsh ras hold time 4t - 10 -- ns t cas cas low time 3t -- ns t csh cas hold time 7t - 10 -- ns t cp cas high pulse width t -- ns t crp delay cas high to ras 3t - 10 -- ns t rcd ras to cas delay time 2t -- ns t rad ras to column address delay t -- ns t asr row address set-up time 3t - 10 -- ns t rah row address hold time t -- ns t asc column address set-up time t -- ns t cah column address hold time 3t - 10 -- ns t ar column address hold time from ras low 5t - 10 -- ns t ral column address to ras lead 3t -- ns t rcs read set-up time before cas 4t - 10 -- ns t rch read command hold time t -- ns t rrh read command hold time from ras 2t - 10 -- ns t wch write command hold time 6t - 10 -- ns t wp write command low time 10t -- ns t wcr write command hold time from ras 8t - 10 -- ns t cwl write command to cas lead 9t - 10 -- ns t rwl write command to ras lead 8t - 10 -- ns t ds data output set-up time t -- ns t dh data output hold time 3t -- ns t dhr data output hold from ras 7t - 10 -- ns t rfsh refresh cycle time mems(3) = 0 -- 400t ns mems(3) = 1 -- 800t ns t csr cas set-up time for refresh 2t - 10 -- ns t chr cas hold time for refresh 6t - 10 -- ns t rpc precharge to cas active time t -- ns symbol parameter conditions min. typ. max. unit
1996 apr 25 38 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 sub-cpu timing; see fig.13 t 0 syn to ?rst scl 250 -- ns t 1 scl cycle time 500 -- ns t 2 time between bytes 250 -- ns t 3 data set-up 150 -- ns t 4 data hold 0 -- ns t 5 data access -- 150 ns atapi host interface timing; see fig.14 pio 8 and 16- bit transfer t 0 cycle time 33 mhz clock 150 -- ns 16 mhz clock 240 -- ns t 1 address to hwr/ hrd set-up 30 -- ns t 2 hwr/ hrd active 33 mhz clock 80 -- ns 16 mhz clock 100 -- ns t 2i hwr/ hrd inactive 33 mhz clock 70 -- ns 16 mhz clock 140 -- ns t 3 hwr data set-up 30 -- ns t 4 hwr data hold 10 -- ns t 5 hrd data set-up 50 -- ns t 6 hrd data 3-state -- 30 ns t 7 address to iocs16 only for 16-bit data register -- 30 ns t 8 address to iocs16 negate only for 16-bit data register -- 30 ns t 9 hwr/ hrd to address hold 10 -- ns t 10 iordy set-up -- 35 ns t 11 iordy width only if iordy negated -- 1250 ns t 12 read data valid to iordy active only if iordy negated 0 -- ns s ingle - word dma transfer ; see fig.15 t 0 cycle time 33 mhz clock 240 -- ns 16 mhz clock 480 -- ns t 1 dmack to dmarq -- 80 ns t 2 dmack to hwr/ hrd 0 -- ns t 3 hwr/ hrd active 33 mhz clock 120 -- ns 16 mhz clock 240 -- ns t 4 hwr/ hrd to dmack hold 0 -- ns t 5 hwr data set-up 35 -- ns t 6 hwr data hold 20 -- ns t 7 hrd data access -- 60 ns t 8 hrd data hold 5 -- ns symbol parameter conditions min. typ. max. unit
1996 apr 25 39 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 m ulti - word dma transfer ; see fig.16; note 3 t 0 cycle time 130 -- ns t 1 hwr/ hrd to dmarq inactive -- 40 ns t 2 dmack to hwr/ hrd 0 -- ns t 3 hwr/ hrd active 80 -- ns t 4 hwr/ hrd inactive 50 -- ns t 5 hwr/ hrd to dmack hold 5 -- ns t 6 hwr data set-up 30 -- ns t 7 hwr data hold 15 -- ns t 8 hrd data access -- 60 ns t 9 hrd data hold 5 -- ns t 10 dmack inactive to read data 3-state -- 25 ns sanyo compatibility mode host interface timing; see fig.17 comin and sbout access t 0 hen set-up 30 -- ns t 1 hen hold 0 -- ns t 2 cmd set-up 15 -- ns t 3 cmd hold 5 -- ns t 4 hwr/ hrd active 33 mhz clock 50 -- ns 16 mhz clock 75 -- ns t 5 hwr/ hrd data inactive 33 mhz clock 60 -- ns 16 mhz clock 145 -- ns t 6 hwr data set-up 50 -- ns t 7 hwr data hold 20 -- ns t 8 hrd data access -- 80 ns t 9 hrd data to 3-state 5 - 60 ns t 10 sten to hrd only for sbout read 0 -- ns t 11 hrd to sten inactive for last sbout read; 33 mhz clock -- 100 ns 16 mhz clock -- 145 ns t 12 hwr to dten/ sten inactive only for comin write when cmdbk = 0 -- 100 ns symbol parameter conditions min. typ. max. unit
1996 apr 25 40 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 w ait control data transfer ; see fig.18 t 0 hen set-up 30 -- ns t 1 hen hold 0 -- ns t 2 cmd set-up 15 -- ns t 3 cmd hold 5 -- ns t 4 hwr/ hrd active 33 mhz clock 50 -- ns 16 mhz clock 75 -- ns t 5 hwr/ hrd inactive 33 mhz clock 60 -- ns 16 mhz clock 145 -- ns t 6 hwr data set-up 50 -- ns t 7 hwr data hold 20 -- ns t 8 hrd data access -- 80 ns t 9 hrd data to 3-state 5 - 60 ns t 10 hwr/ hrd to w ait active -- 80 ns t 11 dten to hwr/ hrd 0 -- ns t 12 hwr/ hrd to dten inactive for last data transferred; 33 mhz clock -- 100 ns 16 mhz clock -- 145 ns t 13 hwr/ hrd to eop only for last data access -- 120 ns t 14 hwr/ hrd inactive to eop inactive only for last data access -- 120 ns drq control data transfer ; see fig.19 t 0 hen set-up 30 -- ns t 1 hen hold 0 -- ns t 2 cmd set-up 15 -- ns t 3 cmd hold 5 -- ns t 4 hwr/ hrd active 33 mhz clock 50 -- ns 16 mhz clock 75 -- ns t 5 hwr/ hrd data inactive 33 mhz clock 60 -- ns 16 mhz clock 145 -- ns t 6 hwr data set-up 50 -- ns t 7 hwr data hold 20 -- ns t 8 hrd data access -- 80 ns t 9 hrd data to 3-state 5 - 60 ns t 10 drq to hwr/ hrd 0 -- ns t 11 hwr/ hrd to drq inactive -- 80 ns t 12 dten to hwr/ hrd 0 -- ns t 13 hwr/ hrd to dten inactive for last data transferred; 33 mhz clock -- 100 ns 16 mhz clock -- 145 ns t 14 hwr/ hrd to eop only for last data access -- 120 ns symbol parameter conditions min. typ. max. unit
1996 apr 25 41 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 t 15 hwr/ hrd inactive to eop inactive only for last data access -- 120 ns oak compatibility mode host interface timing; see fig.20 comin, hcon write and sbout, tstat read t 0 hen set-up 30 -- ns t 1 hen hold 0 -- ns t 2 dmack set-up 30 -- ns t 3 dmack hold 0 -- ns t 4 address set-up 30 -- ns t 5 address hold 0 -- ns t 6 hwr/ hrd active 33 mhz clock 50 -- ns 16 mhz clock 75 -- ns t 7 hwr/ hrd inactive 33 mhz clock 60 -- ns 16 mhz clock 145 -- ns t 8 hwr data set-up 50 -- ns t 9 hwr data hold 20 -- ns t 10 hrd data access -- 80 ns t 11 hrd data to 3-state 5 - 60 ns r eset sub -cpu; see fig.21; note 4 t 0 hen set-up 30 -- ns t 1 hen hold 0 -- ns t 2 dmack set-up 30 -- ns t 3 dmack hold 0 -- ns t 4 address set-up 30 -- ns t 5 address hold 0 -- ns t 6 hwr active 33 mhz clock 50 -- ns 16 mhz clock 65 -- ns t 7 hwr inactive 33 mhz clock 60 -- ns 16 mhz clock 145 -- ns t 8 hwr to scrst -- 100 ns t 9 hwr inactive to scrst inactive 512clk -- ns n on -dma data transfer ; see fig.22; note 4 t 0 hen set-up 30 -- ns t 1 hen hold 0 -- ns t 2 dmack set-up 30 -- ns t 3 dmack hold 0 -- ns t 4 address set-up 30 -- ns t 5 address hold 0 -- ns t 6 hwr/ hrd active 33 mhz clock 50 -- ns 16 mhz clock 75 -- ns symbol parameter conditions min. typ. max. unit
1996 apr 25 42 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 notes 1. all timings are for single-speed, they should be divided by the speed up to eight times speed. 2. t represents half a clock period. 3. the timings for this mode can only be met with a 33 mhz clock. 4. clk = 1 clock period. t 7 hwr/ hrd inactive 33 mhz clock 60 -- ns 16 mhz clock 145 -- ns t 8 hwr data set-up 50 -- ns t 9 hwr data hold 20 -- ns t 10 hrd data access -- 80 ns t 11 hrd data to 3-state 5 - 60 ns t 12 cycle time 3clk -- ns 8- bit dma data transfer ; see fig.23 t 0 dmarq to dmack 0 -- ns t 1 hwr/ hrd to dmarq inactive -- 80 ns t 2 dmack set-up 30 -- ns t 3 dmack hold 0 -- ns t 4 hwr/ hrd active 33 mhz clock 50 -- ns 16 mhz clock 75 -- ns t 5 hwr/ hrd inactive 33 mhz clock 60 -- ns 16 mhz clock 145 -- ns t 6 hwr data set-up 50 -- ns t 7 hwr data hold 20 -- ns t 8 hrd data access -- 80 ns t 9 hrd data to 3-state -- 60 ns p seudo 16- bit dma read transfer ; see fig.24; note 4 t 0 hrd to dmarq inactive -- 80 ns t 1 dmarq to dmack 0 -- ns t 2 hrd inactive to dmack inactive 0 -- ns t 3 hrd active 33 mhz clock 50 -- ns 16 mhz clock 65 -- ns t 4 hfbc to data valid -- clk ns t 5 data 3-state to hfbc inactive clk -- ns t 6 hrd data access -- 80 ns t 7 hrd data to 3-state -- 60 ns t 8 hfbc active -- 5clk ns t 9 data valid to hfblb 2clk -- ns t 10 hfblb to hfbc inactive 2clk -- ns symbol parameter conditions min. typ. max. unit
1996 apr 25 43 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 11.1 q-to-w subcode interface timing fig.7 q-to-w subcode interface timing diagram. handbook, full pagewidth mge195 t fw t f t lw t hw sfsy rck sub p sf97 sf0 sf1 sf2 sf3 sf4 sf5 qrstuvw pqrstuvw pqrstuvw pqrstuvw pqrstuvw fig.8 q-to-w subcode timing diagram. handbook, full pagewidth mge196 t cd t lpw t pac t hd t hd t hd t ac t ac t hpw sfsy rck sub
1996 apr 25 44 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 11.2 external memory sram timing fig.9 read cycle timing diagram. handbook, full pagewidth mge197 address data t rc t ds t dh fig.10 write cycle timing diagram. handbook, full pagewidth mge198 address rwe data t wc t as t wr t wp t do
1996 apr 25 45 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 11.3 external memory dram timing fig.11 write cycle timing diagram. handbook, full pagewidth mge199 t rc t ar t ras t rp t csh t rcd t rsh t cas t crp t crp t asr t asc t rad t ral t rah t cah t wch t wcr t rwl t cwl t dhr t dh t ds t wp ras cas ra0 to ra13 row column rd0 to rd7 rwe
1996 apr 25 46 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 fig.12 read cycle timing diagram. handbook, full pagewidth mge200 t rc t ar t ras t rp t csh t rcd t rsh t cas t crp t crp t asr t asc t rad t ral t rah t cah t rch t rac t cac t rcs t rrh ras cas ra0 to ra13 row column input rd0 to rd7 rwe
1996 apr 25 47 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 11.4 sub-cpu interface timing fig.13 sub-cpu interface timing diagram. handbook, full pagewidth mge201 t 0 t 1 t 2 t 3 t 4 t 5 syn scl sda (sub-cpu to elm) sda (elm to sub-cpu) 0 1 7 11.5 atapi host interface timing fig.14 pio 8 and 16-bit transfer. handbook, full pagewidth t 0 t 1 t 2 t 9 t 2i t 4 t 3 t 6 t 5 t 7 t 8 t 10 t 12 t 11 mge202 address hwr/hrd write data valid read data valid iocs16 iordy valid
1996 apr 25 48 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 fig.15 single-word dma transfer. handbook, full pagewidth mge203 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 dmarq dmack hwr / hrd write data valid (hd0 to hd15) read data valid (hd0 to hd15) fig.16 multi-word dma transfer. handbook, full pagewidth mge204 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 dmarq dmack hwr/hrd write data valid (hd0 to hd15) read data valid (hd0 to hd15)
1996 apr 25 49 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 11.6 sanyo compatibility mode host interface timing fig.17 comin and sbout access. handbook, full pagewidth t 0 t 1 t 3 t 2 t 6 t 7 t 9 t 8 t 10 t 12 t 11 t 4 t 5 sten/dten (cmdbk = 0, comin write) sten (sbout read) sbout read (hd0 to hd7) comin write (hd0 to hd7) hwr/hrd cmd hen mge205
1996 apr 25 50 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 fig.18 wait control and data transfer. handbook, full pagewidth mge206 t 10 t 11 t 12 t 13 t 14 t 8 t 9 t 7 t 6 t 4 t 5 t 3 t 2 t 0 t 1 hen cmd hwr/hrd write data valid (hd0 to hd7) read data valid (hd0 to hd7) wait dten eop
1996 apr 25 51 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 fig.19 drq control data transfer. handbook, full pagewidth mge207 t 11 t 10 t 12 t 13 t 14 t 15 t 8 t 9 t 7 t 6 t 4 t 5 t 3 t 2 t 0 t 1 hen cmd hwr/hrd write data valid (hd0 to hd7) read data valid (hd0 to hd7) dten eop drq (wait)
1996 apr 25 52 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 11.7 oak compatibility mode host interface timing fig.20 comin, hcon write and sbout, tstat read. handbook, full pagewidth mge208 t 11 t 10 t 8 t 9 t 7 t 6 t 4 t 5 t 3 t 2 t 0 t 1 sbout, tstat read comin, hcon write hwr/hrd da1 to da0 dmack hen fig.21 reset sub-cpu. handbook, full pagewidth mge209 t 8 t 9 t 7 t 6 t 4 t 5 t 3 t 2 t 0 t 1 hwr da1 to da0 dmack hen don't care write scrst
1996 apr 25 53 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 fig.22 non-dma data transfer. handbook, full pagewidth mge210 t 11 t 12 t 10 t 8 t 9 t 7 t 6 t 4 t 5 t 3 t 2 t 0 t 1 hwr/hrd da1 to da0 dmack hen write data valid (hd0 to hd7) read data valid (hd0 to hd7) fig.23 8-bit dma data transfer. handbook, full pagewidth mge211 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 dmarq dmack hwr/hrd write data valid (hd0 to hd7) read data valid (hd0 to hd7)
1996 apr 25 54 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 11.8 crystal oscillator the crystal oscillator is a conventional 2 pin design operating at 15 to 35 mhz. this oscillator is also capable of operating with a ceramic resonator. it is capable of oscillating with both fundamental and third overtone mode crystals. external components should be used to suppress the fundamental output of the third overtone types as illustrated in fig.25. fig.24 pseudo 16-bit dma read transfer. handbook, full pagewidth mge212 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 read data valid (hd0 to hd7) hrd dmack dmarq hfbc hfblb first byte last byte fig.25 crystal oscillator circuit. handbook, halfpage mge213 100 k w 470 w 1 nf 10 pf 10 pf 25 mhz 3.3 m h oscillator saa7380 crout crin 3rd overtone only
1996 apr 25 55 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 12 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 2.90 2.65 0.25 0.45 0.30 0.25 0.14 14.1 13.9 0.8 1.95 18.2 17.6 1.4 1.2 1.2 0.8 7 0 o o 0.2 0.2 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.6 sot318-2 d (1) (1) (1) 20.1 19.9 h d 24.2 23.6 e z 1.0 0.6 d b p e q e a 1 a l p q detail x l (a ) 3 b 24 c b p e h a 2 d z d a z e e v m a 1 80 65 64 41 40 25 pin 1 index x y d h v m b w m w m 92-12-15 95-02-04 0 5 10 mm scale qfp80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm sot318-2 a max. 3.2
1996 apr 25 56 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 13 soldering 13.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 13.2 re?ow soldering reflow soldering techniques are suitable for all qfp and so packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference manual (order code 9397 750 00192). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. 13.3 wave soldering 13.3.1 qfp wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering the following packages: qfp52 (sot379-1), qfp100 (sot317-1), qfp100 (sot317-2), qfp100 (sot382-1) or qfp160 (sot322-1). 13.3.2 so wave soldering techniques can be used for all so packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream end. 13.3.3 m ethod (qfp and so) during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 13.4 repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1996 apr 25 57 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 14 definitions 15 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
1996 apr 25 58 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 notes
1996 apr 25 59 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (elm) saa7380 notes
philips semiconductors C a worldwide company argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. (02) 805 4455, fax. (02) 805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. (01) 60 101-1256, fax. (01) 60 101-1250 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. (172) 200 733, fax. (172) 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. (359) 2 689 211, fax. (359) 2 689 102 canada: philips semiconductors/components: tel. (800) 234-7381, fax. (708) 296-8556 chile: see south america china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. (852) 2319 7888, fax. (852) 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. (032) 88 2636, fax. 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(03) 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. (02) 709-1412, fax. (02) 709-1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. (03) 750 5214, fax. (03) 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. 9-5(800) 234-7831, fax. (708) 296-8556 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. (040) 2783749, fax. (040) 2788399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. (09) 849-4160, fax. (09) 849-7811 norway: box 1, manglerud 0612, oslo, tel. (022) 74 8000, fax. (022) 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. (63) 2 816 6380, fax. (63) 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. (022) 612 2831, fax. (022) 612 2327 portugal: see spain romania: see italy singapore: lorong 1, toa payoh, singapore 1231, tel. (65) 350 2000, fax. (65) 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. (011) 470-5911, fax. (011) 470-5494 south america: rua do rocio 220 - 5th floor, suite 51, cep: 04552-903-s?o paulo-sp, brazil, p.o. box 7383 (01064-970), tel. (011) 821-2333, fax. (011) 829-1849 spain: balmes 22, 08007 barcelona, tel. (03) 301 6312, fax. (03) 301 4107 sweden: kottbygatan 7, akalla. s-16485 stockholm, tel. (0) 8-632 2000, fax. (0) 8-632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. (01) 488 2211, fax. (01) 481 77 30 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1, p.o. box 22978, taipei 100, tel. (886) 2 382 4443, fax. (886) 2 382 4444 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. (66) 2 745-4090, fax. (66) 2 398-0793 turkey : talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. (0212) 279 2770, fax. (0212) 282 6707 ukraine: philips ukraine, 2a akademika koroleva str., office 165, 252148 kiev, tel. 380-44-4760297, fax. 380-44-4766991 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. (0181) 730-5000, fax. (0181) 754-8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. (800) 234-7381, fax. (708) 296-8556 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. (381) 11 825 344, fax. (359) 211 635 777 internet: http://www.semiconductors.philips.com/ps/ for all other countries apply to: philips semiconductors, marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31-40-2724825 scds48 ? philips electronics n.v. 1996 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. printed in the netherlands 517021/1200/01/pp60 date of release: 1996 apr 25 document order number: 9397 750 00806

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