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general description the max3969 is a recommended upgrade for the max3964 and max3968. the max3964a limiting amplifi- er, with 2mv p-p input sensitivity and pecl data outputs, is ideal for low-cost atm, fddi, and fast ethernet fiber optic applications. the max3964a features an integrated power detector that senses the input-signal power. it provides a received-signal-strength indicator (rssi), which is an analog indication of the power level and complementary pecl loss-of-signal (los) outputs, which indicate when the power level drops below a programmable threshold. the threshold can be adjusted to detect signal ampli- tudes as low as 2.7mv p-p . an optional squelch function disables switching of the data outputs by holding them at a known state during an los condition. the max3968 provides the same functionality as the max3964a, but has data-output edge speed suitable for escon and 266mbps fibre channel applications. the max3964a/max3968 are available in die form, as tested wafers, and in 20-pin qsop packages. the max3964aetp is available in a 20-pin thin qfn package. applications 125mbps fddi receivers 155mbps lan atm receivers fast ethernet receivers escon receivers 155mbps fttx receivers features ? single supply: +3.0v to +5.5v ? 2mv p-p input sensitivity ? 1.2ns output edge speed ? loss-of-signal detector with programmable threshold ? analog received-signal-strength indicator ? output squelch function ? compatible with 4b/5b data coding max3964a/max3968 +3.0v to +5.5v, 125mbps to 266mbps limiting amplifiers with loss-of-signal detector ________________________________________________________________ maxim integrated products 1 ordering information max3964a max3968 czn czp rssi los+ v cc c az 1 f v cc v cc filter v cc0 out- gnd filter 10nf c in 4700pf c in 4700pf 0.1 f out+ 155mbps tia in in- in+ los- out- out+ sub* gnd r2 50 ? 50 ? 50 ? 50 ? r1 100k ? inv *pin not available on max3964aetp. v cc - 2v squelch v cc v cc photodiode v th typical operating circuit 19-1314; rev 5; 8/06 pin configurations and selector guide appear at end of data sheet. * dice are designed to operate over a 0c to +100? junction temperature (tj) range, but are tested and guaranteed only at t a = +25?. ** package code: t2044-1 + denotes lead-free package. for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package max3964a etp -40? to +85? 20 thin qfn** max3964aetp+ -40? to +85? 20 thin qfn** max3964ac/d -40? to +85? dice* max3968 cep 0? to +70? 20 qsop max3968c/d 0? to +70? dice* evaluation kit available
max3964a/max3968 +3.0v to +5.5v, 125mbps to 266mbps limiting amplifiers with loss-of-signal detector 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics?max3964acep/max3968cep (v cc = +3.0v to +5.5v, pecl outputs terminated with 50 ? to (v cc - 2v), t a = 0? to +70?, unless otherwise noted. typical values are at v cc = +3.3v and t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (sub, gnd tied to ground) v cc , v cco .............................................................-0.5v to +7.0v filter, rssi, in+, in-, czp, czn, squelch, los+, los-, inv, vth, out+, out- ......-0.5v to (v cc + 0.5v) pecl output current (out+, out-, los+, los-) ............50ma differential voltage between czp and czn..........-1.5v to +1.5v differential voltage between in+ and in- .............-1.5v to +1.5v continuous power dissipation (t a = +70?) 20-lead thin qfn (derate 16.9mw/? above +70?) ............. .............1349mw 20-pin qsop (derate 6.7mw/? above +70?)...........500mw operating temperature range ...........................-40? to +85? operating junction temperature range (die) .....-40? to +150? processing temperature (die) ........................................+400? storage temperature range .......................... -65? to +160? lead temperature (soldering, 10s) ................................+300? parameter symbol conditions min typ max units supply current i cc pecl outputs open 22 40 ma los hysteresis input = 3.3mv p-p to 90mv p-p (note 2) 3.8 5 8.0 db squelch input current v squelch = v cc , t a = +25? 27 100 ? pecl output voltage high (note 3) -1025 -880 mv pecl output voltage low (note 3) -1810 -1620 mv pecl los output voltage high (note 3) -1035 -880 mv pecl los output voltage low (note 3) -1810 -1620 mv los assert accuracy input = 7mv p-p or 90mv p-p -2.5 +2.5 db minimum los assert input 2.7 mv p-p maximum los deassert input 143 mv p-p input sensitivity 2.0 3.3 mv p-p input overload 1.5 v p-p 20% to 80% transition time, max3964a 0.92 1.2 2.20 output transition time t r , t f max3968 0.4 0.8 1.2 ns pulse-width distortion (note 4) 50 200 ps
max3964a/max3968 +3.0v to +5.5v, 125mbps to 266mbps limiting amplifiers with loss-of-signal detector _______________________________________________________________________________________ 3 note 1: dice are tested and guaranteed at t a = +25? only. note 2: los hysteresis = 20log(v los-deassert / v los-assert ). note 3: voltage measurements are relative to supply voltage (v cc ). note 4: pwd = [(width of wider pulse) - (width of narrower pulse)] / 2, measured with 100mbps 1-0 pattern. electrical characteristics?max3964aetp (v cc = +3.0v to +5.5v, pecl outputs terminated with 50 ? to (v cc - 2v), t a = -40? to +85?. typical values measured at v cc = +3.3v and t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units supply current i cc pecl outputs open 22 45 ma los hysteresis input = 4.0mv p-p (note 2) 3.0 5 8.0 db squelch input current 27 100 ? pecl output voltage high (note 3) -1.085 -0.880 v pecl output voltage low (note 3) -1.830 -1.550 v input = 7mv p-p or 90mv p-p , 0? to +85? -3 +3 los assert accuracy input = 7mv p-p or 90mv p-p , -40? to 0? -3.6 +3.6 db minimum los assert input 2.7 mv p-p maximum los deassert input 143 mv p-p input sensitivity 24 mv p-p input overload 1.5 v p-p output transition time t r , t f 20% to 80% 1.6 2.4 ns pulse-width distortion (note 4) 50 250 ps p-p typical operating characteristics (max3964a ev kit, v cc = +3.3v, decibels (db) calculated as 20 log ? v, pecl outputs terminated with 50 ? to (v cc - 2v), t a = +25?, unless otherwise noted.) 1.00 1 100 1k 10 rssi voltage vs. input amplitude 2.00 3.00 1.50 2.50 max3964/65toc01 input amplitude (mv) v rssi (v) input pattern is 2 23 - 1 prbs los deasserted los asserted 1.5 1.6 1.7 1.9 1.8 2.0 2.2 2.1 2.3 -40 0 20 -20 40 60 80 100 rssi voltage vs. temperature max3964/65toc02 temperature ( c) v rssi (v) input = 100mv input = 10mv input = 5mv 100 30 1 100 1k 10 10k pulse-width distortion vs. input amplitude 40 50 60 max3964/65toc03 input amplitude (mv p-p ) pwd (ps) 70 80 90
max3964a/max3968 +3.0v to +5.5v, 125mbps to 266mbps limiting amplifiers with loss-of-signal detector 4 _______________________________________________________________________________________ typical operating characteristics (continued) (max3964a ev kit, v cc = +3.3v, decibels (db) calculated as 20 log ? v, pecl outputs terminated with 50 ? to (v cc - 2v), t a = +25?, unless otherwise noted.) 0 0.6 1.2 2.4 1.8 3.0 -50 0 -25 25 50 75 100 data output edge speed (20% to 80%) vs. temperature max3964/65toc04 temperature ( c) edge speed (ns) max3968 max3964a los operation with squelch max3964 toc06 data output los+ data input 10 s/div 1ns/div max3964a eye diagram (input = 3.3mv) max3964 toc07 200mv/div 1600 600 0.1 1 10 100 1k 10k output amplitude vs. input voltage (differential signal levels) 800 max3964/65toc05 input voltage (mv) output amplitude (mv) 1000 1200 1400
max3964a/max3968 +3.0v to +5.5v, 125mbps to 266mbps limiting amplifiers with loss-of-signal detector _______________________________________________________________________________________ 5 pin description pin qsop thin qfn name function 1 19 squelch squelch input. the squelch function disables the data outputs by forcing out- low and out+ high during a loss-of-signal condition. connect to gnd or leave unconnected to disable. connect to v cc to enable squelching. 2 20 v th output of internal op amp that sets loss-of-signal threshold voltage (figure 1). connect a resistor from v th to inv and from inv to ground (minimum resistance 100k ? ) to program the desired threshold voltage. 3 1 inv inverting input of internal op amp that sets loss-of-signal threshold voltage (figure 1). connect a resistor from v th to inv and from inv to ground (minimum resistance 100k ? ) to program the desired threshold voltage. 4 2 filter filter output of full-wave logarithmic detectors (fwds). the fwd outputs are summed together at filter to generate the received-signal-strength indicator (rssi). connect a capacitor from filter to v cc for proper operation. 5 3 rssi received-signal-strength indicator output. the analog dc voltage at rssi indicates the input signal power. the rssi output is reduced approximately 120mv when los+ is asserted. 6 4 in- inverting data input 7 5 in+ noninverting data input 8 sub substrate. connect to ground. 9, 10 6, 7, 8 gnd ground 11 9 czp auto-zero capacitor input. connect a capacitor between czp and czn to determine the offset- correction-loop bandwidth. 12 10 czn auto-zero capacitor input. connect a capacitor between czp and czn to determine the offset- correction-loop bandwidth. 13 11 v cco output buffer supply voltage. connect to the same potential as v cc , but filter v cco and v cc separately. 14 12 out+ noninverting pecl data output. terminate with 50 ? to (v cc - 2v). 15 13 out- inverting pecl data output. terminate with 50 ? to (v cc - 2v). 16 14 los- inverting loss-of-signal output. los- is asserted low when input power drops below the los threshold. this pin is pecl compatible and should be terminated with 50 ? to (v cc - 2v). 17 15 los+ noninverting loss-of-signal output. los+ is asserted high when input power drops below the los threshold. this pin is pecl compatible and should be terminated with 50 ? to (v cc - 2v). 18 16 v cco max3964a/max3968: this pin can be left open or connected to the positive supply. 19, 20 17, 18 v cc +3.0v to +5.5v supply voltage ?p exposed pad connect the exposed pad to board ground for optional electrical and thermal performance.
max3964a/max3968 +3.0v to +5.5v, 125mbps to 266mbps limiting amplifiers with loss-of-signal detector 6 _______________________________________________________________________________________ detailed description the max3964a contains a series of limiting amplifiers and power detectors, offset correction, data-squelch cir- cuitry, and pecl output buffers for data and loss-of-sig- nal (los) outputs. the max3968 provides pecl los outputs with data outputs suitable for 266mbps. figure 1 shows a functional diagram of the max3964a/max3968. limiting amplifiers a series of four limiting amplifiers provides gain of approximately 65db. power detector each amplifier stage contains a full-wave logarithmic detector (fwd), which indicates the rms input signal power. the fwd outputs are summed together at the filter pin where the signal is filtered by an external capacitor (cfilter) connected between filter and v cc . the filter signal generates the rssi output volt- age, which is proportional to the input power in deci- bels. when los+ is low, v rssi is approximated by the following equation: v rssi (v) = 1.2v + 0.5log (v in ) where v in is measured in mv p-p . this relation translates to a 25mv increase in v rssi for every 1db increase in v in (25mv/db). the rssi output is reduced approximately 120mv when los+ is asserted. pecl outputs the data outputs (out+, out-) and the max3964a/ max3968 loss-of-signal outputs (los+, los-) are sup- ply-referenced pecl outputs. standard pecl termina- tion at each output of 50 ? to (v cc - 2v) is recommended for best performance. input offset correction a low-frequency feedback loop around the limiting amplifier improves receiver sensitivity and powerdetec- tor accuracy. the offset-correction loop? bandwidth is determined by an external capacitor (caz) connected between the czp and czn pins. the offset correction is optimized for data streams with a 50% duty cycle. a different average duty cycle results in increased pulse-width distortion and loss of sensitivity. the offset-correction circuitry is less sensi- tive to variations of input duty cycle (for example, the 40% to 60% duty cycle encountered in 4b/5b coding) when the input is less than 30mv p-p . czn czp out+/out- los+/los- rssi squelch los+ los comparator filter in+/in- v cc v cco r1 r2 vtr sub gnd inv v cc c filter fwd = full-wave detector c az limiter offset correction limiter i i o limiter limiter fwd fwd fwd fwd 1.2v reference max3964a max3968 figure 1. functional diagram
max3964a/max3968 +3.0v to +5.5v, 125mbps to 266mbps limiting amplifiers with loss-of-signal detector _______________________________________________________________________________________ 7 loss-of-signal comparator the los comparator indicates when the input signal power is below the programmed los threshold. to ensure supply and temperature independence, vth is generated by a 1.2v bandgap reference. the op amp? external gain-setting resistors (r1 and r2) can be chosen to set v th between 1.2v and 2.4v. to ensure chatter-free operation, the los comparator is designed with approximately 5db of hysteresis. squelch the squelch function disables the data outputs by forc- ing out- low and out+ high during a los condition. this function ensures that when there is a loss of sig- nal, the limiting amplifier (and all downstream devices) does not respond to input noise or corrupt data. connect squelch to gnd or leave it unconnected to disable squelch. connect squelch to v cc to enable data squelching. applications information program the los threshold figure 2 provides information for selecting the los threshold voltage (v th ). if r1 is 100k ? and if the responsivities of the photodiode and preamplifier are known, then the value of r2 can be selected from figure 2 to provide los assert at the desired input power. select capacitors a typical max3964a/max3968 implementation requires four external capacitors (c az , c filter , and two input coupling capacitors). for all applications up to 266mbps, maxim recommends the following: c az = 1? c filter = 10nf c in = 4700pf wire bonding for high-current density and reliable operation, the max3964a series uses gold metalization. diepad size is 4mils square with a 6mil pitch. die thickness is 15mils. 0 20 80 60 40 120 100 -40 -36 -34 -38 -32 -30 -28 -26 optical input power at los assert (dbm) value of r2 (k ? ) 200kv/w 30kv/w 10kv/w 15kv/w 20kv/w 100kv/w figure 2. los assert programming resistor vs. los assert power (for various pin-tia gains )
max3964a/max3968 +3.0v to +5.5v, 125mbps to 266mbps limiting amplifiers with loss-of-signal detector 8 _______________________________________________________________________________________ 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 v cc v cc v cco los+ filter inv v th top view los- out- out+ v cco sub in+ in- rssi 12 11 9 10 czn czp gnd gnd qsop max3964a max3968 squelch 20 19 18 17 v th squelch v cc v cc 16 v cco 13 12 11 14 15 out+ out- los- los+ v cco 4 3 2 1 in- rssi filter inv 5 in+ 6 7 8 9 gnd gnd gnd czp 10 czn max3964aetp thin qfn squelch max3964a max3968 v cc v th v cc v cc0 czn czp gnd sub gnd 0.047" (1.19mm) 0.057" (1.45mm) los+ los- out- out+ v cco inv filter rssi in- in+ pin configurations chip topography transistor count: 915 substrate connected to sub sub connected to gnd on max3964aetp part data rate (mbps) los outputs max3964a* 125 to 155 pecl max3968 125 to 266 pecl selector guide * the max3964a is functionally equivalent to max3964, but offers slightly improved esd tolerance. the max3969 is a recommend- ed upgrade for the max3964, max3964a, and max3968.
max3964a/max3968 +3.0v to +5.5v, 125mbps to 266mbps limiting amplifiers with loss-of-signal detector _______________________________________________________________________________________ 9 qsop.eps f 1 1 21-0055 package outline, qsop .150", .025" lead pitch package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max3964a/max3968 +3.0v to +5.5v, 125mbps to 266mbps limiting amplifiers with loss-of-signal detector 10 ______________________________________________________________________________________ 24l qfn thin.eps package outline, 21-0139 2 1 e 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max3964a/max3968 +3.0v to +5.5v, 125mbps to 266mbps limiting amplifiers with loss-of-signal detector maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 11 2006 maxim integrated products is a registered trademark of maxim integrated products, inc. package outline, 21-0139 2 2 e 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) revision history rev 0; 10/98: initial data sheet release. rev 1; 10/02: added max3964etp. rev 2; 5/03: added package code for tqfn (page 1); updated package drawing (pages 11, 12). rev 3; 9/04: added max3964a (pages 1 to 13). rev 4; 2/06: added lead-free package information to ordering information table (page 1). rev 5; 8/06: removed references to max3964 and max3965, ttl loss of signal, gndo; updated caz value to 0.1? and cin from 10nf to 4700pf. updated typical application circuit.
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs m axim > p roduc ts > fiber and h igh-speed c ommunic ations max3964, max3965, max3968 +3.0v to +5.5v, 125mbps to 266mbps limiting amplifiers with loss-of-signal detector recommended upgrades for new designs part number replacement explanation max3964 max3969 improved performance and features max3964ac /d max3969 max3964aetp max3969 max3964aetp+ max3969 max3964evkit max3969 max3965 max3969 max3968 max3969 quickview technical documents ordering info more information all data sheet full data sheet (pdf, 296kb) download e-mail diagram typical operating circuit didn't find what you need? next day product selection assistance from applications engineers parametric search applications help quickview technical documents ordering info more information des c ription key features a pplic ations /u s es key spec ific ations diagram data sheet a pplic ation n otes des ign guides e ngineering journals reliability reports software/m odels e valuation kits p ric e and a vailability samples buy o nline p ac kage i nformation lead-free i nformation related p roduc ts n otes and c omments e valuation kits doc ument ref.: 1 9 -1 3 1 4 ; rev 5 ; 2 0 0 6 -0 8 -2 1 t his page las t modified: 2 0 0 7 -0 6 -0 5
c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y

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