View LC866412B_6515658.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

91400 rm (im) sk no.6699-1/21 ver.1.05 o0499 preliminary overview the lc866448b/44b/40b/36b/32b/28b/24b/20b/16b/12b/08b microcontrollers are 8-bit single chip microcontrollers with the following on-chip functional blocks: - cpu : operable at a minimum bus cycle time of 0.5s (microsecond) - on-chip rom maximum capacity : 48k bytes - on-chip ram capacity : 1152/768/640/512 bytes (lc866448b/44b/40b/36b/32b/28b/24b/20b/16b/12b/08b) - 16-bit timer /counter (or two 8-bit timers) - 16-bit timer /pwm (or two 8-bit timers) - 8-channel 8-bit ad converter - two 8-bit synchronous serial-interface circuits (1-channel 16bit, 1-channel 8bit) - 14-source 10-vectored interrupt system all of the above functions are fabricated on a single chip. 8-bit single chip microcontroller lc866448b/44b/40b/36b/32b/28b/24b/20b/16b/12b/08b ordering number : enn*6699 cmos ic
lc866448b/44b/40b/36b/32b/28b/24b/20b/16b/12b/08b no.6699-2/21 features (1) read-only memory (rom) : lc866448b 49152 8 bits : lc866444b 45056 8 bits : lc866440b 40960 8 bits : lc866436b 36864 8 bits : lc866432b 32768 8 bits : lc866428b 28672 8 bits : lc866424b 24576 8 bits : lc866420b 20480 8 bits : lc866416b 16384 8 bits : LC866412B 12288 8 bits : lc866408b 8192 8 bits (2) random access memory (ram) : lc866448b/44b/40b/36b 1152 8 bits : lc866432b/28b/24b 768 8 bits : lc866420b/16b 640 8 bits : LC866412B/08b 512 8 bits (3) bus cycle time/instruction cycle time the lc866448b/44b/40b/36b/32b/28b/24b/20b/16b/12b/08b are constructed to read rom twice within one instruction cycle. it has 1.7 times more performance capability within the same instruction cycle compared to our 4-bit microcomputers (lc66000 series). bus cycle time indicates the speed to read rom. bus cycle time cycle time clock divider system clock oscillation oscillation frequency voltage 0.5 s 1 s 1/1 ceramic resonator oscillation 6mhz 4.5v to 6.0v 2 s 4 s 1/1 ceramic resonator oscillation 3mhz 2.5v to 6.0v 7.5 s 15 s 1/1 rc resonator oscillation 800khz 2.5v to 6.0v 183 s 366 s 1/2 crystal oscillation 32.768khz 2.5v to 6.0v (4) ports - input/output ports : 1 port (8 terminals : port 1) input/output programmable in a bit - 15v withstand input/output ports : 2 ports (12 terminals) input/output port programmable in nibble unit : 1 port (8 terminals : port 0) (when the n-channel open drain output is selected, the data in a bit can be inputted.) input/output port programmable in a bit : 1 port (4 terminals : port 3) - input port : 2 ports (14 terminals : port 7,8) - vfd output port : 38 terminals large current output for digit : 16 terminals pull-down resistor option available - other function input/output port : 1 port (6 terminals : port e) input port : 2 ports (16 terminals : port c,d) (5) vfd automatic dislay controller -segment/digit output pattern programmable any segment/digit combination available vfd parallel-drive available - 16-step dimmer function available (6) ad converter - 8-channel 8-bit ad converter (7) serial-interface - 1 channel 16-bit serial-interface circuits - 1 channel 8-bit serial-interface circuits - lsb first / msb first function available - internal 8-bit baud-rate generator in common with two serial-interface circuits
lc866448b/44b/40b/36b/32b/28b/24b/20b/16b/12b/08b no.6699-3/21 (8) timer - timer 0 16-bit timer/counter 2-bit prescaler + 8-bit programmable prescaler mode 0 : two 8-bit timers with programmable prescaler mode 1 : 8-bit timer with programmable prescaler + 8-bit counter mode 2 : 16-bit timer with programmable prescaler mode 3 : 16-bit counter the resolution of timer is tcyc. (tcyc: cycle time) - timer 1 16-bit timer/pwm mode 0 : two 8-bit timers mode 1 : 8-bit timer + 8-bit pwm mode 2 : 16-bit timer mode 3 : variable-bit pwm (9-16 bits) in mode 0 and mode 1,the resolution of timer and pwm is tcyc. in mode 2 and mode 3,the resolution of timer and pwm selectable: tcyc or 1/2 tcyc by program - base timer every 500ms overflow system for a clock application (using 32.768khz crystal oscillation for base timer clock) every 976s, 3.9ms, 15.6ms, 62.5ms overflow system (using 32.768khz crystal oscillation for base timer clock) the base timer clock selectable; 32.768khz crystal oscillation, system clock, and programmable prescaler output of timer 0 (9) buzzer output - the buzzer sound frequency selectable; 4khz, 2khz (using 32.768khz crystal oscillation for base timer clock) (10) remote-control receiver circuit (shares with the p73/int3/t0in terminal) - noise rejection function (the time constant of noize rejection filter: 1tcyc/16tcyc/64tcyc) (tcyc: instruction cycle time) - switch polarity function (11) watchdog timer - the watchdog timer is taken on rc outside - watchdog timer operation selectable: interrupt system, system reset (12) interrupt system - 14-source 10-vectored interrupts : 1. external interrupt int0 (include watchdog timer) 2. external interrupt int1 3. external interrupt int2, timer/counter t0l (lower 8-bit) 4. external interrupt int3, base timer 5. timer/counter t0h (upper 8-bit) 6. timer t1l, timer t1h 7. serial-interface sio0 8. serial-interface sio1 9. ad converter 10. vfd automatic display controller, port 0 - built-in interrupt priority control register microcontroller allows 3 levels of interrupt; low level, high level, and highest level of multiplex interrupt. it can specify a low level or a high level interrupt priority from int2/t0l through port 0 (i.e. the above interrupt number from three through ten). it can also specify a low level or the highest level interrupt priority to int0 and int1.
lc866448b/44b/40b/36b/32b/28b/24b/20b/16b/12b/08b no.6699-4/21 (13) real-time service operation the real-time service (rts) functions the 4-byte data-transfer between the special function registers at acknowledging the interrupt request. the rts starts within 1 instruction cycle-time and completes within 5 instructions cycle-time after occurring the interrupt request. (14) subroutine stack levels - 128 levels (max.): stack area included in ram area (15) multiplication and division 16-bit 8-bit (7 instruction cycle times) 16-bit / 8-bit (7 instruction cycle times) (16) three oscillation circuits - on-chip rc oscillation circuit using for the system clock. - on-chip cf oscillation circuit using for the system clock. - on-chip crystal oscillation circuit using for the system clock and for time-base clock. (17) standby function - halt mode function the halt mode is used to reduce power dissipation. in this operation mode, program execution is stopped. this operation mode can be released by interrupt request signals or the initial system reset request signal. - hold mode function the hold mode is used to freeze all the oscillations; rc (internal), cf and crystal oscillations. this mode can be released by the following operations. reset terminal ( res ) set to low level p70/int0/t0in, p71/int1/t0in terminals set to assigned level (programmable) input a port 0 interrupt condition (18) factory shipment qfp80e delivery form (19) development support tools evaluation (eva) chip : lc866097 eprom version : lc86e6449 one time version : lc86p6449 emulator : eva-86000 + ecb866400 (evaluation chip board) + pod866400 (pod) notice for use 1. set vdd=4.0v to 6.0v at using s16 to s37 as input port. 2. follow the under table. frequency range of the system clock voltage range clock divider note 15khz to 30khz 1/1 can not use 1/2 divider 30khz to 6mhz 4.5v to 6.0v 1/1,1/2 15khz to 30khz 1/1 can not use 1/2 divider 30khz to 1.5mhz 1/1,1/2 1.5mhz to 3mhz 2.5v to 6.0v 1/2 can not use 1/1 divider 4.5v to 6.0v 1/1,1/2 internal rc oscillation 2.5v to 6.0v 1/2 can not use 1/1 divider
lc866448b/44b/40b/36b/32b/28b/24b/20b/16b/12b/08b no.6699-5/21 pin assignment qip80e package dimension (unit : mm) 3174 sanyo : qip-80e p00 p01 p02 p03 p04 p05 p06 p07 vss2 p10/so0 p11/si0/sb0 p12/sck0 p13/so1 p14/si1/sb1 p15/sck1 p16/buz s15/t15 s14/t14 s13/t13 s12/t12 s11/t11 s10/t10 s9/t9 s8/t8 s7/t7 s6/t6 s5/t5 s4/t4 s3/t3 s2/t2 s1/t1 s0/t0 p17/pwm0 p30 p31 p32 p33 p70/int0 res xt1/p74 xt2/p75 vss1 cf1 cf2 vdd1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7 p71/int1 p72/int2/t0i n p73/int3/t0i n s37/pe5 s36/pe4 s35/pe3 s34/pe2 s33/pe1 s32/pe0 s31/pd7 s30/pd6 s29/pd5 s28/pd4 s27/pd3 s26/pd2 s25/pd1 s24/pd0 s23/pc7 s22/pc6 s21/pc5 s20/pc4 s19/pc3 s18/pc2 s17/pc1 s16/pc0 vp vdd2 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
lc866448b/44b/40b/36b/32b/28b/24b/20b/16b/12b/08b no.6699-6/21 system block diagram interrupt control standby control ir rom pla cf rc x?tal clock generator pc base timer sio0 sio1 timer 0 timer 1 adc int0 to 3 noise filtter ram (128 bytes) port 1 port 3 port 7 port 8 bus interface acc b register c register psw rar ram stack pointer watchdog timer port 0 real time service alu high voltage output vfd controller
lc866448b/44b/40b/36b/32b/28b/24b/20b/16b/12b/08b no.6699-7/21 pin description pin name i/o function description option vss1,2 - power pin (-) short-circuit vss1 to vss2. - vdd1,2 - power pin (+) *1 refer to notes - vp - power pin (+) for the vfd output pull-down resistor - port0 p00 to p07 i/o 8-bit input/output port input for port 0 interrupt input/output in nibble units input for hold release 15v withstand at n-channel open drain output pull-up resistor : provided/not provided (each nibble) output form : cmos/n-channel open drain (each bit) port1 p10 to p17 i/o 8-bit input/output port input/output can be specified in a bit unit other pin functions p10 sio0 data output p11 sio0 data input/bus input/output p12 sio0 clock input/output p13 sio1 data output p14 sio1 data input/bus input/output p15 sio1 clock input/output p16 buzzer output p17 timer 1 output (pwm0 output) output form : cmos/n-channel open drain (each bit) port3 p30 to p33 i/o 4-bit input/output port input/output in bit unit 15v withstand at n-channel open drain output output form : cmos/n-channel open drain (each bit) 6-bit input port other pin functions p70 : int0 input/hold release/n-channel tr. output for watchdog timer p71 : int1 input/hold release input p72 : int2 input/timer 0 event input p73 : int3 input with noise filter/timer 0 event input p74 : 32.768khz crystal oscillation terminal xt1 p75 : 32.768khz crystal oscillation terminal xt2 interrupt received forms, the vector addresses pull-up resistor : provided/not provided (p70,71,72,73) * p74 , p75 don?t have the pull-up resistor option. rising falling rising & falling high level low level vector int0 enable enable disable enable enable 03h int1 enable enable disable enable enable 0bh int2 enable enable enable disable disable 13h port7 p70 p71 to p75 i/o i int3 enable enable enable disable disable 1bh continue.
lc866448b/44b/40b/36b/32b/28b/24b/20b/16b/12b/08b no.6699-8/21 pin name i/o function description option port8 p80 to 87 i 8-bit input port other function ad input port (8 port pins) - s0/t0 to s6/t6 o output for vfd display controller segment/timing in common pull-down resistor : provided/not provided (each nibble) s7/t7 to s15/t15 o output for vfd display controller segment/timing with internal pull-down resistor in common internal pull-down resistor output s16 to s31 i/o output for vfd display controller segment other function s16 : high voltage input port pc0 s17 : high voltage input port pc1 s18 : high voltage input port pc2 s19 : high voltage input port pc3 s20 : high voltage input port pc4 s21 : high voltage input port pc5 s22 : high voltage input port pc6 s23 : high voltage input port pc7 s24 : high voltage input port pd0 s25 : high voltage input port pd1 s26 : high voltage input port pd2 s27 : high voltage input port pd3 s28 : high voltage input port pd4 s29 : high voltage input port pd5 s30 : high voltage input port pd6 s31 : high voltage input port pd7 pull-down resistor : provided/not provided (each nibble) s32 to s37 i/o output for vfd display controller segment other function s32 : high voltage i/o port pe0 s33 : high voltage i/o port pe1 s34 : high voltage i/o port pe2 s35 : high voltage i/o port pe3 s36 : high voltage i/o port pe4 s37 : high voltage i/o port pe5 pull-down resistor : provided/not provided (each nibble) res i reset pin - xt1/ p74 i input pin for 32.768khz crystal oscillation other function p74 for input port in case of non use, connect to vdd1. - xt2/p75 o output pin for 32.768khz crystal oscillation other function p75 for input port in case of non use, at using as oscillator, should be left opened. at using as a port, connect to vdd1. - cf1 i input pin for the ceramic resonator oscillation - cf2 o output pin for the ceramic resonator oscillation - * all of port options (except pull-up resistor of port 0) can be specified in bit unit.
lc866448b/44b/40b/36b/32b/28b/24b/20b/16b/12b/08b no.6699-9/21 *a state of pins at reset pin name input/output mode a state of pull-up resistor specified at pull-up option port 0 input fixed pull-up resistor off ports 1,3 input programmable pull-up resistor off ports 70,71,72,73 input fixed pull-up resistor off s0/t0 to s15/t15 p channel transistor off s16 to s37 p channel transistor off [notes] when connecting to the power supply, the power pins must be connected like following figure. in case for the lc866448b/44b/40b/36b/32b/28b/24b/20b/16b/12b/08b in case for the lc866432a/28a/24a/20a/16a/12a/08a *1 each of the power pins, vdd1 and vdd2, should be connected the capacitors for reducing the noise into the vdd1 pin. lsi vdd1 vdd2 (vfd power pin) vss1 vss2 power supply for back-up lsi vdd1 vdd2 (vfd power pin) vss1 vss2 power supply for back-up
lc866448b/44b/40b/36b/32b/28b/24b/20b/16b/12b/08b no.6699-10/21 1. absolute maximum ratings at vss1=vss2=0v and ta=25 c ratings parameter symbol pins conditions v dd [v] min. typ. max. unit supply voltage vddmax vdd1,vdd2 vdd1=vdd2 -0.3 +7.0 vi(1) ports 71,72,73 ports 74 ,75 port 8 res -0.3 vdd+0.3 input voltage vi(2) vp vdd-45 vdd+0.3 output voltage vo s0/t0 to s15/t15 vdd-45 vdd+0.3 vio(1) port 1 port 70 ports 0, 3 at cmos output option -0.3 vdd+0.3 vio(2) ports 0, 3 at n-ch open drain output option -0.3 15 input/output voltage vio(3) s16 to s37 vdd-45 vdd+0.3 v ioph(1) ports 0, 1, 3 cmos output at each pins -10 ioph(2) s0/t0 to s15/t15 at each pins -30 peak output current ioph(3) s16 to s37 at each pins -15 ioah(1) ports 0, 1, 3 the total of all pins -30 ioah(2) s0/t0 to s15/t15 the total of all pins -55 high level output current total output current ioah(3) s16 to s37 the total of all pins -115 iopl(1) ports 0, 1, 3 at each pins 20 peak output current iopl(2) port 70 at each pins 15 ioal(1) port 0 the total of all pins 40 low level output current total output current ioal(2) ports 1,3 the total of all pins 40 ma maximum power dissipation pdmax qfp80e ta=-30 to+70c 480 mw operating temperature range topr -30 70 storage temperature range tstg -55 125 c
lc866448b/44b/40b/36b/32b/28b/24b/20b/16b/12b/08b no.6699-11/21 2. recommended operating range at ta=-30 c to +70 c, vss1=vss2=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit vdd(1) 0.98 s t cyc t cyc 400 s 4.5 6.0 operating supply voltage vdd(2) vdd1=vdd2 3.9 s t cyc t cyc 400 s 2.5 6.0 hold voltage vhd vdd1=vdd2 rams and the registers hold voltage at hold mode. 2.0 6.0 pull-down voltage vp vp 2.5 to 6.0 -35 vdd vih(1) port 0 at cmos output output disable 2.5 to 6.0 0.33vdd +1.0 vdd 4.0 to 6.0 0.8vdd 13.5 vih(2) port 0 at n-ch open drain output output disable 2.5 to 4.0 0.75vdd 13.5 vih(3) port 1 ports 72,73 port 3 at cmos output option output disable 2.5 to 6.0 0.75vdd vdd 4.5 to 6.0 0.8vdd 13.5 vih(4) port 3 at n-ch open drain output option output disable tr. off 2.5 to 4.0 0.75vdd 13.5 vih(5) port 70 port input/interrupt port 71 res output n-channel tr. off 2.5 to 6.0 0.75vdd vdd input high voltage vih(6) port 70 watchdog timer output n-channel tr. off 2.5 to 6.0 0.9vdd vdd vih(7) port 8 ports 74 ,75 using as port 2.5 to 6.0 0.75vdd vdd vih(8) s16 to s37 output p-channel tr. off 4.0 to 6.0 0.33vdd +1.0 vdd vil(1) port 0 at cmos output option output disable 2.5 to 6.0 vss 0.2vdd vil(2) port 0 at n-ch open drain output output disable 2.5 to 6.0 vss 0.25vdd vil(3) ports 1,3 ports 72,73 output disable 2.5 to 6.0 vss 0.25vdd vil(4) port 70 port input/interrupt port 71 res output n-channel tr. off 2.5 to 6.0 vss 0.25vdd vil(5) port 70 watchdog timer output n-channel tr. off 2.5 to 6.0 vss 0.8vdd -1.0 vil(6) port 8 ports 74 ,75 using as port 2.5 to 6.0 vss 0.25vdd input low voltage vil(7) s16 to s37 output p-channel tr. off 4.0 to 6.0 vp 0.2vdd v 4.5 to 6.0 0.98 400 operation cycle time t cyc 2.5 to 6.0 3.9 400 s continue.
lc866448b/44b/40b/36b/32b/28b/24b/20b/16b/12b/08b no.6699-12/21 ratings parameter symbol pins conditions vdd[v] min. typ. max. unit fmcf(1) cf1, cf2 6mhz (ceramic resonator oscillation) refer to figure 1 4.5 to 6.0 to be deter-mi n ed 6 to be deter-mi n ed fmcf(2) cf1, cf2 3mhz (ceramic resonator oscillation) refer to figure 1 2.5 to 6.0 to be deter-mi n ed 3 to be deter-mi n ed fmrc rc oscillation 2.5 to 6.0 0.3 0.8 3.0 mhz oscillation frequency range (note 1) fsxtal xt1, xt2 32.768khz (crystal oscillation) refer to figure 2 2.5 to 6.0 32.768 khz tmscf(1) cf1, cf2 6mhz (ceramic resonator oscillation) refer to figure 3 4.5 to 6.0 0..1 3.0 4.5 to 6.0 0.1 3.0 tmscf(2) cf1, cf2 3mhz (ceramic resonator oscillation) refer to figure 3 2.5 to 6.0 0.1 3.0 ms 4.5 to 6.0 0.7 0.8 oscillation stabilizing time period (note 1) tssxtal xt1, xt2 32.768khz (crystal oscillation) refer to figure 3 2.5 to 6.0 1.4 2.2 s (note 1) the oscillation constant is shown on table 1 and table 2.
lc866448b/44b/40b/36b/32b/28b/24b/20b/16b/12b/08b no.6699-13/21 3. electrical characteristics at ta=-30 c to +70 c, vss1=vss2=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iih(1) ports 0,3 at open drain output output disable vin=13.5v (including off-leakage current of the output tr.) 2.5 to 6.0 5 iih(2) port 0 without pull-up mos tr. ports 1,3 output disable pull-up mos tr. off. vin=vdd (including off-leakage current of the output tr.) 2.5 to 6.0 1 iih(3) ports 70,71,72,73 without pull-up mos tr. port 8 vin=vdd 2.5 to 6.0 1 iih(4) res vin=vdd 2.5 to 6.0 1 iih(5) ports 74 ,75 using as port vin=vdd 2.5 to 6.0 1 input high current iih(6) s16 to s37 without pull-down resistor (ports c,d,e) output disable vin=vdd 2.5 to 6.0 1 iil(1) ports 1,3 port 0 without pull-up mos tr. output disable pull-up mos tr. off. vin=vss (including off-leakage current of the output tr.) 2.5 to 6.0 -1 iil(2) ports 70,71,72,73 without pull-up mos tr. port 8 vin=vss 2.5 to 6.0 -1 iil(3) res vin=vss 2.5 to 6.0 -1 input low current iil(4) ports 74 ,75 vin=vss using as port 2.5 to 6.0 -1 a voh(1) ioh=-1.0ma 4.5 to 6.0 vdd-1 voh(2) ports 0,1,3 of cmos output ioh=-0.1ma 2.5 to 6.0 vdd-0.5 voh(3) ioh=-20ma 4.5 to 6.0 vdd-1.8 voh(4) s0/t0 to s15/t15 ioh=-1ma the current of any unmeasurement pin is not over 1ma. 2.5 to 6.0 vdd-1 voh(5) ioh=-5ma 4.5 to 6.0 vdd-1.8 output high voltage voh(6) s16 to s37 the current of any unmeasurement pin is not over 1ma. 2.5 to 6.0 vdd-1 vol(1) iol=10ma 4.5 to 6.0 1.5 vol(2) iol=1.6ma 4.5 to 6.0 0.4 vol(3) ports 0,1,3 iol=1.0ma the current of any unmeasurement pin is not over 1ma. 2.5 to 6.0 0.4 vol(4) iol=1ma 4.5 to 6.0 0.4 output low voltage vol(5) port 70 iol=0.5ma 2.5 to 6.0 0.4 v 4.5 to 6.0 15 40 70 pull-up mos tr. resistor rpu ports 0,1,3 ports 70,71,72,73 voh=0.9vdd 2.5 to 4.5 25 70 150 k ? continue.
lc866448b/44b/40b/36b/32b/28b/24b/20b/16b/12b/08b no.6699-14/21 ratings parameter symbol pins conditions vdd[v] min. typ. max. unit ioff(1) output p-channel tr. off vout=vss 2.5 to 6.0 -1 output off- leak current ioff(2) s0/t0 to s6/t6, s16 to s37 without pull-down resistor output p-channel tr. off vout=vdd-40v 2.5 to 6.0 -30 a resistance of the low level hold tr. rinpd s16 to s37 output p-channel tr. off using as input ports 4.0 to 6.0 200 high voltage pull-down resistor rpd s0/t0 to s15/t15, s16 to s37 without pull-down resistor output p-channel tr. off vout=3v vp=-30v 5.0 60 100 200 k ? hysteresis voltage vhis port 1 ports 70,71,72,73 res output disable 2.5 to 6.0 0.1vdd v pin capacitance cp all pins f=1mhz vin=vss for all unmeasured terminals. ta=25c 2.5 to 6.0 10 pf 4. serial input/output characteristics / ta=-30 c to +70 c, vss1=vss2=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit cycle t ckcy (1) 2 low level pulse width t ckl (1) 1 input clock high level pulse width t ckh (1) sck0,sck1 refer to figure 5 2.5 to 6.0 1 cycle t ckcy (2) 2 low level pulse width t ckl (2) 1/2t ckcy serial clock output clock high level pulse width t ckh (2) sck0,sck1 use pull-up resistor (1k ? ) in the open drain output. refer to figure 5 2.5 to 6.0 1/2t ckcy t cyc 4.5 to 6.0 0.1 data set-up time t ick 2.5 to 6.0 0.4 4.5 to 6.0 0.1 serial input data hold time t cki si0,si1 sb0,sb1 data set-up to sck0,1 data hold from sck0,1 refer to figure 5 2.5 to 6.0 0.4 4.5 to 6.0 7/12 t cyc +0.2 output delay time (external clock using for serial transfer clock) t cko(1) 2.5 to 6.0 7/12 t cyc +1 4.5 to 6.0 1/3 t cyc +0.2 serial output output delay time (internal clock using for serial transfer clock) t cko(2) so0,so1 sb0,sb1 use pull-up resistor (1k ? ) in the open drain output. data hold from sck0,1 refer to figure 5 2.5 to 6.0 1/3 t cyc +1 s
lc866448b/44b/40b/36b/32b/28b/24b/20b/16b/12b/08b no.6699-15/21 5. pulse input conditions at ta=-30 c to +70 c, vss1=vss2=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit tpih(1) tpil(1) int0, int1 int2/t0in interrupt acceptable timer0-countable 2.5 to 6.0 1 tpih(2) tpil(2) int3/t0in (the noise rejection clock selected to 1/1.) interrupt acceptable timer0-countable 2.5 to 6.0 2 tpih(3) tpil(3) int3/t0in (the noise rejection clock selected to 1/16.) interrupt acceptable timer0-countable 2.5 to 6.0 32 tpih(4) tpil(4) int3/t0in (the noise rejection clock selected to 1/64.) interrupt acceptable timer0-countable 2.5 to 6.0 128 t cyc high/low level pulse width tpil(5) res reset acceptable 2.5 to 6.0 200 s 6. ad converter characteristics at ta=-30 c to + 70 c, vss1=vss2=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit resolution n 4.5 to 6.0 8 bit absolute precision (note 2) et 4.5 to 6.0 1.5 lsb ad conversion time = 16 tcyc (adcr2=0) (note 3) 15.68 (tcyc= 0.98 s) 65.28 (tcyc= 4.08 s) conversion time tcad ad conversion time = 32 tcyc (adcr2=1) (note 3) 4.5 to 6.0 31.36 (tcyc= 0.98 s) 130.56 (tcyc= 4.08 s) s analog input voltage range vain 4.5 to 6.0 vss vdd v iainh vain=vdd 4.5 to 6.0 1 analog port input current iainl an0 to an7 vain=vss 4.5 to 6.0 -1 a (note 2) absolute precision excepts the quantizing error (1/2 lsb). (note 3) the conversion time means the time from executing the ad conversion instruction to setting the complete digital conversion value to the register.
lc866448b/44b/40b/36b/32b/28b/24b/20b/16b/12b/08b no.6699-16/21 7. current dissipation characteristics at ta=-30 c to +70 c, vss1=vss2=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iddop(1) fmcf=6mhz ceramic resonator oscillation fsxtal=32.768khz crystal oscillation system clock : cf oscillation internal rc oscillation stops 1/1 divided 4.5 to 6.0 10 25 iddop(2) 4.5 to 6.0 3 9 iddop(3) fmcf=3mhz ceramic resonator oscillation fsxtal=32.768khz crystal oscillation system clock : cf oscillation internal rc oscillation stops 1/2 divided 2.5 to 4.5 1.5 5 iddop(4) 4.5 to 6.0 0.7 3.4 iddop(5) fmcf=0hz (the oscillation stops) fsxtal=32.768khz crystal oscillation system clock : rc oscillation 1/2 divided 2.5 to 4.5 0.4 2.8 ma iddop(6) 4.5 to 6.0 35 130 current dissipation during basic operation (note 4) iddop(7) fmcf=0hz (the oscillation stops) fsxtal=32.768khz crystal oscillation system clock : 32.768khz internal rc oscillation stops 1/2 divided 2.5 to 4.5 15 70 a continue.
lc866448b/44b/40b/36b/32b/28b/24b/20b/16b/12b/08b no.6699-17/21 ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iddhalt(1) halt mode fmcf=6mhz ceramic resonator oscillation fsxtal=32.768khz crystal oscillation system clock : cf oscillation internal rc oscillation stops 1/1 divided 4.5 to 6.0 5 14 iddhalt(2) 4.5 to 6.0 2.2 7 iddhalt(3) halt mode fmcf=3mhz ceramic resonator oscillation fsxtal=32.768khz crystal oscillation system clock : cf oscillation internal rc oscillation stops 1/2 divided 2.5 to 4.5 0.8 4 ma iddhalt(4) 4.5 to 6.0 400 1600 iddhalt(5) halt mode fmcf=0hz (the oscillation stops) fsxtal=32.768khz crystal oscillation system clock : rc oscillation 1/2 divided 2.5 to 4.5 200 1300 iddhalt(6) 4.5 to 6.0 25 100 current dissipation in halt mode (note 4) iddhalt(7) halt mode fmcf=0hz (the oscillation stops) fsxtal=32.768khz crystal oscillation system clock : crystal oscillation internal rc oscillation stops 1/2 divided 2.5 to 4.5 8 55 iddhold(1) 4.5 to 6.0 0.05 30 current dissipation in hold mode (note 4) iddhold(2) hold mode 2.5 to 4.5 0.02 20 a (note 4) the currents of the output transistors and the pull-up mos transistors are ignored.
lc866448b/44b/40b/36b/32b/28b/24b/20b/16b/12b/08b no.6699-18/21 table 1. ceramic resonator oscillation recommended constant (main-clock) oscillation type maker oscillator c1 c2 csa6.00mg 33pf 33pf murata cst6.00mgw on chip kbr-6.0msb 33pf 33pf pbrc6.00a(chip type) 33pf 33pf kbr-6.0mkc 6mhz ceramic resonator oscillation kyocera pbrc6.00b(chip type) on chip csa3.00mg 33pf 33pf murata cst3.00mgw on chip 3mhz ceramic resonator oscillation kyocera kbr-3.0ms 47pf 47pf * both c1 and c2 must be use k rank (10%) and sl characteristics. table 2. crystal oscillation guaranteed constant (sub-clock) oscillation type maker oscillator c3 c4 rd 32.768khz crystal oscillation epson c-002rx 18pf 18pf 680k ? * both c3 and c4 must be use j rank (5%) and ch characteristics. (not in need of high precision, use k rank (10%) and sl characteristics.) (notes) please place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length since the circuit pattern affects the oscillation frequency. if you use other oscillators herein, we provide no guarantee for the characteristics. figure 1 main-clock circuit figure 2 sub-clock circuit ceramic resonator oscillation crystal oscillation cf c2 c1 cf1 cf2 xt1 xt2 rd c4 c3 x?tal
lc866448b/44b/40b/36b/32b/28b/24b/20b/16b/12b/08b no.6699-19/21 < reset time and oscillation stabilizing time. > < hold release signal and oscillation stabilizing time. > figure 3 oscillation stable time power supply res interrnal rc resonator oscillation xt1, xt2 operation mode hold release signal interrnal rc resonator oscillation cf1, cf2 operation mode cf1, cf2 xt1, xt2 vdd vdd limit ov reset time tmscf tssxtal unfixed reset instruction execution mode valid hold instruction execution mode instruction execution mode ocr6=1 tmscf tssxtal
lc866448b/44b/40b/36b/32b/28b/24b/20b/16b/12b/08b no.6699-20/21 figure 4 reset circuit figure 5 serial input / output test condition figure 6 pulse input timing condition tpih tpil so0, so1 sb0, sb1 si0 si1 sck0 sck1 tc k o tc ki t i c k tc kh tc kl tc k c y 0.5vdd 50 p f 1k ? s, after power supply has been over inferior limit of supply voltage. c res vdd r res res
lc866448b/44b/40b/36b/32b/28b/24b/20b/16b/12b/08b no.6699-21/21 memo: ps

▲Up To Search▲

Price & Availability of LC866412B

	To Download LC866412B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .