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| sharc and the sharc logo are registered trademarks of ana log devices, inc. sharc processor adsp-21469 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the proper ty of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.3113 ? 2010 analog devices, inc. all rights reserved. summary high performance 32-bit/40-bi t floating-point processor optimized for high performance audio processing single-instruction, multiple-data (simd) computational architecture 5 mbits of on-chip ram, 4 mbits of on-chip rom up to 450 mhz operating frequency qualified for automotive applications, see automotive prod- ucts on page 70 code compatible with all other members of the sharc family the adsp-21469 processor is available with unique audio- centric peripherals such as the digital applications interface, dtcp (digital transmission content protection protocol), serial ports, precision clock generators, s/pdif transceiver, asynchronous samp le rate converters, input data port, and more. for complete ordering information, see ordering guide on page 70 figure 1. function al block diagram internal memory i/f block 0 ram/rom b0d 64-bit instruction cache 5 stage sequencer pex pey pmd 64-bit iod0 32-bit epd bus 64-bit core bus cross bar dai routing/pins s/pdif tx/rx pcg a - d dpi routing/pins spi/b uart block 1 ram/rom block 2 ram block 3 ram ami ddr2 ctl ep external port pin mux timer 1 - 0 sport 7 - 0 asrc 3 - 0 pwm 3 - 0 dag1/2 timer pdap/ idp 7 - 0 twi iod0 bus dtcp/ mtm pcg c - d core flags jtag dmd 64-bit pmd 64-bit dmd 64-bit core flags iod1 32-bit peripheral bus b1d 64-bit b2d 64-bit b3d 64-bit dpi peripherals dai peripherals peripherals external port s thermal diode fft fir iir link port 1 - 0 mlb spep bus internal memory simd core peripheral bus 32-bit flagx/irqx/ tmrexp
rev. 0 | page 2 of 72 | june 2010 adsp-21469 table of contents summary ............................................................... 1 revision history ...................................................... 2 general description ................................................. 3 family core architecture ........................................ 4 family peripheral architecture ................................ 7 system design .................................................... 10 development tools ............................................. 11 additional information ........................................ 11 related signal chains .......................................... 11 pin function descriptions ....................................... 12 unused ddr2 pins ............................................. 12 specifications ........................................................ 17 operating conditions .......................................... 17 electrical characteristics ....................................... 18 absolute maximum ratings ................................... 20 esd sensitivity ................................................... 20 package information ............................................ 20 timing specifications ........................................... 21 test conditions .................................................. 58 output drive currents ......................................... 58 capacitive loading .............................................. 59 thermal characteristics ........................................ 61 csp_bga ball assignmentautomotive models .......... 63 csp_bga ball assignmentstandard models .............. 66 outline dimensions ................................................ 69 surface-mount design .......................................... 69 automotive products .............................................. 70 ordering guide ..................................................... 70 revision history 6/10revision 0: initial version adsp-21469 rev. 0 | page 3 of 72 | june 2010 general description the adsp-21469 sharc ? processor is a member of the simd sharc family of dsps that feat ure analog devices super har- vard architecture. the processor is source code compatible with the adsp-2126x, adsp-2136x, adsp-2137x, and adsp-2116x dsps, as well as with first ge neration adsp-2106x sharc pro- cessors in sisd (single-instru ction, single-data) mode. the processor is a 32-bit/40-bit floating point processor optimized for high performance audio applic ations with its large on-chip sram, multiple internal buses to eliminate i/o bottlenecks, and an innovative digital applications interface (dai). table 1 shows performance benchmarks for the adsp-21469 processor, and table 2 shows the products features. figure 1 on page 1 shows the two clock domains that make up the adsp-21469 processors. the core clock domain contains the following features: ? two processing elements (p ex, pey), each of which com- prises an alu, multiplier, shifter, and data register file ? data address generators (dag1, dag2) ? program sequencer wi th instruction cache ? one periodic interval timer with pinout ? pm and dm buses capable of supporting 2 64-bit data transfers between me mory and the core at every core pro- cessor cycle ?on-chip sram (5m bit) ?on-chip mask-progr ammable rom (4m bit) ? jtag test access port for em ulation and boundary scan. the jtag provides software debug through user break- points which allows flex ible exception handling. figure 1 on page 1 also shows the peripher al clock domain (also known as the i/o processor) which contains the following features: ?iod0 (peripheral dma) and iod1 (external port dma) buses for 32-bit data transfers ? peripheral and external port buses for core connection ? external port with an ami and ddr2 controller ? 4 units for pwm control ? 1 mtm unit for internal-to-internal memory transfers table 1. processor benchmarks benchmark algorithm speed (at 450 mhz) 1024 point complex fft (radix 4, with reversal) 20.44 ? s fir filter (per tap) 1 1 assumes two files in multichannel simd mode 1.11 ns iir filter (per biquad) 1 4.43 ns matrix multiply (pipelined) [3 3] [3 1] [4 4] [4 1] 10.0 ns 17.78 ns divide (y/x) 6.67 ns inverse square root 10.0 ns table 2. sharc family features feature adsp-21469 maximum frequency 450 mhz ram 5m bits rom n/a audio decoders in rom 1 no dtcp hardware accelerator 2 no pulse-width modulation yes s/pdif yes ddr2 memory interface yes ddr2 memory bus width 16 bits direct dma from sports to external memory yes fir, iir, fft accelerator yes mlb interface automotive models only idp yes serial ports 8 dai (sru)/dpi (sru2) 20/14 pins uart 1 link ports 2 ami interface with 8-bit support yes spi 2 twi yes src performance C128 db package 324-ball csp_bga 1 audio decoding algorithms include pcm, dolby digital ex, dolby pro logic iix, dts 96/24, neo:6, dts es, mpeg-2 aac, mp3, and functions like bass management, delay, speake r equalization, graphic equalization, and more. decoder/postprocessor algorithm combin ation support varies depending upon the chip version and the system configurations. please visit www.analog.com for complete product information and availability. 2 these products contain the digital tran smission content protection protocol, a proprietary security protocol. contact yo ur analog devices sales office for more information. table 2. sharc family features (continued) feature adsp-21469 rev. 0 | page 4 of 72 | june 2010 adsp-21469 ? digital applications interface that includes four precision clock generators (pcg), an input data port (idp) for serial and parallel interconnect, an s/pdif receiver/transmitter, four asynchronous sample rate converters, eight serial ports, a flexible signal routing unit (dai sru). ? digital peripheral interface that includes two timers, a 2- wire interface, one uart, two serial peripheral interfaces (spi), 2 precision clock generators (pcg) and a flexible signal routing unit (dpi sru). as shown in figure 1 on page 1 , the processor uses two compu- tational units to deliver a significant performance increase over the previous sharc processors on a range of dsp algorithms. with its simd computational hardware, the processors can perform 2.7 gflops running at 450 mhz and 2.4 gflops running at 400 mhz. family core architecture the adsp-21469 is code compatible at the assembly level with the adsp-2137x, adsp-2136x , adsp-2126x, adsp-21160, and adsp-21161, and with the first generation adsp-2106x sharc processors. the adsp-21469 shares architectural fea- tures with the adsp-2126x, adsp-2136x, adsp-2137x, and adsp-2116x simd sharc processors, as shown in figure 2 and detailed in the following sections. simd computational engine the adsp-21469 contains two computational processing elements that operate as a single-instruction, multiple-data (simd) engine. the processing el ements are referred to as pex and pey and each contains an alu, multiplier, shifter, and register file. pex is always active, and pey may be enabled by setting the peyen mode bit in the mode1 register. when this mode is enabled, the same instru ction is executed in both pro- cessing elements, but each proc essing element operates on different data. this architecture is efficient at executing math intensive dsp algorithms. entering simd mode also has an effect on the way data is trans- ferred between memory and the processing elements. when in simd mode, twice the data bandwidth is required to sustain computational operation in the processing elements. because of this requirement, entering simd mode also doubles the band- width between memory and the processing elements. when using the dags to transfer data in simd mode, two data values are transferred with ea ch access of memory or the register file. independent, paralle l computation units within each processing element is a set of computational units. the computational units consist of an arithmetic/logic unit (alu), multiplier, and shifter. these units perform all opera- tions in a single cycle. the thre e units within each processing element are arranged in paralle l, maximizing computational throughput. single multifunctio n instructions execute parallel alu and multiplier operations. in simd mode, the parallel alu and multiplier operations occur in both processing ele- ments. these computation unit s support ieee 32-bit single- precision floating-point, 40-bit extended precision floating- point, and 32-bit fixed-point data formats. timer a core timer that can generate pe riodic software interrupts. the core timer can be configured to use flag3 as a timer expired signal. data register file a general-purpose data register file is contained in each pro- cessing element. the register fi les transfer data between the computation units and the data buses, and store intermediate results. these 10-port, 32-regist er (16 primary, 16 secondary) register files, combined with the processors enhanced harvard architecture, allow unconstrained data flow between computa- tion units and internal memory. the registers in pex are referred to as r0-r15 and in pey as s0-s15. context switch many of the processors register s have secondary registers that can be activated during interrupt servicing for a fast context switch. the data registers in the register file, the dag registers, and the multiplier result register s all have secondary registers. the primary registers are active at reset, while the secondary registers are activated by control bits in a mode control register. universal registers these registers can be used fo r general-purpose tasks. the ustat (4) registers allow easy bit manipulations (set, clear, toggle, test, xor) for all system registers (control/status) of the core. the data bus exchange register (px) permits data to be passed between the 64-bit pm data bus and the 64-bit dm data bus, or between the 40-bit register file and the pm/dm data buses. these registers contain hardware to handle the data width difference. single-cycle fetch of instruction and four operands the processors feature an enhanced harvard architecture in which the data memory (dm) bu s transfers data and the pro- gram memory (pm) bus transfer s both instructions and data (see figure 2 ). with the its separate program and data memory buses and on-chip instruction ca che, the processor can simulta- neously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle. instruction cache the processors contain an on -chip instruction cache that enables three-bus operation for fe tching an instruction and four data values. the cache is selectiveonly the instructions whose fetches conflict with pm bus data accesses are cached. this cache allows full speed executio n of core, looped operations such as digital filter multiply -accumulates, and fft butterfly processing. data address generators with zero-overhead hardware circular buffer support the two data address generators (dags) are used for indirect addressing and implementing circular data buffers in hardware. circular buffers allow efficient programming of delay lines and adsp-21469 rev. 0 | page 5 of 72 | june 2010 other data structures required in digital signal processing, and are commonly used in digital filters and fourier transforms. the two dags of the processors contain sufficient registers to allow the creation of up to 32 ci rcular buffers (16 primary regis- ter sets, 16 secondary). the dags automatically handle address pointer wraparound, reduce overhead, increase performance, and simplify implementation. circular buffers can start and end at any memory location. flexible instruction set the 48-bit instruction word acco mmodates a variety of parallel operations for concise programming. for example, the adsp-21469 can conditionally exec ute a multiply, an add, and a subtract in both processing el ements while branching and fetch- ing up to four 32-bit values from memoryall in a single instruction. variable instruction set architecture (visa) in addition to supporting the st andard 48-bit instructions from previous sharc processors , the adsp-21469 supports new instructions of 16 and 32 bits. this feature, called variable instruction set architecture (visa), drops redundant/unused bits within the 48-bit instruction to create more efficient and compact code. the program sequencer supports fetching these 16-bit and 32-bit instructions from both internal and external ddr2 memory. source modules need to be built using the visa option in order to allow co de generation tools to create these more efficient opcodes. on-chip memory the processors contain 5 mbits of internal ram. each block can be configured for different combinations of code and data storage (see table 4 ). each memory block supports single-cycle, independent accesses by the core processor and i/o processor. the adsp-21469 memory architectu re, in combinat ion with its separate on-chip buses, allows tw o data transfers from the core and one from the i/o processor in a single cycle. the processors sram can be configured as a maximum of 160k words of 32-bit data, 320k words of 16-bit data, 106.7k words of 48-bit instructions (or 40- bit data), or combinations of different word sizes up to 5 mb its. all of the memory can be accessed as 16-bit, 32-bit, 48- bit, or 64-bit words. a 16-bit figure 2. sharc co re block diagram s simd core cache interrupt 5 stage program sequencer pm address 32 dm address 32 dm data 64 pm data 64 dag1 16x32 mrf 80-bit alu multiplier shifter rf rx/fx pex 16x40-bit jtag dmd/pmd 64 astatx stykx astaty styky timer rf sx/sfx pey 16x40-bit mrb 80-bit msb 80-bit msf 80-bit flag system i/f ustat 4x32-bit px 64-bit dag2 16x32 alu multiplier shifter data swap pm address 24 pm data 48 rev. 0 | page 6 of 72 | june 2010 adsp-21469 floating-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. conver- sion between the 32-bit floating-point and 16-bit floating-point formats is performed in a sing le instruction. while each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the dm bus for transfers, and the ot her block stores instructions and data using the pm bus for transfers. using the dm bus and pm buses, with one bus dedicated to a memory block, assures single-c ycle execution with two data transfers. in this case, the inst ruction must be available in the cache. the memory map in table 3 displays the internal memory address space of the adsp-21469 processor. the 48-bit space section describes what this address range looks like to an instruction that re trieves 48-bit memory. the 32-bit section describes what this ad dress range looks like to an instruction that retrieves 32-bit memory. on-chip memory bandwidth the internal memory architecture allows programs to have four accesses at the same time to an y of the four blocks (assuming there are no block conflicts). th e total bandwidth is realized using the dmd and pmd buses (2 64-bits, cclk speed) and the iod0/1 buses (2 32-bit, pclk speed). non-secured rom for non-secured rom, booting modes are selected using the bootcfg pins as shown in table 8 on page 10 . in this mode, emulation is always enabled, and the ivt is placed on the inter- nal ram except for the ca se where bootcfgx = 011. rom based security the adsp-21469 has a rom securi ty feature that provides hardware support for securing user software code by preventing unauthorized reading from the internal code when enabled. when using this feature, the pr ocessor does not boot-load any external code, executing exclusively from internal rom. addi- tionally, the processor is not fr eely accessible via the jtag port. instead, a unique 64-bit key, wh ich must be scanned in through the jtag or test access port will be assigned to each customer. the device ignores a wrong key. emulation features are avail- able after the correct key is scanned. digital transmission content protection the dtcp specification defines a cryptographic protocol for protecting audio entertainment content from illegal copying, intercepting, and tampering as it traverses high performance digital buses, such as the ieee 1394 standard. only legitimate entertainment content delivered to a source device via another approved copy protection syst em (such as the dvd content scrambling system) is protected by this copy prot ection system. table 3. adsp-21469 internal memory space iop registers 0x0000 0000C0x0003 ffff long word (64 bits) extended precision normal or instruction word (48 bits) normal word (32 bits) short word (16 bits) block 0 ram 0x0004 9000C0x0004 efff block 0 ram 0x0008 c000-0x0009 3fff block 0 ram 0x0009 2000-0x0009 dfff block 0 ram 0x0012 4000C0x0013 bfff reserved 0x0004 f000C0x0005 8fff reserved 0x0009 4000C0x0009 5554 reserved 0x0009 e000C0x000b 1fff reserved 0x0013 c000C0x0016 3fff block 1 ram 0x0005 9000C0x0005 efff block 1 ram 0x000a c000-0x000b 3fff block 1 ram 0x000b 2000-0x000b dfff block 1 ram 0x0016 4000-0x0017 bfff reserved 0x0005 f000C0x0005 ffff reserved 0x000b 4000C0x000b 5554 reserved 0x000b e000C0x000b ffff reserved 0x0017 c000C0x0017 ffff block 2 ram 0x0006 0000C0x0006 3fff block 2 ram 0x000c 0000C0x000c 5554 block 2 ram 0x000c 0000-0x000c 7fff block 2 ram 0x0018 0000C0x0018 ffff reserved 0x0006 4000C0x0006 ffff reserved 0x000c 5555C0x000d 5554 reserved 0x000c 8000C0x000d ffff reserved 0x0019 0000C0x001b ffff block 3 ram 0x0007 0000C0x0007 3fff block 3 ram 0x000e 0000C0x000e 5554 block 3 ram 0x000e 0000C0x000e 7fff block 3 ram 0x001c 0000C0x001c ffff reserved 0x0007 4000C0x0007 ffff reserved 0x000e 5555C0x000f 5554 reserved 0x000e 8000C0x000f ffff reserved 0x001d 0000C0x001f ffff adsp-21469 rev. 0 | page 7 of 72 | june 2010 family peripheral architecture the adsp-21469 family contains a rich set of peripherals that support a wide variety of applications including high quality audio, medical imaging, communications, military, test equip- ment, 3d graphics, speech recogn ition, motor control, imaging, and other applications. external port the external port interface supports access to the external mem- ory through core and dma acce sses. the external memory address space is divided into four banks. any bank can be pro- grammed as either asynchronous or synchronous memory. the external ports are comprise d of the following modules. ? an asynchronous memory in terface which communicates with sram, flash, and other devices that meet the stan- dard asynchronous sram access protocol. the ami supports 2m words of external memory in bank 0 and 4m words of external memory in bank 1, bank 2, and bank 3. ? a ddr2 dram controller. external memory devices up to 2 gbits in size can be supported. ? arbitration logic to coordi nate core and dma transfers between internal and external memory over the external port. external memory the external port on the proc essor provides a high perfor- mance, glueless interface to a wide variety of industry-standard memory devices. the external port may be used to interface to synchronous and/or asynchronous memory devices through the use of its separate internal ddr2 memory controller. the 16-bit ddr2 dram controller connects to industry-standard syn- chronous dram devices, while the second 8-bit asynchronous memory controller is intended to interface to a variety of mem- ory devices. four memory select pins enable up to four separate devices to coexist, supporting any desired combination of syn- chronous and asynchronous device types. non-ddr2 dram external memory addres s space is shown in table 4 . simd access to external memory the ddr2 controller on the adsp-21469 processor supports simd access on the 64-bit epd (e xternal port data bus) which allows to access the complementar y registers on the pey unit in the normal word space (nw). th is improves performance since there is no need to explicitly lo ad the complimentary registers as in sisd mode. visa and isa access to external memory the ddr2 controller on the adsp-21469 processor supports visa code operation which redu ces the memory load since the visa instructions are compressed. moreover, bus fetching is reduced because, in the best case , one 48-bit fetch contains three valid instructions. code execut ion from the traditional isa operation is also supported. note that code execution is only supported from bank 0 regardless of visa/isa. table 5 shows the address ranges for instruction fetch in each mode. ddr2 support the adsp-21469 supports a 16-bit ddr2 interface operating at a maximum frequency of half the core clock. execution from external memory is supported. external memory devices up to 2 gbits in size can be supported. ddr2 dram controller the ddr2 dram controller provides a 16-bit interface to up to four separate banks of industry -standard ddr2 dram devices. fully compliant with the ddr2 dram standard, each bank can have its own memory select line (ddr2_cs3 C ddr2_cs0), and can be configured to contain between 32m bytes and 256m bytes of memory. ddr2 dram external memory address space is shown in table 6 . a set of programmable timing parameters is available to config- ure the ddr2 dram banks to support memory devices. note that the external memory bank addresse s shown are for normal-word (32-bit) accesses. if 48-bit instructions, as well as 32-bit data, are both placed in the same external memory bank, care must be taken while mapping them to avoid overlap. asynchronous memory controller the asynchronous memory controller provides a configurable interface for up to four sepa rate banks of memory or i/o devices. each bank can be independently programmed with dif- ferent timing parameters, enabling connection to a wide variety table 4. external memory for non-ddr2 dram addresses bank size in words address range bank 0 2m 0x0020 0000 C 0x003f ffff bank 1 4m 0x0400 0000 C 0x043f ffff bank 2 4m 0x0800 0000 C 0x083f ffff bank 3 4m 0x0c00 0000 C 0x0c3f ffff table 5. external bank 0 instruction fetch access type size in words address range isa (nw) 4m 0x0020 0000 - 0x005f ffff visa (sw) 10m 0x0060 0000 C 0x00ff ffff table 6. external memory for ddr2 dram addresses bank size in words address range bank 0 62m 0x0020 0000 C 0x03ff ffff bank 1 64m 0x0400 0000 C 0x07ff ffff bank 2 64m 0x0800 0000 C 0x0bff ffff bank 3 64m 0x0c00 0000 C 0x0fff ffff rev. 0 | page 8 of 72 | june 2010 adsp-21469 of memory devices including sr am, flash, and eprom, as well as i/o devices that interface with standard memory control lines. bank 0 occupies a 2m word window and banks 1, 2, and 3 occupy a 4m word window in th e processors address space but, if not fully populated, these windows are not made contiguous by the memory controller logic. external port throughput the throughput for the external port, based on a 400 mhz clock, is 66m bytes/s for the ami and 800m bytes/s for ddr2. link ports two 8-bit wide link ports can connect to the link ports of other dsps or peripherals. link port s are bidirectional ports having eight data lines, an acknowledge line, and a clock line. link ports can operate at a maxi mum frequency of 166 mhz. medialb the adsp-21469 automo tive model has a ml b interface which allows the processor to function as a media local bus device. it includes support for both 3-pi n and 5-pin media local bus pro- tocols. it supports speeds up to 1024 fs (49.25 mbits/sec, fs = 48.1 khz) and up to 31 logical channels, with up to 124 bytes of data per media local bus frame. the mlb interface supports most25 and most50 data rates. the isochronous mode of transfer is not supported. pulse-width modulation the pwm module is a flexible , programmable, pwm waveform generator that can be programme d to generate the required switching patterns for various a pplications related to motor and engine control or audio power control. the pwm generator can generate either center-aligned or edge-aligned pwm wave- forms. in addition, it can generate complementary signals on two outputs in paired mode or independent signals in non- paired mode (applicable to a single group of four pwm waveforms). the pwm generator is capable of operating in two distinct modes while generating center-aligned pwm wave- forms: single update mode or double update mode. the entire pwm module has four groups of four pwm outputs each. therefore, this module generates 16 pwm outputs in total. each pwm group produces two pairs of pwm signals on the four pwm outputs. digital applications interface (dai) the digital applications interface (dai) provides the ability to connect various peripherals to any of the dai pins (dai_p20C1). programs make these connections using the signal routing unit (sru), shown in figure 1 on page 1 . the sru is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the dai to be intercon- nected under software control. th is allows easy use of the dai associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with noncon- figurable signal paths. the dai includes the peripheral s described in the following sections. serial ports the adsp-21469 features eight sy nchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as analog devices ad183x family of audio codecs , adcs, and dacs. the serial ports are made up of two data lines, a clock, and frame sync. the data lines can be programmed to either transmit or receive and each data line has a dedicated dma channel. serial ports can support up to 16 transmit or 16 receive dma channels of audio data when all eight sports are enabled, or four full duplex tdm stream s of 128 channe ls per frame. the serial ports operate at a maximum data rate of f pclk /4. serial port data can be automatically transferred to and from on-chip memory/external memory via dedicated dma chan- nels. each of the serial ports can work in conjunction with another serial port to prov ide tdm support. one sport pro- vides two transmit signals whil e the other sport provides the two receive signals. the fram e sync and clock are shared. serial ports operate in five modes: ? standard dsp serial mode ?multichannel (tdm) mode ?i 2 s mode ?packed i 2 s mode ? left-justified mode s/pdif-compatible digital audio receiver/transmitter the s/pdif receiver/transmitter has no separate dma chan- nels. it receives audio data in serial format and converts it into a biphase encoded signal. the serial data input to the receiver/ transmitter can be formatted as left justified, i 2 s or right justi- fied with word widths of 16, 18, 20, or 24 bits. the serial data, clock, and fram e sync inputs to the s/pdif receiver/transmitter are routed th rough the signal routing unit (sru). they can come from a va riety of sources, such as the sports, external pins, and th e precision clock generators (pcgs), and are controlled by the sru control registers. asynchronous sample rate converter the asynchronous sample rate co nverter (asrc) contains four asrc blocks, is the same core as that used in the ad1896 192 khz stereo asynchronous sample rate converter, and provides up to 128 db snr. the asrc bloc k is used to perform synchro- nous or asynchronous samp le rate conversion across independent stereo channels, wi thout using internal processor resources. the four src blocks ca n also be configured to oper- ate together to convert multicha nnel audio data without phase mismatches. finally, the asrc can be used to clean up audio data from jittery clock sources such as the s/pdif receiver. adsp-21469 rev. 0 | page 9 of 72 | june 2010 input data port the idp provides up to eight se rial input channelseach with its own clock, frame sync, and data inputs. the eight channels are automatically multiplexed into a single 32-bit by eight-deep fifo. data is always formatted as a 64-bit frame and divided into two 32-bit words. the serial protocol is designed to receive audio channels in i 2 s, left-justified sample pair, or right-justified mode. one frame sync cycle indica tes one 64-bit left/right pair, but data is sent to the fifo as 32-bit words (that is, one-half of a frame at a time). the proce ssor supports 24- and 32-bit i 2 s, 24- and 32-bit left-justified, and 24-, 20-, 18- and 16-bit right- justified formats. precision clock generators the precision clock generators (pcg) consist of four unitsa, b, c, and d, each of which genera tes a pair of signals (clock and frame sync) derived from a clock input signal. the units are identical in functionality and operate independently of each other. the two signals generated by each unit are normally used as a serial bit clock/frame sync pair. digital peripheral interface (dpi) the digital peripheral interfac e provides connections to two serial peripheral interface (spi ) ports, one univ ersal asynchro- nous receiver-transmitter (uart) , 12 flags, a 2-wire interface (twi), and two general-purpose timers. the dpi includes the peripherals described in the following sections. serial peripheral interface the adsp-21469 sharc processors contain two serial periph- eral interface ports (spi). the spi is an industry-standard synchronous serial li nk, enabling the spi-compatible port to communicate with other spi comp atible devices. the spi con- sists of two data pins, one device select pin, and one clock pin. it is a full-duplex synchronous seri al interface, supporting both master and slave modes. the sp i port can operate in a multi- master environment by interfacing with up to four other spi-compatible devices, either acti ng as a master or slave device. the spi-compatible peripheral implementation also features programmable baud rate, clock phase, and polarities. the spi- compatible port uses open-drain drivers to support a multimas- ter configuration and to avoid data contention. uart port the processors provide a full-duplex universal asynchronous receiver/transmitter (uart) port , which is fully compatible with pc-standard uarts. the uart port provides a simpli- fied uart interface to other pe ripherals or hosts, supporting full-duplex, dma-supported, asynch ronous transfers of serial data. the uart also has mult iprocessor communication capa- bility using 9-bit address detection. this allows it to be used in multidrop networks through the rs-485 data interface standard. the uart port also in cludes support for 5 to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. the uart port supports two modes of operation: ? pio (programmed i/o) C the processor sends or receives data by writing or reading i/o-mapped uart registers. the data is double-buffered on both transmit and receive. ? dma (direct memory access) C the dma controller trans- fers both transmit and receive data. this reduces the number and frequency of interrupts required to transfer data to and from memory. timers the adsp-21469 has a total of thre e timers: a core timer that can generate periodic software interrupts and two general- purpose timers that can generate periodic interrupts and be independently set to operat e in one of three modes: ?pulse waveform generation mode ?pulse width co unt/capture mode ? external event watchdog mode the core timer can be configured to use flag3 as a timer expired signal, and each genera l-purpose timer has one bidirec- tional pin and four registers that implement its mode of operation. a single control and status register enables or dis- ables both general-purpose timers independently. 2-wire interface port (twi) the twi is a bidirectional, 2-wire serial bus used to move 8-bit data while maintaining compliance with the i 2 c bus protocol. the twi master incorporates the following features: ? 7-bit addressing ? simultaneous master and slave operation on multiple device systems with suppor t for multi master data arbitration ? digital filtering and timed event processing ? 100 kbps and 400 kbps data rates ? low interrupt rate i/o processor features automotive versions of the adsp-21469 i/o processor provide 67 channels of dma, while stan dard versions provide 36 chan- nels of dma, as well as an extensive set of peripherals that are described in the following sections. dma controller the processors on-chip dma cont roller allows data transfers without processor intervention . the dma controller operates independently and invisibly to the processor core, allowing dma operations to occur while the core is simultaneously exe- cuting its program instructio ns. dma transfers can occur between the adsp-21469s internal memory and its serial ports, the spi-compatible (serial periph eral interface) ports, the idp (input data port), the parallel da ta acquisition port (pdap), or the uart. up to 67 channels of dma are available on the adsp-21469 processors as shown in table 7 . programs can be downloaded to the adsp-21469 using dma transfers. other dma features include interrupt generation upon completion of dma trans- fers, and dma chaining for automatic linked dma transfers. rev. 0 | page 10 of 72 | june 2010 adsp-21469 delay line dma the adsp-21469 processor provides delay line dma function- ality. this allows processor reads and writes to external delay line buffers (and hence to external memory) with limited core interaction. scatter/gather dma the adsp-21469 processor provides scatter/gather dma func- tionality. this allows processo r dma reads/writes to/from non- contiguous memory blocks. iir accelerator the iir (infinite impulse response) accelerator consists of a 1440 word coefficient memory fo r storage of biquad coeffi- cients, a data memory for storin g the intermediate data, and one mac unit. a controller manages th e accelerator. the iir accel- erator runs at the peripheral clock frequency. fft accelerator fft accelerator implements radix-2 complex/real input, com- plex output fft with no core intervention. the fft accelerator runs at the peripheral clock frequency. fir accelerator the fir (finite impulse response) accelerator consists of a 1024 word coefficient memory, a 1024 word deep delay line for the data, and four mac units. a controller manages the accelerator. the fir accelerator runs at the peripheral clock frequency. system design the following sections provide an introduction to system design options and power supply issues. program booting the internal memory of th e adsp-21469 boots at system power-up from an 8-bit eprom via the external port, link port, an spi master, or an spi slave. booting is determined by the boot configuration (bootcfg2C0) pins in table 8 . the running reset feature allows a user to perform a reset of the processor core and peripherals, without resetting the pll and ddr2 dram controller or performing a boot. the func- tionality of the resetout pin also acts as the input for initiating a running reset. for more information, see the adsp-214xx sharc processor hardware reference . power supplies the processors have separa te power supply connections for the internal (v dd_int ), external (v dd_ext ), and analog (v dd_a ) power supplies. the internal and analog supplies must meet the v dd_int specifications. the external supply must meet the v dd_ext specification. all external supply pins must be con- nected to the sa me power supply. note that the analog supply pin (v dd_a ) powers the processors internal clock generator pll. to produce a stable clock, it is rec- ommended that pcb designs use an external filter circuit for the v dd_a pin. place the filter components as close as possible to the v dd_a /agnd pins. for an example circuit, see figure 3 . (a recommended ferrite chip is the murata blm18ag102sn1d). to reduce noise coupling, the pc b should use a parallel pair of power and ground planes for v dd_int and gnd. use wide traces to connect the bypass ca pacitors to the analog power (v dd_a ) and ground (agnd) pins. note that the v dd_a and agnd pins specified in figure 3 are inputs to the processor and not the analog ground plane on the boardthe agnd pin should connect directly to digi tal ground (gnd) at the chip. table 7. dma channels peripheral dma channels sports 16 idp/pdap 8 spi 2 uart 2 external port 2 link port 2 accelerators 2 memory-to-memory 2 mlb 1 1 automotive models only. 31 table 8. boot mode selection bootcfg2C0 booting mode 000 spi slave boot 001 spi master boot 010 ami boot (for 8-bit flash boot) 011 no boot occurs, processor executes from internal rom after reset 100 link port 0 boot 101 reserved figure 3. analog power (v dd_a ) filter circuit hi z ferrite bead chip locate all components close to vdd_a and agnd pins vdd_a 100nf 10nf 1nf adsp-2146x v dd_int agnd adsp-21469 rev. 0 | page 11 of 72 | june 2010 target board jtag emulator connector analog devices dsp tools product line of jtag emulators uses the ieee 1149.1 jtag test acce ss port of the adsp-21469 pro- cessors to monitor and control the target board processor during emulation. analog devices dsp tools product line of jtag emulators provides emulat ion at full processor speed, allowing inspection and modifica tion of memory, registers, and processor stacks. the processor' s jtag interface ensures that the emulator will not affect target system loading or timing. for complete information on analog devices sharc dsp tools product line of jtag emulator operation, see the appro- priate emulator hardware user's guide. development tools the adsp-21469 processor is supported with a complete set of crosscore ? software and hardware development tools, including analog devices emulators and visualdsp++ ? devel- opment environment. the same emulator hardware that supports other sharc processors also fully emulates the adsp-21469 processors. ez-kit lite evaluation board for evaluation of the processors, use the ez-kit lite ? board being developed by analog devices. the board comes with on- chip emulation capabilities and is equipped to enable software development. multiple daug hter cards are available. designing an emulator-compatible dsp board (target) the analog devices family of emulators are tools that every dsp developer needs to test an d debug hardware and software systems. analog devices has supplied an ieee 1149.1 jtag test access port (tap) on each jtag dsp. nonintrusive in- circuit emulation is assured by the use of the processors jtag interfacethe emulator does not af fect target system loading or timing. the emulator uses the tap to access the internal fea- tures of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. the processor must be halted to send data and com- mands, but once an operation has been completed by the emulator, the dsp system is set running at full speed with no impact on system timing. to use these emulators, the targ et board must include a header that connects the dsps jtag port to the emulator. for details on target board desi gn issues including mechanical layout, single processor connections, signal buffering, signal ter- mination, and emulator pod logic, see the ee-68: analog devices jtag emulation technical reference on the analog devices website ( www.analog.com )use site search on ee-68. this document is updated regularly to keep pace with improvements to emulator support. evaluation kit analog devices offers a range of ez-kit lite ? evaluation plat- forms to use as a cost effective method to learn more about developing or prototyping appl ications with analog devices processors, platforms, and softwa re tools. each ez-kit lite includes an evaluation board along with an evaluation suite of the visualdsp++ ? development and debugging environment with the c/c++ compiler, assemble r, and linker. also included are sample applicat ion programs, power supply, and a usb cable. all evaluation versions of the software tools are limited for use only with the ez-kit lite product. the usb controller on the ez-kit lite board connects the board to the usb port of the users pc, enabling the visualdsp++ evaluation suite to emulate the on-board proces- sor in-circuit. this permits the customer to download, execute, and debug programs for the ez-kit lite system. it also allows in-circuit programming of the on -board flash device to store user-specific boot code, enabling the board to run as a stand- alone unit without being connected to the pc. with a full version of visualdsp ++ installed (sold separately), engineers can develop software fo r the ez-kit lite or any cus- tom defined system. connecting one of analog devices jtag emulators to the ez-kit lite board enables high speed, non- intrusive emulation. additional information this data sheet provides a ge neral overview of the adsp-21469 architecture and functionality. for detailed information on the adsp-21469 family core architectu re and instruction set, refer to the sharc processor programming reference . related signal chains a signal chain is a series of signal-c onditioning electronic com- ponents that receive input (data acquired from sampling either real-time phenomena or from stor ed data) in tandem, with the output of one portion of the ch ain supplying input to the next. signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. for more information about this term and related topics, see the "signal chain" entry in wikipedia or the glossary of ee terms on the analog devices website. analog devices eases signal proc essing system development by providing signal processing comp onents that are designed to work together well. a tool fo r viewing relationships between specific applications and related components is available on the www.analog.com website. the application signal chains page in the circuits from the lab tm site ( http://www.analog. com/signalchains ) provides: ? graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications ? drill down links for components in each chain to selection guides and application information ? reference designs applying be st practice design techniques rev. 0 | page 12 of 72 | june 2010 adsp-21469 pin function descriptions unused ddr2 pins when the ddr2 controller is not used: ? leave the ddr2 signal pins floating. ? internally, three-state the ddr2 i/o signals. this can be done by setting the dis_ddrctl bit of ddr2ctl0 register. ? power down the receive path by setting the pwd bits of the ddr2padctlx register. ?connect the v dd_ddr2 pins to the v dd_int supply. ?leave v ref floating/unconnected. table 9. pin descriptions name type state during/ after reset description ami_addr 23C0 i/o/t (ipu) high-z/driven low (boot) external address. the processor outputs addresses for external memory and peripherals on these pins. the data pins can be multiplexed to support the pdap (i) and pwm (o). after reset, all ami_addr 23C0 pins are in external memory interface mode and flag(0C3) pins are in flags mode (default). when configured in the idp_pdap_ctl register, idp channel 0 scans the ami_addr 23C0 pins for parallel input data. unused ami pins can be left unconnected. ami_data 7C0 i/o/t (ipu) high-z external data. the data pins can be multiplexed to support the external memory interface data (i/o), the pdap (i), flags (i/o) and pwm (o). after reset, all ami_data pins are in emif mode and flag(0-3) pins are in flags mode (default). unused ami pins can be left unconnected. ami_ack i (ipu) memory acknowledge (ami_ack). external devices can deassert ami_ack (low) to add wait states to an external memory access. ami_ack is used by i/o devices, memory controllers, or other peripherals to hold off completion of an external memory access. unused ami pins can be left unconnected. ami_ms 0C1 o/t (ipu) high-z memory select lines 0C1. these lines are asserted (low) as chip selects for the corre- sponding banks of external memory on the ami interface. the ms 1-0 lines are decoded memory address lines that change at the same time as the other address lines. when no external memory access is occurring the ms 1-0 lines are inactive; they are active however when a conditional memory access instruction is executed, whether or not the condition is true. unused ami pins can be left unconnected. the ms1 pin can be used in eport/flash boot mode. for more information, see the adsp-214xx sharc processor hardware reference. ami_rd o/t (ipu) high-z ami port read enable. ami_rd is asserted whenever the processor reads a word from external memory. ami_wr o/t (ipu) high-z external port write enable. ami_wr is asserted when the processor writes a word to external memory. flag[0]/irq0 i/o (ipu) flag[0] input flag0/interrupt request0. flag[1]/irq1 i/o (ipu) flag[1] input flag1/interrupt request1. flag[2]/irq2 / ami_ms2 i/o (ipu) flag[2] input flag2/interrupt request2/async memory select2. flag[3]/tmrexp/ ami_ms3 i/o (ipu) flag[3] input flag3/timer expired/async memory select3. the following symbols appear in the type column of table 9 : a = asynchronous, i = input, o = output, s = synchronous, a/d = active drive, o/d = open-drain, and t = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. the internal pull-up (ipu) and internal pull-down (ipd) resistors ar e designed to hold the internal path from the pins at the e xpected logic levels. to pull-up or pull-down the external pads to the expected logi c levels, use external resistors. internal pull-up/pull-down resi stors cannot be enabled/disabled and the value of these resistors cannot be pr ogrammed. the range of an ipu resistor can be between 26 k ? C63 k ? . the range of an ipd resistor can be between 31 k ? C85 k ? . in this table, the ddr2 pins are sstl18 co mpliant. all other pins are lvttl compliant. adsp-21469 rev. 0 | page 13 of 72 | june 2010 ddr2_addr 15C0 o/t high-z/driven low ddr2 address. ddr2 address pins. ddr2_ba 2-0 o/t high-z/driven low ddr2 bank address input. defines which internal bank an activate, read, write, or precharge command is being applied to. ba 2C0 define which mode registers, including mr, emr, emr(2), and emr(3) are loaded during the load mode register command. ddr2_cas o/t high-z/driven high ddr2 column address strobe. connect to ddr2_cas pin; in conjunction with other ddr2 command pins, defines the operation for the ddr2 to perform. ddr2_cke o/t high-z/driven low ddr2 clock enable output to ddr2. active high signal. connect to ddr2 cke signal. ddr2_cs 3-0 o/t high-z/driven high ddr2 chip select. all commands are masked when ddr2_cs 3-0 is driven high. ddr2_cs 3-0 are decoded memory addr ess lines. each ddr2_cs 3-0 line selects the corresponding external bank. ddr2_data 15-0 i/o/t high-z ddr2 data in/out. connect to corresponding ddr2_data pins. ddr2_dm 1-0 o/t high-z/driven high ddr2 input data mask. mask for the ddr2 write data if driven high. sampled on both edges of ddr2_dqs at ddr2 side. dm0 corresponds to ddr2_data 7C0 and dm1 corresponds to ddr2_data15C8. ddr2_dqs 1-0 ddr2_dqs 1-0 i/o/t (differential) high-z data strobe. output with write data. input with read data. dqs0 corresponds to ddr2_data 7C0 and dqs1 corresponds to ddr2_data 15C8. based on software control via the ddr2ctl3 register, this pin can be single-ended or differential. ddr2_ras o/t high-z/driven high ddr2 row address strobe. connect to ddr2_ras pin; in conjunction with other ddr2 command pins, defines the opera tion for the ddr2 to perform. ddr2_we o/t high-z/driven high ddr2 write enable. connect to ddr2_we pin; in conjunction with other ddr2 command pins, defines the operation for the ddr2 to perform. ddr2_clk0, ddr2_clk0 , ddr2_clk1, ddr2_clk1 o/t (differential) high-z/driven low ddr2 memory clocks. two differential outputs available via software control (ddr2ctl0 register). free running, minimum frequency not guaranteed during reset. ddr2_odt o/t high-z/driven low ddr2 on die termination. odt pin when driven high (along with other require- ments) enables the ddr2 termination resistances. odt is enabled/disabled regardless of read or write commands. table 9. pin descriptions (continued) name type state during/ after reset description the following symbols appear in the type column of table 9 : a = asynchronous, i = input, o = output, s = synchronous, a/d = active drive, o/d = open-drain, and t = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. the internal pull-up (ipu) and internal pull-down (ipd) resistors ar e designed to hold the internal path from the pins at the e xpected logic levels. to pull-up or pull-down the external pads to the expected logi c levels, use external resistors. internal pull-up/pull-down resi stors cannot be enabled/disabled and the value of these resistors cannot be pr ogrammed. the range of an ipu resistor can be between 26 k ? C63 k ? . the range of an ipd resistor can be between 31 k ? C85 k ? . in this table, the ddr2 pins are sstl18 co mpliant. all other pins are lvttl compliant. rev. 0 | page 14 of 72 | june 2010 adsp-21469 dai _p 20C1 i/o/t (ipu) high-z digital applications interface . these pins provide the physical interface to the dai sru. the dai sru configuration registers define the combination of on-chip audio- centric peripheral inputs or outputs conn ected to the pin and to the pins output enable. the configuration registers of these peripherals then determine the exact behavior of the pin. any input or output signal present in the dai sru may be routed to any of these pins. the dai sru provides the connection from the serial ports, the s/pdif module, input data ports (2), and th e precision clock generators (4), to the dai_p20C1 pins. dpi _p 14C1 i/o/t (ipu) high-z digital peripheral interface. these pins provide the physical interface to the dpi sru. the dpi sru configuration registers define the combination of on-chip peripheral inputs or outputs connected to the pin and to the pins output enable. the configuration registers of these peripherals then determines the exact behavior of the pin. any input or output signal present in the dpi sru may be routed to any of these pins. the dpi sru provides the connection from the timers (2), spis (2), uart (1), flags (12), and general-purpos e i/o (9) to the dpi_p14C1 pins. ldat0 7C0 ldat1 7C0 i/o/t (ipd) high-z link port data (link ports 0C1) . when configured as a transmitter, the port drives both the data lines. lclk0 lclk1 i/o/t (ipd) high-z link port clock (link ports 0C1). allows asynchronous data transfers. when configured as a transmitter, the port drives lclkx lines. an external 25 k ? pull-down resistor is required for the proper operation of this pin. lack0 lack1 i/o/t (ipd) high-z link port acknowledge (link port 0C1). provides handshaking. when the link ports are configured as a receiver, the port drives the lackx line. an external 25 k ? pull- down resistor is required for the proper operation of this pin. thd_p i thermal diode anode . if unused, can be left floating. thd_m o thermal diode cathode . if unused, can be left floating. mlbclk 1 i (ipd) media local bus clock. this clock is generated by the mlb controller that is synchro- nized to the most network and provides the timing for the entire mlb interface. 49.152 mhz at fs = 48 khz. if unused, can be left floating. mlbdat 1 i/o/t (ipd) in 3 pin mode. i/t (ipd) in 5 pin mode. high-z media local bus data. the mlbdat line is driven by the transmitting mlb device and is received by all other mlb device s including the mlb controller. the mlbdat line carries the actual data. in 5-pin mlb mode, this pin is an input only. if unused, can be left floating. mlbsig 1 i/o/t (ipd) in 3 pin mode. i/t(ipd) in 5 pin mode. high-z media local bus signal. this is a multiplexed signal which carries the channel/ address generated by the mlb controller, as well as the command and rxstatus bytes from mlb devices. in 5-pin mode, this pi n is an input only. if unused, can be left floating. mlbdo 1 o/t (ipd) high-z media local bus data output (in 5 pin mode). this pin is used only in 5-pin mlb mode. this serves as the output data pin in 5- pin mode. if unused, can be left floating. mlbso 1 o/t (ipd) high-z media local bus signal output (in 5 pin mode). this pin is used only in 5-pin mlb mode. this serves as the output signal pin in 5-pin mode. if unused, can be left floating. table 9. pin descriptions (continued) name type state during/ after reset description the following symbols appear in the type column of table 9 : a = asynchronous, i = input, o = output, s = synchronous, a/d = active drive, o/d = open-drain, and t = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. the internal pull-up (ipu) and internal pull-down (ipd) resistors ar e designed to hold the internal path from the pins at the e xpected logic levels. to pull-up or pull-down the external pads to the expected logi c levels, use external resistors. internal pull-up/pull-down resi stors cannot be enabled/disabled and the value of these resistors cannot be pr ogrammed. the range of an ipu resistor can be between 26 k ? C63 k ? . the range of an ipd resistor can be between 31 k ? C85 k ? . in this table, the ddr2 pins are sstl18 co mpliant. all other pins are lvttl compliant. adsp-21469 rev. 0 | page 15 of 72 | june 2010 tdi i (ipu) test data input (jtag). provides serial data for the boundary scan logic. tdo o /t high-z test data output (jtag). serial scan output of the boundary scan path. tms i (ipu) test mode select (jtag). used to control the test state machine. tck i test clock (jtag). provides a clock for jtag boundary scan. tck must be asserted (pulsed low) after power-up or held low for proper operation of the device. trst i (ipu) test reset (jtag). resets the test state machine. trst must be asserted (pulsed low) after power-up or held low for proper operation of the processor. emu o/t (ipu) high-z emulation status. m ust be connec ted to the adsp-21469 analog devices dsp tools product line of jtag emulators target board connector only. clk_cfg 1C0 i core to clkin ratio control. these pins set the start up clock frequency. note that the operating frequency can be changed by programming the pll multiplier and divider in the pmctl register at any time after the core comes out of reset. the allowed values are: 00 = 6:1 01 = 32:1 10 = 16:1 11 = reserved clkin i local clock in. used in conjunction with xtal. clkin is the clock input. it configures the processors to use either its internal clock generator or an external clock source. connecting the necessary components to clkin and xtal enables the internal clock generator. connecting the external clock to clkin while leaving xtal unconnected configures the processors to use the external clock source such as an external clock oscillator. clkin may not be halted, changed, or operated below the specified frequency. xtal o crystal oscillator terminal. used in conjunction with clkin to drive an external crystal. reset i processor reset. resets the processor to a known state. upon deassertion, there is a 4096 clkin cycle latency for the pll to lock. after this time, the core begins program execution from the hardware reset vector address. the reset input must be asserted (low) at power-up. resetout / runrstin i/o (ipu) reset out/running reset in. the default setting on this pin is reset out. this pin also has a second function as runrstin which is enabled by setting bit 0 of the runrstctl register. for more information, see the adsp-214xx sharc processor hardware reference . boot_cfg 2C0 i boot configuration select. these pins select the boot mode for the processor. the boot_cfg pins must be valid before reset (hardware and software) is de-asserted. 1 the mlb pins are only available on automotive models of the adsp-21469 processors. these pins are nc (no connect) on the standa rd models. for more information, see csp_bga ball assignmentaut omotive models on page 63 , and csp_bga ball assignmentsta ndard models on page 66 . table 9. pin descriptions (continued) name type state during/ after reset description the following symbols appear in the type column of table 9 : a = asynchronous, i = input, o = output, s = synchronous, a/d = active drive, o/d = open-drain, and t = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. the internal pull-up (ipu) and internal pull-down (ipd) resistors ar e designed to hold the internal path from the pins at the e xpected logic levels. to pull-up or pull-down the external pads to the expected logi c levels, use external resistors. internal pull-up/pull-down resi stors cannot be enabled/disabled and the value of these resistors cannot be pr ogrammed. the range of an ipu resistor can be between 26 k ? C63 k ? . the range of an ipd resistor can be between 31 k ? C85 k ? . in this table, the ddr2 pins are sstl18 co mpliant. all other pins are lvttl compliant. rev. 0 | page 16 of 72 | june 2010 adsp-21469 table 10. pin list, power and ground name type description v dd _ int pinternal power v dd _ ext pexternal power v dd _ a panalog power for pll v dd _ thd pthermal diode power v dd _ ddr 2 1 pddr2 interface power v ref pddr2 input voltage reference gnd g ground agnd g analog ground 1 applies to ddr2 signals. adsp-21469 rev. 0 | page 17 of 72 | june 2010 specifications operating conditions 450 mhz 400 mhz unit parameter 1 1 specifications subject to change without notice. description min nom max min nom max v dd _ int internal (core) supply voltage 1.05 1.1 1.15 1.0 1.05 1.1 v v dd _ ext external (i/o) supply voltage 3.13 3.3 3.47 3.13 3.3 3.47 v v dd _ a 2 2 see figure 3 on page 10 for an example filter circuit. analog power supply voltage 1.05 1.1 1.15 1.0 1.05 1.1 v v dd _ ddr 2 3, 4 3 applies to ddr2 signals. 4 if unused, see unused ddr2 pins on page 12 . ddr2 controller supply voltage 1.7 1.8 1.9 1.7 1.8 1.9 v v dd _ thd thermal diode supply voltage 3.13 3.3 3.47 3.13 3.3 3.47 v v ref ddr2 reference voltage 0.84 0.9 0.96 0.84 0.9 0.96 v v ih 5 5 applies to input and bidir ectional pins: ami_addr23C0, ami _data7C0, flag3C0, dai_px, dpi_px , bootcfgx, clkcfgx, (runrstin ), reset , tck, tms, tdi, trst . high level input voltage @ v dd _ ext = max 2.0 2.0 v v il 5 low level input voltage @ v dd _ ext = min 0.8 0.8 v v ih _ clkin 6 6 applies to input pin clkin. high level input voltage @ v dd _ ext = max 2.0 2.0 v v il _ clkin 6 low level input voltage @ v dd _ ext = min 1.32 1.32 v v il _ ddr 2 (dc) dc low level input voltage v ref C 0.125 v ref C 0.125 v v ih _ ddr 2 (dc) dc high level input voltage v ref + 0.125 v ref + 0.125 v v il _ ddr 2 (ac) ac low level input voltage v ref C 0.25 v ref C 0.25 v v ih _ ddr 2 (ac) ac high level input voltage v ref + 0.25 v ref + 0.25 v t j junction temperature 324-lead csp_bga @ t ambient 0 c to +70 c 0 115 0 110 c t j junction temperature 324-lead csp_bga @ t ambient C40 c to +85 c n/a n/a C40 125 c rev. 0 | page 18 of 72 | june 2010 adsp-21469 electrical characteristics 450 mhz 400 mhz unit parameter 1 description test conditions min max min max v oh 2 high level output voltage @ v dd _ ext = min, i oh = C1.0 ma 3 2.4 2.4 v v ol 2 low level output voltage @ v dd _ ext = min, i ol = 1.0 ma 3 0.4 0.4 v v oh _ ddr 2 high level output voltage for ddr2 @ v dd _ ddr = min, ioh = C13.4 ma 1.4 1.4 v v ol _ ddr 2 low level output voltage for ddr2 @ v dd _ ddr = min, iol = 13.4 ma 0.29 0.29 v i ih 4, 5 high level input current @ v dd _ ext = max, v in = v dd _ ext max 10 10 a i il 4, 6 low level input current @ v dd _ ext = max, v in = 0 v 10 10 a i ilpu 5 low level input current pull-up @ v dd _ ext = max, v in = 0 v 200 200 a i ihpd 6 high level input current pull-down @ v dd _ ext = max, v in = v dd _ ext max 200 200 a i ozh 7, 8 three-state leakage current @ v dd _ ext /v dd _ ddr = max, v in = v dd _ ext /v dd _ ddr max 10 10 a i ozl 7, 9 three-state leakage current @ v dd _ ext /v dd _ ddr = max, v in = 0 v 10 10 a i ozlpu 8 three-state leakage current pull-up @ v dd _ ext = max, v in = 0 v 200 200 a i ozhpd 9 three-state leakage current pull-down @ v dd _ ext = max, v in = v dd _ ext max 200 200 a i dd - intyp 10, 11 supply current (internal) f cclk > 0 mhz table 12 + table 13 asf table 12 + table 13 asf ma i dd _ a 12 supply current (analog) v dd _ a = max 10 10 ma c in 13, 14 input capacitance t case = 25 c55pf 1 specifications subject to change without notice. 2 applies to output and bid irectional pins: ami_addr23-0, ami_data7-0, ami_rd , ami_wr , flag3C0, dai_px, dpi_px, emu , tdo. 3 see output drive currents on page 58 for typical drive current capabilities. 4 applies to input pins: bootcfgx, clkcfgx, tck, reset , clkin. 5 applies to input pins with internal pull-ups: trst , tms, tdi. 6 applies to input pins with internal pull-downs: mlbclk 7 applies to three-statab le pins: all ddr2 pins. 8 applies to three-statable pins with pull-ups: dai_px, dpi_px, emu . 9 applies to three-statable pins with pull-downs: mlbdat, mlbsig, mlbdo, mlbso, ldat07-0, ldat17-0 , lclk0, lclk1, lack0, lack1. 10 typical internal current data reflec ts nominal operating conditions. 11 see engineer-to-engineer note estimatin g power dissipation for ad sp-2146x sharc proc essors for further information. 12 characterized but not tested. 13 applies to all signal pins. 14 guaranteed, but not tested. adsp-21469 rev. 0 | page 19 of 72 | june 2010 total power dissipation total power dissipation has two components: 1. internal power consumption 2. external power consumption internal power consumption al so comprises two components: 1. static, due to leakage current. table 12 shows the static cur- rent consumption (i dd-static ) as a function of junction temperature (t j ) and core voltage (v dd_int ). 2. dynamic (i dd-dynamc ), due to transistor switching char- acteristics and activity level of the processor. the activity level is reflected by the activity scaling factor (asf), which represents application code running on the processor core and having various levels of peripheral and external port activity ( table 11 ). dynamic current consumption is calcu- lated by scaling the specific application by the asf and using baseline dynamic current consumption as a reference. external power consumption is due to the switching activity of the external pins. the asf is combined with the cclk frequency and v dd_int dependent data in table 13 to calculate this part. the second part is due to transistor switching in the peripheral clock (pclk) domain, which is included in the i dd_int specification equation. table 11. activity scaling factors (asf) 1 1 see estimating power for sh arc processors (ee-348) for more information on the explanation of the power vect ors specific to the asf table. activity scaling factor (asf) idle 0.38 low 0.58 high 1.23 peak 1.35 peak-typical (50:50) 2 2 ratio of continuous instructi on loop (core) to ddr2 control code reads:writes. 0.87 peak-typical (60:40) 0.94 peak-typical (70:30) 1.00 table 12. i dd-static (ma) t j (c) 1 v dd_int (v) 1 0.95 v 1.0 v 1.05 v 1.10 v 1.15 v C45 72 91 110 140 167 C35 79 99 119 149 181 C25 89 109 131 163 198 C15 101 122 145 182 220 C5 115 140 166 206 249 5 134 162 192 237 284 15 158 189 223 273 326 25 186 222 260 318 377 35 218 259 302 367 434 45 258 305 354 428 503 55 305 359 413 497 582 65 360 421 484 578 675 75 424 496 566 674 781 85 502 580 660 783 904 95 586 683 768 912 1048 105 692 794 896 1054 1212 115 806 921 1036 1220 1394 125 939 1070 1198 1404 1601 1 valid temperature and voltage ranges are model-specific. see operating conditions on page 17 . rev. 0 | page 20 of 72 | june 2010 adsp-21469 absolute maximum ratings stresses greater than those listed in table 14 may cause perma- nent damage to the device. these are stress ratings only; functional operation of the device at these or any other condi- tions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd sensitivity package information the information presented in figure 4 provides details about the package branding for th e adsp-21469 processors. for a complete listing of pr oduct availability, see ordering guide on page 70 . table 13. baseline dynamic current in cclk domain (ma, with asf = 1.0) 1 f cclk (mhz) 2 voltage (v dd_int ) 2 0.95 v 1.0 v 1.05 v 1.10 v 1.15 v 1007882869198 150 115 121 130 136 142 200 150 159 169 177 188 250 186 197 208 219 231 300 222 236 249 261 276 350 259 275 288 304 319 400 293 309 328 344 361 450 n/a n/a 366 385 406 1 the values are not guaranteed as standalone maximum specifications. they must be combin ed with static current per the equations of electrical characteristics on page 18 . 2 valid frequency and voltage ra nges are model-specific. see operating conditions on page 17 . table 14. absolute maximum ratings parameter rating internal (core) supply voltage (v dd _ int ) C0.3 v to +1.32 v analog (pll) supply voltage (v dd _ a ) C0.3 v to +1.15 v external (i/o) supply voltage (v dd _ ext ) C0.3 v to +3.6 v thermal diode supply voltage (v dd _ thd ) C0.3 v to +3.6 v ddr2 controller supply voltage (v dd _ ddr 2) C0.3 v to +1.9 v ddr2 input voltage C0.3 v to +1.9 v input voltage C0.3 v to +3.6 v output voltage swing C0.3 v to v dd_ext +0.5 v storage temperature range C65 ? c to +150 ? c junction temperature while biased 125 ? c esd (electrostatic discharge) sensitive device. charged devi c es and c ir c uit boards c an dis c harge without dete c tion. a l though this produ c t features patented or proprietary prote c tion c ir c uitry, damage may o cc ur on devi c es subje c ted to high energy esd. t herefore, proper esd pre c autions shou l d be taken to avoid performan c e degradation or l oss of fun c tiona l ity. figure 4. typical package brand table 15. package brand information 1 1 non-automotive only. for branding in formation specific to automotive products, contact analog devices inc. brand key field description t temperature range pp package type z rohs compliant option cc see ordering guide vvvvvv.x assembly lot code n.n silicon revision # rohs compliant designation yyww date code vvvvvv.x n.n tppz-cc s adsp-2146x a yyww country_of_origin adsp-21469 rev. 0 | page 21 of 72 | june 2010 timing specifications use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addition or su btraction would yield meaningful results for an individual device, the va lues given in this data sheet reflect statistical variations and worst cases. consequently, it is not meaningful to add parameters to derive longer times. see figure 45 on page 58 under test conditions for voltage refer- ence levels. in the following sections, switching characteristics specify how the processor changes it s signals. circuitry external to the pro- cessor must be designed for co mpatibility with these signal characteristics. switch ing characteristics de scribe what the pro- cessor will do in a given ci rcumstance. use switching characteristics to ensure that any timing requirement of a device connected to the processor (s uch as memory) is satisfied. in the following sections, timing requirements apply to signals that are controlled by circuitry exte rnal to the processor, such as the data input for a read operat ion. timing requirements guar- antee that the processor operates correctly with other devices. core clock requirements the processors internal clock (a multiple of clkin) provides the clock signal for timing inte rnal memory, processor core, and serial ports. during reset, prog ram the ratio between the proces- sors internal clock frequenc y and external (clkin) clock frequency with the clk_cfg1C0 pins. the processors internal clock sw itches at higher frequencies than the system input clock (clk in). to generate the internal clock, the processor uses an internal phase-locked loop (pll, see figure 5 ). this pll-based clocki ng minimizes the skew between the system clock (clkin ) signal and the processors internal clock. voltage controlled oscillator in application designs, the p ll multiplier value should be selected in such a way that the vco frequency never exceeds f vco specified in table 18 . ? the product of clkin and pllm must never exceed 1/2 of f vco (max) in table 18 if the input divider is not enabled (indiv = 0). ? the product of clkin and pllm must never exceed f vco (max) in table 18 if the input divider is enabled (indiv = 1). the vco frequency is calculated as follows: f vco = 2 pllm f input f cclk = (2 pllm f input ) ( plld ) where: f vco = vco output pllm = multiplier value programm ed in the pmctl register. during reset, the pllm value is derived from the ratio selected using the clk_cfg pins in hardware. plld = divider value 2, 4, 8, or 16 based on the plld value programmed on the pmctl regist er. during reset this value is 2. f input = input frequency to the pll f input = clkin when the input divider is disabled, or f input = clkin ? 2 when the input divider is enabled note the definitions of the clock periods that are a function of clkin and the appropriate ra tio control shown in and table 16 . all of the timing specifications for the adsp-21469 peripherals are define d in relation to t pclk . see the peripheral specific section for each peri pherals timing information. figure 5 shows core to clkin relati onships with external oscil- lator or crystal. the shaded di vider/multiplier blocks denote where clock ratios can be set through hardware or software using the power management control register (pmctl). for more information, see the adsp-214xx sharc processor hard- ware reference . table 16. clock periods timing requirements description t ck clkin clock period t cclk processor core clock period t pclk peripheral clock period = 2 t cclk rev. 0 | page 22 of 72 | june 2010 adsp-21469 figure 5. core clock and system clock relationship to clkin loop filter clkin pclk ddr2_clk ddr2 divider b yp a s s m u x divide by 2 cclk by p a s s m u x pll xtal clkin divider resetout reset buf vco buf plli clk pll divider clk_cfgx/pmctl (2xpllm) pin mux resetout clkout (test only) delay of 4096 clkin cycles corerst cclk pclk clk_cfgx/ pmctl link port clock divider lclk b y p a s s m u x pmctl (pllbp) pmctl (pllbp) pmctl (indiv) pmctl (lclkr) pmctl (ddr2ckr) pmctl (plld) pll multiplier f input f cclk adsp-21469 rev. 0 | page 23 of 72 | june 2010 power-up sequencing the timing requirements for pr ocessor startup are given in table 17 . while no specific power-up sequencing is required between v dd _ ext , v dd _ ddr 2 , and v dd _ int , there are some consider- ations that the system design s should take into account. ? no power supply should be powered up for an extended period of time (> 200 ms) befo re another supply starts to ramp up. ?if v dd _ int power supply comes up after v dd _ ext , any pin, such as resetout and reset , may actually drive momentarily until the v dd _ int rail has powered up. systems sharing these signals on the bo ard must determine if there are any issues that need to be addressed based on this behavior. note that during power-up, when the v dd _ int power supply comes up after v dd _ ext , a leakage current of the order of three- state leakage current pull-up, pull-down may be observed on any pin, even if that pin is an input only (for example the reset pin) until the v dd _ int rail has powered up. table 17. power up sequencing timing requirements (processor startup) parameter min max unit timing requirements t rstvdd reset low before v dd _ int or v dd _ ext or v dd _ ddr 2 on 0 ms t ivdd - evdd v dd _ int on before v dd _ ext C200 +200 ms t evdd _ ddr 2 vdd v dd _ ext on before v dd _ ddr 2 C200 +200 ms t clkvdd 1 clkin valid after v dd _ int or v dd _ ext or v dd _ ddr 2 valid 0 200 ms t clkrst clkin valid before reset deasserted 10 2 ms t pllrst pll control setup before reset deasserted 20 3 ms switching characteristic t corerst core reset deasserted after reset deasserted 4096 t ck + 2 t cclk 4, 5 ms 1 valid v dd _ int assumes that the supply is fully ramped to its nominal value. voltage ramp rates can vary from microseconds to hundreds of mil liseconds depending on the design of the powe r supply subsystem. 2 assumes a stable clkin signal, after meeting worst-case startup timing of crystal oscillators. refer to your crystal oscillator manufacturer's data sheet for startup time. assume a 25 ms maximum oscillator startup time if using the xtal pin an d internal oscillator circuit in conjunction with an external c rystal. 3 based on clkin cycles. 4 applies after the power-up sequence is complete. subsequent resets require a minimum of four clkin cycles for reset to be held low in order to properly initialize and propagate default states at all i/o pins. 5 the 4096 cycle count depends on t srst specification in table 19 . if setup time is not met, one additional clkin cycle may be added to the core reset time, resulting in 4097 cycles maximum. figure 6. power-up sequencing t rstvdd t clkvdd t clkrst t corerst t pllrst v ddext v ddint clkin clk_cfg1C0 reset resetout t ivddevdd rev. 0 | page 24 of 72 | june 2010 adsp-21469 clock input clock signals the adsp-21469 can use an external clock or a crystal. see the clkin pin description in table 9 . programs can configure the processor to use its internal cl ock generator by connecting the necessary components to clkin and xtal. figure 8 shows the component connections used for a crystal operating in funda- mental mode. note that the clock rate is achieved using a 25 mhz crystal and a pll multiplier ratio 16:1 (cclk:clkin achieves a clock speed of 400 mhz). to achieve the full core clock ra te, programs need to configure the multiplier bits in the pmctl register. table 18. clock input parameter 400 mhz 1 1 applies to all 40 0 mhz models. see ordering guide on page 70 . 450 mhz 2 2 applies to all 45 0 mhz models. see ordering guide on page 70 . unit min max min max timing requirements t ck clkin period 15 3 3 applies only for clk_cfg1C0 = 00 and defa ult values for pll control bits in pmctl. 100 13.26 100 ns t ckl clkin width low 7.5 45 6.63 45 ns t ckh clkin width high 7.5 45 6.63 45 ns t ckrf clkin rise/fall (0.4 v to 2.0 v) 3 4 4 guaranteed by simulation but not tested on silicon. 3 4 ns t cclk 5 5 any changes to pll control bits in the pmctl regis ter must meet core clock timing specification t cclk . cclk period 2.5 10 2.22 10 ns f vco 6 6 see figure 5 on page 22 for vco diagram. vco frequency 200 900 200 900 mhz t ckj 7, 8 7 actual input jitter should be combined with ac specifications for acc urate timing analysis. 8 jitter specification is maximum peak-to -peak time interval error (tie) jitter. clkin jitter tolerance C250 +250 C250 +250 ps figure 7. clock input clkin t ck t ckl t ckh t ckj figure 8. recommended circuit for fundamental mode crystal operation c1 22pf y1 r1 1m * xtal clkin c2 22pf 25.000 mhz r2 47 * r2 should be chosen to limit crystal drive power. refer to crystal manufacturers specifications *typical values adsp-2146x adsp-21469 rev. 0 | page 25 of 72 | june 2010 reset running reset the following timing specification applies to resetout /runrstin pin when it is configured as runrstin . table 19. reset parameter min max unit timing requirements t wrst 1 reset pulse width low 4 t ck ns t srst reset setup before clkin low 8 ns 1 applies after the power-up sequence is comp lete. at power-up, the processors internal ph ase-locked loop requires no more than 1 00 m s while reset is low, assuming stable v dd and clkin (not including start-up time of external clock oscillator). figure 9. reset clkin reset t srst t wrst table 20. running reset parameter min max unit timing requirements t wrunrst running reset pulse width low 4 t ck ns t srunrst running reset setup before clkin high 8 ns figure 10. running reset clkin runrstin t wrunrst t srunrst rev. 0 | page 26 of 72 | june 2010 adsp-21469 interrupts the following timing specification applies to the flag0, flag1, and flag2 pins when they are config ured as irq0 , irq1 , and irq2 interrupts as well as the dai_p20C1 and dpi_p14C1 pins when they ar e configured as interrupts. core timer the following timing specification applies to flag3 when it is configured as the core timer (tmrexp). table 21. interrupts parameter min max unit timing requirement t ipw irqx pulse width 2 t pclk + 2 ns figure 11. interrupts interrupt inputs t ipw table 22. core timer parameter min max unit switching characteristic t wctim tmrexp pulse width 4 t pclk C 1 ns figure 12. core timer flag3 (tmrexp) t wctim adsp-21469 rev. 0 | page 27 of 72 | june 2010 timer pwm_out cycle timing the following timing specification applies to timer0 and timer1 in pwm_out (pulse-width modulation) mode. timer signals are routed to the dpi_p 14C1 pins through the dpi sru. therefore, the timing specificatio ns provided below are valid at the dpi_p14C1 pins. timer wdth_cap timing the following timing specification applies to timer0 and timer1 in wdth_cap (pulse wi dth count and capture) mode. timer signals are routed to the dpi_p14C1 pins through the sru. therefore, the timing specifications provided below are valid at the dpi_p14C1 pins. table 23. timer pwm_out timing parameter min max unit switching characteristic t pwmo timer pulse width output 2 t pclk C 1.2 2 (2 31 C 1) t pclk ns figure 13. timer pwm_out timing pwm outputs t pwmo table 24. timer width capture timing parameter min max unit timing requirement t pwi timer pulse width 2 t pclk 2 (2 31 C 1) t pclk ns figure 14. timer width capture timing timer capture inputs t pwi rev. 0 | page 28 of 72 | june 2010 adsp-21469 pin to pin direct routing (dai and dpi) for direct pin connections only (for example dai_pb01_i to dai_pb02_o). table 25. dai and dpi pin to pin routing parameter min max unit timing requirement t dpio delay dai/dpi pin input valid to dai/dpi output valid 1.5 12 ns figure 15. dai and dpi pin to pin direct routing dai_pn dpi_pn dai_pm dpi_pm t dpio adsp-21469 rev. 0 | page 29 of 72 | june 2010 precision clock generator (direct pin routing) this timing is only valid when the sru is configured such that the precision clock generator (pcg) takes its inputs directly from the dai pins (via pin buffers) and sends its outputs directly to the dai pins. for the other ca ses, where the pcgs inputs and outputs are not directly routed to/from dai pins (via pin buffers) there is no timing data available. all timing param- eters and switching characteristics apply to external dai pins (dai_p01 C dai_p20). table 26. precision clock generator (direct pin routing) parameter min max unit timing requirement s t pcgiw input clock period t pclk 4 ns t strig pcg trigger setup before falling edge of pcg input clock 4.5 ns t htrig pcg trigger hold after falling edge of pcg input clock 3ns switching characteristics t dpcgio pcg output clock and frame sync active edge delay after pcg input clock 2.5 10 ns t dtrigclk pcg output clock delay after pcg trigger 2.5 + (2.5 t pcgip ) 10 + (2.5 t pcgip )ns t dtrigfs pcg frame sync delay after pcg trigger 2.5 + ((2.5 + d C ph) t pcgip ) 10 + ((2.5 + d C ph) t pcgip )ns t pcgow 1 output clock period 2 t pcgip C 1 ns d = fsxdiv, ph = fsxphase. for more information, see the adsp-214xx sharc processor hardware reference, precision clock genera tors chapter. 1 normal mode of operation. figure 16. precision clock generator (direct pin routing) dai_pn dpi_pn pcg_trigx_i dai_pm dpi_pm pcg_extx_i (clkin) dai_py dpi_py pck_clkx_o dai_pz dpi_pz pcg_fsx_o t dtrigfs t dtrigclk t dpcgio t strig t htrig t pcgow t dpcgio t pcgiw rev. 0 | page 30 of 72 | june 2010 adsp-21469 flags the timing specifications provided below apply to ami_addr23C0 and ami_data7C 0 when configured as flags. see table 9 on page 12 for more information on flag use. table 27. flags parameter min max unit timing requirement t fipw dpi_p14C1, ami_addr23C0, ami_data7C0, flag3C0 in pulse width 2 t pclk + 3 ns switching characteristic t fopw dpi_p14C1, ami_addr23C0, ami_data7C0, flag3C0 out pulse width 2 t pclk C 3 ns figure 17. flags flag inputs flag outputs t fopw t fipw adsp-21469 rev. 0 | page 31 of 72 | june 2010 ddr2 sdram read cycle timing table 28. ddr2 sdram read cycle timing, v dd-ddr2 nominal 1.8 v 200 mhz 1 1 in order to ensure proper operation of the ddr2, all the ddr2 gu idelines have to be strictly followed (see engineer-to-engineer note ee-349). 225 mhz 1 parameter min max min max unit timing requirements t ac dq output access time from ck/ck C1.0 0.7 C1.0 0.7 ns t dqsck dqs output access time from ck/ck C1.0 0.7 C1.0 0.7 ns t dqsq dqs-dq skew for dqs and associated dq signals 0.450 0.450 ns t qh dq, dqs output hold time from dqs 1.9 1.71 ns t rpre read preamble 0.6 0.6 t ck t rpst read postamble 0.25 0.25 t ck switching characteristics t ck clock cycle time 4.8 4.22 ns t ch minimum clock pulse width 2.35 2.75 2.05 2.45 ns t cl maximum clock pulse width 2.35 2.75 2.05 2.45 ns t as address setup time 1.85 1.65 ns t ah address hold time 1.0 0.9 ns figure 18. ddr2 sdram controller input ac timing ddr2_clkx ddr2_dqsn t ac t rpre t dqsq t dqsq t qh t rpst ddr2_data ddr2_clkx ddr2_dqsn t dqsck t ck t ch t cl t as t ah ddr2_addr ddr2_ctl t qh rev. 0 | page 32 of 72 | june 2010 adsp-21469 ddr2 sdram write cycle timing table 29. ddr2 sdram write cycle timing, v dd-ddr2 nominal 1.8 v 200 mhz 1 1 in order to ensure proper operation of the ddr2, all the ddr2 gu idelines have to be strictly followed (see engineer-to-engineer note no: ee-349). 225 mhz 1 parameter min max min max unit switching characteristics t ck clock cycle time 4.8 4.22 ns t ch minimum clock pulse width 2.35 2.75 2.05 2.45 ns t cl maximum clock pulse width 2.35 2.75 2.05 2.45 ns t dqss 2 2 write command to first dqs delay = wl t ck + t dqss . dqs latching rising transitions to associated clock edges C0.4 0.4 C0.45 0.45 ns t ds last data valid to dqs delay 0.6 0.5 ns t dh dqs to first data invalid delay 0.65 0.55 ns t dss dqs falling edge to clock setup time 1.95 1.65 ns t dsh dqs falling edge hold time from ck 2.05 1.8 ns t dqsh dqs input high pulse width 2.05 1.65 ns t dqsl dqs input low pulse width 2.0 1.65 ns t wpre write preamble 0.8 0.8 t ck t wpst write postamble 0.5 0.5 t ck t as control/address maximum delay from ddck rise 1.85 1.65 ns t ah control/address minimum delay from ddck rise 1.0 0.9 ns figure 19. ddr2 sdram controller output ac timing t ds t dh t dqss t dsh t dss t wpre t dqsl t dqsh t wpst ddr2_addr ddr2_ctl t as t ah ddr2_data/dm ddr2_clkx ddr2_clkx ddr2_dqsn ddr2_dqsn t ck t ch t cl adsp-21469 rev. 0 | page 33 of 72 | june 2010 ami read use these specifications for asyn chronous interfacing to memo- ries. note that timing for ami_ack, ami_data, ami_rd , ami_wr , and strobe timing parameters only apply to asyn- chronous access mode. table 30. memory read parameter min max unit timing requirements t dad address, selects delay to data valid 1, 2 w + t ddr 2_ clk C5.4 ns t drld ami_rd low to data valid 1 w C 3.2 ns t sds data setup to ami_rd high 2.5 ns t hdrh data hold from ami_rd high 3, 4 0ns t daak ami_ack delay from address, selects 2, 5 t ddr 2_ clk C9.5 + w ns t dsak ami_ack delay from ami_rd low 4 w C 7.0 ns switching characteristics t drha address selects hold after ami_rd high rh + 0.20 ns t darl address selects to ami_rd low 2 t ddr 2_ clk C 3.8 ns t rw ami_rd pulse width w C 1.4 ns t rwr ami_rd high to ami_rd low hi + t ddr 2_ clk C 1 ns w = (number of wait states specified in amictlx register) t ddr 2_ clk . rhc = (number of read hold cycles specified in amictlx register) t ddr 2_ clk where predis = 0 hi = rhc: read to read from same bank hi = rhc + ic: read to read from different bank hi = rhc + max (ic, (4 t ddr2_clk )): read to write from same or different bank where predis = 1 hi = rhc + max(ic, (4 t ddr2_clk )): read to write from same or different bank hi = rhc + (3 tddr2_clk): read to read from same bank hi = rhc + max(ic, (3 t ddr2_clk )): read to read from different bank ic = (number of idle cycles sp ecified in amictlx register) t ddr2_clk h = (number of hold cycles specified in amictlx register) t ddr2_clk 1 data delay/setup: system must meet t dad , t drld , or t sds. 2 the falling edge of ami_ms x, is referenced. 3 note that timing for ami_ack, ami_data, ami_rd , ami_wr , and strobe timing parameters only apply to asynchronous access mode. 4 data hold: user must meet t hdrh in asynchronous access mode. see test conditions on page 58 for the calculation of hold time s given capacitive and dc loads. 5 ami_ack delay/setup: user must meet t daak , or t dsak , for deassertion of ami_ack (low). rev. 0 | page 34 of 72 | june 2010 adsp-21469 figure 20. ami read ami_ack ami_data t drha t rw t hdrh t rwr t dad t darl t drld t sds t dsak t daak ami_wr ami_rd ami_addr ami_msx adsp-21469 rev. 0 | page 35 of 72 | june 2010 ami write use these specifications for asyn chronous interfacing to memo- ries. note that timing for ami_ack, ami_data, ami_rd , ami_wr , and strobe timing parameters only apply to asyn- chronous access mode. table 31. memory write parameter min max unit timing requirements t daak ami_ack delay from address, selects 1, 2 t ddr 2_ clk C 9.7 + w ns t dsak ami_ack delay from ami_wr low 1, 3 w C 6 ns switching characteristics t dawh address, selects to ami_wr deasserted 2 t ddr 2_ clk C3.1+ w ns t dawl address, selects to ami_wr low 2 t ddr 2_ clk C3 ns t ww ami_wr pulse width w C 1.3 ns t ddwh data setup before ami_wr high t ddr 2_ clk C3.0+ w ns t dwha address hold after ami_wr deasserted h + 0.15 ns t dwhd data hold after ami_wr deasserted h ns t datrwh data disable after ami_wr deasserted 4 t ddr 2_ clk C 1.37 + h t ddr 2_ clk + 4.9 + h ns t wwr ami_wr high to ami_wr low 5 t ddr 2_ clk C1.5+ h ns t ddwr data disable before ami_rd low 2t ddr 2_ clk C 6 ns t wde ami_wr low to data enabled t ddr 2_ clk C 3.5 ns w = (number of wait states specified in amictlx register) t sddr 2_ clk h = (number of hold cycles specified in amictlx register) t ddr 2_ clk 1 ami_ack delay/setup: system must meet t daak , or t dsak , for deassertion of ami_ack (low). 2 the falling edge of ami_msx is referenced. 3 note that timing for ami_ack, ami_data, ami_rd , ami_wr , and strobe timing parameters only applies to asynchronous access mode. 4 see test conditions on page 58 for calculation of hold times given capacitive and dc loads. 5 for write to write: t ddr2_clk + h, for both same bank and differe nt bank. for write to read: (3 t ddr2_clk ) + h, for the same bank and different banks. figure 21. ami write ami_ack ami_data t dawh t dwha t wwr t datrwh t dwhd t ww t ddwr t ddwh t dawl t wde t dsak t daak ami_rd ami_wr ami_addr ami_msx rev. 0 | page 36 of 72 | june 2010 adsp-21469 link ports calculation of link receiver data setup and hold relative to link clock is required to determin e the maximum allowable skew that can be introduced in the transmission path length differ- ence between ldata and lclk. setup skew is the maximum delay that can be introduced in ldata relative to lclk: (setup skew = t lclktwh min C t dldch C t sldcl ). hold skew is the maximum delay that can be introduced in lclk relative to ldata: (hold skew = t lclktwl min C t hldch C t hldcl ). table 32. link portsreceive parameter min max unit timing requirements t sldcl data setup before lclk low 0.5 ns t hldcl data hold after lclk low 1.5 ns t lclkiw lclk period t lclk (6 ns) ns t lclkrwl lclk width low 2.6 ns t lclkrwh lclk width high 2.6 ns switching characteristics t dlalc lack low delay after lclk low 1 512ns 1 lack goes low with t dlalc relative to rise of lclk after first byte, but does not go low if the receiver's link buffer is not about to fill. figure 22. link portsreceive ldat7C0 lclk lack (out) t hldcl t sldcl in t lclkrwh t lclkrwl t lclkiw t dlalc adsp-21469 rev. 0 | page 37 of 72 | june 2010 table 33. link portstransmit parameter min max unit timing requirements t slach lack setup before lclk low 8.5 ns t hlach lack hold after lclk low 0 ns switching characteristics t dldch data delay after lclk high 1 ns t hldch data hold after lclk high C1 ns t lclktwl lclk width low 0.5 t lclk C 0.4 0.6 t lclk + 0.4 1 ns t lclktwh lclk width high 0.4 t lclk C 0.4 1 0.5 t lclk + 0.4 ns t dlaclk lclk low delay after lack high t lclk C 2 t lclk + 8 ns 1 for 1:2.5 ratio. for other ratios this specification is 0.5 t lclk C 1. figure 23. link portstransmit lclk ldat7C0 lack (in) out t dldch t hldch t slach t hlach t dlaclk t lclktwh t lclktwl last byte transmitted first byte transmitted 1 notes the t slach and t hlach specifications apply only to the lack falling edge. if these specifications are met, lclk would extend and the dotted lclk falling edge would not occur as shown. the position of the dotted falling edge can be calculated using the t lclktwh specification. t lclktwh min should be used for t slach and t lclktwh max for t hlach . rev. 0 | page 38 of 72 | june 2010 adsp-21469 serial ports in slave transmitter mode and ma ster receiver mode the maxi- mum serial port frequency is f pclk /8. to determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) serial clock (sclk) width. serial port signals are routed to the dai_p20C1 pins using the sru. therefore, the timing spec ifications provided below are valid at the dai_p20C1 pins. in figure 24 either the rising edge or the falling edge of sclk (exter nal or internal) can be used as the active sampling edge. table 34. serial portsexternal clock parameter min max unit timing requirements t sfse 1 frame sync setup before sclk (externally generated frame sync in either transmit or receive mode) 2.5 ns t hfse 1 frame sync hold after sclk (externally generated frame sync in either transmit or receive mode) 2.5 ns t sdre 1 receive data setup before receive sclk 1.9 ns t hdre 1 receive data hold after sclk 2.5 ns t sclkw sclk width (t pclk 4) 2 C 0.5 ns t sclk sclk period t pclk 4 ns switching characteristics t dfse 2 frame sync delay after sclk (internally generated frame sync in either transmit or receive mode) 10.25 ns t hofse 2 frame sync hold after sclk (internally generated frame sync in either transmit or receive mode) 2 ns t ddte 2 transmit data delay after transmit sclk 8.5 ns t hdte 2 transmit data hold after transmit sclk 2 ns 1 referenced to sample edge. 2 referenced to drive edge. table 35. serial portsinternal clock parameter min max unit timing requirements t sfsi 1 frame sync setup before sclk (externally generated frame sync in either transmit or receive mode) 7 ns t hfsi 1 frame sync hold after sclk (externally generated frame sync in either transmit or receive mode) 2.5 ns t sdri 1 receive data setup before sclk 7 ns t hdri 1 receive data hold after sclk 2.5 ns switching characteristics t dfsi 2 frame sync delay after sclk (internally generated frame sync in transmit mode) 4 ns t hofsi 2 frame sync hold after sclk (internally generated frame sync in transmit mode) C1.0 ns t dfsir 2 frame sync delay after sclk (internally generated frame sync in receive mode) 9.75 ns t hofsir 2 frame sync hold after sclk (internally generated frame sync in receive mode) C1.0 ns t ddti 2 transmit data delay after sclk 3.25 ns t hdti 2 transmit data hold after sclk C1.25 ns t sclkiw transmit or receive sclk width 2 t pclk C 1.5 2 t pclk + 1.5 ns 1 referenced to the sample edge. 2 referenced to drive edge. adsp-21469 rev. 0 | page 39 of 72 | june 2010 figure 24. serial ports drive edge sample edge dai_p20C1 (data channel a/b) dai_p20C1 (fs) dai_p20C1 (sclk) t hofsir t hfsi t hdri data receiveinternal clock drive edge sample edge dai_p20C1 (data channel a/b) dai_p20C1 (fs) dai_p20C1 (sclk) t hfsi t ddti data transmitinternal clock drive edge sample edge dai_p20C1 (data channel a/b) dai_p20C1 (fs) dai_p20C1 (sclk) t hofse t hofsi t hdti t hfse t hdte t ddte data transmitexternal clock drive edge sample edge dai_p20C1 (data channel a/b) dai_p20C1 (fs) dai_p20C1 (sclk) t hofse t hfse t hdre data receiveexternal clock t sclkiw t dfsir t sfsi t sdri t sclkw t dfse t sfse t sdre t dfse t sfse t sfsi t dfsi t sclkiw t sclkw rev. 0 | page 40 of 72 | june 2010 adsp-21469 table 36. serial portsenable and three-state parameter min max unit switching characteristics t ddten 1 data enable from external transmit sclk 2 ns t ddtte 1 data disable from external transmit sclk 11.5 ns t ddtin 1 data enable from internal transmit sclk C1 ns 1 referenced to drive edge. figure 25. serial portsenable and three-state drive edge drive edge drive edge dai_p20C1 (data channel a/b) dai_p20C1 (frame sync) dai_p20C1 (sclk, ext) t ddtin t ddten t ddtte adsp-21469 rev. 0 | page 41 of 72 | june 2010 the sportx_tdv_o output signal (routing unit) becomes active in sport multichannel mode. during transmit slots (enabled with active channe l selection registers) the sportx_tdv_o is asserted for communication with external devices. table 37. serial portstd v (transmit data valid) parameter min max unit switching characteristics 1 t drdven data-valid enable delay from drive edge of external clock 3 ns t dfdven data-valid disable delay from drive edge of external clock 8 ns t drdvin data-valid enable delay from drive edge of internal clock C0.1 ns t dfdvin data-valid disable delay from drive edge of internal clock 2 ns 1 referenced to drive edge. figure 26. serial portstransmit data valid internal and external clock drive edge drive edge dai_p20C1 (sclk, ext) t drdven t dfdven drive edge drive edge dai_p20C1 (sclk, int) t drdvin t dfdvin tdvx dai_p20-1 tdvx dai_p20-1 rev. 0 | page 42 of 72 | june 2010 adsp-21469 table 38. serial portsexternal late frame sync parameter min max unit switching characteristics t ddtlfse 1 data delay from late external transmit frame sync or external receive frame sync with mce = 1, mfd = 0 7.75 ns t ddtenfs 1 data enable for mce = 1, mfd = 0 0.5 ns 1 the t ddtlfse and t ddtenfs parameters apply to left-justified as well as dsp serial mode, and mce = 1, mfd = 0. figure 27. external late frame sync drive sample external receive fs with mce = 1, mfd = 0 2nd bit dai_p20C1 (sclk) dai_p20C1 (fs) dai_p20C1 (data channel a/b) 1st bit drive t ddte/i t hdte/i t ddtlfse t ddtenfs t sfse/i drive sample late external transmit fs 2nd bit dai_p20C1 (sclk) dai_p20C1 (fs) dai_p20C1 (data channel a/b) 1st bit drive t ddte/i t hdte/i t ddtlfse t ddtenfs t sfse/i t hfse/i t hfse/i adsp-21469 rev. 0 | page 43 of 72 | june 2010 input data port (idp) the timing requirements for the idp are given in table 39 . idp signals are routed to the dai_p20C1 pins using the sru. there- fore, the timing specifications provided below are valid at the dai_p20C1 pins. table 39. input data port (idp) parameter min max unit timing requirements t sisfs 1 frame sync setup before serial clock rising edge 3.8 ns t sihfs 1 frame sync hold after serial clock rising edge 2.5 ns t sisd 1 data setup before serial clock rising edge 2.5 ns t sihd 1 data hold after serial clock rising edge 2.5 ns t idpclkw clock width (t pclk 4) 2 C 1 ns t idpclk clock period t pclk 4 ns 1 the serial clock, data, and frame sync signals can come from any of the dai pins. the serial clock and frame sync signals can also come via pcg or sports. pcg's input can be either clkin or any of the dai pins. figure 28. idp master timing dai_p20C1 (sclk) sample edge dai_p20C1 (fs) dai_p20C1 (sdata) t ipdclk t ipdclkw t sisfs t sihfs t sihd t sisd rev. 0 | page 44 of 72 | june 2010 adsp-21469 parallel data acquisition port (pdap) the timing requirements for the pdap are provided in table 40 . pdap is the parallel mode operation of channel 0 of the idp. for details on the operation of the pdap, see the pdap chapter of the adsp-214xx sharc pr ocessor hardware reference . note that the 20 bits of external pdap data can be provided through the ami_addr 23C4 pins or over the dai pins. table 40. parallel data acquisition port (pdap) parameter min max unit timing requirements t sphold 1 pdap_hold setup before pdap_clk sample edge 2.5 ns t hphold 1 pdap_hold hold after pdap_clk sample edge 2.5 ns t pdsd 1 pdap_dat setup before serial clock pdap_clk sample edge 3.85 ns t pdhd 1 pdap_dat hold after serial clock pdap_clk sample edge 2.5 ns t pdclkw clock width (t pclk 4) 2 C 3 ns t pdclk clock period t pclk 4 ns switching characteristics t pdhldd delay of pdap strobe after last pdap_clk capture edge for a word 2 t pclk + 3 ns t pdstrb pdap strobe pulse width 2 t pclk C 1 ns 1 data source pins are ami_addr23C4 or dai pins. source pins for serial clock and frame sync are 1) ami_addr3C2 pins, 2) dai pin s. figure 29. pdap timing dai_p20C1 (pdap_clk) sample edge dai_p20C1 (pdap_hold) dai_p20C1 (pdap_strobe) t pdstrb t pdhldd t pdhd t pdsd t sphold t hphold t pdclk t pdclkw dai_p20C1/ addr23C4 (pdap_data) adsp-21469 rev. 0 | page 45 of 72 | june 2010 sample rate converterserial input port the asrc input signals are rout ed from the dai_p20C1 pins using the sru. therefore, the timi ng specifications provided in table 41 are valid at the dai_p20C1 pins. table 41. asrc, serial input port parameter min max unit timing requirements t srcsfs 1 frame sync setup before serial clock rising edge 4 ns t srchfs 1 frame sync hold after serial clock rising edge 5.5 ns t srcsd 1 data setup before serial clock rising edge 4 ns t srchd 1 data hold after serial clock rising edge 5.5 ns t srcclkw clock width (t pclk 4) 2 C 1 ns t srcclk clock period t pclk 4 ns 1 the serial clock, data, and frame sync signals can come from any of the dai pins. the serial clock and frame sync signals can also come via pcg or sports. pcgs input can be either clkin or any of the dai pins. figure 30. asrc serial input port timing dai_p20C1 (sclk) sample edge dai_p20C1 (fs) dai_p20C1 (sdata) t srcclk t srcclkw t srcsfs t srchfs t srchd t srcsd rev. 0 | page 46 of 72 | june 2010 adsp-21469 sample rate converterserial output port for the serial output port, the frame sync is an input and it should meet setup and hold times with regard to the serial clock on the output port. the serial da ta output has a hold time and delay specification with regard to serial clock. note that the serial clock rising edge is the sampling edge, and the falling edge is the drive edge. table 42. asrc, serial output port parameter min max unit timing requirements t srcsfs 1 frame sync setup before serial clock rising edge 4 ns t srchfs 1 frame sync hold after serial clock rising edge 5.5 ns t srcclkw clock width (t pclk 4) 2 C 1 ns t srcclk clock period t pclk 4 ns switching characteristics t srctdd 1 transmit data delay after serial clock falling edge 9.9 ns t srctdh 1 transmit data hold after serial clock falling edge 1 ns 1 the serial clock, data, and frame sync signals can come from any of the dai pins. the serial clock and frame sync signals can also come via pcg or sports. pcgs input can be either clkin or any of the dai pins. figure 31. asrc serial output port timing dai_p20C1 (sclk) sample edge dai_p20C1 (fs) dai_p20C1 (sdata) t srcclk t srcclkw t srcsfs t srchfs t srctdd t srctdh adsp-21469 rev. 0 | page 47 of 72 | june 2010 pulse-width modulation (pwm) generators the following timing specifications apply when the ami_addr23C8 pins are configured as pwm. table 43. pulse-width modulation (pwm) timing parameter min max unit switching characteristics t pwmw pwm output pulse width t pclk C 2 (2 16 C 2) t pclk C 2 ns t pwmp pwm output period 2 t pclk C 1.5 (2 16 C 1) t pclk C 1.5 ns figure 32. pwm timing pwm outputs t pwmw t pwmp rev. 0 | page 48 of 72 | june 2010 adsp-21469 s/pdif transmitter serial data input to the s/pdif transmitter can be formatted as left-justified, i 2 s, or right-justified with word widths of 16, 18, 20, or 24 bits. the following se ctions provide timing for the transmitter. s/pdif transmitter-serial input waveforms figure 33 shows the right-justified mo de. lrclk is high for the left channel and low fo r the right channel. data is valid on the rising edge of serial clock. the msb is delayed minimum in 24-bit output mode or maximum in 16-bit output mode from an lrclk transition, so that when there are 64 serial clock peri- ods per lrclk period, the lsb of the data will be right-justified to the next lrclk transition. figure 34 shows the default i 2 s-justified mode. lrclk is low for the left channel and hi for the right channel. data is valid on the rising edge of serial clock. the msb is left-justified to an lrclk transition but with a delay. figure 35 shows the left-justified mo de. lrclk is high for the left channel and lo for the right channel. data is valid on the rising edge of serial clock. the msb is left-justified to an lrclk transition with no delay. table 44. s/pdif transmitter right-justified mode parameter nominal unit timing requirement t rjd lrclk to msb delay in right-justified mode 16-bit word mode 18-bit word mode 20-bit word mode 24-bit word mode 16 14 12 8 sclk sclk sclk sclk figure 33. right-justified mode table 45. s/pdif transmitter i 2 s mode parameter nominal unit timing requirement t i 2 sd lrclk to msb delay in i 2 s mode 1 sclk figure 34. i 2 s-justified mode msb left/right channel lsb lsb msbC1 msbC2 lsb+2 lsb+1 dai_p20C1 lrclk dai_p20C1 sclk dai_p20C1 sdata t rjd msb left/right channel lsb msbC1 msbC2 lsb+2 lsb+1 dai_p20C1 lrclk dai_p20C1 sclk dai_p20C1 sdata t i2sd adsp-21469 rev. 0 | page 49 of 72 | june 2010 table 46. s/pdif transmitter left-justified mode parameter nominal unit timing requirement t ljd lrclk to msb delay in left-justified mode 0 sclk figure 35. left-justified mode msb left/right channel lsb msbC1 msbC2 lsb+2 lsb+1 dai_p20C1 lrclk dai_p20C1 sclk dai_p20C1 sdata t ljd rev. 0 | page 50 of 72 | june 2010 adsp-21469 s/pdif transmitter input data timing the timing requirements for th e s/pdif transmitter are given in table 47 . input signals are routed to the dai_p20C1 pins using the sru. therefore, the ti ming specifications provided below are valid at the dai_p20C1 pins. oversampling clock (hfclk) switching characteristics the s/pdif transmitter has an oversampling clock. this hfclk input is divided down to generate the biphase clock. table 47. s/pdif transmitter input data timing parameter min max unit timing requirements t sisfs 1 frame sync setup before serial clock rising edge 3 ns t sihfs 1 frame sync hold after serial clock rising edge 3 ns t sisd 1 data setup before serial clock rising edge 3 ns t sihd 1 data hold after serial clock rising edge 3 ns t sitxclkw transmit clock width 9 ns t sitxclk transmit clock period 20 ns t sisclkw clock width 36 ns t sisclk clock period 80 ns 1 the serial clock, data, and frame sync signals can come from an y of the dai pins. the serial clock and frame sync signals can a lso come via pcg or sports. pcgs input can be either clkin or any of the dai pins. figure 36. s/pdif transmitter input timing sample edge dai_p20C1 (txclk) dai_p20C1 (sclk) dai_p20C1 (fs) dai_p20C1 (sdata) t sitxclkw t sitxclk t sisclkw t sisclk t sisfs t sihfs t sisd t sihd table 48. oversampling clock (hfclk) switching characteristics parameter max unit hfclk frequency for hfclk = 384 frame sync oversampling ratio frame sync <= 1/t sihfclk mhz hfclk frequency for hfclk = 256 frame sync 49.2 mhz frame rate (fs) 192.0 khz adsp-21469 rev. 0 | page 51 of 72 | june 2010 s/pdif receiver the following section describes timing as it relates to the s/pdif receiver. internal digital pll mode in the internal digital phase-lock ed loop mode the internal pll (digital pll) generates the 512 fs clock. table 49. s/pdif receiver inte rnal digital pll mode timing parameter min max unit switching characteristics t dfsi lrclk delay after serial clock 5 ns t hofsi lrclk hold after serial clock C2 ns t ddti transmit data delay after serial clock 5 ns t hdti transmit data hold after serial clock C2 ns t sclkiw 1 transmit serial clock width 8 t pclk C 2 ns 1 serial clock frequency is 64 frame s ync, where fs = the frequency of lrclk. figure 37. s/pdif receiver internal digital pll mode timing dai_p20C1 (sclk) sample edge dai_p20C1 (fs) dai_p20C1 (data channel a/b) drive edge t sclkiw t dfsi t hofsi t ddti t hdti rev. 0 | page 52 of 72 | june 2010 adsp-21469 spi interfacemaster the adsp-21469 contains two spi ports. both primary and sec- ondary are available through dpi only. the timing provided in table 50 and table 51 applies to both. table 50. spi interface protocolmaster switching and timing specifications parameter min max unit timing requirements t sspidm data input valid to spiclk edge (data input setup time) 8.2 ns t hspidm spiclk last sampling edge to data input not valid 2 ns switching characteristics t spiclkm serial clock cycle 8 t pclk C 2 ns t spichm serial clock high period 4 t pclk C 2 ns t spiclm serial clock low period 4 t pclk C 2 ns t ddspidm spiclk edge to data out valid (data out delay time) 2.5 ns t hdspidm spiclk edge to data out not valid (data out hold time) 4 t pclk C 2 ns t sdscim dpi pin (spi device select) low to first spiclk edge 4 t pclk C 2 ns t hdsm last spiclk edge to dpi pin (spi device select) high 4 t pclk C 2 ns t spitdm sequential transfer delay 4 t pclk C 1 ns figure 38. spi master timing t spichm t sdscim t spiclm t spiclkm t hdsm t spitdm t ddspidm t hspidm t sspidm dpi (output) mosi (output) miso (input) mosi (output) miso (input) cphase = 1 cphase = 0 t hdspidm t hspidm t hspidm t sspidm t sspidm t ddspidm t hdspidm spiclk (cp = 0, cp = 1) (output) adsp-21469 rev. 0 | page 53 of 72 | june 2010 spi interfaceslave table 51. spi interface protocolslave switching and timing specifications parameter min max unit timing requirements t spiclks serial clock cycle 4 t pclk C 2 ns t spichs serial clock high period 2 t pclk C 2 ns t spicls serial clock low period 2 t pclk C 2 ns t sdsco spids assertion to first spiclk edge, cphase = 0 or cphase = 1 2 t pclk ns t hds last spiclk edge to spids not asserted, cphase = 0 2 t pclk ns t sspids data input valid to spiclk edge (data input setup time) 2 ns t hspids spiclk last sampling edge to data input not valid 2 ns t sdppw spids deassertion pulse width (cphase = 0) 2 t pclk ns switching characteristics t dsoe spids assertion to data out active 0 6.8 ns t dsoe 1 spids assertion to data out active (spi2) 0 8 ns t dsdhi spids deassertion to data high impedance 0 10.5 ns t dsdhi 1 spids deassertion to data high impedance (spi2) 0 10.5 ns t ddspids spiclk edge to data out valid (data out delay time) 9.5 ns t hdspids spiclk edge to data out not valid (data out hold time) 2 t pclk ns t dsov spids assertion to data out valid (cphase = 0) 5 t pclk ns 1 the timing for these parameters applies when the spi is routed through the signal ro uting unit. for more information, see the p rocessor hardware refere nce, serial peripheral interface port chapter. figure 39. spi slave timing t spichs t spicls t spiclks t hds t sdppw t sdsco t dsoe t ddspids t ddspids t dsdhi t hdspids t hspids t sspids t sspids t dsdhi t ddspids t dsov t hspids t sspids t hdspids spids (input) miso (output) mosi (input) miso (output) mosi (input) cphase = 1 cphase = 0 spiclk (cp = 0, cp = 1) (input) rev. 0 | page 54 of 72 | june 2010 adsp-21469 media local bus all the numbers given are appl icable for all speed modes (1024 fs, 512 fs, and 256 fs for 3-pin; 512 fs and 256 fs for 5- pin) unless otherwise specified. please refer to medialb specifi- cation document rev 3.0 for more details. table 52. mlb interface, 3-pin specifications parameter min typ max unit 3-pin characteristics t mlbclk mlb clock period 1024 fs 512 fs 256 fs 20.3 40 81 ns ns ns t mckl mlbclk low time 1024 fs 512 fs 256 fs 6.1 14 30 ns ns ns t mckh mlbclk high time 1024 fs 512 fs 256 fs 9.3 14 30 ns ns ns t mckr mlbclk rise time (v il to v ih ) 1024 fs 512 fs/256 fs 1 3 ns ns t mckf mlbclk fall time (v ih to v il ) 1024 fs 512 fs/256 fs 1 3 ns ns t mpwv 1 mlbclk pulse width variation 1024 fs 512 fs/256 fs 0.7 2.0 ns p-p ns p-p t dsmcf dat/sig input setup time 1 ns t dhmcf dat/sig input hold time 1 ns t mcfdz dat/sig output time to three-state 0 15 ns t mcdrv dat/sig output data delay from mlbclk rising edge 8 ns t mdzh 2 bus hold time 1024 fs 512 fs/256 fs 2 4 ns ns c mlb dat/sig pin load 1024 fs 512 fs/256 fs 40 60 pf pf 1 pulse width variation is measured at 1.25 v by triggering on one edge of mlbclk and measuring the spread on the other edge, mea sured in nanoseconds pe ak-to-peak (ns p-p). 2 the board must be designed to ensure that the high impedance bus does not leave the lo gic state of the final driven bit for thi s time period. therefore, coupling must be minimized while meeting the ma ximum capacitive load listed. adsp-21469 rev. 0 | page 55 of 72 | june 2010 figure 40. mlb timing (3-pin interface) table 53. mlb interface, 5-pin specifications parameter min typ max unit 5-pin characteristics t mlbclk mlb clock period 512 fs 256 fs 40 81 ns ns t mckl mlbclk low time 512 fs 256 fs 15 30 ns ns t mckh mlbclk high time 512 fs 256 fs 15 30 ns ns t mckr mlbclk rise time (v il to v ih )6ns t mckf mlbclk fall time (v ih to v il )6ns t mpwv 1 mlbclk pulse width variation 2 ns p-p t dsmcf 2 dat/sig input setup time 3 ns t dhmcf dat/sig input hold time 5 ns t mcdrv ds/do output data delay from mlbclk rising edge 8 ns t mcrdl 3 do/so low from mlbclk high 512 fs 256 fs 10 20 ns ns c mlb ds/do pin load 40 pf 1 pulse width variation is measured at 1.25 v by triggering on one edge of mlbclk and measuring the spread on the other edge, mea sured in nanoseconds pe ak-to-peak (ns p-p). 2 gate delays due to or'ing logic on the pins must be accounted for. 3 when a node is not driving valid data onto the bus, the mlbso and mlbdo output lines shall remain low. if the output lines can float at anytime, incl uding while in reset, external pull-down resistors are required to keep the outputs fr om corrupting the medialb signal lines when not being driven. t mckh mlbsig/ mlbdat (rx, input) t mckl t mckr mlbsig/ mlbdat (tx, output) t mcfdz t dsmcf mlbclk t mlbclk valid t dhmcf t mckf t mcdrv valid t mdzh rev. 0 | page 56 of 72 | june 2010 adsp-21469 figure 41. mlb timing (5-pin interface) figure 42. mlb 3-pin and 5-pin ml bclk pulse width variation timing t mckh mlbsig, mlbdat (rx, input) t mckl t mckr mlbso, mlbdo (tx, output) t dsmcf mlbclk t mlbclk valid valid t dhmcf t mckf t mcdrv t mcrdl t mpwv mlbclk adsp-21469 rev. 0 | page 57 of 72 | june 2010 universal asynchronous receiver-transmitter (uart) portsreceive and transmit timing for information on the uart po rt receive and transmit opera- tions, see the adsp-214xx sharc hard ware reference manual . 2-wire interface (twi)receive and transmit timing for information on the twi receive and transmit operations, see the adsp-214xx sharc hardwa re reference manual . jtag test access port and emulation table 54. jtag test access port and emulation parameter min max unit timing requirements t tck tck period 20 ns t stap tdi, tms setup before tck high 5 ns t htap tdi, tms hold after tck high 6 ns t ssys 1 1 system inputs = ami_data, ddr2_data, clkcfg1 -0, bootcfg2-0 reset, dai, dpi, flag3-0. system inputs setup before tck high 7 ns t hsys 1 system inputs hold after tck high 18 ns t trstw trst pulse width 4 t ck ns switching characteristics t dtdo tdo delay from tck low 10 ns t dsys 2 2 system outputs = ami_addr/data, ddr2_addr/data, ami_ctrl, ddr2_ctrl, dai, dpi, flag3-0, emu . system outputs delay after tck low t ck 2 + 7 ns figure 43. ieee 1149.1 jtag test access port tck tms tdi tdo system inputs system outputs t tck t stap t htap t dtdo t ssys t hsys t dsys rev. 0 | page 58 of 72 | june 2010 adsp-21469 test conditions the ac signal specifications (timing parameters) appear in table 19 on page 25 through table 54 on page 57 . these include output disable time, output enable time, and capacitive loading. the timing specifications for the sharc apply for the voltage reference levels in figure 44 . timing is measured on sign als when they cross the v meas level as described in figure 45 . all delays (in nanoseconds) are mea- sured between the point that the first signal reaches v meas and the point that the second signal reaches v meas . the value of v meas is 1.5 v for non-ddr pins and 0.9 v for ddr pins. output drive currents figure 46 and figure 46 shows typical i-v characteristics for the output drivers of the adsp-21469, and table 55 shows the pins associated with each driver. th e curves represent the current drive capability of the output drivers as a function of output voltage. figure 44. equivalent device loading for ac measurements (includes all fixtures) figure 45. voltage reference levels for ac measurements t1 zo = 50 (impedance) td = 4.04 1.18 ns 2pf tester pin electronics 50 0.5pf 70 400 45 4pf notes: the worst-case transmission line delay is shown and can be used for the output timing analysis to reflect the transmission line effect and must be considered. the transmission line (td) is for load only and does not affect the data sheet timing specifications. analog devices recommends using the ibis model timing for a given system requirement. if necessary, a system may incorporate external drivers to compensate for any timing differences. v load dut output 50 input or output v meas v meas table 55. driver types driver type associated pins a lack1C0, ldat0[7:0], ldat1[7:0], mlbclk, mlbdat, mlbdo, mlbsig, mlbso, ami_ack, ami_addr23C0, ami_data7C0, ami_ms1C0 , ami_rd , ami_wr , dai_p, dpi_p, emu , flag3C0, resetout, tdo blclk1C0 c ddr2_addr15C0, ddr2_ba2C0, ddr2_cas, ddr2_cke, ddr2_cs3C0, ddr2_data15C0, ddr2_dm1C0, ddr2_odt, ddr2_ras, ddr2_we d (true) ddr2_clk1C0, ddr2_dqs1C0 d (comp) ddr2_clk1C0 , ddr2_dqs1C0 figure 46. output buffer characteristics (worst-case non-ddr2) sweep (v ddext ) voltage (v) 0 3.5 0.5 1.0 1.5 2.0 2.5 3.0 0 100 200 source/sink (v ddext ) current (ma) 150 50 - 100 - 200 - 150 - 50 v oh 3.13 v, 125 c v ol 3.13 v, 125 c type a type a type b type b adsp-21469 rev. 0 | page 59 of 72 | june 2010 capacitive loading output delays and holds are based on standard capacitive loads: 30 pf on all pins (see table 55 ). figure 52 through figure 57 show graphically how output dela ys and holds vary with load capacitance. the graphs of figure 48 through figure 57 may not be linear outside the ranges sh own for typical output delay vs. load capacitance and typical ou tput rise time (20% to 80%, v = min) vs. load capacitance. figure 47. output buffer characteristics (worst-case ddr2) figure 48. typical output rise/fall time non-ddr2 (20% to 80%, v dd_ext = max) sweep (v ddext ) voltage (v) 0 0 30 50 source (v ddext ) current (ma) 40 20 - 50 v oh 3.13 v, 125 c v ol 3.13 v, 125 c 10 - 30 - 40 - 20 - 10 1.5 0.5 1.0 type c & d, half drive type c & d, full drive type c & d, half drive type c & d, full drive load capacitance (pf) 6 0 0 7 4 2 1 3 rise and fall times (ns) 125 200 100 25 175 50 75 150 5 y = 0.0342x + 0.309 y = 0.0153x + 0.2131 y = 0.0413x + 0.2651 y = 0.0152x + 0.1882 type a drive fall type a drive rise type b drive fall type b drive rise figure 49. typical output rise/fall time non-ddr2 (20 to 80, v dd_ext = min) figure 50. typical output rise/fall time ddr2 (20 to 80, v dd_ext = max) load capacitance (pf) 6 0 0 10 4 2 rise and fall times (ns) 25 200 150 50 75 100 125 175 y = 0.0746x + 0.5146 y = 0.0572x + 0.5571 y = 0.0278x + 0.3138 y = 0.0258x + 0.3684 type a fall type a rise type b rise type b fall 8 12 14 load capacitance (pf) 0.6 0 0.7 0.4 0.2 0.1 0.3 rise and fall times (ns) 0.5 y = 0.0058x + 0.2113 y = 0.0217x + 0.26 y = 0.0198x + 0.2304 y = 0.0061x + 0.207 05 40 30 10 15 20 25 35 type c & d half drive fall 0.8 0.9 1.0 type c & d half drive rise type c & d full drive rise type c & d full drive fall rev. 0 | page 60 of 72 | june 2010 adsp-21469 figure 51. typical output rise/fall time ddr2 (20% to 80%, v dd_ext = min) figure 52. typical output rise/fall delay non-ddr (v dd_ext = min) load capacitance (pf) 0 rise and fall times (ns) 25 40 20 535 10 15 30 3 0 3.5 2 1 0.5 1.5 2.5 4 y = 0.0841x + 0.8997 type c & d half drive fall y = 0.0617x + 0.7995 type c & d half drive rise y = 0.0421x + 0.9257 type c & d full drive fall type c & d full drive rise y = 0.0304x + 0.8204 load capacitance (pf) 6 0 0 7 4 2 1 3 rise and fall times delay (ns) 125 200 100 25 175 50 75 150 5 y = 0.0256x + 3.5876 y = 0.0116x + 3.5697 8 y = 0.0359x + 2.9227 9 10 y = 0.0136x + 3.1135 type a drive fall type a drive rise type b drive fall type b drive rise figure 53. typical output rise/fall delay no- ddr (v dd_ext = max) figure 54. typical output rise/fall delay ddr pad c (v dd_ext = min) load capacitance (pf) 3 0 3.5 2 1 0.5 1.5 rise and fall delay (ns) 2.5 y = 0.0152x + 1.7611 y = 0.0060x + 1.7614 y = 0.0196x + 1.2934 y = 0.0074x + 1.421 0 25 200 150 50 75 100 125 175 type a fall type a rise type b rise type b fall 4 4.5 load capacitance (pf) 0 rise and fall delay (ns) 25 20 535 10 15 30 type c half drive (fall) y = 0.0122x + 2.0405 type c half drive (rise) y = 0.0079x + 2.0476 type c full drive (rise & fall) y = 0.0023x + 1.9472 2.4 2.6 1.8 1.6 1.4 2.8 2.2 2.0 3.0 adsp-21469 rev. 0 | page 61 of 72 | june 2010 thermal characteristics the adsp-21469 processor is rate d for performa nce over the temperature range specified in operating conditions on page 17 . table 56 airflow measurements comply with jedec standards jesd51-2 and jesd51-6, and th e junction-to-board measure- ment complies with jesd51-8. test board design complies with jedec standards jesd51-7 (csp_b ga). the junction-to-case measurement complies with mi l- std-883. all measurements use a 2s2p jedec test board. to determine the junction temper ature of the device while on the application pcb use: t j = junction temperature (c) where: t case = case temperature (c) measur ed at the top center of the package ? jt = junction-to-top (of package) characterization parameter is the typical value from table 56 . p d = power dissipation values of ? ja are provided for package comparison and pcb design considerations. ? ja can be used for a first order approxi- mation of t j by the equation: where: t a = ambient temperature c values of ? jc are provided for pack age comparison and pcb design considerations when an external heat sink is required. figure 55. typical output rise/fall delay ddr pad d (v dd_ext = min) figure 56. typical output rise/fall delay ddr pad c (v dd_ext = max) load capacitance (pf) 2.4 0 2.6 1.8 1.6 1.4 2.8 rise and fall delay (ns) 25 20 535 10 15 30 2.2 2.0 3.0 type d half drive true (fall) type d half drive comp (fall) y = 0.0123x + 2.3194 type d half drive true (rise) y = 0.0077x + 2.2912 type d half drive comp (rise) y = 0.0077x + 2.2398 type d full drive comp (rise) y = 0.0022x + 2.1499 type d full drive true (rise & fall) type d full drive comp (fall ) y = 0.0022x + 2.2027 load capacitance (pf) 0 rise and fall delay (ns) 25 20 535 10 15 30 type c half drive (fall) y = 0.0046x + 1.0577 type c half drive (rise) y = 0.0032x + 1.0622 type c full drive (rise & fall) y = 0.0007x + 0.9841 1.1 1.2 0.8 0.7 1.3 1.0 0.9 1.4 figure 57. typical output rise/fall delay ddr pad d (v dd_ext = max) load capacitance (pf) 1.3 0 1.4 1.0 0.9 0.8 rise and fall delay (ns) 25 20 535 10 15 30 1.2 1.1 type d half drive true (fall) type d half drive comp (fall) y = 0.0047x + 1.1884 type d half drive true (rise) y = 0.003x + 1.1758 type d half drive comp (rise) y = 0.0031x + 1.1599 type d full drive comp (rise) y = 0.0007x + 1.0964 type d full drive true (rise & fall) type d full drive comp (fall) y = 0.0008x + 1.1074 t j t case ? jt p d ? ?? + = t j t a ? ja p d ? ?? + = rev. 0 | page 62 of 72 | june 2010 adsp-21469 values of ? jb are provided for package comparison and pcb design considerations. note that the thermal characteristics val- ues provided in table 56 are modeled values. thermal diode the adsp-21469 processors inco rporate therma l diodes to monitor the die temperature. the thermal diode of is a grounded collector pnp bipolar ju nction transistor (bjt). the thd_p pin is connected to the emitter and the thd_m pin is connected to the base of the transistor. these pins can be used by an external temperature sensor (such as adm 1021a or lm86, or others) to read the die temperature of the chip. the technique used by the extern al temperature sensor is to measure the change in v be when the thermal diode is operated at two different currents. this is shown in the following equation: where: n = multiplication factor clos e to 1, depending on process variations k = boltzmanns constant t = temperature (c) q = charge of the electron n = ratio of the two currents the two currents are usually in the range of 10 a to 300 a for the common temperature se nsor chips available. table 57 contains the thermal diod e specifications using the transistor model. note that me asured ideality factor already takes into effect variations in beta ( ? ). table 56. thermal characteristics for 324-lead csp_bga parameter condition typical unit ? ja airflow = 0 m/s 22.7 c/w ? jma airflow = 1 m/s 20.4 c/w ? jma airflow = 2 m/s 19.5 c/w ? jc 6.6 c/w ? jt airflow = 0 m/s 0.11 c/w ? jmt airflow = 1 m/s 0.19 c/w ? jmt airflow = 2 m/s 0.24 c/w ? v be n kt q ----- - in(n) ? ? = table 57. thermal diode parameterstransistor model 1 symbol parameter min typ max unit i fw 2 forward bias current 10 300 ? a i e emitter current 10 300 ? a n q 3, 4 transistor ideality 1.012 1.015 1.017 r t 4, 5 series resistance 0.12 0.2 0.28 ? 1 see the engineer-to-engineer note ee-346. 2 analog devices does not reco mmend operation of the the rmal diode under reverse bias. 3 not 100% tested. specified by design characterization. 4 the ideality factor, nq, represents the deviation from ideal diode behavior as exem plified by the diode equation: i c = i s (e qvbe/nqkt C1), where i s = saturation current, q = electronic charge, v be = voltage across the diode, k = boltzmann co nstant, and t = absolute temperature (kelvin). 5 the series resistance (r t ) can be used for more ac curate readings as needed. adsp-21469 rev. 0 | page 63 of 72 | june 2010 csp_bga ball assignmentautomotive models table 58 lists the automotive cs p_bga ball assignments by signal. table 58. csp_bga ball assignment (alphabetical by signal) signal ball no. signal ball no. signal ball no. signal ball no. agnd h02 clk_cfg1 g02 ddr2_cke e01 dpi_p09 n01 ami_ack r10 clkin l01 ddr2_clk0 a07 dpi_p10 n02 ami_addr0 v16 dai_p01 r06 ddr2_clk0 b07 dpi_p11 n03 ami_addr01 u16 dai_p02 v05 ddr2_clk1 a13 dpi_p12 n04 ami_addr02 t16 dai_p03 r07 ddr2_clk1 b13 dpi_p13 m03 ami_addr03 r16 dai_p04 r03 ddr2_cs0 c01 dpi_p14 m04 ami_addr04 v15 dai_p05 u05 ddr2_cs1 d01 emu k02 ami_addr05 u15 dai_p06 t05 ddr2_cs2 c02 flag0 r08 ami_addr06 t15 dai_p07 v06 ddr2_cs3 d02 flag1 v07 ami_addr07 r15 dai_p08 v02 ddr2_data0 b02 flag2 u07 ami_addr08 v14 dai_p09 r05 ddr2_data01 a02 flag3 t07 ami_addr09 u14 dai_p10 v04 ddr2_data02 b03 gnd a01 ami_addr10 t14 dai_p11 u04 ddr2_data03 a03 gnd a18 ami_addr11 r14 dai_p12 t04 ddr2_data04 b05 gnd c04 ami_addr12 v13 dai_p13 u06 ddr2_data05 a05 gnd c06 ami_addr13 u13 dai_p14 u02 ddr2_data06 b06 gnd c08 ami_addr14 t13 dai_p15 r04 ddr2_data07 a06 gnd d05 ami_addr15 r13 dai_p16 v03 ddr2_data08 b08 gnd d07 ami_addr16 v12 dai_p17 u03 ddr2_data09 a08 gnd d09 ami_addr17 u12 dai_p18 t03 ddr2_data10 b09 gnd d10 ami_addr18 t12 dai_p19 t06 ddr2_data11 a09 gnd d17 ami_addr19 r12 dai_p20 t02 ddr2_data12 a11 gnd e03 ami_addr20 v11 ddr2_addr0 d13 ddr2_data13 b11 gnd e05 ami_addr21 u11 ddr2_addr01 c13 ddr2_data14 a12 gnd e12 ami_addr22 t11 ddr2_addr02 d14 ddr2_data15 b12 gnd e13 ami_addr23 r11 ddr2_addr03 c14 ddr2_dm0 c03 gnd e16 ami_data0 u18 ddr2_addr04 b14 ddr2_dm1 c11 gnd f01 ami_data1 t18 ddr2_addr05 a14 ddr2_dqs0 a04 gnd f02 ami_data2 r18 ddr2_addr06 d15 ddr2_dqs0 b04 gnd f04 ami_data3 p18 ddr2_addr07 c15 ddr2_dqs1 a10 gnd f14 ami_data4 v17 ddr2_addr08 b15 ddr2_dqs1 b10 gnd f16 ami_data5 u17 ddr2_addr09 a15 ddr2_odt b01 gnd g03 ami_data6 t17 ddr2_addr10 d16 ddr2_ras c09 gnd g04 ami_data7 r17 ddr2_addr11 c16 ddr2_we c10 gnd g05 ami_ms0 t10 ddr2_addr12 b16 dpi_p01 r02 gnd g07 ami_ms1 u10 ddr2_addr13 a16 dpi_p02 u01 gnd g08 ami_rd j04 ddr2_addr14 b17 dpi_p03 t01 gnd g09 ami_wr v10 ddr2_addr15 a17 dpi_p04 r01 gnd g10 boot_cfg0 j02 ddr2_ba0 c18 dpi_p05 p01 gnd g11 boot_cfg1 j03 ddr2_ba1 c17 dpi_p06 p02 gnd g12 boot_cfg2 ho3 ddr2_ba2 b18 dpi_p07 p03 gnd g15 clk_cfg0 g01 ddr2_cas c07 dpi_p08 p04 gnd h04 rev. 0 | page 64 of 72 | june 2010 adsp-21469 gnd h07 gnd v01 v dd _ ddr 2 e04 v dd _ int f13 gnd h08 gnd v18 v dd _ ddr 2 e07 v dd _ int g06 gnd h09 lack_0 k17 v dd _ ddr 2 e10 v dd _ int g13 gnd h10 lack_1 p17 v dd _ ddr 2 e11 v dd _ int h05 gnd h11 lclk_0 j18 v dd _ ddr 2 e17 v dd _ int h06 gnd h12 lclk_1 n18 v dd _ ddr 2 f03 v dd _ int h13 gnd j01 ldat0_0 e18 v dd _ ddr 2 f05 v dd _ int h14 gnd j07 ldat0_1 f17 v dd _ ddr 2 f15 v dd _ int j06 gnd j08 ldat0_2 f18 v dd _ ddr 2 g14 v dd _ int j13 gnd j09 ldat0_3 g17 v dd _ ddr 2 g16 v dd _ int k06 gnd j10 ldat0_4 g18 v dd _ ext h15 v dd _ int k13 gnd j11 ldat0_5 h16 v dd _ ext h18 v dd _ int l06 gnd j12 ldat0_6 h17 v dd _ ext j05 v dd _ int l13 gnd j14 ldat0_7 j16 v dd _ ext j15 v dd _ int m06 gnd j17 ldat1_0 k18 v dd _ ext k14 v dd _ int m13 gnd k05 ldat1_1 l16 v dd _ ext l05 v dd _ int n06 gnd k07 ldat1_2 l17 v dd _ ext m14 v dd _ int n07 gnd k08 ldat1_3 l18 v dd _ ext m18 v dd _ int n08 gnd k09 ldat1_4 m16 v dd _ ext n05 v dd _ int n09 gnd k10 ldat1_5 m17 v dd _ ext p06 v dd _ int n13 gnd k11 ldat1_6 n16 v dd _ ext p08 v dd _ thd n10 gnd k12 ldat1_7 p16 v dd _ ext p10 v ref d04 gnd l07 mlbclk k03 v dd _ ext p12 v ref d11 gnd l08 mlbdat k04 v dd _ ext p14 xtal k01 gnd l09 mlbsig l02 v dd _ ext p15 gnd l10 mlbso l03 v dd _ ext t08 gnd l11 mlbdo l04 v dd _ ext t09 gnd l12 reset m01 v dd _ ext u08 gnd l14 resetout /runrstin m02 v dd _ ext u09 gnd m05 tck k15 v dd _ ext v08 gnd m07 tdi l15 v dd _ ext v09 gnd m08 tdo m15 v dd _ int d12 gnd m09 thd_m n12 v dd _ int e06 gnd m10 thd_p n11 v dd _ int e08 gnd m11 tms k16 v dd _ int e09 gnd m12 trst n15 v dd _ int e14 gnd n14 vdd_a h01 v dd _ int e15 gnd n17 v dd _ ddr 2 c05 v dd _ int f06 gnd p05 v dd _ ddr 2 c12 v dd _ int f07 gnd p07 v dd _ ddr 2 d03 v dd _ int f08 gnd p09 v dd _ ddr 2 d06 v dd _ int f09 gnd p11 v dd _ ddr 2 d08 v dd _ int f10 gnd p13 v dd _ ddr 2 d18 v dd _ int f11 gnd r09 v dd _ ddr 2 e02 v dd _ int f12 table 58. csp_bga ball assignment (alp habetical by signal) (continued) signal ball no. signal ball no. signal ball no. signal ball no. adsp-21469 rev. 0 | page 65 of 72 | june 2010 figure 58. ball configuration, automotive model 4 25 3 1 6 7 8 9 101112131415 17 16 18 a1 corner index area a b c d e f g h j k l m n p r t u v d r r r t t a s a s v dd_thd v ref v dd_ddr2 v dd_int v dd_ext gnd agnd v dd_a d d d d d d d d d d d d d d d d d i/o signals rev. 0 | page 66 of 72 | june 2010 adsp-21469 csp_bga ball assignmentstandard models table 59 lists the standard model csp_bga ball assignments by signal. table 59. csp_bga ball assignment (alphabetical by signal) signal ball no. signal ball no. signal ball no. signal ball no. agnd h02 clk_cfg1 g02 ddr2_cke e01 dpi_p09 n01 ami_ack r10 clkin l01 ddr2_clk0 a07 dpi_p10 n02 ami_addr0 v16 dai_p01 r06 ddr2_clk0 b07 dpi_p11 n03 ami_addr01 u16 dai_p02 v05 ddr2_clk1 a13 dpi_p12 n04 ami_addr02 t16 dai_p03 r07 ddr2_clk1 b13 dpi_p13 m03 ami_addr03 r16 dai_p04 r03 ddr2_cs0 c01 dpi_p14 m04 ami_addr04 v15 dai_p05 u05 ddr2_cs1 d01 emu k02 ami_addr05 u15 dai_p06 t05 ddr2_cs2 c02 flag0 r08 ami_addr06 t15 dai_p07 v06 ddr2_cs3 d02 flag1 v07 ami_addr07 r15 dai_p08 v02 ddr2_data0 b02 flag2 u07 ami_addr08 v14 dai_p09 r05 ddr2_data01 a02 flag3 t07 ami_addr09 u14 dai_p10 v04 ddr2_data02 b03 gnd a01 ami_addr10 t14 dai_p11 u04 ddr2_data03 a03 gnd a18 ami_addr11 r14 dai_p12 t04 ddr2_data04 b05 gnd c04 ami_addr12 v13 dai_p13 u06 ddr2_data05 a05 gnd c06 ami_addr13 u13 dai_p14 u02 ddr2_data06 b06 gnd c08 ami_addr14 t13 dai_p15 r04 ddr2_data07 a06 gnd d05 ami_addr15 r13 dai_p16 v03 ddr2_data08 b08 gnd d07 ami_addr16 v12 dai_p17 u03 ddr2_data09 a08 gnd d09 ami_addr17 u12 dai_p18 t03 ddr2_data10 b09 gnd d10 ami_addr18 t12 dai_p19 t06 ddr2_data11 a09 gnd d17 ami_addr19 r12 dai_p20 t02 ddr2_data12 a11 gnd e03 ami_addr20 v11 ddr2_addr0 d13 ddr2_data13 b11 gnd e05 ami_addr21 u11 ddr2_addr01 c13 ddr2_data14 a12 gnd e12 ami_addr22 t11 ddr2_addr02 d14 ddr2_data15 b12 gnd e13 ami_addr23 r11 ddr2_addr03 c14 ddr2_dm0 c03 gnd e16 ami_data0 u18 ddr2_addr04 b14 ddr2_dm1 c11 gnd f01 ami_data1 t18 ddr2_addr05 a14 ddr2_dqs0 a04 gnd f02 ami_data2 r18 ddr2_addr06 d15 ddr2_dqs0 b04 gnd f04 ami_data3 p18 ddr2_addr07 c15 ddr2_dqs1 a10 gnd f14 ami_data4 v17 ddr2_addr08 b15 ddr2_dqs1 b10 gnd f16 ami_data5 u17 ddr2_addr09 a15 ddr2_odt b01 gnd g03 ami_data6 t17 ddr2_addr10 d16 ddr2_ras c09 gnd g04 ami_data7 r17 ddr2_addr11 c16 ddr2_we c10 gnd g05 ami_ms0 t10 ddr2_addr12 b16 dpi_p01 r02 gnd g07 ami_ms1 u10 ddr2_addr13 a16 dpi_p02 u01 gnd g08 ami_rd j04 ddr2_addr14 b17 dpi_p03 t01 gnd g09 ami_wr v10 ddr2_addr15 a17 dpi_p04 r01 gnd g10 boot_cfg0 j02 ddr2_ba0 c18 dpi_p05 p01 gnd g11 boot_cfg1 j03 ddr2_ba1 c17 dpi_p06 p02 gnd g12 boot_cfg2 h03 ddr2_ba2 b18 dpi_p07 p03 gnd g15 clk_cfg0 g01 ddr2_cas c07 dpi_p08 p04 gnd h04 adsp-21469 rev. 0 | page 67 of 72 | june 2010 gnd h07 gnd v01 v dd _ ddr 2 e04 v dd _ int f13 gnd h08 gnd v18 v dd _ ddr 2 e07 v dd _ int g06 gnd h09 lack_0 k17 v dd _ ddr 2 e10 v dd _ int g13 gnd h10 lack_1 p17 v dd _ ddr 2 e11 v dd _ int h05 gnd h11 lclk_0 j18 v dd _ ddr 2 e17 v dd _ int h06 gnd h12 lclk_1 n18 v dd _ ddr 2 f03 v dd _ int h13 gnd j01 ldat0_0 e18 v dd _ ddr 2 f05 v dd _ int h14 gnd j07 ldat0_1 f17 v dd _ ddr 2 f15 v dd _ int j06 gnd j08 ldat0_2 f18 v dd _ ddr 2 g14 v dd _ int j13 gnd j09 ldat0_3 g17 v dd _ ddr 2 g16 v dd _ int k06 gnd j10 ldat0_4 g18 v dd _ ext h15 v dd _ int k13 gnd j11 ldat0_5 h16 v dd _ ext h18 v dd _ int l06 gnd j12 ldat0_6 h17 v dd _ ext j05 v dd _ int l13 gnd j14 ldat0_7 j16 v dd _ ext j15 v dd _ int m06 gnd j17 ldat1_0 k18 v dd _ ext k14 v dd _ int m13 gnd k05 ldat1_1 l16 v dd _ ext l05 v dd _ int n06 gnd k07 ldat1_2 l17 v dd _ ext m14 v dd _ int n07 gnd k08 ldat1_3 l18 v dd _ ext m18 v dd _ int n08 gnd k09 ldat1_4 m16 v dd _ ext n05 v dd _ int n09 gnd k10 ldat1_5 m17 v dd _ ext p06 v dd _ int n13 gnd k11 ldat1_6 n16 v dd _ ext p08 v dd _ thd n10 gnd k12 ldat1_7 p16 v dd _ ext p10 v ref d04 gnd l07 nc k03 v dd _ ext p12 v ref d11 gnd l08 nc k04 v dd _ ext p14 xtal k01 gnd l09 nc l02 v dd _ ext p15 gnd l10 nc l03 v dd _ ext t08 gnd l11 nc l04 v dd _ ext t09 gnd l12 reset m01 v dd _ ext u08 gnd l14 resetout /runrstin m02 v dd _ ext u09 gnd m05 tck k15 v dd _ ext v08 gnd m07 tdi l15 v dd _ ext v09 gnd m08 tdo m15 v dd _ int d12 gnd m09 thd_m n12 v dd _ int e06 gnd m10 thd_p n11 v dd _ int e08 gnd m11 tms k16 v dd _ int e09 gnd m12 trst n15 v dd _ int e14 gnd n14 vdd_a h01 v dd _ int e15 gnd n17 v dd _ ddr 2 c05 v dd _ int f06 gnd p05 v dd _ ddr 2 c12 v dd _ int f07 gnd p07 v dd _ ddr 2 d03 v dd _ int f08 gnd p09 v dd _ ddr 2 d06 v dd _ int f09 gnd p11 v dd _ ddr 2 d08 v dd _ int f10 gnd p13 v dd _ ddr 2 d18 v dd _ int f11 gnd r09 v dd _ ddr 2 e02 v dd _ int f12 table 59. csp_bga ball assignment (alp habetical by signal) (continued) signal ball no. signal ball no. signal ball no. signal ball no. rev. 0 | page 68 of 72 | june 2010 adsp-21469 figure 59. ball configuration, standard model 4 25 3 1 6 7 8 9 101112131415 17 16 18 a1 corner index area a b c d e f g h j k l m n p r t u v d r r r nc t t a s a s v dd_thd v ref v dd_ddr2 v dd_int v dd_ext gnd agnd v dd_a d d d d d d d d d d d d d d d d d i/o signals adsp-21469 rev. 0 | page 69 of 72 | june 2010 outline dimensions the adsp-21469 processor is avai lable in a 19 mm by 19 mm csp_bga lead-free package. surface-mount design the following table is provided as an aid to pcb design. for industry-standard desi gn recommendations, refer to ipc-7351, generic requirements for surfac e-mount design and land pat- tern standard . figure 60. 324-ball chip scale package, ball grid array [csp_bga] (bc-324-1) dimensions shown in millimeters * compliant to jedec standards mo-192-aag-1 with the exception to package height. 1.00 bsc 1.00 ref a b c d e f g 9 8 11 10 13 12 7 6 5 42 31 bottom view 17.00 bsc sq h j k l m n p r t u v 0.50 nom 0.45 min detail a top view detail a coplanarity 0.20 0.70 0.60 0.50 ball diameter seating plane 19.10 19.00 sq 18.90 a1 ball corner a1 ball corner * 1.80 1.71 1.56 1.31 1.21 1.11 15 14 17 16 18 package package ball attach type package solder mask opening package ball pad size 324-ball csp_bga (bc-324-1) solder mask defined 0.43 mm diameter 0.6 mm diameter rev. 0 | page 70 of 72 | june 2010 adsp-21469 automotive products the adsp-21469w model is avai lable with controlled manu- facturing to support the quality and reliability requirements of automotive applications. note that automotive models may have specifications that differ from commercial models and designers should review the specif ications section of this data sheet carefully. only the automotive grade products shown in table 60 are available for use in automotive applications. con- tact your local adi account repr esentative for specific product ordering information and to obtain the specific automotive reliability reports for these models. ordering guide table 60. automotive products model 1 temperature range 2 on-chip sram package description package option ad21469wbbcz3xx 3 C40c to +85c 5m bit 324-ball grid array (csp_bga) bc-324-1 1 z = rohs compliant part. 2 referenced temperature is ambient temperature. the am bient temperature is not a specification. please see operating conditions on page 17 for junction temperature (t j ) specification, which is the on ly temperature specification. 3 xx denotes silicon revision. model 1 1 z = rohs compliant part. temperature range 2 2 referenced temperature is ambient temperature. the ambie nt temperature is not a sp ecification. please see operating conditions on page 17 for junction temperature (t j ) specification, which is the on ly temperature specification. on-chip sram processor instruction rate (max) package description package option ADSP-21469KBCZ-3 0 ? c to +70 ? c 5m bit 400 mhz 324-ball grid array (csp_bga) bc-324-1 adsp-21469bbcz-3 C40 ? c to +85 ? c 5m bit 400 mhz 324-ball grid array (csp_bga) bc-324-1 adsp-21469kbcz-4 0 ? c to +70 ? c 5m bit 450 mhz 324-ball grid array (csp_bga) bc-324-1 adsp-21469 rev. 0 | page 71 of 72 | june 2010 rev. 0 | page 72 of 72 | june 2010 adsp-21469 ? 2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07900-0-6/10(0) |
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