? semiconductor components industries, llc, 2012 july, 2012 ? rev. 0 1 publication order number: nlsx4302e/d nlsx4302e 2-bit 20 mb/s dual-supply level translator the nlsx4302e is a 2 ? bit configurable dual ? supply bidirectional auto sensing translator that does not require a directional control pin. the v cc i/o and v l i/o ports are designed to track two different power supply rails, v cc and v l respectively. both the v cc and v l supply rails are configurable from 1.5 v to 5.5 v. this allows voltage logic signals on the v l side to be translated into lower, higher or equal value voltage logic signals on the v cc side, and vice ? versa. the nlsx4302e translator uses external pull ? up resistors on the i/o lines. the external pull ? up resistors are used to pull up the i/o lines to either v l or v cc . the nlsx4302e is an excellent match for open ? drain applications such as the i 2 c communication bus. features ? v l can be less than, greater than or equal to v cc ? wide v cc operating range: 1.5 v to 5.5 v wide v l operating range: 1.5 v to 5.5 v ? high ? speed with 20 mb/s guaranteed date rate ? low bit ? to ? bit skew ? enable input and i/o pins are overvoltage tolerant (ovt) to 5.5 v ? non ? preferential powerup sequencing ? power ? off protection ? small space saving package: 1.4 mm x 1.2 mm uqfn8 package ? these devices are pb ? free and are rohs compliant typical applications ? i 2 c, smbus ? low voltage asic level translation ? mobile phones, pdas, cameras important information ? esd protection for all pins ? human body model (hbm) > 6000 v ? machine model (mm) > 400 v marking diagrams http://onsemi.com uqfn8 mu suffix case 523as device package shipping ? ordering information NLSX4302EBMUTCG uqfn8 (pb ? free) 3000/tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd801 1/d. e = specific device code m = date code em 1 v l v cc gnd en i/o v l 1 i/o v l 2 i/o v cc 1 i/o v cc 2 logic diagram
nlsx4302e http://onsemi.com 2 figure 1. block diagram (1 i/o line) figure 2. pin ? out diagram uqfn8 (top through v iew) v cc i/o v cc 1 i/o v cc 2 en v l i/o v l 1 i/o v l 2 gnd 8 7 6 5 1 2 3 4 pin assignment pins description v cc v cc supply voltage v l v l supply voltage gnd ground en output enable, referenced to v l i/o v cc n i/o port, referenced to v cc i/o v l n i/o port, referenced to v l function table en operating mode l hi ? z h i/o buses connected
nlsx4302e http://onsemi.com 3 maximum ratings symbol parameter value condition unit v cc high ? side dc supply v oltage ? 0.3 to +7.0 v v l high ? side dc supply v oltage ? 0.3 to +7.0 v i/o v cc v cc ? referenced dc input/output v oltage ? 0.3 to (v cc + 0.3) v i/o v l v l ? referenced dc input/output v oltage ? 0.3 to (v l + 0.3) v v en enable control pin dc input v oltage ? 0.3 to +7.0 v i i/o_sc short ? circuit duration (i/o v l and i/o v cc to gnd) 40 continuous ma t stg storage t emperature ? 65 to +150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. recommended opera ting conditions symbol parameter min max unit v cc high ? side positive dc supply voltage 1.5 5.5 v v l high ? side positive dc supply v oltage 1.5 5.5 v v en enable control pin v oltage gnd 5.5 v v io_vcc i/o pin voltage (side referred to v cc ) gnd v cc v v io_vl i/o pin voltage (side referred to v l ) gnd v l v t/ v input transition rise and fall rate i/o v l ? or i/o v l ? ports, push ? pull driving control input 10 10 ns/v t a operating temperature range ? 40 +85 c
nlsx4302e http://onsemi.com 4 dc electrical characteristics (v l = 1.5 v to 5.5 v and v cc = 1.5 v to 5.5 v, unless otherwise specified) (note 1) ? 40 c to +85 c symbol parameter test conditions (note 2) v l (v) v cc (v) min typ max unit v ih_vl i/o high level i/o_vl data inputs i/o_vl n 1.65?5.50 1.65?5.50 v l ? 0.4 v control input en 1.65?5.50 1.65?5.50 v l x 0.7 v ih_vcc i/o high level i/o_vcc data inputs i/o_vcc n 1.65?5.50 1.65?5.50 v cc ? 0.4 v v il_vl i/o low level i/o_vl data inputs i/o_vl n 1.65?5.50 1.65?5.50 0.4 v control input en 1.65?5.50 1.65?5.50 v l x 0.3 v il_vcc i/o low level i/o_vcc data inputs i/o_vcc n 1.65?5.50 1.65?5.50 0.4 v v ol low level output voltage v il = 0.15 v, i ol = 6 ma 1.65?5.50 1.65?5.50 0.4 v i l input leakage current control input en, v in = v l or gnd 1.65?5.50 1.65?5.50 1 a i off power ? off leakage current i/o_vl n , i/o_vcc n v in or v o = 0 to 5.5 v 0 0 2 a i/o_vl n 0 5.50 i/o_vcc n 5.50 0 i oz tristate output mode leakage current (note 3) i/o_vl n , i/o_vcc n v o = 0 to 5.5 v, en = v il 5.50 5.50 2 a i/o_vl n v o = 0 to 5.5 v, en = don?t care 5.50 0 i/o_vcc n 0 5.50 i cc quiescent supply current, active mode (notes 4, 5) v l v in = v cci or gnd, i o = 0, en = v ih_vl 1.65?5.50 1.65?5.50 5.0 a v cc i ccz quiescent supply current, standby mode (notes 4, 5) v l v in = v cci or gnd, i o = 0, en = v il_vl 1.65?5.50 1.65?5.50 5.0 a v cc i cc_off quiescent supply current, power ? off (notes 3, 5) v l v in = 5.5 v or gnd, i o = 0, en = don?t care, i/o_vcc to i/o_vl 0 1.65?5.50 2.0 a 1.65?5.50 0 v cc v in = 5.5 v or gnd, i o = 0, en = don?t care, i/o_vl to i/o_vcc 1.65?5.50 0 0 1.65?5.50 1. typical values are for v l = +1.8 v, v cc = +3.3 v and t a = +25 c. 2. all units are production tested at t a = +25 c. limits over the operating temperature range are guaranteed by design. 3. ?don?t care? indicates any valid logic level. 4. v cci is the power supply associated with the input side. 5. reflects current per supply, v l or v cc .
nlsx4302e http://onsemi.com 5 dynamic output electrical characteristics output rise / fall times (output load: c l = 50 pf, r pu = 2.2 k , push/pull driver, t a = ? 40 c to +85 c) (note 6) symbol parameter v cco (note 7) unit 4.5 to 5.5 v 3.0 to 3.6 v 2.3 to 2.7 v 1.65 to 1.95 v typ typ typ typ t rise output rise time, i/o_vl n , i/o_vcc n 6.4 5 6.5 10.7 ns t fall output fall time, i/o_vl n , i/o_vcc n 10 9.5 8.6 9.5 ns 6. output rise and fall times guaranteed by design and are not production tested. 7. v cco is the v l or v cc power supply associated with the output side. maximum data rate (output load: c l = 50 pf, r pu = 2.2 k , push/pull driver, t a = ? 40 c to +85 c) (note 8) v l parameter v cc unit 4.5 to 5.5 v 3.0 to 3.6 v 2.3 to 2.7 v 1.65 to 1.95 v min min min min 4.5 to 5.5 v i/o_vl n ,to i/o_vcc n or i/o_vcc n to i/o_vl n 50 41 31 17 mhz 3.0 to 3.6 v 34 35 36 23 mhz 2.3 to 2.7 v 25 27 30 24 mhz 1.65 to 1.95 v 14 16 22 21 mhz 8. maximum frequency guaranteed by design and is not production tested.
nlsx4302e http://onsemi.com 6 ac electrical characteristics (output load: c l = 50 pf, r pu = 2.2 k , push/pull driver, t a = ? 40 c to +85 c) (note 9) symbol parameter v cc unit 4.5 to 5.5 v 3.0 to 3.6 v 2.3 to 2.7 v 1.65 to 1.95 v typ max typ max typ max typ max v l = 4.5 to 5.5 v t plh i/o_vl n to i/o_vcc n , i/o_vcc n to i/o_vl n 2.5 4.3 3 5 3 6.4 4 8.6 ns t phl i/o_vl n to i/o_vcc n , i/o_vcc n to i/o_vl n 5 8.1 8 13 8 17.3 15 28.5 ns t pzl oe to i/o_vl n , oe to i/o_vcc n 14 19.6 16 20 22 26.5 33 44 ns t plz oe to i/o_vl n , oe to i/o_vcc n 24 31.4 25 32 24 31.8 28 36.2 ns t skew i/o_vl n to i/o_vcc n , i/o_vcc n to i/o_vl n (note 10) 0.3 0.3 0.5 0.6 0.8 0.8 1.2 1.9 ns v l = 3.0 to 3.6 v t plh i/o_vl n to i/o_vcc n , i/o_vcc n to i/o_vl n 2.5 4.7 3 5.4 3 6.5 5 9.3 ns t phl i/o_vl n to i/o_vcc n , i/o_vcc n to i/o_vl n 7 14.2 6 10.1 8 14.6 15 27 ns t pzl oe to i/o_vl n , oe to i/o_vcc n 15 18.8 18 22.3 19 23.5 29 38.3 ns t plz oe to i/o_vl n , oe to i/o_vcc n 25 34.9 22 27.6 22 27.9 23 28.8 ns t skew i/o_vl n to i/o_vcc n , i/o_vcc n to i/o_vl n (note 10) 0.4 0.5 0.5 0.6 0.6 0.7 2.5 3.0 ns v l = 2.3 to 2.7 v t plh i/o_vl n to i/o_vcc n , i/o_vcc n to i/o_vl n 3 5.6 4 6 4 7.3 6 10.3 ns t phl i/o_vl n to i/o_vcc n , i/o_vcc n to i/o_vl n 12 18.1 11 14.1 8 11.9 15 22.1 ns t pzl oe to i/o_vl n , oe to i/o_vcc n 16 23.7 17 21.5 25 30 31 36.6 ns t plz oe to i/o_vl n , oe to i/o_vcc n 28 33.8 26 31 25 30.8 25 30 ns t skew i/o_vl n to i/o_vcc n , i/o_vcc n to i/o_vl n (note 10) 0.5 0.7 0.8 1 0.6 0.6 2.3 2.7 ns v l = 1.65 to 1.95 v t plh i/o_vl n to i/o_vcc n , i/o_vcc n to i/o_vl n 5 9 5 9.2 6 9.2 7 12.7 ns t phl i/o_vl n to i/o_vcc n , i/o_vcc n to i/o_vl n 19 28.3 15 25.5 12 17.3 14 19 ns t pzl oe to i/o_vl n , oe to i/o_vcc n 23 32.2 22 26.5 25 32 40 72 ns t plz oe to i/o_vl n , oe to i/o_vcc n 35 44 32 38.7 33 36.7 30 36.5 ns t skew i/o_vl n to i/o_vcc n , i/o_vcc n to i/o_vl n (note 10) 0.5 1.1 1.4 1.5 0.8 1.1 2.0 2.5 ns 9. ac characteristics are guaranteed by design and are not production tested. 10. skew is the variation of propagation delay between output signals and applies only to output signals on the same port (i/o_v l n or i/o_vcc n ) and switching with the same polarity (low ? to ? high or high ? to ? low). skew is defined by applying a single input to the two input channels and measuring the difference in propagation delays between the output channels.
nlsx4302e http://onsemi.com 7 capacitance (t a = 25 c) symbol parameter test condition typical unit c in input capacitance, control pin (en) v l = v cc = gnd 2 pf c io input / output capacitance (i/o_vl n , i/o_vcc n ) v l = v cc = 5 v,en = gnd, i/o_vl n = i/o_vcc n = 5 v 3 pf c pd power dissipation capacitance (note 11) v l = v cc = 5 v,en = 5 v, v in = 5 v or gnd, f = 400 khz 17 pf 11. c pd is defined as the value of the internal equivalent capacitance per channel. test setup and timing definitions figure 3. ac test circuit figure 4. propagation delays and tri-state measurements figure 5. definition of rise and fall times
nlsx4302e http://onsemi.com 8 figure 6. definition of output skew figure 7. definition of output tri-state times
nlsx4302e http://onsemi.com 9 applications information level translator architecture the nlsx4302e auto sense translator provides bi ? directional voltage level shifting to transfer data in multiple supply voltage systems. this device has two supply voltages, v l and v cc , which set the logic levels on the input and output sides of the translator. when used to transfer data from the v l to the v cc ports, input signals referenced to the v l supply are translated to output signals with a logic level matched to v cc . in a similar manner, the v cc to v l translation shifts input signals with a logic level compatible to v cc to an output signal matched to v l . the nlsx4302e consists of two bi ? directional channels that independently determine the direction of the data flow without requiring a directional pin. the one ? shot circuits are used to detect the rising or falling input signals. in addition, the one shots decrease the rise and fall time of the output signal for high ? to ? low and low ? to ? high transitions. each input/output channel requires external pullup resistors. enable input (en) the nlsx4302e has an enable pin (en) that can be used to minimize the power consumption of the device when the transmitter is not transmitting data. normal translation operation occurs when the en pin is equal to a logic high signal. the en pin is referenced to the v l supply and has overvoltage tolerant (ovt) protection. power supply guidelines the sequencing of the power supplies will not damage the device during the power up operation. in addition, the i/o v cc and i/o v l pins are in the high impedance state if either supply voltage is equal to 0 v. for optimal performance, 0.01 f to 0.1 f decoupling capacitors should be used on the v l and v cc power supply pins. ceramic capacitors are a good design choice to filter and bypass any noise signals on the voltage lines to the ground plane of the pcb. the noise immunity will be maximized by placing the capacitors as close as possible to the supply and ground pins, along with minimizing the pcb connection traces.
nlsx4302e http://onsemi.com 10 package dimensions uqfn8 1.4x1.2, 0.4p case 523as issue a ?? ?? a b e d bottom view b e 6x 0.10 b 0.05 a c c note 3 2x 0.10 c pin one reference top view 2x 0.10 c a a1 (a3) 0.05 c 0.05 c c seating plane side view l2 1 2 4 8 dim min max millimeters a 0.45 0.55 a1 0.00 0.05 a3 0.13 ref b 0.15 0.25 d 1.40 bsc l1 ??? 0.15 e 1.20 bsc e 0.40 bsc l 0.20 0.40 detail b detail a *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. soldering footprint* pitch 0.55 7x dimensions: millimeters 1 6 l 0.45 1.61 1.40 0.40 l2 0.30 0.50 0.25 8x l1 detail a l alternate constructions l ??? ??? ??? m m on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf . sc illc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circui t, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data she ets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for e ach customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designe d, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any o ther application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such u nintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this l iterature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 nlsx4302e/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc a sales representative
|
