? semiconductor components industries, llc, 2006 january, 2006 ? rev. 5 1 publication order number: mpf4392/d mpf4392, mpf4393 preferred devices jfet switching transistors n?channel ? depletion features ? pb?free packages are available* maximum ratings rating symbol value unit drain ?source voltage v ds 30 vdc drain ?gate voltag v dg 30 vdc gate?source voltage v gs 30 vdc forward gate current i g(f) 50 madc total device dissipation @ t a = 25 c derate above 25 c p d 350 2.8 mw mw/ c operating and storage channel temperature range t channel , t stg ?65 to +150 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. http://onsemi.com 2 source 3 gate 1 drain preferred devices are recommended choices for future use and best overall value. device package shipping ? ordering information mpf4392 to?92 1000 units / bulk mpf4392g to?92 (pb?free) 1000 units / bulk mpf4393 to?92 1000 units / bulk MPF4393G to?92 (pb?free) 1000 units / bulk mpf4393rlrp to?92 1000 / ammo box mpf4393rlrpg to?92 (pb?free) 1000 / ammo box to?92 (to?226aa) case 29?11 style 5 1 2 3 marking diagram mpf439x = device code x = 2 or 3 a = assembly location y = year ww = work week = pb?free package mpf 439x ayww (note: microdot may be in either location)
mpf4392, mpf4393 http://onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics gate ?source breakdown voltage (i g = 1.0 adc, v ds = 0) v (br)gss 30 ? ? vdc gate reverse current (v gs = 15 vdc, v ds = 0) (v gs = 15 vdc, v ds = 0, t a = 100 c) i gss ? ? ? ? 1.0 0.2 nadc adc drain?cutoff current (v ds = 15 vdc, v gs = 12 vdc) (v ds = 15 vdc, v gs = 12 vdc, t a = 100 c) i d(off) ? ? ? ? 1.0 0.1 nadc adc gate source voltage (v ds = 15 vdc, i d = 10 nadc) mpf4392 mpf4393 v gs ?2.0 ?0.5 ? ? ?5.0 ?3.0 vdc on characteristics zero ?gate ?voltage drain current (note 1) (v ds = 15 vdc, v gs = 0) mpf4392 mpf4393 i dss 25 5.0 ? ? 75 30 madc drain?source on?voltage (i d = 6.0 madc, v gs = 0) mpf4392 (i d = 3.0 madc, v gs = 0) mpf4393 v ds(on) ? ? ? ? 0.4 0.4 vdc static drain?source on resistance (i d = 1.0 madc, v gs = 0) mpf4392 mpf4393 r ds(on) ? ? ? ? 60 100 small? signal characteristics forward transfer admittance (v ds = 15 vdc, i d = 25 madc, f = 1.0 khz) mpf4392 (v ds = 15 vdc, i d = 5.0 madc, f = 1.0 khz) mpf4393 |y fs | ? ? 17 12 ? ? mmhos drain?source ?on? resistance (v gs = 0, i d = 0, f = 1.0 khz) mpf4392 mpf4393 r ds(on) ? ? ? ? 60 100 input capacitance (v gs = 15 vdc, v ds = 0, f = 1.0 mhz) c iss ? 6.0 10 pf reverse transfer capacitance (v gs = 12 vdc, v ds = 0, f = 1.0 mhz) (v ds = 15 vdc, i d = 10 madc, f = 1.0 mhz) c rss ? ? 2.5 3.2 3.5 ? pf switching characteristics rise time (see figure 2) (i d(on) = 6.0 madc) mpf4392 (i d(on) = 3.0 madc) mpf4393 t r ? ? 2.0 2.5 5.0 5.0 ns fall time (see figure 4) (v gs(off) = 7.0 vdc) mpf4392 (v gs(off) = 5.0 vdc) mpf4393 t f ? ? 15 29 20 35 ns turn?on time (see figures 1 and 2) (i d(on) = 6.0 madc) mpf4392 (i d(on) = 3.0 madc) mpf4393 t on ? ? 4.0 6.5 15 15 ns turn?off time (see figures 3 and 4) (v gs(off) = 7.0 vdc) mpf4392 (v gs(off) = 5.0 vdc) mpf4393 t off ? ? 20 37 35 55 ns 1. pulse test: pulse width 300 s, duty cycle 3.0%.
mpf4392, mpf4393 http://onsemi.com 3 figure 1. turn?on delay time figure 2. rise time figure 3. turn?off delay time figure 4. fall time typical switching characteristics i d , drain current (ma) , turn?on delay time (ns) d(on) t 5.0 2.0 20 10 0.5 1.0 3.0 7.0 5.0 1.0 50 100 0.7 2.0 10 20 , rise time (ns) r t , turn?off delay time (ns) d(off) t , fall time (ns) f t 30 50 200 500 1000 v gs(off) = 7.0 v = 5.0 v mpf4392 mpf4393 i d , drain current (ma) 5.0 2.0 20 10 0.5 1.0 3.0 7.0 5.0 1.0 50 100 0.7 2.0 10 20 30 50 200 500 1000 i d , drain current (ma) 5.0 2.0 20 10 0.5 1.0 3.0 7.0 5.0 1.0 50 100 0.7 2.0 10 20 30 50 200 500 1000 i d , drain current (ma) 5.0 2.0 20 10 0.5 1.0 3.0 7.0 5.0 1.0 50 100 0.7 2.0 10 20 30 50 200 500 1000 t j = 25 c t j = 25 c t j = 25 c t j = 25 c r k = r d r k = 0 r k = r d r k = 0 r k = r d r k = 0 r k = r d r k = 0 v gs(off) = 7.0 v = 5.0 v mpf4392 mpf4393 v gs(off) = 7.0 v = 5.0 v mpf4392 mpf4393 v gs(off) = 7.0 v = 5.0 v mpf4392 mpf4393
mpf4392, mpf4393 http://onsemi.com 4 figure 5. switching time test circuit 10 2.0 15 3.0 5.0 7.0 0.5 1.0 3.0 30 5.0 0.3 0.1 10 0.05 0.03 v r , reverse voltage (volts) c, capacitance (pf) 50 170 20 ?10 ?40 80 140 ?70 r 1.8 1.0 2.0 1.2 1.4 1.6 0.8 0.6 0.4 , drain?source on?state ds(on) resistance (normalized) t channel , channel temperature ( c) 1.5 1.0 110 v dd v gg r gg r t r gen 50 v gen r k r d output input 50 50 set v ds(off) = 10 v input pulse t r 0.25 ns t f 0.5 ns pulse width = 2.0 s duty cycle 2.0% r gg r k r d = r d (r t + 50) r d + r t + 50 figure 6. typical forward transfer admittance note 1 the switching characteristics shown above were measured using a test circuit similar to figure 5. at the beginning of the switching interval, the gate voltage is at gate supply voltage (?v gg ). the drain?source voltage (v ds ) is slightly lower than drain supply voltage (v dd ) due to the voltage divider. thus reverse transfer capacitance (c rss ) or gate?drain capacitance (c gd ) is charged to v gg + v ds . during the turn?on interval , gate?source capacitance (c gs ) discharges through the series combination of r gen and r k . c gd must discharge to v ds(on) through r g and r k in series with the parallel combination of effective load impedance (r d ) and drain?source resistance (r ds ). during the turn?off, this charge flow is reversed. predicting turn?on time is somewhat difficult as the channel resistance r ds is a function of the gate?source voltage. while c gs discharges, v gs approaches zero and r ds decreases. since c gd discharges through r ds , turn?on time is non?linear. during turn?off, the situation is reversed with r ds increasing as c gd charges. the above switching curves s how two impedance conditions: 1) r k is equal to r d which simulates the switching behavior of cascaded stages where the driving source impedance is normally the load impedance of the previous stage, and 2) r k = 0 (low impedance) the driving source impe dance is that of the generator. figure 7. typical capacitance i d , drain current (ma) 2.0 5.0 3.0 7.0 0.5 1.0 3.0 7.0 5.0 50 30 10 20 0.7 2.0 10 20 , forward transfer admittance (mmhos) fs y 80 120 160 200 1.0 3.0 5.0 2.0 v gs , gate?source voltage (volts) 4.0 0 40 6.0 7.0 8.0 0 r , drain?source on?state ds(on) resistance (ohms) t channel = 25 c (c ds is negligible) c gs t channel = 25 c v ds = 15 v figure 8. effect of gate?source voltage on drain?source resistance figure 9. effect of temperature on drain?source on?state resistance mpf4392 mpf4393 c gd i d = 1.0 ma v gs = 0 i dss = 10 ma 25 ma 50 ma 75 ma 100 ma 125 ma t channel = 25 c
mpf4392, mpf4393 http://onsemi.com 5 i dss , zero?gate voltage drain current (ma) , drain?source on?state ds(on) r 20 10 30 40 50 30 40 50 60 70 20 resistance (ohms) 0 10 0 1.0 2.0 3.0 4.0 5.0 , gate?source voltage gs v (volts) 6.0 7.0 8.0 9.0 10 70 60 80 90 100 80 90 100 110 120 130 140 150 note 2 the zero?gate?voltage drain current (i dss ), is the principle determinant of other j?fet characteristics . figure 10 shows the relationship of gate?source of f voltage (v gs(off) ) and drain?source on resistance (r ds(on) ) to i dss . most of the devices will be within 10% of the values shown in figure 10. this data will be usefu l in predicting the characteristic variations for a given par t number. for example: unknown r ds(on) and v gs range for an mpf4392 the electrical characteristics table indicates that an mpf4392 has an i dss range of 25 to 75 ma. figure 10 shows r ds(on) = 52 for i dss = 25 ma and 30 for i dss 75 ma. the corresponding v gs values are 2.2 v and 4.8 v. figure 10. effect of i dss on drain?source resistance and gate?source voltage t channel = 25 c r ds(on) @ v gs = 0 v gs(off)
mpf4392, mpf4393 http://onsemi.com 6 package dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. contour of package beyond dimension r is uncontrolled. 4. lead dimension is uncontrolled in p and beyond dimension k minimum. r a p j l b k g h section x?x c v d n n xx seating plane dim min max min max millimeters inches a 0.175 0.205 4.45 5.20 b 0.170 0.210 4.32 5.33 c 0.125 0.165 3.18 4.19 d 0.016 0.021 0.407 0.533 g 0.045 0.055 1.15 1.39 h 0.095 0.105 2.42 2.66 j 0.015 0.020 0.39 0.50 k 0.500 ??? 12.70 ??? l 0.250 ??? 6.35 ??? n 0.080 0.105 2.04 2.66 p ??? 0.100 ??? 2.54 r 0.115 ??? 2.93 ??? v 0.135 ??? 3.43 ??? 1 style 5: pin 1. drain 2. source 3. gate to?92 (to?226) case 29?11 issue al on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 mpf4392/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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