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ic41uv4105 integrated circuit solution inc. 1 dr020-0b 08/24/2001 document title 1mx4 bit dynamic ram with fast page mode revision history revision no history draft date remark 0a initial draft august 9,2001 preliminary 0b 1.change for v cc 2.6 0.3 to 2.6 0.2v august 24,2001 the attached datasheets are provided by icsi. integrated circuit solution inc reserve the right to change the specifications a nd products. icsi will answer to your questions about device. if you have any questions, please contact the icsi offices.
features ? fast page mode access cycle ? ttl compatible inputs and outputs ? refresh interval: -- 1,024 cycles/16 ms ? refresh mode: ras -only, cas -before- ras (cbr), and hidden ? jedec standard pinout ? single power supply: 2.6v 0.2v description the icsi 4105 series is a 1,048,576 x 4-bit high-performance cmos dynamic random access memory. the fast page mode allows 1,024 random accesses within a single row with access cycle time as short as 20 ns per 4-bit word. these features make the 4105 series ideally suited for high- bandwidth graphics, digital signal processing, high-performance computing systems, and peripheral applications. the 4105 series is packaged in a 20-pin 300mil soj and a 20 pin tsop-2 ic41uv4105 1m x 4 (4 ? mbit) dynamic ram with fast page mode integrated circuit solution inc. 2 dr020-0a 08/09/2001 key timing parameters parameter - 50 -70 - 100 unit ras access time (t rac ) 50 70 100 ns cas access time (t cac )142025ns column address access time (t aa )25 35 50 ns fast page mode cycle time (t pc )204560ns read/write cycle time (t rc ) 90 130 180 ns icsi reserves the right to make changes to its products at any time without notice in order to improve design and supply the be st possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 2000, integrated circuit solution inc. pin descriptions a0-a9 address inputs i/o0-3 data inputs/outputs we write enable oe output enable ras row address strobe cas column address strobe vcc power gnd ground pin configuration 20 (26) pin soj, tsop - 2 1 2 3 4 5 9 10 11 12 13 26 25 24 23 22 18 17 16 15 14 i/o0 i/o1 we ras a9 a0 a1 a2 a3 vcc gnd i/o3 i/o2 cas oe a8 a7 a6 a5 a4
ic41uv4105 integrated circuit solution inc. 3 dr020-0b 08/24/2001 functional block diagram truth table function ras ras ras ras ras cas cas cas cas cas we we we we we oe oe oe oe oe address t r /t c i/o standby h h x x x high-z read l l h l row/col d out write: word (early write) l l l x row/col d in read-write l l h ll h row/col d out , d in hidden refresh read l h l l h l row/col d out write (1) l h l l l x row/col d out ras -only refresh l h x x row/na high-z cbr refresh h l l x x x high-z note: 1. early write only. oe we cas cas we oe data i/o bus column decoders sense amplifiers memory array 1,048,576 x 4 row decoder data i/o buffers cas control logic we control logics oe control logic i/o0-i/o3 ras ras a0-a9 ras clock generator refresh counter address buffers
ic41uv4105 4 integrated circuit solution inc. dr020-0b 08/24/2001 functional description the ic41uv4105 are cmos drams optimized for high- speed bandwidth, low power applications. during read or write cycles, each bit is uniquely addressed through the 10 address bits. these are entered 10 bits (a0-a9) at a time. the row address is latched by the row address strobe ( ras ). the column address is latched by the column address strobe ( cas ). ras is used to latch the first ten bits and cas is used the latter ten bits. memory cycle a memory cycle is initiated by bring ras low and it is terminated by returning both ras and cas high. to ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum t ras time has expired. a new cycle must not be initiated until the minimum precharge time t rp , t cp has elapsed. read cycle a read cycle is initiated by the falling edge of cas or oe , whichever occurs last, while holding we high. the column address must be held for a minimum time specified by t ar . data out becomes valid only when t rac , t aa , t cac and t oe are all satisfied. as a result, the access time is dependent on the timing relationships between these parameters. write cycle a write cycle is initiated by the falling edge of cas and we , whichever occurs last. the input data must be valid at or before the falling edge of cas or we , whichever occurs last. refresh cycle to retain data, 1,024 refresh cycles are required in each 16 ms period . there are two ways to refresh the memory: 1. by clocking each of the 1,024 row addresses (a0 through a9) with ras at least once every 16 ms . any read, write, read-modify-write or ras-only cycle re- freshes the addressed row. 2. using a cas -before- ras refresh cycle. cas -before- ras refresh is activated by the falling edge of ras , while holding cas low. in cas -before- ras refresh cycle, an internal 10-bit counter provides the row ad- dresses and the external address inputs are ignored. cas -before- ras is a refresh-only mode and no data access or device selection is allowed. thus, the output remains in the high-z state during the cycle. power - on after application of the v cc supply, an initial pause of 200 s is required followed by a minimum of eight initial- ization cycles (any combination of cycles containing a ras signal). during power-on, it is recommended that ras track with v cc or be held at a valid v ih to avoid current surges.
ic41uv4105 integrated circuit solution inc. 5 dr020-0b 08/24/2001 absolute maximum ratings (1) symbol parameters rating unit v t voltage on any pin relative to gnd ? 0.5 to +3.4 v v cc supply voltage ? 0.5 to +3.4 v i out output current 50 ma p d power dissipation 1 w t a commercial operation temperature 0 to +70 o c t stg storage temperature ? 55 to +125 o c note: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. recommended operating conditions (voltages are referenced to gnd.) symbol parameter min. typ. max. unit v cc supply voltage 2.4 2.6 2.8 v v ih input high voltage 1.8 ? v cc + 0.3 v v il input low voltage ? 0.3 ? 0.6 v t a commercial ambient temperature 0 ? 70 o c capacitance (1,2) symbol parameter max. unit c in 1 input capacitance: a0-a9 5 pf c in 2 input capacitance: ras , cas , we , oe 7pf c io data input/output capacitance: i/o0-i/o3 7 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25 o c, f = 1 mhz.
ic41uv4105 6 integrated circuit solution inc. dr020-0b 08/24/2001 electrical characteristics (1) (recommended operating conditions unless otherwise noted.) symbol parameter test condition speed min. max. unit i il input leakage current any input 0v v in vcc ? 55a other inputs not under test = 0v i io output leakage current output is disabled (hi-z) ? 55a 0v v out vcc v oh output high voltage level i oh = ? 2.0 ma 2.0 ? v v ol output low voltage level i ol = 2 ma ? 0.8 v i cc 1 standby current: ttl ras , cas v ih ? 1ma i cc 2 standby current: cmos ras , cas v cc ? 0.2v 0.5 ma i cc 3 operating current: ras , cas , -50 ? 75 ma random read/write (2,3,4) address cycling, t rc = t rc (min.) -70 ? 65 average power supply current -100 ? 55 i cc 4 operating current: ras = v il , cas v ih -50 ? 60 ma fast page mode (2,3,4) t rc = t rc (min.) -70 ? 50 average power supply current -100 ? 40 i cc 5 refresh current: ras cycling, cas v ih -50 ? 75 ma ras -only (2,3) t rc = t rc (min.) -70 ? 65 average power supply current -100 ? 55 i cc 6 refresh current: ras , cas cycling -50 ? 75 ma cbr (2,3,5) t rc = t rc (min.) -70 ? 65 average power supply current -100 ? 55 notes: 1. an initial pause of 200 s is required after power-up followed by eight ras refresh cycles ( ras -only or cbr) before proper device operation is assured. the eight ras cycles wake-up should be repeated any time the t ref refresh requirement is exceeded. 2. dependent on cycle rates. 3. specified values are obtained with minimum cycle time and the output open. 4. column-address is changed once each fast page cycle. 5. enables on-chip refresh and address counters.
ic41uv4105 integrated circuit solution inc. 7 dr020-0b 08/24/2001 ac characteristics (1,2,3,4,5,6) (recommended operating conditions unless otherwise noted.) - 50 - 70 - 100 symbol parameter min. max. min. max. min. max. units t rc random read or write cycle time 90 ? 130 ? 180 ? ns t rac access time from ras (6, 7) ? 50 ? 70 ? 100 ns t cac access time from cas (6, 8, 15) ? 14 ? 20 ? 25 ns t aa access time from column-address (6) ? 25 ? 35 ? 50 ns t ras ras pulse width 50 10k 70 10k 100 10k ns t rp ras precharge time 30 ? 50 ? 70 ? ns t cas cas pulse width (23) 8 10k 20 10k 25 10k ns t cp cas precharge time (9) 8 ? 10 ? 10 ? ns t csh cas hold time (21) 50 ? 70 ? 100 ? ns t rcd ras to cas delay time (10, 20) 19 36 20 50 25 75 ns t asr row-address setup time 0 ? 0 ? 0 ? ns t rah row-address hold time 8 ? 10 ? 15 ? ns t asc column-address setup time (20) 0 ? 0 ? 0 ? ns t cah column-address hold time (20) 8 ? 15 ? 20 ? ns t ar column-address hold time 40 ? 70 ? 100 ? ns (referenced to ras ) t rad ras to column-address delay time (11) 14 25 15 35 20 50 ns t ral column-address to ras lead time 25 ? 35 ? 50 ? ns t rpc ras to cas precharge time 0 ? 5 ? 5 ? ns t rsh ras hold time 14 ? 20 ? 25 ? ns t clz cas to output in low-z (15, 24) 3 ? 3 ? 3 ? ns t crp cas to ras precharge time (21) 5 ? 5 ? 5 ? ns t od output disable time (19, 24) 315 320325ns t oe output enable time (15, 16) ? 15 - 20 - 25 ns t oes oe low to cas high setup time 5 ? 5 ? 5 ? ns t rcs read command setup time (17, 20) 0 ? 0 ? 0 ? ns t rrh read command hold time 0 ? 0 ? 0 ? ns (referenced to ras ) (12) t rch read command hold time 0 ? 0 ? 0 ? ns (referenced to cas ) (12, 17, 21) t wch write command hold time (17) 8 ? 10 ? 15 ? ns t wcr write command hold time 40 ? 70 ? 100 ? ns (referenced to ras ) (17) t wp write command pulse width (17) 8 ? 10 ? 15 ? ns t rwl write command to ras lead time (17) 14 ? 20 ? 25 ? ns t cwl write command to cas lead time (17, 21) 14 ? 20 ? 25 ? ns t wcs write command setup time (14, 17, 20) 0 ? 0 ? 0 ? ns t dhr data-in hold time (referenced to ras )40 ? 50 ? 60 ? ns
ic41uv4105 8 integrated circuit solution inc. dr020-0b 08/24/2001 ac characteristics (continued) (1,2,3,4,5,6) (recommended operating conditions unless otherwise noted.) -50 - 70 - 100 symbol parameter min. max. min. max. min. max. units t ach column-address setup time to cas 15 ? 15 ? 15 ? ns precharge during write cycle t oeh oe hold time from we during 10 ? 20 ? 25 ? ns read-modify-write cycle (18) t ds data-in setup time (15, 22) 0 ? 0 ? 0 ? ns t dh data-in hold time (15, 22) 8 ? 15 ? 20 ? ns t rwc read-modify-write cycle time 125 ? 185 ? 240 ? ns t rwd ras to we delay time during 70 ? 100 ? 130 ? ns read-modify-write cycle (14) t cwd cas to we delay time (14, 20) 34 ? 45 ? 55 ? ns t awd column-address to we delay time (14) 42 ? 60 ? 85 ? ns t pc fast page mode read or write 20 ? 45 ? 60 ? ns cycle time t rasp fast page mode ras pulse width 50 100k 70 100k 100 100k ns t cpa access time from cas precharge (15) -27-40-55ns t prwc fast page mode read write 47 ? 100 ? 120 ? ns cycle time t off output buffer turn-off delay from 3 15 3 15 3 15 ns cas or ras (13,15,19, 24) t csr cas setup time (cbr refresh) (20, 25) 5 ? 5 ? 5 ? ns t chr cas hold time (cbr refresh) ( 21, 25) 10 ? 10 ? 10 ? ns t ord oe setup time prior to ras during 0 ? 0 ? 0 ? ns hidden refresh cycle t ref auto refresh period 1,024 cycles ? 16 ? 16 ? 16 ms t t transition time (rise or fall) (2, 3) 350350350ns ac test conditions output load: one ttl load and 100 pf input timing reference levels: v ih = 1.8v, v il = 0.6v output timing reference levels: v oh = 1.6v, v ol = 0.6v
ic41uv4105 integrated circuit solution inc. 9 dr020-0b 08/24/2001 notes: 1. an initial pause of 200 s is required after power-up followed by eight ras refresh cycle ( ras -only or cbr) before proper device operation is assured. the eight ras cycles wake-up should be repeated any time the t ref refresh requirement is exceeded. 2. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times, are measured between v ih and v il (or between v il and v ih ) and assume to be 1 ns for all inputs. 3. in addition to meeting the transition rate specification, all input signals must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 4. if cas and ras = v ih , data output is high-z. 5. if cas = v il , data output may contain data from the last valid read cycle. 6. measured with a load equivalent to one ttl gate and 100 pf. 7. assumes that t rcd t rcd (max). if t rcd is greater than the maximum recommended value shown in this table, t rac will increase by the amount that t rcd exceeds the value shown. 8. assumes that t rcd t rcd (max). 9. if cas is low at the falling edge of ras , data out will be maintained from the previous cycle. to initiate a new cycle and clear the data output buffer, cas and ras must be pulsed for t cp . 10. operation with the t rcd (max) limit ensures that t rac (max) can be met. t rcd (max) is specified as a reference point only; if t rcd is greater than the specified t rcd (max) limit, access time is controlled exclusively by t cac . 11. operation within the t rad (max) limit ensures that t rcd (max) can be met. t rad (max) is specified as a reference point only; if t rad is greater than the specified t rad (max) limit, access time is controlled exclusively by t aa . 12. either t rch or t rrh must be satisfied for a read cycle. 13. t off (max) defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . 14. t wcs , t rwd , t awd and t cwd are restrictive operating parameters in late write and read-modify-write cycle only. if t wcs t wcs (min), the cycle is an early write cycle and the data output will remain open circuit throughout the entire cycle. if t rwd t rwd (min), t awd t awd (min) and t cwd t cwd (min), the cycle is a read-write cycle and the data output will contain data read from the selected cell. if neither of the above conditions is met, the state of i/o (at access time and until cas and ras or oe go back to v ih ) is indeterminate. oe held high and we taken low after cas goes low result in a late write ( oe -controlled) cycle. 15. output parameter (i/o) is referenced to corresponding cas input. 16. during a read cycle, if oe is low then taken high before cas goes high, i/o goes open. if oe is tied permanently low, a late write or read-modify-write is not possible. 17. write command is defined as we going low. 18. late write and read-modify-write cycles must have both t od and t oeh met ( oe high during write cycle) in order to ensure that the output buffers will be open during the write cycle. the i/os will provide the previously written data if cas remains low and oe is taken back to low after t oeh is met. 19. the i/os are in open during read cycles once t od or t off occur. 20. determined by falling edge of cas . 21. determined by rising edge of cas . 22. these parameters are referenced to cas leading edge in early write cycles and we leading edge in late write or read- modify-write cycles. 23. cas must meet minimum pulse width. 24. the 3 ns minimum is a parameter guaranteed by design. 25. enables on-chip refresh and address counters.
ic41uv4105 10 integrated circuit solution inc. dr020-0b 08/24/2001 don?t care read cycle note: 1. t off is referenced from rising edge of ras or cas , whichever occurs last. t ras t rc t rp t ar t cah t asc t rad t ral oe i/o we address cas ras row column row open open valid data t csh t cas t rsh t crp t rcd t rah t asr t rrh t rch t rcs t aa t cac t off (1) t rac t clz t oes t oe t od
ic41uv4105 integrated circuit solution inc. 11 dr020-0b 08/24/2001 read write cycle (late write and read-modify-write cycles) don ? t care t ras t rwc t rp t ar t cah t asc t rad t ral t ach we oe address cas ras row column row t csh t cas t rsh t crp t rcd t rah t asr t rwd t cwl t cwd t rwl t awd t wp t rcs t cac t clz t ds t dh t oeh t od t oe t rac t aa i/o open open valid d out valid d in
ic41uv4105 12 integrated circuit solution inc. dr020-0b 08/24/2001 early write cycle ( oe = don't care) don ? t care t ras t rc t rp t ar t cah t asc t rad t ral t ach i/o we address cas ras row column row t csh t cas t rsh t crp t rcd t rah t asr t cwl t wcr t wch t rwl t wp t wcs t dh t ds t dhr valid data
ic41uv4105 integrated circuit solution inc. 13 dr020-0b 08/24/2001 fast page mode read cycle don ? t care out t ar i/o we oe address cas ras row column column column t ar t csh t cas t cas t cas t rasp t rsh t pc t rcd t crp t asr t rad t rcs t asc t asc t asc t ral t cah t cp t cp t rp t cah t cac t aa t clz t rac t oe t clz t cac t oe t cac t oe out out t od t od t od t clz t aa t aa t rah t cah t crp t cpa t cpa
ic41uv4105 14 integrated circuit solution inc. dr020-0b 08/24/2001 fast page mode early write cycle don ? t care t ar i/o we oe address cas ras row column column column t ar t cwl t wcr t dhr t csh t cas t cas t cas t rasp t rsh t pc t rcd t crp t asr t wcs t ds t rad t asc t asc t asc t ral t cah t wch t dh t ds t ds t dh t dh t cp t cp t rp t cah t rah t cah t crp t cwl t wcs t wcs t wch t wp t wp t rwl t wch t wp valid d in valid d in valid d in
ic41uv4105 integrated circuit solution inc. 15 dr020-0b 08/24/2001 ras ras ras ras ras - only refresh cycle ( oe , we = don't care) t ras t rc t rp i/o address cas ras row row open t crp t rah t asr t rpc don ? t care fast page mode read write cycle ( late write and read-modify-write cycle ) don ? t care out t ar t rwd t awd i/o we oe address cas ras row column column column t ar t csh t cas t cas t cas t rasp t rsh t prwc t rcd t cwd t cwd t cwd t crp t asr t rad t rcs t asc t asc t asc t ral t cah t cp t cp t rp t cah t awd t awd t cac t aa t dh t clz t rac t dh t dh t oe t clz t cac t oe t cac t oe out out in in in t od t od t ds t od t ds t clz t aa t aa t wp t rah t wp t wp t cwl t cwl t cwl t rwl t cah t crp t ds
ic41uv4105 16 integrated circuit solution inc. dr020-0b 08/24/2001 hidden refresh cycle (1) ( we = high; oe = low) cbr refresh cycle (addresses; we , oe = don't care) t ras t ras t rp t rp i/o cas ras open t cp t rpc t csr t chr t rpc t csr t chr t ras t ras t rp cas ras t crp t rcd t rsh t chr t ar t asc t rad address row column t rah t asr t ral t cah i/o open open valid data t aa t cac t rac t clz t off (2) oe t oe t ord t od don ? t care don ? t care notes: 1. a hidden refresh may also be performed after a write cycle. in this case, we = low and oe = high. 2. t off is referenced from rising edge of ras or cas , whichever occurs last.
ic41uv4105 integrated circuit solution inc. 17 dr020-0b 08/24/2001 ordering information commercial range: 0 c to 70 c voltage: 2.6v speed (ns) order part no. package 50 IC41UV4105-50J 300mil soj 50 ic41uv4105-50t 300mil tsop-2 70 ic41uv4105-70j 300mil soj 70 ic41uv4105-70t 300mil tsop-2 100 ic41uv4105-100j 300mil soj 100 ic41uv4105-100t 300mil tsop-2 integrated circuit solution inc. headquarter: no.2, technology rd. v, science-based industrial park, hsin-chu, taiwan, r.o.c. tel: 886-3-5780333 fax: 886-3-5783000 branch office: 7f, no. 106, sec. 1, hsin-tai 5 th road, hsichih taipei county, taiwan, r.o.c. tel: 886-2-26962140 fax: 886-2-26962252 http://www.icsi.com.tw

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