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1230 HD61602/hd61603 (segment type lcd driver) description the HD61602 and the hd61603 are liquid crystal display driver lsis with a ttl and c mos comp atible interface. each of the lsis can be connected to various microprocessors. the HD61602 incorporates the power supply circuit for the liquid crystal display driver. using the software-controlled liquid crystal driving method, several types of liquid crystals can be connected according to the applications. the hd61603 is a liquid crystal display driver lsi only for static drive and has 64 segment outputs that can display 8 digits per chip. features wide-range operating voltage ? operates in a wide range of supply voltage: 2.2v to 5.5v ? compatible with ttl interface at 4.5v to 5.5v low current consumption ? can run from a battery power supply (100 a max. at 5 v) ? standby input enables standby operation at lower current consumption (5 a max. on 5v) internal power supply circuit for liquid crystal display driver (HD61602) ? internal power supply circuit for liquid crystal display driver facilitates the connection to a microprocessor system
HD61602/hd61603 1231 ordering information type no. package HD61602r 80-pin plastic qfp (fp-80) HD61602rh 80-pin plastic qfp (fp-80a) hd61603r 80-pin plastic qfp (fp-80) versatile segment driving capacity type no. driving method display segments example of use frame freq. (hz) at f osc = 100 khz package HD61602 static 51 8 segments 6 digits + 3 marks 33 80-pin plastic 1/2 bias 1/2 duty 102 8 segments 12 digits + 6 marks 65 qfp (fp-80, 1/3 bias 1/3 duty 153 9 segments 17 digits 208 fp-80a, 1/4 duty 204 8 segments 25 digits + 4 marks 223 tfp-80) hd61603 static 64 8 segments 8 digits 33 80-pin plastic qfp (fp-80)
HD61602/hd61603 1232 pin arrangement 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 ready vdd osc1 osc2 sync seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 cs we re sb d7 d6 d5 d4 vss d3 d2 d1 d0 vref1 vref2 vc2 vc1 v1 v2 v3 com0 com1 com2 com3 seg50 seg49 seg48 seg47 seg46 seg45 seg44 seg43 seg42 seg41 seg40 seg39 seg38 seg37 seg36 seg35 (fp-80a) (top view) HD61602rh 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 osc1 osc2 sync seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 vdd ready cs we re sb d3 d2 d1 d0 vss v3 com0 seg63 seg62 seg61 seg60 seg59 seg58 seg57 seg56 seg55 seg54 seg53 seg52 seg51 seg50 seg49 seg48 seg47 seg46 seg45 seg44 seg43 seg42 seg41 seg40 seg39 seg38 seg37 (fp-80) hd61603r 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 osc1 osc2 sync seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 vdd ready cs we re sb d7 d6 d5 d4 vss d3 d2 d1 d0 vref1 vref2 vc2 vc2 v1 v2 v3 com0 com1 com2 com3 seg50 seg49 seg48 seg47 seg46 seg45 seg44 seg43 seg42 seg41 seg40 seg39 seg38 seg37 (fp-80) HD61602r
HD61602/hd61603 1233 block diagram sync HD61602 osc data controller data latch 8 bits 2 mode setting latch operation mode lcd driving voltage generator ready cs we re d0?7 sb lcd driving timing generator ram write timing generator parallel/serial converter address decoder driving voltage selection v1 v2 v3 display data ram segment driver common driver common output (4 lines) segment output (51 lines) sync hd61603 osc data controller data latch 4 bits 4 mode setting latch ready cs we re d0?3 sb lcd driving timing generator ram write timing generator parallel/serial converter address decoder display data ram segment driver common driver common output segment output (64 lines) to vdd v3
HD61602/hd61603 1234 terminal functions HD61602 terminal functions terminal name no. of lines input/output connected to function vdd 1 power supply positive power supply. ready 1 nmos open drain output mcu while data is being set in the display data ram and mode setting latch in the lsi after data transfer, low is output from the ready terminal to inhibit the next data input. there are two modes: one in which low is output only when both of &6 and 5( are low, and the other in which low is output regardless of &6 and 5( . &6 1 input mcu chip select input. data can be written only when this terminal is low. :( 1 input mcu write enable input. input data of d0 to d7 is latched at the rising edge of :( . 5( 1 input mcu resets the input data byte counter. after both &6 and 5( are low, the first data is recognized as the 1st byte data. sb 1 input mcu high level input stops lsi operations. 1. stops oscillation and clock input. 2. stops lcd driver. 3. stops writing data into display ram. d0Cd7 8 input mcu data input terminal for 8-bit 2-byte data. vss 1 power supply negative power supply. vref1 1 output external r reference voltage output. generates lcd driving voltage. vref2 1 input external r divides the reference voltage of vref1 with external r to determine lcd driving voltage. vref2 ? v1. vc1, vc2 2 output external c connection terminals for boosting c of lcd driving voltage generator. an external c is connected between vc1 and vc2. v1, v2, v3 3 output (input) external c lcd driving voltage outputs. an external c is connected to each terminal. com0Ccom3 4 output lcd lcd common (backplate) driving output. seg0Cseg50 51 output lcd lcd segment driving output. sync 1 input mcu synchronous input for 2 or more chips applications. lcd driver timing circuit is reset by high input. lcd is off. osc1 osc2 2 input output external r attach external r to these terminals for oscillation. an external clock (100 khz) can be input to osc1. note: logic polarity is positive. 1 = high = active.
HD61602/hd61603 1235 hd61603 terminal functions terminal name no. of lines input/output connected to function vdd 1 power supply positive power supply. ready 1 nmos open drain output mcu while data is being set in the display data ram and mode setting latch in the lsi after data transfer, low is output from the ready terminal to inhibit the next data input. there are two modes: one in which low is output only when both of &6 and 5( are low, and the other in which low is output regardless of &6 and 5( . &6 1 input mcu chip select input. data can be written only when this terminal is low. :( 1 input mcu write enable input. input data of d0 to d3 is latched at the rising edge of :( . 5( 1 input mcu resets the input data byte counter. after both of &6 and 5( are low, the first data is recognized as the 1st byte data. sb 1 input mcu high level input stops the lsi operations. 1. stops oscillation and clock input. 2. stops lcd driver. 3. stops writing data into display ram. d0Cd3 4 input mcu data input terminal from where 4-bit 4 data are input. vss 1 power supply negative power supply. v3 1 input power supply power supply input for lcd drive. voltage between vdd and v3 is used as driving voltage. com0 1 output lcd lcd common (backplate) driving output. seg0Cseg63 64 output lcd lcd segment driving output. sync 1 input mcu synchronous input for 2 or more chips applications. lcd driver timing circuit is reset by high input. lcd is off. osc1 osc2 2 input output external r attach external r to these terminals for oscillation. an external clock (100 khz) can be input to osc 1 . note: logic polarity is positive. 1 = high = active.
HD61602/hd61603 1236 display ram HD61602 display ram the HD61602 has an internal display ram shown in figure 1. display data is stored in the ram, or is read according to the lcd driving timing to display on the lcd. one bit of the ram corresponds to 1 segment of the lcd. note that some bits of the ram cannot be displayed depending on lcd driving mode. display ram 51 bits segment address (seg0?eg50) common address (com0?om3) 4 bits figure 1 display ram
HD61602/hd61603 1237 reading data from display ram: a display ram segment address corresponds to a segment output. the data at segment address segn is output to segment output segn terminal. a common address corresponds to the output timing of a common output and a segment output. the same common address data is simultaneously read. the data of display ram is reproduced on the lcd panel. when a 7-segment type lcd driver is connected, for example, the correspondence between the display ram and the display pattern in each mode is as follows: 1. static drive in the static drive, only the column of com0 of display ram is output. com1 to com3 are not displayed (figure 2). 2. 1/2 duty cycle drive in the 1/2 duty cycle drive, the columns of com0 and com1 of display ram are output in time sharing. the columns of com2 and com3 are not displayed (figure 3). com3 com2 com1 com0 f edcdpgba display ram seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 lcd connection a b c d dp e f g com0 seg11 seg8 seg9 seg10 seg12 seg13 seg14 seg15 figure 2 example of correspondence between lcd connection and display ram (static drive, HD61602) com3 com2 com1 com0 feddp display ram seg4 seg5 seg6 seg7 seg8 seg9 lcd connection a b c d dp e f g com1 seg6 seg4 seg5 seg7 com0 agcb figure 3 example of correspondence between lcd connection and display ram (1/2 duty cycle, HD61602)
HD61602/hd61603 1238 3. 1/3 duty cycle drive in the 1/3 duty cycle drive, the columns of com0 to com2 are output in time sharing. no column of com3 is displayed. y cannot be rewritten by display data (input on an 8-segment basis). please use bit manipulation to turn on/off the display of y (figure 4). 4. 1/4 duty cycle drive in the 1/4 duty cycle drive, all the columns of com0 to com3 are displayed (figure 5). b c lcd connection a d dp e f g com2 seg3 seg4 seg5 com0 y com1 com3 com2 com1 com0 eddp display ram seg3 seg4 seg5 seg6 fgc yab figure 4 example of correspondence between lcd connection and display ram (1/3 duty cycle, HD61602) com3 com2 com1 com0 ddp display ram seg2 seg3 seg4 ec gb b c lcd connection a d dp e f g com2 seg2 seg3 com0 com1 com3 fa figure 5 example of correspondence between lcd connection and display ram (1/4 duty cycle, HD61602)
HD61602/hd61603 1239 writing data into display ram: data is written into the display ram in the following five methods: 1. bit manipulation data is written into any bit of ram on a bit basis. 2. static display mode 8-bit data is written on a digit basis according to the 7-segment type lcd pattern of static drive. 3. 1/2 duty cycle display mode 8-bit data is written on a digit basis according to the 7-segment type lcd pattern of 1/2 duty cycle drive. 4. 1/3 duty cycle display mode 8-bit data is written on a digit basis according to the 7-segment type lcd pattern of 1/3 duty cycle drive. 5. 1/4 duty cycle display mode 8-bit data is written on a digit basis according to the 7-segment type lcd pattern of 1/4 duty cycle drive. the ram area and the allocation of the segment data for 1-digit display depend on the driving methods as described in reading data from display ram. 8-bit data is written on a digit basis corresponding to the above duty cycle driving methods. the digits are allocated as shown figure 8 (allocation of digits). as the data can be transferred on a digit basis from a microprocessor, transfer efficiency is improved by allocating the lcd pattern according to the allocation of each bit data of the digit in the data ram. figure 6 shows the digit address (displayed as adn) to specify the store address of the transferred 8-bit data on a digit basis. figure 7 shows the correspondence between each segment in an adn and the 8-bit input data. when data is transferred on a digit basis 8-bit display data and digit address should be specified as described above. however, when the digit address is ad6 for static, ad12 for 1/2 duty cycle, or ad25 for 1/4 duty cycle, display ram does not have enough bits for the data. thus the extra bits of the input 8-bit data are ignored. in bit manipulation, any one bit of display ram can be written. when data is transferred on a bit basis, 1-bit display data, a segment address (6 bits) and a common address (2 bits) should be specified.
HD61602/hd61603 1240 (4) 1/4 duty cycle display ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad25 (3) 1/3 duty cycle display ad0 ad1 ad2 ad3 ad4 ad5 ad6 . . . ad16 (2) 1/2 duty cycle display ad0 ad1 ad2 ad3 ad4 . . . ad12 com0com1 (1) static ad0 ad1 ad2 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg50 . . . ad6 com2 com0com1 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg50 com2 com0com1 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg50 com2 com3 com0com1 com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg50 . . . ad24 figure 6 allocation of digit (HD61602) seg3 n seg3 n+1 seg3 n+2 com0 com1 com2 bit 7 6 4 1 3 bit 0 5 2 (3) 1/3 duty display seg4 n seg4 n+1 seg4 n+2 seg4 n+3 com0 com1 bit 7 6 4 2 5 3 (2) 1/2 duty display bit 0 1 seg0 seg8 n+1 seg8 n+2 seg8 n+3 seg8 n+4 seg8 n+5 seg8 n+6 seg8 n+7 com0 bit 7 6 5 (1) static display 4 3 2 1 bit 0 seg2 n seg2 n+1 com0 com1 com2 bit 7 6 21 3 (4) 1/4 duty display 5 bit 0 4 com3 figure 7 bit assignment in an adn (HD61602)
HD61602/hd61603 1241 hd61603 display ram the hd61603 has an internal display ram as shown in figure 8. display data is stored in the ram and output to the segment output terminal. reading data from display ram: each bit of the display ram corresponds to an lcd segment. the data at segment address segn is output to segment output segn terminal. figure 9 shows an example of the correspondence between the display ram bit and the display pattern when a 7-segment type lcd is connected. writing data into display ram: data is written into the display ram in the following two methods: 1. bit manipulation data is written into any bit of ram on a bit basis. 2. static display mode 8-bit data is written on a digit basis according to the 7-segment type lcd pattern of static drive. display ram 64 bits segment address (seg0?eg63) 1 bit (com0) figure 8 display ram (hd61603) com0 f edcdpgba display ram seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 lcd connection a b c d dp e f g com0 seg11 seg8 seg9 seg10 seg12 seg13 seg14 seg15 seg16 figure 9 example of correspondence between display ram bit and display pattern (hd61603)
HD61602/hd61603 1242 the 8-bit data is written on a digit basis into the digit address (displayed as adn) shown in figure 10. when data is transferred from a microprocessor, four 4-bit data are needed to specify the digit address and an 8-bit display data. figure 11 shows the correspondence between each segment in an adn and the transferred 8-bit data. in bit manipulation, any one bit of display ram can be written. when data is transferred on a bit basis, 1-bit display data and a segment address (6 bits) should be specified. seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 com0 ad0 ad1 ad2 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 seg59 seg60 seg61 seg62 seg63 ad6 ad7 figure 10 allocation of digits (hd61603)
HD61602/hd61603 1243 seg8 n seg8 n+1 seg8 n+2 seg8 n+3 seg8 n+4 seg8 n+5 seg8 n+6 seg8 n+7 6 5 4 3 2 1 com0 bit 7 bit 0 figure 11 bit assignment in an adn (hd61603)
HD61602/hd61603 1244 operating modes HD61602 operating modes the HD61602 has the following operating modes: 1. lcd drive mode determines the lcd driving method. a. static drive mode lcd is driven statically. b. 1/2 duty cycle drive mode lcd is driven at 1/2 duty cycle and 1/2 bias. c. 1/3 duty cycle drive mode lcd is driven at 1/3 duty cycle and 1/3 bias. d. 1/4 duty cycle drive mode lcd is driven at 1/4 duty cycle and 1/3 bias. 2. data display mode determines how to write display data into the data ram. a. static display mode 8-bit data is written into the display ram according to the digit in static drive. b. 1/2 duty cycle display mode 8-bit data is written into the display ram according to the digit in 1/2 duty cycle drive. c. 1/3 duty cycle display mode 8-bit data is written into the display ram according to the digit in 1/3 duty cycle drive. d. 1/4 duty cycle display mode 8-bit data is written into the display ram according to the digit in 1/4 duty cycle drive. 3. ready output mode determines the ready output timing. after a data set is transferred, the data is processed internally. the next data cannot be acknowledged during the processing period. the ready output reports the period to the mpu. the timing when the ready is output can be selected from the following two modes: a. ready is mode always available (figure 12). b. ready is mode available by &6 and 5( (figure 13). 4. lcd off mode in this mode, the HD61602 stops driving lcd and turns it off. 5. external driving voltage mode a mode for using external driving voltage (v1, v2, and v3). the above 5 modes are specified by mode setting data. the modes are independent of each other and can be used in any combination. bit manipulation is independent of data display mode and can be used regardless of it.
HD61602/hd61603 1245 data transfer period ready we cs next data transfer input inhibit period figure 12 ready output timing (when it is always available) next data transfer data transfer period ready we cs re input inhibit period figure 13 ready output timing (when it is made available by &6 &6 and 5( 5( )
HD61602/hd61603 1246 hd61603 operating modes the hd61603 has the following modes: 1. ready output mode determines the ready output timing. after a data set is transferred, the data is processed internally. the next data cannot be acknowledged during the processing period. the ready output reports the period to the mpu. the timing when ready is output can be selected from the following two modes: a. ready is always available (figure 14). b. ready is mode available by &6 and 5( (figure 15). 2. lcd off mode in this mode, the hd61603 stops driving the lcd and turns it off. data transfer period ready we cs next data transfer input inhibit period figure 14 ready output timing (when it is always available) next data transfer data transfer period ready we cs re input inhibit period figure 15 ready output timing (when it is made available by &6 &6 and 5( 5( )
HD61602/hd61603 1247 input data formats HD61602 input data formats input data is composed of 8 bits 2. input them as 2-byte data after re ady output changes from low to high or low pulse is entered into 5( terminal. 1. display data (updates display on an 8-segment basis) 00 5 display address (digit address adn) 1st byte 76543210 display data 2nd byte 76543210 a. display address digit address adn in accordance with display mode b. display data pattern data that is written into the display ram according to display mode and the address 2. bit manipulation data (updates display on a segment basis) 01 display data 555 com address 1st byte 76543210 55 seg address 2nd byte 76543210 a. display data data that is written into 1 bit of the specified display ram. b. com address common address of display ram c. seg address segment address of display ram
HD61602/hd61603 1248 3. mode setting data 10 5 0 ready bit drive mode bits 1st byte 76543210 55555 off/on bit 2nd byte 76543210 external power supply display mode bits a. display mode bits 00: static display mode 01: 1/2 duty cycle display mode 10: 1/3 duty cycle display mode 11: 1/4 duty cycle display mode b. off/on bit 1: lcd off (set to 1 when sync is entered) 0: lcd on c. drive mode bits 00: static drive 01: 1/2 duty cycle drive 10: 1/3 duty cycle drive 11: 1/4 duty cycle drive d. ready bit 0: ready bus mode; ready outputs 0 only while cs and re are 0. (reset to 0 when sync is entered) 1: ready port mode; ready outputs 0 regardless of cs and re. e. external power supply bit 0: driving voltage is generated internally. 1: driving voltage is supplied externally. (set to 1 when sync is entered.) 4. 1-byte instruction 11 5 1st byte 76543210 55555 the first data (first byte) is ignored when bit 6 and bit 7 in the byte are 1.
HD61602/hd61603 1249 hd61603 input data formats input data is composed of 4 bits 4. input them as four 4-bit data after re ady output changes from low to high or low pulse is entered into 5( terminal. 1. display data (updates display on an 8-segment basis) 00 55 1st byte 3210 bit 7 6 5 4 3rd byte 3210 5 display address (digit address adn) 2nd byte 3210 bit 3 2 1 0 4th byte 3210 display data display data a. display address digit address adn shown in figure 10. b. display data pattern data that is written into the display ram as shown in figure 11. 2. bit manipulation data (updates display on a segment basis) 01 5 1st byte 3210 bit 5 4 3rd byte 3210 5 2nd byte 3210 bit 3 2 1 0 4th byte 3210 seg address seg address display data 5 00 55 a. display data data that is written into 1 bit of the specified display ram. b. seg address segment address of display ram (segment output)
HD61602/hd61603 1250 3. mode setting data 10 0 1st byte 3210 3rd byte 3210 5 2nd byte 3210 4th byte 3210 ready bit 55 55 5 55 5 off/on bit 00 a. off/on bit 1: lcd off (set to 1 when sync is entered.) 0: lcd on b. ready bits 0: ready bus mode; ready outputs 0 only while &6 and 5( are 0. (reset to 0 when sync is entered.) 1: ready port mode; ready outputs 0 regardless of &6 and 5( . 4. 1-byte instruction 11 5 1st byte 3210 5 the first data (4 bits) is ignored when bit 3 and 2 in the data are 1.
HD61602/hd61603 1251 how to input data how to input HD61602 data input data is composed of 8 bits 2. take care that the data transfer is not interrupted, because the first 8-bit data is distinguished from the second one by the sequence only. if data transfer is interrupted, or at power on, the following two methods can be used to reset the count of the number of bytes (count of the first and second bytes): 1. set &6 and 5( inputs low (no display data changes). 2. input 2 or more 1-byte instruction data in which bit 7 and 6 are 1 (display data may change). the data input method via data input terminals ( &6 , :( , d0 to d7) is similar to that of static ram such as hm6116. an access of the lsi can be made through the same bus line as rom and ram. when output ports of a microprocessor are used for an access, refer to the timing specifications and figure 16. cs we re ready sync sb d0?7 mode setting data mode setting data display data * 6 * 6 * 1 * 4 * 5 * 3 * 2 * 5 * 5 power on 1st 2nd 1st 2nd 1st 2nd notes: 1. 2. 3. 4. 5. 6. 7. ready output is indefinite during 12 clocks after the oscillation start at power on (clock: osc2 clock). high pulse should be applied to sync terminal when using two or more chips synchronously. in the mode in which ready is always available, ready output is in definite while sync is high. reset the byte counter after power on. ready output period is within 3.5 clocks in the mode setting operation and bit manipulation or within 10.5 clocks when the display data (8 bits) is updated. connect a pull-up resister if we or re may be floating. it is not always necessary to follow this example. figure 16 example of data transfer sequence
HD61602/hd61603 1252 how to input hd61603 data input data is composed of 4 bits 4. take care that data transfer is not interrupted, because the first 4-bit data to the fourth 4-bit data are distinguished from each other by the sequence only. if data transfer is interrupted, or at power on, the following two methods can be used to reset the count of the number of data (count of the first 4-bit data to the fourth 4-bit data): 1. set &6 and 5( low. 2. input 4 or more 1-byte instruction data (4-bit data) in which bit 3 and 2 are 1 (display data may change). the data input method via data input terminals ( &6 , :( , d0 to d3) is similar to that of static ram such as hm6116. an access of the lsi can be made through the same bus line as rom and ram. when output ports of a microprocessor are used for an access, refer to the timing specifications and figure 17. power on cs we re ready sync sb d0?3 * 6 * 6 * 1 * 4 * 5 * 3 * 2 * 5 * 5 mode setting data mode setting data display data 1st 2nd 3rd 4th 1st 2nd 3rd 4th 1st 2nd 3rd 4th notes: 1. 2. 3. 4. 5. 6. 7. ready output is indefinite during 12 clocks after the oscillation start at power on (clock: osc2 clock). high pulse should be applied to sync terminal when using two or more chips synchronously. in the mode in which ready is always available, ready output is in definite while sync is high. reset the 4-bit data counter after power on. ready output period is within 3.5 clocks in the mode setting operation and bit manipulation or within 10.5 clocks when the display data (8 bits) is updated. connect a pull-up resister if we or re may be floating. it is not always necessary to follow this example. figure 17 example of data transfer sequence
HD61602/hd61603 1253 notes on ready output note that the ready output w ill be unsettled during 1.5 clocks (max) after inputting the first 2-byte data for setting the mode after turning the power on. this is because the re ady bit d ata of mode setting latches and the mode of re ady pin (ready bus or port mode) are uns ettled until the completion of mode setting. there are two kinds of the ready output waveforms depending of the modes: 1. ready bus mode (ready bit = 0) 2. ready port mode (ready bit = 1) however, if you input sync before mode s etting, waveform will be determined; when you choose ready bus mode, (1) a in figure 18 w ill be output, and when you choose re ady port mode, (2) a will be output. the figures can be applied both to HD61602 and hd61603. 1st 2nd ready output is unsettled. mode setting data are latched. mode setting data (2-byte data) mode setting latch is unsettled. a b 1.5 clocks (max) note: cs = low (1) ready bus mode (2) ready port mode note: cs = low, re = high a b 1.5 clocks (max) 3.5 clocks (max) power on power on power on 1.5 clocks (max) ce we d0?7 we re ready we ready figure 18 ready output according to modes
HD61602/hd61603 1254 standby operation standby operation with low power consumption can be activated when pin sb is used. normal operation of the lsi is activated when pin sb is low level, and the lsi goes into the standby state when pin sb is high level. the standby state of the lsi is as follows: 1. lcd driver is stopped (lcd is off). 2. display data and operating mode are held. 3. the operation is suspended while display changes (while ready is outputting low.) in this case, ready outputs high within 10.5 clocks or 3.5 clocks after release from the standby mode. 4. oscillation is stopped. when this mode is not used, connect pin sb to vss. multichip operation when an lcd is driven with two or more chips, the driving timing of the lcd must be synchronized. in this case, the chips are synchronized with each other by using sync input. if sync input is high, the lcd driver timing circuit is reset. apply high pulse to the sync input after the operating mode is set. a high pulse to the sync input changes the mode s etting data. (the off/on bit is set and the ready bit is reset. see 3. mode setting data in input data formats.) transfer the mode setting data into the lsi after every sync operation. if a power on reset signal is applied to the sync pin, the lcd can be off-s tate when the power is turned on. when sync input is not used, connect pin sync to vss. when sb input is used, after standby mode is released, a high pulse must be applied to the sync input, and mode setting data must be set again. restriction on usage minimize the noise by inserting a noise by-pass capacitor ( 3 1 f) between vdd and vss pins. (insert one as near chip as possible.)
HD61602/hd61603 1255 liquid crystal display drive voltage circuit (HD61602) what is lcd voltage? HD61602 drives liquid crystal display using four levels of voltages (figure 19); vdd, v1, v2, and v3 (vdd is the highest and v3 is the lowest). the vo ltage between vdd and v3 is called vlcd and it is necessary to apply the appropriate vlcd according to the liquid crystal display. v3 always needs to be supplied regardless of the display duty ratio since it supplies the voltage to the lcd drive circuit of HD61602. vdd v1 v2 v3 vlcd d v d v d v figure 19 lcd output waveform and output levels
HD61602/hd61603 1256 when internal drive power supply is used when the internal drive power supply is used, attach c1Cc4 for charge pump circuits and variable resistance r1 for deciding display drive voltage to HD61602 as shown in figure 20. internal voltage is available by setting external voltage switching bits of mode setting data 0. figure 21 shows voltage characteristics between vdd and vref1. vo ltage is divided at r1, and then input into vref2. voltage between vdd and vref2 is equiv alent to ?v in figure 21, and so vlcd can be changed by regulating the voltage. vref2 is usually regulated by variable resistance, but when replacing r1 with two nonvariable resistances take vref1 between max and min into consideration as shown in figure 21. internal drive power supply is generated by using capacitance, and so large current cannot flow. when large liquid crystal display panel is used, examine the external drive power supply. regulator voltage follower charge pump circuit 2 (v1 ?vdd) 3 (v1 ?vdd) HD61602 vdd vss vref1 vref2 vc1 vc2 v1 v2 v3 com seg0 seg1 seg2 1 11 16 17 18 19 20 21 22 c6 c5 r1 r 1 r 2 c2 c3 c4 power lcd r1 = 1 m w variable c1 = 0.3 m f c2?4 = 0.3 m f c5 = 0.1 to 0.3 m f c6 3 1 m f 23?6 77 76 75 + figure 20 example
HD61602/hd61603 1257 when external drive power supply is used an external power supply can be used by setting external voltage switching bits of mode setting data to 1. when a large liquid crystal display panel is used, in multichip designs, which need accurate liquid crystal drive voltage, use the external power supply. see figure 22. r2Cr5 is connected in series between vdd and vss, and by these resistance r atio each voltage of ?v and vlcd is generated and then supplied to v1, v2, and v3. c2Cc4 are smoothing capacitors. when regulating brightness, change the resistance value by setting r5 variable resistance. 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 3456 min typ max vdd?ss (v) 2 vdd?ref1 (v) figure 21 voltage characteristics between vdd and vref1 nc nc vdd vss vref1 vref2 vc1 vc2 v1 v2 v3 r2 r3 r4 r5 c2 c3 c4 t r sb c6 positive power supply (3) 1/3 and 1/4 duty cycle drive nc nc vdd vss vref1 vref2 vc1 vc2 v1 v2 v3 r2 r3 r5 c2 c3 t r sb c6 positive power supply (2) 1/2 duty cycle drive nc nc vdd vss vref1 vref2 vc1 vc2 v1 v2 v3 r2 c4 r5 t r sb c6 positive power supply (1) static drive c6 3 1 m f notes: 1. 2. when standby mode is used, a transistor is required. r2?5 should be some k w ?ome tens of k w , and c2?4 should be 0.1 m f?.3 m f. figure 22 example when external drive voltage is used
HD61602/hd61603 1258 liquid crystal display drive voltage (hd61603) as shown in figure 23, apply lcd drive voltage from the external power supply. oscillation circuit when internal oscillation circuit is used when the internal oscillation circuit is used, attach an external resister r osc as shown in figure 24. (insert r osc as near chip as possible, and make the osc1 side shorter.) when external clock is used when an external clock of 100 khz with cmos level is provided, pin osc1 can be used for the input pin. in this case, open pin osc2. vdd vss v3 r2 t r sb c6 positive power supply c6 3 1 m f r1 1 11 12 note: when standby mode is used, a transistor is required. figure 23 example of drive voltage generator 79 80 r osc osc2 osc1 79 80 r osc osc2 osc1 79 80 osc2 osc1 nc etc. hd14049ub multichip operation figure 24 example of oscillation circuit
HD61602/hd61603 1259 hd74ls138 a b c gy address bus +5 v a 13 a 14 a 15 data bus d7? d0 e ba r/w vcc vss hd6809 cpu +5 v +5 v +5 v d0 HD61602 liquid crystal hd14049ub +5 v +5 v 4 vdd ready sb vss vc1 vc2 com0 to com3 seg0 seg50 v1 v2 v3 vref1 vref2 osc2 we re cs sync d0?7 osc1 HD61602 vdd ready sb vss vc1 seg1 seg50 vc2 v1 v2 v3 vref1 vref2 osc2 osc1 d0?7 we re cs sync figure 25 example (1) hd74ls138 a b c gy address bus +5 v a 13 a 14 a 15 data bus d3? d0 e ba r/w v cc vss hd6809 cpu +5 v +5 v d0 hd61603 liquid crystal hd14049ub +5 v vdd ready sb vss seg0 seg63 v3 we re cs sync d0?3 osc1 hd61603 vdd ready sb vss seg0 seg63 v3 d0?3 we re cs sync com0 osc2 osc1 osc2 figure 26 example (2)
HD61602/hd61603 1260 absolute maximum ratings item symbol limit unit power supply voltage* vdd, v1, v2, v3 C0.3 to +7.0 v terminal voltage* vt C0.3 to vdd +0.3 v operating temperature t opr C20 to +75 c storage temperature t stg C55 to +125 c * value referenced to vss = 0v. note: if lsis are used above absolute maximum ratings, they may be permanently destroyed. using them within electrical characteristics limits is strongly recommended for normal operation. use beyond these conditions will cause malfunction and poor reliability. recommended operating conditions limit item symbol min typ max unit power supply voltage vdd 2.2 5.5 v v1, v2, v3 0 vdd v terminal voltage* vt 0 vdd v operating temperature t opr C20 75 c * value referenced to vss = 0v.
HD61602/hd61603 1261 electrical characteristics dc characteristics (1) (vss = 0v, vdd = 4.5 to 5.5v, ta = C20 to +75c, unless otherwise noted) limit item symbol min typ max unit test condition input high voltage osc1 vih1 0.8 vdd vdd v others vih2 2.0 vdd v input low voltage osc1 vil1 0 0.2 vdd v others vil2 0 0.8 v output leakage current ready i oh 5 a v0 = vdd output low voltage ready vol 0.4 v i ol = 0.4 ma input leakage input terminal i il1 C1.0 1.0 a vin = 0Cvdd current* 1 v1 i il2 C20 20 a vin = vddCv3 v2, v3 i il3 C5.0 5.0 a lcd driver voltage drop com0Ccom3 vd1 0.3 v id = 3 a for each com, v3 = vddC3v seg0Cseg50 vd2 0.6 v id = 3 a for each seg, v3 = vddC3v power supply current i dd 100 a during display* 2 r osc = 360 k w i dd 5 a at standby internal driving voltage drop v1, v2, v3 vtr 0.4 v vref2 = vddC1 v, c1Cc4 = 0.3 f, rl = 3 m w notes: 1. v1, v2: apply only to HD61602. 2. except the transfer operation of display data and bit data.
HD61602/hd61603 1262 dc characteristics (2) (vss = 0v, vdd = 2.2 to 3.8v, ta = C20 to +75c, unless otherwise noted) limit item symbol min typ max unit test condition input high voltage vih 0.8 vdd vdd v input low voltage vil 0 0.1 vdd v output leakage current ready ioh 5 a vin = vdd output low voltage ready vol 0.1 vdd v iol = 0.04 ma input leakage input terminal i il1 C1.0 0 1.0 a vin = 0Cvdd current* 1 v1 i il2 C20 20 a vin = vddCv3 v2, v3 i il3 C5.0 5.0 a lcd driver voltage drop com0Ccom3 vd1 0.3 v id = 3 a for each com, v3 = vddC3v seg0Cseg50 vd2 0.6 v id = 3 a for each seg, v3 = vddC3v power supply current i ss 50 a during display* 2 r osc = 330 k w i ss 5 a at standby internal driving voltage drop v1, v2, v3 vtr 0.4 v vref2 = vddC1v, c1Cc4 = 0.3 f, rl = 3 m w , vdd = 3C3.8 v notes: 1. v1, v2: apply only to HD61602. 2. except the transfer operation of display data and bit data.
HD61602/hd61603 1263 ac characteristics (1) (vss = 0v, vdd = 4.5 to 5.5v, ta = C20 to +75c, unless otherwise noted) limit item symbol min typ max unit test condition oscillation frequency osc2 f osc 70 100 130 khz r osc = 360 k w external clock frequency osc1 f osc 70 100 130 khz external clock duty osc1 duty 40 50 60 % i/o signal timing t s 400 ns t h 10 ns t wh 300 ns t wl 400 ns t wr 400 ns t dl 1.0 s figure 31 t en 400 ns t op1 9.5 10.5 clock for display data transfer t op2 2.5 3.5 clock for bit and mode data transfer input signal rise time and fall time t r , t f 25ns
HD61602/hd61603 1264 ac characteristics (2) (vss = 0v, vdd = 2.2 to 3.8v, ta = C20 to +75c, unless otherwise noted) limit item symbol min typ max unit test condition oscillation frequency osc2 f osc 70 100 130 khz r osc = 330 k w external clock frequency osc1 f osc 70 100 130 khz external clock duty osc1 duty 40 50 60 % i/o signal timing t s 1.5 s (vdd = 3.0C3.8 v) t h 1.0 s t wh 1.5 s t wl 1.5 s t dl 2.0 s figure 32 t wr 1.5 s t en 2.0 s t op1 9.5 10.5 clock for display data transfer t op2 2.5 3.5 clock for bit and mode data transfer input signal rise time and fall time t r , t f 25ns
HD61602/hd61603 1265 vil t wh vih vil vih vil t wh vih vil t s t h vih vil cs we d0?7 figure 27 write timing ( 5( 5( is fixed at high level, and sync at low level) vil vil vih vih vil vih voh vol t en t wr t dl t dl t en we re ready figure 28 reset/read timing ( &6 &6 and sync are fixed at low level) vil vih t dl t en t op1, t op2 we ready vol voh figure 29 ready timing (when the ready output is always available)
HD61602/hd61603 1266 voh t wh voh t en vih vil vih within 1 clock ready sync figure 30 sync timing 10 k w vdd 47 k w 120 k w 1s2074h vss 30 pf measurement terminal (ready) figure 31 bus timing load circuit (ls-ttl load) vdd measurement terminal (ready) vss 30 pf 470 k w figure 32 bus timing load circuit (cmos load)

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