View SPEAR320_6250125.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

july 2011 doc id 16755 rev 5 1/73 1 SPEAR320 embedded mpu with arm926 core, optimized for factory automati on and consumer applications features arm926ej-s 333 mhz core high-performance 8-channel dma dynamic power-saving features configurable peripheral functions on 102 shared i/os. memory: ? 32 kb rom and 8 kb internal sram ? lpddr-333/ddr2-666 external memory interface ? sdio/mmc card interface ? serial flash memory interface (smi) ? flexible static memo ry controller (fsmc) up to 16-bit data bus width, supporting nand flash ? external memory interface (emi) up to 16- bit data bus width, supporting nor flash and fpgas security ? cryptographic accelerator connectivity ? 2 x usb 2.0 host ? 1 x usb 2.0 device ? 2 x fast ethernet ports (for external mii/smii phy) ? 2 x can interface ? 3 x ssp synchronous serial port (spi, microwire or ti protocol) ?2 x i 2 c ? 1 x fast irda interface ? 3 x uart interface ? 1 x standard parallel device port peripherals supported ? tft/stn lcd controller (resolution up to 1024 x 768 and up to 24 bpp) ? touchscreen support miscellaneous functions ? integrated real time clock, watchdog, and system controller ? 8-channel 10-bit adc, 1 msps ? 4 x pwm timers ? jpeg codec accelerator ? 6x 16-bit general purpose timers with programmable prescaler, 4 capture inputs ? up to 102 gpios with interrupt capability applications the SPEAR320 embedded mpu is configurable for a range of industrial and consumer applications such as: programmable logic controllers factory automation printers table 1. device summary order code temp range, c package packing SPEAR320-2 -40 to 85 lfbga289 (15x15 mm, pitch 0.8 mm) tr ay lfbga289 (15 x 15 x 1.7 mm) www. s t.com
contents SPEAR320 2/73 doc id 16755 rev 5 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 cpu arm 926ej-s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 embedded memory units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2.1 bootrom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 mobile ddr/ddr2 memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 serial memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 external memory interface (emi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6 sdio controller/mmc card interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.7 flexible static memory controller (fsmc) . . . . . . . . . . . . . . . . . . . . . . . . 14 3.8 multichannel dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.9 ethernet controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.9.1 mii0 ethernet controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.9.2 smii0/smii1/mii1 ethernet controllers . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.10 can controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.11 usb2 host controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.12 usb2 device controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.13 clcd controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.14 gpios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.15 parallel port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.16 synchronous serial ports (ssp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.17 i2c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.18 uarts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.18.1 uart0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.18.2 uart1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.18.3 uart2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.19 jpeg codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.20 cryptographic co-processor (c3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.21 8-channel adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SPEAR320 contents doc id 16755 rev 5 3/73 3.22 system controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.22.1 power saving system mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.22.2 clock and reset system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.23 vectored interrupt controller (vic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.24 general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.25 pwm timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.26 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.27 rtc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1 re q uired external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2 dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.3 shared i/o pins (pl_gpios) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.3.1 pl_gpio pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.3.2 configuration modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.3.3 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.3.4 boot pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.3.5 gpios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.3.6 multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.4 pl_gpio pin sharing for debug modes . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.2 maximum power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.3 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.4 overshoot and undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.5 3.3v i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.6 lpddr and ddr2 pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.7 power up se q uence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.8 removing power supplies for power saving . . . . . . . . . . . . . . . . . . . . . . . 49 6.9 power on reset (mreset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7 timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
contents SPEAR320 4/73 doc id 16755 rev 5 7.1 external interrupt timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.2 reset timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.3 ddr2 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.3.1 ddr2 read cycle timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.3.2 ddr2 write cycle timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.3.3 ddr2 command timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.4 clcd timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.5 i 2 c timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.6 fsmc timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.6.1 nand flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.7 emi timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.8 sdio timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.9 mii ethernet mac 10/100 mbps timing characteristics . . . . . . . . . . . . . . 60 7.9.1 mii transmit timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.9.2 mii receive timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.9.3 mdio timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.10 smii ethernet mac timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . 61 7.11 smi - serial memory interface timing char acteristics . . . . . . . . . . . . . . . . 62 7.12 ssp timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.12.1 spi master mode timings (clock phase = 0) . . . . . . . . . . . . . . . . . . . . . 64 7.12.2 spi master mode timings (clock phase = 1) . . . . . . . . . . . . . . . . . . . . . 65 7.13 uart timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7.14 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
SPEAR320 list of tables doc id 16755 rev 5 5/73 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. ethernet port multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3. master clock, rtc, reset and 3.3 v comparator pin descriptions . . . . . . . . . . . . . . . . . . . 26 table 4. power supply pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 5. debug pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 6. smi pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 7. usb pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 8. adc pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 9. ddr pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 10. pl_gpio pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 11. pl_gpio multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 12. table shading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 13. ball sharing during debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 14. SPEAR320 main memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 table 15. reconfigurable array subsystem memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 16. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 17. maximum power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 18. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 19. overshoot and undershoot specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 20. low voltage ttl dc input specification (3 v< v dd <3.6 v) . . . . . . . . . . . . . . . . . . . . . . . . 47 table 21. low voltage ttl dc output specification (3 v< v dd <3.6 v) . . . . . . . . . . . . . . . . . . . . . . . 47 table 22. pull-up and pull-down characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 23. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 24. driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 25. on die termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 26. reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 27. pl_gpio external interrupt input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0 table 28. cold (power-on) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 29. ddr2 read cycle timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 30. ddr2 write cycle timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 31. ddr2 command timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 32. clcd timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 33. timing characteristics for i 2 c in high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 34. timing characteristics for i 2 c in fast speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 35. timing characteristics for i 2 c in standard speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 36. timing characteristics for nand flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 table 37. emi timings for read cycle with acknowledgement on wait# . . . . . . . . . . . . . . . . . . . . . . 57 table 38. emi timings for write cycle with acknowledgement on wait# . . . . . . . . . . . . . . . . . . . . . . 58 table 39. sdio timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 40. mii tx timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 41. mii rx timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 42. mdc timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 43. smii timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 44. smi timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 45. timing re q uirements for ssp (all modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 46. timing re q uirements for spi master mode (clock phase = 0). . . . . . . . . . . . . . . . . . . . . . . 64 table 47. switching characteristics over recommended operating conditions for spi master mode (clock phase =0 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
list of tables SPEAR320 6/73 doc id 16755 rev 5 table 48. timing re q uirements for spi master mode (clock phase = 1). . . . . . . . . . . . . . . . . . . . . . . 65 table 49. switching characteristics over recommended operating conditions for spi master mode (clock phase = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 50. uart transmit timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 51. uart receive timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 52. 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 53. lfbga289 (15 x 15 x 1.7 mm) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 54. thermal resistance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 55. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
SPEAR320 list of figures doc id 16755 rev 5 7/73 list of figures figure 1. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. typical system architec ture using SPEAR320 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3. hierarchical multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 4. power-up se q uence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 5. power-down se q uence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 6. ddr2 read cycle waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 7. ddr2 write cycle waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 8. ddr2 command waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 9. clcd waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 10. output signal waveforms for i 2 c signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 11. output command signal waveforms for nand flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 12. output address signal waveforms for nand flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 13. in/out data address signal waveforms for nand flash . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 14. emi read cycle waveforms with acknowledgement on emi_wait# . . . . . . . . . . . . . . . . . . 57 figure 15. emi write cycle waveforms with acknowledgement on emi_wait#. . . . . . . . . . . . . . . . . . 57 figure 16. emi read cycle waveforms without acknowledgement on emi_wait# . . . . . . . . . . . . . . . 58 figure 17. emi write cycle waveforms without acknowledgement on emi_wait# . . . . . . . . . . . . . . . 58 figure 18. sdio timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 19. mii tx waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 20. mii rx waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 21. mdc waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 22. smii input/output timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 23. smi i/o waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 24. ssp_clk timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 25. spi master mode external timing (clock phase = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 26. spi master mode external timing (clock phase = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 27. uart transmit and receive timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 28. lfbga289 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9
description SPEAR320 8/73 doc id 16755 rev 5 1 description the SPEAR320 is a member of the spear fa mily of embedded mpus, optimized for industrial automation and consumer applications. it is based on the powerful arm926ej-s processor (up to 333 mhz), widely used in applications where high computation performance is re q uired. in addition, SPEAR320 ha s an mmu that allows virtual memory management - making the system compliant with linux operating system. it also offers 16 kb of data cache, 16 kb of instruction cache, jtag and etm (embedded trace macrocell ? ) for debug operations. a full set of peripherals allows the system to be used in many applications, some typical applications being factory automation, printer and consumer applications. figure 1. functional block diagram add title on master page add subtitle on master page usb device 2.0 +phy irda usb host 2.0 phy phy 2x can 3x ssp 2x ethernet 10/100 (smii/mii interface) mobile ddr/ddr2 memory controller 32 kbytes bootrom 8 kbytes sram fsmc nand flash interface jtag/trace arm926ej-s @333 mhz system controller interrupt controller watchdog rtc plls icache dcache mmu = functions with shared i/os depending on the device configuration. c3 crypto accelerator multichannel dma controller jpeg codec accelerator emi nor flash/ fpga interface hub up to 102 gpios 2x i 2 c master/slave lcd controller 1024*768 std parallel port adc 6x general purpose timer 3x uart irda 4x pwm timer serial flash interface sdio/mmc card interface
SPEAR320 main features doc id 16755 rev 5 9/73 2 main features arm926ej-s 32-bit risc cpu, up to 333 mhz ? 16 kbytes of instruction cache, 16 kbytes of data cache ? 3 instruction sets: 32-bit for high performance, 16-bit (thumb) for efficient code density, byte java mode (jazelle?) for direct execution of java code. ? tightly coupled memory 32-kbyte on-chip bootrom 8-kbyte on-chip sram external dram memory interface: ? 8/16-bit (mobile ddr@166 mhz) ? 8/16-bit (ddr2@333 mhz) serial memory interface sdio interface supporting spi, sd1, sfd4 and sd8 modes 8/16-bits nand flash controller (fsmc) external memory interface (emi) for connecting nor flash or fpgas boot capability from nand flas h, serial/parallel nor flash boot and field upgrade capability from usb high performance 8-channel dma controller 3x ethernet controllers (up to 2 operating concurrently) two usb2.0 host (high-full-low speed ) with integrated phy transceiver one usb2.0 device (high-full-low speed) with integrated phy transceiver 2x can 2.0 interfaces up to 102 gpios with interrupt capability up to 4 pwm outputs 3x ssp master/slave (supporti ng motorola, texas instrument s, national semiconductor protocols) up to 41.5 mbps standard parallel port (spp device implementation) 2 x i 2 c master/slave interface (slow-fa st-high speed, up to 1.2 mb/s) 3x uart: ? uart0 (up to 3 mbps) with hardware flow control and modem interface ? uart1 (up to 7 mbps) with hardware flow control (in some operating modes) ? uart2 (up to 7 mbps) with software flow control adc 10-bit, 1 msps 8 inputs jpeg codec accelerator 1 clock/pixel color lcd interface (up to 1024x768, 24-bits clcd controller, tft and stn panels) touchscreen support crypto accelerator (des/3des/aes/sha1)
main features SPEAR320 10/73 doc id 16755 rev 5 advanced power saving features ? normal, slow, doze and sleep modes cpu clock with software-programmable fre q uency ? enhanced dynamic power-domain management ? clock gating functionality ?low fre q uency operating mode ? automatic power saving controlled from application activity demands vectored interrupt controller system and peripheral controller ? 3 pairs of 16-bit general purpose timers with programmable prescaler ? rtc with separate power supply allowing battery connection ? watchdog timer ? miscellaneous registers array for embedded mpu configuration programmable pll for cpu and system clocks jtag ieee 1149.1 boundary scan etm functionality multiplexed on primary pins supply voltages ? 1.2 v core, 1.8 v/2.5 v ddr, 2. 5 v plls, 1.5 v rtc and 3.3 v i/os operating temperature: - 40 to 85 c lfbga289 (15 x 15 mm, pitch 0.8 mm)
SPEAR320 architecture overview doc id 16755 rev 5 11/73 3 architecture overview the SPEAR320 internal architec ture is based on several s hared subsystem logic blocks interconnected through a multilayer interconnection matrix. the switch matrix structure allows different subsystem dataflow to be executed in parallel improving the core platform efficiency. high performance master agents are directly interconnected with the memory controller reducing the memory access latency. the overall memory bandwidth assigned to each master port can be programmed and optimized through an internal efficient weighted round- robin arbitration mechanism. figure 2. typical sy stem architecture using SPEAR320 3.1 cpu arm 926ej-s the core of the SPEAR320 is an arm926ej-s reduce d instruction set computer (risc) processor. it supports the 32-bit arm and 16-bit thumb instruction sets, enabling the user to trade off between high performance and high code density and includes features for efficient execution of java byte codes. clock, re s et 3 2 khz 24 mhz rtc 8 -ch a nnel dma 6 timer s / wd s pear 3 20 arm 9 26ej- s u p to 333 mhz 8 kb em b ed. s ram 3 2 kb em b ed. rom mmu interr u pt/ s y s t controller gpio ddr memory controller ddr2 mo b ile ddr emi nor fl as h nand fl as h fpga eeprom s mi fl as h de bu g, tr a ce jtag etm 9 2x i2c internet acce ss phy irdda u s b2.0 phy device u s b2.0 phy ho s t u s b2.0 phy ho s t 3 x uart jpeg codec a cceler a tor c 3 crypto a cceler a tor 2x ethernet f s mc 3 x ss p can s dio/mmc mmc s d-c a rd s dio adc to u ch s creen lcd controller 4x pwm p a r a llel port 2x can controller are a network
architecture overview SPEAR320 12/73 doc id 16755 rev 5 the arm cpu and is clocked at a fre q uency up to 333 mhz. it has a 16-kbyte instruction cache, a 16-kbyte data cache, and features a memory management unit (mmu) which makes it fully compliant with linux and vxworks operating systems. it also includes an embedded trace module (etm medium+) for real-time cpu activity tracing and debugging. it supports 4-bit and 8-bit normal trace mode and 4-bit demultiplexed trace mode, with normal or half-rate clock. 3.2 embedded memory units 32 kbytes of bootrom 8 kbytes of sram 3.2.1 bootrom bootrom is small firmware program that is executed just after the SPEAR320 exits from reset. it supports the following boot modes: boot from nor serial flash boot from nand flash boot from nor parallel flash boot / upgrade from usb the first three modes support different ways of booting the application software, they re q uire a second-level boot software (xloader) to be located in flash. usb boot mode can be used for software maintenance or upgrade, if booting from any of the flash memories is not possible. the bootrom selects the boot mode from the boot pin settings (see section 4.3.4: boot pin s ). a setting is available to allow the bootrom to be bypassed. 3.3 mobile ddr/ddr2 memory controller SPEAR320 integrates a high performance multi- channel memory contro ller able to support low power mobile ddr and ddr2 double data rate memory devices. the multi-port architecture ensures memory is shared efficiently among different high-bandwidth client modules. it has 6 internal ports. one of them is reserved for register access during the controller initialization while the other five are used to access the external memory. it also includes the physical layer (phy) and dlls for fine tuning the timing parameters to maximize the data valid windows at different fre q uencies. 3.4 serial memory interface SPEAR320 provides a serial memo ry interface (smi), acting as an ahb slave interface (32- , 16- or 8-bit) to spi-compatible off-chip memories. these serial memories can be used either as data storage or for code execution.
SPEAR320 architecture overview doc id 16755 rev 5 13/73 main features: supports spi-compatible flash and eeprom devices acts always as a spi master and up to 2 spi slave memory devices are supported (with separate chip select signals), with up to 16 mb address space each smi clock signal (smiclk) is generated by smi (and input to all slaves) using a clock provided by the ahb bus smiclk can be up to 50 mhz in fast read mode (or 20 mhz in normal mode). it can be controlled by a programmable 7-bit prescaler allowing up to 127 different clock fre q uencies. 3.5 external memory interface (emi) the emi controller provides a simple external memory interface that can be used for example to connect to nor flash memory or fpga devices. main features: emi bus master 16 and 8-bit transfers can access 4 different peripherals using cs#, one at a time. supports single asynchronous transfers. supports peripherals which use byte lane procedure 3.6 sdio controller/mmc card interface the sdio host controller conforms to the sd host controller standard specification version 2.0. it handles sdio/sd protocol at transmission level, packing data, adding cyclic redundancy check (crc), start/end bit and checking for transaction format correctness. the host controller provides programmed i/o and dma data transfer method. main features: meets the following specifications: ? sd host controller standard specification version 2.0 ? sdio card specification version 2.0 ? sd memory card specification draft version 2.0 ? sd memory card security specification version 1.01 ? mmc specification version 3.31 and 4.2 supports both dma and non-dma mode of operation supports mmc plus and mmc mobile card detection (insertion / removal) card password protection host clock rate variable between 0 and 48 mhz supports 1 bit, 4 bit and 8 bit sd modes and spi mode supports multi media card interrupt mode allows card to interrupt host in 1 bit, 4 bit, 8 bit sd modes and spi mode. up to 100 mbits per second data rate using 4 parallel data lines (sd4 bit mode)
architecture overview SPEAR320 14/73 doc id 16755 rev 5 up to 416 mbits per second data rate using 8 bit parallel data lines (sd8 bit mode) cyclic redundancy check crc7 for co mmand and crc16 for data integrity designed to work with i/o cards, re ad-only cards and read/write cards error correction code (ecc) support for mmc4.2 cards supports read wait control, suspend/resume operation supports fifo overrun and underrun condition by stopping sd clock 3.7 flexible static memory controller (fsmc) SPEAR320 provides a flexible stat ic memory controller (fsmc) wh ich interfaces to external parallel nand flash memories. main features: 8/16-bit wide data path fsmc performs only one access at a time and only one external device is accessed supports little-endian and big-endian memory architectures ahb burst transfer handling to reduce access time to external devices supplies an independent configuration for each memory bank programmable timings to support a wide range of devices ? programmable wait states (up to 31) ? programmable bus turnaround cycles (up to 15) ? programmable output enable and write enable delays (up to 15) independent chip select control for each memory bank shares the address bus and the data bus with all the external peripherals only chips selects are uni q ue for each peripheral external asynchronous wait control boot memory bank configurable at reset using external control pins 3.8 multichannel dma controller within its basic subsystem, SPEAR320 provides a dma controller (dmac) able to service up to 8 independent dma channels for serial data transfers between single source and destination (i.e., memory-to-memory, memory-to-peripheral, peripheral to- memory, and peripheral-to-peripheral). each dma channel can support a unidirectional transfer, with internal four-word fifo per channel.
SPEAR320 architecture overview doc id 16755 rev 5 15/73 3.9 ethernet controllers SPEAR320 features three multiplexed ether net macs, supporting up to two ports concurrently. the three controllers are named: mii0 smii0 smii1/mii1 table 2. ethernet port multiplexing configuration mode (see section 4.3.2: configuration modes ) available interfaces interface name mode 1 or mode 4 2 x smii smii0 + smii1 mode 1 or mode 4 with mii0 alternate i/o functions enabled 1 x smii + 1 x mii smii0+ mii0 mode 2 with mii0 alternate i/o functions enabled 2 x mii mii1 + mii0 mode 3 1 x smii smii0 mode 3 with mii0 alternate i/o functions enabled 1 x mii mii0
architecture overview SPEAR320 16/73 doc id 16755 rev 5 3.9.1 mii0 ethernet controller main features: supports the default media independent interface (mii) defined in the ieee 802.3 specifications. supports 10/100 mbps data transfer rates local fifo available (4 kbyte rx, 2 kbyte tx) supports both half-duplex and full-duplex operation. in half-duplex operation, csma/cd protocol is provided programmable frame length to support both standard and jumbo ethernet frames with size up to 16 kbytes 32/64/128-bit data transfer interface on system-side. a variety of flexible address filtering modes are supported a set of control and status registers (csrs) to control gmac core operation native dma with single-channel transmit and receive engines, providing 32/64/128-bit data transfers dma implements dual-buffer (ring) or linked-list (chained) descriptor chaining an ahb slave acting as programming interface to access all csrs, for both dma and gmac core subsystems an ahb master for data transfer to system memory 32-bit ahb master bus width, supporting 32, 64, and 128-bit wide data transactions it supports both big-endian and little-endian. 3.9.2 smii0/smii1/mii1 ethernet controllers the two ethernet controllers called smii0 and smii1/mii1 each have dedicated tx/rx signals while synchronization and clock signals are common for phy connection. each of the two ports provides the following features: compatible with ieee standard 802.3 10 and 100 mbit/s operation full and half duplex operation statistics counter registers for rmon/mib interrupt generation to signal receive and transmit completion automatic pad and crc generation on transmitted frames automatic discard of frames received with errors address checking logic supports up to four specific 48-bit addresses supports promiscuous mode where all valid received frames are copied to memory
SPEAR320 architecture overview doc id 16755 rev 5 17/73 hash matching of unicast and multicast destination addresses external address matching of received frames physical layer management through mdio interface supports serial network interface operation half duplex flow control by forc ing collisions on incoming frames full duplex flow control with recognition of incoming pause frames and hardware generation of transmitted pause frames support for 802.1q vlan tagging with recognition of incoming vlan and priority tagged frames multiple buffers per receive and transmit frame wake on lan support jumbo frames of up to 10240 bytes supported configurable endianess for the dma interface (ahb master)
architecture overview SPEAR320 18/73 doc id 16755 rev 5 3.10 can controller SPEAR320 has two can controllers fo r interfacing can 2.0 networks. main features: supports can protocol version 2.0 part a and b bit rates up to 1 mbit/s 16 message objects(136 x 16 message ram) each message object has its own identifier mask maskable interrupt programmable loop-back mode for self-test operation disabled automatic retransmission mode for time triggered can applications 3.11 usb2 host controller SPEAR320 has two fully independent usb 2.0 ho sts. each consists of 5 major blocks: ehci capable of managing high-speed transfers (hs mode, 480 mbps) ohci that manages the full and the low speed transfers (12 and 1.5 mbps) local 2-kbyte fifo local dma integrated usb2 transceiver (phy) both hosts can manage an external power switch, providing a control line to enable or disable the power, and an input line to sense any over-current condition detected by the external switch. one host controller at time can perform high speed transfer. 3.12 usb2 device controller main features: supports the 480 mbps high-speed mode (hs) for usb 2.0, as well as the 12 mbps full-speed (fs) and the low-speed (ls modes) for usb 1.1 supports 16 physical endpoints, configurable as different logical endpoints integrated usb transceiver (phy) local 4 kbyte fifo shared among all the endpoints dma mode and slave-only mode are supported in dma mode, the udc supports descriptor-based memory structures in application memory in both modes, an ahb slave is provided by udc-ahb, acting as programming interface to access to memory-mapped control and status registers (csrs) an ahb master for data transfer to system memory is provided, supporting 8, 16, and 32-bit wide data transactions on the ahb bus a usb plug (upd) detects the connection of a cable.
SPEAR320 architecture overview doc id 16755 rev 5 19/73 3.13 clcd controller SPEAR320 has a color li q uid crystal display controller (c lcdc) that provides all the necessary control signals to interface directly to a variety of color and monochrome lcd panels. main features: resolution programmable up to 1024 x 768 16-bpp true-color non-palletized, for color stn and tft 24-bpp true-color non-palletized, for color tft supports single and dual panel mono super twisted nematic (stn) displays with 4 or 8- bit interfaces supports single and dual-panel color and monochrome stn displays supports thin film transistor (tft) color displays 15 gray-level mono, 3375 color stn, and 32 k color tft support 1, 2, or 4 bits per pixel (bpp) palletized displays for mono stn 1, 2, 4 or 8-bpp palletized color displays for color stn and tft programmable timing for different display panels 256 entry, 16-bit palette ram, arranged as a 128 x 32-bit ram physically frame, line and pixel clock signals ac bias signal for stn and data enable si gnal for tft panels patented gray scale algorithm supports little and big-endian 3.14 gpios a maximum of 102 gpios (pl_gpios) are available when part of the embedded ips are not needed (see section 4.3: shared i/o pin s (pl_gpio s ) ). within its basic subs ystem, SPEAR320 provides a base general purpose input/output (gpio) block (basgpio). the base gpio block provides 6 programmable inputs or outputs. each input/output can be controlled in two distinct modes: software mode, through an apb interface. hardware mode, through a hardware control interface. main features of the base gpio block are: six individually programmable input/output pins (default to input at reset) an apb slave acting as control interface in "software mode" programmable interrupt generation capability on any number of pins. hardware control capability of gpio lines for differ ent system configurations. bit masking in both read and write operation through address lines. other gpio blocks are present in the reconfigurable array subsystem.
architecture overview SPEAR320 20/73 doc id 16755 rev 5 3.15 parallel port main features: slave mode device interface for standard parallel port host supports unidirectional 8-bit data transfer from host to slave supports 9th bit for parity/data/command etc. maskable interrupts for data, device reset, auto line feed apb input clock fre q uency re q uired is 83 mhz for acknowledgement timings 3.16 synchronous serial ports (ssp) SPEAR320 provides three synchro nous serial ports (ssp) that offer a master or slave interface to enable synchronous serial communication with slave or master peripherals main features: master or slave operation. programmable clock bit rate and prescale. separate transmit and receive first-in, first-out memory buffers, 16-bits wide, 8 locations deep. programmable choice of interface operation: ? spi (motorola) ? microwire (national semiconductor) ? ti synchronous serial. programmable data frame size from 4 to 16-bits. independent masking of transmit fifo, receive fifo, and receive overrun interrupts. internal loopback test mode available. dma interface 3.17 i2c the SPEAR320 has 2 i2c interfaces: main features: compliance to the i 2 c bus specification (philips) supports three modes: ? standard (100 kbps) ? fast (400 kbps) ? high-speed clock synchronization master and slave mode configuration possible multi-master mode (bus arbitration) 7-bit or 10-bit addressing 7-bit or 10-bit combined format transfers
SPEAR320 architecture overview doc id 16755 rev 5 21/73 slave bulk transfer mode ignores cbus addresses (predessor to i2c that used to share the i2c bus) transmit and receive buffers interrupt or polled-mode operation handles bit and byte waiting at all bus speeds digital filter for the re ceived sda and scl lines handles component parameters for configurable software driver support supports apb data bus widths of 8, 16 and 32 bits. 3.18 uarts the SPEAR320 has 3 uarts wi th different capabilities. 3.18.1 uart0 main features: separate 16 x 8 (16 locations deep x 8-bit wide) transmit and 16 x 12 receive fifos to reduce cpu interrupts speed up to 3 mbps hardware and/or software flow control modem interface signals 3.18.2 uart1 main features: separate 16 x 8 (16 location deep x 8-bit wide) transmit and 16x12 receive fifos to reduce cpu interrupts speed up to 7 mbps hardware flow control (in small printers and automation expansion modes only) and/or software flow control 3.18.3 uart2 main features: separate 16x8 (16 location deep x 8-bit wide) transmit and 16x12 receive fifos to reduce cpu interrupts speed up to 7 mbps software flow control 3.19 jpeg codec SPEAR320 provides a jpeg codec with header processing (jpgc), able to decode (or encode) image data co ntained in the SPEAR320 ram, from the jpeg (or mcu) format to the mcu (or jpeg) format.
architecture overview SPEAR320 22/73 doc id 16755 rev 5 main features: compliance with the baseline jpeg standard (iso/iec 10918-1) single-clock per pixel encoding/decoding support for up to four channels of component color 8-bit/channel pixel depths programmable q uantization tables (up to four) programmable huffman tables (two ac and two dc) programmable minimum coded unit (mcu) configurable jpeg header processing support for restart marker insertion use of two dma channels and of two 8 x 32-bits fifo's (local to the jpeg) for efficient transferring and buffering of encoded/decoded data from/to the codec core. 3.20 cryptographic co-processor (c3) SPEAR320 has an embedd ed channel control coprocessor (c3). c3 is a high-performance instruction driven dma based co-processor. it executes instruction flows generated by the host processor. after it has been set-up by the host it runs in a completely autonomous way (dma data in, data processing, dma data out), until the completion of all the re q uested operations. c3 has been used to accelerate the processing of cryptographic, security and network security applications. it can be used for other types of data intensive applications as well. main features: supported cryptographic algorithms: ? advanced encryption sta ndard (aes) cipher in ecb, cbc, ctr modes. ? data encryption standard (des) cipher in ecb and cbc modes. ? sha-1, hmac-sha-1, md5, hmac-md5 digests. instruction driven dma based programmable engine. ahb master port for data access from/to system memory. ahb slave port for co-processor regi ster accesses and in itial engine-setup. the co-processor is fully autonomous (dma input reading, cryptographic operation execution, dma output writing) after being set up by the host processor. the co-processor executes programs written by the host in memory, it can execute an unlimited list of programs. the co-processor supports hardware chaining of cryptographic blocks for optimized execution of data-flow re q uiring multiple algorithms processing over the same set of data (for example encryption + hashing on the fly).
SPEAR320 architecture overview doc id 16755 rev 5 23/73 3.21 8-channel adc main features: successive approximatio n conversion method 10-bit resolution @1 msps hardware supporting up to 13.5 bits resolution at 8 ksps by oversampling and accumulation eight analog input (ain) channels, ranging from 0 to 2.5 v inl 1 lsb, dnl 1 lsb programmable conversion speed, (min. conversion time is 1 s) programmable averaging of results from 1 (no averaging) up to 128 programmable auto scan for all the eight channels. 3.22 system controller the system controller provides an interface for controllin g the operation of the overall system. main features: power saving system mode control crystal oscillator and pll control configuration of system response to interrupts reset status capture and soft reset generation watchdog and timer module clock enable 3.22.1 power saving system mode control using three mode control bits, the system controller switch th e SPEAR320 to any one of four different modes: doze, sleep, slow and normal. sleep mode : in this mode the system clocks, hclk and clk, are disabled and the system controller clock sclk is driven by a low speed oscillator (n ominally 32768 hz). when either a fiq or an irq interrupt is generated (through the vic) the system enters doze mode. additionally, the operating mode setting in the system control register automatically changes from sleep to doze. doze mode : in this mode the system clocks , hclk and clk, and the system controller clock sclk are driven by a lo w speed oscillator. t he system controller moves into sleep mode from doze mode on ly when none of th e mode control bits are set and the processor is in wait-for-interrupt state. if slow mode or normal mode is re q uired the system moves into the xtal co ntrol transition stat e to initialize the crystal oscillator. slow mode : during this mode, both the system clocks and the system controller clock are driven by the crystal oscillator. if normal mode is selected, the system goes into the "pll control" transition state. if neither the slow nor the normal mode control bits are set, the system goes into the "switch from xtal" transition state. normal mode : in normal mode, both the system clocks and the system controller clock are driven by the pll output. if the normal mode control bit is not set, then the system goes into the "switch from pll" transition state.
architecture overview SPEAR320 24/73 doc id 16755 rev 5 3.22.2 clock and reset system the clock system is a fully programmable bloc k that generates all the clocks necessary to the chip. the default operating clock fre q uencies are: clock @ 333 mhz for the cpu. clock @ 166 mhz for ahb bus and ahb peripherals. clock @ 83 mhz for, apb bus and apb peripherals. clock @ 333 mhz for ddr memory interface. the default values give the maximum allowed clock fre q uencies. the clock fre q uencies are fully programmable through dedicated registers. the clock system consists of 2 main parts: a multi clock generator bl ock and two internal plls. the multi clock generator block, takes a reference signal (which is usually delivered by the pll), generates all clocks for the ips of SPEAR320 accordi ng to dedicated programmable registers. each pll uses an oscillator input of 24 mhz to generate a clock signal at a fre q uency corresponding at the highest of the group. this is the reference signal used by the multi clock generator block to obtain all the other re q uested clocks for the group. its main feature is electromagnetic interfer ence reduction capability. the user can set up the pll in order to modulate the vco with a triangular wave. the resulting signal has a spectrum (and power) spread over a small programmable range of fre q uencies centered on f0 (the vco fre q uency), obtaining minimum electromagnetic emissions. this method replaces all the other traditional methods of emi reduction, such as filtering, ferrite beads, chokes, adding power layers and ground planes to pcbs, metal shielding and so on. this gives the customer appreciable cost savings. in sleep mode the SPEAR320 runs with the pll disabled so the available fre q uency is 24 mhz or a sub-multiple (/2, /4, /8). 3.23 vectored interrupt controller (vic) the vic allows the os interrupt handler to q uickly dispatch interrupt service routines in response to peripheral interrupts. there are 32 interrupt lines and the vic uses a separate bit position for each interrupt source. software controls each re q uest line to generate software interrupts. 3.24 general purpose timers SPEAR320 provides 6 general purpose timers (gpts) acting as apb slaves. each gpt consists of 2 channels, each one made up of a programmable 16-bit counter and a dedicated 8-bit timer clock prescaler. the programmable 8-bit prescaler performs a clock division by 1 up to 256, and different input fre q uencies can be chosen through configuration registers (a fre q uency range from 3.96 hz to 48 mhz can be synthesized).
SPEAR320 architecture overview doc id 16755 rev 5 25/73 two different modes of operation are available : auto-reload mode, an interrupt source is activated, the counter is automatically cleared and then it restarts incrementing. single-shot mode, an interrupt source is activated, the counter is stopped and the gpt is disabled. 3.25 pwm timers SPEAR320 provides 4 pwm timers. main features: prescaler to define the input clock fre q uency to each timer programmable duty cycle from 0% to 100% programmable pulse length apb slave interface for register programming 3.26 watchdog timer the arm watchdog module consists of a 32-bit down counter with a programmable timeout interval that has the capability to generate an interrupt and a reset signal on timing out. the watchdog module is intended to be used to apply a reset to a system in the event of a software failure. 3.27 rtc oscillator the rtc provides a 1-second resolution clock. this keeps time when the system is inactive and can be used to wake the system up when a programmed alarm time is reached. it has a clock trimming feature to compensate for the accuracy of the 32.768 khz crystal and a secured time update. main features: time-of-day clock in 24 hour mode calendar alarm capability isolation mode, allowing rtc to work even if power is not supplied to the rest of the device.
pin description SPEAR320 26/73 doc id 16755 rev 5 4 pin description the following tables describe the pinout of the SPEAR320 listed by functional block. list of abbreviations: pu = pull up pd = pull down 4.1 required external components 1. ddr_comp_1v8: place an external 121 k resistor between ball p4 and ball r4 2. usb_tx_rtune: connect an external 43.2 pull-down resistor to ball k5 3. digital_rext: place an external 121 k resistor between ball g4 and ball f4 4. dith_vdd_2v5: add a ferrite bead to ball m4 4.2 dedicated pins table 3. master clock, rtc, reset and 3.3 v comparator pin descriptions group signal name ball direction function pin type master clock mclk_xi p1 in 24 mhz (typical) crystal in oscillator 2.5 v capable mclk_xo p2 out 24 mhz (typical) crystal out rtc rtc_xi e2 in 32 khz crystal in oscillator 1v5 capable rtc_xo e1 out 32 khz crystal out reset mreset m17 in main reset ttl schmitt trigger input buffer, 3.3 v tolerant 3.3 v comp. digital_rext g4 out configuration analog, 3.3 v capable digital_gndbg comp f4 power power power table 4. power supply pin description group signal name ball value digital ground gnd g6 g7 g8 g9 g10 g11 h6 h7 h8 h9 h10 h11 j6 j7 j8 j9 j10 j11 k6 k7 k8 k9 k10 k11 l6 l7 l8 l9 l10 m8 m9 m10 0 v usb_host1_host 0_device_dvss l5
SPEAR320 pin description doc id 16755 rev 5 27/73 note: all the vdd 2v5 power s upplie s are analog vdd. analog ground rtc_gnd f2 0 v dith_pll_vss_ana g1 usb_host1_vssa j2 usb_host0_vssa l1 usb_common_vssac l3 usb_device_vssa n2 dith_vss2v5 n4 mclk_gnd p3 mclk_gndsub r3 adc_agnd n12 i/o digital_vdde3v3 f5 f6 f7 f10 f11 f12 g5 j12 k12 l12 m12 3.3 v core vdd f8 f9 g12 h5 h12 j5 l11 m6 m7 m11 1.2 v usb host0 phy usb_host0_vdd2v5 l2 2.5 v usb_host0_vdd3v3 k4 3.3 v usb host1 phy usb_host1_vdd2v5 k3 2.5 v usb_host1_vdd3v3 j1 3.3 v usb device phy usb_device_vdd2v5 n1 2.5 v usb_device_vdd3v3 n3 3.3 v usb_host1_host0_device_dvdd1v2 m3 1.2 v osci (master clock) mclk_vdd r1 1.2 v mclk_vdd2v5 r2 2.5 v pll1 dith_pll_vdd_ana g2 2.5 v pll2 dith_vdd_2v5 m4 2.5 v ddr i/o ddr_vdde1v8 m5 n5 n6 n7 n8 n9 n10 n11 1.8 v adc adc_avdd n13 2.5 v osci rtc rtc_vdd1v5 f1 1.5 v table 4. power supply pin description (continued) group signal name ball value
pin description SPEAR320 28/73 doc id 16755 rev 5 table 5. debug pin description signal name ball direction function pin type test_0 k16 in test configuration ports. for functional mode, they have to be set to zero. ttl input buffer, 3.3 v tolerant, pd test_1 k15 test_2 k14 test_3 k13 test_4 j15 boot_sel j14 reserved, to be fixed at high level ntrst l16 in test reset input ttl schmitt trigger input buffer, 3.3 v tolerant, pu tdo l15 out test data output ttl output buffer, 3.3 v capable 4 ma tck l17 in test clock ttl schmitt trigger input buffer, 3.3 v tolerant, pu tdi l14 in test data input tms l13 in test mode select table 6. smi pin description signal name ball direction function pin type smi_datain m13 in serial flash input data ttl input buffer 3.3 v tolerant, pu smi_dataout m14 out serial flash output data ttl output buffer 3.3 v capable 4 ma smi_clk n17 i/o serial flash clock smi_cs_0 m15 out serial flash chip select smi_cs_1 m16 table 7. usb pin description group signal name ball direction function pin type usb device usb_device_dp m1 i/o usb device d+ bidirectional analog buffer 5 v tolerant usb_device_dm m2 usb device d- usb_device_vbus g3 in usb device vbus ttl input buffer 3.3 v tolerant, pd
SPEAR320 pin description doc id 16755 rev 5 29/73 usb host usb_host1_dp h1 i/o usb host1 d+ bidirectional analog buffer 5 v tolerant usb_host1_dm h2 usb host1 d- usb_host1_vbus h3 out usbhost1 vbus ttl output buffer 3.3 v capable, 4 ma usb_host1_overcur j4 in usb host1 over-current ttl input buffer 3.3 v tolerant, pd usb_host0_dp k1 i/o usb host0 d+ bidirectional analog buffer 5 v tolerant usb_host0_dm k2 usb host0 d- usb_host0_vbus j3 out usb host0 vbus ttl output buffer 3.3 v capable, 4 ma usb_host0_overcur h4 in usb host0 over-current ttl input buffer 3.3 v tolerant, pd usb usb_txrtune k5 out reference resistor analog usb_analog_test l4 out analog test output analog table 8. adc pin description signal name ball direction function pin type ain_0 n16 in adc analog input channel analog buffer 2.5 v tolerant ain_1 n15 ain_2 p17 ain_3 p16 ain_4 p15 ain_5 r17 ain_6 r16 ain_7 r15 adc_vrefn n14 adc negative voltage reference adc_vrefp p14 adc positive voltage reference table 7. usb pin description (continued) group signal name ball direction function pin type
pin description SPEAR320 30/73 doc id 16755 rev 5 table 9. ddr pin description signal name ball direction function pin type ddr_mem_add_0 t2 out address line sstl_2/sstl_18 ddr_mem_add_1 t1 ddr_mem_add_2 u1 ddr_mem_add_3 u2 ddr_mem_add_4 u3 ddr_mem_add_5 u4 ddr_mem_add_6 u5 ddr_mem_add_7 t5 ddr_mem_add_8 r5 ddr_mem_add_9 p5 ddr_mem_add_10 p6 ddr_mem_add_11 r6 ddr_mem_add_12 t6 ddr_mem_add_13 u6 ddr_mem_add_14 r7 ddr_mem_ba_0 p7 out bank select ddr_mem_ba_1 p8 ddr_mem_ba_2 r8 ddr_mem_ras u8 out row add. strobe ddr_mem_cas t8 out col. add. strobe ddr_mem_we t7 out write enable ddr_mem_clken u7 out clock enable ddr_mem_clkp t9 out differential clock differential sstl_2/ sstl_18 ddr_mem_clkn u9 ddr_mem_cs_0 p9 out chip select sstl_2/ sstl_18 ddr_mem_cs_1 r9 ddr_mem_odt_0 t3 i/o on-die termination enable lines ddr_mem_odt_1 t4
SPEAR320 pin description doc id 16755 rev 5 31/73 ddr_mem_dq_0 p11 i/o data lines (lower byte) sstl_2/ sstl_18 ddr_mem_dq_1 r11 ddr_mem_dq_2 t11 ddr_mem_dq_3 u11 ddr_mem_dq_4 t12 ddr_mem_dq_5 r12 ddr_mem_dq_6 p12 ddr_mem_dq_7 p13 ddr_mem__dqs_0 u10 out lower data strobe differential sstl_2/ sstl_18 nddr_mem_dqs_0 t10 ddr_mem_dm_0 u12 out lower data mask sstl_2/ sstl_18 ddr_mem_gate_open_0 r10 i/o lower gate open ddr_mem_dq_8 t17 i/o data lines (upper byte) ddr_mem_dq_9 t16 ddr_mem_dq_10 u17 ddr_mem_dq_11 u16 ddr_mem_dq_12 u14 ddr_mem_dq_13 u13 ddr_mem_dq_14 t13 ddr_mem_dq_15 r13 ddr_mem_dqs_1 u15 i/o upper data strobe differential sstl_2/ sstl_18 nddr_mem_dqs_1 t15 ddr_mem_dm_1 t14 i/o upper data mask sstl_2/ sstl_18 ddr_mem_gate_open_1 r14 upper gate open ddr_mem_vref p10 in reference voltage analog ddr_mem_comp2v5_gndb gcomp r4 power return for ext. resistors power ddr_mem_comp2v5_rext p4 power ext. resistor analog ddr2_en j13 in configuration ttl input buffer 3.3 v tolerant, pu table 9. ddr pin description (continued) signal name ball direction function pin type
pin description SPEAR320 32/73 doc id 16755 rev 5 4.3 shared i/o pins (pl_gpios) the 98 pl_gpio and 4 pl_clk pins have the following characteristics: ? output buffer: ttl 3.3 v capable up to 10 ma ? input buffer: ttl, 3.3 v tolerant, select able internal pull up/pull down (pu/pd) the pl_gpios can be configured in different modes. this allows SPEAR320 to be tailored for use in various applications like: ? metering concentrators ? large power supply controllers ? small printers 4.3.1 pl_gpio pin description 4.3.2 configuration modes this section describes the main operating modes created by using a selection of the embedded ips. the following modes can be selected by programming some control registers present in the reconfigurable array subsystem. mode 1: smii automation networking mode mode 2: mii automation networking mode mode 3: expanded automation mode mode 4: printer mode ta bl e 11: pl_gpio multiplexing s cheme shows all the i/o functions available in each mode. mode 1 is the default mode for SPEAR320. table 10. pl_gpio pin description group signal name ball direction function pin type pl_gpios pl_gpio_97... pl_gpio_0 (see the ta b l e 1 1 ) i/o general purpose i/o or multiplexed pins (see ta bl e 1 1 ) (see the introduction of the section 4.3 here above) pl_clk1... pl_clk4 programmable logic external clocks
SPEAR320 pin description doc id 16755 rev 5 33/73 smii automation networking mode the ?smii automation networking? operating mode mainly provides: nand flash interface (8 bits, 4 chip selects) 2 can2.0 interfaces 2 smii interfaces 3 uarts ? 1 with hardware flow control (up to 3 mbps) ? 2 with software flow control (baud rate up to 7 mbps) lcd interface (up to 1024x768, 24-bits lcd controller, tft and stn panels) touchscreen facilities 3 independent ssp synchronous serial port (spi, microwire or ti protocol) ports gpios with interrupt capability sdio interface supporting spi, sd1, sd4 and sd8 mode mii automation networking mode the ?mii automation networking? operating mode mainly provides: nand flash interface (8 bits, 4 chip selects) 2 can2.0 interfaces 2 mii interfaces 3 uarts ? 1 with hardware flow control (up to 3 mbps) ? 2 with software flow control (baud rate up to 7 mbps) 3 independent ssp synchronous serial port (spi, microwire or ti protocol) ports gpios with interrupt capability sdio interface supporting spi, sd1, sd4 and sd8 mode expanded automation mode the ?expanded automation? operating mode mainly provides: external memory interface (16 data bits, 24 address bits and 4 chip selects) nand flash interface (8-16 bits and 4 chip selects shared with emi) 2 can2.0 interfaces smii or mii interface 3 uarts ? 1 with hardware flow control (up to 3 mbps) ? 1 with hardware flow control (baud rate up to 7 mbps) ? 1 with software flow control (baud rate up to 7 mbps) ssp port 2 independent i2c interfaces up to 4 pwm outputs gpios with interr upt capabilities
pin description SPEAR320 34/73 doc id 16755 rev 5 printer mode the ?printer? operating mode mainly provides: nand flash interface (8 bits, 4 chip selects) up to 4 pwm outputs 2 smii interfaces 3 uarts ? 1 with hardware flow control (up to 3 mbps) ? 1 with hardware flow control (baud rate up to 7 mbps) ? 1 with software flow control (baud rate up to 7 mbps) sdio interface supporting spi, sd1, sd4 and sd8 mode standard parallel port (spp device implementation) 2 independent ssp synchronous serial ports (spi, microwire or ti protocol) gpios with interr upt capabilities 4.3.3 alternate functions other peripheral functions are listed in the alternate functions column of ta bl e 11: pl_gpio multiplexing s cheme and can be individually enabled/disabled configuring the bits of a dedicated control register. 4.3.4 boot pins the status of the boot pins is read at startup by the bootrom. 4.3.5 gpios the pl_gpio pins can be used as software controlled general purpose i/os (gpios) if they are not used by the i/o fu nctions of the SPEAR320 ips. to configure any pl_gpio pin as gpio, set the corresponding bit in the gpio_select(0 ..3) registers that are 102 bits write registers that select gpio versus some ips.
SPEAR320 pin description doc id 16755 rev 5 35/73 4.3.6 multiplexing scheme to provide the best i/o multiplexing flexib ility and the higher number of gpios for arm controlled input-output function, the following hierarchical multiplexing scheme has been implemented. figure 3. hierarchical multiplexing scheme gpios smii automation netwo rking mii automation network ing expanded automation printer programmer model co ntrol register bits (2:0) gpio_select(0 ..3) registers p l_gpio ras select register alternate functions table 11. pl_gpio multiplexing scheme pl_gpio_# / ball number configuration mode (enabl ed by programmer model control register bits (2:0)) alternate function (enabled by ras select register) boot pins function in gpio alternative mode 12 3 4 pl_gpio_97/h16 cld0 mii1_txclk emi_a0 0 gpio_97 pl_gpio_96/h15 cld1 mii1_txd0 emi_a1 0 gpio_96 pl_gpio_95/h14 cld2 mii1_txd1 emi_a2 0 gpio_95 pl_gpio_94/h13 cld3 mii1_txd2 emi_a3 0 gpio_94 pl_gpio_93/g17 cld4 mii1_txd3 emi_a4 0 gpio_93 pl_gpio_92/g16 cld5 mii1_txen emi_a5 0 gpio_92 pl_gpio_91/g15 cld6 mii1_txer emi_a6 0 gpio_91 pl_gpio_90/g14 cld7 mii1_rxclk emi_a7 0 gpio_90 pl_gpio_89/f17 cld8 mii1_rxdv emi_a8 0 gpio_89 pl_gpio_88/f16 cld9 mii1_rxer emi_a9 0 gpio_88 pl_gpio_87/g13 cld10 mii1_rxd0 emi_a10 0 gpio_87
pin description SPEAR320 36/73 doc id 16755 rev 5 pl_gpio_86/e17 cld11 mii1_rxd1 emi_a11 0 gpio_86 pl_gpio_85/f15 cld12 mii1_rxd2 emi_a12 spp_data0 gpio_85 pl_gpio_84/d17 cld13 mii1_rxd3 emi_a13 spp_data1 gpio_84 pl_gpio_83/e16 cld14 mii1_col emi_a14 spp_data2 gpio_83 pl_gpio_82/e15 cld15 mii1_crs emi_a15 spp_data3 gpio_82 pl_gpio_81/c17 cld16 mii1_mdio emi_a16 spp_data4 gpio_81 pl_gpio_80/d16 cld17 mii1_mdc emi_a17 spp_data5 gpio_80 pl_gpio_79/f14 cld18 0 emi_a18 spp_data6 gpio_79 pl_gpio_78/d15 cld19 0 emi_a19 spp_data7 gpio_78 pl_gpio_77/b17 cld20 0 emi_a20 spp_strbn gpio_77 pl_gpio_76/f13 cld21 0 emi_a21 spp_ackn gpio_76 pl_gpio_75/e14 cld22 0 emi_a22 spp_busy gpio_75 pl_gpio_74/c16 cld23 0 emi_a23 spp_perror gpio_74 pl_gpio_73/a17 clac 0 emi_d8/ fsmc_d8 spp_select gpio_73 pl_gpio_72/b16 clfp 0 emi_d9/ fsmc_d9 spp_autofdn gpio_72 pl_gpio_71/d14 cllp 0 emi_d10/ fsmc_d10 spp_faultn gpio_71 pl_gpio_70/c15 clle 0 emi_d11/ fsmc_d11 spp_initn gpio_70 pl_gpio_69/a16 clpower 0 emi_wait spp_selinn gpio_69 pl_gpio_68/b15 fsmc_d0 fsmc_d0 emi_d0/ fsmc_d0 fsmc_d0 gpio_68 pl_gpio_67/c14 fsmc_d1 fsmc_d1 emi_d1/ fsmc_d0 fsmc_d1 gpio_67 pl_gpio_66/e13 fsmc_d2 fsmc_d2 emi_d2/ fsmc_d2 fsmc_d2 gpio_66 pl_gpio_65/b14 fsmc_d3 fsmc_d3 emi_d3/ fsmc_d3 fsmc_d3 gpio_65 pl_gpio_64/d13 fsmc_d4 fsmc_d4 emi_d4/ fsmc_d4 fsmc_d4 gpio_64 pl_gpio_63/c13 fsmc_d5 fsmc_d5 emi_d5/ fsmc_d5 fsmc_d5 gpio_63 pl_gpio_62/a15 fsmc_d6 fsmc_d6 emi_d6/ fsmc_d6 fsmc_d6 h7 gpio_62 pl_gpio_61/e12 fsmc_d7 fsmc_d7 emi_d7/ fsmc_d7 fsmc_d7 h6 gpio_61 pl_gpio_60/a14 fsmc_addr_l e fsmc_addr_l e fsmc_addr_le fsmc_addr_le h5 gpio_60 pl_gpio_59/b13 fsmc_we fsmc_we emi_we/ fsmc_we fsmc_we h4 gpio_59 pl_gpio_58/d12 fsmc_re fsmc_re emi_oe/ fsmc_re fsmc_re h3 gpio_58 table 11. pl_gpio multiplexing scheme (continued) pl_gpio_# / ball number configuration mode (enabl ed by programmer model control register bits (2:0)) alternate function (enabled by ras select register) boot pins function in gpio alternative mode 12 3 4
SPEAR320 pin description doc id 16755 rev 5 37/73 pl_gpio_57/e11 fsmc_cmd_ le fsmc_cmd_ le fsmc_cmd_le fsmc_cmd_le h2 gpio_57 pl_gpio_56/c12 fsmc_rdy /bsy fsmc_rdy/ bsy fsmc_rdy/bsy fsmc_rdy/ bsy h1 gpio_56 pl_gpio_55/a13 fsmc_cs0 fsmc_cs0 emi_ce0/ fsmc_cs0 fsmc_cs0 h0 gpio_55 pl_gpio_54/e10 fsmc_cs1 fsmc_cs1 emi_ce1/ fsmc_cs1 fsmc_cs1 b3 gpio_54 pl_gpio_53/d11 fsmc_cs2 fsmc_cs2 emi_ce2/ fsmc_cs2 fsmc_cs2 b2 gpio_53 pl_gpio_52/b12 fsmc_cs3 fsmc_cs3 emi_ce_3/ fsmc_cs3 fsmc_cs3 b1 gpio_52 pl_gpio_51/d10 sd_cd sd_cd emi_byten0 sd_cd b0 gpio_51 pl_gpio_50/a12 sd_dat7 sd_dat7 emi_byten1 sd_dat7 tmr_cptr4 gpio_50 pl_gpio_49/c11 sd_dat6 sd_dat6 emi_d12/ fsmc_d12 sd_dat6 tmr_cptr3 gpio_49 pl_gpio_48/b11 sd_dat5 sd_dat5 emi_d13/ fsmc_d13 sd_dat5 tmr_cptr2 gpio_48 pl_gpio_47/c10 sd_dat4 sd_dat4 emi_d14/ fsmc_d14 sd_dat4 tmr_cptr1 gpio_47 pl_gpio_46/a11 sd_dat3 sd_dat3 emi_d15/ fsmc_d15 sd_dat3 tmr_clk4 gpio_46 pl_gpio_45/b10 sd_dat2 sd_dat2 uart1_dcd sd_dat2 tmr_clk3 gpio_45 pl_gpio_44/a10 sd_dat1 sd_dat1 uart1_dsr sd_dat1 tmr_clk2 gpio_44 pl_gpio_43/e9 sd_dat0 sd_dat0 uart1_rts sd_dat0 tmr_clk1 gpio_43 pl_gpio_42/d9 reserved reserved 00 uart0_dtr gpio_42 pl_gpio_41/c9 reserved reserved 00 uart0_ri gpio_41 pl_gpio_40/b9 reserved reserved 00 uart0_dsr gpio_40 pl_gpio_39/a9 reserved reserved 00 uart0_dcd gpio_39 pl_gpio_38/a8 pwm0 pwm0 0 0 uart0_cts gpio_38 pl_gpio_37/b8 pwm1 pwm1 0 0 uart0_rts gpio_37 pl_gpio_36/c8 touch screen x 0 uart1_cts uart1_cts ssp0_cs4 gpio_36 pl_gpio_35/d8 reserved 0 uart1_dtr uart1_dtr ssp0_cs3 gpio_35 pl_gpio_34/e8 sd_led / pwm2 sd_led / pwm2 uart1_ri uart1_ri ssp0_cs2 gpio_34 table 11. pl_gpio multiplexing scheme (continued) pl_gpio_# / ball number configuration mode (enabl ed by programmer model control register bits (2:0)) alternate function (enabled by ras select register) boot pins function in gpio alternative mode 12 3 4
pin description SPEAR320 38/73 doc id 16755 rev 5 pl_gpio_33/e7 can0_tx can0_tx can0_tx uart1_dcd basgpio5 gpio_33 pl_gpio_32/d7 can0_rx can0_rx can0_rx uart1_dsr basgpio4 gpio_32 pl_gpio_31/c7 can1_tx can1_tx can1_tx uart1_rts basgpio3 gpio_31 pl_gpio_30/b7 can1_rx can1_rx can1_rx basgpio2 gpio_30 pl_gpio_29/a7 uart1_tx uart1_tx uart1_tx uart1_tx basgpio1 gpio_29 pl_gpio_28/a6 uart1_rx uart1_rx uart1_rx uart1_rx basgpio0 gpio_28 pl_gpio_27/b6 smii0_tx 0 smii0_tx smii0_tx mii0_txclk gpio_27 pl_gpio_26/a5 smii0_rx 0 smii0_rx smii0_rx mii0_txd0 gpio_26 pl_gpio_25/c6 smii1_tx 0 0 smii1_tx mii0_txd1 gpio_25 pl_gpio_24/b5 smii1_rx 0 0 smii1_rx mii0_txd2 gpio_24 pl_gpio_23/a4 smii_sync 0 smii_sync smii_sync mii0_txd3 gpio_23 pl_gpio_22/d6 smii_clkout 0 smii_clkout smii_clkout mii0_txen gpio_22 pl_gpio_21/c5 smii_clkin 0 smii_clkin smii_clkin mii0_txer gpio_21 pl_gpio_20/b4 ssp1_mosi 0 0 ssp1_mosi mii0_rxclk gpio_20 pl_gpio_19/a3 ssp1_clk 0 0 ssp1_clk mii0_rxdv gpio_19 pl_gpio_18/d5 ssp1_ss0 0 0 ssp1_ss0 mii0_rxer gpio_18 pl_gpio_17/c4 ssp1_miso 0 0 ssp1_miso mii0_rxd0 gpio_17 pl_gpio_16/e6 ssp2_mosi 0 0 0 mii0_rxd1 gpio_16 pl_gpio_15/b3 ssp2_clk 0 pwm0 pwm0 mii0_rxd2 gpio_15 pl_gpio_14/a2 ssp2_ss0 0 pwm1 pwm1 mii0_rxd3 gpio_14 pl_gpio_13/a1 ssp2_miso 0 pwm2 pwm2 mii0_col gpio_13 pl_gpio_12/d4 pwm3 0 pwm3 pwm3 mii0_crs gpio_12 pl_gpio_11/e5 smii_mdio 0 smii_mdio smii_mdio mii0_mdc gpio_11 pl_gpio_10/c3 smii_mdc 0 smii_mdc smii_mdc mii0_mdio gpio_10 pl_gpio_9/b2 0 0 0 0 ssp0_mosi gpio_9 pl_gpio_8/c2 0 0 0 0 ssp0_clk gpio_8 pl_gpio_7/d3 0 0 0 0 ssp0_ss0 gpio_7 pl_gpio_6/b1 0 0 0 0 ssp0_miso gpio_6 pl_gpio_5/d2 0 0 0 0 i2c0_sda gpio_5 pl_gpio_4/c1 0 0 0 0 i2c0_scl gpio_4 pl_gpio_3/d1 0 0 0 0 uart0_rx gpio_3 pl_gpio_2/e4 0 0 0 0 uart0_tx gpio_2 table 11. pl_gpio multiplexing scheme (continued) pl_gpio_# / ball number configuration mode (enabl ed by programmer model control register bits (2:0)) alternate function (enabled by ras select register) boot pins function in gpio alternative mode 12 3 4
SPEAR320 pin description doc id 16755 rev 5 39/73 note: 1 table 11 cell s filled with 0 or 1 are unu s ed and unle ss otherwi s e configured a s alternate function or gpio, the corre s ponding pin i s held at low or high level re s pectively by the internal logic. 2pin s s hared by emi and fsmc: depending on the ahb addre ss to be acce ss ed the pin s are u s ed for emi or fsmc tran s fer s . pl_gpio_1/e3 uart2_tx uart2_tx uart2_tx uart2_tx irda_rx gpio_1 pl_gpio_0/f3 uart2_rx uart2_rx uart2_rx uart2_rx irda_tx gpio_0 pl_clk1/k17 clcp 0 i2c1_sda sd_led pl_clk1 gpio_98 pl_clk2/j17 sd_clk sd_clk i2c1_scl sd_clk pl_clk2 gpio_99 pl_clk3/j16 sd_wp sd_wp 0 sd_wp pl_clk3 gpio_100 pl_clk4/h17 sd_cmd sd_cmd 0 sd_cmd pl_clk4 gpio_101 table 11. pl_gpio multiplexing scheme (continued) pl_gpio_# / ball number configuration mode (enabl ed by programmer model control register bits (2:0)) alternate function (enabled by ras select register) boot pins function in gpio alternative mode 12 3 4 table 12. table shading shading pin group fsmc fsmc pins: nand flash emi emi pins clcd color lcd controller pins touchscreen touchscreen pins uart uart pins can can pins ethernet mac mii/smii ethernet mac pins sdio/mmc sd card controller pins pwm timers pulse-width modu lator timer module pins gpt timer pins irda irda pins ssp ssp pins i2c i2c pins standard parallel port standard parallel port pins
pin description SPEAR320 40/73 doc id 16755 rev 5 4.4 pl_gpio pin sharing for debug modes in some cases the pl_gpio pins may be used in different ways for debugging purposes. there are three different cases (see also ta b l e 13 ): 1. case 1 - all the pl_gpio get values from boundary scan registers during ex-test instruction of jtag . typically this configuration is used to verify correctness of the soldering process during the production flow . 2. case 2 - all the pl_gpio maintain their original meaning but the jtag interface is connected to the processor. this configurat ion is useful during the development phase but offers only "static" debug. 3. case 3 - some pl_gpio, as shown in ta bl e 13: ball s haring during debug , are used to connect the etm9 lines to an external box. this configuration is typically used only during the development phase. it offers a very powerful debug capability. when the processor reaches a breakpoint it is possible, by analyzing the trace buffer, to understand the reason why the processor has reached the break. table 13. ball sharing during debug signals case 1 - no debug case 2 - static debug case 3 - full debug te s t [ 0 ] 0 1 0 te s t [ 1 ] 0 0 1 test[2] 0 0/1 0/1 test[3] 0 0/1 0/1 test[4] 1 0/1 0/1 ntrst ntrst_bscan ntrst_arm ntrst_arm tck tck_bscan tck_arm tck_arm tms tsm_bscan tms_arm tsm_arm tdi tdi_bscan tdi_arm tdi_arm tdo tdo_bscan tdo_arm tdo_arm pl_gpio[97] bsr value original meaning arm_trace_clk pl_gpio[96] bsr value original meaning arm_trace_pkta[0] pl_gpio[95] bsr value original meaning arm_trace_pkta[1] pl_gpio[94] bsr value original meaning arm_trace_pkta[2] pl_gpio[93] bsr value original meaning arm_trace_pkta[3] pl_gpio[92] bsr value original meaning arm_trace_pktb[0] pl_gpio[91] bsr value original meaning arm_trace_pktb[1] pl_gpio[90] bsr value original meaning arm_trace_pktb[2] pl_gpio[89] bsr value original meaning arm_trace_pktb[3] pl_gpio[88] bsr value original meaning arm_trace_synca pl_gpio[87] bsr value original meaning arm_trace_syncb pl_gpio[86] bsr value original meaning arm_pipestata[0] pl_gpio[85] bsr value original meaning arm_pipestata[1]
SPEAR320 pin description doc id 16755 rev 5 41/73 pl_gpio[84] bsr value original meaning arm_pipestata[2] pl_gpio[83] bsr value original meaning arm_pipestatb[0] pl_gpio[82] bsr value original meaning arm_pipestatb[1] pl_gpio[81] bsr value original meaning arm_pipestatb[2] pl_gpio[80] bsr value original meaning arm_trace_pkta[4] pl_gpio[79] bsr value original meaning arm_trace_pkta[5] pl_gpio[78] bsr value original meaning arm_trace_pkta[6] pl_gpio[77] bsr value original meaning arm_trace_pkta[7] pl_gpio[76] bsr value original meaning arm_trace_pktb[4] pl_gpio[75] bsr value original meaning arm_trace_pktb[5] pl_gpio[74] bsr value original meaning arm_trace_pktb[6] pl_gpio[73] bsr value original meaning arm_trace_pktb[7] pl_gpio[72:0] table 13. ball sharing during debug (continued) signals case 1 - no debug case 2 - static debug case 3 - full debug
memory map SPEAR320 42/73 doc id 16755 rev 5 5 memory map table 14. SPEAR320 main memory map start address end address peripheral description 0x0000.0000 0x3fff.ffff external dram low power ddr or ddr2 0x4000.0000 0xbfff.ffff - reconfigurable array subsystem (see ta bl e 1 5 ) 0xc000.0000 0xcfff.ffff - reserved 0xd000.0000 0xd007.ffff uart0 0xd008.0000 0xd00f.ffff adc 0xd010.0000 0xd017.ffff ssp0 0xd018.0000 0xd01f.ffff i2c0 0xd020.0000 0xd07f.ffff - reserved 0xd080.0000 0xd0ff.ffff jpeg codec 0xd100.0000 0xd17f.ffff irda 0xd180.0000 0xd1ff.ffff - reserved 0xd280.0000 0xd7ff.ffff sram static ram shared memory (8 kbytes) 0xd800.0000 0xe07f.ffff - reserved 0xe080.0000 0xe0ff.ffff ethernet controller mac 0xe100.0000 0xe10f.ffff usb 2.0 device fifo 0xe110.0000 0xe11f.ffff usb 2.0 de vice configuration registers 0xe120.0000 0xe12f.ffff usb 2.0 device plug detect 0xe130.0000 0xe17f.ffff - reserved 0xe180.0000 0xe18f.ffff usb2.0 ehci 0-1 0xe190.0000 0xe19f.ffff usb2.0 ohci 0 0xe1a0.0000 0xe20f.ffff - reserved 0xe210.0000 0xe21f.ffff usb2.0 ohci 1 0xe220.0000 0xe27f.ffff - reserved 0xe280.0000 0xe28f.ffff ml usb arb configuration register 0xe290.0000 0xe7ff.ffff - reserved 0xe800.0000 0xefff.ffff - reserved 0xf000.0000 0xf00f.ffff timer0 0xf010.0000 0xf10f.ffff - reserved 0xf110.0000 0xf11f.ffff itc primary 0xf120.0000 0xf7ff.ffff - reserved 0xf800.0000 0xfbff.ffff serial flash memory
SPEAR320 memory map doc id 16755 rev 5 43/73 0xfc00.0000 0xfc1f.ffff serial flash controller 0xfc20.0000 0xfc3f.ffff - reserved 0xfc40.0000 0xfc5f.ffff dma controller 0xfc60.0000 0xfc7f.ffff dram controller 0xfc80.0000 0xfc87.ffff timer 1 0xfc88.0000 0xfc8f.ffff watchdog timer 0xfc90.0000 0xfc97.ffff real time clock 0xfc98.0000 0xfc9f.ffff basgpio 0xfca0.0000 0xfca7.ffff system controller 0xfca8.0000 0xfcaf.ffff miscellaneous registers 0xfcb0.0000 0xfcb7.ffff timer 2 0xfcb8.0000 0xfcff.ffff - reserved 0xfd00.0000 0xfeff.ffff - reserved 0xff00.0000 0xffff.ffff bootrom table 15. reconfigurable array subsystem memory map start address end address peripheral description 0x4000_0000 0x47ff_ffff emi 0x4800_0000 0x4bff_ffff - reserved 0x4c00_0000 0x5fff_ffff fsmc 0x6000_0000 0x6fff_ffff - reserved 0x7000_0000 0x7fff_ffff sdio 0x8000_0000 0x8000_3fff boot memory 0x8000_4000 0x8fff_ffff - reserved 0x9000_0000 0x9fff_ffff clcd 0xa000_0000 0xa0ff_ffff parallel port 0xa100_0000 0xa1ff_ffff can0 0xa200_0000 0xa2ff_ffff can1 0xa300_0000 0xa3ff_ffff uart1 0xa400_0000 0xa4ff_ffff uart2 0xa500_0000 0xa5ff_ffff ssp1 0xa600_0000 0xa6ff_ffff ssp2 0xa700_0000 0xa7ff_ffff i2c1 0xa800_0000 0xa8ff_ffff quad pwm timer 0xa900_0000 0xa9cf_ffff gpio table 14. SPEAR320 main memory map (continued) start address end address peripheral description
memory map SPEAR320 44/73 doc id 16755 rev 5 0xa9d0_0000 0xa9ff_ffff - reserved 0xaa00_0000 0xaaff_ffff smii0 0xab00_0000 0xabff_ffff smii1/mii 0xac00_0000 0xb2ff_ffff - reserved 0xb300_0000 0xbfff_f fff ahb interface table 15. reconfigurable array subsystem memory map (continued) start address end address peripheral description
SPEAR320 electrical characteristics doc id 16755 rev 5 45/73 6 electrical characteristics 6.1 absolute maximum ratings this product contains devices to protect the in puts against damage due to high/low static voltages. however it is advisable to take normal precaution to avoid application of any voltage higher/lower than the specified maximum/minimum rated voltages. the absolute maximum rating is the maximum stress that can be applied to a device without causing permanent damage. however, extended exposure to minimum/maximum ratings may affect long-ter m device reliability. 6.2 maximum power consumption note: the s e value s take into con s ideration the wor s t ca s e s of proce ss variation and voltage range and mu s t be u s ed to de s ign the power s upply s ection of the board. table 16. absolute maximum ratings symbol parameter minimum value maximum value unit v dd 1.2 supply voltage for the core - 0.3 1.44 v v dd 3.3 supply voltage for the i/os - 0.3 3.9 v v dd 2.5 supply voltage for the analog blocks - 0.3 3 v v dd 1.8 supply voltage for the dram interface - 0.3 2.16 v v dd rtc rtc supply voltage -0.3 2.16 v t stg storage temperature -55 150 c t j junction temperature -40 125 c table 17. maximum power consumption symbol description max unit i dd(1.2vsupply) current consumption of v dd 1.2 supply voltage for the core 400 ma i dd(1.8vsupply) current consumption of v dd 1.8 supply voltage for the dram interface (1) 1. peak current with linux memory test (50% write and 50% read) plus dma reading memory. 150 ma i dd(rtc) current consumption of rtc supply voltage 8 a i dd(2.5vsupply) current consumption of 2.5v supply voltage for the analog blocks 30 ma i dd(3.3vsupply) current consumption of 3.3v supply voltage for the i/os (2) 2. with 30 logic channels connected to the dev ice and simultaneously switching at 10 mhz. 12 ma p d maximum power consumption (3) 930 mw
electrical charac teristics SPEAR320 46/73 doc id 16755 rev 5 6.3 dc electrical characteristics the recommended operating conditions are listed in the following table: 6.4 overshoot and undershoot this product can support the following values of overshoot and undershoot. if the amplitude of the overshoot/undershoo t increases (decreases), the ratio of overshoot/undershoot width to the pulse width decreases (increases). the formula relating the two is: amplitude of os/us = 0.75*(1- ratio of os (or us) duration with respect to pulse width) note: the value of over s hoot/under s hoot s hould not exceed the value of 0.5 v. however, the duration of the over s hoot/under s hoot can be increa s ed by decrea s ing it s amplitude. 3. based on bench measurements for worst case silic on under worst case operating conditions. devices tested with operating system running, cpu and ddr2 running at 333 mhz, ddr2 driven by pll2, sdram and all on-chip peripherals and internal modules enabled. 1.2 v current and power are primarily dependent on the applications running and the use of internal chip functions (dma, usb, ethernet, and so on). 3.3 v current and power are primarily dependent on the capacitive loading, fre q uency, and utilization of the external buses. table 18. recommended operating conditions symbol parameter min typ max unit v dd 1.2 supply voltage for the core 1.14 1.2 1.3 v v dd 3.3 supply voltage for the i/os 3 3.3 3.6 v v dd 2.5 pll supply voltage (1) 1. for power supply filtering it is re q uired to add an external ferrite inductor. 2.25 2.5 2.75 v v dd 2.5 oscillator supply voltage 2.25 2.5 2.75 v v dd 1.8 supply voltage for dram interface 1.70 1.8 1.9 v v dd rtc rtc supply voltage 1.3 1.5 1.8 v t o operating temperature -40 85 c table 19. overshoot and undershoot specifications parameter 3v3 i/os 2v5 i/os 1v8 i/os amplitude 500 mv 500 mv 500 mv ratio of overshoot (or unders hoot) duration with respect to pulse width 1/3 1/3 1/3
SPEAR320 electrical characteristics doc id 16755 rev 5 47/73 6.5 3.3v i/o characteristics the 3.3 v i/os are compliant with jedec standard jesd8b. 6.6 lpddr and ddr2 pin characteristics table 20. low voltage ttl dc input specification (3 v< v dd <3.6 v) symbol parameter min max unit v il low level input voltage 0.8 v v ih high level input voltage 2 v v hyst schmitt trigger hysteresis 300 800 mv table 21. low voltage ttl dc output specification (3 v< v dd <3.6 v) symbol parameter test condition min max unit v ol low level output voltage i ol = x ma (1) 1. maximum current load (iol) = 10 ma for pl_gpio and pl_clk pins. for the iol max value of dedicated pins, refer to chapter 4: pin de s cription . 0.3 v v oh high level output voltage i oh = -x ma (1) v dd - 0.3 v table 22. pull-up and pull-down characteristics symbol parameter test condition min max unit r pu e q uivalent pull-up resistance v i = 0 v 29 67 k r pd e q uivalent pull-down resistance v i = v dde 3v3 29 103 k table 23. dc characteristics symbol parameter test condition min max unit v il low level input voltage sstl18 -0.3 v ref -0.125 v v ih high level input voltage sstl18 v ref +0.125 v dde 1v8+0.3 v v hyst input voltage hysteresis 200 mv table 24. driver characteristics symbol parameter min typ max unit r o output impedance 45
electrical charac teristics SPEAR320 48/73 doc id 16755 rev 5 6.7 power up sequence it is recommended to power up the power supplies in the order shown in figure 4 . v dd 1.2 is brought up first, followed by v dd 1.8, then v dd 2.5 and finally v dd 3.3 . the minimum time ( t) between each power up is >0 s. figure 4. power-up sequence table 25. on die termination symbol parameter min typ max unit rt1 termination value of resistance for on die termination 75 rt2 termination value of resistance for on die termination 150 table 26. reference voltage symbol parameter min typ max unit v refin voltage applied to core/pad 0.49 * v dde 0.500 * v dde 0.51 * v dde v v dd 1.2 v dd 1.8 v dd 2.5 v dd 3.3 power-up sequence t t t
SPEAR320 electrical characteristics doc id 16755 rev 5 49/73 6.8 removing power supplies for power saving it is recommended to remove the the power supplies in the order shown in figure 5 . so v dd 3.3 supply is to be removed first, then the v dd 2.5 supply, followed by the v dd 1.8 supply and last the v dd 1.2 . the minimum time ( t) between each power down is >0 s. figure 5. power-down sequence 6.9 power on reset (mreset) the mreset must remain active for at least 10 ms after all the power supplies are in the correct range and should become active in no more than 10 s when one of the power supplies goes out of the correct range. power-down sequence v dd 1.2 v dd 1.8 v dd 2.5 v dd 3.3 t t t
timing requirements SPEAR320 50/73 doc id 16755 rev 5 7 timing requirements note: signal tran s ition level s u s ed for timing mea s urement s are 0.2*vdd and 0.8*vdd. 7.1 external interrupt timing characteristics 7.2 reset timing characteristics note: warm re s et i s generated by writing any value to the sy s tem controller sysstat regi s ter. 7.3 ddr2 timing characteristics the characterization timing is done considering an output load of 10 pf on all the ddr pads. the timing parameters list ed are defined by jedec for ddr memories. ddr memories whose parameters are within the ranges defined in ta b l e 29 , ta bl e 30 and ta b l e 31 can be interfaced with SPEAR320. read cycle timing apply to dqs and dq input to spear. write cycle timings refer to dqs and dq output to spear. table 27. pl_gpio external interrupt input timing symbol description min unit tint minimum width for rising edge interrupt pulse 24 ns table 28. cold (power-on) reset symbol description min unit trp mreset pin active low state duration 10 ms
SPEAR320 timing requirements doc id 16755 rev 5 51/73 7.3.1 ddr2 read cycle timings figure 6. ddr2 read cycle waveforms 7.3.2 ddr2 write cycle timings figure 7. ddr2 write cycle waveforms table 29. ddr2 read cycle timings symbol description min max unit t ck ddr_mem_clkp/clkn cycle time 3 ns t dqsq dqs to dq input setup time 0 0.25t ck +0.4 ns t qh dqs to dq input hold time 0.25t ck +0.7 0.5t ck ns t dqsq t qh t qh t dqsq t dqsq ddr_mem_dqs ddr_mem_dq ddr_mem_clkp/ ddr_mem_clkn t ck ddr_mem_dqs ddr_mem_dq ddr_mem_clkp/ ddr_mem_clkn t ds t dh t dh t ds t ds t dh t dqss
timing requirements SPEAR320 52/73 doc id 16755 rev 5 7.3.3 ddr2 command timings figure 8. ddr2 command waveforms table 30. ddr2 write cycle timings symbol description min max unit t dqss positive dqs latching edge to associated ck edge -0.5 0.5 ns t ds dq & dqm output setup time relative to dqs 0 0.25t ck ? 0.76 ns t dh dq & dqm output hold time relative to dqs 0 0.25t ck ? 0.84 ns table 31. ddr2 command timings symbol description min max unit t is address and control output setup time 0 0.5t ck ? 0.5 ns t ih address and control output hold time 0 0.5t ck ? 0.59 ns t is t ih clk address and commands
SPEAR320 timing requirements doc id 16755 rev 5 53/73 7.4 clcd timing characteristics the characterization timing is done considering an output load of 10 pf on all the outputs. the clcd has a wide variety of configurations and setting and the parameters change accordingly. figure 9 and ta b l e 32 specify the clock to output delay. figure 9. clcd waveform table 32. clcd timings symbol description min max unit t ck clcp clock period 20.83 41.66 ns t d clcp to clcd output data delay 0.97 3.74 ns t ck t d cld[23:0], clac, clle, cllp, clfp, clpower clcp
timing requirements SPEAR320 54/73 doc id 16755 rev 5 7.5 i 2 c timing characteristics the characterization timing is done using primetime considering an output load of 10 pf on scl and sda. figure 10. output signal waveforms for i 2 c signals the timings of the high and low level of scl (t sclhigh and t scllow ) are programmable. table 33. timing characteristics for i 2 c in high-speed mode parameter min unit t su-sta 157.6 ns t hd-sta 325.9 t su-dat 314.0 t hd-dat 0.8 t su-sto 637.7 t hd-sto 4742.2 table 34. timing characteristics for i 2 c in fast speed mode parameter min unit t su-sta 637.6 ns t hd-sta 602.2 t su-dat 1286.1 t hd-dat 0.8 t su-sto 637.7 t hd-sto 4742.2
SPEAR320 timing requirements doc id 16755 rev 5 55/73 note: the timing s s hown in figure 10 depend on the programmed value of t sclhigh and t scllow, s o the value s pre s ent in the three table s here above have been calculated u s ing the minimum programmable value s of : ic_hs_scl_hcnt=19 and ic_hs_scl_lcnt=53 regi s ter s (for high-speed mode); ic_fs_scl_hcnt=99 and ic_fs_scl_lcnt=215 regi s ter s (for fa s t-speed mode); ic_ss_scl_hcnt=664 and ic_ss_scl_lcnt=780 regi s ter s (for standard-speed mode). the s e minimum value s depend on the ahb clock frequency, which i s 166 mhz. 7.6 fsmc timing characteristics the characterization timing is done using primetime considering an output load of 3 pf on the data, 15 pf on fsmc_csx, fsmc_re and fsmc_we and 10 pf on fsmc_addr_le and fsmc_cmd_le. 7.6.1 nand flash configuration figure 11. output command signal waveforms for nand flash table 35. timing characteristics for i 2 c in standard speed mode parameter min unit t su-sta 4723.6 ns t hd-sta 3991.9 t su-dat 4676.1 t hd-dat 0.8 t su-sto 4027.7 t hd-sto 4742.2 f s mc_c s x f s mc_we f s mc_dx comm a nd t cle t we t io f s mc_cmd_le
timing requirements SPEAR320 56/73 doc id 16755 rev 5 figure 12. output address signal waveforms for nand flash figure 13. in/out data address signal waveforms for nand flash note: value s in ta b l e 36 are referred to the common internal s ource clock which ha s a period of t hclk = 6 n s . table 36. timing characteristics for nand flash parameter min max t cle -3.9 2.8 t ale -4.2 2.6 t we (programmable by the tset bits in the fsmc registers) (((tset+1) * t hclk ) - 3 ns) (((tset+1) * t hclk ) + 3 ns) t re (programmable by the tset bits in the fsmc registers) (((tset+1) * t hclk ) - 3 ns) (((tset+1) * t hclk ) + 3 ns) t io (programmable by the thiz bits in the fsmc registers) (((thiz +1) * t hclk ) - 3 ns) (((thiz +1) * t hclk )+ 3 ns) t read (programmable by the twait bits in the fsmc registers) ((twait+1)* t hclk f s mc_addr_le f s mc_c s x f s mc_we f s mc_dx addre ss t ale t we t io f s mc_c s x f s mc_we f s mc_dx (o u t) d a t a o u t t io f s mc_dx (in) f s mc_re t re -> io t we t re t read t nfio -> ff s
SPEAR320 timing requirements doc id 16755 rev 5 57/73 7.7 emi timing characteristics figure 14. emi read cycle waveforms with acknowledgement on emi_wait# note: the value s of t se , t enr , t dcs , t scs are programmable via the emi regi s ter s . note: value s in the above table are referred to the common internal s ource clock which ha s a period of t hclk = 6 n s . figure 15. emi write cycle waveforms with acknowledgement on emi_wait# note: the value s of t se , t enw , t dcs , t scs are programmable via the emi regi s ter s . emi_a emi_byten emi_d emi_csn# emi_oe# address byte enable data t se t scs t enr t dcs emi_wait# t cs->wait t wait table 37. emi timings for read cycle with acknowledgement on wait# symbol min t cs->wait t hclk t wait 4*t hclk emi_a emi_byten emi_d emi_csn# emi_we# write data byte enable data t se t scs t enw t dcs emi_wait# t cs ->t wait t wait
timing requirements SPEAR320 58/73 doc id 16755 rev 5 note: value s in the above table are referred to the common internal s ource clock which ha s a period of t hclk = 6 n s . figure 16. emi read cycle waveforms without acknowledgement on emi_wait# note: the value s of t se , t enr , t dcs , t scs are programmable via the emi regi s ter s . figure 17. emi write cycle waveforms without acknowledgement on emi_wait# note: the value s of t se , t enw , t dcs , t scs are programmable via the emi regi s ter s . table 38. emi timings for write cycle with acknowledgement on wait# symbol min t cs->wait t hclk t wait 4*t hclk emi_a emi_byten emi_d emi_csn# emi_oe# address byte enable data t se t scs t enr t dcs emi_a emi_byten emi_d emi_csn# emi_we# write data byte enable data t se t scs t enw t dcs
SPEAR320 timing requirements doc id 16755 rev 5 59/73 7.8 sdio timing characteristics figure 18. sdio timing diagram table 39. sdio timings symbol description min max unit t ck sd_clk clock period 20.8 41.6 ns t d sd_clk to sd output delay 6.14 7.79 t s setup time re q uirement for sd inputs 9.65 t h hold time re q uirement for sd inputs -1.9 t ck t d sd_clk sd_datx sd_wp sd_cmd sd_led sd_cd sd_datx (input) t s t h
timing requirements SPEAR320 60/73 doc id 16755 rev 5 7.9 mii ethernet mac 10/100 mbps timing characteristics the characterization timing is given for an output load of 5 pf on the mii tx clock and 10 pf on the other pads. 7.9.1 mii transmit timing specifications figure 19. mii tx waveforms note: to calculate the t setup value for the phy you have to con s ider the next t clk ri s ing edge, s o you have to apply the following formula: t setup = t clk - t max 7.9.2 mii receive timing specifications figure 20. mii rx waveforms table 40. mii tx timings symbol description min max unit t ck mii_txclk clock period 40 40 ns t d mii_txclk to mii output data delay -1 8.9 t d mii_txclk mii_txd0-mii_txd3, mii_txen, mii_txer t ck table 41. mii rx timings symbol description min max unit t ck mii_txclk clock period 40 40 ns t s setup time re q uirement for mii receive data 1.6 t h hold time re q uirement for mii receive data 0.7 mii_rxclk mii_rxd0-mii_rxd3 mii_rxer, mii_rxdv t s t h t ck
SPEAR320 timing requirements doc id 16755 rev 5 61/73 7.9.3 mdio timing specifications figure 21. mdc waveforms note: when mdio i s u s ed a s output the data are launched on the falling edge of the clock a s s hown in figure 21 . 7.10 smii ethernet mac timing characteristics figure 22. smii input/output timing waveform table 42. mdc timings symbol description min max unit t ck mdc clock 614.4 614.4 ns t d falling edge of mdc to mdio output delay 204 0.64 t s setup time re q uirement for mdio input 9.6 t h hold time re q uirement for mdio input -6.6 t d mdc t ck t h t s mdio(input) mdio (output) smii_tx t d smii_clkin t ck th smii_rx t s
timing requirements SPEAR320 62/73 doc id 16755 rev 5 caution: data in ta b l e 4 3 subject to smii functional issue de scribed in the SPEAR320 errata sheet. 7.11 smi - serial memory interface timing characteristics figure 23. smi i/o waveforms table 43. smii timings symbol description min max unit t ck smii clock 8 8 ns t s setup time re q uirement for smii_rx -0.90 t h hold time re q uirement for receive smii_rx 2.904 t d smii_clkin to smii_tx output delay 4.12 14.17 table 44. smi timings symbol description min max unit t ck smi clock period 20 50 ns t d smi_clk to smi_dataout output delay -2.96 3.05 t s setup re q uirement for smi_datain 9.69 t h hold re q uirement for smi_datain -2.53 t csf min and max delay of falling edge of smi_cs_0 , 1 w.r.t smi_clk -3.0 2.9 t csr min and max delay of rising edge of smi_cs_0 , 1 w.r.t smi_clk -2.8 2.8 smi_clk smi_datain t s t h t ck t d t csf t csr smi_dataout smi_cs_0,1
SPEAR320 timing requirements doc id 16755 rev 5 63/73 7.12 ssp timing characteristics this module provides a programmable leng th shift register which allows serial communication with other ssp devices thro ugh a 3 or 4 wire interface (ssp_clk, ssp_miso, ssp_mosi and ssp_csn). the ssp supports the following features: master/slave mode operations chip-selects for interfacing to multiple slave spi devices. 3 or 4 wire interface (ssp_sck, ssp_miso, ssp_mosi and ssp_csn) single interrupt separate dma events for spi receive and transmit 16-bit shift register receive buffer register programmable character length (2 to 16 bits) programmable ssp clock fre q uency range 8-bit clock pre-scaler programmable clock phase (delay or no delay) programmable clock polarity note: the following table s and figure s s how the characteriza tion of the ssp u s ing the spi protocol. t = tc(clk) = ssp_clk period is e q ual to the ssp module mast er clock divided by a configurable divider. figure 24. ssp_clk timings table 45. timing requireme nts for ssp (all modes) no. parameters min max unit 1t c(clk) cycle time, ssp_clk 24 ? ns 2t w(clkh) pulse duration, ssp_clk high 0.49*to 0.51*to ns 3t w(clkl) pulse duration, ssp_clk low 0.49*to 0.51*to ns
timing requirements SPEAR320 64/73 doc id 16755 rev 5 7.12.1 spi master mode timings (clock phase = 0) figure 25. spi master mode external timing (clock phase = 0) table 46. timing requirements for spi master mode (clock phase = 0) no. parameters min max unit 4t su(div-clkl) setup time, miso (input) valid before ssp_clk (output) falling edge clock polarity = 0 -0.4 -0.3 ns 5t su(div-clkh) setup time, miso (input) valid before ssp_clk (output) rising edge clock polarity = 1 -0.4 -0.3 ns 6t h(clkl-div) hold time, miso (input) valid after ssp_clk (output) falling edge clock polarity = 0 0.9 1.7 ns 7t h(clkh-div) hold time, miso (input) valid after ssp_clk (output) rising edge clock polarity = 1 0.9 1.7 ns table 47. switching characteristics over recommended operating conditions for spi master mode (clock phase =0 ) no. parameters min max unit 8t d(clkh-dov) delay time, ssp_clk (output) rising edge to mosi (output) transition clock polarity = 0 -3.1 2.2 ns 9t d(clkl-dov) delay time, ssp_clk (output) falling edge to mosi (output) transition clock polarity = 1 -3.1 2.2 ns 10 t d(enl-clkh/l) delay time, ssp_csn (output) falling edge to first ssp_clk (output) ri sing or falling edge tns 11 td (clkh/l-enh) delay time, ssp_clk (output) rising or falling edge to ssp_csn (output) rising edge t/2 ns ssp_csn ssp_sclk (clock polarity = 0) ssp_sclk (clock polarity = 1) ssp_miso (input) ssp_mosi (output)
SPEAR320 timing requirements doc id 16755 rev 5 65/73 7.12.2 spi master mode timings (clock phase = 1) figure 26. spi master mode external timing (clock phase = 1) table 48. timing requirements for spi master mode (clock phase = 1) no. parameters min max. unit 13 t su(div-clkl) setup time, miso (input) valid before ssp_clk (o utput) rising edge clock polarity = 0 -0.4 -0.3 ns 14 t su(div-clkh) setup time, miso (input) valid before ssp_clk (o utput) falling edge clock polarity = 1 -0.4 -0.3 ns 15 t h(clkl-div) hold time, miso (input)valid after ssp_clk (output) rising edge clock polarity = 0 0.9 1.7 ns 16 t h(clkh-div) hold time, miso (input) valid after ssp_clk (output) falling edge clock polarity = 1 0.9 1.7 ns table 49. switching characteristics over recommended operating conditions for spi master mode (clock phase = 1) no. parameters min max unit 17 t d(clkh-dov) delay time, ssp_clk (output) falling edge to mosi (output) transition clock polarity = 0 -3.1 2.2 ns 18 t d(clkl-dov) delay time, ssp_clk (output) rising edge to mosi (output) transition clock polarity = 1 -3.1 2.2 ns 19 t d(enl-clkh/l) delay time, ssp_csn (output) falling edge to first ssp_clk (output) ri sing or falling edge t/2 ns 20 t d(clkh/l-enh) delay time, ssp_clk (outpu t) rising or falling edge to ssp_csn (o utput) rising edge tns
timing requirements SPEAR320 66/73 doc id 16755 rev 5 7.13 uart timing characteristics figure 27. uart transmit and receive timings where (1) b = uart baud rate table 50. uart transmit timing characteristics s.no. parameters min max unit 1 uart0 maximum baud rate 3 mbps uart1/uart2 maximum baud rate 7 2 uart pulse duration transmit data (txd) 0.99b (1) b (1) ns 3 uart transmit start bit 0.99b (1) b (1) ns table 51. uart receive timing characteristics s.no. parameters min max units 4 uart pulse duration receive data (rxd) 0.97b (1) 1.06b (1) ns 5 uart receive start bit 0.97b (1) 1.06b (1) ns
SPEAR320 timing requirements doc id 16755 rev 5 67/73 7.14 adc characteristics table 52. 10-bit adc characteristics symbol parameters min typ max unit f adc_clk adc_clk fre q uency 3 14 mhz av dd adc supply voltage 2.5 v v refp positive reference voltage 2.5 v v refn negative reference voltage 0 v v iref internal reference voltage 1.95 2 2.05 v t startup startup time 50 s v ain input range (absolute) agnd - 0.3 avdd - 0.3 v conversion range v refn v refp c ain input capacitance 5 6.4 8 pf r ain input mux resistance (total e q uivalent samplin g resistance) 1.5 2 2.5 k t conv conversion time (f adc_clk =14 mhz) 1s conversion time 13 adc_clk cycles inl integral linearity error 1 lsb dnl differential linearity error 1 lsb
package information SPEAR320 68/73 doc id 16755 rev 5 8 package information in order to meet environmental re q uirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www. s t.com . ecopack ? is an st trademark. table 53. lfbga289 (15 x 15 x 1.7 mm) mechanical data dim. mm inches min. typ. max. min. typ. max. a 1.700 0.0669 a1 0.270 0.0106 a2 0.985 0.0387 a3 0.200 0.0078 a4 0.800 0.0315 b 0.450 0.500 0.550 0.0177 0.0197 0.0217 d 14.850 15.000 15.150 0.5846 0.5906 0.5965 d1 12.800 0.5039 e 14.850 15.000 15.150 0.5846 0.5906 0.5965 e1 12.800 0.5039 e 0.800 0.0315 f 1.100 0.0433 ddd 0.200 0.0078 eee 0.150 0.0059 fff 0.080 0.0031
SPEAR320 package information doc id 16755 rev 5 69/73 figure 28. lfbga289 package dimensions table 54. thermal resistance characteristics package jc ( c/w) jb ( c/w) ja ( c/w) (1) 1. measured on jesd51 2s2p test board. lfbga289 18.5 24.5 33
revision history SPEAR320 70/73 doc id 16755 rev 5 9 revision history table 55. document revision history date revision changes 12-nov-2009 1 initial release. 2-feb-2010 2 removed i2s feature. changed ?spi? to ?ssp? where applicable. updated figure 1: functional block diagram and figure 2: typical s y s tem architecture u s ing SPEAR320 . corrected figure 3: typical smii s y s tem . updated the feature s on the first page. updated section 3.14: gpio s . added table 10: pl_gpio pin de s cription . reviewed and updated the section 4.3: shared i/o pin s (pl_gpio s ) . added section 4.4: pl_gpio pin s haring for debug mode s . updated section 6.1: ab s olute maximum rating s . deleted the first footnote at the end of the table 17: maximum power con s umption and modified the text in footnote 3. on page 46 updated table 18: recommended operating condition s . added v dd rtc line in the ta b l e 1 6 : a b s olute maximum rating s and table 17: maximum power con s umption . updated table 24: driver characteri s tic s . deleted ?gmii? form section 7.9: mii ethernet mac 10/100 mbp s timing characteri s tic s and also ?1000 mbps?. added section 3.6: sdio contro ller/mmc card interface . updated section 7.12: ssp timing characteri s tic s . updated section 6.7: power up s equence and added section 6.8: removing power s upplie s for power s aving . separated electrical characteri s tic s and timing requirement s into two chapters. changed the title of section 6.5: 3.3v i/o characteri s tic s . added table 54: thermal re s i s tance characteri s tic s . changed all the uart numbering (from 1..3 to 0..2). uart baud rate changed in section 2: main feature s and section 4.3.2: configuration mode s from > 6 mbps into up to 6 mbps.
SPEAR320 revision history doc id 16755 rev 5 71/73 02-feb-2010 2 (continued) changed the baud rate for the uarts with hardware flow control from ?up to 460.8 kbaud? into ?up to 3 mbps?. table 15: reconfigurable array s ub s y s tem memory map : changed a typo error ?uart23? into ?uart2?. section 3.10: can controller : changed ?32 message objects (132 x 32 message ram)? to ?16 messa ge objects (136 x 16 message ram)?. corrected a typo error in the figure 13: in/out data addre ss s ignal waveform s for nand fla s h and figure 16: in/out data s ignal waveform s for 16-bit nand fla s h configuration . updated table 4: power s upply pin de s cription and added a note at the end of the table. corrected the voltage capable of rtc in the ta b l e 3 : m a s ter clock, rtc, re s et and 3.3 v comparator pin de s cription s . updated figures of section 7.6: fsmc timing characteri s tic s . updated figure 19: mii tx waveform s , figure 26: block diagram of mii tx pin s , figure 20: mii rx waveform s corrected the speed of uart1 and uart2 in section 3.18.2: uart1 from ?5 mbps? into ?6 mbps?. updated table 3: ma s ter clock, rtc, re s et and 3.3 v comparator pin de s cription s , table 7: usb pin de s cription and table 9: ddr pin de s cription minor text corrections. 18-nov-2010 3 corrected pin assignment of uart0_rts and cts in table 11: pl_gpio multiplexing s cheme added section 7.14: adc characteri s tic s changed max. speed of uart2 and uart3 in feature descriptions from 6 mbps to 7 mbps and updated table 50: uart tran s mit timing characteri s tic s on page 66 . 02-dec-2010 4 corrected sram size from 56 k to 8 kbytes in chapter 2: main feature s updated feature descriptions for the 3 uarts in section 3.18: uart s table 55. document revision history (continued) date revision changes
revision history SPEAR320 72/73 doc id 16755 rev 5 05-jul-2011 5 removed pu from descr iption of mreset in table 3: ma s ter clock, rtc, re s et and 3.3 v comparator pin de s cription s updated figures and tables in: ? section 6.7: power up s equence ? section 7.3: ddr2 timing characteri s tic s ? section 7.4: clcd timing characteri s tic s ? section 7.5: i 2 c timing characteri s tic s ? section 7.6: fsmc timing characteri s tic s ? section 7.9: mii ethernet mac 10/100 mbp s timing characteri s tic s ? section 7.10: smii ethernet mac timing characteri s tic s ? section 7.11: smi - serial memory interface timing characteri s tic s added section 7.7: emi timing characteri s tic s . added section 7.8: sdio timing characteri s tic s . updated table 52: 10-bit adc characteri s tic s . updated table 54: thermal re s i s tance characteri s tic s . added the t ck max value for clcp clock period in table 32: clcd timing s . updated figure 19: mii tx waveform s . replaced ?43.2 k ? by ?43.2 ? in section 4.1: required external component s ( usb_tx_rtune bullet). table 45: timing requirement s for ssp (all mode s ) : replaced column ? value ? by columns ? min ? and ? max ?. replaced ? clock pha s e = 1 ? by ? clock pha s e = 0 ? at the figure caption of figure 25 . section 4.1: required external component s : added new bullet ? dith_vdd_2v5: add a ferrite bead to ball m4 ?. added a footnote for v dd 2.5 at table 18: recommended operating condition s . updated the footnote at table 21: low voltage ttl dc output s pecification (3 v< v dd <3.6 v) . added a note at the beginning of chapter 7: timing requirement s added section 7.1: external interrupt timing characteri s tic s and section 7.2: re s et timing characteri s tic s . replaced ? embedded/cu s tom s elector ? by ? ras s elect regi s ter ? in figure 3: hierarchical multiplexing s cheme and table 11: pl_gpio multiplexing s cheme . replaced ? embedded ip s ? by ? alternate function s ? in figure 3: hierarchical multiplexing s cheme . replaced the fsmc pins naming in section 7.6: fsmc timing characteri s tic s , as follows: ? nfio by fsmc_dx (where x=0 to 15) ? nf_ce by fsmc_csx (where x= 0 to 3) ? nf_ale by fsmc_addr_le ?nf_we by fsmc_we ? nf_re by fsmc_re ? nf_cle by fsmc_cmd_le table 55. document revision history (continued) date revision changes
SPEAR320 doc id 16755 rev 5 73/73 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2011 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of SPEAR320

	To Download SPEAR320 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .