specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. 10709 ms/73099th (ot)/53098rm (ot) no.5792-1/7 LB1991V overview the LB1991V is a 3-phase brushless motor driver ic that is optimal for driving the dc fan motor. functions ? 3-phase full-wave voltage drive technique (120 voltage-linear technique) ? torque ripple correction circuit (overlap correction) ? speed control technique based on motor voltage and current control ? built-in fg comparators ? built-in thermal shutdown circuit specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit v cc 1 max 10 v v cc 2 max 11 v maximum supply voltage v s max 11 v applied output voltage v o max v s +2 v maximum output current i o max 1.0 a allowable power dissipation pd max independent ic 440 mw operating temperature topr -20 to +75 c storage temperature tstg -55 to +150 c allowable operating ranges at ta = 25 c parameter symbol conditions ratings unit v cc 1 v cc 1 v cc 2 2.7 to 6.0 v v cc 2 3.5 to 9.0 v supply voltage v s up to v cc 2v hall input amplitude v hall between hall effect element inputs 20 to 80 mvp-p monolithic digital ic for fan motor 3-phase brushless motor driver orderin g numbe r : en5792b
LB1991V no.5792-2/7 electrical characteristics at ta = 25 c, v cc 1 = 3v, v cc 2 = 4.75v, v s = 1.5v ratings parameter symbol conditions min typ max unit supply current v cc 1 current drain i cc 1 i out = 100ma 3 5 ma v cc 2 current drain i cc 2 i out = 100ma 7.0 10.0 ma v cc 1 quiescent current i cc 1q v stby = 0v 1.5 3.0 ma v cc 2 quiescent current i cc 2q v stby = 0v 100 a v s quiescent current i s q v stby = 0v 75 100 a vx1 high side residual voltage v xh 1 i out = 0.2a 0.15 0.22 0.29 v low side residual voltage v xl 1 i out = 0.2a 0.15 0.20 0.25 v vx2 high side residual voltage v xh 2 i out = 0.5a 0.25 0.40 v low side residual voltage v xl 2 i out = 0.5a 0.25 0.40 v output saturation voltage v o (sat) i out = 0.8a, sink + source 1.4 v overlap o.l r l = 39 ? 3, rangle = 20k ? *2 72 80 87 % high/low overlap difference ? o.l (average upper side overlap) ? (average lower side overlap) *2 -8 +8 % hall amplifiers input offset voltage v hoff design target *1 -5 +5 mv common-mode input voltage range v hcm rangle = 20k ? 0.95 2.1 v i/o voltage gain v gvh rangle = 20k ? 25.5 28.5 31.5 db standby pin high-level voltage v sth 2.5 v low-level voltage v stl 0.4 v input current i stin v stby = 3v 25 40 a leakage current i stlk v stby = 0v -30 a frc pin high-level voltage v frch 2.5 v low-level voltage v frcl 0.4 v input current i frcin v frc = 3v 25 30 a leakage current i frclk v frc = 0v -30 a vh hall supply voltage v hall i h = 5ma, vh(+) ? vh( ? ) 0.85 0.95 1.05 v ( ? ) pin voltage v h ( ? ) i h = 5ma 0.81 0.88 0.95 v fg comparator input offset voltage v fgoff -3 +3 mv input bias voltage i bfg v fgin + = v fgin ? = 1.5v 500 na input bias current offset ? i bfg v fgin + = v fgin ? = 1.5v -100 +100 na common-mode input voltage range v fgcm 1.2 2.5 v output high-level voltage v fgoh at the internal pull-up resistors 2.8 v output low-level voltage v fgol at the internal pull-up resistors 0.2 v voltage gain v gfg design target *1 100 db output current (sink) i fgos for the output pin low level 5 ma thermal shutdown operating temperature tsd design target *1 180 c temperature hysteresis ? tsd design target *1 20 c *1: design target values in the conditions column are not tested. *2: the standard for overlap is the value as measured.
LB1991V no.5792-3/7 package dimensions unit : mm (typ) 3175c pin assignment 1 v cc 1 2 v cc 2 3 v s 4 nc 5 u out 6 rf 7 v out 8 rf 16 15 14 13 12 11 10 9 fg in + u in 2 u in 1 stby 20 19 18 17 24 23 22 21 w out vh + vh ? a ngle fg out fg in ? frc gnd top view LB1991V v in 2 v in 1 w in 2 w in 1 truth table hall input source phase sink phase u v w frc v w h 1 w v h h l l u w h 2 w u h l l l u v h 3 v u h l h l w v h 4 v w l l h l w u h 5 u w l h h l v u h 6 u v l h l l note: the ?h? entries in the frc column indicate a voltage of 2. 50v or higher, and the ?l? entries indicate a voltage of 0.4v o r lower. (when v cc 1 is 3v.) at the hall inputs, for each phase a high-level input is th e state where the (+) input is 0.02v or higher than the ( ? ) input. similarly, a low-level input is the state where the (+) input is 0.02v or lower than the ( ? ) input. sanyo : ssop24(275mil) 7.8 5.6 7.6 0.22 0.65 (0.33) 12 13 24 1 0.5 0.15 1.5max 0.1 (1.3) -20 0 20 40 60 80 100 0 0.5 0.4 0.3 0.2 0.1 pd max -- ta 0.44 0.264 75 ambient temperature, ta -- c allowable power dissipation, pd max -- w
LB1991V no.5792-4/7 block diagram v cc 1 2 v cc 2 3v s 5 u out 6 rf 7 v out 8 rf 16 14 12 9 fg in + u in 2 u in 1 stby 20 19 18 17 23 22 21 w out vh + vh ? a ngle fg out fg in ? frc v in 2 v in 1 w in 2 w in 1 u v w u-v v-w w-u 13 gnd +vf sbd sbd sbd tsd b b b 1 15 10 11 24 v cc 1 v cc 2 2 r1 v s /2 r1 r1 r2 vx v s /4 r2 v o 1 r4 r3 vx+ 1.5 r5 o.l v o 1 v o 2v o 3 r6 r6 (v s /2)+ vx+vf v s ? vx ? vf+2 vx+vf r5 r5 r5 r5 r5 r5 v o 1= v s +( v s -vx)= v s -vx 1 4 1 4 1 2 r3 r3+r4 o.l= v o 3= v s + ? (vx+vf)+ v s + =v s ? vx ? vf+2 1 2 1 2 i=o.l v o 1/(1.5 r5) 3i 3i hall input synthesis (matrix) synthesized signal level shifters drive signal current generation block power to the hatch blocks is supplied from v cc 2. 0 current distribution hall amplifiers forward/ reverse switching upper/lower amplitude limiters fg amplifier 1.2v reference voltage and bias startup circuit bias supply hall power-supply voltage output circuit
LB1991V no.5792-5/7 pin function pin no. pin name pin function equivalent circuit 1 v cc 1 supply voltage for all circuits other than the ic internal output block and the amplitude control block. 2 v cc 2 supply voltage for the ic internal output control block and the amplitude control block. 3 v s motor drive power supply. the voltage applied to this pin must not exceed v cc 2. 5 u out u phase output. 7 v out v phase output. 9 w out w phase output. (these outputs include built-in spark killer diodes.) 6,8 rf ground for the output power transistors. 3 5 6 (8) 2 (7,9) v cc 2 v s rf 10k ? 5k ? 5k ? 1/2 v s 1/4 v s each out 10 vh + 11 vh ? hall element bias voltage supply. a voltage that is typically 0.95v is generated between the vh + and vh ? pins (when i h is 5ma). 11 1 v cc 1 vh ? 20k ? 10 vh + 20k ? a bout 1.9v about 0.9v 13 gnd ground for circuits other than the output transistor. the rf pin potential is the lowest output transistor potential. 14 frc forward/reverse selection. applications can select motor forward or reverse direction rotation using this pin. (this pin has hysteresis c haracteristics.) 15 stby selects the bias supply for all circuits other than the fg comparators. the bias supply is cut when this pin is set to the low level. 14 v cc 1 frc 100k ? 50k ? 15 v cc 1 stby 100k ? 100k ? 16 17 u in 1 u in 2 u phase hall element input. the logic high level is the state where the in + voltage is greater than the in ? voltage. 18 19 v in 1 v in 2 v phase hall element input. the logic high level is the state where the in + voltage is greater than the in ? voltage. 20 21 w in 1 w in 2 w phase hall element input. the logic high level is the state where the in + voltage is greater than the in ? voltage. 12 angle hall input/output gain control. the gain is controlled by the resistor connected between this pin and ground. 16 v cc 1 4k ? 17 400 ? 400 ? 200 ? 4k ? 200 ? (18,20) (19,21) 0.3v 1 17 v cc 1 angle 200 ? 1.2v typ each input of 1 each input of 2 22 fg in + fg comparator non-inverting inputs. there is no internally applied bias. 23 fg in ? fg comparator inverting inputs. there is no internally applied bias. 24 fg out fg comparator outputs. there is an internal 20k ? resistor load. 1 v cc 1 24 200 ? 23 15k ? 200 ? 22 50k ? fg in ? fg in + 20k ? fg outn
LB1991V no.5792-6/7 overlap generation and calculation method 0 v xl v s v s a cd b v s ? v xh v v n v 180 v xh v s ? v xh o.l ( ? v xh ) v s 2 ? v xh v s 2 v xl v xl upper side residual voltage upper side clamp potential electrical angle lower side residual voltage lower side clamp potential time absolute voltage calculated center point overlap generation since the voltage generated in the amplitude control block is, taking the center point as the reference, 2 (1/2 v s ? v x ) on one side, the intersection point of the waveform will be (1/2 v s ? vx) from the center point. to clamp that waveform at (1/2 v s ? v x ) referenced to the center point the overlap must be: a/b 100 = 100 (%). overlap calculation ? upper side overlap calculated center point: v n = (v s ? v xh ? v xl ) 2 + v xl = (v s ? v xh + v xl ) 2 since a = v ? v n , b = v s ? v xh ? v n , the upper side overlap will be: = a b = v ? ((v s ? v xh + v xl )/2) v s ? v xh ? ((v s ? v xh + v xl )/2) 100 which can be calculated as: = 2v ? (v s ? v xh ) ? v xl (v s ? v xh ) ? v xl 100(%) ? lower side overlap since c = v n ? v , and d = v n ? v xl , the lower side overlap will be: = c d = ((v s ? v xh + v xl )/2) ? v ((v s ? v xh + v xl )/2) ? v xl 100 which can be calculated as: = (v s ? v xh ) + v xl ? 2v (v s ? v xh ) ? v xl 100(%)
LB1991V ps no.5792-7/7 sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probabi lity. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. test circuit LB1991V a sj im4 a sk im5 v stby v frc 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 sq sp so sn sm sl v h 3 v h 1 1k ? v h 2 1 f 15v la6358 100k ? v in f=1khz ? 50dbm v vm4 ss 1 2 1 2 1 2 sr 100k ? 0.1 f 1k ? 100k ? 1k ? a sw im7 a sv im6 12 st a sa a sb a sc v s 1.5v v cc 2 4.75v v fg 2 1 2 2 3 3 1 su v fg 1 v cc 1 3v i out 3 5ma im1 im2 im3 sd 39 ? 3 se sf 2 13 2 13 sg v vm1 i out 1 100ma 200ma 500ma 800ma v v vm2 vm5 sh 2 1 i out 2 4ma v vm3 s1 21 20k ? v cc 1=3v v cc 2=4.75v v s =1.5v v h 1=1.4v v h 2=4.75v v h 3=1.5v v frc =3v v stby =3v v fg 1=v fg 2=1.5v switch status: 0 : closed x : open the following hold unless otherwise specified: this catalog provides information as of january, 2009. specifications and information herein are subject to change without notice.
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