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june 2007 rev. 1 1/23 23 STSLVDSP27 8-bit low voltage serializer with 1.8v high speed dual differential line drivers and embedded dpll features sub-low voltage differential signaling: v od = 150mv with r t = 100 , c l = 10pf clock range: 4 to 27 mhz in parallel mode, byp = gnd operative frequency serial mode, byp = v dd ; din0 to dout, cl kin to clkout, f opr = 1 to 208 mhz max embedded dpll requires no external components output voltage rise and fall times t rvod = t fvod = 610ps typ at f opr = 208mhz high speed propagation delay times t plh ~t phl = 2.1ns typ at v dd = 3.0v; v io = 1.8v operating voltage range: v dd (opr) = 2.5v to 3.6v v io (opr) = 1.65v to 1.95v high impedance on driver outputs i oz = 1a max; en = gnd; v o = gnd or v io low voltage cmos input threshold (din0-din7, clkin, en, byp, dvo, dv1) v il = 0.3 x v dd max; v ih = 0.7 x v dd min 3.6v tolerant on all inputs (din0-din7, clkin, en, byp, dv0, dv1) lead-free flip-chip package smia ccp1 (mipi csi-1) compatible phy description the STSLVDSP27 is an 8:1 bit serializer with embedded dpll. the dual differential line drivers implement the electrical characteristics of sub-low voltage differential signaling (sublvds), bringing out the serialized data and related synchronous clock signal. the STSLVDSP27 serializer ic is provided with two power supply rails, v dd and v io . the first supply is related to the logic levels of the input data (din0-din7, clkin) and enables (en, byp, dv0, dv1) pins. v io provides the power supply to the output current drivers in the device. v io is always expected to be a nominal 1.8v. v dd depends on the application, but will always be equal to or higher than v io . in order to minimize static current consumption, it is possible to shut down the transmitters when the interface is not used by setting a power-down (en) pin. this operation reduces the maximum cu rrent consumption to 20a, making this device ideal for portable applications like mobile phones and portable battery equipment. simplified functionality can be reached using the byp select pin, which disables the internal dpll circuitry. when this pin is high the device can work with serialized signals from din0 input only. a synchronous clkin signal must be provided and it will be put-out using sub- lvds level by clkout port; the sub-lvds data will be put-out by dout port at a maximum frequency of 208mhz. this innovative device provides an optimized high-speed link solution from different cmos sensor devices (parallel or serial outputs) to more advanced graphic controllers in mobile phone applications. all inputs and outputs are equipped with protection circuits against static discharge, providing esd immunity from transient excess voltage. the STSLVDSP27 is designed for operation over the commercial temperature range -40c to 85c. flip-chip20 www.st.com order code part number temperature range package packaging STSLVDSP27bjr -40 to 85 c flip-chip20 (tape & reel) 3000 parts per reel
STSLVDSP27 2/23 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 test circuits and timing diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
STSLVDSP27 block diagram 3/23 1 block diagram figure 1. simplified block diagram typical application
pin configuration STSLVDSP27 4/23 2 pin configuration figure 2. pin configuration and logic diagra m (top view - bumps are on the other side) table 1. pin description pln n symbol name and function b1 din0 cmos parallel/serial data inputs a1, a2, a3, a4, b4, c4, d4 di n1-din7 cmos parallel data inputs d1, c1 dout+, dout- sublvds driver data outputs b3 clkin cmos parallel/serial clock input d3, c3 clkout+, clkout- sublvds driver clock outputs c2, d2 dv0, dv1 cmos data valid inputs b2 gnd ground e1 v dd main power supply voltage e2 v io sublvds bus output supply voltage e3 en cmos main chip enable input e4 byp cmos by-pass select input
STSLVDSP27 pin configuration 5/23 note: n:0..1; z = high impedance, x = don?t care note: n:0..1; z = high impedance, x = don?t care table 2. truth table (bypass functionality: din0 => dout, clkin => clkout; main chip enable (1) functionality) controls input differential outputs en byp dv0 dv1 din0 din1-7 clkin dout+ dout- clkout+ clkout- lxxxxxxzzzz hhxx l x l l h l h hhxx l xh l h h l hhxxhx l h l l h hhxxhxh h l h l 1. all differential outputs are put in high impedance vs gnd only; the internal dpll circuit is put in shutdown mode to obtain minimum power consumption. table 3. truth table (data valid functionality) controls input differential outputs en byp dv0 (1) dv1 (1) din0 din1-7 clkin dout+ dout- clkout+ clkout- hllxxxx h l h l hlxlxxx h l h l 1. an and gate is designed on data valid inputs (dv0, dv1) to enable the standard functionality; only when the dv0=dv1="h" the device will work ac cording to description in main page
maximum ratings STSLVDSP27 6/23 3 maximum ratings note: absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these condition is not implied. table 4. absolute maximum ratings symbol parameter value unit v dd supply voltage -0.5 to 4.6 v v io sublvds bus supply voltage -0.5 to 4.6 v v i dc input voltage (din0-din7, byp, clkin, en, dv0, dv1) -0.5 to 4.6 v v o dc output voltage (dout+,dout-,clkout+,clkout-) -0.5 to (v io + 0.5) v esd electrostatic discharge protection iec61000-4-2 contact r = 330 , c = 150pf (all pins vs gnd) 2 kv t stg storage temperature range -65 to +150 c table 5. recommended operating conditions symbol parameter min. typ. max. unit v dd main supply voltage (1) (2) 2.5 3.0 3.6 v v io sublvds bus supply voltage 1.65 1.80 1.95 v v dd_noise peak-to-peak permitted main supply voltage noise (2) 100 mv r t termination resistance (per pair differential output line) 80 100 120 c l termination capacitance (per line vs gnd pin) 10 pf t a operating ambient temperature range -40 85 c t j operating junction temperature range -40 125 c t r , t f rise and fall time (din0-din7, byp, clkin, en, dv0, dv1; 10% to 90%; 90% to 10%) 10 ns 1. v dd main supply voltage in serial mode (byp = v dd ) can be reduced down to 1.65v fo r typical 1.8v input signals 2. v dd main supply voltage in parallel m ode (byp = gnd) can reach 2.5v when v dd_noise = 100mv and v dd = 2.55v
STSLVDSP27 electrica l characteristics 7/23 4 electrical characteristics table 6. electrical characteristics (over recommended operating conditions unless otherwise noted. all typical values are at t a = 25c, and v dd = 3.0v, v io = 1.8v) symbol parameter test cond itions min. typ. max. unit v cm common mode output voltage ( figure 3. ) r t = 100 1% v io /2- 0.1 v io /2 v io /2+ 0.1 v v cm(ss) common mode output voltage change between logic state ("l" and "h") ( figure 5. ) r t = 100 1% -20 20 mv v cm(pp) common mode peak-to- peak output voltage change between logic state ("l" and "h") ( figure 5. ) r t = 100 1% -40 40 mv |v od | differential output voltage ( figure 3. ) r t = 100 1% 100 150 200 mv v od differential output voltage change between logic state ("l" and "h") r t = 100 1% -20 20 mv dc vod clock duty cycle@208mhz differential output voltage clkout+, clkout-, dout+, dout- r t = 100 1% byp=v dd ; en=v dd f clkin = 208mhz, f din0 = 208mhz 45 50 55 % i io driver output current clkout+, clkout-, dout+, dout- r t = 100 1% 1 1.5 2 ma r o driver output impedance (single ended) clkout+, clkout-, dout+, dout- ( figure 8. ) v cm = v io /2 + 100mv and v io /2 -100mv 40 100 140 d ro driver output impedance mismatch between r odout , r oclkout 10 %
electrical characteristics STSLVDSP27 8/23 i s supply current (i io + i dd ) en=v dd , byp=v dd or gnd, din0-din7=v dd or gnd no load (r t = ) 15 ma en=v dd , byp=v dd or gnd, din0-din7=v dd or gnd r t = 100 1% 15 en=v dd , byp=v dd (dpll="off") r t = 100 1%, c l = 10pf per line, dv0=dv1=v dd , f din0 and clkin = 208 mhz (v il and v ih levels) 12 en=v dd , byp=gnd(dpll="on") r t = 100 1%, c l = 10pf per line, dv0 = dv1= v dd , f clkout = 160mhz f din0-din7,clkin = 22 mhz (v il and v ih levels) 20 i soff shutdown supply current (i io + i dd ) en = gnd, v dd = 2.7v to 3.6v v io = 1.65v to 1.95v din0-din7, clkin, byp = gnd or v dd 20 a v ih high level input voltage (din0-din7, byp, clkin, en, dv0, dv1) v dd = 2.7v to 3.6v, v io = 1.65v to 1.95v 0.7xv dd 3.6 v v il low level input voltage (din0-din7, byp, clkin, en, dv0, dv1) v dd = 2.7v to 3.6v, v io = 1.65v to 1.95v 00.3xv dd v i ih high level input current (din0-din7, byp, clkin, en, dv0, dv1) v ih = 0.7 x v dd 1 a i il low level input current (din0-din7, byp, clkin, en, dv0, dv1) v il = 0.3 x v dd 1 a i oz high impedance output current clkout+,clkout-, dout+, dout- v o = 0 or v cc 1 a table 6. electrical characteristics (over recommended operating conditions unless otherwise noted. all typical values are at t a = 25c, and v dd = 3.0v, v io = 1.8v) symbol parameter test cond itions min. typ. max. unit
STSLVDSP27 electrica l characteristics 9/23 note: 1 50% v din to 50% v dout table 7. serial switching characteristics (dpll = "off", r t = 100 1%, c l = 10pf, over recommended operating conditions unless otherwise noted. typical values are referred to t a = 25c and v dd = 3.0v, v io = 1.8v) symbol parameter test conditions min. typ. max. unit t rvod rise time differential output voltage (20% to 80%) ( figure 4. ) t rdin = 4.9ns (10% to 90%); f din = 10mhz, pulsewidth din = 50ns 400 610 1000 ps t fvod fall time differential output voltage (80% to 20%) ( figure 4. ) t rdin = 4.2ns (90% to 10%); f din = 10mhz, pulsewidth din = 50ns 400 610 1000 ps t plhd differential propagation delay time (din to dout) (low to high) ( note: 1 ) ( figure 4. ) t rdin = 4.9ns (10% to 90%); t fdin = 4.2ns (90% to 10%); f din = 10mhz, pulsewidth din = 50ns 1.0 2.1 2.8 ns t phld differential propagation delay time (din to dout) (low to high) ( note: 1 ) ( figure 4. ) t fdin = 4.2ns (10% to 90%); f din = 10mhz, pulsewidth din = 50ns 1.0 2.1 2.8 ns t en enable delay time (en to dout: t plz , t phz ) ( figure 7. ) t ren = 2.0ns (10% to 90%); t fen = 2.0ns (90% to 10%) 20 s t dis disable delay time (en to dout: t plz , t phz ) ( figure 7. ) t ren = 2.0ns (10% to 90%); t fen = 2.0ns (90% to 10%) 1000 ns f opr operating frequency serial mode without dpll byp = v dd t rdin0,clkin =1ns (10% to 90%); t fdin0,clkin =1ns (90% to 10%) f din0,clkin = 208mhz pulsewidth din0,clkin = 2.4ns 1208mhz t skew1 differential skew between signals on each differential pair (t plhd - t phld ) t rdin = 4.9ns (10% to 90%); t fdin = 4.2ns (90% to 10%); f din = 10mhz, pulsewidth din = 50ns 150 ps t skew2 channel to channel skew between any two signals on each different differential pair ( figure 6. ) t rdin = 4.9ns (10% to 90%); t fdin = 4.2ns (90% to 10%); f din = 10mhz, pulsewidth din = 50ns 200 ps
electrical characteristics STSLVDSP27 10/23 table 8. parallel switching characteristics (dpll = "on", r t = 100 1%, c l = 10pf, over recommended operating conditions unless otherwise noted. typical values are referred to t a = 25c and v dd = 3.0v, v io = 1.8v) symbol parameter test conditions min. typ. max. unit t rvod rise time differential output voltage (20% to 80%) ( figure 4. ) t rdin = 4.9ns (10% to 90%); f din = 10mhz, pulsewidth din = 50ns 400 610 1000 ps t fvod fall time differential output voltage (80% to 20%) ( figure 4. ) t rdin = 4.2ns (90% to 10%); f din = 10mhz, pulsewidth din = 50ns 400 610 1000 ps t plhdin0 differential propagation delay time din0 (clkin to dout) (low to high) ( note 2 ) ( figure 10. ) t rdin0-din7,clkin =4.9ns (10% to 90%); t fdin0-din7,clkin = 4.2ns (90% to 10%); f din0-din7,clkin =22mhz, pulsewidth din = 50ns 8ns t phldin0 differential propagation delay time din0 (clkin to dout) (high to low) ( note 2 ) ( figure 10. ) t rdin0-din7,clkin =4.2ns (90% to 10%); t fdin0-din7,clkin = 4.2ns (90% to 10%); f din0-din7,clkin =22mhz, pulsewidth din = 50ns 8ns t plhdin7 differential propagation delay time din7 (clkin to dout) (low to high) ( note 2 ) ( figure 10. ) t rdin0-din7,clkin =4.9ns (10% to 90%); t fdin0-din7,clkin = 4.2ns (90% to 10%); f din0-din7,clkin =22mhz, pulsewidth din = 50ns 53 ns t phldin7 differential propagation delay time din7 (clkin to dout) (high to low) ( note 2 ) ( figure 10. ) t rdin0-din7,clkin =4.2ns (90% to 10%); t fdin0-din7,clkin = 4.2ns (90% to 10%); f din0-din7,clkin =10mhz, pulsewidth din = 50ns 53 ns t ocd differential propagation delay time (clkin to dout first positive edge) (low to high) ( figure 10. ) t rdin0-din7,clkin =4.9ns (10% to 90%); t fdin0-din7,clkin = 4.2ns (90% to 10%); f din0-din7,clkin =10mhz, pulsewidth din = 50ns 11 ns t su_clk set-up time (din0-din7, dv to clkin) (lh or hl to positive clkin edge) ( figure 11. ) t rdin0-din7,clkin =4.9ns (10% to 90%); t fdin0-din7,clkin = 4.2ns (90% to 10%); f din0-din7,clkin =4 to 22mhz, pulsewidth din = 50ns 12 ns t h_clk hold time (clkin to din0- din7, dv) (positive clkin edge to lh or hl din,dv transition) ( figure 11. ) t rdin0-din7,clkin =4.9ns (10% to 90%); t fdin0-din7,clkin =4.2ns (90% to 10%); f din0-din7,clkin =4 to 22mhz, pulsewidth din = 50ns 10 ns t en enable delay time (en to dout: t plz , t phz ) ( figure 7. ) t ren = 2.0ns (10% to 90%); t fen = 2.0ns (90% to 10%) 20 s t dis disable delay time (en to dout: t plz , t phz ) ( figure 7. ) t ren = 2.0ns (10% to 90%); t fen = 2.0ns (90% to 10%) 1000 ns f opr operating frequency parallel mode with dpll byp = gnd, f din0-din7,clkin =4 to 27mhz pulsewidth din0,clkin = 50% t rdin0,clkin =3ns (10% to 90%); t fdin0,clkin =3ns (90% to 10%) 427mhz
STSLVDSP27 electrica l characteristics 11/23 note: 1 50% v din to 50% v dout 2 50% clkin (positive edge) to 50% v dout (din0 will be referred to clkout first positive edge; din7 will be referred to clkout eighth positive edge) 3 power down can be guaranteed when v io =1.8v, en = gnd, if low impedance < 1m vs gnd is guaranteed on v dd pin f clkout clkout frequency parallel mode with dpll byp = gnd, f din0-din7,clkin =4 to 27mhz pulsewidth din0,clkin = 50% t rdin0,clkin =3ns (10% to 90%); t fdin0,clkin =3ns (90% to 10%) 32 216 mhz t skew1 differential skew between signals on each differential pair (t plhd - t phld ) t rdin = 4.9ns (10% to 90%); t fdin = 4.2ns (90% to 10%); f din = 10mhz, pulsewidth din = 50ns 150 ps t skew2 channel to channel skew between any two signals on each different differential pair ( figure 6. ) t rdin = 4.9ns (10% to 90%); t fdin = 4.2ns (90% to 10%); f din = 10mhz, pulsewidth din = 50ns 200 ps t dv data valid before clkout time ( figure 12. ) byp = gnd, f din0-din7,clkin =4 to 27mhz pulsewidth din0,clkin = 50% t rdin0,clkin =3ns (10% to 90%); t fdin0,clkin =3ns (90% to 10%) 1ns t dh data valid hold after clkout time ( figure 12. ) byp = gnd, f din0-din7,clkin =4 to 27mhz pulsewidth din0,clkin = 50% t rdin0,clkin =3ns (10% to 90%); t fdin0,clkin =3ns (90% to 10%) 2ns t plls dpll settling time (en to clkout) 50% lh en to 50% clkout (first negative edge) ( figure 9. ) t ren =2.0ns (10% to 90%) t fen =2.0ns (90% to 10%) dv0=dv1=v dd ; byp= gnd; din1- din7=v dd or gnd; f clkin =4 to 27mhz 70 s j cy-cy rms cycle-to-cycle jitter between clkin and clkout signals t rclkin = 4.9ns (10% to 90%); t fclkin = 4.2ns (90% to 10%); f clkin = 4 to 27mhz, pulsewidth clkin =50% 100 ps peak cycle-to-cycle jitter between clkin and clkout signals t rclkin = 4.9ns (10% to 90%); t fclkin = 4.2ns (90% to 10%); f clkin = 4 to 27mhz, pulsewidth clkin =50% 600 table 8. parallel switching characteristics (dpll = "on", r t = 100 1%, c l = 10pf, over recommended operating conditions unless otherwise noted. typical values are referred to t a = 25c and v dd = 3.0v, v io = 1.8v) symbol parameter test conditions min. typ. max. unit
electrical characteristics STSLVDSP27 12/23 table 9. capacitive characteristics symbol parameter test condition value unit v dd (v) t a = 25c min. typ. max. c in input capacitance (din0-din7, clkin, en, byp, dv0, dv1) 2.7 to 3.6 v io = 1.65v to 1.95v, v i = gnd or v dd 4pf
STSLVDSP27 test circuits and timing diagram 13/23 5 test circuits and timing diagram note: r t = 100 1% note: r t = 100 1%; c l = 10pf; t rdin = 4.9ns; t fdin = 4.2ns; f din = 10mhz; pulsewidth din = 50ns. figure 3. voltage and input current definition v cm = (v d+ + v d- )/2 figure 4. test circuit, timing and voltage definitions for differential output signal
test circuits and timing diagram STSLVDSP27 14/23 note: r t = 100 1%; c l = 10pf; t rdin = 4.9ns; t fdin = 4.2ns; f din = 10mhz; pulsewidth din = 50ns. note: r t = 100 1%; c l = 10pf; t rdin = 4.9ns; t fdin = 4.2ns; f din = 10mhz; pulsewidth din = 50ns figure 5. test circuit and definitions for the driver common mode output voltage figure 6. t skew2
STSLVDSP27 test circuits and timing diagram 15/23 note: r t = 100 1%; c l = 10pf; t rdin = 2.0ns; t fdin = 2.0ns; f en = 1mhz; pulsewidth din = 500ns note: r t = 100 1%; c l = 10pf v x+ = v d+(vcm=1.0v) - v d+(vcm=0.8v) ; v x- = v d-(vcm=1.0v) - v d-(vcm=0.8v) ; r 0+ = (r t /2 x v x+ )/(200mv - v x+ ); r 0- = (r t /2 x v x- )/(200mv - v x- ) figure 7. t en (t pzl , t pzh ); t dis (t phz , t plz ) figure 8. r o : driver output impedance
test circuits and timing diagram STSLVDSP27 16/23 note: during t plls test dv0=dv1=v dd figure 9. t plls
STSLVDSP27 test circuits and timing diagram 17/23 figure 10. general timing diagram (parallel mode) 0 < tocd < tclkin clkin din[0..7] tocd clkout dout dv[0..1] tclkin p 1 p n p 2 p n-1 p1: d0 p n : d7 p n+1 p n : d6 p n : d5 p n : d4 p n : d3 p n : d2 p n : d1 p n : d0 p n-1 : d4 p n-1 : d5 p n-1 : d6 p n-1 : d7 p 2 : d3 p 2 : d1 p 2 : d0 p 2 : d2 p 1 : d1 p 1 : d4 p 1 : d3 p 1 : d2 p 1 : d5 p 1 : d6 p 1 : d7 p n+1 data does not appear in the output stream
test circuits and timing diagram STSLVDSP27 18/23 note: t clkin note: t clkout figure 11. t clkin figure 12. t clkout
STSLVDSP27 package mechanical data 19/23 6 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com.
package mechanical data STSLVDSP27 20/23 dim. mm. mil s . min. typ. max. min. typ. max. a0. 8 10. 89 1.00 3 1. 93 5.0 39 .4 a1 0.15 0.24 0. 3 55. 99 .4 1 3 . 8 a2 0.65 25.6 b 0.25 0. 3 00. 3 5 9 . 8 11. 8 1 3 . 8 d 2.41 2.46 2.51 9 4. 99 6. 998 . 8 d1 2.00 7 8 .7 e1. 93 1. 98 2.0 3 76.0 7 8 .0 7 9 . 9 e1 1.5 5 9 .1 e 0.50 1 9 .7 s e 0.25 9 . 8 flip-chip20 mechanical data 74 8 7 339 -d
STSLVDSP27 package mechanical data 21/23 dim. mm. inch. min. typ. max. min. typ. max. a1 8 0 7.0 8 6 c 12. 8 1 3 .2 0.504 0.51 9 d 20.2 0.7 9 5 n60 2. 3 62 t 14.4 0.567 ao 2.1 3 2.2 3 2. 33 0.0 8 4 0.0 88 0.0 9 2 bo 2.62 2.72 2. 8 2 0.10 3 0.107 0.111 ko 1.05 1.15 1.25 0.041 0.045 0.04 9 po 3 . 9 4.1 0.15 3 0.161 p 3 . 9 4.1 0.15 3 0.161 tape & reel flip-chip20 mechanical data
revision history STSLVDSP27 22/23 7 revision history table 10. revision history date revision changes 01-jun-2007 1 initial release.
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