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| product specifications part no.: vl 47 b 5663a - f8 s e rev: 1.0 tel 949.888.2444 C 30052 tomas, rancho santa margarita, ca 92688 usa C www.virtium.com 1 general information 2 gb 256 m x 64 ddr3 sdram non - ecc unbuffered sodimm 204 - pin description the vl 47 b5 6 63 a is a 256 mx 64 ddr3 sdram high density so dimm. this dual rank memory module consists of six teen cmos 128 m x 8 bits with 8 banks ddr3 synchronous drams in bga packages and a 2k eeprom with thermal sensor in an 8 - pin mlf package. this module is a 2 0 4 - pin small - outline dual in - line memory module and is intended for mounting into a n edg e connector socket. decoupling capacitors are mounted on the printed circuit board for each ddr3 sdram . features pin description 20 4 - pin, s mall - outline d ual i n - line m emory m odule ( so dimm) fast data transfer rate: pc3 - 8500 vdd = vddq = 1.5v +/ - 0.075v jedec standard 1.5v +/ - 0.075v i/o (sstl_15 compatible ) vddspd = 3.0 v to 3.6v eight internal component banks for concurrent operation 8 - bit pre - fetch architecture bi - directional d ifferential data - s trobe nominal and dynamic o n - die termination (odt) zq c alibr ation s upport programmable cas # l atency: 7 (ddr3 - 1066) programmable b urst; length (8) average r efresh p eriod 7.8 us asynchronous r eset fly - by topology on board terminated command, address, and control bus serial presence detect (spd) eeprom with thermal sensor thermal sensor range: - 40 o c to +125 o c (max +/ - 3 o c accuracy) jedec pinout gold edge contacts lead - free, rohs compliant pcb: height 30.00 mm ( 1. 181 ) , double sided component operating temperature (toper): - commercial (0 o c <= tc <= 95 o c) - industrial ( - 40 o c <= tc <= 95 o c) note s : double refresh rate is required when 85 o c < t oper < = 95 o c. t oper is dram case temperature (tc ) pin name function a0 ~ a1 3 address inputs a10/ap address i nput/ autoprecharge a12/bc # address input/ burst chop ba0 ~ ba2 bank address inputs dq0 ~ dq63 data input/output dqs0 ~ dqs7 data strobes dqs0# ~ dqs 7 # data strobes complement dm0~dm7 data masks ck0, ck0#, ck1, ck1# clock input s odt0, odt1 on - die termination control cke0, cke1 clock enables cs0#, cs1# chip selects ras# row address strobes cas# column address strobes we# write enable reset# register and sdram control vdd voltage supply vss ground sa0~sa1 spd address sda spd data input/output scl spd clock input event# temperature event output vrefca reference voltage for ca vrefdq reference voltage for dq vddspd spd voltage supply vtt termination voltage nc no connect order information: vl 47 b 56 63 a - f8 s e - x operating temperature none: commercial s1: industrial screening dram die e - die dram manufacturer s - samsung module speed f8: pc3 - 8500 @ cl7 vl: lead - free/rohs dram component: samsung k4b 1 g0846 e - b c h9
product specifications part no.: vl 47 b 5663a - f8 s e rev: 1.0 tel 949.888.2444 C 30052 tomas, rancho santa margarita, ca 92688 usa C www.virtium.com 2 pin configuration 204 - pin ddr3 sodimm front 204 - pin ddr3 sodimm back pin name pin name pin name pin name pin name pin name pin name pin name 1 vrefdq 53 dq19 105 vdd 157 dq42 2 vss 54 vss 106 vdd 158 dq46 3 vss 55 vss 107 a10 159 dq43 4 dq4 56 dq28 108 ba1 160 dq47 5 dq0 57 dq24 109 ba0 161 vss 6 dq5 58 dq29 110 ras# 162 vss 7 dq1 59 dq25 111 vdd 163 dq48 8 vss 60 vss 112 vdd 164 dq52 9 vss 61 vss 113 we# 165 dq49 10 dqs0# 62 dq s 3# 114 cs0# 166 dq53 11 dm0 63 dm3 115 cas# 167 vss 12 dqs0 64 dq s 3 116 odt0 168 vss 13 vss 65 vss 117 vdd 169 dqs6# 14 vss 66 vss 118 vdd 170 dm6 15 dq2 67 dq26 119 a13 171 dqs6 16 dq6 68 dq30 120 odt1 172 vss 17 dq3 69 dq27 121 cs1# 173 vss 18 dq7 70 dq31 122 nc 174 dq54 19 vss 71 vss 123 vdd 175 dq50 20 vss 72 vss 124 vdd 176 dq55 21 dq8 73 cke0 125 nc 177 dq51 22 dq12 74 cke1 126 vrefca 178 vss 23 dq9 75 vdd 127 vss 179 vss 24 dq13 76 vdd 128 vss 180 dq60 25 vss 77 nc 129 dq32 181 dq56 26 vss 78 a15 * 130 dq36 182 dq61 27 dqs1# 79 ba2 131 dq33 183 dq57 28 dm1 80 a14 * 132 dq37 184 vss 29 dqs1 81 vdd 133 vss 185 vss 30 reset# 82 vdd 134 vss 186 dqs7# 31 vss 83 a12 135 dqs4# 187 dm7 32 vss 84 a11 136 dm4 188 dqs7 33 dq10 85 a9 137 dqs4 189 vss 34 dq14 86 a7 138 vss 190 vss 35 dq11 87 vdd 139 vss 191 dq58 36 dq15 88 vdd 140 dq38 192 dq62 37 vss 89 a8 141 dq34 193 dq59 38 vss 90 a6 142 dq39 194 dq63 39 dq16 91 a5 143 dq35 195 vss 40 dq20 92 a4 144 vss 196 vss 41 dq17 93 vdd 145 vss 197 sa0 42 dq21 94 vdd 146 dq44 198 event# 43 vss 95 a3 147 dq40 199 vddspd 44 vss 96 a2 148 dq45 200 sda 45 dqs2# 97 a1 149 dq41 201 sa1 46 dm2 98 a0 150 vss 202 scl 47 dqs2 99 vdd 151 vss 203 vtt 48 vss 100 vdd 152 dqs5# 204 vtt 49 vss 101 ck0 153 dm5 50 dq22 102 ck1 154 dqs5 51 dq18 103 ck0# 155 vss 52 dq23 104 ck1# 156 vss * : these pins are not used in this module. product specifications part no.: vl 47 b 5663a - f8 s e rev: 1.0 tel 949.888.2444 C 30052 tomas, rancho santa margarita, ca 92688 usa C www.virtium.com 3 function block diagram d8-d15 zq dq5 dq45 dq5 0.1uf dm dq3 dq0 dq6 dqs# cke1 vdd cs# dq40 dm6 vss dq0 cs# dq2 we# dq17 dm1 dqs d0-d15 dqs# dq6 dq56 dq6 dqs0# dqs dqs zq dq5 dq5 2. zq resistors are 240 ohms +/-1% d0 d1 dq52 dqs7 dq1 dq3 dq6 dqs# ras# dq21 dqs2 vss d0-d15 dqs dq7 dq44 dqs vddspd dq4 dq6 d0-d15 dqs# dq2 dq6 1. unless otherw ise noted, resistor values are 15 ohms +/-5% vrefca dq1 dq53 dm7 cs# dq4 dq5 dq5 ba0-ba2 vss dq20 dqs2# dq1 d0-d15 zq dq8 dq48 vss dqs4 dq2 dq4 d13 dq6 dq0 dqs notes: vtt dqs dq58 dqs7# dm dq2 dq2 dq6 ba0-ba2: sdrams d0-d15 w ith integrated thermal sensor dq24 dm2 cs# d0-d15 cs# dq10 dq50 dq1 serial pd/ thermal sensor d2 dm d15 cs# dq1 dq51 vss cs1#, cke1, odt1 36 ohm +/-5% dq5 dq42 dq4 dq7 dqs# dq0 dqs odt0 sa1 dq26 dqs3# dm dq6 dq9 dq57 cs# vtt dq5 dq5 d14 dq7 d7 dq59 dq1 reset#: sdrams d0-d15 dqs0 dm dq43 dq2 zq dq5 dq1 vss cke0: sdrams d0-d7 event# dq27 dm3 dq7 dq5 dq15 dq35 dm cs0# dq3 dq7 d12 dm dqs# dq47 cs# reset# vrefdq dq3 cs# dq6 d6 dq1 cke0 a2 dq31 dqs3 zq dq2 dq14 dq34 dq7 dq0 dq1 dq3 d11 dqs dq7 dq62 dm 3.3pf ck0, ck1 dq0 dq0 dqs dm dqs# cs# we#: sdrams d0-d15 event# dq30 vss dq0 dq0 dq12 dq37 zq dqs# dq0 cs# d9 dq4 dm dq54 dq7 ck0 cs# dq4 dqs vss dqs dq7 dm cas#: sdrams d0-d15 a0 dq6 dq25 vss dq3 dq1 dq11 dq33 dq0 dq0 zq dq0 d10 dq2 dq3 dq49 zq ck0# vdd dq2 dqs# dq1 dq4 dm dq7 cas# sa0 dqs4# zq dq29 vss dq4 d5 dq13 dq39 dq3 dq1 dqs# dqs# d8 d4 dq4 dq55 dq0 d0-d7 command, address, control, and clock line terminations zq dq6 cs# dq2 dq3 zq a0-a13 a1 dm4 vss dq28 dqs5# dq2 dm vss dqs# dq16 dq32 dq4 dq2 dq6 dq1 a0-a13, ba0-ba2 ras#, cas#, we#, cs0#, cke0, odt0 dq5 dq1 dq61 dq3 vss dq7 dq1 dm d3 dq4 dq0 odt0: sdrams d0-d7 scl dm0 dq7 vss dqs5 dqs# dq3 vss dq7 dq18 dq38 dq2 dq3 cs# dq2 3.3pf dq3 dq2 dq46 dq4 30 ohm +/-5% dq6 dm dq7 dq5 dqs dq3 odt1: sdrams d8-d15 sda ck0#, ck1# vss vss dm5 dq5 dq4 dq0 dq19 dq36 dqs# dq4 dq7 zq ck1 dq1 dq3 dq41 dq2 ddr3 sdram cs# dq7 zq dq3 zq dq4 odt1 serial pd dm dq6 vss dqs6 dq6 dqs dq3 ras#: sdrams d0-d15 dq23 dqs1 dq5 dq5 zq ck1# dq0 dq4 dq60 dqs# dqs dq7 dq5 cs1# dq1 cs# dq2 cke1: sdrams d8-d15 ddr3 sdram dqs# dq63 dqs6# dqs zq dq4 a0-a13: sdrams d0-d15 dq22 dqs1# dq6 product specifications part no.: vl 47 b 5663a - f8 s e rev: 1.0 tel 949.888.2444 C 30052 tomas, rancho santa margarita, ca 92688 usa C www.virtium.com 4 absolute maximum ratings symbol parameter m in m ax unit vdd voltage on vdd pin relative to vss - 0.4 1.975 v vddq voltage on vddq pin relative to vss - 0.4 1.975 v vin, vout voltage on any pin relative to vss - 0.4 1.975 v tstg storage temperature - 55 1 00 0 c il input leakage current; any input 0v product specifications part no.: vl 47 b 5663a - f8 s e rev: 1.0 tel 949.888.2444 C 30052 tomas, rancho santa margarita, ca 92688 usa C www.virtium.com 6 idd specification condition symbol f8 ( ddr3 - 1 066 ) unit operating one bank active - precharge current; tck= tck(idd); trc= trc(idd); tras= tras min(idd); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching idd0* 560 ma operating one bank active - read - precharge current; iout = 0ma; bl = 8; cl = cl(idd); al = 0; tck= tck(idd); trc= trc(idd); tras= tras min(idd); trcd= trcd(idd); cke is high, cs# is high between valid commands; address bus inputs are switching; data patte rn is same as idd4w. idd1* 680 ma precharge power - down current; all device banks idle; tck= tck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating idd2p - f** 400 ma idd2p - s** 160 ma precharge standby current; all device banks idle; tck= tck(idd); cke is high; cs# is high; other control and address bus inputs are switching; data bus inputs are switching. idd2n** 480 ma precharge quiet standby current; all device banks idle; tck= tck(idd); cke is high; cs# is high; other control and address bus inputs are stable; data bus inputs are floating idd2q** 480 ma active power - down current; all device banks open; tck= tck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating. idd3p** 400 ma active standby current; all device banks open; tck= tck(idd); trp= trp(idd); tras= tras max(idd)); cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching. idd3n** 720 ma operating burst read current; all device banks open; continuous burst reads; iout = 0ma; bl = 8; cl = cl(idd); al = 0; tck= tck(idd); tras= tras max(idd); trp= trp(idd); cke is high, cs# is high between valid commands; address bus inputs are switching; data pattern is same as idd4w. idd4r* 960 ma operating burst write current; all device banks open; continuous burst writes; bl = 8; cl = cl(idd); al = 0; tck= tck(idd); tras= tras max(idd); trp= trp(idd); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching. idd4w* 1000 m a burst refresh current; tck=tck(idd); refresh command at every trfc(idd) interval; cke is high; cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching. idd5** 2400 ma self refresh current; ck and ck# at 0v; cke < 0.2v; other control and address bus inputs are floating; data bus inputs are floating. idd6** 160 ma operating bank interleave read current; all bank interleaving reads; iout = 0ma; bl = 8; cl = cl(idd); al = trcd(idd) - 1*tck(idd); tck= tck(idd); trc= trc(idd); trrd = trrd(idd); trcd = 1*tck(idd) ; cke is high; cs# is high between valid commands; address bus inputs are stable during deselects; data pattern is same as idd4r. idd7* 1560 ma note: idd specification is based on samsung e - die components. *: value calculated as one module rank in this operating condition, and all other module ranks in idd2p (cke low) mode. **: value calculated reflects all module ranks in this operating condit ion. product specifications part no.: vl 47 b 5663a - f8 s e rev: 1.0 tel 949.888.2444 C 30052 tomas, rancho santa margarita, ca 92688 usa C www.virtium.com 7 ac timing parameters & specifications parameter symbol k0 ( ddr3 - 1600) k9 ( ddr3 - 1333 ) f8 ( ddr3 - 1066 ) unit min max min max min max clock timing minimum clock cycle time (dll off mode) tck(dll_off) 8 - 8 - 8 - ns average clock period tck( avg) 1.25 <1.50 1.5 <1.875 1.875 <2.5 n s clock period tck(abs) tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max n s average high pulse width tch(avg) 0.47 0.53 0.47 0.53 0.47 0.53 tck(avg) average low pulse width tcl(avg) 0.47 0.53 0.47 0.53 0.47 0.53 tck(avg) clock period jitter tjit(per) - 70 70 - 80 80 - 90 90 ps clock period jitter during dll locking period tjit(per, lck) - 60 60 - 70 70 - 80 80 ps cycle to cycle period jitter tjit(cc) 140 160 180 ps cycle to cycle period jitter during dll locking period tjit(cc, lck) 120 140 160 ps cumulative error across 2 cycles terr(2per) - 103 103 - 118 118 - 132 132 ps cumulative error across 3 cycles terr(3per) - 122 122 - 140 140 - 157 157 ps cumulative error across 4 cycles terr(4per) - 136 136 - 155 155 - 175 175 ps cumulative error across 5 cycles terr(5per) - 147 147 - 168 168 - 188 188 ps cumulative error across 6 cycles terr(6per) - 155 155 - 177 177 - 200 200 ps cumulative error across 7 cycles terr(7per) - 163 163 - 186 186 - 209 209 ps cumulative error across 8 cycles terr(8per) - 169 169 - 193 193 - 217 217 ps cumulative error across 9 cycles terr(9per) - 175 175 - 200 200 - 224 224 ps cumulative error across 10 cycles terr(10per) - 180 180 - 205 205 - 231 231 ps cumulative error across 11 cycles terr(11per) - 184 184 - 210 210 - 237 237 ps cumulative error across 12 cycles terr(12per) - 188 188 - 215 215 - 242 242 ps cumulative error across n = 13, 14 ... 49, 50 cycles terr( n per) terr( n per)min =(1+ 0.68ln( n ) )*tjit(per)min terr( n per)max=(1+ 0.68ln( n ) )*tjit(per)max ps absolute clock high pulse width tch(abs) 0.43 - 0.43 - 0.43 - tck(avg) absolute clock low pulse width tcl(abs) 0.43 - 0.43 - 0.43 - tck(avg) data timing dqs,dqs# to dq skew, per group, per access tdqsq - 100 - 125 - 150 ps dq output hold time from dqs, dqs# tqh 0.38 - 0.38 - 0.38 - tck(avg) dq low - impedance time from ck, ck# tlz(dq) - 450 225 - 500 250 - 600 300 ps dq high - impedance time from ck, ck# thz(dq) - 225 - 250 - 300 ps data setup time to dqs, dqs# referenced to vih(ac)vil(ac) levels tds(base) ( ac175) - - - - 25 - ps data setup time to dqs, dqs# referenced to vih(ac)vil(ac) levels tds(base) ( ac150) 10 - 30 - - - ps data hold time to dqs, dqs# referenced to vih(ac) vil(ac) levels tdh(base) 45 - 65 - 100 - ps dq and dm input pulse width for each input tdipw 360 - 400 - 490 - ps product specifications part no.: vl 47 b 5663a - f8 s e rev: 1.0 tel 949.888.2444 C 30052 tomas, rancho santa margarita, ca 92688 usa C www.virtium.com 8 ac timing parameters & specifications parameter symbol k0 ( ddr3 - 1600) k9 ( ddr3 - 1333 ) f8 ( ddr3 - 1066 ) unit min max min max min max data strobe timing dqs, dqs# read preamble trpre 0.9 - 0.9 - 0.9 - tck dqs, dqs# differential read postamble trpst 0.3 - 0.3 - 0.3 - tck dqs, dqs# output high time tqsh 0.4 - 0.4 - 0.38 - tck(avg) dqs, dqs# output low time tqsl 0.4 - 0.4 - 0.38 - tck(avg) dqs, dqs# write preamble twpre 0.9 - 0.9 - 0.9 - tck dqs, dqs# write postamble twpst 0.3 - 0.3 - 0.3 - tck dqs, dqs# rising edge output access time from rising ck, ck# tdqsck - 225 225 - 255 255 - 300 300 ps dqs, dqs# low - impedance time (referenced from rl - 1) tlz(dqs) - 450 225 - 500 250 - 600 300 ps dqs, dqs# high - impedance time (referenced from rl+bl/ 2) thz(dqs) - 225 - 250 - 300 ps dqs, dqs# differential input low pulse width tdqsl 0.45 0.55 0.45 0.55 0.45 0.55 tck dqs, dqs# differential input high pulse width tdqsh 0.45 0.55 0.45 0.55 0.45 0.55 tck dqs, dqs# rising edge to ck, ck# rising edge tdqss - 0.27 0.27 - 0.25 0.25 - 0.25 0.25 tck(avg) dqs,dqs# failing edge setup time to ck, ck# rising edge tdss 0.18 - 0.2 - 0.2 - tck(avg) dqs,dqs# failing edge hold time to ck, ck# rising edge tdsh 0.18 - 0.2 - 0.2 - tck(avg) command and address timing dll locking time tdllk 512 - 512 - 512 - nck internal read command to precharge command delay trtp max ( 4tck,7.5ns) - max ( 4tck,7.5ns) - max ( 4tck,7.5ns) - delay from start of internal write transaction to internal read command twtr max ( 4tck,7.5ns) - max ( 4tck,7.5ns) - max ( 4tck,7.5ns) - write recovery time twr 15 - 15 - 15 - ns mode register set command cycle time tmrd 4 - 4 - 4 - nck mode register set command update delay tmod max ( 12tck,15ns) - max ( 12tck,15ns) - max ( 12tck,15ns) - cas# to cas# command delay tccd 4 - 4 - 4 - nck auto precharge write recovery + precharge time tdal(min) wr + roundup (trp / tck(avg)) nck multi - purpose register recovery time tmprr 1 - 1 - 1 - nck active to precharge command period tras 35 9*trefi 36 9*trefi 37.5 9*trefi ns active to internal read or write delay time trcd 13.75 - 13.5 - 13.13 - ns precharge command period trp 13.75 - 13.5 - 13.13 - ns active to active or ref command period trc 48.75 - 49.5 - 50.63 - ns active to active command period for 1kb page size trrd max (4tck, 6ns) - max (4tck, 6ns) - max (4tck, 7.5ns) - active to active command period for 2kb page size trrd max ( 4tck,7.5ns) - max ( 4tck,7.5ns) - max ( 4tck,10ns) - four activate window for 1kb page size tfaw 30 - 30 - 37.5 - ns four activate window for 2kb page size tfaw 40 - 45 - 50 - ns command and address setup time to ck, ck# referenced to vih(ac) / vil(ac) levels tis(base) ( ac175) - - - - 125 - ps command and address setup time to ck, ck# referenced to vih(ac) / vil(ac) levels tis(base) ( ac150) 170 - 190 - - - ps command and address hold time from ck, ck# referenced to vih(ac) / vil(ac) levels tih(base) 120 - 140 - 200 - ps control & address input pulse width for each input tipw 560 - 620 - 780 - ps product specifications part no.: vl 47 b 5663a - f8 s e rev: 1.0 tel 949.888.2444 C 30052 tomas, rancho santa margarita, ca 92688 usa C www.virtium.com 9 ac timing parameters & specifications parameter symbol k0 ( ddr3 - 1600) k9 ( ddr3 - 1333 ) f8 ( ddr3 - 1066 ) unit min max min max min max refresh timing 1 gb refresh to refresh or refresh to active command interval trfc 1 10 - 1 10 - 1 10 - ns average periodic refresh interval ( 0c<= tcase <= 85 c) trefi 7.8 - 7.8 - 7.8 - us average periodic refresh interval ( 85c<= tcase <= 95 c) trefi 3.9 - 3.9 - 3.9 - us calibration timing power - up and reset calibration time tzqiniti 512 - 512 - 512 - tck normal operation full calibration time tzqoper 256 - 256 - 256 - tck normal operation short calibration time tzqcs 64 - 64 - 64 - tck reset timing exit reset from cke high to a valid command txpr max ( 5tck, trfc + 10ns) - max ( 5tck, trfc + 10ns) - max ( 5tck, trfc + 10ns) - self refresh timing exit self refresh to commands not requiring a locked dll txs max(5tc, trfc+10ns) - max(5tc, trfc+10ns) - max(5tc, trfc +10ns) - exit self refresh to commands requiring a locked dll txsdll tdllk(min) - tdllk(min) - tdllk(min) - nck minimum cke low width for self refresh entry to exit timing tckesr tcke(min) + 1tck - tcke ( min) + 1tck - tcke(min) + 1tck - valid clock requirement after self refresh entry (sre) tcksre max(5tc, 10ns) - max(5tck, 10ns) - max(5tck, 10ns) - valid clock requirement before self refresh exit (srx) tcksrx max(5tc, 10ns) - max(5tck, 10ns) - max(5tck, 10ns) - power down timing exit power down with dll to any valid command; exit precharge power down with dll frozen to commands not requiring a locked dll txp max (3tck, 6ns) - max (3tck, 6ns) - max (3tck, 7.5ns) - exit precharge power down with dll frozen to commands requiring a locked dll txpdll max ( 10tck,24ns) - max ( 10tck,24ns) - max ( 10tck,24ns) - cke minimum pulse width tcke max (3tck, 5ns) - max (3tck, 5.625ns) - max (3tck, 5.625ns) - command pass disable delay tcpded 1 - 1 - 1 - nck power down entry to exit timing tpd tcke(min) 9*trefi tcke(min) 9*trefi tcke(min) 9*trefi tck timing of act command to power down entry tactpden 1 - 1 - 1 - nck timing of pre command to power down entry tprpden 1 - 1 - 1 - nck timing of rd/rda command to power down entry trdpden rl + 4 +1 - rl + 4 +1 - rl + 4 +1 - timing of wr command to power down entry bl8 (otf, mrs), bl4otf twrpden wl + 4 + (twr/ tck(avg)) - wl + 4 + (twr/ tck(avg)) - wl + 4 + (twr/ tck(avg)) - nck timing of wra command to power down entry bl8 (otf, mrs), bl4otf twrapden wl+4 +wr+1 - wl+4 +wr+1 - wl+4 +wr+1 - nck timing of wr command to power down entry (bl4mrs) twrpden wl + 2 + (twr/ tck(avg)) - wl + 2 + ( twr/ tck(avg)) - wl + 2 + (twr/ tck(avg)) - nck timing of wra command to power down entry (bl4mrs) twrapden wl+2 +wr+1 - wl+2 +wr+1 - wl+2 +wr+1 - nck timing of ref command to power down entry trefpden 1 - 1 - 1 - timing of mrs command to power down entry tmrspden tmod(min) - tmod(min) - tmod(min) - product specifications part no.: vl 47 b 5663a - f8 s e rev: 1.0 tel 949.888.2444 C 30052 tomas, rancho santa margarita, ca 92688 usa C www.virtium.com 10 ac timing parameters & specifications parameter symbol k0 ( ddr3 - 1600) k9 ( ddr3 - 1333 ) f8 ( ddr3 - 1066 ) unit min max min max min max odt timing odt high time without write command or with write command and bc4 odth4 4 - 4 - 4 - nck odt high time with write command and bl8 odth8 6 - 6 - 6 - nck asynchronous rtt turn - on delay (power - down with dll frozen) taonpd 2 8.5 2 8.5 2 8.5 ns asynchronous rtt turn - off delay (power - down with dll frozen) taofpd 2 8.5 2 8.5 2 8.5 ns odt turn - on taon - 225 225 - 250 250 - 300 300 ps rtt_nom and rtt_wr turn - off time from odtl off reference taof 0.3 0.7 0.3 0.7 0.3 0.7 tck(avg) rtt dynamic change skew tadc 0.3 0.7 0.3 0.7 0.3 0.7 tck(avg) write leveling timing first dqs pulse rising edge after tdqss margining mode is programmed twlmrd 40 - 40 - 40 - tck dqs/dqs delay after tdqs margining mode is programmed twldqsen 25 - 25 - 25 - tck setup time for tdqss latch twls 165 - 195 - 245 - ps hold time for tdqss latch twlh 165 - 195 - 245 - ps write leveling output delay twlo 0 7.5 0 9 0 9 ns write leveling output error twloe 0 2 0 2 0 2 ns product specifications part no.: vl 47 b 5663a - f8 s e rev: 1.0 tel 949.888.2444 C 30052 tomas, rancho santa margarita, ca 92688 usa C www.virtium.com 11 package dimensions note: 1. all dimensions are in millimeters with tolerance +/ - 0.15mm unless otherwise specified. 2. the dimensional diagram is for reference only. 21.00 typ 24.80 typ front view 3.00 typ 4.0 +/- 0.10 (2x) 4.00 typ 67.60 pin 2 pin 203 20.00 pin 1 2.55 typ 2.15 typ 30.00 1.80 (2x) back view 0.60 typ 3.40 max 0.45 typ 1.0 +/- 0.10 1.0 +/- 0.10 typ 63.60 typ typ 0.5 r 6.00 typ pin 204 39.00 typ product specifications part no.: vl 47 b 5663a - f8 s e rev: 1.0 tel 949.888.2444 C 30052 tomas, rancho santa margarita, ca 92688 usa C www.virtium.com 12 revision history: date rev. page changes 10 / 24 /201 2 1.0 all spec release |
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