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preliminary?ubject to change without notice this document contains detailed information on power considerations, dc/ac electrical characteristics, and ac timing speci cations for the mpc8250 powerquicc ii? communications processor. the following topics are addressed: topic page section 1.1, ?features? 2 section 1.2, ?electrical and thermal characteristics? 5 section 1.2.1, ?dc electrical characteristics? 5 section 1.2.2, ?thermal characteristics? 10 section 1.2.3, ?power considerations? 10 section 1.2.4, ?ac electrical characteristics? 11 section 1.3, ?clock con guration modes? 18 section 1.3.1, ?local bus mode? 18 section 1.3.2, ?pci mode? 21 section 1.4, ?pinout? 27 section 1.5, ?package description? 40 section 1.6, ?ordering information? 42 advance inf ormation MPC8250EC/d rev. 0.4 5/2002 mpc8250 hardware speci cations
2 mpc8250 hardware speci?ations motorola preliminary?ubject to change without notice features figure 1 shows the block diagram for the mpc8250. figure 1. mpc8250 block diagram 1.1 features the major features of the mpc8250 are as follows: footprint-compatible with the mpc8260 dual-issue integer core ? a core version of the ec603e microprocessor ? system core microprocessor supporting frequencies of 150?200 mhz ? separate 16-kbyte data and instruction caches: ? four-way set associative ? physically addressed ? lru replacement algorithm ? powerpc architecture-compliant memory management unit (mmu) ? common on-chip processor (cop) test interface ? high-performance (4.4?5.1 spec95 benchmark at 200 mhz; 280 dhrystones mips at 200 mhz) ? supports bus snooping for data cache coherency ? floating-point unit (fpu) 16 kbytes g2 core i-cache i-mmu 16 kbytes d-cache d-mmu communication processor module (cpm) timers parallel i/o baud rate generators 32 kbytes 32-bit risc microcontroller and program rom serial dmas 4 virtual idmas 60x-to-pci bridge bridge memory controller clock counter system functions system interface unit (siu) local bus 32 bits, up to 83 mhz pci bus 32 bits, up to 66 mhz or mcc2 fcc1 fcc2 fcc3 scc1 scc2 scc3 scc4 smc1 smc2 spi i 2 c serial interface 3 mii ports 60x bus dual-port ram interrupt controller time slot assigner 4 tdm ports non-multiplexed i/o 60x-to-local bus interface unit
motorola mpc8250 hardware speci?ations 3 preliminary?ubject to change without notice features separate power supply for internal logic (1.8 v) and for i/o (3.3v) separate plls for g2 core and for the cpm ? g2 core and cpm can run at different frequencies for power/performance optimization ? internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios ? internal cpm/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios 64-bit data and 32-bit address 60x bus ? bus supports multiple master designs ? supports single- and four-beat burst transfers ? 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller ? supports data parity or ecc and address parity 32-bit data and 18-bit address local bus ? single-master bus, supports external slaves ? eight-beat burst transfers ? 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller 60x-to-pci bridge ? programmable host bridge and agent ? 32-bit data bus, 66 mhz, 3.3 v ? synchronous and asynchronous 60x and pci clock modes ? all internal address space available to external pci host ? dma for memory block transfers ? pci-to-60x address remapping system interface unit (siu) ? clock synthesizer ? reset controller ? real-time clock (rtc) register ? periodic interrupt timer ? hardware bus monitor and software watchdog timer ? ieee 1149.1 jtag test access port twelve-bank memory controller ? glueless interface to sram, page mode sdram, dram, eprom, flash and other user- de nable peripherals ? byte write enables and selectable parity generation ? 32-bit address decodes with programmable bank size ? three user programmable machines, general-purpose chip-select machine, and page-mode pipeline sdram machine ? byte selects for 64 bus width (60x) and byte selects for 32 bus width (local) ? dedicated interface logic for sdram cpu core can be disabled and the device can be used in slave mode to an external core
4 mpc8250 hardware speci?ations motorola preliminary?ubject to change without notice features communications processor module (cpm) ? embedded 32-bit communications processor (cp) uses a risc architecture for exible support for communications protocols ? interfaces to g2 core through on-chip 32-kbyte dual-port ram and dma controller ? serial dma channels for receive and transmit on all serial channels ? parallel i/o registers with open-drain and interrupt capability ? virtual dma functionality executing memory-to-memory and memory-to-i/o transfers ? three fast communications controllers supporting the following protocols: ? 10/100-mbit ethernet/ieee 802.3 cdma/cs interface through media independent interface (mii) ? transparent ? hdlc?up to t3 rates (clear channel) ? one multichannel controller (mcc2) ? handles 128 serial, full-duplex, 64-kbps data channels. the mcc can be split into four subgroups of 32 channels each. ? almost any combination of subgroups can be multiplexed to single or multiple tdm interfaces up to four tdm interfaces per mcc ? four serial communications controllers (sccs) identical to those on the mpc860, supporting the digital portions of the following protocols: ? ethernet/ieee 802.3 cdma/cs ? hdlc/sdlc and hdlc bus ? universal asynchronous receiver transmitter (uart) ? synchronous uart ? binary synchronous (bisync) communications ? transparent ? two serial management controllers (smcs), identical to those of the mpc860 ? provide management for bri devices as general circuit interface (gci) controllers in time- division-multiplexed (tdm) channels ? transparent ? uart (low-speed operation) ? one serial peripheral interface identical to the mpc860 spi ? one inter-integrated circuit (i 2 c) controller (identical to the mpc860 i 2 c controller) ? microwire compatible ? multiple-master, single-master, and slave modes ? up to four tdm interfaces ? supports one group of four tdm channels ? 2,048 bytes of si ram ? bit or byte resolution ? independent transmit and receive routing, frame synchronization
motorola mpc8250 hardware speci?ations 5 preliminary?ubject to change without notice electrical and thermal characteristics ? supports t1, cept, t1/e1, t3/e3, pulse code modulation highway, isdn basic rate, isdn primary rate, motorola interchip digital link (idl), general circuit interface (gci), and user-de ned tdm serial interfaces ? eight independent baud rate generators and 20 input clock pins for supplying clocks to fccs, sccs, smcs, and serial channels ? four independent 16-bit timers that can be interconnected as two 32-bit timers pci bridge ? pci speci cation revision 2.2 compliant and supports frequencies up to 66 mhz ? on-chip arbitration ? support for pci to 60x memory and 60x memory to pci streaming ? pci host bridge or periphera l capabilities ? includes 4 dma channels for the following transfers: ? pci-to-60x to 60x-to-pci ? 60x-to-pci to pci-to-60x ? pci-to-60x to pci-to-60x ? 60x-to-pci to 60x-to-pci ? includes all of the con guration registers (which are automatically loaded from the eprom and used to con gure the mpc8265a) required by the pci standard as well as message and doorbell registers ? supports the i 2 o standard ? hot-swap friendly (supports the hot swap speci cation as de ned by picmg 2.1 r1.0 august 3, 1998) ? support for 66 mhz, 3.3 v speci cation ? 60x-pci bus core logic which uses a buffer pool to allocate buffers for each port ? makes use of the local bus signals, so there is no need for additional pins 1.2 electrical and thermal characteristics this section provides ac and dc electrical speci cations and thermal characteristics for the mpc8250. 1.2.1 dc electrical characteristics this section describes the dc electrical characteristics for the mpc8250. table 1 shows the maximum electrical ratings.
6 mpc8250 hardware speci?ations motorola preliminary?ubject to change without notice electrical and thermal characteristics table 2 lists recommended operational voltage conditions. note vddh and vdd must track each other and both must vary in the same direction?in the positive direction (+5% and +0.1 vdc) or in the negative direction (-5% and -0.1 vdc). this device contains circuitry protecting against damage due to high static voltage or electrical elds; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (either gnd or v cc ). table 1. absolute maximum ratings 1 1 absolute maximum ratings are stress ratings only; functional operation (see table 2) at the maximums is not guaranteed. stress beyond those listed may affect device reliability or cause permanent damage. rating symbol value unit core supply voltage 2 2 caution: vdd/vccsyn must not exceed vddh by more than 0.4 v at any time, including during power-on reset. vdd -0.3 ?2.5 v pll supply voltage 2 vccsyn -0.3 ?2.5 v i/o supply voltage 3 3 caution: vddh can exceed vdd/vccsyn by 3.3 v during power on reset by no more than 100 msec. vddh should not exceed vdd/vccsyn by more than 2.5 v during normal operation. vddh -0.3 ?4.0 v input voltage 4 4 caution: vin must not exceed vddh by more than 2.5 v at any time, including during power-on reset. vin gnd(-0.3) ?3.6 v junction temperature t j 120 ?c storage temperature range t stg (-55) ?(+150) ?c table 2. recommended operating conditions 1 1 caution: these are the recommended and tested operating conditions. proper device operating outside of these conditions is not guaranteed. rating symbol value unit core supply voltage vdd 1.7 ?2.1 2 / 1.9?.1 3 2 for devices operating at less than 233 mhz cpu, 166 mhz cpm, and 66 mhz bus frequencies. 3 for devices operating at greater than or equal to 233 mhz cpu, 166 mhz cpm, and 66 mhz bus frequencies. v pll supply voltage vccsyn 1.7 ?2.1 2 / 1.9?.1 3 v i/o supply voltage vddh 3.135 ?3.465 v input voltage vin gnd (-0.3) ?3.465 v junction temperature (maximum) t j 105 4 4 note that for extended temperature parts the range is (-40) t a ?105 t j . ?c ambient temperature t a 0?0 4 ?c
motorola mpc8250 hardware speci?ations 7 preliminary?ubject to change without notice electrical and thermal characteristics table 3 shows dc electrical characteristics. table 3. dc electrical characteristics characteristic symbol min max unit input high voltage, all inputs except clkin v ih 2.0 3.465 v input low voltage v il gnd 0.8 v clkin input high voltage v ihc 2.4 3.465 v clkin input low voltage v ilc gnd 0.4 v input leakage current, v in = vddh 1 i in ?0a hi-z (off state) leakage current, v in = vddh 1 i oz ?0a signal low input current, v il = 0.8 v i l ?a signal high input current, v ih = 2.0 v i h ?a output high voltage, i oh = ? ma v oh 2.4 v
8 mpc8250 hardware speci?ations motorola preliminary?ubject to change without notice electrical and thermal characteristics i ol = 7.0ma br bg abb/irq2 ts a[0-31] tt[0-4] tbst tsize[0?] aa ck ar tr y dbg dbb /irq3 d[0-63] dp(0)/rsr v /ext_br2 dp(1)/irq1 /ext_bg2 dp(2)/tlbisync /irq2 /ext_dbg2 dp(3)/irq3 /ext_br3 /ckstp_out dp(4)/irq4 /ext_bg3 /core_srest dp(5)/tben/irq5 /ext_dbg3 dp(6)/cse(0)/irq6 dp(7)/cse(1)/irq7 psd v al t a tea gbl /irq1 ci/ baddr29/irq2 wt /baddr30/irq3 l2_hit /irq4 cpu_bg/ baddr31/irq5 cpu_dbg cpu_br irq0 /nmi_out irq7 /int_out /ape poreset hreset sreset rstconf qreq v ol 0.4 v table 3. dc electrical characteristics (continued) characteristic symbol min max unit
motorola mpc8250 hardware speci?ations 9 preliminary?ubject to change without notice electrical and thermal characteristics i ol = 5.3ma cs [0-9] cs (10)/bctl1 cs (11)/ap(0) baddr[27?8] ale bctl0 pwe (0:7)/psddqm( 0:7)/pbs (0:7) psda10/pgpl0 psd we/ pgpl1 poe/psdras/pgpl2 psdcas/pgpl3 pgta/pupmwait/pgpl4/ppbs psdamux/pgpl5 lwe[0?]lsddqm[0:3]/lbs[0?]/pci_cfg[0? lsda10/lgpl0/pci_modckh0 lsdwe/lgpl1/pci_modckh1 loe/lsdras/lgpl2/pci_modckh2 lsdcas/lgpl3/pci_modckh3 lgta/lupmwait/lgpl4/lpbs lsdamux/lgpl5/pci_modck l wr modck1/ap(1)/tc(0)/bnksel(0) modck2/ap(2)/tc(1)/bnksel(1) modck3/ap(3)/tc(2)/bnksel(2) i ol = 3.2ma l_a14/par l_a15/frame /smi l_a16/trd y l_a17/ird y /ckstp_out l_a18/st op l_a19/devsel l_a20/idsel l_a21/perr l_a22/serr l_a23/req0 l_a24/req1 /hsejsw l_a25/gnt0 l_a26/gnt1 /hsled l_a27/gnt2 /hsenum l_a28/rst /core_sreset l_a29/int a l_a30/req2 l_a31 lcl_d(0-31)/ad(0-31) lcl_dp(0-3)/c/be (0-3) pa[0?1] pb[4?1] pc[0?1] pd[4?1] tdo v ol 0.4 v 1 the leakage current is measured for nominal vddh and vdd or both vddh and vdd must vary in the same direction; that is, vddh and vdd either both vary in the positive direction (+5% and +0.1 vdc) or both vary in the negative direction (-5% and -0.1 vdc). table 3. dc electrical characteristics (continued) characteristic symbol min max unit
10 mpc8250 hardware speci?ations motorola preliminary?ubject to change without notice electrical and thermal characteristics 1.2.2 thermal characteristics table 4 describes thermal characteristics. 1.2.3 power considerations the average chip-junction temperature , t j , in c can be obtained from the following: t j = t a + (p d x ja ) (1) where t a = ambient temperature c ja = package thermal resistance , junction to ambient , c/w p d = p int + p i/o p int = i dd x v dd watts (chip internal power) p i/o = power dissipation on input and output pins (determined by user) for most applications p i/o < 0.3 x p int . if p i/o is neglected , an approximate relationship between p d and t j is the following: p d = k/(t j + 273 c) (2) solving equations (1) and (2) for k gives: k = p d x (t a + 273 c) + ja x p d 2 (3) where k is a constant pertaining to the particular part. k can be determined from equation (3) by measuring p d (at equilibrium) for a known t a . using this value of k , the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . 1.2.3.1 layout practices each v cc pin should be provided with a low-impedance path to the board?s power supply. each ground pin should likewise be provided with a low-impedance path to ground. the power supply pins drive distinct groups of logic on chip. the v cc power supply should be bypassed to ground using at least four 0.1 f by-pass capacitors located as close as possible to the four sides of the package. the capacitor leads and associated printed circuit traces connecting to chip v cc and ground should be kept to less than half an inch per capacitor lead. a four-layer board is recommended, employing two inner layers as v cc and gnd planes. table 4. thermal characteristics characteristics symbol value unit air flow thermal resistance for tbga ja 13.07 1 1 assumes a single layer board with no thermal vias c/w nc 2 2 natural convection ja 9.55 1 c/w 1 m/s ja 10.48 3 3 assumes a four layer board c/w nc ja 7.78 3 c/w 1 m/s
motorola mpc8250 hardware speci?ations 11 preliminary?ubject to change without notice electrical and thermal characteristics all output pins on the mpc8250 have fast rise and fall times. printed circuit (pc) trace interconnection length should be minimized in order to minimize overdamped conditions and re ections caused by these fast output switching times. this recommendation particularly applies to the address and data buses. maximum pc trace lengths of six inches are recommended. capacitance calculations should consider all device loads as well as parasitic capacitances due to the pc traces. attention to proper pcb layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the v cc and gnd circuits. pull up all unused inputs or signals that will be inputs during reset. special care should be taken to minimize the noise levels on the pll supply pins. table 5 provides preliminary, estimated power dissipation for various con gurations. note that suitable thermal management is required for conditions above p d = 3w (when the ambient temperature is 70 ? c or greater) to ensure the junction temperature does not exceed the maximum speci ed value. also note that the i/o power should be included when determining whether to use a heat sink. 1.2.4 ac electrical characteristics the following sections include illustrations and tables of clock diagrams, signals, and cpm outputs and inputs for the 66 mhz mpc8250 device. note that ac timings are based on a 50-p f load. typical output buffer impedances are shown in table 6. table 5. estimated power dissipation for various con?urations 1 1 test temperature = room temperature (25 ? c) bus (mhz) cpm multiplier core cpu multiplier cpm (mhz) cpu (mhz) p int (w) 2 2 p int = i dd x v dd watts vddl 1.8 volts vddl 2.0 volts nominal maximum nominal maximum 66.66 2 3 133 200 1.2 2 1.8 2.3 66.66 2.5 3 166 200 1.3 2.1 1.9 2.3 66.66 3 4 200 266 2.3 2.9 66.66 3 4.5 200 300 2.4 3.1 83.33 2 3 166 250 2.2 2.8 83.33 2 3 166 250 2.2 2.8 83.33 2.5 3.5 208 291 2.4 3.1 table 6. output buffer impedances 1 1 these are typical values at 65? c. the impedance may vary by ?5% with process and temperature. output buffers typical impedance ( ? ) 60x bus 40 local bus 40 memory controller 40 parallel i/o 46 pci 25
12 mpc8250 hardware speci?ations motorola preliminary?ubject to change without notice electrical and thermal characteristics table 7 lists cpm output characteristics. table 8 lists cpm input characteristics. note that although the speci cations generally reference the rising edge of the clock, the following ac timing diagrams also apply when the falling edge is the active edge. figure 2 shows the fcc external clock. figure 2. fcc external clock diagram table 7. ac characteristics for cpm outputs 1 1 output speci?ations are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. spec_num max/min characteristic max delay (ns) min delay (ns) 66 mhz 83 mhz 66 mhz 83 mhz sp36a/sp37a fcc outputs?nternal clock (nmsi) 6 5.5 1 1 sp36b/sp37b fcc outputs?xternal clock (nmsi) 14 12 2 1 sp40/sp41 tdm outputs/si 25 16 5 4 sp38a/sp39a scc/smc/spi/i2c outputs?nternal clock (nmsi) 19 16 1 0.5 sp38b/sp39b ex_scc/smc/spi/i2c outputs?xternal clock (nmsi) 19 16 2 1 sp42/sp43 pio/timer/dma outputs 14 11 1 0.5 table 8. ac characteristics for cpm inputs 1 1 input speci?ations are measured from the 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. spec_num characteristic setup (ns) hold (ns) 66 mhz 83 mhz 66 mhz 83 mhz sp16a/sp17a fcc inputs?nternal clock (nmsi) 10 8 0 0 sp16b/sp17b fcc inputs?xternal clock (nmsi) 3 2.5 3 2 sp20/sp21 tdm inputs/si 15 12 12 10 sp18a/sp19a scc/smc/spi/i2c inputs?nternal clock (nmsi) 20 16 0 0 sp18b/sp19b scc/smc/spi/i2c inputs?xternal clock (nmsi) 5454 sp22/sp23 pio/timer/dma inputs 10 8 3 3 serial clkin fcc input signals fcc output signals sp16b sp17b sp36b/sp37b
motorola mpc8250 hardware speci?ations 13 preliminary?ubject to change without notice electrical and thermal characteristics figure 3 shows the fcc internal clock. figure 3. fcc internal clock diagram figure 4 shows the scc/smc/spi/i 2 c external clock. figure 4. scc/smc/spi/i 2 c external clock diagram figure 5 shows the scc/smc/spi/i 2 c internal clock. figure 5. scc/smc/spi/i 2 c internal clock diagram brg_out fcc input signals fcc output signals sp16a sp17a sp36a/sp37a serial clkin scc/smc/spi/i2c input signals scc/smc/spi/i2c output signals sp18b sp19b sp38b/sp39b brg_out scc/smc/spi/i2c input signals scc/smc/spi/i2c output signals sp18a sp19a sp38a/sp39a
14 mpc8250 hardware speci?ations motorola preliminary?ubject to change without notice electrical and thermal characteristics figure 6 shows pio, timer, and dma signals. figure 6. pio, timer, and dma signal diagram table 9 lists siu input characteristics. table 9. ac characteristics for siu inputs 1 1 input speci?ations are measured from the 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. spec_num characteristic setup (ns) hold (ns) 66 mhz 83 mhz 66 mhz 83 mhz sp11/sp10 aa ck /ar tr y /t a /ts /tea /dbg /bg /br 6511 sp12/sp10 data bus in normal mode 5411 sp13/sp10 data bus in ecc and parity modes 8611 sp14/sp10 dp pins 7611 sp15/sp10 all other pins 5411 clkin pio/timer/dma input signals timer/dma output signals sp22 sp23 sp42/sp43 pio output signals sp42/sp43
motorola mpc8250 hardware speci?ations 15 preliminary?ubject to change without notice electrical and thermal characteristics table 10 lists siu output characteristics. activating data pipelining (setting br x [dr] in the memory controller) improves the ac timing. when data pipelining is activated, sp12 can be used for data bus setup even when ecc or parity are used. also, sp33a can be used as the ac speci cation for dp signals. figure 7 shows tdm input and output signals. figure 7. tdm signal diagram table 10. ac characteristics for siu outputs 1 1 output speci?ations are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. spec_num max/min characteristic max delay (ns) min delay (ns) 66 mhz 83 mhz 66 mhz 83 mhz sp31/sp30 psd v al /tea /t a 7 6 0.5 0.5 sp32/sp30 add/add_atr./baddr/ci/gbl/wt 8 6.5 0.5 0.5 sp33a/sp30 data bus 6.5 6.5 0.5 0.5 sp33b/sp30 dp 8 7 0.5 0.5 sp34/sp30 memc signals/ale 6 5 0.5 0.5 sp35/sp30 all other signals 6 5.5 0.5 0.5 serial clkin tdm input signals tdm output signals sp20 sp21 sp40/sp41
16 mpc8250 hardware speci?ations motorola preliminary?ubject to change without notice electrical and thermal characteristics figure 8 shows the interaction of several bus signals. figure 8. bus signals figure 9 shows signal behavior for all parity modes (including ecc, rmw parity, and standard parity). figure 9. parity mode diagram figure 10 shows signal behavior in memc mode. clkin aack /artry /ta /ts /tea / data bus normal mode all other input signals psd v al /tea /ta output signals add/add_atr/baddr/ci/ data bus output signals all other output signals sp11 sp12 sp15 sp10 sp10 sp10 sp30 sp30 sp30 sp30 sp32 sp33a sp35 dbg /bg /br input signals gbl/wt output signals sp31 input signal clkin data bus, ecc, and parity mode input signals dp mode input signal dp mode output signal sp13 sp10 sp14 sp10 sp33b/sp30
motorola mpc8250 hardware speci?ations 17 preliminary?ubject to change without notice electrical and thermal characteristics figure 10. memc mode diagram note generally, all mpc8250 bus and system output signals are driven from the rising edge of the input clock (clkin). memory controller signals, however, trigger on four points within a clkin cycle. each cycle is divided by four internal ticks: t1, t2, t3, and t4. t1 always occurs at the rising edge, and t3 at the falling edge, of clkin. however, the spacing of t2 and t4 depends on the pll clock ratio selected, as shown in table 11. figure 11 is a graphical representation of table 11. figure 11. internal tick spacing for memory controller signals note the upm machine outputs change on the internal tick determined by the memory controller programming; the ac speci cations are relative to the internal tick. note that sdram and gpcm machine outputs change on clkin?s rising edge. table 11. tick spacing for memory controller signals pll clock ratio tick spacing (t1 occurs at the rising edge of clkin) t2 t3 t4 1:2, 1:3, 1:4, 1:5, 1:6 1/4 clkin 1/2 clkin 3/4 clkin 1:2.5 3/10 clkin 1/2 clkin 8/10 clkin 1:3.5 4/14 clkin 1/2 clkin 11/14 clkin clkin v_clk memory controller signals sp34/sp30 clkin t1 t2 t3 t4 clkin t1 t2 t3 t4 for 1:2.5 for 1:3.5 clkin t1 t2 t3 t4 for 1:2, 1:3, 1:4, 1:5, 1:6
18 mpc8250 hardware speci?ations motorola preliminary?ubject to change without notice clock con?uration modes 1.3 clock con?uration modes to con gure the main pll multiplication factor and the core, cpm, and 60x bus frequencies, the modck[1?3] pins are sampled while hreset is asserted. table 12 shows the eight basic con guration modes. another 49 modes are available by using the con guration pin (rstconf ) and driving four pins on the data bus. 1.3.1 local bus mode table 12 describes default clock modes for the mpc8250. table 13 describes all possible clock con gurations when using the hard reset con guration sequence. note that clock con guration changes only after por is asserted. note also that basic modes are shown in boldface type. table 12. clock default modes modck[1?] input clock frequency cpm multiplication factor cpm frequency core multiplication factor core frequency 000 33 mhz 3 100 mhz 4 133 mhz 001 33 mhz 3 100 mhz 5 166 mhz 010 33 mhz 4 133 mhz 4 133 mhz 011 33 mhz 4 133 mhz 5 166 mhz 100 66 mhz 2 133 mhz 2.5 166 mhz 101 66 mhz 2 133 mhz 3 200 mhz 110 66 mhz 2.5 166 mhz 2.5 166 mhz 111 66 mhz 2.5 166 mhz 3 200 mhz table 13. clock configuration modes 1 modck_h?odck[1?] input clock frequency 2,3 cpm multiplication factor 2 cpm frequency 2 core multiplication factor 2 core frequency 2 0001_000 33 mhz 2 66 mhz 4 133 mhz 0001_001 33 mhz 2 66 mhz 5 166 mhz 0001_010 33 mhz 2 66 mhz 6 200 mhz 0001_011 33 mhz 2 66 mhz 7 233 mhz 0001_100 33 mhz 2 66 mhz 8 266 mhz 0001_101 33 mhz 3 100 mhz 4 133 mhz 0001_110 33 mhz 3 100 mhz 5 166 mhz 0001_111 33 mhz 3 100 mhz 6 200 mhz 0010_000 33 mhz 3 100 mhz 7 233 mhz 0010_001 33 mhz 3 100 mhz 8 266 mhz
motorola mpc8250 hardware speci?ations 19 preliminary?ubject to change without notice clock con?uration modes 0010_010 33 mhz 4 133 mhz 4 133 mhz 0010_011 33 mhz 4 133 mhz 5 166 mhz 0010_100 33 mhz 4 133 mhz 6 200 mhz 0010_101 33 mhz 4 133 mhz 7 233 mhz 0010_110 33 mhz 4 133 mhz 8 266 mhz 0010_111 33 mhz 5 166 mhz 4 133 mhz 0011_000 33 mhz 5 166 mhz 5 166 mhz 0011_001 33 mhz 5 166 mhz 6 200 mhz 0011_010 33 mhz 5 166 mhz 7 233 mhz 0011_011 33 mhz 5 166 mhz 8 266 mhz 0011_100 33 mhz 6 200 mhz 4 133 mhz 0011_101 33 mhz 6 200 mhz 5 166 mhz 0011_110 33 mhz 6 200 mhz 6 200 mhz 0011_111 33 mhz 6 200 mhz 7 233 mhz 0100_000 33 mhz 6 200 mhz 8 266 mhz 0100_001 reserved 0100_010 0100_011 0100_100 0100_101 0100_110 0100_111 reserved 0101_000 0101_001 0101_010 0101_011 0101_100 0101_101 66 mhz 2 133 mhz 2 133 mhz 0101_110 66 mhz 2 133 mhz 2.5 166 mhz 0101_111 66 mhz 2 133 mhz 3 200 mhz table 13. clock configuration modes 1 (continued) modck_h?odck[1?] input clock frequency 2,3 cpm multiplication factor 2 cpm frequency 2 core multiplication factor 2 core frequency 2
20 mpc8250 hardware speci?ations motorola preliminary?ubject to change without notice clock con?uration modes 0110_000 66 mhz 2 133 mhz 3.5 233 mhz 0110_001 66 mhz 2 133 mhz 4 266 mhz 0110_010 66 mhz 2 133 mhz 4.5 300 mhz 0110_011 66 mhz 2.5 166 mhz 2 133 mhz 0110_100 66 mhz 2.5 166 mhz 2.5 166 mhz 0110_101 66 mhz 2.5 166 mhz 3 200 mhz 0110_110 66 mhz 2.5 166 mhz 3.5 233 mhz 0110_111 66 mhz 2.5 166 mhz 4 266 mhz 0111_000 66 mhz 2.5 166 mhz 4.5 300 mhz 0111_001 66 mhz 3 200 mhz 2 133 mhz 0111_010 66 mhz 3 200 mhz 2.5 166 mhz 0111_011 66 mhz 3 200 mhz 3 200 mhz 0111_100 66 mhz 3 200 mhz 3.5 233 mhz 0111_101 66 mhz 3 200 mhz 4 266 mhz 0111_110 66 mhz 3 200 mhz 4.5 300 mhz 0111_111 66 mhz 3.5 233 mhz 2 133 mhz 1000_000 66 mhz 3.5 233 mhz 2.5 166 mhz 1000_001 66 mhz 3.5 233 mhz 3 200 mhz 1000_010 66 mhz 3.5 233 mhz 3.5 233 mhz 1000_011 66 mhz 3.5 233 mhz 4 266 mhz 1000_100 66 mhz 3.5 233 mhz 4.5 300 mhz 1100_000 4 66 mhz 2 133 mhz bypass 66 mhz 1100_001 4 66 mhz 2.5 166 mhz bypass 66 mhz 1100_010 4 66 mhz 3 200 mhz bypass 66 mhz 1 because of speed dependencies, not all of the possible con?urations in table 13 are applicable. 2 the user should choose the input clock frequency and the multiplication factors such that the frequency of the cpu is equal to or greater than 133 mhz (150 mhz for extended temperature parts) and the cpm ranges between 66?33 mhz. table 13. clock configuration modes 1 (continued) modck_h?odck[1?] input clock frequency 2,3 cpm multiplication factor 2 cpm frequency 2 core multiplication factor 2 core frequency 2
motorola mpc8250 hardware speci?ations 21 preliminary?ubject to change without notice clock con?uration modes 1.3.2 pci mode in pci mode only, modck_hi[0:3] and pci_modck come from the following external pins: pci_modck = lgpl5 modck_hi[0:3] = {lgpl0,lgpl1,lgpl2,lgpl3} note the minimum tval = 2 when pci_modck = 1 and minimum tval = 1 when pci_modck = 0; therefore, board designers should use clock con gurations that t this condition to achieve pci-compliant ac timing. table 15 describes all possible clock con gurations when using the mpc8250?s internal pci bridge in host mode. 3 input clock frequency is given only for the purpose of reference. user should set modck_h?odck_l so that the resulting con?uration does not exceed the frequency rating of the users part. example . if a part is rated at 266 mhz cpu, 200 mhz cpm, and 66 mhz bus, any of the following are possible (note that the three input clock frequencies are only three of many possible input clock frequencies): 1. 66 mhz input clock and modck_h?odck_l[0111?01] (with a core multiplication factor of 4 and a cpm multiplication factor of 3). the resulting con?uration equals the parts maximum possible frequencies of 266 mhz cpu, 200 mhz cpm, and 66 mhz bus. 2. 50 mhz input clock and modck_h?odck_l[0111?01] to achieve a con?uration of 200 mhz cpu, 150 mhz cpm, and 50 mhz bus. 3. 40 mhz input clock and modck_h?odck_l[0010?11] to achieve a con?uration of 200 mhz cpu, 160 mhz cpm, and 40 mhz bus. note that with each example, any one of several values for modck_h?odck_l could possibly be used as long as the resulting con?uration does not exceed the parts rating. 4 at this mode the cpu pll is bypassed (the cpu frequency equals the bus frequency). table 14. clock default con?urations in pci host mode (modck_hi = 0000) modck[1?] 1 1 assumes modck_hi = 0000. input clock frequency (bus) cpm multiplication factor cpm frequency core multiplication factor core frequency pci division factor 2 2 the frequency depends on the value of pci_modck. if pci_modck is high (logic ??, the pci frequency is divided by 2 (33 instead of 66 mhz, etc.) pci frequency 2 000 66 mhz 2 133 mhz 2.5 166 mhz 2/4 66/33 mhz 001 66 mhz 2 133 mhz 3 200 mhz 2/4 66/33 mhz 010 66 mhz 2.5 166 mhz 3 200 mhz 3/6 55/28 mhz 011 66 mhz 2.5 166 mhz 3.5 233 mhz 3/6 55/28 mhz 100 66 mhz 2.5 166 mhz 4 266 mhz 3/6 55/28 mhz 101 66 mhz 3 200 mhz 3 200 mhz 3/6 66/33 mhz 110 66 mhz 3 200 mhz 3.5 233 mhz 3/6 66/33 mhz 111 66 mhz 3 200 mhz 4 266 mhz 3/6 66/33 mhz
22 mpc8250 hardware speci?ations motorola preliminary?ubject to change without notice clock con?uration modes table 15. clock con?uration modes in pci host mode modck_h modck[1?] input clock frequency 1 (bus) cpm multiplication factor cpm frequency core multiplication factor core frequency pci division factor 2 pci frequency 2 0001_000 33 mhz 3 100 mhz 5 166 mhz 3/6 33/16 mhz 0001_001 33 mhz 3 100 mhz 6 200 mhz 3/6 33/16 mhz 0001_010 33 mhz 3 100 mhz 7 233 mhz 3/6 33/16 mhz 0001_011 33 mhz 3 100 mhz 8 266 mhz 3/6 33/16 mhz 0010_000 33 mhz 4 133 mhz 5 166 mhz 4/8 33/16 mhz 0010_001 33 mhz 4 133 mhz 6 200 mhz 4/8 33/16 mhz 0010_010 33 mhz 4 133 mhz 7 233 mhz 4/8 33/16 mhz 0010_011 33 mhz 4 133 mhz 8 266 mhz 4/8 33/16 mhz 0011_000 3 33 mhz 5 166 mhz 5 166 mhz 5 33 mhz 0011_001 3 33 mhz 5 166 mhz 6 200 mhz 5 33 mhz 0011_010 3 33 mhz 5 166 mhz 7 233 mhz 5 33 mhz 0011_011 3 33 mhz 5 166 mhz 8 266 mhz 5 33 mhz 0100_000 3 33 mhz 6 200 mhz 5 166 mhz 6 33 mhz 0100_001 3 33 mhz 6 200 mhz 6 200 mhz 6 33 mhz 0100_010 3 33 mhz 6 200 mhz 7 233 mhz 6 33 mhz 0100_011 3 33 mhz 6 200 mhz 8 266 mhz 6 33 mhz 0101_000 66 mhz 2 133 mhz 2.5 166 mhz 2/4 66/33 mhz 0101_001 66 mhz 2 133 mhz 3 200 mhz 2/4 66/33 mhz 0101_010 66 mhz 2 133 mhz 3.5 233 mhz 2/4 66/33 mhz 0101_011 66 mhz 2 133 mhz 4 266 mhz 2/4 66/33 mhz 0101_100 66 mhz 2 133 mhz 4.5 300 mhz 2/4 66/33 mhz 0110_000 66 mhz 2.5 166 mhz 2.5 166 mhz 3/6 55/28 mhz 0110_001 66 mhz 2.5 166 mhz 3 200 mhz 3/6 55/28 mhz 0110_010 66 mhz 2.5 166 mhz 3.5 233 mhz 3/6 55/28 mhz 0110_011 66 mhz 2.5 166 mhz 4 266 mhz 3/6 55/28 mhz 0110_100 66 mhz 2.5 166 mhz 4.5 300 mhz 3/6 55/28 mhz 0111_000 66 mhz 3 200 mhz 2.5 166 mhz 3/6 66/33 mhz 0111_001 66 mhz 3 200 mhz 3 200 mhz 3/6 66/33 mhz
motorola mpc8250 hardware speci?ations 23 preliminary?ubject to change without notice clock con?uration modes 0111_010 66 mhz 3 200 mhz 3.5 233 mhz 3/6 66/33 mhz 0111_011 66 mhz 3 200 mhz 4 266 mhz 3/6 66/33 mhz 0111_100 66 mhz 3 200 mhz 4.5 300 mhz 3/6 66/33 mhz 1000_000 66 mhz 3 200 mhz 2.5 166 mhz 4/8 50/25 mhz 1000_001 66 mhz 3 200 mhz 3 200 mhz 4/8 50/25 mhz 1000_010 66 mhz 3 200 mhz 3.5 233 mhz 4/8 50/25 mhz 1000_011 66 mhz 3 200 mhz 4 266 mhz 4/8 50/25 mhz 1000_100 66 mhz 3 200 mhz 4.5 300 mhz 4/8 50/25 mhz 1001_000 66 mhz 3.5 233 mhz 2.5 166 mhz 4/8 58/29 mhz 1001_001 66 mhz 3.5 233 mhz 3 200 mhz 4/8 58/29 mhz 1001_010 66 mhz 3.5 233 mhz 3.5 233 mhz 4/8 58/29 mhz 1001_011 66 mhz 3.5 233 mhz 4 266 mhz 4/8 58/29 mhz 1001_100 66 mhz 3.5 233 mhz 4.5 300 mhz 4/8 58/29 mhz 1010_000 100 mhz 2 200 mhz 2 200 mhz 3/6 66/33 mhz 1010_001 100 mhz 2 200 mhz 2.5 250 mhz 3/6 66/33 mhz 1010_010 100 mhz 2 200 mhz 3 300 mhz 3/6 66/33 mhz 1010_011 100 mhz 2 200 mhz 3.5 350 mhz 3/6 66/33 mhz 1010_100 100 mhz 2 200 mhz 4 400 mhz 3/6 66/33 mhz 1011_000 100 mhz 2.5 250 mhz 2 200 mhz 4/8 62/31 mhz 1011_001 100 mhz 2.5 250 mhz 2.5 250 mhz 4/8 62/31mhz 1011_010 100 mhz 2.5 250 mhz 3 300 mhz 4/8 62/31 mhz 1011_011 100 mhz 2.5 250 mhz 3.5 350 mhz 4/8 62/31 mhz 1011_100 100 mhz 2.5 250 mhz 4 400 mhz 4/8 62/31 mhz 1100_000 4 66mhz 2 133mhz bypass 66mhz 2/4 66/33 mhz 1100_001 4 66mhz 2.5 166mhz bypass 66mhz 3/6 55/28 mhz 1100_010 4 66mhz 3 200mhz bypass 66mhz 3/6 66/33 mhz table 15. clock con?uration modes in pci host mode (continued) modck_h modck[1?] input clock frequency 1 (bus) cpm multiplication factor cpm frequency core multiplication factor core frequency pci division factor 2 pci frequency 2
24 mpc8250 hardware speci?ations motorola preliminary?ubject to change without notice clock con?uration modes table 17 describes all possible clock con gurations when using the mpc8250?s internal pci bridge in agent mode. 1 input clock frequency is given only for the purpose of reference. user should set modck_h?odck_l so that the resulting con?uration does not exceed the frequency rating of the users part. example . if a part is rated at 266 mhz cpu, 200 mhz cpm, and 66 mhz bus, any of the following are possible (note that the three input clock frequencies are only three of many possible input clock frequencies): 1. 66 mhz input clock, modck_h?odck_l[0111?11] (with a core multiplication factor of 4 and a cpm multiplication factor of 3), and pci_modck = 0 (see note 2 below). the resulting con?uration equals the parts maximum possible frequencies of 266 mhz cpu, 200 mhz cpm, 66 mhz 60x bus, and a pci frequency of 66 mhz. 2. 50 mhz input clock, modck_h?odck_l[0111?11], and pci_modck = 0 (see note 2below) to achieve a con?uration of 200 mhz cpu, 150 mhz cpm, 50 mhz 60x bus, and a pci frequency of 50 mhz. 3. 40 mhz input clock, modck_h?odck_l[0010?00], and pci_modck = 0 (see note 2 below) to achieve a con?uration of 200 mhz cpu, 160 mhz cpm, 40 mhz 60x bus, and a pci frequency of 40 mhz. note that with each of the examples, any one of several values for modck_h?odck_l could possibly be used as long as the resulting con?uration does not exceed the parts rating. 2 the frequency depends on the value of pci_modck. if pci_modck is high (logic ??, the pci frequency is divided by 2 (33 instead of 66 mhz, etc.). 3 in this mode, pci_modck must be ?? 4 in this mode the core pll is bypassed (core frequency equals to bus frequency; for debug purpose only). table 16. clock default con?urations in pci agent mode (modck_hi = 0000) 1 1 the user should verify that all buses and functions run frequencies that are within the supported ranges. modck[1?] 2 2 assumes modck_hi = 0000. input clock frequency (pci) 3 cpm multiplication factor 3 3 the frequency depends on the value of pci_modck. if pci_modck is high (logic ??, the pci frequency is divided by 2 (33 instead of 66 mhz, etc.) and the cpm multiplication factor is multiplied by 2. cpm frequency core multiplication factor core frequency 4 4 core frequency = (60x bus frequency)(core multiplication factor) bus division factor 60x bus frequency 5 5 bus frequency = cpm frequency / bus division factor 000 66/33 mhz 2/4 133 mhz 2.5 166 mhz 2 66 mhz 001 66/33 mhz 2/4 133 mhz 3 200 mhz 2 66 mhz 010 66/33 mhz 3/6 200 mhz 3 200 mhz 3 66 mhz 011 66/33 mhz 3/6 200 mhz 4 266 mhz 3 66 mhz 100 66/33 mhz 3/6 200 mhz 3 240 mhz 2.5 80 mhz 101 66/33 mhz 3/6 200 mhz 3.5 280 mhz 2.5 80 mhz 110 66/33 mhz 4/8 266 mhz 3.5 300 mhz 3 88 mhz 111 66/33 mhz 4/8 266 mhz 3 300 mhz 2.5 100 mhz
motorola mpc8250 hardware speci?ations 25 preliminary?ubject to change without notice clock con?uration modes table 17. clock con?uration modes in pci agent mode 1 modck_h ? modck[1?] input clock frequency (pci) 2,3 cpm multiplication factor 2 cpm frequency core multiplication factor core frequency 4 bus division factor 60x bus frequency 5 0001_001 66/33 mhz 2/4 133 mhz 5 166 mhz 4 33 mhz 0001_010 66/33 mhz 2/4 133 mhz 6 200 mhz 4 33 mhz 0001_011 66/33 mhz 2/4 133 mhz 7 233 mhz 4 33 mhz 0001_100 66/33 mhz 2/4 133 mhz 8 266 mhz 4 33 mhz 0010_001 50/25 mhz 3/6 150 mhz 3 180 mhz 2.5 60 mhz 0010_010 50/25 mhz 3/6 150 mhz 3.5 210 mhz 2.5 60 mhz 0010_011 50/25 mhz 3/6 150 mhz 4 240 mhz 2.5 60 mhz 0010_100 50/25 mhz 3/6 150 mhz 4.5 270 mhz 2.5 60 mhz 0011_000 66/33 mhz 2/4 133 mhz 2.5 110mhz 3 44 mhz 0011_001 66/33 mhz 2/4 133 mhz 3 132 mhz 3 44 mhz 0011_010 66/33 mhz 2/4 133 mhz 3.5 154 mhz 3 44 mhz 0011_011 66/33 mhz 2/4 133 mhz 4 176mhz 3 44 mhz 0011_100 66/33 mhz 2/4 133 mhz 4.5 198 mhz 3 44 mhz 0100_000 66/33 mhz 3/6 200 mhz 2.5 166 mhz 3 66 mhz 0100_001 66/33 mhz 3/6 200 mhz 3 200 mhz 366 mhz 0100_010 66/33 mhz 3/6 200 mhz 3.5 233 mhz 366 mhz 0100_011 66/33 mhz 3/6 200 mhz 4 266 mhz 366 mhz 0100_100 66/33 mhz 3/6 200 mhz 4.5 300 mhz 366 mhz 0101_000 6 33 mhz 5 166 mhz 2.5 166 mhz 2.5 66 mhz 0101_001 6 33 mhz 5 166 mhz 3 200 mhz 2.5 66 mhz 0101_010 6 33 mhz 5 166 mhz 3.5 233 mhz 2.5 66 mhz 0101_011 6 33 mhz 5 166 mhz 4 266 mhz 2.5 66 mhz 0101_100 6 33 mhz 5 166 mhz 4.5 300 mhz 2.5 66 mhz 0110_000 50/25 mhz 4/8 200 mhz 2.5 166 mhz 3 66 mhz 0110_001 50/25 mhz 4/8 200 mhz 3 200 mhz 3 66 mhz 0110_010 50/25 mhz 4/8 200 mhz 3.5 233 mhz 3 66 mhz 0110_011 50/25 mhz 4/8 200 mhz 4 266 mhz 3 66 mhz 0110_100 50/25 mhz 4/8 200 mhz 4.5 300 mhz 3 66 mhz
26 mpc8250 hardware speci?ations motorola preliminary?ubject to change without notice clock con?uration modes 0111_000 66/33 mhz 3/6 200 mhz 2 200 mhz 2 100 mhz 0111_001 66/33 mhz 3/6 200 mhz 2.5 250 mhz 2 100 mhz 0111_010 66/33 mhz 3/6 200 mhz 3 300 mhz 2 100 mhz 0111_011 66/33 mhz 3/6 200 mhz 3.5 350 mhz 2 100 mhz 1000_000 66/33 mhz 3/6 200 mhz 2 160 mhz 2.5 80 mhz 1000_001 66/33 mhz 3/6 200 mhz 2.5 200 mhz 2.5 80 mhz 1000_010 66/33 mhz 3/6 200 mhz 3 240 mhz 2.5 80 mhz 1000_011 66/33 mhz 3/6 200 mhz 3.5 280 mhz 2.5 80 mhz 1000_100 66/33 mhz 3/6 200 mhz 4 320 mhz 2.5 80 mhz 1000_101 66/33 mhz 3/6 200 mhz 4.5 360 mhz 2.5 80 mhz 1001_000 66/33 mhz 4/8 266 mhz 2.5 166 mhz 4 66 mhz 1001_001 66/33 mhz 4/8 266 mhz 3 200 mhz 4 66 mhz 1001_010 66/33 mhz 4/8 266 mhz 3.5 233 mhz 4 66 mhz 1001_011 66/33 mhz 4/8 266 mhz 4 266 mhz 4 66 mhz 1001_100 66/33 mhz 4/8 266 mhz 4.5 300 mhz 4 66 mhz 1010_000 66/33 mhz 4/8 266 mhz 2.5 222 mhz 3 88 mhz 1010_001 66/33 mhz 4/8 266 mhz 3 266 mhz 3 88 mhz 1010_010 66/33 mhz 4/8 266 mhz 3.5 300 mhz 3 88 mhz 1010_011 66/33 mhz 4/8 266 mhz 4 350 mhz 3 88 mhz 1010_100 66/33 mhz 4/8 266 mhz 4.5 400 mhz 3 88 mhz 1011_000 66/33 mhz 4/8 266 mhz 2 212mhz 2.5 106 mhz 1011_001 66/33 mhz 4/8 266 mhz 2.5 265 mhz 2.5 106 mhz 1011_010 66/33 mhz 4/8 266 mhz 3 318 mhz 2.5 106 mhz 1011_011 66/33 mhz 4/8 266 mhz 3.5 371 mhz 2.5 106 mhz 1011_100 66/33 mhz 4/8 266 mhz 4 424 mhz 2.5 106 mhz 1100_000 7 66/33mhz 2/4 133mhz bypass 66mhz 2 66 mhz 1100_001 7 66/33mhz 3/6 200mhz bypass 80mhz 2.5 80 mhz 1100_010 7 66/33mhz 3/6 200mhz bypass 66mhz 3 66 mhz 1 the user should verify that all buses and functions run frequencies that are within the supported ranges. table 17. clock con?uration modes in pci agent mode (continued) 1 modck_h ? modck[1?] input clock frequency (pci) 2,3 cpm multiplication factor 2 cpm frequency core multiplication factor core frequency 4 bus division factor 60x bus frequency 5
motorola mpc8250 hardware speci?ations 27 preliminary?ubject to change without notice pinout 1.4 pinout this section provides the pin assignments and pinout list for the mpc8250. 1.4.1 pin assignments figure 12 shows the pinout of the mpc8250?s 480 tbga package as viewed from the top surface. 2 the frequency depends on the value of pci_modck. if pci_modck is high (logic ??, the pci frequency is divided by 2 (33 instead of 66 mhz, etc.) and the cpm multiplication factor is multiplied by 2. 3 input clock frequency is given only for the purpose of reference. user should set modck_h?odck_l so that the resulting con?uration does not exceed the frequency rating of the users part. example . if a part is rated at 266 mhz cpu, 200 mhz cpm, and 66 mhz bus, any of the following are possible (note that the three input clock frequencies are only three of many possible input clock frequencies): 1. 50 mhz input clock, modck_h?odck_l[0110?11] (with a core multiplication factor of 4, a cpm multiplication factor of 4, and a bus division factor of 3), and pci_modck = 0 (see note 2 above). the pci frequency is 50 mhz and the resulting con?uration equals the parts maximum possible frequencies of 266 mhz cpu, 200 mhz cpm, and 66 mhz 60x bus. 2. 66 mhz input clock, modck_h?odck_l[0100?01], and pci_modck = 1 (see note 2 above) to achieve a pci frequency of 33 mhz and a con?uration of 200mhz cpu, 200 mhz cpm, and 66 mhz 60x bus. 3. 40 mhz input clock, modck_h?odck_l[1001?11], and pci_modck = 0 (see note 2 above) to achieve a pci frequency of 40 mhz and a con?uration of 160 mhz cpu, 160 mhz cpm, and 40 mhz 60x bus. note that with each of the examples, any one of several values for modck_h?odck_l could possibly be used as long as the resulting con?uration does not exceed the parts rating. 4 core frequency = (60x bus frequency)(core multiplication factor) 5 bus frequency = cpm frequency / bus division factor 6 in this mode, pci_modck must be ?? 7 in this mode the core pll is bypassed (core frequency equals bus frequency; for debug purpose only).
28 mpc8250 hardware speci?ations motorola preliminary?ubject to change without notice pinout figure 12. pinout of the 480 tbga package as viewed from the top surface figure 13 shows the side pro le of the tbga package to indicate the direction of the top surface view. figure 13. side view of the tbga package 1 2 3 4 5 6 7 8 910111213141516 17 18 19 20 21 22 23 24 25 26 27 28 29 not to scale 1 2 3 4 5 6 7 8 9 10111213 141516171819202122 2324 2526272829 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj soldermask copper traces die copper heat spreader (oxidized for insulation) 1.27 mm pitch glob-top dam etched pressure sensitive die glob-top filled area polymide tape cavity adhesive attach view
motorola mpc8250 hardware speci?ations 29 preliminary?ubject to change without notice pinout table 18 shows the pinout list of the mpc8250. table 19 de nes conventions and acronyms used in table 18. table 18. pinout list pin name ball br w5 bg f4 abb /irq2 e2 ts e3 a0 g1 a1 h5 a2 h2 a3 h1 a4 j5 a5 j4 a6 j3 a7 j2 a8 j1 a9 k4 a10 k3 a11 k2 a12 k1 a13 l5 a14 l4 a15 l3 a16 l2 a17 l1 a18 m5 a19 n5 a20 n4 a21 n3 a22 n2 a23 n1 a24 p4 a25 p3 a26 p2 a27 p1 a28 r1
30 mpc8250 hardware speci?ations motorola preliminary?ubject to change without notice pinout a29 r3 a30 r5 a31 r4 tt0 f1 tt1 g4 tt2 g3 tt3 g2 tt4 f2 tbst d3 tsiz0 c1 tsiz1 e4 tsiz2 d2 tsiz3 f5 aa ck f3 ar tr y e1 dbg v1 dbb /irq3 v2 d0 b20 d1 a18 d2 a16 d3 a13 d4 e12 d5 d9 d6 a6 d7 b5 d8 a20 d9 e17 d10 b15 d11 b13 d12 a11 d13 e9 d14 b7 d15 b4 d16 d19 d17 d17 table 18. pinout list (continued) pin name ball
motorola mpc8250 hardware speci?ations 31 preliminary?ubject to change without notice pinout d18 d15 d19 c13 d20 b11 d21 a8 d22 a5 d23 c5 d24 c19 d25 c17 d26 c15 d27 d13 d28 c11 d29 b8 d30 a4 d31 e6 d32 e18 d33 b17 d34 a15 d35 a12 d36 d11 d37 c8 d38 e7 d39 a3 d40 d18 d41 a17 d42 a14 d43 b12 d44 a10 d45 d8 d46 b6 d47 c4 d48 c18 d49 e16 d50 b14 d51 c12 d52 b10 table 18. pinout list (continued) pin name ball
32 mpc8250 hardware speci?ations motorola preliminary?ubject to change without notice pinout d53 a7 d54 c6 d55 d5 d56 b18 d57 b16 d58 e14 d59 d12 d60 c10 d61 e8 d62 d6 d63 c2 dp0/rsr v /ext_br2 b22 irq1 /dp1/ext_bg2 a22 irq2 /dp2/tlbisync /ext_dbg2 e21 irq3 /dp3/ckstp_out /ext_br3 d21 irq4 /dp4/core_sreset /ext_bg3 c21 irq5 /dp5/tben /ext_dbg3 b21 irq6 /dp6/cse0 a21 irq7 /dp7/cse1 e20 psd v al v3 t a c22 tea v5 gbl /irq1 w1 ci /baddr29/irq2 u2 wt /baddr30/irq3 u3 l2_hit /irq4 y4 cpu_bg /baddr31/irq5 u4 cpu_dbg r2 cpu_br y3 cs0 f25 cs1 c29 cs2 e27 cs3 e28 cs4 f26 cs5 f27 table 18. pinout list (continued) pin name ball
motorola mpc8250 hardware speci?ations 33 preliminary?ubject to change without notice pinout cs6 f28 cs7 g25 cs8 d29 cs9 e29 cs10 /bctl1 f29 cs11 /ap0 g28 baddr27 t5 baddr28 u1 ale t2 bctl0 a27 pwe0 /psddqm0 /pbs0 c25 pwe1 /psddqm1 /pbs1 e24 pwe2 /psddqm2 /pbs2 d24 pwe3 /psddqm3 /pbs3 c24 pwe4 /psddqm4 /pbs4 b26 pwe5 /psddqm5 /pbs5 a26 pwe6 /psddqm6 /pbs6 b25 pwe7 /psddqm7 /pbs7 a25 psda10/pgpl0 e23 psd we /pgpl1 b24 poe /psdras /pgpl2 a24 psdcas /pgpl3 b23 pgt a /pupmwait/pgpl4/ppbs a23 psdamux/pgpl5 d22 l we0 /lsddqm0 /lbs0 /pci_cfg0 h28 l we1 /lsddqm1 /lbs1 /pci_cfg1 h27 l we2 /lsddqm2 /lbs2 /pci_cfg2 h26 l we3 /lsddqm3 /lbs3 /pci_cfg3 g29 lsda10/lgpl0/pci_modckh0 d27 lsd we /lgpl1/pci_modckh1 c28 loe /lsdras /lgpl2/pci_modckh2 e26 lsdcas /lgpl3/pci_modckh3 d25 lgt a /lupmwait/lgpl4/lpbs c26 lgpl5/lsdamux/pci_modck b27 l wr d28 table 18. pinout list (continued) pin name ball
34 mpc8250 hardware speci?ations motorola preliminary?ubject to change without notice pinout l_a14/par n27 l_a15/frame /smi t29 l_a16/trd y r27 l_a17/ird y /ckstp_out r26 l_a18/st op r29 l_a19/devsel r28 l_a20/idsel w29 l_a21/perr p28 l_a22/serr n26 l_a23/req0 aa27 l_a24/req1 /hsejsw p29 l_a25/gnt0 aa26 l_a26/gnt1 /hsled n25 l_a27/gnt2 /hsenum aa25 l_a28/rst /core_sreset ab29 l_a29/int a ab28 l_a30/req2 p25 l_a31/dllout ab27 lcl_d0/ad0 h29 lcl_d1/ad1 j29 lcl_d2/ad2 j28 lcl_d3/ad3 j27 lcl_d4/ad4 j26 lcl_d5/ad5 j25 lcl_d6/ad6 k25 lcl_d7/ad7 l29 lcl_d8/ad8 l27 lcl_d9/ad9 l26 lcl_d10/ad10 l25 lcl_d11/ad11 m29 lcl_d12/ad12 m28 lcl_d13/ad13 m27 lcl_d14/ad14 m26 lcl_d15/ad15 n29 lcl_d16/ad16 t25 table 18. pinout list (continued) pin name ball
motorola mpc8250 hardware speci?ations 35 preliminary?ubject to change without notice pinout lcl_d17/ad17 u27 lcl_d18/ad18 u26 lcl_d19/ad19 u25 lcl_d20/ad20 v29 lcl_d21/ad21 v28 lcl_d22/ad22 v27 lcl_d23/ad23 v26 lcl_d24/ad24 w27 lcl_d25/ad25 w26 lcl_d26/ad26 w25 lcl_d27/ad27 y29 lcl_d28/ad28 y28 lcl_d29/ad29 y25 lcl_d30/ad30 aa29 lcl_d31/ad31 aa28 lcl_dp0/c0/be0 l28 lcl_dp1/c1/be1 n28 lcl_dp2/c2/be2 t28 lcl_dp3/c3/be3 w28 irq0 /nmi_out t1 irq7 /int_out /ape d1 trst ah3 tck ag5 tms aj3 tdi ae6 tdo af5 tris ab4 poreset ag6 hreset ah5 sreset af6 qreq aa3 rstconf aj4 modck1/ap1/tc0/bnksel0 w2 modck2/ap2/tc1/bnksel1 w3 modck3/ap3/tc2/bnksel2 w4 table 18. pinout list (continued) pin name ball
36 mpc8250 hardware speci?ations motorola preliminary?ubject to change without notice pinout xfc ab2 clkin1 ah4 pa0/rest ar t1 /dreq3 ac29 pa1/reject1 /done3 ac25 pa2/clk20/d a ck3 ae28 pa3/clk19/d a ck4 /l1rxd1a2 ag29 pa4/reject2 /done4 ag28 pa5/rest ar t2 /dreq4 ag26 pa 6 ae24 pa7/smsyn2 ah25 pa8/smrxd2 af23 pa9/smtxd2 ah23 pa10/msnum5 ae22 pa11/msnum4 ah22 pa12/msnum3 aj21 pa13/msnum2 ah20 pa14/fcc1_rxd3 ag19 pa15/fcc1_rxd2 af18 pa16/fcc1_rxd1 af17 pa17/fcc1_rxd0/fcc1_rxd ae16 pa18/fcc1_txd0/fcc1_txd aj16 pa19/fcc1_txd1 ag15 pa20/fcc1_txd2 aj13 pa21/fcc1_txd3 ae13 pa22 af12 pa23 ag11 pa24/msnum1 ah9 pa25/msnum0 aj8 pa26/fcc1_mii_rx_er ah7 pa27/fcc1_mii_rx_dv af7 pa28/fcc1_mii_tx_en ad5 pa29/fcc1_mii_tx_er af1 pa30/fcc1_mii_crs/fcc1_r ts ad3 pa31/fcc1_mii_col ab5 pb4/fcc3_txd3/l1rsynca2/fcc3_r ts ad28 table 18. pinout list (continued) pin name ball
motorola mpc8250 hardware speci?ations 37 preliminary?ubject to change without notice pinout pb5/fcc3_txd2/l1tsynca2/l1gnta2 ad26 pb6/fcc3_txd1/l1rxda2/l1rxd0a2 ad25 pb7/fcc3_txd0/fcc3_txd/l1txda2/l1txd0a2 ae26 pb8/fcc3_rxd0/fcc3_rxd/txd3 ah27 pb9/fcc3_rxd1/l1txd2a2 ag24 pb10/fcc3_rxd2 ah24 pb11/fcc3_rxd3 aj24 pb12/fcc3_mii_crs/txd2 ag22 pb13/fcc3_mii_col/l1txd1a2 ah21 pb14/fcc3_mii_tx_en/rxd3 ag20 pb15/fcc3_mii_tx_er/rxd2 af19 pb16/fcc3_mii_rx_er/clk18 aj18 pb17/fcc3_mii_rx_dv/clk17 aj17 pb18/fcc2_rxd3/l1clkod2/l1rxd2a2 ae14 pb19/fcc2_rxd2/l1rqd2/l1rxd3a2 af13 pb20/fcc2_rxd1/l1rsyncd2/l1txd1a1 ag12 pb21/fcc2_rxd0/fcc2_rxd/l1tsyncd2/l1gntd2 ah11 pb22/fcc2_txd0/fcc2_txd/l1rxdd2 ah16 pb23/fcc2_txd1/l1txdd2 ae15 pb24/fcc2_txd2/l1rsyncc2 aj9 pb25/fcc2_txd3/l1tsyncc2/l1gntc2 ae9 pb26/fcc2_mii_crs/l1rxdc2 aj7 pb27/fcc2_mii_col/l1txdc2 ah6 pb28/fcc2_mii_rx_er/fcc2_r ts /l1tsyncb2/l1gntb2/txd1 ae3 pb29/l1rsyncb2/fcc2_mii_tx_en ae2 pb30/fcc2_mii_rx_dv/l1rxdb2 ac5 pb31/fcc2_mii_tx_er/l1txdb2 ac4 pc0/dreq1/brgo7/smsyn2 /l1clkoa2 ab26 pc1/dreq2/brgo6/l1rqa2 ad29 pc2/fcc3_cd /done2 ae29 pc3/fcc3_cts /d a ck2 /cts4 ae27 pc4/si2_l1st4/fcc2_cd af27 pc5/si2_l1st3/fcc2_cts af24 pc6/fcc1_cd aj26 pc7/fcc1_cts aj25 table 18. pinout list (continued) pin name ball
38 mpc8250 hardware speci?ations motorola preliminary?ubject to change without notice pinout pc8/cd4 /rena4/si2_l1st2/cts3 af22 pc9/cts4 /clsn4/si2_l1st1/l1tsynca2/l1gnta2 ae21 pc10/cd3 /rena3 af20 pc11/cts3 /clsn3/l1txd3a2 ae19 pc12/cd2 /rena2 ae18 pc13/cts2 /clsn2 ah18 pc14/cd1 /rena1 ah17 pc15/cts1 /clsn1/smtxd2 ag16 pc16/clk16/tin4 af15 pc17/clk15/tin3/brgo8 aj15 pc18/clk14/tga te2 ah14 pc19/clk13/brgo7 ag13 pc20/clk12/tga te1 ah12 pc21/clk11/brgo6 aj11 pc22/clk10/done1 ag10 pc23/clk9/brgo5/d a ck1 ae10 pc24/clk8/t out4 af9 pc25/clk7/brgo4 ae8 pc26/clk6/t out3 /tmclk aj6 pc27/fcc3_txd/fcc3_txd0/clk5/brgo3 ag2 pc28/clk4/tin1/t out2 /cts2 /clsn2 af3 pc29/clk3/tin2/brgo2/cts1 /clsn1 af2 pc30/clk2/t out1 ae1 pc31/clk1/brgo1 ad1 pd4/brgo8/fcc3_r ts /smrxd2 ac28 pd5/done1 ad27 pd6/d a ck1 af29 pd7/smsyn1fcc1_txclav2 af28 pd8/smrxd1/brgo5 ag25 pd9/smtxd1/brgo3 ah26 pd10/l1clkob2/brgo4 aj27 pd11/l1rqb2 aj23 pd12 ag23 pd13 aj22 pd14/l1clkoc2/i2cscl ae20 table 18. pinout list (continued) pin name ball
motorola mpc8250 hardware speci?ations 39 preliminary?ubject to change without notice pinout pd15/l1rqc2 /i2csda aj20 pd16/spimiso ag18 pd17/brgo2/spimosi ag17 pd18/spiclk af16 pd19/spisel/brgo1 ah15 pd20/r ts4 /tena4/l1rsynca2 aj14 pd21/txd4/l1rxd0a2/l1rxda2 ah13 pd22/rxd4/l1txd0a2/l1txda2 aj12 pd23/r ts3 /tena3 ae12 pd24/txd3 af10 pd25/rxd3 ag9 pd26/r ts2 /tena2 ah8 pd27/txd2 ag7 pd28/rxd2 ae4 pd29/r ts1 /tena1 ag1 pd30/txd1 ad4 pd31/rxd1 ad2 vccsyn ab3 vccsyn1 b9 gndsyn ab1 clkin2 ae11 spare4 1 u5 pci_mode 2 af25 spare6 1 v4 thermal0 3 aa1 thermal1 3 ag4 i/o power ag21, ag14, ag8, aj1, aj2, ah1, ah2, ag3, af4, ae5, ac27, y27, t27, p27, k26, g27, ae25, af26, ag27, ah28, ah29, aj28, aj29, c7, c14, c16, c20, c23, e10, a28, a29, b28, b29, c27, d26, e25, h3, m4, t3, aa4, a1, a2, b1, b2, c3, d4, e5 table 18. pinout list (continued) pin name ball
40 mpc8250 hardware speci?ations motorola preliminary?ubject to change without notice package description symbols used in table 18 are described in table 19. 1.5 package description the following sections provide the package parameters and mechanical dimensions for the mpc8250. 1.5.1 package parameters package parameters are provided in table 20. the package type is a 37.5 x 37.5 mm, 480-lead tbga. core power u28, u29, k28, k29, a9, a19, b19, m1, m2, y1, y2, ac1, ac2, ah19, aj19, ah10, aj10, aj5 ground aa5, af21, af14, af8, ae7, af11, ae17, ae23, ac26, ab25, y26, v25, t26, r25, p26, m25, k27, h25, g26, d7, d10, d14, d16, d20, d23, c9, e11, e13, e15, e19, e22, b3, g5, h4, k5, m3, p5, t4, y5, aa2, ac3 1 must be pulled down or left ?ating. 2 should be asserted if the pci function is desired; if pci is not desired, this pin should be pulled up or left ?ating. 3 for information on how to use this pin, refer to mpc8260 powerquicc ii thermal resistor guide available at www.motorola.com/semiconductors. table 19. symbol legend symbol meaning o verbar signals with overbars, such as t a , are active low. mii indicates that a signal is part of the media independent interface. table 20. package parameters parameter value package outline 37.5 x 37.5 mm interconnects 480 (29 x 29 ball array) pitch 1.27 mm nominal unmounted package height 1.55 mm table 18. pinout list (continued) pin name ball
motorola mpc8250 hardware speci?ations 41 preliminary?ubject to change without notice package description 1.5.2 mechanical dimensions figure 14 provides the mechanical dimensions and bottom surface nomenclature of the 480 tbga package. figure 14. mechanical dimensions and bottom surface nomenclature dim millimeters min max a 1.45 1.65 a1 0.60 0.70 a2 0.85 0.95 a3 0.25 b 0.65 0.85 d 37.50 bsc d1 35.56 ref e 1.27 bsc e 37.50 bsc e1 35.56 ref notes: 1. dimensions and tolerancing per asme y14.5m-1994. 2. dimensions in millimeters. 3. dimension b is measured at the maximum solder ball diameter, parallel to primary data a. 4. primary data a and the seating plane are de?ed by the spherical crowns of the solder balls.
42 mpc8250 hardware speci?ations motorola preliminary?ubject to change without notice ordering information 1.6 ordering information figure 15 provides an example of the motorola part numbering nomenclature for the mpc8250. in addition to the processor frequency, the part numbering scheme also consists of a part modi er that indicates any enhancement(s) in the part from the original production design. each part number also contains a revision code that refers to the die mask revision number and is speci ed in the part numbering scheme for identi cation purposes only. for more information, contact your local motorola sales of ce. figure 15. motorola part number key table 21. document revision history document revision substantive changes 0 initial version 0.1 note 2 for table 4 (changes in italics): ?..greater than or equal to 266 mhz, 200 mhz cpm... updated figure 15 table 17: core and bus frequency values for the following ranges of modck_hmodck: 0011_000 to 0011_100 and 1011_000 to 1011_1000 table 18: footnotes added to pins at ae11, af25, u5, and v4. 0.2 table 18: modi?d notes to pins ae11 and af25. table 18: added note to pins aa1 and ag4 (therm0 and therm1). 0.3 table 18: modi?d note to pinaf25. 0.4 table 2: notes 2 and 3 addition of note on page 6 : vddh and vdd t r a c king table 13: note 3 table 15: note 1 table 17: note 3 product code device number process technology package (zu = 480 tbga) processor frequency die revision level mpc 825x a (none = 0.29 micron c temperature range zu xxx (cpu/cpm/bus) x a = 0.25 micron) (blank = 0 to 105 ?c c = -40 to 105 ?c)
motorola mpc8250 hardware speci?ations 43 preliminary?ubject to change without notice ordering information
MPC8250EC/d how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd.; sps, technical information center, 3-20-1, minami-azabu minato-ku, tokyo 106-8573 japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong kong 852-26668334 technical information center: 1-800-521-6274 home page: http://www.motorola.com/semiconductors document comments: fax (512) 933-2625, attn: risc applications engineering information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and speci?ally disclaims any and all liability, including without limitation consequential or incidental damages. ?ypical parameters which may be provided in motorola data sheets and/or speci?ations can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?ypicals must be validated for each customer application by customers technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of?ers, employees, subsidiaries, af?iates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the u.s. patent and trademark of?e. digital dna is a trademark of motorola, inc. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/af?mative action employer. ?motorola, inc. 2002

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