cy2xp31 312.5 mhz lvpecl clock generator cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-06385 rev. *h revised april 7, 2011 features one lvpecl output pair output frequency: 312.5 mhz external crystal frequency: 25 mhz low rms phase jitter at 312. 5 mhz, using 25 mhz crystal (1.875 mhz to 20 mhz): 0.3 ps (typical) pb-free 8-pin tssop package supply voltage: 3.3 v or 2.5 v commercial and industrial temperature ranges functional description the cy2xp31 is a pll (phase locked loop) based high performance clock generator. it is optimized to generate 10 gb ethernet, sonet, and other high performance clock frequencies. it also produces an output frequency that is 12.5 times the crystal frequency. it uses cypress?s low noise vco technology to achieve less than 1 ps typical rms phase jitter, which meets both 10 gb ethernet and sonet jitter requirements. the cy2xp31 has a crystal oscillator interface input and one lvpecl output pair. pinouts figure 1. pin diagram ? 8-pin tssop /2 phase detector crystal oscillator vco /25 oe external crystal xout xin clk clk# logic block diagram 1 2 36 7 8 xout xin oe vss vdd clk# 45 vdd clk table 1. pin definition ? 8-pin tssop pin number pin name i/o type description 1, 8 vdd power 3.3 v or 2.5 v power supply. all supply current flows through pin 1 2 vss power ground 3, 4 xout, xin xtal output and inpu t parallel resonant crystal interface 5 oe cmos input output enable. when high, t he output is enabled. when low, the output is high impedance 6,7 clk#, clk lvpecl output di fferential clock output [+] feedback
cy2xp31 document #: 001-06385 rev. *h page 2 of 10 frequency table inputs output frequency (mhz) crystal frequency (mhz) pll multiplier value 25 12.5 312.5 absolute maximum conditions parameter description conditions min max unit v dd supply voltage ?0.5 4.4 v v in [1] input voltage, dc relative to v ss ?0.5 v dd + 0.5 v t s temperature, storage non operating ?65 150 c t j temperature, junction ? 135 c esd hbm esd protection, human body mo del jedec std 22-a114-b 2000 ? v ul?94 flammability rating at 1/8 in. v?0 ja [2] thermal resistance, junction to ambient 0 m/s airflow 100 c/w 1 m/s airflow 91 2.5 m/s airflow 87 notes 1. the voltage on any input or i/o pin cannot exceed the power pin during power-up. 2. simulated using apache sentinel ti software. the board is deri ved from the jedec multilayer standard. it measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). the internal layers are 100% copper pla nes, while the top and bottom layers have 50% metalization. no via s are included in the model. operating conditions parameter description min max unit v dd 3.3 v supply voltage 3.135 3.465 v 2.5 v supply voltage 2.375 2.625 v t a ambient temperature, commercial 0 70 c ambient temperature, industrial ?40 85 c t pu power-up time for all v dd to reach minimum specified voltage (ensure power ramps is monotonic) 0.05 500 ms [+] feedback
cy2xp31 document #: 001-06385 rev. *h page 3 of 10 dc electrical characteristics parameter description test conditions min typ max unit i dd operating supply current with output unterminated v dd = 3.465 v, oe = v dd , output untermi- nated ? ? 125 ma v dd = 2.625 v, oe = v dd , output untermi- nated ? ? 120 ma i ddt operating supply current with output terminated v dd = 3.465 v, oe = v dd , output terminated ? ? 150 ma v dd = 2.625 v, oe = v dd , output terminated ? ? 145 ma v oh lvpecl output high voltage v dd = 3.3 v or 2.5 v, r term = 50 to v dd ? 2.0 v v dd ?1.15 ? v dd ?0.75 v v ol lvpecl output low voltage v dd = 3.3 v or 2.5 v, r term = 50 to v dd ? 2.0 v v dd ?2.0 ? v dd ?1.625 v v od1 lvpecl peak-to-peak output voltage swing v dd = 3.3 v or 2.5 v, r term = 50 to v dd ? 2.0 v 600 ? 1000 mv v od2 lvpecl output voltage swing (v oh - v ol ) v dd = 2.5 v, r term = 50 to v dd ? 1.5 v 500 ? 1000 mv v ocm lvpecl output common mode voltage (v oh + v ol )/2 v dd = 2.5 v, r term = 50 to v dd ? 1.5 v 1.2 ? ? v i oz lvpecl output leak age current output off, oe = v ss ?35 ? 35 a v ih input high voltage, oe pin 0.7*v dd ?v dd +0.3 v v il input low voltage, oe pin ?0.3 ? 0.3*v dd v i ih input high current, oe pin oe = v dd ??115a i il input low current, oe pin oe = v ss ?50 ? ? a c in [5] input capacitance, oe pin ? 15 ? pf c inx [5] pin capacitance, xin & xout ? 4.5 ? pf ac electrical characteristics [5] parameter description conditions min typ max unit f out output frequency ? 312.5 ? mhz t r , t f [3] output rise or fall time 20% to 80% of full output swing ? 0.5 1.0 ns t jitter( ) [6] rms phase jitter (random) 312.5 mhz, (1.875 to 20 mhz) ? 0.3 ? ps t dc [7] output duty cycle measured at zero crossing point 45 ? 55 % t ohz output disable time time from falling edge on oe to stopped outputs (asynchronous) ? ? 100 ns t oe output enable time time from rising edge on oe to outputs at a valid frequency (asynchronous) ? ? 100 ns t lock startup time time for clk to reach valid frequency measured from the time v dd = v dd (min.) ??5ms recommended crystal specifications [4] parameter description min max unit mode mode of oscillation fundamental f frequency 25 25 mhz esr equivalent series resistance ? 50 c s shunt capacitance ? 7 pf [+] feedback
cy2xp31 document #: 001-06385 rev. *h page 4 of 10 parameter measurements figure 2. 3.3 v output load ac test circuit figure 3. 2.5 v output load ac test circuit figure 4. output dc parameters figure 5. output rise and fall time notes 3. refer to figure 5 on page 4 . 4. characterized using an 18 pf parallel resonant crystal. 5. not 100% tested, guaranteed by design and characterization. 6. refer to figure 6 on page 5 . 7. refer to figure 7 on page 5 . scope v dd v ss lvpecl 50 50 z = 50 z = 50 clk# clk 2v -1.3v +/- 0.165v scope v dd v ss lvpecl 50 50 z = 50 z = 50 clk# clk 2v -0.5v +/- 0.125v clk v a v b clk# v od v ocm = (v a + v b )/2 20% 80% t r clk 20% 80% clk# t f [+] feedback
cy2xp31 document #: 001-06385 rev. *h page 5 of 10 figure 6. rms phase jitter figure 7. output duty cycle figure 8. output enable timing phase noise phase noise mask offset frequency f1 f2 rms jitter = area under the masked phase noise plot noise power clk t pw t period t dc = t pw t period clk# oe clk high impedance t ohz t oe v il v ih clk# [+] feedback
cy2xp31 document #: 001-06385 rev. *h page 6 of 10 application information power supply filtering techniques as in any high speed analog circuitry, noise at the power supply pins can degrade performance. to achieve optimum jitter perfor- mance, use good power supply isolation practices. figure 9 illus- trates a typical filtering scheme. because all of the current flows through pin 1, the resistance and inductance between this pin and the supply is minimized. a 0.01 or 0.1 f ceramic chip capacitor is also located close to this pin to provide a short and low impedance ac path to ground. a 1 to 10 f ceramic or tantalum capacitor is located in the general vicinity of this device and may be shared with other devices. figure 9. power supply filtering termination for lvpecl output the cy2xp31 implements its lvpecl driver with a current steering design. for proper operation, it requires a 50 ohm dc termination on each of the two output signals. for 3.3 v operation, this data sheet specifies output levels for termination to v dd ?2.0 v. this same termination voltage can also be used for v dd = 2.5 v operation, or it can be terminated to v dd -1.5 v. note that it is also possible to terminate with 50 ohms to ground (v ss ), but the high and low signal levels differ from the data sheet values. termination resistors are best located close to the desti- nation device. to avoid reflec tions, trace characteristic impedance (z 0 ) should match the termination impedance. figure 10 shows a standard termination scheme. figure 10. lvpecl output termination crystal input interface the cy2xp31 is characterized with 18 pf parallel resonant crystals. the capacitor values shown in figure 11 are deter- mined using a 25 mhz 18 pf parallel resonant crystal and are chosen to minimize the ppm error. note that the optimal values for c1 and c2 depend on the parasitic trace capacitance and are therefore layout dependent. figure 11. crystal input interface 3.3v 10 f 0.1 f v dd v dd 0.01 f (pin 1) (pin 8) clk 84 84 z0 = 50 z0 = 50 3.3v 125 125 in clk# device xin xout x1 18 pf parallel crystal c1 33 pf c2 27 pf [+] feedback
cy2xp31 document #: 001-06385 rev. *h page 7 of 10 ordering code definitions package drawing and dimensions figure 12. 8-pin thin shrunk small outline package (4.40 mm body) z8 ordering information part number package type product flow cy2xp31zxc 8-pin tssop commercial, 0 c to 70 c cy2xp31zxct 8-pin tssop ? tape and reel commercial, 0 c to 70 c cy2xp31zxi 8-pin tssop industrial, -40 c to 85 c cy2xp31zxit 8-pin tssop ? tape and reel industrial, -40 c to 85 c t = tape and reel temperature range : c = commercial, i = industrial pb-free package type part identifier family company id: cy = cypress xx cy xxx z x t c/i 51-85093 *c [+] feedback
cy2xp31 document #: 001-06385 rev. *h page 8 of 10 acronyms document conventions table 2. acronyms used acronym description clkout clock output cmos complementary metal oxide semiconductor dpm die pick map eprom erasable programmable read only memory lvds low-voltage differential signaling lvpecl low voltage positive emitter coupled logic ntsc national televi sion system committee oe output enable pal phase alternate line pd power-down pll phase locked loop ppm parts per million ttl transistor transistor logic table 3. units of measure symbol unit of measure c degrees celsius khz kilohertz k kilohms mhz megahertz m megaohms a microamperes s microseconds v microvolts vrms microvolts root-mean-square ma milliamperes mm millimeters ms milliseconds mv millivolts na nanoamperes ns nanoseconds nv nanovolts ohms [+] feedback
cy2xp31 document #: 001-06385 rev. *h page 9 of 10 document history page document title: cy2xp31 312. 5 mhz lvpecl clock generator document number: 001-06385 revision ecn orig. of change submission date description of change ** 422680 rgl see ecn new data sheet *a 506198 rgl see ecn supplied values in tbds, change status from advance information to preliminary *b 1337067 jwk / kvm /ari see ecn changed vcc* to vdd*, vee to vss, gave pins 1 and 8 the same name (vdd), added msl and cin specifications, removed pull up from pin 5, changed v il , v ih , i ih , i dd , i dda , v oh , v ol , t r and t f specifications, added commercial temperature, changed supply filtering recommendations removed alternate termination figure, cleaned up several drawings fixed cross references and edited data sheet for template compliance, title change *c 2669117 kvm/ aesa 03/05/2009 changed crystal frequency to 25 mhz only; removed other frequencies; output frequencies adjusted accordingly, changed phase jitter value, removed msl spec changed iil and iih values, changed rise / fall time value from 350 ps to 500 ps changed max junction temp from 125 c to 135 c, added thermal resistance clarified that idd is with outputs loaded, changed data sheet status to final. *d 2700242 kvm/pyrs 04/30/2009 typos: changed vcc to vdd oe pin capacitance changed from 7pf to 15pf changed idd footnote reformatted ac & dc tables added specs cinx and ioz added oe timing, and startup timing added oe waveforms added idd for 2.5 v changed footnote about external power dissipation *e 2718433 wwz/hmt 06/12/2009 no change. submit to ecn for product launch. *f 2767308 kvm 09/22/2009 add i dd spec for unterminated outputs change parameter name for i dd (terminated outputs) from i dd to i ddt remove i dd footnote about externally dissipated current add footnote reference to c in and c inx :not 100% tested add max limit for t r , t f : 1.0 ns change t lock max from 10 ms to 5 ms *g 2896121 kvm 03/19/2010 updated package diagram (figure 12) *h 3219081 bash 04/07/2011 template and style u pdates as per current cypress standards. added ordering code definitions, ac ronyms, and units of measure. updated package diagram to *c. [+] feedback
document #: 001-06385 rev. *h revised april 7, 2011 page 10 of 10 all products and company names mentioned in this document may be the trademarks of their respective holders. cy2xp31 ? cypress semiconductor corporation, 2006-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.com/go/automotive clocks & buffers cypress.com/go/clocks interface cypress.com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cypress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypre ss.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback
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