1/4 rev. a structure silicon monolithic integrated circuit product series 1ch piezo driv er built-in 15mhz oscillator type bh6456gul features ? built-in 15mhz oscillator ? built in 1ch h bridge driver ? 2-wire serial interface (i2c-compatible) ? absolute maximum ra tings (ta=+25c) parameter symbol limit unit power supply voltage vc c -0.3 to +4.5 v motor power supply volta ge vm -0.3 to +5.5 v power save input voltage vps -0.3 to vcc+0.3 v control input voltage vin -0.3 to vcc+0.3 v power dissipation pd 530 1 mw operating temperature range topr -25 to +85 c junction temperature tjmax +125 c storage temperature range tstg -55 to +125 c h-bridge output current iout -500 to +500 2 ma 1 conditions: mounted on a glass epoxy board (50mm ? 58mm ? 1.75mm; 8 layers). in case of ta>25c, reduced by 5.3 mw/c. 2 must not exceed pd, aso, or tjmax of 125c. ? operating conditions (ta= -25c to +85c) parameter symbol min. typ. max. unit power supply voltage vcc 2.3 3.0 3.6 v motor power supply voltage vm 2.3 3.0 4.8 v power save input voltage vps 0 - vcc v control input voltage vin 0 - vcc v 2-wire serial interface transmission rate scl - - 400 khz h-bridge output current iout - - ? 400 3 ma 3 must not exceed pd, aso. this product is not designed for pr otection against radioactive rays. status of this document
2/4 rev. a electrical characteristics (unless othe rwise specified ta=25c, vcc=vm=3.0v) parameter symbol limit unit conditions min. t yp .max. overall circuit current during standby operation iccst - 0 1 a ps=l circuit current icc - 3.2 6.4 ma ps=h, scl=400khz, osc active uvlo uvlo volta g e vuvlo 1.8 - 2.2 v power save in p ut hi g h level in p ut volta g e vpsh 1.5 - vcc v low level input volta g e vpsl 0 - 0.5 v hi g h level input current ipsh 15 30 60 a vinh=3.0v low level input current ipsl -3 0 - a vinl=0v control in p ut ( sda,scl ) hi g h level in p ut volta g e vinh 1.5 - vcc v low level input volta g e vinl 0-0.5v low level output volta g e vol - - 0.4 v iin=3.0ma ( sda ) hi g h level input current iinh -10 - 10 a input volta g e=vcc low level input current iinl -10 - 10 a input volta g e=gnd h brid g e drive output on-resistance ronp - 0.7 1.0 ? ronn - 0.7 1.0 ? cycle length of sequence drive tmin 10.35 10.67 11.00 s 4 built in clk 160 count output rise time t r -0.10.8 s 5 7.5 load condition output fall time tf - 0.02 0.4 s 5 7.5 load condition 4 the time that 1 cycle of sequence drive at the below setting of 2-wire serial data ta[7:0]=8?h13, brake1[7:0]=8?h03, tb[7:0]=8?h1e, brake2[7:0]=8?h6b, osc[2:0]=3?h0 5 output switching wave 2-wire serial interface specification (fast mode : scl=400khz) 100% 0% tf tr 90% 10% 10% 90% output voltage write mode : s 0 0 0 1 1 0 0 0 a pst2t1t0w3w2w1w0 a d7d6d5d4d3d2d1d0 a p master is output write up date slave is output read mode :s00011000apst2t1t0w3w2w1w0as00011001ad7d6d5d4d3d2d1d 0na p write read s=start condition a=acknowledge ps=power save w3w0=resister addre ss p=stop condition a=not acknowledge t2t0=test bit d7d0=data
3/4 rev. a 1 2 3 4 avm outb scl sda b outa gnd vcc ps fig4. bh6456gul pin arrangement (top view) top view side view bottom view 1.0 0.05 1.95 0.05 0.1 0.05 0.55max 0.25 0.1 ( 0.15) index post 1pin mark p=0.5 1 0.25 0.05 p=0.5 3 0.225 0.05 characteristics of the sda and scl bus lines for 2-wire serial interface. (unless otherwise specified, ta=-25 +85c, vcc=2.3 3.6v ) parameter symbol fast-mode 6 standard-mode 6 unit min. typ. max. min. typ. max. scl clock frequency fscl - - 400 - - 100 khz high period of the scl clock thigh 0.6 - - 4.0 - - s low period of the scl clock tlow 1.3 - - 4.7 - - s rise time of sda signal tr - - 0.3 - - 1.0 s fall time of sda signal tf - - 0.3 - - 0.3 s hold time (repeated) start condition thd:sta 0.6 - - 4.0 - - s set-up time (repeated) start condition tsu:sta 0.6 - - 4.7 - - s data hold time thd:dat 0 - 0.9 0 - 3.45 s data set-up time tsu:dat 100 - - 250 - - ns set-up time for stop condition tsu:sto 0.6 - - 4.0 - - s bus free time between a stop and start condition tbuf 1.3 - - 4.7 - - s pulse width of spikes which must be suppressed by the input filter ti 0 - 50 0 - 50 ns 6 standard-mode and fast-mode 2-wire serial interface devices must be able to transmit or receive at that speed. the maximum bit transfer rates of 100 kbit/s for standard-mode devices and 400 kbit/s for fast-mode devices this transfer rates is provided the maximum transfer rates, for example it is able to drive 100 kbit/s of clocks with fast-mode . definition of timing on the 2-wire serial interface fig.1 definition of timing for serial data fig.2 definition of timing for start and stop bit package outline pin arrangement top view block diagram scl tbuf sda thd : sta tsu : dat tr tf thd : dat thigh tlow scl start bit sda stop bit tsu : sta thd : sta tsu : sto fig5. bh6456gul block diagram fig3. vcsp50l1 package (unit mm) sda scl vcc vreg gnd outb outa vm pre driver band gap uvlo 2-wire serial interface 15mhz osc controller ps 4b 3a 4a 3b 2b 2a 1b 1a tsd h bridge aau lot no.
4/4 rev. a resister map address w3 w2 w1 w0 d7 d6 d5 d4 d3 d2 d1 d 0h 0 0 0 0 hize initb[2] initb[1] initb[0] init start mode dir 1h 0 0 0 1 ta[7] ta[6] ta[5] ta[4] ta[3] ta[2] ta[1] ta[0] 2h 0 0 1 0 brake1[7] brake1[6] brake1[5] brake1[4] brake1[3] brake1[2] brake1[1] brake1[0] 3h 0 0 1 1 tb[7] tb[6] tb[5] tb[4] tb[3] tb[2] tb[1] tb[0] 4h 0 1 0 0 brake2[7] brake2[6] brake2[5] brake2[4] brake2[3] brake2[2] brake2[1] brake2[0] 5h 0 1 0 1 cnt[7] cnt[6] cnt[5] cnt[4] cnt[3] cnt[2] cnt[1] cnt[0] 6h 0 1 1 0 cnt[15] cnt[14] cnt[13] cnt[12] cnt[11] cnt[10] cnt[9] cnt[8] 7h 0 1 1 1 pa pb osc[2] osc[1] osc[0] cntck[2] cntck[1] cntck[0] 8h 1 0 0 0 test test test test test test test test 9h 1 0 0 1 test test test test test test test test ah 1 0 1 0 test test test test test test ext initext bh 1 0 1 1 test test test test test test test test ch 1 1 0 0 test test test test test test test test * a low signal should be input to the test bit at all times operation notes (1) absolute maximum ratings use of the ic in excess of absolute maximum ratings such as the applied voltage or operating temperature range (topr) may resul t in ic damage. assumptions should not be made regarding th e state of the ic (short mode or open mode) when such damage is suffered. the implem entation of a physical safety measure such as a fuse should be considered when us e of the ic in a special mode where the absolute maximum rat ings may be exceeded is anticipated. (2) power supply lines regenerated current may flow as a result of the inductance of printed circuit board. insert capacitors between the power supply and ground pins to serve as a route for regenerated current. determine the capacitance in full consideration of all the characteristics of the ele ctrolytic capacitor, because the electrolytic capacitor may loose some capacitance at low temperatures. if the c onnected power supply does not have sufficient current absorption capacity, regenerative current will cause the voltage on the power supply line to rise, which combined with the product and its peripheral circuitry may exceed the absolute maximum ratings. it is recommended to implement a physi cal safety measure such as the insertion of a voltage clamp diode between the power supply and ground pins. (3) ground potential ensure a minimum gnd pin potential in all operating conditions. (4) setting of heat use a thermal design that allows for a sufficient margin in li ght of the power dissipation (pd) in actual operating conditions. (5) actions in strong magnetic field use caution when using the ic in the pres ence of a strong magnetic field as doing so may cause the ic to malfunction. (6) aso when using the ic, set that it does not exceed absolute maximum ratings or aso. (7) thermal shutdown circuit this ic incorporates a thermal shutdown circuit (tsd). if the temperature of the chip reaches the following temperature, the mo tor output will be opened. tsd is designed only to shut the ic off to prevent runaway thermal operation. it is not de signed to protect the ic or g uarantee its operation. do not continue to use the ic after operating this circuit or use the ic in an environment where the operation of this circuit is assumed. tsd on temperature [c] (typ.) hy steresis temperature [c] (typ.) 150 20 (8) ps terminal release ps after rising vcc. ps works resetting logic as well. if keep connecting ps with vcc, resetting cannot be done cause m isoperating or destroy.
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