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ds05-50110-1e fujitsu semiconductor data sheet mcp (multi-chip package) flash memory & sram cmos 8m ( 8/ 16) flash memory & 2m ( 8) static ram MB84VD2002 -10 /mb84vd2003 -10 n features ? power supply voltage of 2.7 to 3.6 v ? high performance 100 ns maximum access time ? operating temperature C20 to +85 c flash memory ? simultaneous operations read-while erase or read-while-program ? minimum 100,000 write/erase cycles ? sector erase architecture two 16 k byte, four 8 k bytes, two 32 k byte, and fourteen 64 k bytes. any combination of sectors can be concurrently erased. also supports full chip erase. ? boot code sector architecture MB84VD2002: top sector mb84vd2003: bottom sector ? embedded erase tm algorithms automatically pre-programs and erases the chip or any sector ? embedded program tm algorithms automatically writes and verifies data at specified address ?data polling and toggle bit feature for detection of program or erase cycle completion ? ready-busy output (ry/by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, automatically switch themselves to low power mode. ?low v cc write inhibit 2.5 v ? erase suspend/resume suspends the erase operation to allow a read in another sector within the same device ? please refer to "mbm29dl800ta/ba" data sheet in detailed function sram ? power dissipation operating : 35 ma max. standby : 50 m a max. ? power down features using ce1 s and ce2s ? data retention supply voltage: 2.0 v to 3.6 v embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc.
2 MB84VD2002 -10 /mb84vd2003 -10 n block diagram n example of connection with chipset v ss v cc s 8 m bit reset flash memory we 2 m bit static ram ce f a 0 to a 18 oe ce1 s v ss v cc f a 0 to a 18 a 0 to a 16 dq 0 to dq 7 ry/by ce2s a -1 sa byte dq 8 to dq 15 a[0:19] rom_cs/ ram_cs/ hwr/ lwr/ rd/ d[0:15] chipset MB84VD2002/3 dq[0:15] oe we ce2s v cc s ce1 s ce f sa a[0:18] v cc v cc f byte reset ry/by a[1:19] a0 battery backup d[0:15] battery backup control
3 MB84VD2002 -10 /mb84vd2003 -10 n pin assignments (top view) abcdef gh 6ce1 sv ss dq 1 a 1 a 2 a 4 ce2s a 9 5a 10 dq 5 dq 2 a 0 a 3 a 7 ry/by a 14 4oe dq 7 dq 4 dq 0 a 6 a 18 reset a 15 3a 11 a 8 a 5 dq 8 dq 3 dq 12 a 12 byte 2a 13 a 17 sa* ce fdq 10 v cc fdq 6 dq 15 /a -1 1we v cc sa 16 v ss dq 9 dq 11 dq 13 dq 14 table 1 pin configuration pin function input/ output a 0 to a 16 address inputs (common) i a -1 , a 17 to a 18 address input (flash) i sa address input (sram) i dq 0 to dq 7 data inputs/outputs (common) i/o dq 8 to dq 15 data inputs/outputs (flash) i/o ce f chip enable (flash) i ce1 s chip enable (sram) i ce2s chip enable (sram) i oe output enable (common) i we write enable (common) i ry/by ready/busy outputs (flash) o byte selects 8-bit or 16-bit mode (flash) i reset hardware reset pin/sector protection unlock (flash) i n.c. no internal connection v ss device ground (common) power v cc f device power supply (flash) power v cc s device power supply (sram) power *: a 17 for sram
4 MB84VD2002 -10 /mb84vd2003 -10 n product line up n bus operations legend: l = v il , h = v ih , x = v il or v ih . see dc characteristics for voltage levels. notes: 1. other operations except for indicated this column are inhibited. 2. we can be v il if oe is v il , oe at v ih initiates the write operations. 4. do not apply ce f = v il , ce1 s = v il and ce2s = v ih at a time. flash memory sram ordering part no. v cc = 3.0 v MB84VD2002-10/mb84vd2003-10 max. address access time (ns) 100 100 max. ce access time (ns) 100 100 max. oe access time (ns) 40 50 table 2 user bus operations (byte = v il ) operation (1), (3) ce fce1 sce2s oe we dq 0 to dq 7 dq 8 to dq 15 reset full standby h hx x x high-z high-z h xl output disable x x x h h high-z high-z h read from flash (2) l hx lh d out high-z h xl write to flash l hx hl d in high-z h xl read from sram h l h l h d out high-z h write to sram h l h x l d in high-z h flash hardware reset x hx x x high-z high-z l xl table 3 user bus operations (byte = v ih ) operation (1), (3) ce fce1 sce2s oe we dq 0 to dq 7 dq 8 to dq 15 reset full standby h hx x x high-z high-z h xl output disable x x x h h high-z high-z h read from flash (2) l hx lh d out d out h xl write to flash l hx hl d in d in h xl read from sram h l h l h d out high-z h write to sram h l h x l d in high-z h flash hardware reset x hx x x high-z high-z l xl +0.6 v C0.3 v
5 MB84VD2002 -10 /mb84vd2003 -10 n flexible sector-erase architecture on flash memory ? two 16 k byte, four 8 k bytes, two 32 k byte, and fourteen 64 k bytes. ? individual-sector, multiple-sector, or bulk-erase capability. 16k byte/8k word 32k byte/16k word 8k byte/4k word 8k byte/4k word 8k byte/4k word 8k byte/4k word 32k byte/16k word 16k byte/8k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 7ffffh 7e000h 7a000h 79000h 78000h 77000h 76000h 72000h 70000h 68000h 60000h 58000h 50000h 48000h 40000h 38000h 30000h 28000h 20000h 18000h 10000h 08000h 00000h fffffh fc000h f4000h f2000h f0000h ee000h ec000h e4000h e0000h d0000h c0000h b0000h a0000h 90000h 80000h 70000h 60000h 50000h 40000h 30000h 20000h 10000h 00000h 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 16k byte/8k word 32k byte/16k word 8k byte/4k word 8k byte/4k word 8k byte/4k word 8k byte/4k word 32k byte/16k word 16k byte/8k word fffffh f0000h e0000h d0000h c0000h b0000h a0000h 90000h 80000h 70000h 60000h 50000h 40000h 30000h 20000h 1c000h 14000h 12000h 10000h 0e000h 0c000h 04000h 00000h 7ffffh 78000h 70000h 68000h 60000h 58000h 50000h 48000h 40000h 38000h 30000h 28000h 20000h 18000h 10000h 0c000h 0a000h 09000h 08000h 07000h 06000h 02000h 00000h mbm29dl800ta sector architecture mbm29dl800ba sector architecture ( 16) ( 8) ( 16) ( 8) bank 2 bank 1 bank 2 bank 1 MB84VD2002 sector architecture mb84vd2003 sector architecture
6 MB84VD2002 -10 /mb84vd2003 -10 note: the address range is a 18 : a -1 if in byte mode (byte = v il ). the address range is a 18 : a 0 if in word mode (byte = v ih ). table 4 sector address tables (mb84dv2002) bank sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range bank address a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 2 sa0 0000xxx 64/32 00 000h to 0ffffh 00000h to 07fffh sa1 0001xxx 64/32 10 000h to 1ffffh 08000h to 0ffffh sa2 0010xxx 64/32 20 000h to 2ffffh 10000h to 17fffh sa3 0011xxx 64/32 30 000h to 3ffffh 18000h to 1ffffh sa4 0100xxx 64/32 40 000h to 4ffffh 20000h to 27fffh sa5 0101xxx 64/32 50 000h to 5ffffh 28000h to 2ffffh sa6 0110xxx 64/32 60 000h to 6ffffh 30000h to 37fffh sa7 0111xxx 64/32 70 000h to 7ffffh 38000h to 3ffffh sa8 1000xxx 64/32 80 000h to 8ffffh 40000h to 47fffh sa9 1001xxx 64/32 90 000h to 9ffffh 48000h to 4ffffh sa101010xxx 64/32 a0 000h to affffh 50000h to 57fffh sa111011xxx 64/32 b0 000h to bffffh 58000h to 5ffffh sa121100xxx 64/32 c0 000h to cffffh 60000h to 67fffh sa131101xxx 64/32 d0 000h to dffffh 68000h to 6ffffh bank 1 sa14111000x 16/8 e 0000h to e3fffh 70000h to 71fffh sa151110 01x 32/16 e4000h to e7fffh, e8000h to ebfffh 72000h to 73fffh, 74000h to 75fffh 10x sa161110110 8/4 ec000h to edfffh7 6000h to 76fffh sa171110111 8/4 ee000h to effffh7 7000h to 77fffh sa181111000 8/4 f 0000h to f1fffh 78000h to 78fffh sa191111001 8/4 f 2000h to f3fffh 79000h to 79fffh sa201111 01x 32/16 f4000h to f7fffh, f8000h to fbfffh 7a000h to 7bfffh, 7c000h to 7dfffh 10x sa21111111x 16/8 fc000h to fffffh7e000h to 7ffffh
7 MB84VD2002 -10 /mb84vd2003 -10 note: the address range is a 18 : a -1 if in byte mode (byte = v il ). the address range is a 18 : a 0 if in word mode (byte = v ih ). table 5 sector address tables (mb84dv2003) bank sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range bank address a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 2 sa211111xxx 64/32 f0 000h to fffffh 78000h to 7ffffh sa201110xxx 64/32 e0 000h to effffh 70000h to 77fffh sa191101xxx 64/32 d0 000h to dffffh 68000h to 6ffffh sa181100xxx 64/32 c0 000h to cffffh 60000h to 67fffh sa171011xxx 64/32 b0 000h to bffffh 58000h to 5ffffh sa161010xxx 64/32 a0 000h to affffh 50000h to 57fffh sa151001xxx 64/32 90 000h to 9ffffh 48000h to 4ffffh sa141000xxx 64/32 80 000h to 8ffffh 40000h to 47fffh sa130111xxx 64/32 70 000h to 7ffffh 38000h to 3ffffh sa120110xxx 64/32 60 000h to 6ffffh 30000h to 37fffh sa110101xxx 64/32 50 000h to 5ffffh 28000h to 2ffffh sa100100xxx 64/32 40 000h to 4ffffh 20000h to 27fffh sa9 0011xxx 64/32 30 000h to 3ffffh 18000h to 1ffffh sa8 0010xxx 64/32 20 000h to 2ffffh 10000h to 17fffh bank 1 sa7 000111x 16/8 1c000h to 1ffffh0e000h to 0ffffh sa6 0001 10x 32/16 14000h to 17fffh, 18000h to 1bfffh 0a000h to 0bfffh, 0c000h to 0dfffh 01x sa5 0001001 8/4 1 2000h to 13fffh 09000h to 09fffh sa4 0001000 8/4 1 0000h to 11fffh 08000h to 08fffh sa3 0000111 8/4 0e000h to 0ffffh0 7000h to 07fffh sa2 0000110 8/4 0c000h to 0dfffh0 6000h to 06fffh sa1 0000 10x 32/16 08000h to 0bfffh, 04000h to 07fffh 04000h to 05fffh, 02000h to 03fffh 01x sa0 000000x 16/8 0 0000h to 03fffh 00000h to 01fffh
8 MB84VD2002 -10 /mb84vd2003 -10 *1: a -1 is for byte mode. (b): byte mode (w): word mode table 6. 1 flash memory autoselect codes type a 6 a 1 a 0 a -1 *1 code (hex) manufacturers code v il v il v il v il 04h device code MB84VD2002 byte v il v il v ih v il 4ah word x 224ah mb84vd2003 byte v il v il v ih v il cbh word x 22cbh table 6. 2 expanded autoselect code table type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturers code 04h a -1 /0000000000000100 device code MB84VD2002 (b) (w) 4ah 224ah a -1 0 hi-z 0 hi-z 1 hi-z 0 hi-z 0 hi-z 0 hi-z 1 hi-z 0 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 mb84vd2003 (b) (w) cbh 22cbh a -1 0 hi-z 0 hi-z 1 hi-z 0 hi-z 0 hi-z 0 hi-z 1 hi-z 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 1 1
9 MB84VD2002 -10 /mb84vd2003 -10 notes: 1. address bits a 11 to a 18 = x = h or l for all address commands except or program address (pa), sector address (sa), and bank address (ba). 2. bus operations are defined in tables 2 and 3. 3. ra = address of the memory location to be read pa = address of the memory location to be programmed addresses are latched on the falling edge of the write pulse. sa = address of the sector to be erased. the combination of a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 will uniquely select any sector. ba = bank address (a 16 to a 18 ) 4. rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the falling edge of write pulse. 5. spa =sector address to be protected. set sector address (sa) and (a 6 , a 1 , a 0 ) = (0, 1, 0). sd = sector protection verify data. output 01h at protected sector addresses and output 00h at unprotected sector addresses. * : this command is valid while fast mode. table 7 flash memory command definitions command sequence bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data read/reset word 1 xxxh f0h byte read/reset word 3 555h aah 2aah 55h 555h f0hrard byte aaah 555h aaah autoselect word 3 555h aah 2aah 55h (ba) 555h 90h byte aaah 555h (ba) aaah program word 4 555h aah 2aah 55h 555h a0hpapd byte aaah 555h aaah chip erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h byte aaah 555h aaah aaah 555h aaah sector erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h byte aaah 555h aaah aaah 555h erase suspend 1 bab0h erase resume 1 ba30h set to fast mode word 3 555h aah 2aah 55h 555h 20h byte aaah 555h aaah fast program * word 2 xxxh a0hpapd byte xxxh reset from fast mode * word 2 ba 90h xxxh f0h byte ba xxxh extended sector protect word 4 xxxh 60h spa 60h spa 40h spa sd byte
10 MB84VD2002 -10 /mb84vd2003 -10 n absolute maximum ratings storage temperature .................................................................................................. C55c to + 125c ambient temperature with power applied .................................................................. C25c to +85c voltage with respect to ground all pins (note) .......................................................... C0.3 v to v cc f +0.5 v C0.3 v to v cc s +0.5 v v cc f/v cc s supply (note) .............................................................................................. C0.3 v to +4.6 v note: minimum dc voltage on input or i/o pins are C0.5 v. during voltage transitions, inputs may negativeovershoot v ss to C2.0 v for periods of up to 20 ns. maximum dc voltage on output and i/o pins are v cc f +0.5 v or v cc s +0.5 v. during voltage transitions, outputs may positive overshoot to v cc +2.0 v for periods of up to 20 ns. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating ranges commercial devices ambient temperature (t a ) .........................................................................C20c to +85c v cc f/v cc s supply voltages.........................................................................+2.7 v to +3.6 v operating ranges define those limits between which the functionality of the device is guaranteed. warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand.
11 MB84VD2002 -10 /mb84vd2003 -10 n dc characteristics * : v cc indicate lower of v cc f or v cc s ** :during standby mode with ce1 s = v ccs C 0.2 v, ce2s should be ce2s < 0.2v or ce2s > v ccs C 0.2v *** :embeded algorithm (program or erase) is in progress. (@5 mhz) parameter symbol parameter description test conditions min. typ. max. unit i li input leakage current C1.0 +1.0 m a i lo output leakage current C1.0 +1.0 m a i cc1 f flash v cc active current (read) v cc f = v cc max., ce f = v il oe = v ih byte t cycle = 10 mhz 18 ma word 20 byte t cycle = 5 mhz 8 word 10 i cc2 f flash v cc active current (program/erase) v cc f = v cc max., ce f = v il , oe = v ih 35ma i cc3 f *** flash v cc active current (read-while-program) ce = v il, oe = v ih byte 45 ma word 45 i cc4 f *** flash v cc active current (read-while-erase) ce = v il, oe = v ih byte 45 ma word 45 i cc5 f flash v cc active current (erase-suspend- program) ce = v il, oe = v ih 35ma i cc1 s sram v cc active current v cc s = v cc max., ce1 s = v il , ce2s = v ih t cycle =10 mhz 40 ma t cycle = 1 mhz 12 ma i cc2 s sram v cc active current ce1 s = 0.2 v, ce2s = v cc s C 0.2 v, we = v cc s C 0.2 v t cycle = 10 mhz 35 ma t cycle = 1 mhz 6 ma i sb1 f flash v cc standby current v cc f = v cc max., ce f = v cc f 0.3 v reset = v cc f 0.3 v 5 m a i sb2 f flash v cc standby current (reset ) v cc f = v cc max., reset = v ss 0.3 v 5 m a i sb1 s sram v cc standby current ce1 s = v ih or ce2s = v il 2ma i sb2 s ** sram v cc standby current ce1 s = v cc C0.2 v or ce2s = 0.2 v v cc s = 3.0 v 10% t a = 25c 1 2.5 m a t a = C20 to +85c 55 m a v cc s = 3.3 v 0.3 v t a = 25c 1.5 3 m a t a = C20 to +85c 60 m a v cc s = 3.0 v t a = 25c 1 2 m a t a = C20 to +40c 5 m a t a = C20 to +85c 50 m a v il input low level C0.3 0.6 v v ih input high level 2.2 v cc +0.3* v v ol output low voltage level i ol = 2.1 ma, v cc f = v cc s = v cc min. 0.4v v oh output high voltage level i oh = C500 m a, v cc f = v cc s = v cc min. v cc C 0.5 v v lko flash low v cc lock-out voltage 2.32.5v
12 MB84VD2002 -10 /mb84vd2003 -10 n ac characteristics ?ce timing ? timing diagram for alternating sram to flash ? read only operations characteristics (flash) note: test conditionsCoutput load: 1 ttl gate and 30 pf input rise and fall times: 5 ns input pulse levels: 0.0 v to 3.0 v timing measurement reference level input: 1.5 v output: 1.5 v parameter symbols description test setup -10 unit jedec standard t ccr ce recover time min. 0 ns parameter symbols description test setup -10 (note) unit jedec standard min. max. t avav t rc read cycle time 100 ns t avqv t acc address to output delay ce f = v il oe = v il 100ns t elqv t ce f chip enable to output delay oe = v il 100ns t glqv t oe output enable to output delay 40 ns t ehqz t df chip enable to output high-z 30 ns t ghqz t df output enable to output high-z 30 ns t axqx t oh output hold time from addresses, ce f or oe , whichever occurs first 0ns t ready reset pin low to read mode 20 s t elfl t elfh ce or byte switching low or high 5 ns ce f t ccr t ccr ce1 s ce2s t ccr t ccr
13 MB84VD2002 -10 /mb84vd2003 -10 ? read cycle (flash) we oe ce f t ce t oe dq addresses stable high-z output valid high-z t oeh t acc t rc reset t acc t oh dq t rc addresses stable high-z output valid t rh t df addresses addresses
14 MB84VD2002 -10 /mb84vd2003 -10 ? erase/program operations (flash) note : 1. this does not include the preprogramming time. 2. this timing is for sector protection operation. parameter symbols description -10 unit jedec standard min. typ. max. t avav t wc write cycle time 100 ns t avwl t as address setup time (we to addr.) 0 ns t avel t as address setup time (ce f to addr.) 0 ns t aso address setup time to oe low during toggle bit polling 15 ns t wlax t ah address hold time (we to addr.) 50 ns t elax t ah address hold time (ce f to addr.) 50 ns t aht address hold time from ce or oe high during toggle bit polling 0ns t dvwh t ds data setup time 50 ns t whdx t dh data hold time 0 ns t oeh output enable hold time read 0 ns toggle and data polling 10 ns t ceph ce high during toggle bit polling 20 ns t oeph oe high during toggle bit polling 20 ns t ghel t ghel read recover time before write (oe to ce f) 0 ns t ghwl t ghwl read recover time before write (oe to we )0ns t wlel t ws we setup time (ce f to we )0ns t elwl t cs cef setup time (we to ce f) 0 ns t ehwh t wh we hold time (ce f to we )0ns t wheh t ch cef hold time (we to ce f) 0 ns t wlwh t wp write pulse width 50 ns t eleh t cp ce f pulse width 50 ns t whwl t wph write pulse width high 30 ns t ehel t cph cef pulse width high 30 ns t whwh1 t whwh1 byte programming operation 8 s t whwh2 t whwh2 sector erase operation (note 1) 1 sec 15sec t vcs v cc f setup time 50 s t vlht voltage transition time (note 2) 4 s t vidr rise time to v id (note 2) 500 ns t rb recover time from ry/by 0ns t rp reset pulse width 500 ns t rh reset hold time before read 200 ns t eoe delay time from embedded output enable 100 ns t busy program/erase valid to ry/by delay 90 ns t flqz byte switching low to output high-z 30 ns t fhqv byte switching high to output active 30 ns
15 MB84VD2002 -10 /mb84vd2003 -10 ? write cycle (we control) (flash) t ch t wp t whwh1 t wc t ah ce f oe t rc dq t as t f oe t wph t ghwl t dh dq 7 pd a0h d out we 555h pa pa t oh data polling 3rd bus cycle t cs t co t ds d out addresses notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence 6. these waveforms are for the x16 mode. the addresses differ from x8 mode.
16 MB84VD2002 -10 /mb84vd2003 -10 ? write cycle (ce f control) (flash) notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence 6. these waveforms are for the x16 mode. the addresses differ from x8 mode. t cp t ds t whwh1 t wc t ah we oe dq t as t cph t dh dq 7 a0h d out ce f 555h pa pa data polling 3rd bus cycle t ws t wh t ghel pd addresses
17 MB84VD2002 -10 /mb84vd2003 -10 ? ac waveforms chip/sector erase operations (flash) addresses v cc ce f oe dq we 555h 2aah 555h 555h 2aah sa *1 t ds t ch t as t ah t cs t wph t dh t ghwl t vcs t wc t wp aah 55h 80h aah 55h 10h/ 30h for sector erase 30h notes: 1. sa is the sector address for sector erase. addresses = 555h forchip erase. 2. these waveforms are for the x16 mode. the addresses differ from x8 mode.
18 MB84VD2002 -10 /mb84vd2003 -10 ? ac waveforms for data polling during embedded algorithm operations (flash) ? ac waveforms for toggle bit during embedded algorithm operations (flash) t oeh t oe t whwh1 or 2 ce oe t eoe t busy we data t df t ch t ce high-z high-z dq 7 = valid data dq 0 to dq 6 valid data dq 7 * dq 7 dq 0 to dq 6 ry/by data dq 0 to dq 6 = output flag * : dq 7 = valid data (the device has completed the embedded operation). * : dq 6 stops toggling (the device has completed the embedded operation). t dh t oe t ce ce we oe dq 6 /dq 2 address ry/by data toggle data toggle data toggle data stop toggling output valid * t busy t oeh t oeh t oeph t aht t aht t aso t as t ceph
19 MB84VD2002 -10 /mb84vd2003 -10 ?ry/by timing diagram during write/erase operations (flash) ? reset , ry/by timing diagram (flash) ? timing diagram for word mode configuration (flash) the rising edge of the last we signal ce f ry/by we t busy entire programming or erase operations t rp reset t ready ry/by we t rb ce byte t elfh t fhqv a -1 data output (dq 0 to dq 7 ) dq 15 dq 15 /a -1 dq 0 to dq 14 (dq 0 to dq 14 ) data output
20 MB84VD2002 -10 /mb84vd2003 -10 ? timing diagram for byte mode configuration (flash) ?byte timing diagram for write operations (flash) ? temporary sector unprotection (flash) ce byte dq 15 /a -1 dq 0 to dq 14 t elfl dq 15 a -1 t flqz data output (dq 0 to dq 7 ) (dq 0 to dq 14 ) data output the falling edge of the last we signal t hold ce or we (t ah ) t set (t as ) input valid byte 3 v reset v cc ce we ry/by t vlht program or erase command sequence 3 v t vlht t vcs t vidr v id t vlht unprotection period
21 MB84VD2002 -10 /mb84vd2003 -10 ? back-to-back read/write timing diagram ce dq we address ba1 ba1 ba1 ba2 (555h) ba2 (pa) ba2 (pa) oe valid output valid output valid output status valid intput valid intput t rc t rc t rc t rc t wc t wc t aht t as t as t ah t acc t ce t oe t oeh t wp t ghwl t ds t df t dh t df t ceph read command command read read read (a0h) (pd)
22 MB84VD2002 -10 /mb84vd2003 -10 ? extended sector protection (flash) spax : sector address to be protected spay : next sector address to be protected time-out : time-out window = 150 m s (min) spay reset a 6 oe we ce data a 1 v cc a 0 add spax spax 60h 01h 40h 60h 60h time-out t vcs t vlht t vidr t oe
23 MB84VD2002 -10 /mb84vd2003 -10 ? read cycle (sram) ? read cycle (note 1) (sram) note: 1. we remains high for the read cycle. parameter symbol parameter description min. max. unit t rc read cycle time 100 ns t aa address access time 100 ns t co1 chip enable (ce1 s) access time 100 ns t co2 chip enable (ce2s) access time 100 ns t oe output enable access time 50 ns t coe chip enable (ce1 s low and ce2s high) to output active 5 ns t oee output enable low to output active 0 ns t od chip enable (ce1 s high or ce2s low) to output high-z 40 ns t odo output enable high to output high-z 40 ns t oh output data hold time 10 ns t rc t aa t oh t co1 t od t odo t oee t coe valid data out addresses ce1 s oe dq ce2s t coe t oe t co2 t od
24 MB84VD2002 -10 /mb84vd2003 -10 ? write cycle (sram) ? write cycle (note 4) (we control) (sram) parameter symbol parameter description min. max. unit t wc write cycle time 100 ns t wp write pulse width 60 ns t cw chip enable to end of write 80 ns t as address setup time 0 ns t wr write recovery time 0 ns t odw we low to output high-z 40 ns t oew we high to output active 0 ns t ds data setup time 40 ns t dh data hold time 0 ns t wc t as t wp t wr t cw t odw t oew t ds t dh valid data in addresses we ce1 s d out d in ce2s t cw notes: 2. if ce1 s goes low (or ce2s goes high) coincident with or after we goes low, the output will remain at high impedance. 3. if ce1 s goes high (or ce2s goes low) coincident with or before we goes high, the output will remain at high impedance. 4. if oe is high during the write cycle, the outputs will remain at high impedance. 5. because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied. note 2 note 5 note 3 note 5
25 MB84VD2002 -10 /mb84vd2003 -10 ? write cycle (note 4) (ce 1s control) (sram) t wc t as t wp t wr t cw t odw t coe t ds t dh valid data in addresses we ce1 s d out d in ce2s t cw notes: 2. if ce1 s goes low (or ce2s goes high) coincident with or after we goes low, the output will remain at high impedance. 3. if ce1 s goes high (or ce2s goes low) coincident with or before we goes high, the output will remain at high impedance. 4. if oe is high during the write cycle, the outputs will remain at high impedance. 5. because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied. note 5 note 5
26 MB84VD2002 -10 /mb84vd2003 -10 ? write cycle (note 4) (ce2s control) (sram) t wc t as t wp t wr t cw t odw t coe t ds t dh valid data in addresses we ce1 s d out d in ce2s notes: 2. if ce1 s goes low (or ce2s goes high) coincident with or after we goes low, the output will remain at high impedance. 3. if ce1 s goes high (or ce2s goes low) coincident with or before we goes high, the output will remain at high impedance. 4. if oe is high during the write cycle, the outputs will remain at high impedance. 5. because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied. note 5 note 5 t cw
27 MB84VD2002 -10 /mb84vd2003 -10 n erase and programming performance (flash) n data retention characteristics (sram) * : 5 m a (max.) at t a = C20c to +40c ?ce1 s controlled data retention mode (note 1) parameter limits unit comment min. typ. max. sector erase time 1 10 sec excludes programming time prior to erasure byte programming time 8 300 m s excludes system-level overhead word programming time 16 360 m s chip programming time 8.4 t.b.d sec excludes system-level overhead erase/program cycle 100,000 cycles parameter symbol parameter description min. typ. max. unit v dh data retention supply voltage 2.0 3.6 v i dds2 standby current v dh = 3.0 v 50* m a v dh = 3.6 v 60 m a t cdr chip deselect to data retention mode time 0 ns t r recovery time 5 ms v cc s 2.7 v v ih gnd data retention mode see note 2 t cdr ce1 s v ccs C0.2 v see note 2 t r
28 MB84VD2002 -10 /mb84vd2003 -10 ? ce2s cont r olled data retention mode (note 3) notes : 1 . in ce1 s controlled data retention mod e , input l e v el of ce2s should be fi x ed vccs to vccs-0.2v or vss to 0.2v du r ing data retention mod e . other input and input/output pins can be used bet w een -0.3v to vccs+0.3 v . 2 . when ce1 s is ope r ating at the v ih min. l e v el (2.2 v), the stand b y current is gi v en b y i sb1 s du r ing the t r ansition of v cc s from 3.6 to 2.2 v . 3 . in ce2s controlled data retention mod e , input and input/output pins can be used bet w een bet w een -0.3v to vccs+0.3 v . n pin ca p a ci t ance note : t est conditions t a = 25 c , f = 1.0 mhz n hand l ing of p a ck a g e please handle this pa c kage carefully since the sides of pa c kages are r ight angl e . n c a ution 1.)the high v oltage (vid) can not apply to address pins and control pins e xcept reset . there f or e , it can not use autoselect and sector protect function b y applying the high v oltage (vid) to specific pin s . 2.) f or the sector protection, since the high v oltage (vid) can be applied to the reset , it can be protected the sector useing "extended sector protect" command. parameter symbol parameter description test setup typ. max. unit c in input capacitance v in = 0 t.b.d t.b.d pf c out output capacitance v out = 0 t.b.d t.b.d pf c in2 control pin capacitance v in = 0 t.b.d t.b.d pf v cc s 2.7 v gnd data retention mode v ih v il ce2s t cdr t r 0.2 v
29 MB84VD2002 -10 /mb84vd2003 -10 n pac k ag e n package dimensions 48-pin plastic fbga (bga-48p-m06) c 1998 fujitsu limited mcm-m001-2-3 10.00?.15 0.30?.10 (.012?004) 1.40?.20 (.055?008) 5.00?.15 (.197?006) (.394?006) 0.40?.10 (.016?004) 1.00?.15 (.039?006) 7.00?.15(.276?006) 0.15(.006) 11.00?.15(.433?006) index 1st pin index dimension in mm (inches). 48-pin plastic bga (bga-48p-m06) note: the actual shape of coners may differ from the dimension.
30 MB84VD2002 -10 /mb84vd2003 -10 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: (044) 754-3763 fax: (044) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9805 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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