features www.advantech.com/products online download PCI-1755 bus-mastering dma data transfer with scatter gather technology 32/16/8-bit pattern i/o with start and stop trigger function, 2 modes handshaking i/o interrupt handling capability onboard active terminators for high speed and long distance transfer pattern match and change state detection interrupt function general-purpose 8-ch di/o ? ? ? ? ? 80 mb/s, 32-ch digital i/o pci card introduction the PCI-1755 supports pci-bus mastering dma for high-speed data transfer. by setting aside a block of memory in the pc, the PCI-1755 performs bus-mastering data transfers without cpu intervention, setting the cpu free to perform other more urgent tasks such as data analysis and graphic manipulation. the function allows users to run all i/o unctions simultaneously at full speed without losing data. specifcations channels 32 ttl compatible number of ports port a, port b, port c and port d (8 bits/port) i/o confguration 32di (pa ~ pd) (default); 32do (pa ~ pd); 16di (pa ~ pb) & 16do (pc ~ pd); 8di (pa) & 8do (pc) (programmable) onboard fifo 16 kb for di & 16 kb do channels transfer characteristics data transfer mode bus mastering dma with scatter-gather data transfer bus width 8/16/32 bits (programmable) max. transfer rate di: 80 m bytes/sec, 32-bit @ 20 mhz 120 m bytes/sec, 32-bit @ 40 mhz external pacer when data length is less than fifo size do: 80 mbytes/sec, 32-bit @ 20 mhz operation mode handshaking handshaking mode direction i/o samples no. finite transfer, continuous i/o asynchronous 8255 emulation synchronous burst handshaking clock source for burst handshaking internal: 30 mhz, 20 mhz, 15 mhz, 12 mhz, 10 mhz, timer#0 for di & timer#1 for do external: ext_clkin for di & ext_clkout for do normal mode input data acquisition at a predetermined rate by internal/external clock output waveform generation at a predetermined rate by internal/external clock clock source for di internal: 30 mhz, 20 mhz, 15 mhz, 12 mhz, 10 mhz, timer#0 external: ext_clkin clock source for do internal: 30 mhz, 20 mhz, 15 mhz, 12 mhz, 10 mhz, timer#1 external: ext_clkout start mode software command/trigger signal occurred from di_str or do_str/pattern di stop mode software command/trigger signal occurred from di_stp (for di) or do_str (for do)/pattern di/finite transfers chang detection (di only) monitor the selected input channel and capture data whenever there is a transition on one of the channels, and then issue a irq clock source for di internal: 30 mhz, 20 mhz, 15 mhz, 12 mhz, 10 mhz, timer#0 external: ext_clkin start mode software command/trigger signal occurred from di_stp/pattern di stop mode software command/trigger signal occurred from di_stp/ patterndi/finite transfers trigger capability di trigger signal di_str, di_stp do trigger signal do_str, do_stp low 0.8 v max. high 2.0 v min. trigger type rising or falling edge, or digital pattern (for di only) pulse width for edge triggers 10 ns min. pattern trigger detection capabilities detect pattern match or mismatch on user-selected data lines terminator onboard schottky diode termination messaging the messages can be generated when 1. a specified number of bytes have been transferred, 2. when a specified input pattern is matched, 3. when a measurement operation completes. input voltage low 0 v min.; 0.8 v max. high 2.0 v min.; 5 v max. input load terminator off: ttl compatible low +0.5 v @ 20 ma high +2.7 v @ 1 ma max. terminator on terminator resistor 110 ? termination voltage 2.9 v low +0.5 v @ 22.4 ma high +2.7 v @ 1 ma max. output voltage low 0.5 v max. high 2.7 v min. driving capacity low 0.5 v max @ +48 ma (sink) high 2.4 v min. @ -15 ma (source) hysteresis 500 mv power available at i/o connector +4.65 ~ +5.25 v dc @ 1a general-purposedi/ o di channels di0 ~ di7 (ttl compatible) do channels do0 ~ do7 (ttl compatible) interrupt source di0 ~ 7 and timer#2, pattern match and change detection, di fifo overflow and do fifo underflow, di_stp and do_stp pacer channels timer#0, timer#1 and timer#2 timer#0 timer pacer for digital input timer#1 timer pacer for digital output timer#2 interrupt source resolution 16-bit base clock 10 mhz general i/o connector type 100-pin scsi-ii female dimensions (l x h) 175 x 100 mm (6.9" x 3.9") power consumption typical terminator off: +5 v @ 1 a terminator on: +5 v @ 1 a max. terminator off: +5 v @ 1 a terminator on: +5 v @ 1 a temperature operating 0 ~ 60 c (32 ~ 140 f) (refer to iec 68-2-1, 2) storage -20 ~ 85 c (-4 ~ 185 f) relative humidity 5 ~ 95% rh non-condensing (refer to iec 68-2-3) cert. fcc, ce certified ordering information PCI-1755 ultra-speed 32-ch digital i/o card adam-39100 PCI-1755 wiring terminal for din-rail mounting pcl-101100-1 100-pin scsi-ii cable with male connectors on both ends and special shielding for noise reduction, 1 m ? ? ? ? ? ? ? ? ?
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