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k5q6432ycm - t010 revision 0.3 june. 2001 - 1 - document title multi-chip package memory 64m bit (8mx8) nand flash memory / 32m bit (2mx16) utram revision history the attached datasheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to your requests and questions about device. if you ha ve any questions, please contact the samsung branch office near you. revision no. 0.0 0.1 0.2 0.3 remark advanced information preliminary preliminary final history initial issue. changed device name k5q6420ycm-to70 -> K5Q6432YCM-T010 - improve operating current from 30ma to 25ma.. - release speed from 70ns to 100ns. - release standby current form 170 m a to 200 m a. - add power up timing diagram. - add ac characteristics for continuous write. - expand max operating temperature from 70 c to 85 c. - changed i ol / i oh from 1.0ma/-0.5ma to 0.1ma/-0.1ma. - release standby current from 200ua to 250ua - release deep power down current from 10ua to 20ua - release twc for continuous write operation from 100ns to 110ns - release tcw for continuous write operation from 90ns to 100ns - release taw for continuous write operation from 90ns to 100ns - release tbw for continuous write operation from 90ns to 100ns - release twp for continuous write operation from 90ns to 100ns - improve standby current from 250ua to 150ua draft date dec. 19th 2000 feb. 28th 2001 april. 6th 2001 june. 11th 2001 note : for more detailed features and specifications including faq, please refer to samsung?s web site. http://samsungelectronics.com/semiconductors/products/products_index.html
k5q6432ycm - t010 revision 0.3 june. 2001 - 2 - multi-chip package memory 64m bit (8mx8) nand flash memory / 32m bit (2mx16) utram the k5q6432ycm featuring single 3.0v power supply is a multi chip package memory which combines 64mbit nand flash and 32mbit unit transistor cmos ram. the 64mbit flash memory is organized as 8m x8 bit and the 32mbit utram is organized as 2m x16 bit. in 64mb nand flash a 528-byte page program can be typically achieved within 300us and an 8k-byte block erase can be typically achieved within 2ms. in serial read operation, a byte can be read by 50ns. the dq pins serve as the ports for address and data input/output as well as command inputs. even the write-intensive systems can take advantage of the flash s extended reliability of 100k program/ erase cycles by providing ecc(error correcting code) with real time mapping-out algorithm. these algorithms have been imple- mented in many mass storage applications and also the spare 16 bytes of a page combined with the other 512 bytes can be utilized by system-level ecc. the k5q6432ycm is suitable for use in data memory of mobile communication system to reduce not only mount area but also power consumption. this device is available in 69-ball tbga type. features power supply voltage : 2.7v to 3.3 v organization - flash : (8m + 256k)bit x 8bit - utram : 2m x 16 bit access time - flash : random access : 10us(max.), serial read : 50ns(min.) - utram : 100 ns power consumption (typical value) - flash read current : 10 ma(@20mhz) program/erase current : 10 ma standby current : 10 m a - utram operating current : 18 ma standby current : 120 m a flash automatic program and erase page program : (512 + 16)byte block erase : (8k + 256)byte flash fast write cycle time program time : 300us(typ.) block erase time : 2ms(typ.) flash endurance : 100,000 program/erase cycles minimum flash data retention : 10 years operating temperature : -25 c ~ 85 c package : 69 - ball tbga type - 8 x 13mm, 0.8 mm pitch general description samsung electronics co., ltd. reserves the right to change products and specifications without notice. ball configuration ball name description a 0 to a 20 address input balls (utram) dq 0 to dq 7 data input/output balls (common) dq 8 to dq 15 data input/output balls (utram) vccu power supply (utram) vcc f power supply (flash memory) vccq f output buffer power (flash memory) this input may be tied directly to v ccf . vss ground (common) ub upper byte enable (utram) lb lower byte enable (utram) wp write protection (flash memory) cle command latch enable(flash memory) ale address latch enable(flash memory) ce f chip enable (flash memory) cs u chip enable (utram low active) zz deep power down(utram high active) we write enable (common) oe / re output enable (common) r/ b ready/busy (flash memory) n.c no connection a 7 u b a 8 a 3 a 6 c e f l b z z a 1 9 a 2 a 5 a 1 8 a l e a 2 0 a 9 a 4 d q 6 w p o e / r e d q 9 d q 3 d q 4 d q 1 3 1 2 3 4 5 6 a b c d e f c l e w e v s s a 1 0 d q 1 a 0 a 1 a 1 7 a 1 1 a 1 2 a 1 5 a 1 3 n . c a 1 4 n . c a 1 6 r / b 7 8 v c c f d q 8 d q 2 d q 1 1 d q 5 h d q 1 4 c s u d q 0 d q 1 0 v c c q f v c c u d q 1 2 g d q 7 v s s n . c d q 1 5 n . c n . c n . c n . c n . c n . c n . c n . c n . c n . c n . c n . c i n d e x 9 1 0 k j ball description 69 ball tbga , 0.8mm pitch top view (ball down)
k5q6432ycm - t010 revision 0.3 june. 2001 - 3 - figure 1. functional block diagram ub cs u vccu zz lb 512bytes 16 bytes note : column address : starting address of the register. 00h command(read) : defines the starting address of the 1st half of the register. 01h command(read) : defines the starting address of the 2nd half of the register. * a 8 is set to "low" or "high" by the 00h or 01h command. * l must be set to "low" dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 3rd cycle a 17 a 18 a 19 a 20 a 21 a 22 *l *l 1st half page register (=256 bytes) 2nd half page register (=256 bytes) 16k pages (=1024 blocks) 512 bytes 8 bit 16 bytes 1 block =16 pages = (8k + 256) bytes dq 0 ~ dq 7 1 page = 528 bytes 1 block = 528 bytes x 16 pages = (8k + 256) bytes 1 device = 528 bytes x 16pages x 1024 blocks = 66 mbits column address row address (page address) page register figure 2. flash array organization r/ b wp cef ale address(a0 to a20) 64 m bit flash memory 32 m bit utram cle we oe / re vss vccf vss vccqf dq 0 to dq 15 dq 0 to dq 15 dq 0 to dq 7
k5q6432ycm - t010 revision 0.3 june. 2001 - 4 - nand flash product introduction the flash memory is a 69mbit(69,206,016 bit) memory organized as 16,384 rows(pages) by 528 columns. spare sixteen columns are located from column address of 512 to 527. a 528-byte data register is connected to memory cell arrays accommodating data transfer between the dq buffers and memory during page read and page program operations. the memory array is made up of 16 cells that are serially connected to form a nand structure. each of the 16 cells resides in a different page. a block consists o f the 16 pages formed by one nand structures, totaling 4,224 nand structures of 16 cells. the array organization is shown in figure 2. th e program and read operations are executed on a page basis, while the erase operation is executed on a block basis. the memory array consists of 1024 separately erasable 8k-byte blocks. it indicates that the bit by bit erase operation is prohibited on the flash memory. the flash memory has addresses multiplexed into 8 dq s. this scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design. command, address and data are all written throug h dq s by bringing we to low while ce is low. data is latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and address respectively, via the dq pins. all commands require one bus cycle except for block erase command which requires two cycles: one cycle for erase-setup and another for erase-execution after block address loading. the 8m byte physical space requires 23 addresses, thereby requiring three cycles for byte-level addressing: col - umn address, low row address and high row address, in that order. page read and page program need the same three address cycles following the required command input. in block erase operation, however, only the two row address cycles are used. device operations are selected by writing specific commands into the command register. table 1 defines the specific commands of the flash memory. table 1. command sets note : 1. the 00h command defines starting address of the 1st half of registers. the 01h command defines starting address of the 2nd half of registers. after data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half register(00h) on the next cycle. function 1st. cycle 2nd. cycle acceptable command during busy read 1 00h/01h (1) - read 2 50h - read id 90h - reset ffh - o page program 80h 10h block erase 60h d0h read status 70h - o
k5q6432ycm - t010 revision 0.3 june. 2001 - 5 - table 2. flash memory operations table note : 1. x can be v il or v ih. 2. wp should be biased to cmos high or cmos low for standby. cle ale ce we re wp mode h l l h x read mode command input l h l h x address input(3clock) h l l h h write mode command input l h l h h address input(3clock) l l l h h data input l l l h x sequential read & data output l l x h h x during read(busy) x x x x x h during program(busy) x x x x x h during erase(busy) x x (1) x x x l write protect x x h x x 0v/v cc (2) stand-by table 3. utram operations table 1. x means don t care.(must be low or high state) cs zz oe we lb ub dq 1~8 dq 9~1 mode power h h x 1) x 1) x 1) x 1) high-z high-z deselected standby x 1) l x 1) x 1) x 1) x 1) high-z high-z deselected deep power down l h x 1) x 1) h h high-z high-z deselected standby l h h h l x 1) high-z high-z output disabled active l h h h x 1) l high-z high-z output disabled active l h l h l h dout high-z lower byte read active l h l h h l high-z dout upper byte read active l h l h l l dout dout word read active l h x 1) l l h din high-z lower byte write active l h x 1) l h l high-z din upper byte write active l h x 1) l l l din din word write active
k5q6432ycm - t010 revision 0.3 june. 2001 - 6 - flash memory operation page read upon initial device power up, the device defaults to read1 mode. this operation is also initiated by writing 00h to the command reg- ister along with three address cycles. once the command is latched, it does not need to be written for the following page read o per- ation. two types of operations are available : random read, serial page read . the random read mode is enabled when the page address is changed. the 528 bytes of data within the selected page are trans- ferred to the data registers in less than 10 m s(tr). during read busy, the device can go into pseudo-standy mode by taking ce to v ih , which frees dq bus and allows the cpu to access other devices. the cpu can detect the completion of this data transfer(tr) by analyzing the output of r/ b pin. once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing re . high to low transitions of the re clock output the data stating from the selected column address up to the last column address. the way the read1 and read2 commands work is like a pointer set to either the main area or the spare area. the spare area of bytes 512 to 527 may be selectively accessed by writing the read2 command. addresses a 0 to a 3 set the starting address of the spare area while addresses a 4 to a 7 are ignored. the read1 command(00h/01h) is needed to move the pointer back to the main area. figures 3 and 4 show typical sequence and timings for each read operation. figure 3. read1 operation start add.(3cycle) 00h 01h a 0 ~ a 7 & a 9 ~ a 22 data output(sequential) (00h command) 1st half array 2nd half array data field spare field (01h command)* 1st half array 2nd half array data field spare field * after data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle. ce cle ale r/ b we dq 0 ~ 7 re t r
k5q6432ycm - t010 revision 0.3 june. 2001 - 7 - page program the device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive bytes up to 528, in a single page program cycle. the number of consecutive partial page programming operation within the same page without an intervening erase operation should not exceed 2 for main array and 3 for spare array. the addressing may be done in any random order in a block. a page program cycle consists of a serial data loading period in which up to 528 bytes of data m ay be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the approp ri- ate cell. serial data loading can be started from 2nd half array by moving pointer. about the pointer operation, please refer to the attached technical notes. the serial data loading period begins by inputting the serial data input command(80h), followed by the three cycle address input and then serial data loading. the bytes other than those to be programmed do not need to be loaded.the page program confirm com- mand(10h) initiates the programming process. writing 10h alone without previously entering the serial data will not initiate the pro- gramming process. the internal write state-control automatically executes the algorithms and timings necessary for program and verify, thereby freeing the cpu for other tasks. once the program process starts, the read status register command may be entered, with re and ce low, to read the status register. the cpu can detect the completion of a program cycle by monitoring the r/ b output, or the status bit(dq 6) of the status register. only the read status command and reset command are valid while pro- gramming is in progress. when the page program is complete, the write status bit(dq 0) may be checked(figure 5). the internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. the command register remains in read sta tus command mode until another valid command is written to the command register. figure 5. program & read status operation 80h a 0 ~ a 7 & a 9 ~ a 22 dq 0 ~ 7 r/ b address & data input dq 0 pass 528 byte data 10h 70h fail t prog figure 4. read2 operation 50h a 0 ~ a 3 & a 9 ~ a 22 data output(sequential) spare field ce cle ale r/ b we 1st half array 2nd half array data field spare field start add.(3cycle) (a 4 ~ a 7 : don't care) dq 0 ~ 7 re t r
k5q6432ycm - t010 revision 0.3 june. 2001 - 8 - figure 6. block erase operation block erase the erase operation is done on a block(8k byte) basis. block address loading is accomplished in two cycles initiated by an erase setup command(60h). only address a 13 to a 22 is valid while a 9 to a 12 is ignored. the erase confirm command(d0h) following the block address loading initiates the internal erasing process. this two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. at the rising edge of we after the erase confirm command input, the internal write state-control handles erase and erase-verify. when the erase operation is completed, the write status bit(dq 0) may be checked. figure 6 details the sequence. 60h block add. : a 9 ~ a 22 dq 0 ~ 7 r/ b address input(2cycle) dq 0 pass d0h 70h fail t bers read status the device contains a status register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. after writing 70h command to the command register, a read cycle output s the content of the status register to the dq pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/ b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 4 for specific status register definitions. the command register remains in status read mode until further commands are issued to it. therefore, if the status register is read during a random r ead cycle, a read command(00h or 50h) should be given before sequential page read cycle. dq # status definition dq 0 program / erase "0" : successful program / erase "1" : error in program / erase dq 1 reserved for future use "0" dq 2 "0" dq 3 "0" dq 4 "0" dq 5 "0" dq 6 device operation "0" : busy "1" : ready dq 7 write protect "0" : protected "1" : not protected table4. read status register definition
k5q6432ycm - t010 revision 0.3 june. 2001 - 9 - figure 7. read id operation read id the device contains a product identification mode, initiated by writing 90h to the command register, followed by an address inpu t of 00h. two read cycles sequentially output the manufacture code(ech), and the device code (e6h) respectively. the command regis- ter remains in read id mode until further commands are issued to it. figure 7 shows the operation sequence. figure 8. reset operation reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during rand om read, program or erase modes, the reset operation will abort these operation. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. internal address registers are cleared to "0"s and data regist ers to "1"s. the command register is cleared to wait for the next command, and the status register is cleared to value c0h when wp is high. refer to table 5 for device status after reset operation. if the device is already in reset state a new reset command will not be accepted to by the command register. the r/ b pin transitions to low for t rst after the reset command is written. reset command is not necessary for normal operation. refer to figure 8 below. after power-up after reset operation mode read 1 waiting for next command ffh dq 0 ~ 7 r/ b table5. device status t rst ce cle i/o 0 ~ 7 ale re we 90h 00h ech address. 1cycle maker code device code t cea t ar1 t rea e6h t whr
k5q6432ycm - t010 revision 0.3 june. 2001 - 10 - data protection the device is designed to offer protection from any involuntary program/erase during power-transitions. an internal voltage dete ctor disables all functions whenever vcc is below about 2.2v. wp pin provides hardware protection and is recommended to be kept at v il during power-up and power-down as shown in figure 9. the two step command sequence for program/erase provides additional software protection. figure 9. ac waveforms for power transition ready/ busy the device has a r/ b output that provides a hardware method of indicating the completion of a page program, erase and random read completion. the r/ b pin is normally high but transitions to low after program or erase command is written to the command reg- ister or random read is started after address loading. it returns to high when the internal controller has finished the operatio n. the pin is an open-drain driver thereby allowing two or more r/ b outputs to be or-tied. an appropriate pull-up resister is required for proper operation and the value may be calculated by the following equation. rp = v cc r/ b open drain output device gnd v cc (max.) - v ol (max.) i ol + ? i l = 2.9v 8ma + ? i l where i l is the sum of the input currents of all devices tied to the r/ b pin. v cc wp high ? ? ~ 2.2v ~ 2.2v rp
k5q6432ycm - t010 revision 0.3 june. 2001 - 11 - identifying invalid block(s) invalid block(s) invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by samsung. the i nfor- mation regarding the invalid block(s) is so called as the invalid block information. devices with invalid block(s) have the same quality level or as devices with all valid blocks and have the same ac and dc characteristics. an invalid block(s) does not affect the perfor- mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. the system d esign must be able to mask out the invalid block(s) via address mapping. the 1st block, which is placed on 00h block address, is full y guaranteed to be a valid block, therefore you don?t need to execute error correction for 1st block. all device locations are erased(ffh) except locations where the invalid block(s) information is written prior to shipping. the i nvalid block(s) status is defined by the 6th byte in the spare area. samsung makes sure that either the 1st or 2nd page of every invalid block has non-ffh data at the column address of 517. since the invalid block information is also erasable in most cases, it is i mpos- sible to recover the information once it has been erased. therefore, the system must be able to recognize the invalid block(s) b ased on the original invalid block information and create the invalid block table via the following suggested flow chart(figure 10). any intentional erasure of the original invalid block information is prohibited. * figure 10. flow chart to create invalid block table start set block address = 0 check "ffh" ? increment block address last block ? end no yes yes create (or update) no invalid block(s) table check "ffh" at the column address 517 of the 1st and 2nd page in the block nand flash technical notes
k5q6432ycm - t010 revision 0.3 june. 2001 - 12 - figure 11. flash program flow chart start dq 6 = 1 ? write 00h dq 0 = 0 ? no * if ecc is used, this verification write 80h write address write data write 10h read status registe write address wait for tr time verify data no program completed or r/b = 1 ? program error yes no yes * program error yes : if program operation results in an error, map out the block including the page in error and copy the target data to another block. * operation is not needed. error in write or read operation over its life time, the additional invalid blocks may develop with nand flash memory. refer to the qualification report for the actual data.the following possible failure modes should be considered to implement a highly reliable system. in the case of status read fail- ure after erase or program, block replacement should be done. because program status fail during a page program does not affect the data of the other pages in the same block, so you can execute block replacement on a page basis with a page sized buffer. t o improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be recla imed by ecc without any block replacement. the said additional block failure rate does not include those reclaimed blocks. failure mode detection and countermeasure sequence write erase failure status read after erase --> block replacement program failure status read after program --> block replacement read back ( verify after program) --> block replacement or ecc correction read single bit failure verify ecc -> ecc correction ecc : error correcting code --> hamming code etc. example) 1bit correction & 2bit detection nand flash technical notes
k5q6432ycm - t010 revision 0.3 june. 2001 - 13 - figure 12. flash erase flow chart start dq 6 = 1 ? dq 0 = 0 ? no * write 60h write block address write d0h read status register or r/b = 1 ? erase error yes no : if erase operation results in an error, map out the failing block and replace it with another block. * erase completed yes figure 13. flash read flow chart start verify ecc no write 00h write address read data ecc generation reclaim the error page read completed yes figure 14. flash block replacement buffer memory error occurs block a block b when the error happens with page "a" of block "a", try to write the data into another block "b" from an exter- nal buffer. then, prevent further system access to block "a" (by creating a "invalid block" table or other appropriate scheme.) page a nand flash technical notes
k5q6432ycm - t010 revision 0.3 june. 2001 - 14 - samsung nand flash has three address pointer commands as a substitute for the two most significant column addresses. ?00h? command sets the pointer to ?a? area(0~255byte), ?01h? command sets the pointer to ?b? area(256~511byte), and ?50h? command sets the pointer to ?c? area(512~527byte). with these commands, the starting column address can be set to any of a whole page(0~527byte). ?00h? or ?50h? is sustained until another address pointer command is inputted. ?01h? command, however, is effec - tive only for one operation. after any operation of read, program, erase, reset, power_up is executed once with ?01h? command, the address pointer returns to ?a? area by itself. to program data starting from ?a? or ?c? area, ?00h? or ?50h? command must be input- ted before ?80h? command is written. a complete read operation prior to ?80h? command is not necessary. to program data starting from ?b? area, ?01h? command must be inputted right before ?80h? command is written. 00h (1) command input sequence for programming ?a? area address / data input 80h 10h 00h 80h 10h address / data input the address pointer is set to ?a? area(0~255), and sustained 01h (2) command input sequence for programming ?b? area address / data input 80h 10h 01h 80h 10h address / data input ?b?, ?c? area can be programmed. it depends on how many data are inputted. ?01h? command must be rewritten before every program operation the address pointer is set to ?b? area(256~512), and will be reset to ?a? area after every program operation is executed. 50h (3) command input sequence for programming ?c? area address / data input 80h 10h 50h 80h 10h address / data input only ?c? area can be programmed. ?50h? command can be omitted. the address pointer is set to ?c? area(512~527), and sustained ?00h? command can be omitted. it depends on how many data are inputted. ?a?,?b?,?c? area can be programmed. pointer operation of nand flash table 6. destination of the pointer command pointer position area 00h 01h 50h 0 ~ 255 byte 256 ~ 511 byte 512 ~ 527 byte 1st half array(a) 2nd half array(b) spare array(c) "a" area 256 byte (00h plane) "b" area (01h plane) "c" area (50h plane) 256 byte 16 byte "a" "b" "c" internal page register pointer select commnad (00h, 01h, 50h) pointer figure 15. block diagram of pointer operation nand flash technical notes
k5q6432ycm - t010 revision 0.3 june. 2001 - 15 - nand flash technical notes ce we t wp t ch t cs (min. 10ns) start add.(3cycle) 80h data input ce cle ale we i/o 0 ~ 7 data input ce don?t-care ? ? 10h for an easier system interface, ce may be inactive during data-loading or sequential data-reading as shown below. the internal 528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. in addition , for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating ce during the data-loading and read- ing would provide significant saving in power consumption. start add.(3cycle) 00h ce cle ale we i/o 0 ~ 7 data output(sequential) ce don?t-care ? r/ b t r re t cea out t rea (max. 45ns) ce re i/o 0 ~ 7 figure 16. program operation with ce don?t-care. figure 17. read operation with ce don?t-care. system interface using ce don?t-care.
k5q6432ycm - t010 revision 0.3 june. 2001 - 16 - recommended operating conditions (voltage reference to gnd, t a =-25 to 70 c) parameter symbol min typ. max unit supply voltage v ccf, v ccu 2.7 3.0 3.3 v supply voltage v ccqf 2.7 3.0 3.3 v supply voltage v ss 0 0 0 v absolute maximum ratings note : 1. minimum dc voltage is -0.2v on input/output pins. during transitions, this level may undershoot to -2.0v for periods <30ns. maximum dc voltage on input/output pins is v ccq +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended peri ods may affect reliability. parameter symbol rating unit voltage on any pin relative to v ss v in, v out -0.2 to (vccf,vccu)+ 0.3 v v ccf, v ccu -0.2 to 3.6v v vccqf -0.2 to 3.6v c temperature under bias t bias -25 to + 85 storage temperature t stg -65 to + 150 c dc and operating characteristics (recommended operating conditions otherwise noted.) parameter symbol test conditions min max unit input leakage current i li v ccf, v ccu= v ccf max. , v ccu max. v ccqf= v ccqf max.,v in= v ccqf or gnd - 10 m a output leakage current i lo v ccf, v ccu= v ccf max. , v ccu max. v ccqf= v ccqf max.,v in= v ccqf or gnd - 10 m a input low voltage level, all inputs v il -0.4 0.4 v input high voltage level v ih vccqf-0.4 vccqf+0.4 output low voltage level v ol vccf=vccf min, vccu=vccu min i ol = 0.1ma - 0.4 output high voltage level v oh vccf=vccf min, vccu=vccu min. i oh = -0.1ma vccqf-0.3 -
k5q6432ycm - t010 revision 0.3 june. 2001 - 17 - dc and operating characteristics (continued) parameter symbol test conditions typ max unit flash active sequential read currnt i cc 1f trc=50ns, cef =v il , i out =0ma v ccf= v ccf max,v ccqf= v ccqf max 10 20 ma active program current i cc 2f v ccf= v ccf max,v ccqf= v ccqf max 10 20 ma active erase current i cc 3f v ccf= v ccf max,v ccqf= v ccqf max 10 20 ma stand_by current i sb 2f cef =vccqf, wp =0v/v ccqf 10 50 m a utram operating current i cc 1u cycle time=1 m s, 100% duty, i io =0ma, cs u 0.2v, zz 3 vcc u -0.2v, v in 0.2v or v in 3 v ccu -0.2v 2 5 ma i cc 2u cycle time=min, 100% duty, i io =0ma, cs u=v il , zz =v ih , v in =v il or v ih 18 25 ma stand_by current(cmos) i sb 2u cs u 3 vcc u -0.2v, zz 3 vcc u -0.2v, other inputs =0~vcc u 120 150 m a deep power down i sbd zz 0.2v, other input =0~vcc u 5 20 m a capacitance (t a = 25 c, v cc = 3.0v, f = 1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input/output capacitance c dq v il =0v - 20 pf input capacitance c in v in =0v - 18 pf valid block of flash memory(flash) note : 1. the flash memory may include invalid blocks when first shipped. additional invalid blocks may develop while being used. the number of valid blocks is presented with both cases of invalid blocks considered. invalid blocks are defined as blocks that contain one or more bad bits . do not try to access these invalid blocks for program and erase. refer to the attached technical notes for a appropriate management of invalid blocks. 2. the 1st block, which is placed on 00h block address, is guaranteed to be a valid block. parameter symbol min typ. max unit valid block number n vb 1014 1020 1024 blocks zz =v il cs =v ih zz =v il cs =v il , ub or/and lb =v il zz =v ih cs =v ih , zz =v ih standby mode state machines(utram) read operation(8 times) power on initial state (wait 200 m s) active standby mode deep power down mode standby mode characteristic(utram) power mode memory cell data standby current( m a) wait time( m s) standby valid 250 0 deep power down invaild 20 200 zz =v ih cs =v ih
k5q6432ycm - t010 revision 0.3 june. 2001 - 18 - input / output reference waveform 0v vccqf vccqf input & output test point 2 vccqf 2 device under test c l r2 r1 out vccq note : c l includes jig capacitance. test configuration c l (pf) r1(ohm) r2(ohm) 2.7v - 3.3v standard test 50 25k 25k test configuration
k5q6432ycm - t010 revision 0.3 june. 2001 - 19 - flash ac characteristics for operation (vcc=2.7~3.3v, t a =-25 to 85 c) note : 1. if reset command(ffh) is written at ready state, the device goes into busy for maximum 5us parameter symbol min max unit data transfer from cell to register t r - 10 m s ale to re delay( id read ) t ar1 20 - ns ale to re delay(read cycle) t ar2 50 - ns ce access time t cea - 45 ns ready to re low t rr 20 - ns re pulse width t rp 30 - ns we high to busy t wb - 100 ns read cycle time t rc 50 - ns re access time t rea - 35 ns re high to output hi-z t rhz 15 30 ns ce high to output hi-z t chz - 20 ns re high hold time t reh 15 - ns output hi-z to re low t ir 0 - ns we high to re low t whr 60 - ns device resetting time (read/program/erase) t rst - 5/10/500 (1) m s flash ac timing characteristics for command / address / data input (vcc=2.7~3.3v, t a =-25 to 85 c) parameter symbol min max unit cle set-up time t cls 0 - ns cle hold time t clh 10 - ns ce setup time t cs 0 - ns ce hold time t ch 10 - ns we pulse width t wp 25 - ns ale setup time t als 0 - ns ale hold time t alh 10 - ns data setup time t ds 20 - ns data hold time t dh 10 - ns write cycle time t wc 50 - ns we high hold time t wh 15 - ns flash program/erase characteristics (vcc=2.7~3.3v, t a =-25 to 85 c) parameter symbol min typ max unit program time t prog - 300 600 m s number of partial program cycles in the same page main array nop - - 2 cycles spare array - - 3 cycles block erase time t bers - 2 4 ms
k5q6432ycm - t010 revision 0.3 june. 2001 - 20 - * flash command latch cycle ce we cle ale dq 0 ~ 7 command t cls t cs t clh t ch t wp t als t alh t ds t dh * flash address latch cycle ce we cle ale dq 0 ~ 7 a 0 ~a 7 t cls t cs t wc t wp t als t ds t dh t alh t als t wh a 9 ~a 16 t wc t wp t ds t dh t alh t als t wh a 17 ~a 22 t wp t ds t dh t alh
k5q6432ycm - t010 revision 0.3 june. 2001 - 21 - * flash input data latch cycle ce cle we dq 0 ~ 7 din 0 din 1 din 511 ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp ? ? ? * flash s equential out cycle after read (cle=l, we =h, ale=l) re ce r/ b dq 0 ~ 7 dout dout dout t rc t rea t rr t rhz* t rea t reh t rea t chz* t rhz* ? ? ? ? notes : transition is measured 200mv from steady state voltage with load. this parameter is sampled and not 100% tested.
k5q6432ycm - t010 revision 0.3 june. 2001 - 22 - * flash status read cycle ce we cle re dq 0 ~ 7 70h status output t cls t clh t cs t wp t ch t ds t dh t rea t ir t rhz* t chz* t whr t cea t cls flash read1 operation (read one page) ce cle r/ b dq 0 ~ 7 we ale re busy 00h or 01h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 23 dout n dout n+1 dout n+2 dout n+3 column address page(row) address t wb t ar2 t r t rc t rhz t chz dout 527 t wc t rr ? ? ?
k5q6432ycm - t010 revision 0.3 june. 2001 - 23 - flash read2 operation (read one page) ce cle r/ b dq 0 ~ 7 we ale re 50h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 22 dout dout 527 m address a 0 ~ a 3 :valid address a 4 ~ a 7 :dont care 511+m dout 511+m+1 t ar2 t r t wb t rr ? ? ? selected row start address m 512 16 flash page program operation ce cle r/ b dq 0 ~ 7 we ale re 80h 70h dq 0 din n din din 10h 527 n+1 a 0 ~ a 7 a 17 ~ a 22 a 9 ~ a 16 sequential data input command column address page(row) address 1 up to 528 byte data sequential input program command read status command dq 0 =0 successful program dq 0 =1 error in program t prog t wb t wc t wc t wc ? ? ?
k5q6432ycm - t010 revision 0.3 june. 2001 - 24 - flash manufacture & device id read operation ce cle dq 0 ~ 7 we ale re 90h read id command maker code device code 00h ech e6h t rea address 1st cycle flash block erase operation (erase one block) ce cle r/ b dq 0 ~ 7 we ale re 60h a 17 ~ a 22 a 9 ~ a 16 auto block erase erase command read status command dq 0 =1 error in erase doh 70h dq 0 busy t wb t bers dq 0 =0 successful erase page(row) address t wc ? setup command
k5q6432ycm - t010 revision 0.3 june. 2001 - 25 - utram ac characteristics (vcc=2.7~3.3v, t a =-25 to 85 c) 1. the characteristics which is restricted for continuous wirte operation over 20 times, please refer to technical note. 2. the characteristics for continuous wirte operation. parameter list symbol speed bins units 100ns 1) 100ns 2) min max min max read read cycle time t rc 100 - 100 - ns address access time t aa - 100 - 100 ns chip select to output t co - 100 - 100 ns output enable to valid output t oe - 50 - 50 ns ub , lb access time t ba - 100 - 100 ns chip select to low-z output t lz 10 - 10 - ns ub , lb enable to low-z output t blz 10 - 10 - ns output enable to low-z output t olz 5 - 5 - ns chip disable to high-z output t hz 0 25 0 25 ns ub , lb disable to high-z output t bhz 0 25 0 25 ns output disable to high-z output t ohz 0 25 0 25 ns output hold from address change t oh 5 - 5 - ns write write cycle time t wc 100 - 110 - ns chip select to end of write t cw 80 - 100 - ns address set-up time t as 0 - 0 - ns address valid to end of write t aw 80 - 100 - ns ub , lb valid to end of write t bw 80 - 100 - ns write pulse width t wp 70 - 100 - ns write recovery time t wr 0 - 0 - ns write to output high-z t whz 0 30 0 30 ns data to write time overlap t dw 40 - 40 - ns data hold from write time t dh 0 - 0 - ns end write to output low-z t ow 5 - 5 - ns
k5q6432ycm - t010 revision 0.3 june. 2001 - 26 - address data out previous data valid data valid utram timing diagrams timing waveform of read cycle(1) (address controlled , cs = oe =v il , zz = we= v ih , ub or/and lb =v il ) timing waveform of read cycle(2) ( zz = we =v ih ) t aa t rc t oh (read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. 3. the minimum read cycle( t rc ) is determined later one of the t rc1 and t rc2. data valid high-z t rc1 t oh t aa t ba t oe t olz t blz t lz t ohz t bhz t hz t rc2 t co address cs ub , lb oe data out
k5q6432ycm - t010 revision 0.3 june. 2001 - 27 - t as(3) timing waveform of write cycle(1) ( we controlled , zz =v ih ) timing waveform of write cycle(2) ( cs controlled , zz =v ih ) address data undefined ub , lb we data in data out t wc t cw(2) t aw t bw t wp(1) t as(3) t dh t dw t whz t ow high-z high-z data valid cs address data valid ub , lb we data in data out high-z high-z t wc t cw(2) t aw t bw t wp(1) t dh t dw t wr(4) cs t wr(4)
k5q6432ycm - t010 revision 0.3 june. 2001 - 28 - timing waveform of write cycle(3) ( ub , lb controlled , zz =v ih ) (write cycle) 1. a wri t e occurs during the overlap(t wp ) of low cs and low we . a write begins when cs goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest transition when cs goes high and we goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr applied in case a write ends as cs or we going high. address data valid ub , lb we data in data out high-z high-z t wc t cw(2) t bw t wp(1) t dh t dw t wr(4) t aw t as(3) cs zz mode deep power down mode normal operation 1 m s 200 m s ~ ~ ~ ~ normal operation read operation twice or stay high during 300 m s suspend wake up timing waveform of deep power down mode cs
k5q6432ycm - t010 revision 0.3 june. 2001 - 29 - 200 m s ~ ~ read operation twice v cc zz cs timing waveform of power up(1) 200 m s ~ ~ v cc zz cs timing waveform of power up(2) (no dummy cycle) 300 m s ~ ~
k5q6432ycm - t010 revision 0.3 june. 2001 - 30 - technical note introduction u t ram is based on single-transistor dram cells. as with any other dram, the data in these cells must be periodically refreshed to prevent data loss. what makes the u t ram unique is that it offers a true sram style interface that hides all refresh operations from the memory controller. start with a dram technology the key to the u t ram is its high speed and low power. this speed comes from the use of many small blocks, often just 32kbits each, to create u t ram arrays. the small blocks have short word lines with little capacitance, eliminating a major source of operating current in conventional dram blocks. each independent macro-cell on a u t ram device consists of a number of these blocks. each chip has one or more macro. the address decoding logic is also fast. u t ram perform a complete read operation in every trc, but u t ram needs power up sequence like a dram. power up sequence and diagram 1. apply power. 2. maintain stable power for a minium 200 m s with cs =high. 3. issue read operation at least 2 times. u t ram usage and timing design achieves sram specific operations the u t ram design works just like an sram, with no wait states or other overhead for precharging or refreshing its inter- nal dram cells. samsung electronics(samsung) hides these operations with advanced design. precharging takes place during every access, overlapped with the end of the cycle and the decoding portion of the next cycle. hiding refresh is more difficult, every row in every block must be refreshed at least once during the refresh interval to prevent data loss. samsung provides a internal refresh controller for devices. when all accesses during a refresh interval are directed to one macro-cell, as can happen in signal processing applications, a more sophisticated approach is required to hide refresh. the pseudo sram, sometimes used on these applica- tions, which is required a memory controller that can hold off accesses when a refresh operation is needed. samsung unique qualitative advantage over these parts(in addition to quantitative improvements in access speed and power con- sumption) is that the u t ram never needs to hold off accesses, and indeed it has no hold off signal. the circuitry that gives samsung this advantage is fairly simple but has not previ- ously been disclosed. avoid timing following figures are show you a abonormal timing which is not supported on u t ram and their solution. at read operation, if your system have a timing which sustain invalid states over 4us at read mode like figure 1. there are some guide line for proper operation of u t ram. when your system have multiple invalid address signal shorter than trc on the timing which showed in figure 1, u t ram need a normal read timing during that cycle(figure 2) or toggle the cs to ?high? about ?trc?(figure 3). cs =v il , ub or/and lb =v il zz =v ih read operation(2 times) power on initial state (wait 200 m s) active cs =v ih cs we address less than trc over 4us cs we address trc over 4us figure 2. put on read operation every 4us figure 1.
k5q6432ycm - t010 revision 0.3 june. 2001 - 31 - figure 3. cs we address over 4us trc toggle cs to high every 4us cs we address twp over 4us twc write operation have similar restricted operation with read. if your system have a timing which sustain invalid states over 4us at write mode and system have continuous write signal with min. twc over 4us like figure 4. figure 5. figure 4. cs we address twp over 4us twc trc figure 6. cs we address twp over 4us twc trc you must put read timing on the cycle(figure 5) or toggle the cs to high about ?trc?(figure 6). toggle cs to high every 4us toggle we to high and stay high at least trc every 4us
k5q6432ycm - t010 revision 0.3 june. 2001 - 32 - package dimension 69-ball tape ball grid array package (measured in millimeters) top view bottom view side view 13.00 0.10 0.45 0.05 0.08max 0 . 3 5 0 . 0 5 1 . 1 0 0 . 1 0 #a1 8.00 0.10 1 3 . 0 0 0 . 1 0 1 4 2 7 6 5 3 8 a b c e g d f h 0.80 0.80 x9=7.20 a 0 . 8 0 x 9 = 7 . 2 0 1 3 . 0 0 0 . 1 0 3.60 69- ? 0.45 0.05 9 10 j k 3 . 6 0 0 . 8 0 b 8.00 0.10 0.20 m a b ? (datum a) (datum b)

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