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1. general description the 74ahc74; 74ahct74 is a high-speed si-gate cmos device and is pin compatible with low-power schottky ttl (lsttl). it is speci?ed in compliance with jedec standard no. 7a. the 74ahc74; 74ahct74 is a dual positive-edge triggered, d-type ?ip-?op with individual data (d) inputs, clock (cp) inputs, set ( sd) and reset ( rd) inputs; also complementary q and q outputs. the set and reset are asynchronous active low inputs and operate independently of the clock input. information on the data input is transferred to the q output on the low-to-high transition of the clock pulse. the d inputs must be stable one set-up time prior to the low-to-high clock transition for predictable operation. schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. 2. features n balanced propagation delays n inputs accepts voltages higher than v cc n input levels: u cmos levels: 74ahc74 only u ttl levels: 74ahct74 only n esd protection: u hbm eia/jesd22-a114-b exceeds 2000 v u mm eia/jesd22-a115-a exceeds 200 v n speci?ed from - 40 c to +85 c and from - 40 c to +125 c 3. quick reference data 74ahc74; 74ahct74 dual d-type ?ip-?op with set and reset; positive-edge trigger rev. 04 7 february 2005 product data sheet table 1: quick reference data gnd = 0 v; t amb = 25 c; t r = t f 3.0 ns. symbol parameter conditions min typ max unit type 74ahc74 t phl , t plh propagation delay ncp to nq, n qc l = 15 pf; v cc = 5 v - 3.7 - ns n sd, n rd to nq, n qc l = 15 pf; v cc = 5 v - 3.7 - ns f max maximum clock pulse frequency - 170 - mhz
9397 750 14504 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 04 7 february 2005 2 of 23 philips semiconductors 74ahc74; 74ahct74 dual d-type ?ip-?op with set and reset; positive-edge trigger [1] c pd is used to determine the dynamic power dissipation (p d in m w): p d =c pd v cc 2 f i n+ ? (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in v; n = number of inputs switching; ? (c l v cc 2 f o ) = sum of outputs. [2] the condition is v i = gnd to v cc . 4. ordering information c i input capacitance v i =v cc or gnd - 4.0 - pf c pd power dissipation capacitance c l = 50 pf; f i = 1 mhz [1] [2] -12-pf type 74ahct74 t phl , t plh propagation delay ncp to nq, n qc l = 15 pf; v cc = 5 v - 3.3 - ns n sd, n rd to nq, n qc l = 15 pf; v cc = 5 v - 3.7 - ns f max maximum clock pulse frequency - 160 - mhz c i input capacitance v i =v cc or gnd - 4.0 - pf c pd power dissipation capacitance c l = 50 pf; f i = 1 mhz [1] [2] -16-pf table 1: quick reference data continued gnd = 0 v; t amb = 25 c; t r = t f 3.0 ns. symbol parameter conditions min typ max unit table 2: ordering information type number package temperature range name description version 74ahc74d - 40 c to +125 c so14 plastic small outline package; 14 leads; body width 3.9 mm sot108-1 74ahc74pw - 40 c to +125 c tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 74AHC74BQ - 40 c to +125 c dhvqfn14 plastic dual in-line compatible thermal enhanced very thin quad ?at package; no leads; 14 terminals; body 2.5 3 0.85 mm sot762-1 74ahct74d - 40 c to +125 c so14 plastic small outline package; 14 leads; body width 3.9 mm sot108-1 74ahct74pw - 40 c to +125 c tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 74ahct74bq - 40 c to +125 c dhvqfn14 plastic dual in-line compatible thermal enhanced very thin quad ?at package; no leads; 14 terminals; body 2.5 3 0.85 mm sot762-1
9397 750 14504 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 04 7 february 2005 3 of 23 philips semiconductors 74ahc74; 74ahct74 dual d-type ?ip-?op with set and reset; positive-edge trigger 5. functional diagram fig 1. functional diagram fig 2. logic symbol fig 3. iec logic symbol mna418 rd ff sd 410 q 1q 2q 1q 2q 5 9 2 12 3 11 6 8 q 1sd cp 2cp 1cp 2d 1d d 2sd 113 1rd 2rd rd ff sd 4 q 1q 1q 5 2 3 6 q 1sd cp 1cp 1d d 1 1rd mna420 rd ff sd 10 q 2q 2q 9 12 11 8 q 2sd cp 2cp 2d d 13 2rd mna419 6 3 2 c1 4 s 1d 1 r 5 8 11 12 c1 10 s 1d 13 r 9
9397 750 14504 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 04 7 february 2005 4 of 23 philips semiconductors 74ahc74; 74ahct74 dual d-type ?ip-?op with set and reset; positive-edge trigger 6. pinning information 6.1 pinning 6.2 pin description fig 4. logic diagram (one ?ip-?op) mna421 sd cp rd d c c q c c c c c c q c c (1) the die substrate is attached to this pad using conductive die attach material. it can not be used as supply pin or input fig 5. pin con?guration so14 and tssop14 fig 6. pin con?guration dhvqfn14 74 1rd v cc 1d 2rd 1cp 2d 1sd 2cp 1q 2sd 1q 2q gnd 2q 001aac449 1 2 3 4 5 6 7 8 10 9 12 11 14 13 001aac450 74 transparent top view 1q 2q 1q 2sd 1sd 2cp 1cp 2d 1d 2rd gnd 2q 1rd v dd 6 9 gnd (1) 5 10 4 11 3 12 2 13 7 8 1 14 terminal 1 index area table 3: pin description symbol pin description 1 rd 1 asynchronous reset-direct input (active low) 1d 2 data input 1cp 3 clock input (low-to-high, edge-triggered)
9397 750 14504 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 04 7 february 2005 5 of 23 philips semiconductors 74ahc74; 74ahct74 dual d-type ?ip-?op with set and reset; positive-edge trigger 7. functional description 7.1 function table [1] h = high voltage level; l = low voltage level; - = low-to-high transition; q n+1 = state after the next low-to-high cp transition; x = dont care. 8. limiting values 1 sd 4 asynchronous set-direct input (active low) 1q 5 true ?ip-?op output 1 q 6 complement ?ip-?op output gnd 7 ground (0 v) 2 q 6 complement ?ip-?op output 2q 9 true ?ip-?op output 2 sd 10 asynchronous set-direct input (active low) 2cp 11 clock input (low-to-high, edge-triggered) 2d 12 data input 2 rd 13 asynchronous reset-direct input (active low) v cc 14 supply voltage table 3: pin description continued symbol pin description table 4: function table [1] input output n sd n rd ncp nd nq n q nq n+1 n q n+1 lhxxhllh hl xxl hhl llxxhh- - hh - l- - lh hh - h- - hl table 5: limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage - 0.5 +7.0 v v i input voltage - 0.5 +7.0 v i ik input diode current v i < - 0.5 v [1] - - 20 ma i ok output diode current v o < - 0.5 v or v o >v cc + 0.5 v [1] - 20 ma i o output source or sink current v o = - 0.5 v to v cc + 0.5 v - 25 ma
9397 750 14504 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 04 7 february 2005 6 of 23 philips semiconductors 74ahc74; 74ahct74 dual d-type ?ip-?op with set and reset; positive-edge trigger [1] the input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] for so14 packages: above 70 c the value of p tot derates linearly with 8 mw/k. for tssop14 packages: above 60 c the value of p tot derates linearly with 5.5 mw/k. for dhvqfn14 packages: above 60 c the value of p tot derates linearly with 4.5 mw/k. 9. recommended operating conditions 10. static characteristics i cc , i gnd v cc or gnd current - 75 ma t stg storage temperature - 65 +150 c p tot total power dissipation t amb = - 40 c to +125 c [2] - 500 mw table 5: limiting values continued in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit table 6: recommended operating conditions symbol parameter conditions min typ max unit type 74ahc74 v cc supply voltage 2.0 5.0 5.5 v v i input voltage 0 - 5.5 v v o output voltage 0 - v cc v t amb ambient temperature - 40 +25 +125 c t r , t f input rise and fall times v cc = 3.3 v 0.3 v - - 100 ns/v v cc = 5 v 0.5 v - - 20 ns/v type 74ahct74 v cc supply voltage 4.5 5.0 5.5 v v i input voltage 0 - 5.5 v v o output voltage 0 - v cc v t amb ambient temperature - 40 +25 +125 c t r , t f input rise and fall times v cc = 3.3 v 0.3 v - - 20 ns/v table 7: static characteristics type 74ahc74 at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit t amb = 25 c v ih high-level input voltage v cc = 2.0 v 1.5 - - v v cc = 3.0 v 2.1 - - v v cc = 5.5 v 3.85 - - v v il low-level input voltage v cc = 2.0 v - - 0.5 v v cc = 3.0 v - - 0.9 v v cc = 5.5 v - - 1.65 v
9397 750 14504 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 04 7 february 2005 7 of 23 philips semiconductors 74ahc74; 74ahct74 dual d-type ?ip-?op with set and reset; positive-edge trigger v oh high-level output voltage v i = v ih or v il i o = - 50 m a; v cc = 2.0 v 1.9 2.0 - v i o = - 50 m a; v cc = 3.0 v 2.9 3.0 - v i o = - 50 m a; v cc = 4.5 v 4.4 4.5 - v i o = - 4.0 ma; v cc = 3.0 v 2.58 - - v i o = - 8.0 ma; v cc = 4.5 v 3.94 - - v v ol low-level output voltage v i = v ih or v il i o = 50 m a; v cc = 2.0 v - 0 0.1 v i o = 50 m a; v cc = 3.0 v - 0 0.1 v i o = 50 m a; v cc = 4.5 v - 0 0.1 v i o = 4 ma; v cc = 3.0 v - - 0.36 v i o = 8 ma; v cc = 4.5 v - - 0.36 v i li input leakage current v i = v cc or gnd; v cc = 5.5 v - - 0.1 m a i oz 3-state output off-state current v i = v ih or v il ; v o = v cc or gnd; v cc = 5.5 v -- 0.25 m a i cc quiescent supply current v i = v cc or gnd; i o = 0 a; v cc = 5.5 v - - 2.0 m a c i input capacitance v i =v cc or gnd - 3 10 pf t amb = - 40 c to +85 c v ih high-level input voltage v cc = 2.0 v 1.5 - - v v cc = 3.0 v 2.1 - - v v cc = 5.5 v 3.85 - - v v il low-level input voltage v cc = 2.0 v - - 0.5 v v cc = 3.0 v - - 0.9 v v cc = 5.5 v - - 1.65 v v oh high-level output voltage v i = v ih or v il i o = - 50 m a; v cc = 2.0 v 1.9 - - v i o = - 50 m a; v cc = 3.0 v 2.9 - - v i o = - 50 m a; v cc = 4.5 v 4.4 - - v i o = - 4.0 ma; v cc = 3.0 v 2.48 - - v i o = - 8.0 ma; v cc = 4.5 v 3.8 - - v v ol low-level output voltage v i = v ih or v il i o = 50 m a; v cc = 2.0 v - - 0.1 v i o = 50 m a; v cc = 3.0 v - - 0.1 v i o = 50 m a; v cc = 4.5 v - - 0.1 v i o = 4 ma; v cc = 3.0 v - - 0.44 v i o = 8 ma; v cc = 4.5 v - - 0.44 v i li input leakage current v i = v cc or gnd; v cc = 5.5 v - - 1.0 m a i oz 3-state output off-state current v i = v ih or v il ; v o = v cc or gnd; v cc = 5.5 v -- 2.5 m a table 7: static characteristics type 74ahc74 continued at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit
9397 750 14504 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 04 7 february 2005 8 of 23 philips semiconductors 74ahc74; 74ahct74 dual d-type ?ip-?op with set and reset; positive-edge trigger i cc quiescent supply current v i = v cc or gnd; i o = 0 a; v cc = 5.5 v --20 m a c i input capacitance - - 10 pf t amb = - 40 c to +125 c v ih high-level input voltage v cc = 2.0 v 1.5 - - v v cc = 3.0 v 2.1 - - v v cc = 5.5 v 3.85 - - v v il low-level input voltage v cc = 2.0 v - - 0.5 v v cc = 3.0 v - - 0.9 v v cc = 5.5 v - - 1.65 v v oh high-level output voltage v i = v ih or v il i o = - 50 m a; v cc = 2.0 v 1.9 - - v i o = - 50 m a; v cc = 3.0 v 2.9 - - v i o = - 50 m a; v cc = 4.5 v 4.4 - - v i o = - 4.0 ma; v cc = 3.0 v 2.40 - - v i o = - 8.0 ma; v cc = 4.5 v 3.70 - - v v ol low-level output voltage v i = v ih or v il i o = 50 m a; v cc = 2.0 v - - 0.1 v i o = 50 m a; v cc = 3.0 v - - 0.1 v i o = 50 m a; v cc = 4.5 v - - 0.1 v i o = 4 ma; v cc = 3.0 v - - 0.55 v i o = 8 ma; v cc = 4.5 v - - 0.55 v i li input leakage current v i = v cc or gnd; v cc = 5.5 v - - 2.0 m a i oz 3-state output off-state current v i = v ih or v il ; v o = v cc or gnd; v cc = 5.5 v -- 10.0 m a i cc quiescent supply current v i = v cc or gnd; i o = 0 a; v cc = 5.5 v --40 m a c i input capacitance - - 10 pf table 7: static characteristics type 74ahc74 continued at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit table 8: static characteristics type 74ahct74 at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit t amb = 25 c v ih high-level input voltage v cc = 4.5 v to 5.5 v 2.0 - - v v il low-level input voltage v cc = 4.5 v to 5.5 v - - 0.8 v v oh high-level output voltage v i = v ih or v il i o = - 50 m a; v cc = 4.5 v 4.4 4.5 - v i o = - 8.0 ma; v cc = 4.5 v 3.94 - - v v ol low-level output voltage v i = v ih or v il i o = 50 m a; v cc = 4.5 v - 0 0.1 v i o = 8 ma; v cc = 4.5 v - - 0.36 v
9397 750 14504 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 04 7 february 2005 9 of 23 philips semiconductors 74ahc74; 74ahct74 dual d-type ?ip-?op with set and reset; positive-edge trigger i li input leakage current v i = v ih or v il ; v cc = 5.5 v - - 0.1 m a i oz 3-state output off-state current v i =v ih or v il ;v o =v cc or gnd per input pin; other inputs at v cc or gnd; i o = 0 a; v cc = 5.5 v -- 0.25 m a i cc quiescent supply current v i = v cc or gnd; i o = 0 a; v cc = 5.5 v - - 2.0 m a d i cc additional quiescent supply current per input pin v i =v cc - 2.1 v; other inputs at v cc or gnd; i o = 0 a; v cc = 4.5 v to 5.5 v - - 1.35 ma c i input capacitance - 3 10 pf t amb = - 40 c to +85 c v ih high-level input voltage v cc = 4.5 v to 5.5 v 2.0 - - v v il low-level input voltage v cc = 4.5 v to 5.5 v - - 0.8 v v oh high-level output voltage v i = v ih or v il i o = - 50 m a; v cc = 4.5 v 4.4 - - v i o = - 8.0 ma; v cc = 4.5 v 3.8 - - v v ol low-level output voltage v i = v ih or v il i o = 50 m a; v cc = 4.5 v - - 0.1 v i o = 8 ma; v cc = 4.5 v - - 0.44 v i li input leakage current v i = v ih or v il ; v cc = 5.5 v - - 1.0 m a i oz 3-state output off-state current v i =v ih or v il ;v o =v cc or gnd per input pin; other inputs at v cc or gnd; i o = 0 a; v cc = 5.5 v -- 2.5 m a i cc quiescent supply current v i = v cc or gnd; i o = 0 a; v cc = 5.5 v --20 m a d i cc additional quiescent supply current per input pin v i =v cc - 2.1 v; other inputs at v cc or gnd; i o = 0 a; v cc = 4.5 v to 5.5 v - - 1.5 ma c i input capacitance - - 10 pf c pd power dissipation capacitance c l = 50 pf; f i = 1 mhz [2] [3] -16-pf t amb = - 40 c to +125 c v ih high-level input voltage v cc = 4.5 v to 5.5 v 2.0 - - v v il low-level input voltage v cc = 4.5 v to 5.5 v - - 0.8 v v oh high-level output voltage v i = v ih or v il i o = - 50 m a; v cc = 4.5 v 4.4 - - v i o = - 8.0 ma; v cc = 4.5 v 3.70 - - v v ol low-level output voltage v i = v ih or v il i o = 50 m a; v cc = 4.5 v - - 0.1 v i o = 8 ma; v cc = 4.5 v - - 0.55 v i li input leakage current v i = v ih or v il ; v cc = 5.5 v - - 2.0 m a i oz 3-state output off-state current v i =v ih or v il ;v o =v cc or gnd per input pin; other inputs at v cc or gnd; i o = 0 a; v cc = 5.5 v -- 10.0 m a table 8: static characteristics type 74ahct74 continued at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit
9397 750 14504 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 04 7 february 2005 10 of 23 philips semiconductors 74ahc74; 74ahct74 dual d-type ?ip-?op with set and reset; positive-edge trigger 11. dynamic characteristics i cc quiescent supply current v i = v cc or gnd; i o = 0 a; v cc = 5.5 v --40 m a d i cc additional quiescent supply current per input pin v i =v cc - 2.1 v; other inputs at v cc or gnd; i o = 0 a; v cc = 4.5 v to 5.5 v - - 1.5 ma c i input capacitance - - 10 pf table 8: static characteristics type 74ahct74 continued at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit table 9: dynamic characteristics type 74ahc74 gnd = 0 v; t r = t f 3.0 ns; see figure 9 . symbol parameter test conditions min typ max unit t amb = 25 c [1] t phl , t plh propagation delay ncp to nq, n qv cc = 3.0 v to 3.6 v; see figure 7 c l = 15 pf - 5.2 11.9 ns c l = 50 pf - 7.4 15.4 ns v cc = 4.5 v to 5.5 v; see figure 7 c l = 15 pf - 3.7 7.3 ns c l = 50 pf - 5.2 9.3 ns n sd, n rd to nq, n qv cc = 3.0 v to 3.6 v; see figure 8 c l = 15 pf - 5.4 12.3 ns c l = 50 pf - 7.7 15.8 ns v cc = 4.5 v to 5.5 v; see figure 8 c l = 15 pf - 3.7 7.7 ns c l = 50 pf - 5.3 9.7 ns f max maximum clock pulse frequency v cc = 3.0 v to 3.6 v; see figure 7 c l = 15 pf 80 125 - mhz c l =50pf 50 75 - mhz v cc = 4.5 v to 5.5 v; see figure 7 c l = 15 pf 130 170 - mhz c l = 50 pf 90 115 - mhz t w pulse width clock pulse high or low c l = 50 pf; see figure 7 v cc = 3.0 v to 3.6 v 6.0 - - ns v cc = 4.5 v to 5.5 v 5.0 - - ns set or reset pulse low c l = 50 pf; see figure 8 v cc = 3.0 v to 3.6 v 6.0 - - ns v cc = 4.5 v to 5.5 v 5.0 - - ns
9397 750 14504 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 04 7 february 2005 11 of 23 philips semiconductors 74ahc74; 74ahct74 dual d-type ?ip-?op with set and reset; positive-edge trigger t rem removal time set or reset c l = 50 pf; see figure 8 v cc = 3.0 v to 3.6 v 5.0 - - ns v cc = 4.5 v to 5.5 v 3.0 - - ns t su set-up time nd to ncp c l = 50 pf; see figure 7 v cc = 3.0 v to 3.6 v 6.0 - - ns v cc = 4.5 v to 5.5 v 5.0 - - ns t h hold time nd to ncp c l = 50 pf; see figure 7 v cc = 3.0 v to 3.6 v 0.5 - - ns v cc = 4.5 v to 5.5 v 0.5 - - ns c pd power dissipation capacitance c l = 50 pf; f i = 1 mhz [2] [3] -12-pf t amb = - 40 c to +85 c t phl , t plh propagation delay ncp to nq, n qv cc = 3.0 v to 3.6 v; see figure 7 c l = 15 pf 1.0 - 14.0 ns c l = 50 pf 1.0 - 17.5 ns v cc = 4.5 v to 5.5 v; see figure 7 c l = 15 pf 1.0 - 8.5 ns c l = 50 pf 1.0 - 10.5 ns n sd, n rd to nq, n qv cc = 3.0 v to 3.6 v; see figure 8 c l = 15 pf 1.0 - 14.5 ns c l = 50 pf 1.0 - 18.0 ns v cc = 4.5 v to 5.5 v; see figure 8 c l = 15 pf 1.0 - 9.0 ns c l = 50 pf 1.0 - 11.0 ns f max maximum clock pulse frequency v cc = 3.0 v to 3.6 v; see figure 7 c l =15pf 45 - - mhz c l =50pf 70 - - mhz v cc = 4.5 v to 5.5 v; see figure 7 c l = 15 pf 110 - - mhz c l =50pf 75 - - mhz t w pulse width clock pulse high or low c l = 50 pf; see figure 7 v cc = 3.0 v to 3.6 v 7.0 - - ns v cc = 4.5 v to 5.5 v 5.0 - - ns set or reset pulse low c l = 50 pf; see figure 8 v cc = 3.0 v to 3.6 v 7.0 - - ns v cc = 4.5 v to 5.5 v 5.0 - - ns table 9: dynamic characteristics type 74ahc74 continued gnd = 0 v; t r = t f 3.0 ns; see figure 9 . symbol parameter test conditions min typ max unit
9397 750 14504 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 04 7 february 2005 12 of 23 philips semiconductors 74ahc74; 74ahct74 dual d-type ?ip-?op with set and reset; positive-edge trigger t rem removal time set or reset c l = 50 pf; see figure 8 v cc = 3.0 v to 3.6 v 5.0 - - ns v cc = 4.5 v to 5.5 v 3.0 - - ns t su set-up time nd to ncp c l = 50 pf; see figure 7 v cc = 3.0 v to 3.6 v 7.0 - - ns v cc = 4.5 v to 5.5 v 5.0 - - ns t h hold time nd to ncp c l = 50 pf; see figure 7 v cc = 3.0 v to 3.6 v 0.5 - - ns v cc = 4.5 v to 5.5 v 0.5 - - ns t amb = - 40 c to +125 c t phl , t plh propagation delay ncp to nq, n qv cc = 3.0 v to 3.6 v; see figure 7 c l = 15 pf 1.0 - 15.0 ns c l = 50 pf 1.0 - 19.5 ns v cc = 4.5 v to 5.5 v; see figure 7 c l = 15 pf 1.0 - 9.5 ns c l = 50 pf 1.0 - 12.0 ns n sd, n rd to nq, n qv cc = 3.0 v to 3.6 v; see figure 8 c l = 15 pf 1.0 - 15.5 ns c l = 50 pf 1.0 - 20.0 ns v cc = 4.5 v to 5.5 v; see figure 8 c l = 15 pf 1.0 - 10.0 ns c l = 50 pf 1.0 - 12.5 ns f max maximum clock pulse frequency v cc = 3.0 v to 3.6 v; see figure 7 c l =15pf 45 - - mhz c l =50pf 70 - - mhz v cc = 4.5 v to 5.5 v; see figure 7 c l = 15 pf 110 - - mhz c l =50pf 75 - - mhz t w pulse width clock pulse high or low c l = 50 pf; see figure 7 v cc = 3.0 v to 3.6 v 7.0 - - ns v cc = 4.5 v to 5.5 v 5.0 - - ns set or reset pulse low c l = 50 pf; see figure 8 v cc = 3.0 v to 3.6 v 7.0 - - ns v cc = 4.5 v to 5.5 v 5.0 - - ns t rem removal time set or reset c l = 50 pf; see figure 8 v cc = 3.0 v to 3.6 v 5.0 - - ns v cc = 4.5 v to 5.5 v 3.0 - - ns table 9: dynamic characteristics type 74ahc74 continued gnd = 0 v; t r = t f 3.0 ns; see figure 9 . symbol parameter test conditions min typ max unit
9397 750 14504 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 04 7 february 2005 13 of 23 philips semiconductors 74ahc74; 74ahct74 dual d-type ?ip-?op with set and reset; positive-edge trigger [1] typical values are measured at nominal v cc . [2] c pd is used to determine the dynamic power dissipation (p d in m w): p d =c pd v cc 2 f i n+ ? (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in v; n = number of inputs switching; ? (c l v cc 2 f o ) = sum of outputs. [3] the condition is v i = gnd to v cc . t su set-up time nd to ncp c l = 50 pf; see figure 7 v cc = 3.0 v to 3.6 v 7.0 - - ns v cc = 4.5 v to 5.5 v 5.0 - - ns t h hold time nd to ncp c l = 50 pf; see figure 7 v cc = 3.0 v to 3.6 v 0.5 - - ns v cc = 4.5 v to 5.5 v 0.5 - - ns table 9: dynamic characteristics type 74ahc74 continued gnd = 0 v; t r = t f 3.0 ns; see figure 9 . symbol parameter test conditions min typ max unit table 10: dynamic characteristics type 74ahct74 gnd = 0 v; t r = t f 3.0 ns; v cc = 4.5 v to 5.5 v; see figure 9 symbol parameter test conditions min typ max unit t amb = 25 c [1] t phl , t plh propagation delay ncp to nq, n q see figure 7 c l = 15 pf - 3.3 7.8 ns c l = 50 pf - 4.8 8.8 ns n sd, n rd to nq, n q see figure 8 c l = 15 pf - 3.7 10.4 ns c l = 50 pf - 5.3 11.4 ns f max maximum clock pulse frequency see figure 7 c l = 15 pf 100 160 - mhz c l = 50 pf 80 140 - mhz t w pulse width clock pulse high or low c l = 50 pf; see figure 7 5.0 - - ns set or reset pulse low c l = 50 pf; see figure 7 5.0 - - ns t rem removal time set or reset c l = 50 pf; see figure 8 3.5 - - ns t su set-up time nd to ncp c l = 50 pf; see figure 7 5.0 - - ns t h hold time nd to ncp see figure 7 0--ns c pd power dissipation capacitance c l = 50 pf; f i = 1 mhz [2] [3] -16-pf
9397 750 14504 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 04 7 february 2005 14 of 23 philips semiconductors 74ahc74; 74ahct74 dual d-type ?ip-?op with set and reset; positive-edge trigger t amb = - 40 c to +85 c t phl , t plh propagation delay ncp to nq, n q see figure 7 c l = 15 pf 1.0 - 9.0 ns c l = 50 pf 1.0 - 10.0 ns n sd, n rd to nq, n q see figure 8 c l = 15 pf 1.0 - 12.0 ns c l = 50 pf 1.0 - 13.0 ns f max maximum clock pulse frequency see figure 7 c l =15pf 80 - - mhz c l =50pf 65 - - mhz t w pulse width clock pulse high or low c l = 50 pf; see figure 7 5.0 - - ns set or reset pulse low c l = 50 pf; see figure 7 5.0 - - ns t rem removal time set or reset c l = 50 pf; see figure 8 3.5 - - ns t su set-up time nd to ncp c l = 50 pf; see figure 7 5.0 - - ns t h hold time nd to ncp see figure 7 0--ns t amb = - 40 c to +125 c t phl , t plh propagation delay ncp to nq, n q see figure 7 c l = 15 pf 1.0 - 10.0 ns c l = 50 pf 1.0 - 11.0 ns n sd, n rd to nq, n q see figure 8 c l = 15 pf 1.0 - 13.0 ns c l = 50 pf 1.0 - 14.5 ns f max maximum clock pulse frequency see figure 7 c l =15pf 80 - - mhz c l =50pf 65 - - mhz t w pulse width clock pulse high or low c l = 50 pf; see figure 7 5.0 - - ns set or reset pulse low c l = 50 pf; see figure 7 5.0 - - ns table 10: dynamic characteristics type 74ahct74 continued gnd = 0 v; t r = t f 3.0 ns; v cc = 4.5 v to 5.5 v; see figure 9 symbol parameter test conditions min typ max unit
9397 750 14504 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 04 7 february 2005 15 of 23 philips semiconductors 74ahc74; 74ahct74 dual d-type ?ip-?op with set and reset; positive-edge trigger [1] typical values are measured at v cc = 5.0 v. [2] c pd is used to determine the dynamic power dissipation (p d in m w): p d =c pd v cc 2 f i n+ ? (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in v; n = number of inputs switching; ? (c l v cc 2 f o ) = sum of outputs. [3] the condition is v i = gnd to v cc . 12. waveforms t rem removal time set or reset c l = 50 pf; see figure 8 3.5 - - ns t su set-up time nd to ncp c l = 50 pf; see figure 7 5.0 - - ns t h hold time nd to ncp see figure 7 0--ns table 10: dynamic characteristics type 74ahct74 continued gnd = 0 v; t r = t f 3.0 ns; v cc = 4.5 v to 5.5 v; see figure 9 symbol parameter test conditions min typ max unit measurement points are given in t ab le 11 . the shaded areas indicate when the input is permitted to change for predictable output performance. v ol and v oh are typical voltage output drop that occur with the output load. fig 7. the clock (ncp) to output (nq, n q) propagation delays, the clock pulse width, the nd to ncp set-up times, the ncp to nd hold times and the maximum clock pulse frequency mna422 t h t su t h t phl t phl t w t plh t plh t su 1/f max v m v m v m v m v i gnd v i gnd ncp input nd input v oh v ol nq output v oh v ol nq output
9397 750 14504 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 04 7 february 2005 16 of 23 philips semiconductors 74ahc74; 74ahct74 dual d-type ?ip-?op with set and reset; positive-edge trigger measurement points are given in t ab le 11 . v ol and v oh are typical voltage output drop that occur with the output load. fig 8. the set (n sd) and reset (n rd) input to output (nq, n q) propagation delays, the set and reset pulse widths and the n rd to ncp removal time table 11: measurement points type input output v m v m 74ahc74 0.5 v cc 0.5 v cc 74ahct74 1.5 v 0.5 v cc for test data see t ab le 12 . de?nitions for test circuit: c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to output impedance z o of the pulse generator. fig 9. load circuitry for switching times mna423 t rem t phl t phl t w t plh t plh v m v m v m t w v m v m v i gnd v i gnd nsd input v i gnd nrd input ncp input v oh v ol nq output v oh v ol nq output mna101 v cc v i v o r t c l pulse generator d.u.t.
9397 750 14504 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 04 7 february 2005 17 of 23 philips semiconductors 74ahc74; 74ahct74 dual d-type ?ip-?op with set and reset; positive-edge trigger table 12: test data type input load test v i t r , t f c l 74ahc74 v cc 3.0 ns 50 pf, 15 pf t plh , t phl 74ahct74 3.0 v 3.0 ns 50 pf, 15 pf t plh , t phl
9397 750 14504 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 04 7 february 2005 18 of 23 philips semiconductors 74ahc74; 74ahct74 dual d-type ?ip-?op with set and reset; positive-edge trigger 13. package outline fig 10. package outline sot108-1 (so14) unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot108-1 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 7 8 1 14 y 076e06 ms-012 pin 1 index 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.35 0.34 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 99-12-27 03-02-19 0 2.5 5 mm scale so14: plastic small outline package; 14 leads; body width 3.9 mm sot108-1
9397 750 14504 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 04 7 february 2005 19 of 23 philips semiconductors 74ahc74; 74ahct74 dual d-type ?ip-?op with set and reset; positive-edge trigger fig 11. package outline sot402-1 (tssop14) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.72 0.38 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot402-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 17 14 8 q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 a max. 1.1 pin 1 index
9397 750 14504 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 04 7 february 2005 20 of 23 philips semiconductors 74ahc74; 74ahct74 dual d-type ?ip-?op with set and reset; positive-edge trigger fig 12. package outline sot762-1 (dhvqfn14) terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 3.1 2.9 d h 1.65 1.35 y 1 2.6 2.4 1.15 0.85 e 1 2 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot762-1 mo-241 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot762-1 dhvqfn14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 26 13 9 8 7 1 14 x d e c b a 02-10-17 03-01-27 terminal 1 index area a c c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1)
9397 750 14504 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 04 7 february 2005 21 of 23 philips semiconductors 74ahc74; 74ahct74 dual d-type ?ip-?op with set and reset; positive-edge trigger 14. revision history table 13: revision history document id release date data sheet status change notice doc. number supersedes 74ahc_ahct74_4 20050207 product data sheet - 9397 750 14504 74ahc_ahct74_3 modi?cations: ? the format of this data sheet is redesigned to comply with the current presentation and information standard of philips semiconductors. ? added: type numbers 74AHC74BQ and 74ahct74bq (dhvqfn14 package). 74ahc_ahct74_3 20040429 product speci?cation - 9397 750 13118 74ahc_ahct74_2 74ahc_ahct74_2 19990923 product speci?cation - 9397 750 06291 74ahc_ahct74_1 74ahc_ahct74_1 19990805 product speci?cation - 9397 750 05747 -
philips semiconductors 74ahc74; 74ahct74 dual d-type ?ip-?op with set and reset; positive-edge trigger 9397 750 14504 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 04 7 february 2005 22 of 23 15. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 17. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 18. contact information for additional information, please visit: http://www.semiconductors.philips.com for sales of?ce addresses, send an email to: sales.addresses@www.semiconductors.philips.com level data sheet status [1] product status [2] [3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2005 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 7 february 2005 document number: 9397 750 14504 published in the netherlands philips semiconductors 74ahc74; 74ahct74 dual d-type ?ip-?op with set and reset; positive-edge trigger 19. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 quick reference data . . . . . . . . . . . . . . . . . . . . . 1 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 5 7.1 function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 recommended operating conditions. . . . . . . . 6 10 static characteristics. . . . . . . . . . . . . . . . . . . . . 6 11 dynamic characteristics . . . . . . . . . . . . . . . . . 10 12 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . 18 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 21 15 data sheet status . . . . . . . . . . . . . . . . . . . . . . . 22 16 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 17 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 18 contact information . . . . . . . . . . . . . . . . . . . . 22

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