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sdf00031aem 1 mn863584 1. type gate driver ic with 244-pin output for tft lcd * number of output channels : 244 outputs * driver operating frequency : 500 khz max. * lcd drive voltage : v ee +40 v max. * driver output level : binary ? incorporating a bidirectional shift register function. 2. overview 3. feature color tft lcd driver publication date: june 2002 m n 863584 - d
sdf00031aem 2 m n863584-d 4. block diagram x243 x2 x1 x244
sdf00031aem 3 m n863584-d 5-1) lcd drive voltage n egative lcd drive voltage output is possible on the basis of the logic ground voltage, v ss . 5. functions v ss v dd v ee v gg logic input x1 to x244 5-2) operation m ode selection mode="h": positive logic the start pulse is fetched at the fx rising edge and the data is shifted. the carry p ulse sy nchronizes with the fx falling edge. the high-level start pulse corresponds to the v gg display voltage. mode="l": negative logic the start p ulse is fetched at the fx falling edge and the data is shifted at the rising edge. the disp lay voltage will be outp ut only when the fx level is high. the carry pulse synchronizes with the fx rising edge. the low-level start pulse corresponds to the v gg display voltage.
sdf00031aem 4 m n863584-d the shift direction can be set with ud input. 5-3) selection of shift direction and number of outputs 244-output mode ud ud="h" ud="l" x 1 - 1 x 2 - x 3 x 242 - x 243 - x 244 start pulse data shift direction carry pulse st vd st vu st vu st vd oevsel oevsel="h" oev="h" oev oev="l" oevsel="l" all v ee output x244 - x243 - x242 x3 - x2 - x1 5-4) non-display function n ormal output n ormal output all v ee output set the oevsel to high level and apply high-level input to the oev. alternatively, set the oevsel to low level and ap p ly low-level inp ut to the oev. then all the outp uts will be set to non-display level regardless of the data in the shift register. this function operates without being synchronized with the fx. the above w ill not reset the shift data. ? ? ? ? ? ? ? ?
sdf00031aem 5 m n863584-d 6. pin descriptions fx i shift register clock input pin stvd / stv u x1 to x244 lcd drive output pins v dd oevsel input pin for selecting oev oevsel="h" : oev=active high oevsel="l" : oev=active low ud u d ="h " : x1 - x2 4 4 v gg power supply for the level shifter and output buffer this power supply drives lcd. power supply v ee logic power supply v ss ud="h " ud="l" st vd st vu input output output input mod e mode="h" : positive-logic operation mode="l" : negative-logic operation oev com1 to com4 dummy pads through wiring pins dumm y 1 to dummy8 pin name i/o function description shift clock of the internal shift register input pin for selecting the right shift or left shift direction i i/o start pulse input and carry pulse output pins i i input pin for selecting input p olarity when oevsel and oev pins are set to high level or low level, the corresponding lcd drive output pins will be at the level of off- potential (v ee ) without being synchronized with the fx regardless of the contents of the data in the shift re g ister. not reset. i input pin for selecting mode o power supply power supply power supply lcd drive output power supply lcd drive power supply 1 v gg system ground lcd drive power supply 2 v dd system ground g round provides this pin with lcd drive voltage. p ower supply for the logic circuit low level reference voltage for logic pins which have same name at the input side and output side are connected. t hey are not connected to a circuit. dummy pads only located. the y are not connected to a circuit. v gg or v ee voltage level is output according to oev, oevsel, and fx inputs and the data in the shift register. u d ="l " : x2 4 4 - x1 ? ?
sdf00031aem 6 m n863584-d 7. basic waveform when mode="h," oevsel="h," and ud="h" x2 when mode="l," oevsel="h," and ud="h" ( ): ud="l" 2 3 4 5 6 243 244 245 246 x1 x3 x244 st vd fx st vu 7 x243 1 oe v (x244) (x243) (x242) (x2) (x1) (stvd) (stvu) 23456 243 244 245 246 x1 x2 x3 x243 fx x244 7 1 st vd oe v st vu (stvu) (x244)(x244) (x243) (x242) (x2) (x1) (stvd) ( ): ud="l"
sdf00031aem 7 m n863584-d 2 3 4 5 6 243 244 245 246 when mode = "h," oevsel = "l," and ud = "h" x1 x2 x3 x244 st vd fx st vu 7 x243 23456 243 244 245 246 x1 x2 x3 x243 fx x244 7 1 1 oe v st vd when mode = "l," oevsel = "l," and ud = "h" oe v st vu (x244) (x243) (x242) (x2) (x1) (stvd) ( ): ud="l" (stvu) (stvu) (x244)(x244) (x243) (x242) (x2) (x1) (stvd) ( ): ud="l"
sdf00031aem 8 m n863584-d a. absolute maximum ratings rating parameter symbol unit supply voltage 1 v dd v v ss =0 v a1 a2 -0.3 to +7.0 v gg a3 v ee digital inp ut voltage op erating ambient tem p eratur e t a a4 -0.3 to v dd +0.3 a5 -20 to +75 v gg -44 to +0.3 supply voltage 2 supply voltage 3 v v storage temp erature t stg -55 to +120 a6 a7 v i v n ote 1) the absolute maximum ratings are the limit values beyond which the ic may be broken. they don't assure operation. n ote 3) the values specified in the product standards are guaranteed on condition that the ic is applied to the manufacturer's standard p acka g es. n ote 4) set the drive voltage to satisfy the following condition when the ic is turned on and turned off and while the ic is operating. v ee v gg n ote 5) if voltage is improperly applied to the ic when the ic is turned on, a high current may flow to the ic, and the ic may be totally broken. when turning on the ic, apply v dd first. then apply v ee , v gg , and the logic signal after v dd has risen to 90% of the set value. the v gg input, v ee input, and logic signal input can be turned on in any order, provided that the following conditions are satisfied for the protection of the v gg power supply. a) the ic is in normal operation at the rising edge of v gg (i.e., the v gg output is selected for only a single output) or all the outputs are in v ee output condition. b) all the inputs are not open and are grounded by a low impedance path until each power supply and the lo g ic si g nal rise. op erating storage tem p eratur e t opr -0.3 to +44 n ote 2) t he operating storage temperature is the temperature range beyond which the ic may be broken. t hey don't assure o p eration. v ss v dd v ee v gg 90% n ote 6) activate the oev, however, if the v dd , v ee , and v gg power supplies are turned on simultaneously. -30 to +85 product standards c c c
s d f 0 0 03 1 a e m 9 m n863584-d b . o p e r a t i ng c o nd i t i ons r a t i n g p a r a m e t e r s y m bol u n i t m i n t y p m a x o p e r a t i n g s u p p ly vo l t a g e 1 v cond i - t i ons b1 b2 b3 2.6 3.6 v dd v gg t a = -20 t o + 7 5 v s s = 0 v v gg -v ee 10 v ee +40 op erating sup p ly voltage 2 op erating sup p ly voltage 3 v v b4 v ee v dd -10 v op erating sup p ly voltage 4 40 2.9 v dd v gg -40 * the delay time of driving output is not guaranteed in the following conditions. -10 -20 -30 -40 10 20 30 40 -5 (-2.1 v, 2.9 v) (-2.1 v, 17.9 v) (-7.1 v, 12.9 v) (-7.1 v, 32.9 v) (-37.1 v, 2.9 v) v gg voltage (v) rating symbol unit min typ max v2.6 3.6 v dd v gg v ee +20 v v ee v dd -5 v 2.9 v dd v gg -10 z the values sp ecified in the product standards are guaranteed on condition that the ic is applied to the manufacturer's standard packages. operating voltage range of v ee and v gg when v dd = 2.9 v v ee voltage (v) c c
sdf00031aem 10 m n863584-d v v high-level inp ut voltage low-level inp ut voltage inp ut leakage current v ih1 v il1 i li1 0.8 1.65 v dd 0 -10 10 c5 c6 c7 1) input pins (rl, fx, oev, oevsel, mode) 2) i/o pins (stvd, stvu) high-level inp ut voltage low-level inp ut voltage v ih3 v il3 v v 0 c8 c9 c10 rating parameter symbol unit min typ max condi- tions 0.2 1.65 0.8 1.65 0.2 1.65 v dd f fx = 20.0 khz v dd = 3.3 v v ee = -15 v v gg = 15 v n o-load output (1) dc characteristics op erating supply current (v dd ) i dd i gg c1 c2 50 300 i ds c3 10 quiescent supply current (v dd ) i gs c4 10 in standby mode, v dd = 3.3 v v ee = -15 v v gg = 15 v t a = 25 v ss = 0 v rating parameter symbol unit min typ max conditions op erating supply current (v gg ) quiescent supply current (v gg ) c. dc charact eri st i cs z the values sp ecified in the product standards are guaranteed on condition that the ic is applied to the manufacturer's standard packages. t a = 25 v ss = 0 v high-level output voltage low-level output voltage v oh v ol v v 0.4 v dd -0.4 c11 -100 100 c c m a m a m a m a m a m a m a
sdf00031aem 11 m n863584-d min typ max v lo1 -50 50 c12 c13 1000 1000 600 400 10 c14 r com parameter symbol conditions rating unit t a = 25 v ss = 0 v 4) through wiring (com1 to com4) 3) lcd drive output pins (x1 to x244) output leakage current output on-state resistance v gg =15 v v ee =-15 v v om =v gg - 0.5 v v om is the voltage that is applied to x1 to x244 p ins. v gg =15 v v ee =-15 v v om =v ee + 0.5 v v om is the voltage that is applied to x1 to x244 p ins. z the values sp ecified in the product standards are guaranteed on condition that the ic is applied to the manufacturer's standard packages. r on -v gg r on -v off wiring resistance c m a w w w
sdf00031aem 12 m n863584-d (2) ac characteristics clock high-level pulse width clock low-level pulse width stv data setup time stv data hold time stv output delay time xn output delay time t fx t wh t wl t su t h t pd1 t pd2 2 ns c l =50 pf c15 c16 c17 c18 c19 c20 c21 500 500 t a = 25 v ss = 0 v rating parameter symbol unit min typ max conditions clock cycle ns ns ns ns 100 300 350 c l =500 pf 1 ns z the values sp ecified in the product standards are guaranteed on condition that the ic is applied to the manufacturer's standard packages. ud setup time ud hold time mode setup time m ode hold time c22 c23 c24 c25 t su1 t h1 t su1 t h1 100 300 300 300 ns ns ns c m s m s
sdf00031aem 13 m n863584-d fx stv input 20% 2 0% 80% 80% 80% 80% 50% 50% stv output 60% 40% 20% t fx t wh t wl t su t h t pd1 t pd2 t pd1 60% ac characteristics timing chart 20% 20% 40% 60% t pd2 ud 80% t su1 t h1 20% fx 80% 20% 80% 20% 80% t su1 t h1 20% 80% 20% 80% 20% 80% 80% 20% 20% 80% fx 80% xn 20% 40% t pd2 60% xn (pos itive logic) 1.7 v 0 v 1.7 v 1.7 v 1.7 v 1.7 v 1.7 v 0 v 0 v 0 v 0 v 0 v (negative logic)
sdf00031aem 14 m n863584-d oe v 80% 20% 80% 20% xn 40% 60% t pd2 t pd2 mode 80% t su1 t h1 20% fx 80% 20% 80% 20% 80% t su1 t h1 20% 80% 20% 80% 20% 1.7 v 0 v 1.7 v 0 v 1.7 v 0 v
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