application note AN280/0189 in full bridge driver applications by thomas l. hopkins controlling voltage transients in applications that involve fast switching of inducti- ve loads, designers must consider the voltage tran- sients that are generated in such applications. to insure a reliable design, the voltage transients must be limited to a level that is within the safe operating conditions of the switching device. this application note discusses the sources of voltage tran-sients in full bridge applications and techniques that can be used to limit these over-voltage conditionsto safe le- vels. special attention will be given to applications using monolithic implementations of full bridge cir- cuits like the sgs-thomson l6202 and l6203. maximum ratings the maximum voltage rating for the bridge driver can be derived from the maximum ratings of the de- vices used in the output stage and are generally the bv ceo or bv dss of the power devices. in addition to the maximum allowable voltage across the output device, additional limits may be needed on the ma- ximum output voltage above supply or below ground, depending on the implementation of the output stage. as an example of a full bridge circuit, consider the sgs-thomson l6202 and l6203. these devices are full bridge drivers implemented with dmos tran- sistors on a monolithic structure. using these devi- ces full bridge drive circuits, like shown in figure 1, are easily implemented. the device has a maximum rating for the supply voltage of 60v, which implies a maximum bv dss forthe outputdevices of 60v. in ad- dition, due to the monolithic implementation, the voltage between the two output terminals must not exceed 60v. therefore, the maximum ratings that must be considered for the application are : v supply 60v v ds any output 60v v 01 -v 02 : 60v similar maximum ratings will exist for any full bridge application,with the exception of the differential out- put voltage limit, which will not exist for discrete im- plementations. figure 1 : dc motor drive circuit using l6203. 1/8
sources of voltage transients to protect against the over-voltage that may occur as a result of the inductive property of the load, volt- age clamps are normally employed to limit the volt- age across the output devices. in bridge applicationsthese clamps are normally a diode brid- ge that clamps the voltage to one diode drop above supply and one diode drop below ground. however, if the diode switches slower than the transistor, there is a short time where neither the transistor nor the diode is conducting and the voltage rise is limited only by the capacitance on the node. the result is that a vol-tage overshoot occurs during the time be- fore the diode turns on. when the bridge is build with dmos power transistors, the intrinsic body diode is often used as the clamp. this is true for the l6202 and l6203. as can be seen in the figure 2, the turn- off time of the dmos device in the l6203 is in the range of 25 to 50ns while the turn-on time of the in- trinsic drain to source diode is in the range of 150ns. this difference in switching time is characteristic of many dmos devices. figure 2 : output switching waveform for l6203. the second main factor contributing to the tran- sients is the parasitic inductancein the wiring or prin- ted circuit board layout. figure 3 shows the parasitic inductances in the dc motor application. when the current flowing in these parasitic inductances is ra- pidly switched, the inductive property of the wire causes a voltage transient. when large currents are rapidly switched, as with dmos transistors, large voltage transientscan be induced across even small parasitic inductances. for an inductive load driven by an h-bridge the change of current in the power supply lead is equal to twice the load current when the bridge is switched off or the bridge is switched from one diagonal pair of transistors being on the other pair. here switching the bridge results in a change of direction of current flow in the power le- ads. the time that it takes to switch the current is es- sentially the turn off time of the output device. in this case the resulting voltage across the inductance is given by the equation : l 2 xi1 toff v = l di/dt = (1) figure 3 : parasitic wiring inductances in dc motor drive circuit. application note 2/8
in fast switching applications, like the l6202, where the switching time is as short as 25ns, the induced voltage spike can become quite large. for example if the dc motor in figure 3 was driven with 4a and the bridge was switched off, a parasitic inductance of only 15nh would produce a 5v spike. since the current is reversed in both the supply and ground le- ads the device would see a 10v spike between the power supply pin and chip ground, if the inductance of both wires were the same. as a design example, consider a dc motor driver shown in figure 1 with the following system charac- teristics : supply voltage max 46v min 38v peak motor current 5a chopping frequency 50khz figure 4 : enable input and motor current for examples. for evaluation, the motor will be driven with a peak current of 4a. figure 4 shows the input signals for the l6202 and the motor current used in the evalua- tion. here the bridge is energized and the load current is allowed to build up to 4a. when the 4a peak is rea- ched, the bridge is disabled and the current decays through the intrinsic diodes in the dmos power sta- ge. all figures in the remainder of this note are taken under these operating conditions. power supply filtering to reduce the effect of the wiring inductance a good high frequencycapacitor can be placed on the board near the bridge circuit to absorb the small amount of inductive energy in the leads. it should be noted that this capacitor is usually required in addition to an electrolytic capacitor, which has poor performan- ce at high frequencies. operating voltages. figure 5a : supply voltage. application note 3/8
figure 5a shows the spike on the power supply pin of the l6203 and the output pins when the bridge was disabled. these waveformswere present when the device was mounted on a printed circuit board where reasonable care was taken in the layout. when a 0.2 m f polyester capacitor was connected between the supply and ground pin of the l6203 the voltage spike on the power supply was significantly reduced, as shown in figure 6a. figure 5b : v01 - v02. looking at the voltage waveform at the output ter- minals of the l6202, shown in figure 6b, a large spi- ke is still present. the worst case spike is measured between the output terminals of the device (v out1 - v out2 ) since the spikes above the supply and below ground are both present. after the voltage spike on the power supply was eliminated, the tran-sients on the output must be related to the mismatch of swit- ching times between the diodes and power transi- stors. to control these spikes two possible alternatives are present ; 1) use faster diodes, or 2) use an external circuit to slow the voltage rise time across the output when the transistors are turned off. schottky diodes connected external to the l6203 would more closely match the switching time of the dmos power transistors, but are expensive and require additional board space. operatingvoltages with 0.2 m f bypass capacitor on supply pin. figure 6a : supply voltage. figure 6b : v01 - v02. slowing down the outputvoltage rise time can be ac- complished by connecting a snubber network across the output ter minals of the device. figure 7 showsthe connectionfor a rc snubbingcircuit used with the l6203. with properly selected values the slope of the voltage waveform can be limited to whe- re the diodes have sufficient time to turn on and clamp the remaining inductive energy. application note 4/8
snubber design considerations the function of the snubber network is to limit the rate of change of the voltage across the motor (out- put terminals of the l6203) when one of the dmos devices is turned off. using the rc snubbing circuit shown in figure 7, the rate of change of the voltage on the output is dominated by the capacitor while the resistor is used primarily to limit the peak current flo- wing through the power transistor when it turns on. figure 7 : dc motor drive applications with snub- ber network and bypass capacitor. the time constant of the motor current is much lon- ger than the switching time, due to the inductance of the motor. at the time of switching the dc motor can be assumed to be a constant current generator equal to the peak current at switching. if this current is switched into the snubber, the voltage across the snubber network will jump to a value equal to the snubber resistance times the motor current. after the initial step, the rate of change is limited by the motor current charging the snubber capacitor. to properly size the snubber network the resistor is selected such that the maximum motor current will produce a voltage less than the minimum power supply voltage. if the resistor is larger than this va- lue, the snubber will be ineffective since the capaci- tor will not limit the voltage rise until the voltage has become greater than the power supply. for the de- sign example, the maximum resistancefor the snub- ber is given by the equation : rmax = vsmin/ipeak = 38v/5a = 7.6 ohm (2) the snubber capacitor is calculated from the peak current and the target rise time. the capacitance is given by the equation : c = ipeak dt/dv = 5a 150ns/50v = 0.015 m f (3) when the snubber network is installed in the appli- cation the voltage transients on the terminals of the l6203 are greatly reduced, as shown in figure 8. the drawback of a snubber network of this type is that a current spike will flow into the transistor when it is switched on as the capacitor is discharged. the theoretical peak value of this spike is given by the equation : i = vsmax/r = 42v/7.5ohm = 5.6a (4) application note 5/8
operating voltages with snubber network and by- pass capacitor. figure 8a : sypply voltage. figure 8b : v01 - v02. this peak current flowing in the snubber is added to the load current when the device is turned on and the total peak current in the transistor is the sum of the snubber circuit current plus the load current. in practice the peak current measured is usually much less than the calculated peak, due to the capacitors internal resistance and inductance and the resistor inductance. figure 9 shows the peak current in the snubber network in the design example. current in the snubber circuit. figure 9a : turn on 2.0a/div. the power dissipated in the snubber resistor is the sum of the dissipation during the turn-on and turn-off of the bridge. the resistor dissipation is : pd = (i1 2. r . dc) + (i2 2. r . dc) (5) where i 1 = current at turn-on i 2 = current at turn-off r = snubber resistor dc = duty cycle of current flow for the design example the power dissipation, not considering the duty cycle is : pd = ((2.5) 2. 7.5 . .01) + ((5) 2. 7.5 . 0.01) = 0.469 + 1.875 = 2.344 w (6) application note 6/8
if the device is chopping for only a portion of the time the dissipation in the resistor will be reduced. figure 9b : turn off 2.0a/div. conclusion with the 0.2 m f bypass capacitor and the snubber circuit in place the voltage transients measured in the application have been limited to within safe va- lues for the l6202. as shown in figure 8, the power supply voltage, the voltage across each of the dmos transistors and the voltage across the output of the bridge (vout1 - vout2) are all within the ma- ximum rating of the device with some margin. summary to insure reliable performance of a h-bridge drive circuit, the designermust insurethat the device ope- rates within the maximum ratings of the device(s) used in the circuit. one of the critical parameters to consider is the maximum voltage capability of the devices. to maintain the reliability, the voltage tran- sients due to switching inductive loads must be maintained within the ratings of the device. two techniques used to control the voltage tran- sients in fast switching applications are proper by- pass filtering of the power supply and snubbing the outputs to control voltage rise times. using these two techniques the voltage transients in a dmos bridge application can be controlled to within safe le- vels. application note 7/8
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifica- tions mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information pre- viously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1995 sgs-thomson microelectronics all rights reserved sgs-thomson microelectronics group of companies australia - brazil - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thaliand - united kingdom - u.s.a. application note 8/8
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