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flash-erasable reprogrammable cmos pal ? device palce22v10 palce22v10 is a replacement device for palc22v10, palc22v10b, and palc22v10d. use ultra37000 tm for all new designs cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-03027 rev. *b revised april 9, 2004 features ? low power ? 90 ma max. commercial (10 ns) ? 130 ma max. commercial (5 ns) ? cmos flash eprom technology for electrical erasabil- ity and reprogrammability ? variable product terms ? 2 (8 through 16) product terms ? user-programmable macrocell ? output polarity control ? individually selectable for registered or combina- torial operation ? up to 22 input terms and 10 outputs ? dip, lcc, and plcc available ? 5 ns commercial version 4 ns t co 3 ns t s 5 ns t pd 181-mhz state machine ? 10 ns military and industrial versions 7 ns t co 6 ns t s 10 ns t pd 110-mhz state machine ? 15-ns commercial, industrial, and military versions ? 25-ns commercial, industrial, and military versions ? high reliability ? proven flash eprom technology ? 100% programming and functional testing logic block diagram (pdip/cdip) pin configuration plcc top view macrocell 8 10 12 14 16 16 14 12 10 8 1110 987 65 4321 12 13 14 15 16 17 18 19 20 21 22 23 24 preset programmable and array (132 x 44) i iiii ii iiicp/i v ss ii/o 9 i/o 8 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 v cc reset macrocell macrocell macrocell macrocell macroc ell macrocell macrocell macrocell macrocell i/o i/o i/o i/o i/o i/o i i i i i i 2 3 4 5 6 7 i 9 i cp/i v i/o i/o 8 i/o i/o i v i i ss 0 1 cc n/c lcc top view 5 6 7 8 9 10 11 4 3 2 282726 12131415161718 25 24 23 22 21 20 19 i/o i/o i/o i/o i/o i/o i i i i i i 2 3 4 5 6 7 i 9 i cp/i v i/o i/o 8 i/o i/o i v i i ss 0 1 cc 1 n/c nc nc nc nc nc nc 25 24 23 22 21 20 19 5 6 7 8 9 10 11 121314 1516 1718 432 282726 1
palce22v10 use ultra37000 tm for all new designs document #: 38-03027 rev. *b page 2 of 13 functional description the cypress palce22v10 is a cmos flash-erasable second-generation programmable array logic device. it is implemented with the famili ar sum-of-products (and-or) logic structure and the programmable macrocell. the palce22v10 is executed in a 24-pin 300-mil molded dip, a 300-mil cerdip, a 28-lead square ceramic leadless chip carrier, a 28-lead square plastic leaded chip carrier, and provides up to 22 inputs and 10 outputs. the palce22v10 can be electrically erased and reprogrammed. the program- mable macrocell provides the capability of defining the archi- tecture of each output individually. each of the ten potential outputs may be specified as ?re gistered? or ?combinatorial.? polarity of each output may also be individually selected, allowing complete flexibility of output configur ation. further configurability is provided through ?array? configurable ?output enable? for each potential output. this feature allows the 10 outputs to be reconfigured as inputs on an individual basis, or alternately used as a combination i/o controlled by the programmable array. palce22v10 features a variable product term architecture. there are 5 pairs of product term sums beginning at 8 product terms per output and incrementing by 2 to 16 product terms per output. by providing this variable structure, the palce22v10 is optimized to the configurations found in a majority of applications withou t creating devices that burden the product term structures with unusable product terms and lower performance. additional features of the cypress palce22v10 include a synchronous preset and an asynchronous reset product term. these product terms are common to all macrocells, elimi- nating the need to dedicate standard product terms for initial- ization functions. the device automatically resets upon power-up. the palce22v10, featuring programmable macrocells and variable product terms, provides a device with the flexibility to implement logic functions in the 500- to 800-gate-array complexity. since each of the ten output pins may be individ- ually configured as inputs on a temporary or permanent basis, functions requiring up to 21 inputs and only a single output and down to twelve inputs and ten outputs are possible. the ten potential outputs are enabled us ing product terms. any output pin may be permanently selected as an output or arbitrarily enabled as an output and an input through the selective use of individual product terms associated with each output. each of these outputs is achieved through an individual program- mable macrocell. these macrocells are programmable to provide a combinatorial or regist ered inverting or non-inverting output. in a registered mode of operation, the output of the register is fed back into the array, providing current status information to the array. this information is available for estab- lishing the next result in applications such as control state machines. in a combinatorial configuration, the combinatorial output or, if the output is dis abled, the signal present on the i/o pin is made available to the array. the flexibility provided by both programmable product term control of the outputs and variable product terms allows a significant gain in functional density through the use of programmable logic. along with this increase in functional density, the cypress palce22v10 provides lower-power operation through the use of cmos technology, and increased testability with flash reprogrammability. selection guide generic part number t pd ns t s ns t co ns i cc ma com?l mil/ind com?l mil/ind com?l mil/ind com?l mil/ind palce22v10-5 5 3 4 130 palce22v10-7 7.5 5 5 130 palce22v10-10 1010667790150 palce22v10-15 15 15 10 10 8 8 90 120 palce22v10-25 25 25 15 15 15 15 90 120 configuration table registered/combinatorial c 1 c 0 configuration 0 0 registered/active low 0 1 registered/active high 1 0 combinatorial/active low 1 1 combinatorial/active high
palce22v10 use ultra37000 tm for all new designs document #: 38-03027 rev. *b page 3 of 13 macrocell output select mux ar ss 10 q q d cp sp input/ feedback mux 1 s macrocell 1 c 0 c
palce22v10 use ultra37000 tm for all new designs document #: 38-03027 rev. *b page 4 of 13 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature .................................?65 c to +150 c ambient temperature with power applied.............................................?55 c to +125 c supply voltage to ground potential (pin 24 to pin 12) ........................................... ?0.5v to +7.0v dc voltage applied to outputs in high-z state ............................................... ?0.5v to +7.0v dc input voltage............................................ ?0.5v to +7.0v output current into outputs (low)............................. 16 ma dc programming voltage............................................. 12.5v latch-up current..................................................... > 200 ma static discharge voltage (per mil-std-883, method 3015) ..... .............. ......... > 2001v operating range range ambient temperature v cc commercial 0 c to +75 c 5v 5% industrial ?40 c to +85 c5v 10% military [1] ?55 c to +125 c 5v 10% electrical characteristics over the operating range [2] parameter description test conditions min. max. unit v oh output high voltage v cc = min., v in = v ih or v il i oh = ?3.2 ma com?l 2.4 v i oh = ?2 ma mil/ind v ol output low voltage v cc = min., v in = v ih or v il i ol = 16 ma com?l 0.5 v i ol = 12 ma mil/ind v ih input high level guaranteed input log ical high voltage for all inputs [3] 2.0 v v il [4] input low level guaranteed input log ical low voltage for all inputs [3] ?0.5 0.8 v i ix input leakage current v ss < v in < v cc , v cc = max. ?10 10 a i oz output leakage current v cc = max., v ss < v out < v cc ?40 40 a i sc output short circuit current v cc = max., v out = 0.5v [5,6] ?30 ?130 ma i cc1 standby power supply current v cc = max., v in = gnd, outputs open in unprogrammed device 10, 15, 25 ns com?l 90 ma 5, 7.5 ns 130 ma 15, 25 ns mil/ind 120 ma 10 ns 120 ma i cc2 [6] operating power supply current v cc = max., v il = 0v, v ih = 3v, output open, device programmed as a 10-bit counter, f = 25 mhz 10, 15, 25 ns com?l 110 ma 5, 7.5 ns com?l 140 ma 15, 25 ns mil/ind 130 ma 10 ns mil/ind 130 ma capacitance [6] parameter description test conditions min. max. unit c in input capacitance v in = 2.0v @ f = 1 mhz 10 pf c out output capacitance v out = 2.0v @ f = 1 mhz 10 pf endurance characteristics [6] parameter description test conditions min. max. unit n minimum reprogramming cycles normal programming conditions 100 cycles notes: 1. t a is the ?instant on? case temperature. 2. see the last page of this specification for group a subgroup testing information. 3. these are absolute values with respect to device ground. a ll overshoots due to system or tester noise are included. 4. v il (min.) is equal to ?3.0v for pulse durations less than 20 ns. 5. not more than one output should be tested at a time. duration of the short circuit should not be more than one second. v out = 0.5v has been chosen to avoid test problems caused by tester ground degradation. 6. tested initially and after any design or process changes that may affect these parameters.
palce22v10 use ultra37000 tm for all new designs document #: 38-03027 rev. *b page 5 of 13 ac test loads and waveforms 5v output including jig and scope c l (a) (b) 5v output including jig and scope 5pf (c) output c l r1238 ? (319 ? mil) r1238 ? (319 ? mil) r2170 ? (236 ? mil) r2170 ? (236 ? mil) 750 ? (1.2k ? mil) output 2.08v = v thc output 2.13v = v thm 90% 10% 3.0v gnd 90% 10% all input pulses <2ns <2ns (d) 99 ? 136 ? equivalent to:th venin equivalent (commercial) equivalent to: th venin equivalent (military) load speed c l package 5, 7.5, 10, 15, 25 ns 50 pf pdip, cdip, plcc, lcc commercial switching characteristics palce22v10 [2, 7] parameter description 22v10-5 22v10-7 22v10-10 22v10-15 22v10-25 unit min. max. min. max. min. max. min. max. min. max. t pd input to output propagation delay [8] 3 5 3 7.5 3 10 3 15 3 25 ns t ea input to output enable delay [9] 6 8 10 15 25 ns t er input to output disable delay [10] 6 8 10 15 25 ns t co clock to output delay [8] 2 4 2 5 2 7 2 8 2 15 ns notes: 7. part (a) of ac test loads and wavefo rms is used for all parameters except t er and t ea(+) . part (b) of ac test loads and waveforms is used for t er . part (c) of ac test loads and waveforms is used for t ea(+) . 8. min. times are tested initially and after any design or process changes that may affect these parameters. 9. the test load of (a) of ac test loads and waveforms is used for measuring t ea(-) . the test load of (c) of ac test loads and waveforms is used for measuring t ea(+) only. please see (e) of ac test loads and waveforms for enable and disable test waveforms and measurement reference levels. 10. this parameter is measured as the time after output disable input that the previous output data state remains stable on the output. this delay is measured to the point at which a previous high level has fallen to 0.5v below v oh min. or a previous low level has risen to 0.5v above v ol max. please see (e) of ac test loads and waveforms for enable and disable test waveforms and measurement reference levels. parameter v x output w aveform measurement level t er (- ) 1.5v v oh 0.5v v x 0.5v t er (+) 2.6v v ol v x t ea (+) 0v 0.5v t ea (- ) v thc v x v ol 1.5v v x v oh (e) test waveforms
palce22v10 use ultra37000 tm for all new designs document #: 38-03027 rev. *b page 6 of 13 t s1 input or feedback set-up time 3 5 6 10 15 ns t s2 synchronous preset set-up time 4 6 7 10 15 ns t h input hold time 0 0 0 0 0 ns t p external clock period (t co + t s ) 7 10 12 20 30 ns t wh clock width high [6] 2.5 3 3 6 13 ns t wl clock width low [6] 2.5 3 3 6 13 ns f max1 external maximum frequency (1/(t co + t s )) [11] 143 100 76.9 55.5 33.3 mhz f max2 data path maximum frequency (1/(t wh + t wl )) [6, 12] 200 166 142 83.3 35.7 mhz f max3 internal feedback maximum frequency (1/(t cf + t s )) [6,13] 181 133 111 68.9 38.5 mhz t cf register clock to feedback input [6,14] 2.5 2.5 3 4.5 13 ns t aw asynchronous reset width 8 8 10 15 25 ns t ar asynchronous reset recovery time 4 5 6 10 25 ns t ap asynchronous reset to registered output delay 7.5 12 13 20 25 ns t spr synchronous preset recovery time 4 6 8 10 15 ns t pr power-up reset time [6,15] 1 1 1 1 1 s military and industrial switching characteristics palce22v10 [2, 7] parameter description 22v10-10 22v10-15 22v10-25 unit min. max. min. max. min. max. t pd input to output propagation delay [8] 3 10 3 15 3 25 ns t ea input to output enable delay [9] 10 15 25 ns t er input to output disable delay [10] 10 15 25 ns t co clock to output delay [8] 2 7 2 8 2 15 ns t s1 input or feedback set-up time 6 10 18 ns t s2 synchronous preset set-up time 7 10 18 ns t h input hold time 0 0 0 ns t p external clock period (t co + t s ) 12 20 33 ns t wh clock width high [6] 3 6 14 ns t wl clock width low [6] 3 6 14 ns f max1 external maximum frequency (1/(t co + t s )) [11] 76.9 50.0 30.3 mhz f max2 data path maximum frequency (1/(t wh + t wl )) [6, 12 ] 142 83.3 35.7 mhz notes: 11. this specification indicates the guaran teed maximum frequency at which a state machine configuration with external feedback can operate. 12. this specification indicates the guaranteed maximum fre quency at which the device can operate in data path mode. 13. this specification indicates the guarante ed maximum frequency at which a state machine configuration with internal only feed back can operate. 14. this parameter is calculated from the clock period at f max internal (1/f max3 ) as measured (see note above) minus t s . 15. the registers in the palce22v10 have been designed with the capability to reset during system power-up. following power-up, all registers will be reset to a logic low state. the output state will depend on the polarity of the output buffer. this feature is useful in establishing stat e machine initialization. to insure proper operation, the rise in v cc must be monotonic and the timing constraints depicted in power-up reset waveform must be satisfied. commercial switching characteristics palce22v10 (continued) [2, 7] parameter description 22v10-5 22v10-7 22v10-10 22v10-15 22v10-25 unit min. max. min. max. min. max. min. max. min. max.
palce22v10 use ultra37000 tm for all new designs document #: 38-03027 rev. *b page 7 of 13 f max3 internal feedback maximum frequency (1/(t cf + t s )) [6, 13] 111 68.9 32.2 mhz t cf register clock to feedback input [6, 14] 3 4.5 13 ns t aw asynchronous reset width 10 15 25 ns t ar asynchronous reset recovery time 6 12 25 ns t ap asynchronous reset to registered output delay 12 20 25 ns t spr synchronous preset recovery time 8 20 25 ns t pr power-up reset time [6, 15] 1 1 1 s switching waveforms power-up reset waveform [15] military and industrial switching characteristics palce22v10 (continued) [2, 7] parameter description 22v10-10 22v10-15 22v10-25 unit min. max. min. max. min. max. t s t h t wl t wh t p t spr t ar t aw t ap t co t pd t er t ea t er t ea inputs i/o, registered feedback synchronous preset cp asynchronous reset registered outputs combinatorial outputs [10] [10] [9] [9] t pr power clock t s t wl 10% registered active low outputs supply voltage t pr max = 1 s 90% v cc
palce22v10 use ultra37000 tm for all new designs document #: 38-03027 rev. *b page 8 of 13 functional logic diagram for palce22v10 0 1 macro? cell macro? cell macro? cell macro? cell macro? cell macro? cell macro? cell macro? cell macro? cell macro? cell 2 3 4 5 6 7 8 9 10 11 23 22 21 20 19 18 17 16 15 14 13 16 20 24 28 32 36 40 ar oe 0 7 oe 0 9 oe 0 11 oe 0 13 oe 0 15 oe 0 15 oe 0 13 oe 0 11 oe 0 9 oe 0 7 s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s sp 12 8 4
palce22v10 use ultra37000 tm for all new designs document #: 38-03027 rev. *b page 9 of 13 military specificatio ns group a subgroup testing ordering information i cc (ma) t pd (ns) t s (ns) t co (ns) ordering code package name package type operating range 130 5 3 4 palce22v10-5pc p13 24-lead (300 mil) molded dip commercial palce22v10-5jc j64 28-lead plastic leaded chip carrier 130 7.5 5 5 palce22v10-7jc j64 28-lead plastic leaded chip carrier commercial palce22v10-7pc p13 24-lead (300-mil) molded dip 90 10 6 7 palce22v10-10jc j64 28-lead plastic leaded chip carrier commercial palce22v10-10pc p13 24-lead (300-mil) molded dip 150 10 6 7 palce22v10-10ji j64 28-lead plastic leaded chip carrier industrial palce22v10-10pi p13 24-lead (300-mil) molded dip palce22v10-10lmb 5962-89841063x l64 28-square leadless chip carrier military palce22v10-10kmb 5962-8984106kx k73 24-lead rectangular cerpack palce22v10-10dmb 5962-8984106lx d14 24-lead (300 mil) cerdip 90 15 10 8 palce22v10-15jc j64 28-lead plastic leaded chip carrier commercial palce22v10-15pc p13 24-lead (300-mil) molded dip 120 15 10 8 palce22v10-15kmb 5962-8984102kx k73 24-lead rectangular cerpack military palce22v10-15kmb 5962-8984103kx k73 24-lead rectangular cerpack palce22v10-15kmb 5962-8984105kx k73 24-lead rectangular cerpack palce22v10-15dmb 5962-8984102lx d14 24-lead (300 mil) cerdip palce22v10-15dmb 5962-8984103lx d14 24-lead (300 mil) cerdip palce22v10-15lmb 5962-89841033x l64 28-square leadless chip carrier palce22v10-15lmb 5962-89841053x l64 28-square leadless chip carrier 90 25 15 15 palce22v10-25jc j64 28-lead plastic leaded chip carrier commercial palce22v10-25pc p13 24-lead (300-mil) molded dip 120 25 15 15 palce22v10-25lmb 5962-89841043x l64 28-square leadless chip carrier military dc characteristics parameter subgroups v oh 1, 2, 3 v ol 1, 2, 3 v ih 1, 2, 3 v il 1, 2, 3 i ix 1, 2, 3 i oz 1, 2, 3 i cc 1, 2, 3 switching characteristics parameter subgroups t pd 9, 10, 11 t co 9, 10, 11 t s 9, 10, 11 t h 9, 10, 11 dc characteristics parameter subgroups
palce22v10 use ultra37000 tm for all new designs document #: 38-03027 rev. *b page 10 of 13 package diagrams 24-lead (300-mil) cerdip d14 mil-std-1835 d-9 config.a 51-80031-** 28-lead plastic leaded chip carrier j64 51-85001-*a
palce22v10 use ultra37000 tm for all new designs document #: 38-03027 rev. *b page 11 of 13 package diagrams (continued) .026 .040 .060 .090 .260 .325 .325 .260 .400 .360 .009 .004 base and seating plane .590 .045 max. .005 min. .050 bsc .015 .019 pin 1 i.d. .005 .015 .620 dimensions in inches min. max. pin 1 i.d. pin 1 i.d. pin 1 i.d option (see option) 24-lead rectangular cerpack k73 mil-std-1835 f-6 config. a 51-80060-*a
palce22v10 use ultra37000 tm for all new designs document #: 38-03027 rev. *b page 12 of 13 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. ultra37000 is a trademark of cypress semico nductor corporation. pal is a register ed trademark of advanced micro devices. all product and company names mentio ned in this document are the tradema rks of their respective holders. package diagrams (continued) 28-square leadless chip carrier l64 mil-std-1835 c-4 51-80051-**
palce22v10 use ultra37000 tm for all new designs document #: 38-03027 rev. *b page 13 of 13 document history page document title: palce22v10 flash-erasable reprogrammable cmos pal ? device document number: 38-03027 rev. ecn no. issue date orig. of change description of change ** 106372 07/11/01 szv change from spec number: 38-00447 to 38-03027 *a 114640 06/25/02 oor added a note on the title pa ge referring all new designs to this device added military part numbers *b 213375 see ecn fsg added note to title page: ?use ultra37000 for all new designs?

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