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  pxs20 microcontroller reference manual devices supported: pxs2005 pxs2010 PXS20RM rev. 1 06/2011
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pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor iii table of contents chapter 1 introduction 1.1 the pxs20 microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 pxs20 device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.3 device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.4 feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.4.1 high-performance e200z4d core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.4.2 crossbar switch (xbar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.4.3 memory protection unit (mpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.4.4 enhanced direct memory access (edma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.4.5 on-chip flash memory with ecc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.4.6 on-chip sram with ecc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.4.7 platform flash memory controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.4.8 platform static ram controller (sramc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.4.9 memory subsystem access time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.4.10 error correction status module (ecsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.4.11 peripheral bridge (pbridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.4.12 interrupt controller (intc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.4.13 system clocks and clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.4.14 frequency-modulated phase-locked loop (fmpll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.4.15 main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.4.16 internal reference clock (rc) oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.4.17 clock, reset, power mode, and test control modules (mc_cgm, mc_rgm, mc_pcu, and mc_me) . . . . . . . . . . . . . . . 1-13 1.4.18 periodic interrupt timer module (pit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.4.19 system timer module (stm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.4.20 software watchdog timer (swt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.4.21 fault collection and control unit (fccu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 1.4.22 system integration unit lite (siul) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 1.4.23 non-maskable interrupt (nmi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 1.4.24 boot assist module (bam). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 1.4.25 system status and configuration module (sscm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 1.4.26 controller area network module (can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 1.4.27 flexray . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 1.4.28 serial communication interface module (uart) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 1.4.29 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 1.4.30 pulse width modulator (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 1.4.31 etimer module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 1.4.32 sine wave generator (swg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 1.4.33 analog-to-digital converter module (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 1.4.34 junction temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 1.4.35 cross triggering unit (ctu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 1.4.36 cyclic redundancy checker (crc) unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 1.4.37 redundancy control and checker unit (rccu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 1.4.38 voltage regulator / power management unit (pmu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 1.4.39 built-in self-test (bist) capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 1.4.40 ieee 1149.1 jtag controller (jtagc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 1.4.41 nexus port controller (npc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 chapter 2 memory map chapter 3 signal description 3.1 package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor iv 3.2 supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30 3.3 system pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 3.4 pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33 3.5 mapping of ports to pgpdo/i r egisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-54 chapter 4 operating modes 4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2 lock step mode (lsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.3 decoupled parallel mode (dpm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.4 selecting lsm or dpm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.4.1 entering lsm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.4.2 entering dpm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.4.2.1 dual-core boot concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.4.2.2 software setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 chapter 5 device boot modes 5.1 boot mode functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 hardware configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2.1 single chip boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2.1.1 boot and alternate boot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3 boot-sector search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3.1 potential boot sectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3.2 reset configuration half-word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.3.3 boot and alternate boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.4 device behavior by boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.4.1 single chip mode ? unsecured . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.4.2 single chip mode ? secured . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.4.3 serial boot loader mode ? public password enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.4.4 serial boot loader mode ? flash memory password enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.4.5 standby boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.4.6 static mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 chapter 6 device security 6.1 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1.1 securing the microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1.2 unsecuring the microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.1.2.1 software unsecure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.2 serial access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 chapter 7 functional safety 7.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.2 redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.3 built-in self-test (bist) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.3.1 bist during boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.3.2 software-triggered bist during operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.3.3 software-triggered self-tests after boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.4 memory error detection and correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.5 monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.6 software measures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.7 fault reaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.8 external measures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor v chapter 8 boot assist module (bam) 8.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.3 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.4.1 entering boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.4.2 boot through bam . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.4.2.1 executing bam . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.4.2.2 bam software flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.4.2.3 bam resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.4.2.4 download and execute the new code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.4.2.5 download 64-bit password and password check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.4.2.6 download start address, vle bit and code size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.4.2.7 download data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 8.4.2.8 execute code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 8.4.3 uart boot ? autobaud disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 8.4.3.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 8.4.3.2 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 8.4.4 can boot ? autobaud disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 8.4.4.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 8.4.4.2 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 8.4.5 boot with autobaud feature [cut2/3 only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 8.4.5.1 configuration and detection/measurement flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 8.4.5.2 autobaud measurement for linflex / uart protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 8.4.5.3 autobaud measurement for flexcan / can protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14 8.4.5.4 shadow flash code improvements and extensions (for cut2 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 8.4.6 reading from test flash [cut 2/3only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 8.4.7 inhibiting bam operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 8.4.8 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 chapter 9 analog-to-digital converter (adc) 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.3 memory map and register descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.3.2 control logic registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.3.2.1 main configuration register (mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.3.2.2 main status register (msr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 9.3.3 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.3.3.1 interrupt status register (isr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.3.3.2 channel pending register 0 (ceocfr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.3.3.3 interrupt mask register (imr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 9.3.3.4 channel interrupt mask register 0 (cimr0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 9.3.4 watchdog threshold interrupt status register (wtisr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 9.3.5 watchdog threshold interrupt mask register (wtimr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 9.3.6 dma enable register (dmae) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.3.7 dma channel select register 0 (dmar0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.3.8 threshold registers (thrhlr n ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 9.3.9 presampling registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 9.3.9.1 presampling control register (pscr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 9.3.9.2 presampling register 0 (psr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.3.10 conversion timing registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.3.10.1conversion timing register 0 (ctr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.3.10.2conversion timing register 1 (ctr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 9.3.11 mask registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17 9.3.11.1normal conversion mask register 0 (ncmr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17 9.3.11.2injected conversion mask register 0 (jcmr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 9.3.12 power down exit delay register (pdedr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor vi 9.3.13 channel data registers (cdr n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19 9.3.14 channel watchdog selection registers (cwsel n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20 9.3.15 channel watchdog enable register 0 (cwenr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21 9.3.16 analog watchdog out of range register 0 (aworr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21 9.3.17 self test registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-22 9.3.17.1self test configuration register 1 (stcr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-22 9.3.17.2self test configuration register 2 (stcr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23 9.3.17.3self test configuration register 3 (stcr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25 9.3.17.4self test baud rate register (stbrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26 9.3.17.5self test status register 1 (stsr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27 9.3.17.6self test status register 2 (stsr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29 9.3.17.7self test status register 3 (stsr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29 9.3.17.8self test status register 4 (stsr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-30 9.3.17.9self test data register 1 (stdr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-30 9.3.17.10self test data register 2 (stdr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-31 9.3.17.11self test analog watchdog register 0 (staw0r). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-31 9.3.17.12self test analog watchdog register 1a (staw1ar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-32 9.3.17.13self test analog watchdog register 1b (staw1br) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-33 9.3.17.14self test analog watchdog register 2 (staw2r). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-33 9.3.17.15self test analog watchdog register 3 (staw3r). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-34 9.3.17.16self test analog watchdog register 4 (staw4r). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-34 9.3.17.17self test analog watchdog register 5 (staw5r). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-35 9.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-36 9.4.1 inter-module communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-36 9.4.2 analog channel conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-37 9.4.2.1 normal conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-37 9.4.2.2 start of normal conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-37 9.4.2.3 normal conversion operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-38 9.4.2.4 injected channel conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-39 9.4.2.5 abort conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-39 9.4.3 analog clock generator and conversion timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-40 9.4.4 adc sampling and conversion timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-40 9.4.5 presampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-41 9.4.6 programmable analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-42 9.4.6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-42 9.4.7 dma functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-43 9.4.8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-43 9.4.9 power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-44 9.4.10 auto-clock-off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-44 9.4.11 self testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-44 9.4.11.1general operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-44 9.4.11.2cpu mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-45 9.4.11.3ctu mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-47 9.4.11.4abort and abort chain for self testing channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-49 9.4.11.5self test analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-49 9.4.11.6watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-50 9.4.11.7baud rate control for test channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-52 chapter 10 clock architecture 10.1 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.2 clock distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.3 detailed module descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 chapter 11 clock generation module (mc_cgm) 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor vii 11.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.3.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 11.3.1.1output clock enable register (cgm_oc_en) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11.3.1.2output clock division select register (cgm_ocds_sc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11.3.1.3system clock select status register (cgm_sc_ss). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.3.1.4system clock divider configuration registers (cgm_sc_dc0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 11.3.1.5auxiliary clock 0 select control register (cgm_ac0_sc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11.3.1.6auxiliary clock 0 divider configuration registers (cgm_ac0_dc0?1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11.3.1.7auxiliary clock 1 select control register (cgm_ac1_sc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 11.3.1.8auxiliary clock 1 divider configuration register (cgm_ac1_dc0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11.3.1.9auxiliary clock 2 select control register (cgm_ac2_sc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 11.3.1.10auxiliary clock 2 divider configurat ion register (cgm_ac2_dc0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 11.3.1.11auxiliary clock 3 select control register (cgm_ac3_sc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15 11.3.1.12auxiliary clock 4 select control register (cgm_ac4_sc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 11.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 11.4.1 system clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 11.4.1.1system clock source selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17 11.4.1.2system clock disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17 11.4.1.3system clock dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17 11.4.2 auxiliary clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17 11.4.2.1auxiliary clock dividers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 11.4.3 functional description of dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 11.4.4 output clock multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 11.4.5 output clock division selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 chapter 12 clock monitor unit (cmu) 12.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.3 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.3.1 control status register (cmu_csr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.3.2 frequency display register (cmu_fdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12.3.3 high-frequency reference register a (cmu_hfrefr_a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.3.4 low-frequency reference register a (cmu_lfrefr_a). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.3.5 interrupt status register (cmu_isr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 12.3.6 measurement duration register (cmu_mdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12.4.1 xosc clock monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12.4.1.1system clock monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 12.4.1.2motor control clock monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 12.4.1.3flexray clock monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 12.4.1.4frequency meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9 chapter 13 cross-triggering unit (ctu) 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.3 ctu overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.4.1 interaction with other peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.4.2 trigger events features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.4.3 trigger generator subunit (tgs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.4.4 tgs in triggered mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.4.5 tgs in sequential mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13.4.6 tgs counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 13.5 scheduler subunit (su) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 13.5.1 adc commands list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9 13.5.2 adc commands list format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9 13.5.3 adc results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10 13.6 reload mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor viii 13.7 power safety mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11 13.7.1 mdis bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11 13.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11 13.8 interrupts and dma requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12 13.8.1 dma support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12 13.8.2 ctu faults and errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12 13.8.3 ctu interrupt/dma requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13 13.9 conversion time evaluate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 13.10 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 13.10.1trigger generator subunit input select ion register (tgsisr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18 13.10.2trigger generator subunit control register (tgscr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-20 13.10.3txcr - trigger x compare register (x = 0,...,7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-20 13.10.4tgs counter compare regist er (tgsccr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21 13.10.5tgs counter reload register (tgscrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21 13.10.6commands list control register 1 (clcr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-22 13.10.7commands list control register 2 (clcr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-23 13.10.8trigger handler control registers (thcr1 and thcr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-24 13.10.9commands list register x (x = 1,...,24) (clrx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-25 13.10.9.1clrx for adc single-conversion mode commands (cms = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-25 13.10.9.2clrx for adc dual-conversion mode commands (cms = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-25 13.10.9.3clrx for self-test commands (st1 = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-26 13.10.10cross triggering unit error flag register (ctuefr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-27 13.10.11cross triggering unit interrupt flag register (ctuifr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-27 13.10.12cross triggering unit interrupt/dma register (ctuir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-28 13.10.13control on time register (cotr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-28 13.10.14cross triggering unit control register (ctucr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-29 13.10.15cross triggering unit digital filter (ctudf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-30 13.10.16cross triggering unit expected value a (ctu_exp_a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-30 13.10.17cross triggering unit expected value b (ctu_exp_b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-31 13.10.18cross triggering unit counter range (ctu_cntrng) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-31 13.10.19fifo dma control register (fdcr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-32 13.10.20fifo control register (fcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-32 13.10.21fifo threshold (fth) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-34 13.10.22fifo status register (fst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-34 13.10.23fifo right aligned data x (x = 0,...,3) (frx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-36 13.10.24fifo signed left aligned data x (x = 0,...,3) (flx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-36 chapter 14 cyclic redundancy checker (crc) unit 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.1.1 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.4 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14.5.1 crc configuration register (crc_cfg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 14.5.2 crc input register (crc_inp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 14.5.3 crc current status register (crc_cstat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5 14.5.4 crc output register (crc_outp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 14.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 14.7 use cases and limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8 chapter 15 crossbar switch (xbar) 15.1 information specific to this device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.1.1 register availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.1.2 mpr reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.1.3 max_halt signal unavailable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.1.4 logical master ids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.1.5 master port allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor ix 15.1.6 slave port allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 15.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 15.2.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 15.2.3 limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 15.2.4 general operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.3 xbar registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 15.3.1 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 15.3.2 xbar register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 15.3.2.1master priority register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 15.3.2.2slave general purpose control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 15.3.2.3master general purpose control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11 15.3.3 coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12 15.4 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13 15.4.1 arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13 15.4.1.1arbitration during undefined length bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13 15.4.1.2fixed priority operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14 15.4.1.3round-robin priority operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14 15.4.2 priority assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 15.4.2.1context switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 15.4.2.2priority elevation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 15.4.3 master port functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 15.4.3.1general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 15.4.3.2master port decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16 15.4.3.3master port capture unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16 15.4.3.4master port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16 15.4.3.5master port state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17 15.4.4 slave port functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18 15.4.4.1general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18 15.4.4.2slave port muxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18 15.4.4.3slave port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-19 15.4.4.4slave port state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-19 15.5 initialization/applicat ion information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-24 15.6 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-24 15.6.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-24 15.6.2 master ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-24 15.6.2.1ignored accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-24 15.6.2.2terminated accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-24 15.6.2.3taken accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-25 15.6.2.4stalled accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-25 15.6.2.5error response terminated accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-25 15.6.3 slave ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-25 chapter 16 deserial serial peripheral interface (dspi) 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 16.1.3 dspi configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 16.1.3.1spi configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 16.1.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 16.1.4.1master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 16.1.4.2slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 16.1.4.3module disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 16.1.4.4external stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 16.1.4.5debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 16.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 16.2.1 pcs[0]/ss ? peripheral chip select/slave select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 16.2.2 pcs[1] - pcs[3] ? peripheral chip selects 1?3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 16.2.3 pcs[4] ? peripheral chip select 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 16.2.4 pcs[5]/pcss ? peripheral chip select 5/peripheral chip select strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6 16.2.5 pcs[6] - pcs[7] ? peripheral chip selects 6 - 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor x 16.2.6 sin ? serial input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6 16.2.7 sout ? serial output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6 16.2.8 sck ? serial clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6 16.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6 16.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6 16.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7 16.3.2.1dspi module configuration register (dspi_mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7 16.3.2.2dspi hardware configuration register (dspi_hcr) [cut2/3 only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10 16.3.2.3dspi transfer count register (dspi_tcr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11 16.3.2.4dspi clock and transfer attributes registers 0?3 (dspi_ctar0?dspi_ctar3) . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12 16.3.2.5dspi status register (dspi_sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17 16.3.2.6dspi dma/interrupt request select and enable register (dspi_rser) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-19 16.3.2.7dspi push tx fifo register (dspi_pushr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-21 16.3.2.8dspi pop rx fifo register (dspi_popr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-24 16.3.2.9dspi transmit fifo registers 0?4 (dspi_txfr0?dspi_txfr4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-24 16.3.2.10dspi receive fifo registers 0?4 (dspi_rxfr0?dspi_rxfr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-25 16.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-26 16.4.1 start and stop of dspi transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-27 16.4.2 serial peripheral interface (spi) configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-27 16.4.2.1master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-28 16.4.2.2slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-28 16.4.2.3fifo disable operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-28 16.4.2.4transmit first in first out (tx fifo) buffering mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-28 16.4.2.5receive first in first out (rx fifo ) buffering mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-29 16.4.3 dspi baud rate and clock delay generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-30 16.4.3.1baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-30 16.4.3.2pcs to sck delay (t csc ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-31 16.4.3.3after sck delay (t asc ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-31 16.4.3.4delay after transfer (tdt). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-31 16.4.3.5peripheral chip select strobe enable (pcss) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-32 16.4.4 transfer formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-33 16.4.4.1classic spi transfer format (cpha = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-33 16.4.4.2classic spi transfer format (cpha = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-34 16.4.4.3modified spi transfer format (mtfe = 1, cpha = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-35 16.4.4.4modified spi transfer format (mtfe = 1, cpha = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-38 16.4.4.5continuous selection format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-39 16.4.5 continuous serial communications clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-41 16.4.6 interrupts/dma requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-43 16.4.6.1end of queue interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-43 16.4.6.2transmit fifo fill interrupt or dma request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-44 16.4.6.3transfer complete interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-44 16.4.6.4transmit fifo underflow interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-44 16.4.6.5receive fifo drain interrupt or dma request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-44 16.4.6.6receive fifo overflow interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-44 16.4.7 power saving features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-44 16.4.7.1.stop mode (external stop mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-44 16.4.7.2module disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-45 16.5 initialization/applicat ion information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-45 16.5.1 how to manage dspi queues. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-45 16.5.2 switching master and slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-46 16.5.3 baud rate settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-46 16.5.4 delay settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-47 16.5.5 calculation of fifo pointer addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-47 16.5.5.1address calculation for the first-in entry and last-in entry in the tx fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-48 16.5.5.2address calculation for the first-in entry and last-in entry in the rx fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-48 chapter 17 e200z4d core complex overview 17.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 17.2.1 execution unit features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 17.2.1.1instruction unit features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xi 17.2.1.2integer unit features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.2.1.3load/store unit features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.2.2 l1 cache features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.2.3 memory management unit features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 17.2.4 exernal core complex interface features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 17.2.5 nexus 3+ features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 17.3 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6 17.3.1 register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6 17.3.1.1processor version register (pvr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8 17.3.1.2processor id register (pir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 17.3.1.3system version register (svr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 17.3.2 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 17.3.3 interrupts and exception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10 17.4 microarchitecture summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12 17.5 availability of detailed documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13 chapter 18 edma channel mux (dma_mux) 18.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.3.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 18.3.1.1channel configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 18.4 dma_mux request source slot mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 18.5 dma_mux trigger inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5 18.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5 18.6.1 dma channels with periodic triggering capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5 18.6.2 dma channels with no trigger ing capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 18.6.3 "always enabled" dma sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8 18.7 initialization/applicati on information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8 18.7.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8 18.7.2 enabling and configuring sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9 chapter 19 enhanced direct me mory access (edma) 19.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.2 memory map/register definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 19.2.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4 19.2.1.1edma control register (dmacr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4 19.2.1.2edma error status (dmaes). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7 19.2.1.3edma enable request low (dmaerql) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9 19.2.1.4edma enable error interrupt low (dmaeeil). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10 19.2.1.5edma set enable request (dmaserq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11 19.2.1.6edma clear enable request (dmacerq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12 19.2.1.7edma set enable error interrupt (dmaseei) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-13 19.2.1.8edma clear enable error interrupt (dmaceei) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-13 19.2.1.9edma clear interrupt request (dmacint) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-14 19.2.1.10edma clear error (dmacerr) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15 19.2.1.11edma set start bit (dmassrt) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-16 19.2.1.12edma clear done status (dmacdne) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-17 19.2.1.13edma interrupt request low (dmaintl) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-17 19.2.1.14edma error low (dmaerrl) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-18 19.2.1.15edma hardware request status low (dmahrsl) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-19 19.2.1.16edma channel n priority (dchprin), n = 0?15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-20
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xii 19.2.1.17transfer control descriptor (tcd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-21 19.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-32 19.3.1 edma microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-32 19.3.2 edma basic data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-33 19.3.3 edma performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-36 19.4 initialization/application info rmation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-39 19.4.1 edma initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-39 19.4.2 edma programming errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-40 19.4.3 edma arbitration mode considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-40 19.4.3.1fixed channel arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-40 19.4.3.2round-robin channel arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-40 19.4.4 edma transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-41 19.4.4.1single request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-41 19.4.4.2multiple requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-42 19.4.5 tcd status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-43 19.4.5.1minor loop complete. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-43 19.4.5.2active channel tcd reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-44 19.4.5.3preemption status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-44 19.4.6 channel linking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-45 19.4.7 dynamic programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-45 19.4.7.1dynamic priority changing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-46 19.4.7.2dynamic channel linking and dynamic scatter/gather . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-46 chapter 20 enhanced motor cont rol timer (etimer) 20.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 20.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20.3 external signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 20.3.1 tio[5:0] - timer input/outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 20.3.2 tai[2:0] - timer auxiliary inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 20.4 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5 20.4.1 module memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5 20.4.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6 20.4.3 timer channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6 20.4.3.1compare register 1 (comp1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6 20.4.3.2compare register 2 (comp2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6 20.4.3.3capture register 1 (capt1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6 20.4.3.4capture register 2 (capt2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7 20.4.3.5load register (load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7 20.4.3.6hold register (hold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7 20.4.3.7counter register (cntr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7 20.4.3.8control register 1 (ctrl1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8 20.4.3.9control register 2 (ctrl2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-11 20.4.3.10control register 3 (ctrl3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-13 20.4.3.11status register (sts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-14 20.4.3.12interrupt and dma enable register (intdma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-16 20.4.3.13comparator load register 1 (cmpld1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-17 20.4.3.14comparator load register 2 (cmpld2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-17 20.4.3.15compare and capture control register (ccctrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-17 20.4.3.16input filter register (filt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-20 20.4.4 watchdog timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-20 20.4.4.1watchdog time-out registers (wdtol and wdtoh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-21 20.4.5 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-21 20.4.5.1channel enable register (enbl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-21 20.4.5.2dma request select registers (dreq0, dreq1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22 20.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-23 20.5.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-23 20.5.2 counting modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-24 20.5.2.1stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-24 20.5.2.2count mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-24 20.5.2.3edge-count mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-24 20.5.2.4gated-count mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-25
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xiii 20.5.2.5quadrature-count mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-25 20.5.2.6signed-count mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-26 20.5.2.7triggered-count mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-26 20.5.2.8one-shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-26 20.5.2.9cascade-count mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-27 20.5.2.10pulse-output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-27 20.5.2.11fixed-frequency pwm mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-28 20.5.2.12variable-frequency pwm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-28 20.5.2.13usage of compare registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-29 20.5.2.14usage of compare load registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-29 20.5.2.15modulo counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-30 20.5.3 other features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-30 20.5.3.1redundant oflag checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-30 20.5.3.2loopback checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-30 20.5.3.3input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-30 20.5.3.4master/slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-31 20.5.3.5watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-31 20.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-31 20.7 dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-32 chapter 21 error correction status module (ecsm) 21.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 21.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 21.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 21.4 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 21.4.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 21.4.2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2 21.4.2.1processor core type (pct) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 21.4.2.2chip-defined platform revision (rev) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 21.4.2.3platform crossbar master configuration (plamc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 21.4.2.4platform crossbar slave configuration (plasc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 21.4.2.5ips on-platform module configuration (iopmc) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5 21.4.2.6miscellaneous reset status register (mrsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5 21.4.2.7miscellaneous user-defined control register (mudcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6 21.4.2.8platform ecc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7 21.4.2.9ecc configuration register (ecr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8 21.4.2.10ecc status register (esr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9 21.4.2.11ecc error generation register (eegr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-12 21.4.2.12platform flash memory ecc address register (pfear) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-15 21.4.2.13platform flash ecc master number register (pfemr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-16 21.4.2.14platform flash memory ecc attributes (pfeat) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-16 21.4.2.15platform flash memory ecc data registers (pfedrl and pfedrh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-17 21.4.2.16platform ram ecc address register (prear) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-19 21.4.2.17platform ram ecc syndrome register (presr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-19 21.4.2.18platform ram ecc master number register (premr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-22 21.4.2.19platform ram ecc attributes (preat) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-23 21.4.2.20platform ram ecc data registers (predrl and predrh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-24 chapter 22 fault collection and control unit (fccu) 22.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 22.1.1 glossary and acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 22.4 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4 22.5 register interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4 22.6 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4 22.6.1 fccu control register (fccu_ctrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 22.6.2 fccu ctrl key register (fccu_ctrlk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xiv 22.6.3 fccu configuration register (fccu_cfg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9 22.6.4 fccu cf configuration register (fccu_cf_cfg0..3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11 22.6.5 fccu ncf configuration register (fccu_ncf_cfg0..3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12 22.6.6 fccu cfs configuration register (fccu_cfs_cfg0..7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-13 22.6.7 fccu ncfs configuration register (fccu_ncfs_cfg0..7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-15 22.6.8 fccu cf status register (fccu_cfs0..3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-15 22.6.9 fccu cf key register (fccu_cfk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-17 22.6.10fccu ncf status register (fccu_ncfs0..3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-18 22.6.11fccu ncf key register (fccu_ncfk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-19 22.6.12fccu ncf enable register (fccu_ncfe0..3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-20 22.6.13fccu ncf time-out enable register (fccu_ncf_toe0..3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-21 22.6.14fccu ncf time-out register (fccu_ncf_to) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-21 22.6.15fccu cfg timeout register (fccu_cfg_to) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-22 22.6.16fccu status register (fccu_stat). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-23 22.6.17fccu cf fake register (fccu_cff). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-24 22.6.18fccu ncf fake register (fccu_ncff) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-24 22.6.19fccu irq status register (fccu_irq_stat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-25 22.6.20fccu irq enable register (fccu_irq_en) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-26 22.6.21fccu xtmr register (fccu_xtmr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-27 22.6.22fccu mcs register (fccu_mcs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-28 22.7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-29 22.7.1 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-29 22.7.2 fsm description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-29 22.7.3 self-checking capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-31 22.7.4 reset interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-32 22.7.5 fault priority scheme and nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-32 22.7.6 fault recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-33 22.7.7 wkup/nmi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-38 22.7.8 stcu interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-39 22.7.9 nvm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-40 22.7.10fccu_f interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-41 22.7.10.1dual-rail protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-42 22.7.10.2time switching protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-43 22.7.10.3bi-stable protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-44 22.7.11fault mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-45 chapter 23 flash memory 23.1 flash memory block (c90fl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23.1.1 c90fl block overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23.1.2 c90fl block features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 23.1.3 c90fl modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3 23.1.3.1c90fl user mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3 23.1.3.2stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3 23.1.4 c90fl block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3 23.1.5 c90fl flash memory functional description (user mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3 23.1.5.1c90fl read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4 23.1.5.2read while write (rww) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4 23.1.5.3c90fl program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 23.1.5.4software locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 23.1.5.5c90fl program suspend/resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 23.1.5.6c90fl erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7 23.1.5.7c90fl erase suspend/resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8 23.1.5.8c90fl shadow block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9 23.1.5.9c90fl reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9 23.1.5.10factory margin read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9 23.1.5.11array integrity self check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-10 23.1.5.12ecc logic check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-11 23.1.6 c90fl memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-12 23.1.6.1module configuration register (mcr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-13 23.1.6.2low/mid address space block locking register (lml) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-18 23.1.6.3high address space block locking register (hbl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-20
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xv 23.1.6.4secondary low/mid address space block locking register (sll). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-21 23.1.6.5low/mid address space block select register (lms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-22 23.1.6.6high address space block select register (hbs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-23 23.1.6.7address register (adr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-24 23.1.6.8bus interface unit 4 register (biu4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-25 23.1.6.9user test 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-25 23.1.6.10user test 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-27 23.1.6.11user test 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-27 23.1.6.12user multiple input signature registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-28 23.1.6.13nonvolatile private censorship password 0 register (nvpwd0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-31 23.1.6.14nonvolatile private censorship password 1 register (nvpwd1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-32 23.1.6.15nonvolatile system censoring information register (nvsci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-32 23.1.7 user option bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-33 23.1.8 test flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-34 23.2 dual-ported platform flash memory controller (pflash2p). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-35 23.2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-35 23.2.1.1features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-36 23.2.1.2block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-36 23.2.1.3general operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-38 23.2.2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-39 23.2.2.1platform flash configuration register 0 (pfcr0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-40 23.2.2.2platform flash access protection register (pfapr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-44 23.2.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-45 23.2.3.1basic interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-45 23.2.3.2read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-46 23.2.3.3write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-46 23.2.3.4flash error response operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-46 23.2.3.5line read buffers and prefetch operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-46 23.2.3.6wait-state emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-48 chapter 24 flexcan module 24.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1 24.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 24.1.2 flexcan module features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 24.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3 24.1.3.1normal mode (user or supervisor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3 24.1.3.2freeze mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3 24.1.3.3listen-only mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3 24.1.3.4loop-back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3 24.1.3.5module disable mode: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 24.1.3.6stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 24.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 24.2.1 can rx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 24.2.2 can tx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 24.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 24.3.1 flexcan memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5 24.3.2 message buffer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6 24.3.3 rx fifo structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9 24.3.4 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11 24.3.4.1module configuration register (mcr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11 24.3.4.2control register (ctrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-16 24.3.4.3free running timer (timer). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-19 24.3.4.4rx global mask (rxgmask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-20 24.3.4.5rx 14 mask (rx14mask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-21 24.3.4.6rx 15 mask (rx15mask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-21 24.3.4.7error counter register (ecr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-21 24.3.4.8error and status register (esr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-23 24.3.4.9interrupt masks 1 register (imask1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-26 24.3.4.10interrupt flags 1 register (iflag1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-27 24.3.4.11rx individual mask registers (rximr0?rximr31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-28 24.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-29
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xvi 24.4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-29 24.4.2 transmit process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-29 24.4.3 arbitration process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-30 24.4.4 receive process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-31 24.4.5 matching process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-32 24.4.6 data coherence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-33 24.4.6.1transmission abort mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-34 24.4.6.2message buffer deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-34 24.4.6.3message buffer lock mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-35 24.4.7 rx fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-36 24.4.7.1precautions when using global mask and individual mask registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-37 24.4.8 can protocol related features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-37 24.4.8.1remote frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-37 24.4.8.2overload frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-38 24.4.8.3time stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-38 24.4.8.4protocol timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-38 24.4.8.5arbitration and matching timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-41 24.4.9 modes of operation details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-42 24.4.9.1freeze mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-42 24.4.9.2module disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-42 24.4.9.3stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-43 24.4.10interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-43 24.4.11bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-44 24.5 initialization/applicat ion information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-45 24.5.1 flexcan initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-45 24.5.2 flexcan addressing and ram size configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-46 chapter 25 flexible motor control pulse widt h modulator module (flexpwm) 25.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1 25.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1 25.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1 25.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 25.1.4 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3 25.1.4.1module level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3 25.1.4.2pwm submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.2 external signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.2.1 pwma[n] and pwmb[n] - external pwm pair. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.2.2 pwmx[n] - auxiliary pwm signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.2.3 fault[n] - fault inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.2.4 ext_sync - external synchronization si gnal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5 25.2.5 ext_force - external output force signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5 25.2.6 exta[n] and extb[n] - alternate pwm control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5 25.2.7 out_trig0[n] and out_trig1[n] - output triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5 25.2.8 ext_clk - external clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5 25.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5 25.3.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5 25.3.2 pwm capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5 25.3.2.1center aligned pwms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5 25.3.2.2edge aligned pwms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7 25.3.2.3phase shifted pwms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7 25.3.2.4double switching pwms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9 25.3.2.5adc triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-10 25.3.2.6enhanced capture capabilities (e-capture) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12 25.3.2.7synchronous switching of multiple outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14 25.3.3 functional details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15 25.3.3.1pwm clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15 25.3.3.2register reload logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-16 25.3.3.3counter synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-17 25.3.3.4pwm generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-18 25.3.3.5output compare capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-19 25.3.3.6force out logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-19
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xvii 25.3.3.7independent or complementary channel operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-20 25.3.3.8deadtime insertion logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-21 25.3.3.9output logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-26 25.3.3.10e-capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-27 25.3.3.11fault protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-28 25.3.4 pwm generator loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-32 25.3.4.1load enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-32 25.3.4.2load frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-32 25.3.4.3reload flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-33 25.3.4.4reload errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-34 25.3.4.5initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-34 25.4 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-35 25.4.1 module memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-35 25.4.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-36 25.4.3 submodule registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-36 25.4.3.1counter register (cnt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-37 25.4.3.2initial count register (init) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-37 25.4.3.3control 2 register (ctrl2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-37 25.4.3.4control 1 register (ctrl1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-40 25.4.3.5value register 0 (val0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-42 25.4.3.6value register 1 (val1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-42 25.4.3.7value register 2 (val2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-43 25.4.3.8value register 3 (val3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-43 25.4.3.9value register 4 (val4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-44 25.4.3.10value register 5 (val5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-44 25.4.3.11output control register (octrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-45 25.4.3.12status register (sts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-46 25.4.3.13interrupt enable register (inten). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-47 25.4.3.14dma enable register (dmaen) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-48 25.4.3.15output trigger control register (tctrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-49 25.4.3.16fault disable mapping register (dismap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-49 25.4.3.17deadtime count registers (dtcnt0, dtcnt1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-50 25.4.3.18capture control x register (captctrlx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-50 25.4.3.19capture compare x register (captcmpx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-52 25.4.3.20capture value 0 register (cval0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-53 25.4.3.21capture value 0 cycle register (cval0cyc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-53 25.4.3.22capture value 1 register (cval1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-53 25.4.3.23capture value 1 cycle register (cval1cyc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-54 25.4.4 configuration registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-54 25.4.4.1output enable register (outen) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-54 25.4.4.2mask register (mask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-55 25.4.4.3software controlled output register (swcout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-55 25.4.4.4deadtime source select register (dtsrcsel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-57 25.4.4.5master control register (mctrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-59 25.4.5 fault channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-60 25.4.5.1fault control register (fctrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-60 25.4.5.2fault status register (fsts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-61 25.4.5.3fault filter register (ffilt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-62 25.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-63 25.6 dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-64 chapter 26 flexray communication controller 26.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 26.1.1 reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 26.1.2 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 26.1.3 color coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2 26.1.4 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2 26.1.5 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 26.1.6 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5 26.1.6.1disabled mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5 26.1.6.2normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xviii 26.2 external signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6 26.2.1 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7 26.2.1.1ca_rx ? receive data channel a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7 26.2.1.2ca_tx ? transmit data channel a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7 26.2.1.3ca_tr_en ? transmit enable channel a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7 26.2.1.4cb_rx ? receive data channel b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7 26.2.1.5cb_tx ? transmit data channel b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7 26.2.1.6cb_tr_en ? transmit enable channel b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7 26.2.1.7dbg3, dbg2, dbg1, dbg0 ? strobe signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7 26.3 controller host interface clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7 26.4 protocol engine clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-8 26.5 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-8 26.5.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-8 26.5.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-11 26.5.2.1register reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-12 26.5.2.2register write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-12 26.5.2.3module version register (fr_mvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-13 26.5.2.4module configuration register (fr_mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-14 26.5.2.5system memory base address register (fr_symbadr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-16 26.5.2.6strobe signal control register (fr_stbscr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-16 26.5.2.7message buffer data size register (fr_mbdsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-18 26.5.2.8message buffer segment size and util ization register (fr_mbssutr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-19 26.5.2.9pe dram access register (fr_pedrar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-19 26.5.2.10pe dram data register (fr_pedrdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-20 26.5.2.11protocol operation control register (fr_pocr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-21 26.5.2.12global interrupt flag and enable register (fr_gifer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-23 26.5.2.13protocol interrupt flag register 0 (fr_pifr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-25 26.5.2.14protocol interrupt flag register 1 (fr_pifr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-28 26.5.2.15protocol interrupt enable register 0 (fr_pier0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-29 26.5.2.16protocol interrupt enable register 1 (fr_pier1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-30 26.5.2.17chi error flag register (fr_chierfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-31 26.5.2.18message buffer interrupt vector regi ster (fr_mbivec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-34 26.5.2.19channel a status error counter register (fr_casercr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-34 26.5.2.20channel b status error counter register (fr_cbsercr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-35 26.5.2.21protocol status register 0 (fr_psr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-35 26.5.2.22protocol status register 1 (fr_psr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-37 26.5.2.23protocol status register 2 (fr_psr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-38 26.5.2.24protocol status register 3 (fr_psr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-40 26.5.2.25macrotick counter register (fr_mtctr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-41 26.5.2.26cycle counter register (fr_cyctr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-42 26.5.2.27slot counter channel a register (fr_sltctar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-42 26.5.2.28slot counter channel b register (fr_sltctbr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-43 26.5.2.29rate correction value register (fr_rtcorvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-43 26.5.2.30offset correction value register (fr_ofcorvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-44 26.5.2.31combined interrupt flag register (fr_cifr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-44 26.5.2.32system memory access time-out register (fr_symator) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-45 26.5.2.33sync frame counter register (fr_sfcntr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-46 26.5.2.34sync frame table offset register (fr_sftor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-47 26.5.2.35sync frame table configuration, control, status register (fr_sftccsr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-47 26.5.2.36sync frame id rejection filter register (fr_sfidrfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-49 26.5.2.37sync frame id acceptance filter value register (fr_sfidafvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-49 26.5.2.38sync frame id acceptance filter mask register (fr_sfidafmr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-50 26.5.2.39network management vector registers (fr_nmvr0?fr_nmvr5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-50 26.5.2.40network management vector length register (fr_nmvlr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-51 26.5.2.41timer configuration and control register (fr_ticcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-52 26.5.2.42timer 1 cycle set register (fr_ti1cysr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-53 26.5.2.43timer 1 macrotick offset register (fr_ti1mtor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-53 26.5.2.44timer 2 configuration register 0 (fr_ti2cr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-54 26.5.2.45timer 2 configuration register 1 (fr_ti2cr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-55 26.5.2.46slot status selection register (fr_sssr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-56 26.5.2.47slot status counter condition register (fr_ssccr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-57 26.5.2.48slot status registers (fr_ssr0?fr_ssr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-58 26.5.2.49slot status counter registers (fr_sscr0?fr_sscr3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-60
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xix 26.5.2.50mts a configuration register (fr_mtsacfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-61 26.5.2.51mts b configuration register (mtsbcfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-61 26.5.2.52receive shadow buffer index register (fr_rsbir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-62 26.5.2.53receive fifo system memory base address register (fr_rfsymbadr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-63 26.5.2.54receive fifo periodic timer register (fr_rfptr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-63 26.5.2.55receive fifo watermark and selection register (fr_rfwmsr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-64 26.5.2.56receive fifo start index register (fr_rfsir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-65 26.5.2.57receive fifo depth and size register (rfdsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-65 26.5.2.58receive fifo a read index register (fr_rfarir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-66 26.5.2.59receive fifo b read index register (fr_rfbrir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-66 26.5.2.60receive fifo fill level and pop count register (fr_rfflpcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-67 26.5.2.61receive fifo message id acceptance fi lter value register (fr_rfmidafvr) . . . . . . . . . . . . . . . . . . . . . . . . . 26-68 26.5.2.62receive fifo message id acceptance filter mask register (fr_rfmidafmr) . . . . . . . . . . . . . . . . . . . . . . . . . 26-68 26.5.2.63receive fifo frame id rejection filter value register (fr_rffidrfvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-69 26.5.2.64receive fifo frame id rejection filter mask register (fr_rffidrfmr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-69 26.5.2.65receive fifo range filter configuration register (fr_rfrfcfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-70 26.5.2.66receive fifo range filter control register (fr_rfrfctr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-70 26.5.2.67last dynamic transmit slot channel a register (fr_ldtxslar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-71 26.5.2.68last dynamic transmit slot channel b register (fr_ldtxslbr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-72 26.5.2.69protocol configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-72 26.5.2.70ecc error interrupt flag and enable register (fr_eeifer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-83 26.5.2.71ecc error report and injection control register (fr_eericr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-85 26.5.2.72ecc error report address register (fr_eerar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-86 26.5.2.73ecc error report data register (fr_eerdr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-86 26.5.2.74ecc error report code register (fr_eercr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-87 26.5.2.75ecc error injection address register (fr_eeiar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-88 26.5.2.76ecc error injection data register (fr_eeidr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-88 26.5.2.77ecc error injection code register (fr_eeicr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-89 26.5.2.78message buffer configuration, contro l, status registers (fr_mbccsrn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-89 26.5.2.79message buffer cycle counter filter registers (fr_mbccfrn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-91 26.5.2.80message buffer frame id registers (fr_mbfidrn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-93 26.5.2.81message buffer index registers (fr_mbidxrn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-93 26.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-93 26.6.1 message buffer concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-94 26.6.2 physical message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-94 26.6.2.1message buffer header field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-94 26.6.2.2message buffer data field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-95 26.6.3 message buffer types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-95 26.6.3.1individual message buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-95 26.6.3.2receive shadow buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-96 26.6.3.3receive fifo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-97 26.6.3.4message buffer configuration and control data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-99 26.6.3.5individual message buffer control data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-99 26.6.3.6receive shadow buffer configuration data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-100 26.6.3.7receive fifo control and configuration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-100 26.6.4 flexray memory area layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-101 26.6.4.1flexray memory area layout (fr_mcr[fam] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-101 26.6.4.2flexray memory area layout (fr_mcr[fam] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-101 26.6.4.3message buffer header area (fr_mcr[fam] = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-102 26.6.4.4message buffer header area (fr_mcr[fam] = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-103 26.6.4.5fifo message buffer header area (fr_mcr[fam] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-103 26.6.4.6message buffer data area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-103 26.6.4.7sync frame table area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-103 26.6.5 physical message buffer description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-103 26.6.5.1message buffer protection and data c onsistency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-103 26.6.5.2message buffer header field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-104 26.6.5.3message buffer data field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-111 26.6.6 individual message buffer functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-113 26.6.6.1individual message buffer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-113 26.6.6.2single transmit message buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-114 26.6.6.3receive message buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-123 26.6.6.4double transmit message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-129 26.6.7 individual message buffer search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-138
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xx 26.6.7.1message buffer cycle counter filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-140 26.6.7.2message buffer channel assignment cons istency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-140 26.6.7.3node related slot multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-141 26.6.7.4message buffer search error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-141 26.6.8 individual message buffer reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-141 26.6.8.1reconfiguration schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-141 26.6.9 receive fifos. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-142 26.6.9.1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-142 26.6.9.2fifo configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-143 26.6.9.3fifo periodic timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-143 26.6.9.4fifo reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-144 26.6.9.5fifo almost-full interrupt generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-144 26.6.9.6fifo overflow error generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-144 26.6.9.7fifo message access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-144 26.6.9.8fifo update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-145 26.6.9.9fifo filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-145 26.6.10channel device modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-148 26.6.10.1dual channel device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-148 26.6.10.2single channel device mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-149 26.6.11external clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-150 26.6.12sync frame id and sync frame deviation tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-151 26.6.12.1sync frame id table content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-152 26.6.12.2sync frame deviation table content. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-152 26.6.12.3sync frame id and sync frame deviation table setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-152 26.6.12.4sync frame id and sync frame deviation table generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-153 26.6.12.5sync frame table access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-154 26.6.13mts generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-154 26.6.14key slot transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-155 26.6.14.1key slot assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-155 26.6.14.2key slot transmission in poc:startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6-155 26.6.14.3key slot transmission in poc:normal active. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-15 5 26.6.15sync frame filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-156 26.6.15.1sync frame acceptance filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-156 26.6.15.2sync frame rejection filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-156 26.6.16strobe signal support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-157 26.6.16.1strobe signal assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-157 26.6.16.2strobe signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-157 26.6.17timer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-158 26.6.17.1absolute timer t1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-158 26.6.17.2absolute / relative timer t2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-158 26.6.18slot status monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-159 26.6.18.1channel status error counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-160 26.6.18.2protocol status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-161 26.6.18.3slot status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-161 26.6.18.4slot status counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-161 26.6.18.5message buffer slot status field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-162 26.6.19system bus access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-162 26.6.19.1system bus illegal address access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-163 26.6.19.2system bus access timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-163 26.6.19.3continue after system bus failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-163 26.6.19.4freeze after system bus failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-163 26.6.20interrupt support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-163 26.6.20.1individual interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-164 26.6.20.2combined interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-164 26.6.21lower bit rate support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-168 26.6.22pe data memory (pe dram). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-169 26.6.22.1pe dram read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-169 26.6.22.2pe dram write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-170 26.6.22.3pe dram write access limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-170 26.6.23chi lookup-table memory (chi lram). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-170 26.6.24memory content error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-171 26.6.24.1memory error types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-171 26.6.24.2memory error reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-171
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xxi 26.6.24.3memory error response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-174 26.6.25memory error injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-175 26.6.25.1chi lram error injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-175 26.6.25.2pe dram error injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-176 26.7 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-177 26.7.1 initialization sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-177 26.7.1.1module initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-177 26.7.1.2protocol initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-177 26.7.1.3chi lram initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-178 26.7.1.4pe dram initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-178 26.7.2 chi lram error injection out of poc:default config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 78 26.7.3 pe dram error injection out of poc:default config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26- 178 26.7.4 shut down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-178 26.7.5 number of usable message buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-179 26.7.6 protocol control command execution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-180 26.7.7 message buffer search on simple message buffer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-181 26.7.7.1simple message buffer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-181 26.7.7.2behavior in static segment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-182 26.7.7.3behavior in dynamic segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-182 chapter 27 frequency-modulated phase -locked loop (fmpll) 27.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1 27.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1 27.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1 27.4 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2 27.5 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2 27.5.1 control register (cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2 27.5.2 modulation register (mr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-5 27.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6 27.6.1 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6 27.6.2 progressive clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6 27.6.3 normal mode with frequency modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7 27.6.4 powerdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8 27.7 requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8 27.8 recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8 chapter 28 interrupt controller (intc) 28.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1 28.1.1 module overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1 28.1.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1 28.1.3 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2 28.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3 28.2.1 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3 28.2.1.1software vector mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3 28.2.1.2hardware vector mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3 28.2.2 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4 28.2.3 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4 28.2.4 factory test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4 28.3 external signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4 28.4 memory map/register definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4 28.4.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4 28.4.2 register information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5 28.4.3 intc block configuration register (intc_bcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6 28.4.4 intc current priority register for processor 0 (intc_cpr_prc0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-7 28.4.5 intc interrupt acknowledge register for processor 0 (intc_iackr_prc0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-8 28.4.6 intc end of interrupt register for processor 0 (intc_eoir_prc0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-9 28.4.7 intc software set/clear interrupt registers (intc_sscir0_3 - intc_sscir4_7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-9 28.4.8 intc priority select registers (intc_psr0_3 - intc_psr252_255). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-11
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xxii 28.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-12 28.5.1 interrupt request sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-12 28.5.1.1peripheral interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-12 28.5.1.2software settable interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-12 28.5.1.3unique vector for each interrupt request source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-13 28.5.2 priority management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-13 28.5.2.1current priority and preemption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-13 28.5.2.2lifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-14 28.5.3 handshaking with processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-14 28.5.3.1software vector mode handshaking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-14 28.5.3.2hardware vector mode handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-16 28.6 initialization/application info rmation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-17 28.6.1 initialization flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-17 28.6.2 interrupt exception handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-17 28.6.2.1software vector mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-18 28.6.2.2hardware vector mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-18 28.6.3 code compression?s impact on vector table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-19 28.6.4 isr, rtos, and task hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-19 28.6.5 order of execution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-20 28.6.6 priority ceiling protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-21 28.6.6.1elevating priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-21 28.6.6.2ensuring coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-22 28.6.7 selecting priorities according to request rates and deadli nes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-22 28.6.8 software settable interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-23 28.6.8.1scheduling a lower priority portion of an isr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-23 28.6.8.2scheduling an isr on another processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-23 28.6.9 lowering priority within an isr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-24 28.6.10negating an interrupt request outside of its isr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-24 28.6.10.1negating an interrupt request as a side effect of an isr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-24 28.6.10.2negating multiple interrupt requests in one isr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-24 28.6.10.3proper setting of interrupt request priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-24 28.6.11examining lifo contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-25 28.7 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-25 chapter 29 jtag controller (jtagc) 29.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 29.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 29.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 29.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 29.1.3.1reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 29.1.3.2ieee 1149.1-2001 defined test modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 29.1.3.3bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 29.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3 29.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3 29.2.2 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3 29.2.2.1tck - test clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3 29.2.2.2tdi - test data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3 29.2.2.3tdo - test data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3 29.2.2.4tms - test mode select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3 29.2.2.5jcomp - jtag compliancy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4 29.3 register definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4 29.3.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4 29.3.1.1instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4 29.3.1.2bypass register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4 29.3.1.3device identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4 29.3.1.4test_ctrl register (cut2/3 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6 29.3.1.5censor_ctrl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6 29.3.1.6boundary scan register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7 29.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7 29.4.1 jtagc reset configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7 29.4.2 ieee 1149.1-2001 (jtag) test access port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xxiii 29.4.3 tap controller state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-8 29.4.3.1enabling the tap controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-10 29.4.3.2selecting an ieee 1149.1-2001 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-10 29.4.4 jtagc block instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-10 29.4.4.1idcode instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-11 29.4.4.2sample/preload instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-11 29.4.4.3sample instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-11 29.4.4.4extest ? external test instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-11 29.4.4.5enable_censor_ctrl instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-12 29.4.4.6access_aux_tap_x instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-12 29.4.4.7bypass instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-12 29.4.5 boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-12 29.5 initialization/applicat ion information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-12 chapter 30 memory protection unit (mpu) 30.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-1 30.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-1 30.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-3 30.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-4 30.5 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-4 30.6 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-4 30.6.1 mpu control/error status register (mpu_cesr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-6 30.6.2 mpu error address register, slave port n (mpu_earn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-6 30.6.3 mpu error detail register, slave port n (mpu_edrn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-7 30.6.4 mpu region descriptor n (mpu_rgdn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-8 30.6.4.1mpu region descriptor n, word 0 (mpu_rgdn.word0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-8 30.6.4.2mpu region descriptor n, word 1 (mpu_rgdn.word1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-9 30.6.4.3mpu region descriptor n, word 2 (mpu_rgdn.word2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-9 30.6.4.4mpu region descriptor n, word 3 (mpu_rgdn.word3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-12 30.6.5 mpu region descriptor alternate access control n (mpu_rgdaacn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-13 30.7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-15 30.7.1 access evaluation macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-15 30.7.1.1access evaluation ? hit determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-16 30.7.1.2access evaluation ? privilege violation determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-17 30.7.2 putting it all together and ahb error terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-18 30.8 initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-19 30.9 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-19 chapter 31 lin controller (linflexd) 31.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-1 31.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-1 31.2.1 lin mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2 31.2.2 uart mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2 31.3 the lin protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3 31.3.1 dominant and recessive logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3 31.3.2 lin frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3 31.3.3 lin header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4 31.3.3.1break field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4 31.3.3.2sync pattern. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4 31.3.4 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5 31.3.4.1data field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5 31.3.4.2identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5 31.3.4.3checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5 31.4 linflexd and software intervention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-6 31.5 summary of operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-6 31.6 controller-level operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-7 31.6.1 initialization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-7 31.6.2 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-8
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xxiv 31.6.3 sleep (low-power) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-8 31.7 lin modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-8 31.7.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-8 31.7.1.1lin header transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-8 31.7.1.2data transmission (transceiver as publisher) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-9 31.7.1.3data reception (transceiver as subscriber) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-9 31.7.1.4error detection and handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-9 31.7.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-9 31.7.2.1data transmission (transceiver as publisher) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-10 31.7.2.2data reception (transceiver as subscriber) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-10 31.7.2.3data discard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-11 31.7.2.4error detection and handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-11 31.7.2.5valid header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-12 31.7.2.6valid message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-12 31.7.2.7overrun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-12 31.7.3 slave mode with identifier filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-12 31.7.3.1filter submodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-12 31.7.3.2identifier filter submode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-13 31.7.4 slave mode with automatic resynchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-14 31.7.4.1automatic resynchronization method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-15 31.7.4.2deviation error on the sync field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-15 31.8 test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-16 31.8.1 loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-16 31.8.2 self test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-16 31.9 uart mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-17 31.9.1 data frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-17 31.9.1.18-bit data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-17 31.9.1.29-bit data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-17 31.9.1.316-bit data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-18 31.9.1.417-bit data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-18 31.9.2 buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-18 31.9.3 uart transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-19 31.9.4 uart receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-20 31.10 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-22 31.10.1lin control register 1 (lincr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-23 31.10.2lin interrupt enable register (linier) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-26 31.10.3lin status register (linsr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-28 31.10.4lin error status register (linesr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-31 31.10.5uart mode control register (uartcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-32 31.10.6uart mode status register (uartsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-35 31.10.7lin timeout control status register (lintcsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-37 31.10.8lin output compare register (linocr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-38 31.10.9lin timeout control register (lintocr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-39 31.10.10lin fractional baud rate register (linfbrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-40 31.10.11lin integer baud rate register (linibrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-40 31.10.12lin checksum field register (lincfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-41 31.10.13lin control register 2 (lincr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-42 31.10.14buffer identifier register (bidr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-43 31.10.15buffer data register least significant (bdrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-44 31.10.16buffer data register most significant (bdrm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-45 31.10.17identifier filter enable register (ifer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-46 31.10.18identifier filter match index (ifmi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-47 31.10.19identifier filter mode register (ifmr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-48 31.10.20identifier filter control registers (ifcr0?ifcr15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-48 31.10.21global control register (gcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-49 31.10.22uart preset timeout register (uartpto) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-51 31.10.23uart current timeout register (uartcto) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-51 31.10.24dma tx enable register (dmatxe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-52 31.10.25dma rx enable register (dmarxe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-53 31.11 dma interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-53 31.11.1master node, tx mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-54 31.11.2master node, rx mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-57 31.11.3slave node, tx mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-59
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xxv 31.11.4slave node, rx mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-62 31.11.5uart node, tx mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-64 31.11.6uart node, rx mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-67 31.11.7use cases and limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-70 31.12 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-71 31.12.18-bit timeout counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-71 31.12.1.1lin timeout mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-71 31.12.1.2output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-72 31.12.2interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-72 31.12.3fractional baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-73 31.13 programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-74 31.13.1master node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-75 31.13.2slave node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-76 31.13.3extended frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-79 31.13.4timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-80 31.13.5uart mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-80 chapter 32 mode entry module (mc_me) 32.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-1 32.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-1 32.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-3 32.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-3 32.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-4 32.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-4 32.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-5 32.3.2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-12 32.3.2.1global status register (me_gs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-13 32.3.2.2mode control register (me_mctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-15 32.3.2.3mode enable register (me_me) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-16 32.3.2.4interrupt status register (me_is) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-17 32.3.2.5interrupt mask register (me_im). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-19 32.3.2.6invalid mode transition status regi ster (me_imts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-20 32.3.2.7debug mode transition status register (me_dmts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-21 32.3.2.8reset mode configuration register (me_reset_mc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-24 32.3.2.9test mode configuration register (me_test_mc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-24 32.3.2.10safe mode configuration register (me_safe_mc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-25 32.3.2.11drun mode configuration register (me_drun_mc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-25 32.3.2.12run0?3 mode configuration registers (me_run0?3_mc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-26 32.3.2.13halt0 mode configuration register (me_halt0_mc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-26 32.3.2.14stop0 mode configuration register (me_stop0_mc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-27 32.3.2.15peripheral status register 0 (me_ps0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-28 32.3.2.16peripheral status register 1 (me_ps1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-29 32.3.2.17peripheral status register 2 (me_ps2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-29 32.3.2.18run peripheral configuration registers (me_run_pc0?7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-30 32.3.2.19low-power peripheral configuration registers (me_lp_pc0?7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-31 32.3.2.20peripheral control registers (me_pctl0?143) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-31 32.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-32 32.4.1 mode transition request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-32 32.4.2 mode details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-34 32.4.2.1reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-34 32.4.2.2drun mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-34 32.4.2.3safe mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-34 32.4.2.4test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-35 32.4.2.5run0?3 modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-36 32.4.2.6halt0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-36 32.4.2.7stop0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-37 32.4.3 mode transition process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-37 32.4.3.1target mode request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-38 32.4.3.2target mode configuration loading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-38 32.4.3.3peripheral clocks disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-39 32.4.3.4processor low-power mode entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-40
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xxvi 32.4.3.5processor and system memory clock disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-40 32.4.3.6clock sources switch-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-40 32.4.3.7flash module switch-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-40 32.4.3.8pad outputs-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-41 32.4.3.9peripheral clocks enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-41 32.4.3.10processor and memory clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-41 32.4.3.11processor low-power mode exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-41 32.4.3.12system clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-41 32.4.3.13pad switch-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-42 32.4.3.14clock sources (with no dependencies) switch-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-42 32.4.3.15clock sources (with dependencies) switch-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-43 32.4.3.16flash switch-off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-43 32.4.3.17current mode update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-43 32.4.4 protection of mode configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-46 32.4.5 mode transition interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-46 32.4.5.1invalid mode configuration interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-46 32.4.5.2invalid mode transition interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-47 32.4.5.3safe mode transition interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-48 32.4.5.4mode transition complete interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-48 32.4.6 peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-48 32.4.7 application example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-49 chapter 33 nexus crossbar slave port data trace module (nxss) [cut2/3 only] 33.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-1 33.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-1 33.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2 33.4 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2 33.4.1 rules for output messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2 33.4.2 auxiliary port arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2 33.5 nxss programmer model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-3 33.5.1 development control registers (dc1 and dc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-3 33.5.2 watchpoint trigger register (wt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-5 33.5.3 data trace control register (dtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-5 33.5.4 data trace start address registers 1 and 2 (dtsa1 and dtsa2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-7 33.5.5 data trace end address registers 1 and 2 (dtea1 and dtea2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-7 33.5.6 breakpoint / watchpoint control register 1 (bwc1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-8 33.5.7 breakpoint / watchpoint control register 2 (bwc2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-9 33.5.8 breakpoint/watchpoint address registers 1 and 2 (bwa1 and bwa2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-10 33.5.9 unimplemented registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-10 33.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-10 33.6.1 tcodes supported by nxss_0 and nxss_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-10 33.6.2 data trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-12 33.6.3 data trace messaging (dtm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-12 33.6.4 dtm message formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-12 33.6.4.1data write and data read messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-12 33.6.4.2dtm overflow error messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-12 33.6.4.3data trace synchronization messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-13 33.6.5 dtm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-14 33.6.5.1enabling data trace messaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-14 33.6.5.2dtm queueing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-15 33.6.5.3relative addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-15 33.6.5.4data trace windowing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-15 33.7 watchpoint support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-15 33.7.1 watchpoint messaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-15 33.7.2 watchpoint error message. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-16
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xxvii chapter 34 nexus port controller (npc) 34.1 information specific to this device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-1 34.1.1 parameter values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-1 34.1.2 unavailable features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-1 34.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-1 34.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-2 34.2.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-2 34.2.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-3 34.2.3.1reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-3 34.2.3.2disabled-port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-3 34.2.3.3full-port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-3 34.2.3.4reduced-port mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-3 34.2.3.5censored mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-3 34.2.3.6nexus double data rate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-4 34.3 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-4 34.3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-4 34.3.2 detailed signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-4 34.3.2.1evto - event out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-5 34.3.2.2jcomp - jtag compliancy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-5 34.3.2.3mdo - message data out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-5 34.3.2.4mseo_b - message start/end out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-5 34.3.2.5tck - test clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-5 34.3.2.6tdi - test data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-5 34.3.2.7tdo - nexus test data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-6 34.3.2.8tms - test mode select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-6 34.3.2.9rdy ? data ready for transfer (on cut2/3 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-6 34.4 register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-6 34.4.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-6 34.4.1.1bypass register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-7 34.4.1.2instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-7 34.4.1.3nexus device id register (did) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-7 34.4.1.4port configuration register (pcr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-8 34.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-10 34.5.1 npc reset configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-10 34.5.2 auxiliary output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-10 34.5.2.1output message protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-11 34.5.2.2output messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-11 34.5.2.3rules of message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-12 34.5.3 ieee 1149.1-2001 (jtag) tap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-13 34.5.3.1enabling the npc tap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-14 34.5.3.2retrieving device idcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-16 34.5.3.3loading nexus-enable instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-16 34.5.3.4selecting a nexus client register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-17 34.5.4 nexus jtag port sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-18 34.5.5 mcko . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-18 34.5.6 evto sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-18 34.5.7 nexus reset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-18 34.5.8 system clock locked indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-18 34.6 initialization/applicat ion information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-19 34.6.1 accessing npc tool-mapped regist ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-19 chapter 35 oscillators 35.1 ircosc 16 mhz internal rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-1 35.2 xosc external oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-2 35.2.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-2 35.2.2 nvm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-3 35.2.3 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-3
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xxviii chapter 36 periodic interrupt timer (pit) 36.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-1 36.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-1 36.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-1 36.2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-2 36.3 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-2 36.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-2 36.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-3 36.3.2.1pit module control register (pitmcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-3 36.3.2.2timer load value register (ldval) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-3 36.3.2.3current timer value register (cval) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-4 36.3.2.4timer control register (tctrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-5 36.3.2.5timer flag register (tflg). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-6 36.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-7 36.4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-7 36.4.1.1timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-7 36.4.1.2debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-8 36.4.2 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-8 36.5 initialization and application information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-9 36.5.1 example configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-9 chapter 37 peripheral bridge (pbridge) 37.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-1 37.2 block interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-1 37.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-1 37.4 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-2 37.4.1 register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-2 37.4.2 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-2 37.4.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-3 37.4.3.1master protection registers (mprot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-3 37.4.3.2peripheral access control registers (pacr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-4 37.4.3.3off-platform peripheral access control registers (opacr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-5 37.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-7 37.5.1 access support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-7 37.5.1.1peripheral write buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-7 37.5.1.2read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-7 37.5.1.3write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-7 37.5.2 general operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-7 chapter 38 power control unit (mc_pcu) 38.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-1 38.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-1 38.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-2 38.2 external signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-2 38.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-2 38.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-2 38.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-3 38.3.2.1power domain status register (pcu_pstat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-3 chapter 39 power management unit (pmu) 39.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-1 39.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-1 39.3 high-power regulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-2
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xxix 39.4 high- and low-voltage detectors (hvd, lvd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-3 39.4.1 current comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-3 39.5 power-up and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-4 39.6 built in self-test (bist) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-4 39.7 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-5 39.7.1 pmuctrl status register (pmuctrl_status) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-6 39.7.2 pmuctrl control register (pmuctrl_ctrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-7 39.7.3 pmuctrl mask fault register (pmuctr l_maskf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-7 39.7.4 pmuctrl fault monitor register (pmuctrl_fault) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-8 39.7.5 pmuctrl interrupt request status register (pmuctrl_irqs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-9 39.7.6 pmuctrl interrupt request enable register (pmuctrl_irqe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-11 chapter 40 register protection (reg_prot) 40.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-1 40.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-1 40.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-1 40.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-2 40.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-2 40.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-2 40.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-3 40.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-4 40.3.2.1module registers (mr0-6143) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-4 40.3.2.2module register and set soft lock bit (lmr0-6143) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-4 40.3.2.3soft lock bit register (slbr0-1535) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-4 40.3.2.4global configuration regi ster (gcr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-5 40.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-6 40.4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-6 40.4.2 change lock settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-6 40.4.2.1change lock settings directly via area #4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-7 40.4.2.2enable locking via mirror module s pace (area #3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-8 40.4.2.3write protection for locking bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-9 40.4.3 access errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-9 40.5 initialization/application info rmation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-10 40.5.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-10 40.5.2 writing c code using the register prot ection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-10 40.6 pxs20 registers under protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-11 chapter 41 reset generation module (mc_rgm) 41.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-1 41.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-1 41.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-2 41.1.3 reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-3 41.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-4 41.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-4 41.3.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-7 41.3.1.1functional event status register (rgm_fes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-8 41.3.1.2destructive event status register (rgm_des) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-10 41.3.1.3functional event reset disable register (rgm_ferd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-12 41.3.1.4destructive event reset disable register (rgm_derd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-14 41.3.1.5functional event alternate request register (rgm_fear). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-15 41.3.1.6functional event short sequence register (rgm_fess) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-16 41.3.1.7functional bidirectional reset enable register (rgm_fbre) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-18 41.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-20 41.4.1 reset state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-20 41.4.1.1phase0 phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-21 41.4.1.2phase1 phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-22 41.4.1.3phase2 phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-22 41.4.1.4phase3 phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-22
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xxx 41.4.1.5idle phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-22 41.4.2 destructive resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-22 41.4.3 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-23 41.4.4 functional resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-23 41.4.5 alternate event generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-24 41.4.6 boot mode capturing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-25 chapter 42 self-test control unit (stcu) 42.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-1 42.1.1 acronyms, abbreviations, and terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-1 42.1.2 the safety integrity subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-2 42.1.3 integrity sw operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-4 42.1.3.1reported errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-4 42.1.3.2no reported errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-4 42.2 stcu main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-5 42.3 block diagram and components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-5 42.4 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-6 42.4.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-6 42.4.2 register conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-8 42.4.3 detailed register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-8 42.4.3.1stcu sk code register (stcu_skc) [cut2/3 only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-8 42.4.3.2stcu configuration register (stcu_cf g) [cut1 only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-9 42.4.3.3stcu error register (stcu_err) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-9 42.4.3.4stcu error key register (stcu_errk) [cut2/3 only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-11 42.4.3.5stcu lbist status register (stcu_lbs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-12 42.4.3.6stcu lbist end flag register (stcu_lbe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-13 42.4.3.7stcu mbist status low register (stcu_mbsl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-13 42.4.3.8stcu mbist status high register (stcu_mbsh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-14 42.4.3.9stcu mbist end flag low register (stcu_mbel). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-15 42.4.3.10stcu mbist end flag high register (stcu_mbeh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-15 42.4.3.11stcu lbist misr expected low register (stcu_lb_misrel) [cut2/3 only]. . . . . . . . . . . . . . . . . . . . . . . . . . . 42-16 42.4.3.12stcu lbist misr expected high regi ster (stcu_lb_misreh) [cut2/3 only] . . . . . . . . . . . . . . . . . . . . . . . . . . 42-17 42.4.3.13stcu lbist misr read low register (stcu_lb_misrrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-17 42.4.3.14stcu lbist misr read high register (stcu_lb_misrrh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-18 42.5 lbist partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-18 42.6 mbist partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-22 42.7 self-test bypass and mbist-only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-23 chapter 43 semaphore unit (sema4) 43.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-1 43.1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-1 43.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-2 43.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-3 43.2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-3 43.3 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-3 43.3.1 semaphores gate n register (sema4_gate n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-4 43.3.2 semaphores processor n irq notification enable (sema4_cp{0,1}ine) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-5 43.3.3 semaphores processor n irq notification (sema4_cp{0,1}ntf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43- 5 43.3.4 semaphores (secure) reset gate n (sema4_rstgt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-6 43.3.5 semaphores (secure) reset ir q notification (sema4_rstntf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-8 43.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-10 43.4.1 semaphore usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-12 43.5 initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-12 43.6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-12 43.7 dma requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-14
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xxxi chapter 44 sine wave generator (swg) 44.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-1 44.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-1 44.3 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-1 44.3.1 swg control register (swg_ctrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-1 44.3.2 swg status register (swg_stat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-3 44.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-4 44.4.1 swg operation after a power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-4 44.4.2 output sine wave frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-4 44.4.3 output sine wave amplitude. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-4 44.5 initialization / application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-4 44.5.1 changing the output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-4 44.5.2 preserving the swg_ctrl data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-5 chapter 45 software watchdog timer (swt) 45.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-1 45.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-1 45.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-1 45.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-1 45.2 external signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-1 45.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-1 45.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-2 45.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-2 45.3.2.1swt control register (swt_cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-2 45.3.2.2swt interrupt register (swt_ir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-4 45.3.2.3swt time-out register (swt_to) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-4 45.3.2.4swt window register (swt_wn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-5 45.3.2.5swt service register (swt_sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-5 45.3.2.6swt counter output register (swt_co) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-6 45.3.2.7swt service key register (swt_sk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-7 45.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-7 chapter 46 static ram (sram) 46.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-1 46.2 sram operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-1 46.3 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-1 46.4 sram ecc mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-1 46.4.1 access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-2 46.4.2 reset effects on sram accesses on cut1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-3 46.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-3 46.6 initialization and application informations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-3 chapter 47 system integration unit lite (siul) 47.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-1 47.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-1 47.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-3 47.3.1 register protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-3 47.4 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-3 47.4.1 detailed signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-4 47.4.1.1general-purpose i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-4 47.4.1.2external interrupt request input pins (eirq[0:31]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-4 47.5 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-4 47.5.1 siul memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-4
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xxxii 47.5.2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-5 47.5.2.1mcu id register 1 (midr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-6 47.5.2.2mcu id register 2 (midr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-7 47.5.2.3interrupt status flag register (isr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-7 47.5.2.4interrupt request enable register (irer). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-8 47.5.2.5interrupt rising-edge event enable register (ireer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-9 47.5.2.6interrupt falling-edge event enable register (ifeer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-9 47.5.2.7interrupt filter enable register (ifer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-10 47.5.2.8pad configuration registers (pcr0?pcr132) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-10 47.5.2.9pad selection for multiplexed inputs (psmi0_3?psmi40_43) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-12 47.5.2.10gpio pad data output registers (gpdo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-13 47.5.2.11gpio pad data input registers (gpdi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-14 47.5.2.12parallel gpio pad data out register (pgpdo0?pgpdo3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-15 47.5.2.13parallel gpio pad data in register (pgpdi0?pgpdi3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-15 47.5.2.14masked parallel gpio pad data out register (mpgpdo0?mpgpdo6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-17 47.5.2.15interrupt filter maximum counter register (ifmc0?ifmc31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-18 47.5.2.16interrupt filter clock prescaler register (ifcpr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-18 47.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-19 47.6.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-19 47.6.2 pad control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-19 47.6.3 general purpose input and output pads (gpio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-20 47.6.4 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-20 47.6.4.1external interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-21 47.7 pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-21 chapter 48 system status and conf iguration module (sscm) 48.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-1 48.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-1 48.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-1 48.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-2 48.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-2 48.3 memory map/register definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-2 48.3.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-3 48.3.1.1system status register (status). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-3 48.3.1.2system memory and id register (memconfig) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-4 48.3.1.3error configuration (error) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-5 48.3.1.4debug status port register (debugport) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-6 48.3.1.5password comparison registers (pwcmph and pwcmpl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-7 48.3.1.6dpm boot register (dpmboot). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-9 48.3.1.7boot key register (dpmkey) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-10 48.3.1.8user option status register (uops). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-11 48.3.1.9sscm control register (sctr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-11 48.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-12 48.5 initialization/application info rmation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-12 48.5.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-12 chapter 49 system timer module (stm) 49.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-1 49.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-1 49.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-1 49.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-1 49.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-1 49.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-1 49.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-1 49.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-2 49.3.2.1stm control register (stm_cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-2 49.3.2.2stm count register (stm_cnt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-3 49.3.2.3stm channel control register (stm_ccrn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-4
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xxxiii 49.3.2.4stm channel interrupt register (stm_cirn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-4 49.3.2.5stm channel compare register (stm_cmpn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-5 49.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-6 chapter 50 temperature sensor (tsens) 50.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-1 50.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-1 50.3 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-1 50.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-1 50.5 obtaining the device temperature using tsens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-2 50.5.1 tsens calibration constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-2 50.5.2 equations for converting tsens voltage to device temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-2 chapter 51 wakeup unit (wkpu) 51.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51-1 51.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51-1 51.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51-1 51.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51-2 51.3 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51-2 51.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51-2 51.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51-2 51.3.2.1nmi status flag register (nsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51-2 51.3.2.2nmi configuration register (ncr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51-3 51.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51-5 51.4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51-5 51.4.2 non-maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51-5 51.4.2.1nmi management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51-6 appendix a revision history
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xxxiv
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xxxv preface overview the primary objective of this document is to define the functionality of the pxs20 microcontroller for use by software and hardware developers. the information in this book is subjec t to change without notic e, as described in the disclaimers on the title page. as with any technical documentation, it is the reader?s responsibil ity to be sure he or she is using the most recent version of the documentation. to locate any published errata or updates for th is document, visit the freescale web site at http://www.freescale.com/. audience this manual is intended for system software and hardware developers and applications programmers who want to develop products with the pxs20 device. it is assumed that the reader understands operating systems, microprocessor syst em design, basic principles of software and hardware, and basic details of the power architecture. organization this document includes chapters that describe: ? the microcontroller as a whole ? the functionality of the indivi dual modules on the microcontroller when the microcontroller is specified as ?pxs20,? the re ader is instructed to appl y this information to all of the microcontrollers specified on the front cover of this manual, unl ess individual devi ce-specific details are provided in that chapter. the following summary provides a brief description of the majo r sections of this manual: ? chapter 1, introduction , includes general descrip tions of the modules and fe atures incorporated in the device while focusing on new features. ? chapter 2, memory map , provides a high-level listi ng of the pxs20 memory map. ? chapter 3, signal description , summarizes the external signal functions, their static electrical characteristics, and pad confi guration settings for the pxs20. ? chapter 4, operating modes , describes the operating modes for the pxs20. ? chapter 5, device boot modes , describes the boot modes for the pxs20. ? chapter 6, device security , describes the censorship mechanism implemented on the pxs20. ? chapter 7, functional safety , describes a set of features to support using the pxs20 for applications that need to fulfil l functional safety requirements.
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xxxvi ? chapter 8, boot assist module (bam) , describes the bam, whic h contains the mcu boot program code supporting the differen t booting modes for this device. ? chapter 9, analog-to-digital converter (adc) , describes the adc module implemented on the pxs20. ? chapter 10, clock architecture , describes the various clock sour ces that are available on the pxs20. ? chapter 11, clock generation module (mc_cgm) , describes the clock generation module (mc_cgm), which generates reference clocks for all the on-chip modules. ? chapter 12, clock monitor unit (cmu) , describes the module that m onitors the external crystal oscillator clock, detects whether the pll leav es an upper or lower frequency boundary, and measures the frequency of the ircosc versus a known reference clock xosc. ? chapter 13, cross-triggering unit (ctu) , describes the ctu block, which converts the events generated by the adc, the pwm, and various timers into adc conversion requests. ? chapter 14, cyclic redundancy checker (crc) unit , describes the computing unit that is dedicated to the computation of crc, thus off-loading the cpu. ? chapter 15, crossbar switch (xbar) , describes the multi-port axbs crossbar switch that supports simultaneous connections between the master and slave ports. ? chapter 16, deserial serial peripheral interface (dspi) , describes the serial peripheral interface (spi) block, which provides a s ynchronous serial interface for communication between the pxs20 and external devices. ? chapter 17, e200z4d core complex overview , describes the organization of the e200z4d power processor core and gives an over view of the programming models as they are implemented on the device. ? chapter 18, edma channel mux (dma_mux) , describes the dma multiplexer block implemented on the pxs20. ? chapter 19, enhanced direct memory access (edma) , describes the enhanced dma controller implemented on the pxs20. ? chapter 20, enhanced motor control timer (etimer) , describes a set of modules containing six identical counter/timer channels. ? chapter 21, error correction status module (ecsm) , describes the ecsm block, which provides monitoring and control functions to report memory errors and apply error-correcting code (ecc) implementations. ? chapter 22, fault collection and control unit (fccu) , describes a programmable redundant hardware channel that collects errors and leads the device in a controlled wa y to a safe state when a failure is present in the device. ? chapter 23, flash memory , describes the flash memory block and the flash memory controller. ? chapter 24, flexcan module , describes the flexcan module, a communication controller implementing the can protocol according to bosch sp ecification version 2.0b and iso standard 11898. ? chapter 25, flexible motor control pu lse width modulator module (flexpwm) , describes the pulse width modulator (pwm) module.
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xxxvii ? chapter 26, flexray communication controller , describes the flexray communicati on controller on the pxs20 that implements the flexray communications system protocol specification, version 2.1 rev a . ? chapter 27, frequency-modulated phase-locked loop (fmpll) , describes the features and function of the fmpll module. ? chapter 28, interrupt controller (intc) , summarizes the software a nd hardware interrupts for the pxs20 device. ? chapter 29, jtag controller (jtagc) , describes configuration and operation of the joint test action group (jtag) controller implementation. it describes t hose items required by the ieee ? 1149.1 standard and provides additional information sp ecific to the device. fo r internal details and sample applications, see the ieee 1149.1 document. ? chapter 30, memory protection unit (mpu) , describes the block that provides hardware access control for all memory references generated in the pxs20. ? chapter 31, lin controller (linflexd) , describes the linflexd (l ocal interconnect network flexible with dma support) contro ller, which provides uart capabili ties as well as an interface to a lin network. ? chapter 32, mode entry module (mc_me) , describes the module that controls the pxs20 mode and mode transition sequences in all functional states. ? chapter 33, nexus crossbar slave port data trace module (nxss) [cut2/3 only] , describes the modules on cut2/3 of the pxs20 that provide th e data trace and watchpoi nt messaging features defined in the class 3 ieee-isto 5001-2003 standard. ? chapter 34, nexus port controller (npc) , describes the nexus development interface (ndi) block, which provides real-time de velopment support capabilities for the pxs20 in compliance with the ieee-isto 5001-2003 standard. ? chapter 35, oscillators , describes the internal rc oscillator (ircosc) and external oscillator (xosc). ? chapter 36, periodic interrupt timer (pit) , describes an array of timers that can be used to initiate interrupts and trigger dma channels. ? chapter 37, peripheral bridge (pbridge) , describes the interface between the system bus and lower bandwidth peripherals via the aips bridge. ? chapter 38, power control unit (mc_pcu) , describes the controls for the bridge that maps the pmc peripheral to the mc_pcu address space. ? chapter 39, power management unit (pmu) , describes the on-chip m odule that provides voltage regulation for the pxs20. ? chapter 40, register protection (reg_prot) , describes the module that offers a mechanism to protect defined memory-mapped address locati ons in a module under protection from being written. ? chapter 41, reset generation module (mc_rgm) , describes the module that centralizes the different reset sources and manages the reset sequence of the device. ? chapter 42, self-test control unit (stcu) , describes the module that controls the sequencing of the device?s self-test before the prim ary user application starts running.
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xxxviii ? chapter 43, semaphore unit (sema4) , describes the module that le ts each processor know which processor has control of common memory. ? chapter 44, sine wave generator (swg) , describes the sine wa ve generator module. ? chapter 45, software watchdog timer (swt) , describes a hardware-bas ed timer that can be implemented to prevent software runaway. ? chapter 46, static ram (sram) , describes the on-chip static ram (sram) implementation, covers general operations, configuration, and in itialization. it also provides information and examples of how to minimize power consumption when using the sram. ? chapter 47, system integration unit lite (siul) , describes the siu modul e, which controls mcu reset configuration, pad configur ation, external interrupt, genera l-purpose i/o (gpio), internal peripheral multiplexing, and th e system reset operation. ? chapter 48, system status a nd configuration module (sscm) , ? chapter 49, system timer module (stm) , describes the timer control module. ? chapter 50, temperature sensor (tsens) , describes the on-board sensor that monitors device temperature. ? chapter 51, wakeup unit (wkpu) , describes the module that supports an external source that can cause non-maskable interrupt requests or wakeup events. ? appendix a, revision history , describes the revision history of this document. information about different device versions (?cuts?) the pxs20 device is availabl e in three silicon versions, or ?cuts?. th ese are referred to as ?cut1,? ?cut2,? and ?cut3? throughout this document. functional differences between the two cuts are clearly identified with the labels ?cut1,? ?cut2,? and ?cut3.? all cut2 functiona lities are applicable for cut3 except for the following : ? bam code (cut2 uses rom and shadow flash, cut3 rom only) ? chip id's (minor_mask_id, jtag_id) ? por and lvd flag behavior acronyms and abbreviations the following table lists some acronyms a nd abbreviations used in this document. term meaning autosar automotive open system architecture gpio general-purpose i/o ieee institute for electric al and electronics engineers jedec joint electron device engineering council jtag joint test action group mux multiplex
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xxxix references in addition to this reference manual, the followi ng documents provide additi onal information on the operation of the pxs20: ? ieee-isto 5001-2003 standard for a global embedded processor interface (nexus) ? ieee 1149.1-2001 standard - ieee standard test access port and boundary-scan architecture ? power architecture book e v1.0 (http://www.freescale.com/files/ 32bit/doc/user_guide/book_eum.pdf) rx receive rtl register transfer language sag safety application guide tbd to be determined tx transmit uart universal asynchronous receiver transmitter term meaning
pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor xl
introduction freescale semiconductor 1-1 pxs20 microcontroller reference manual, rev. 1 chapter 1 introduction 1.1 the pxs20 microcontroller the pxs20 series microcontrollers are system-on-chip devices that are built on power architecture ? technology, are 100% user-mode compat ible with the classic power arch itecture instruction set, contain enhancements that improve the arch itecture?s fit in embedded applicati ons, include additional instruction support for digital signal pr ocessing (dsp), and integrat e technologies to support hi ghly reliable and safe operation across a range of industria l, medical and transportation safe ty critical applications. these microcontrollers include a rich set of peripherals for complex real time c ontrol, such as an enhanced timer unit, analog-to-digital converters, and mu ltiple serial comm unications modules. the pxs20 is designed for a pplications requiring a high sa fety integrity level (sil). all devices in this family are built around a dual core safety platform with an innovative safety concept that reduces system cost and effort for the customer to achieve iec61508 and other corresponding certifications of their system. in order to minimize software overhead and improve operatio nal reliability, all major systems such as cpu core, dma controller, interrupt controller, cro ssbar bus system, memory systems, peripheral systems, and me mory protection unit, in clude built in redundancy and or robust system monitoring. lock step redundancy checking units are imp lemented at each output of this sphere of replication (sor). ecc is avai lable for on-chip ram and flash memories. a programmable fault collection and control unit monitors th e integrity status of the device and provides flexible safe state control. the host processor core of the px s20 is the latest cpu from the e200 family of compatible power architecture cores. the e200z4d 5-stag e pipeline dual issue co re provides a very high level of efficiency, allowing high performance with minimum power consumption. the peripheral set provides high-end el ectrical motor control capability with very low cpu intervention, thanks to the on-chip cros s triggering unit (ctu). this device incorporates high-performance 90 nm embedded flash-memory technology to provide substantial cost reduction per feature and significant performance improvement. 1.2 pxs20 device summary table 1 summarizes the pxs20 microcontroller.
introduction 1-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 table 1. pxs20 family feature set feature pxs20 cpu type 2 e200z4 (in lock-step or decoupled operation) architecture harvard execution speed 0 ? 120 mhz (+2% fm) dmips intrinsic performance > 240 mips simd (dsp + fpu) yes mmu 16 entry instruction set ppc yes instruction set vle yes instruction cache 4 kb, edc mpu-16 regions yes, replicated module semaphore unit (sema4) yes buses core bus ahb, 32-bit address, 64-bit data internal periphery bus 32-bit address, 32-bit data crossbar master slave ports lock step mode: 4 3 decoupled parallel mode: 6 3 memory code/data flash 1 mb, ecc, rww static ram (sram) 128 kb, ecc modules interrupt controller (intc) 16 interrupt levels, replicated module periodic interrupt timer (pit) 1 4 channels system timer module (stm) 1 4 channels, replicated module software watchdog timer (swt) yes, replicated module edma 16 channels, replicated module flexray 1 64 message buffers, dual channel can 2 32 message buffers uart with dma support 2 clock out yes fault control & collection unit (fccu) yes cross triggering unit (ctu) yes etimer 3 6 channels pwm 2 module 4 (2 + 1) channels analog-to-digital converter (adc) 2 12-bit adc, 16 channels per adc (3 internal, 4 shared and 9 external)
introduction freescale semiconductor 1-3 pxs20 microcontroller reference manual, rev. 1 1.3 device block diagram figure 1-1 shows a top-level block diagram of the pxs20. modules (cont.) sine-wave generator (swg) 32 point serial peripheral interface (spi) 3 spi as many as 8 chip selects cyclic redundancy checker (crc) unit yes junction temperature sensor (tsens) yes, replicated module digital i/os ? 16 supply device power supply 3.3 v with integrated bypassable ballast transistor external ballast transistor not needed for bare die analog reference voltage 3.0 v ? 3.6 v and 4.5 v ? 5.5 v clocking frequency-modulated phase-locked loop (fmpll) 2 internal rc oscillator 16 mhz external crystal oscillator 4 ? 40 mhz debug nexus level 3+ packages type 144 lqfp 257 mapbga temperature temperature range (junction) ?40 to 125 c ambient temperature range using external ballast transistor (lqfp) ?40 to 105 c ambient temperature range using external ballast transistor (bga) ?40 to 105 c table 1. pxs20 family feature set (continued) feature pxs20
introduction 1-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 1-1. pxs20 block diagram crossbar switch (xbar) memory protection unit (mpu) fpu vle i-cache e200z4 redundancy checker mmu swt ecsm pmu stm intc edma debug jtag nexus flexray? spe2 vle cache e200z4 mmu swt ecsm pmu stm intc edma redundancy checker pbridge 1 mb flash (ecc) crossbar switch (xbar) memory protection unit (mpu) redundancy checker pbridge 128 kb sram (ecc) redundancy checker bam pxs20 block diagram sscm fmpll fmpll ircosc cmu cmu cmu tsens tsens crc pit pit bam xosc siu wkpu adc adc ctu pwm pwm etimer etimer etimer can can uart/lin uart/lin spi spi spi fccu
introduction freescale semiconductor 1-5 pxs20 microcontroller reference manual, rev. 1 figure 1-2. pxs20 block diagram (continued) 1.4 feature details 1.4.1 high-performance e200z4d core the e200z4d power architecture ? core provides the following features: ? 2 independent execution units, both supporti ng fixed-point and fl oating-point operations ? dual issue 32-bit power architecture ? technology compliant ? 5-stage pipeline (i f, dec, ex1, ex2, wb) ? in-order execution and instruction retirement ? full support for power architecture ? instruction set and variab le length encoding (vle) ? mix of classic 32-bit and 16-bit instruction allowed ? optimization of code size possible ? thirty-two 64-bit genera l purpose registers (gprs) ? harvard bus (32-bit address, 64-bit data) ? i-bus interface capable of one outstanding transaction plus one piped with no wait-on-data return ? d-bus interface capable of two tran sactions outstanding to fill ahb pipe ? i-cache and i-cache controller ? 4 kb, 256-bit cache line (pr ogrammable for 2- or 4-way) ? no data cache ? 16-entry mmu ? 8-entry branch table buffer ? branch look-ahead instruction buffer to accelerate branching ? dedicated branch address calculator adc ? analog-to-digital converter bam ? boot assist module can ? controller area network controller cmu ? clock monitoring unit crc ? cyclic redundanc y check unit ctu ? cross triggering unit ecc ? error correction code ecsm ? error correction status module edma ? enhanced direct memory access controller fccu ? fault collection and control unit fmpll ? frequency modulated phase locked loop intc ? interrupt controller ircosc ? internal rc oscillator jtag ? joint test action group interface mc ? mode entry, clock, reset, & power pbridge ? peripheral i/o bridge pit ? periodic interrupt timer pmu ? power management unit pwm ? pulse width modulator module rc ? redundancy checker rtc ? real time clock sema4 ? semaphore unit siul ? system integration unit lite spi ? serial peripherals interface controller sscm ? system status and configuration module stm ? system timer module swg ? sine wave generator swt ? software watchdog timer tsens ? temperature sensor uart/lin ? universal asynchronous receiver/transmitter/ local interconnect network wkpu ? wakeup unit xosc ? crystal oscillator
introduction 1-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? 3 cycles worst case for missed branch ? load/store unit ? fully pipelined ? single-cycle load latency ? big- and little-endi an modes supported ? misaligned access support ? single stall cycle on load to use ? single-cycle throughput (2-cycle late ncy) integer 32 32 multiplication ? 4 ? 14 cycles integer 32 32 division (average division on various benchm ark of nine cycles) ? single precision fl oating-point unit ? 1 cycle throughput (2-cycle latency) floating-point 32 32 multiplication ? target 9 cycles (worst case acceptable is 12 cycles) throughput floating-point 32 32 division ? special square root and min/max function implemented ? signal processing support: apu-spe 1.1 ? support for vectorized mode: as many as tw o floating-point instructions per clock ? vectored interrupt support ? reservation instruction to suppor t read-modify-write constructs ? extensive system development and tracing support via nexus debug port 1.4.2 crossbar switch (xbar) the xbar multi-port crossbar switch supports simultaneous connections between four master ports and three slave ports. the crossbar supports a 32-bit address bus widt h and a 64-bit data bus width. the crossbar allows four concurrent transactions to occur from any ma ster port to any slave port, although one of those transfers must be an instruction fetc h from internal flash memo ry. if a slave port is simultaneously requested by more than one master port, arbitr ation logic sel ects the higher priority master and grants it ownership of the slav e port. all other masters requesting th at slave port are stalled until the higher priority master completes its transactions. the crossbar provides the following features: ? 4 masters and 3 slaves supporte d per each replicated crossbar ? masters allocation for each cros sbar: e200z4d core with two i ndependent bus interface units (biu) for i and d access (2 masters), one edma, one flexray ? slaves allocation fo r each crossbar: a redundant flash-memory controller with 2 slave ports to guarantee maximum flexibility to handle instru ction and data array, one redundant sram controller with 1 slave port each and 1 redundant peripheral bus bridge ? 32-bit address bus and 64-bit data bus ? programmable arbitration priority
introduction freescale semiconductor 1-7 pxs20 microcontroller reference manual, rev. 1 ? requesting masters can be treated with equal priority and are gr anted access to a slave port in round-robin method, based upon the id of the last master to be granted access or a priority order can be assigned by soft ware at application run time ? temporary dynamic priority elevation of masters the xbar is replicated for each processor. 1.4.3 memory protection unit (mpu) the memory protection unit splits the physical memo ry into 16 different regions. each master (edma, flexray, cpu) can be assigned di fferent access rights to each region. ? 16-region mpu with concurrent ch ecks against each master access ? 32-byte granularity for protected address region the memory protection unit is re plicated for each processor. 1.4.4 enhanced direct memory access (edma) the enhanced direct memory access (edma) cont roller is a second-generation module capable of performing complex data movements via 16 programmable channels, w ith minimal intervention from the host processor. the hardware micr oarchitecture includes a dma engi ne which performs source and destination address calculations, and the actual data movement opera tions, along with an sram-based memory containing the transfer cont rol descriptors (tcd) for the channe ls. this implementation is used to minimize the overall block size. the edma module provides the following features: ? 16 channels supporting 8-, 16-, and 32-bi t value single or block transfers ? support variable sized queues and circular buffered queue ? source and destination address registers independe ntly configured to po st-increment or stay constant ? support major and minor loop offset ? support minor and major loop done signals ? dma task initiated either by hardware requestor or by software ? each dma task can optionally generate an inte rrupt at completion and retirement of the task ? signal to indicate clos ure of last minor loop ? transfer control descriptors mapped inside the sram the edma controller is replicated for each processor. 1.4.5 on-chip flash memory with ecc this device includes programmable, non-volatile fl ash memory. the non-volatile memory (nvm) can be used for instruction storage or data storage, or both. the flash memory module interfaces with the system bus through a dedicated flash memory array controller. it supports a 64-bi t data bus width at the system bus port, and a 128-bit read data interface to flas h memory. the module contai ns four 128-bit prefetch
introduction 1-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 buffers. prefetch buffer hits allow no-wait responses . buffer misses incur a 3 wait state response at 120 mhz. the flash memory module prov ides the following features ? 1 mb of flash memory in unique multi-partitioned hard macro ? sectorization: 16 kb + 2 48 kb + 16 kb + 2 64 kb + 2 128 kb + 2 256 kb ? eeprom emulation (in software) within same module but on different partition ? 16 kb test sector and 16 kb shadow sector for test, censorship device and user option bits ? wait states: ? 3 wait states at 120 mhz ? 2 wait states at 80 mhz ? 1 wait state at 60 mhz ? flash memory line 128-bit wide with 8-bit ecc on 64-bit word (total 144 bits) ? accessed via a 64-bit wide bus for write and a 128-bit wide array for read operations ? 1-bit error correction, 2-bit error detection 1.4.6 on-chip sram with ecc the pxs20 sram provides a gene ral-purpose single port memory. ecc handling is done on a 32-bit boundary for data and it is extended to the addr ess to have the highest possible diagnostic coverage including the array internal address decoder. the sram module provides the following features: ? system sram: 128 kb ? ecc on 32-bit word (syndrome of 7 bits) ? ecc covers sram bus address ? 1-bit error correction, 2-bit error detection ? wait states: ? 1 wait state at 120 mhz ? 0 wait states at 80 mhz and 60 mhz 1.4.7 platform flash memory controller the following list summari zes the key features of th e flash memory controller: ? single ahb port inte rface supports a 64-bit data bus. all ahb aligned a nd unaligned reads within the 32-bit container are supported. only aligned word writes are supported. ? array interfaces support a 128- bit read data bus and a 64-bit write data bus for each bank. ? code flash (bank0) interface pr ovides configurable read bufferi ng and page prefetch support. ? four page-read buffers (each 128 bits wide) a nd a prefetch controller support speculative reading and optimized flash access.
introduction freescale semiconductor 1-9 pxs20 microcontroller reference manual, rev. 1 ? single-cycle read respons es (0 ahb data-phase wait states) for hits in the buffers. the buffers implement a least-recently -used replacement algorithm to maximize performance. ? data flash (bank1) interface includ es a 128-bit register to temporar ily hold a single fl ash page. this logic supports single-cycle read responses (0 ahb da ta-phase wait states) fo r accesses that hit in the holding register. ? no prefetch support is provided for this bank. ? programmable response for read-w hile-write sequences including support for stall-while-write, optional stall notification interrupt, optional flas h operation abort , and optional abort notification interrupt. ? separate and independent configur able access timing (on a per bank basis) to support use across a wide range of platforms and frequencies. ? support of address-based read access timing for emulation of other memory types. ? support for reporting of single- and multi-bit error events. ? typical operating configuration loaded in to programming model by system reset. the platform flash controller is replicated for each processor. 1.4.8 platform static ram controller (sramc) the sramc module is the platform sram array c ontroller, with integrated error detection and correction. the main features of the sramc provide connectivity for the following interfaces: ? xbar slave port (64-bit data path) ? ecsm (ecc error reporting, error injection and configuration) ?sram array the following functions are implemented: ? ecc encoding (32-bit boundary for data and complete address bus) ? ecc decoding (32-bit bounda ry and entire address) ? address translation from the ahb prot ocol on the xbar to the sram array the platform sram controller is replicated for each processor. 1.4.9 memory subsystem access time every memory access the cpu performs requires at least one system cloc k cycle for the data phase of the access. slower memories or periphe rals may require additional data pha se wait states. additional data
introduction 1-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 phase wait states may also occur if the slave being accessed is not park ed on the requesting master in the crossbar. table 1-2 shows the number of addi tional data phase wait states requi red for a range of memory accesses. 1.4.10 error correction status module (ecsm) the ecsm on this device manages th e ecc configuration and reporting for the platform memories (flash memory and sram). it does not im plement the actual ecc calculation. a detected error (double error for flash memory or sram) is also re ported to the fccu. the following er rors and indications are reported into the ecsm dedicated registers: ? ecc error status and configur ation for flash memory and sram ? ecc error reporting for flash memory ? ecc error reporting for sram ? ecc error injection for sram 1.4.11 peripheral bridge (pbridge) the pbridge implements the following features: ? duplicated periphery ? master access right per peripheral (per mast er: read access enable; write access enable) ? write buffering for peripherals ? checker applied on pbridge output toward periphery ? byte endianess swap capability table 1-2. platform memo ry access time summary ahb transfer data phase wait states description e200z4d instruction fetch 0 flash memory prefetch buffer hit (page hit) e200z4d instruction fetch 3 flash memory prefetch buffer miss (based on 4-cycle random flash array access time) e200z4d data read 0?1 sram read e200z4d data write 0 sram 32-bit write e200z4d data write 0 sram 64-bit writ e (executed as 2 x 32-bit writes) e200z4d data write 0?2 sram 8-,16-bit write (read-modify-write for ecc) e200z4d flash memory read 0 flash memory prefetch buffer hit (page hit) e200z4d flash memory read 3 flash memory prefetch buffer miss (at 120 mhz; includes 1 cycle of program flash memory controller arbitration)
introduction freescale semiconductor 1-11 pxs20 microcontroller reference manual, rev. 1 1.4.12 interrupt controller (intc) the intc provides priority-based preemptive scheduli ng of interrupt requests, suitable for statically scheduled hard real-time systems. for high-priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executi ng the interrupt service routine (i sr) has been minimized. the intc provides a unique vector for each inte rrupt request source for quick dete rmination of which isr needs to be executed. it also provides an ample number of prior ities so that lower priority isrs do not delay the execution of higher priority isrs. to allow the appropria te priorities for each s ource of interrupt request, the priority of each interrupt re quest is software configurable. the intc supports the priority ceilin g protocol for coherent accesses. by providing a modifiable priority mask, the priority can be raised te mporarily so that all tasks which sh are the resource can not preempt each other. the intc provides the following features: ? duplicated periphery ? unique 9-bit vector per interrupt source ? 16 priority levels with fixed hardware arbitrati on within priority levels for each interrupt source ? priority elevation for shared resource the intc is replicated for each processor. 1.4.13 system clocks and clock generation the following list summarizes the system clock and clock generation on this device: ? lock status continuously monito red by lock detect circuitry ? loss-of-clock (loc) detection fo r reference and feedback clocks ? on-chip loop filter (for improve d electromagnetic interference pe rformance and fewer external components required) ? programmable output clock di vider of system clock ( ? 1, ? 2, ? 4, ? 8) ? pwm module and as many as three etimer modul es running on an auxiliary clock independent from system clock (wit h max frequency 120 mhz) ? on-chip crystal oscillator with automatic level control ? dedicated internal 16 mhz internal rc oscillator for rapid start-up ? supports automated frequency trimming by hard ware during device startup and by user application ? auxiliary clock domain for motor control pe riphery (pwm, etimer, ctu, adc, and swg) 1.4.14 frequency-modulated phase-locked loop (fmpll) each device has two fmplls.
introduction 1-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 each fmpll allows the user to gene rate high speed system clocks st arting from a minimum reference of 4 mhz input clock. further, the fmpll supports programmable freque ncy modulation of the system clock. the fmpll multiplication fact or, output clock divider ratio are all software configurable. the fmplls have the following major features: ? input frequency: 4?40 mhz continuous ra nge (limited by the crystal oscillator) ? voltage controlled oscillator (vco) range: 256?512 mhz ? frequency modulation via so ftware control to reduce and control emission peaks ? modulation depth 2% if centere d or 0% to ?4% if downshifted via software control register ? modulation frequency: triangular modulation with 25 khz nominal rate ? option to switch modulation on and off via software interface ? reduced frequency divider (rfd) for re duced frequency operation without re-lock ? 3 modes of operation ? bypass mode ? normal fmpll mode with cr ystal reference (default) ? normal fmpll mode with external reference ? lock monitor circuitry with lock status ? loss-of-lock detection for re ference and feedback clocks ? self-clocked mode (scm) operation ? on-chip loop filter ? auxiliary fmpll ? used for flexray due to precise symb ol rate requirement by the protocol ? used for motor control periphery and connected ip (a/d digital inte rface ctu) to allow independent frequencies of operation for pwm and timers and jitter-free control ? option to enable/disable modulation to avoid protocol violation on jit ter and/or potential unadjusted error in elect ric motor control loop ? allows to run motor control periphe ry at different (precisely lowe r, equal or higher as required) frequency than the system to ensure higher resolution 1.4.15 main oscillator the main oscillator provides these features: ? input frequency range 4?40 mhz ? crystal input mode ? external reference clock (3.3 v) input mode ? fmpll reference 1.4.16 internal referenc e clock (rc) oscillator the architecture uses constant curr ent charging of a capacitor. the voltage at the capacitor is compared to the stable bandgap reference voltage. the rc oscillator is the device safe clock.
introduction freescale semiconductor 1-13 pxs20 microcontroller reference manual, rev. 1 the rc oscillator provides these features: ? nominal frequency 16 mhz ? 5% variation over voltage and temperature after process trim ? clock output of the rc oscillator serves as system clock source in case loss of lock or loss of clock is detected by the fmpll ? rc oscillator is used as the default system cloc k during startup and can be used as back-up input source of fmpll(s) in case xosc fails 1.4.17 clock, reset, power mode, an d test control modules (mc_cgm, mc_rgm, mc_pcu, and mc_me) these modules provide the following: ? clock gating and clock distribution control ? halt, stop mode control ? flexible configurable system and auxiliary clock dividers ? various execution modes ? reset, idle, test, safe ? various run modes with softwa re selectable powered modules ? no stand-by mode implemented (no in ternal switchable power domains) 1.4.18 periodic interrupt timer module (pit) the pit module implements the following features: ? 4 general purpose interrupt timers ? 32-bit counter resolution ? can be used for software tick or dma trigger operation 1.4.19 system timer module (stm) the stm implements the following features: ? up-counter with 4 output compare registers ? os task protection and hardware tick implementation per autosar 1 requirement the stm is replicated for each processor. 1.4.20 software watchdog timer (swt) this module implements the following features: ? fault tolerant output ? safe internal rc oscillator as reference clock 1.open system architecture
introduction 1-14 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? windowed watchdog ? program flow control monitor with 16-bit pseudorandom key generation ? allows a high level of safety (sil3 monitor) the swt module is replicated for each processor. 1.4.21 fault collection and control unit (fccu) the fccu module has the following features: ? redundant collection of hardware checker results ? redundant collection of error information and latc h of faults from critic al modules on the device ? collection of self-test results ? configurable and graded fault control ? internal reactions (no internal reaction, irq, functional reset, de structive reset, or safe mode entered) ? external reaction (failure is reported to th e external/surrounding syst em via configurable output pins) 1.4.22 system integration unit lite (siul) the siul controls mcu re set configuration, pad configuration, ex ternal interrupt, general purpose i/o (gpio), internal peripheral multiplexing, and syst em reset operation. the re set configuration block contains the external pin boot configuration logic. the pa d configuration block contro ls the static electrical characteristics of i/o pins . the gpio block provides uniform and di screte input/output control of the i/o pins of the mcu. the siu provides the following features: ? centralized pad control on a per-pin basis ? pin function selection ? configurable weak pull-up/down ? configurable slew rate control (slow/medium/fast) ? hysteresis on gpio pins ? configurable automatic safe mode pad control ? input filtering for external interrupts 1.4.23 non-maskable interrupt (nmi) the non-maskable interrupt with de-glitching f ilter supports high-priority core exceptions. 1.4.24 boot assist module (bam) the bam is a block of read-only memory with hard-coded content. the bam program is executed only if serial booting mode is select ed via boot configuration pins.
introduction freescale semiconductor 1-15 pxs20 microcontroller reference manual, rev. 1 the bam provides the following features: ? enables booting via serial mode (can or lin/uart) ? supports programmable 64-bit password protection for serial boot mode ? supports serial bootloading of either classic powerpc book e c ode (default) or freescale vle code ? automatic switch to serial boot mode if internal flash memory is blank or invalid 1.4.25 system status and configuration module (sscm) the sscm on this device features the following: ? system configuration and status ? debug port status and debug port enable ? multiple boot code starting locati ons out of reset through implemen tation of search for valid reset configuration half word ? sets up the mmu to allow user boot code to execute as either classic powerpc book e code (default) or as freescale vle code out of flash memory ? triggering of device self-tests during reset phase of device boot 1.4.26 controller area network module (can) the can module is a communication controller im plementing the can protocol according to bosch specification version 2.0b. although the can interface was designed to be used primarily as a vehicle networking bus, it is widely used in industrial and other transport appl ications due to its robust operation, time determinism, cost effectiveness, and optional redundant physical layer implementation. the can module provides the following features: ? full implementation of the can pr otocol specification, version 2.0b ? standard data and remote frames ? extended data and remote frames ? 0 to 8 bytes data length ? programmable bit rate as fast as 1mbit/s ? 32 message buffers of 0 to 8 bytes data length ? each message buffer configurable as receive or transmit buffer, all supporting standard and extended messages ? programmable loop-back mode supporting self-test operation ? 3 programmable mask registers ? programmable transmit-first scheme: lowest id or lowest buffer number ? time stamp based on 16- bit free-running timer ? global network time, synchr onized by a specific message ? maskable interrupts ? independent of the transm ission medium (an external transceiver is assumed)
introduction 1-16 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? high immunity to emi ? short latency time due to an arbitration scheme for high-priority messages ? transmit features ? supports configuration of multiple mailboxes to form message queues of scalable depth ? arbitration scheme according to me ssage id or message buffer number ? internal arbitration to guarantee no inner or outer priority inversion ? transmit abort proce dure and notification ? receive features ? individual programmable filters for each mailbox ? 8 mailboxes configurable as a 6-entry receive fifo ? 8 programmable acceptance filters for receive fifo ? programmable clock source ? system clock ? direct oscillator clock to avoid fmpll jitter 1.4.27 flexray the flexray module provides the following features: ? full implementation of flexray protocol specification 2.1 rev. a ? 64 configurable message buffers can be handled ? dual channel or single channel mode of ope ration, each as fast as 10 mbit/s data rate ? message buffers configurable as transmit or receive ? message buffer size configurable ? message filtering for all messa ge buffers based on frame id , cycle count, and message id ? programmable acceptance filters for receive fifo ? message buffer header, status, and payloa d data stored in system memory (sram) ? internal flexray memories have error detection and correction 1.4.28 serial communicatio n interface module (uart) the uart module with dma support on this device features the following: ? uart features: ? full-duplex operation ? standard non return-to-zero (nrz) mark/space format ? data buffers with 4-byte receive, 4-byte transmit ? configurable word length (8-bit or 9-bit words) ? error detection and flagging ? parity, noise and framing errors ? interrupt driven operation with 4 interrupts sources
introduction freescale semiconductor 1-17 pxs20 microcontroller reference manual, rev. 1 ? separate transmitter and r eceiver cpu interrupt sources ? 16-bit programmable baud-rate modul us counter and 16-bit fractional ? 2 receiver wake-up methods ? lin features: ? autonomous lin frame handling ? message buffer to store identi fier and up to eight data bytes ? supports message length of up to 64 bytes ? detection and flagging of lin errors ? sync field; delimiter; id parity; bit, framing; checksum and timeout errors ? classic or extended checksum calculation ? configurable break duration of up to 36-bit times ? programmable baud rate prescalers (13-bit mantissa, 4-bit fractional) ? diagnostic features ? loop back ?self test ? lin bus stuck dominant detection ? interrupt driven operation with 16 interrupt sources ? lin slave mode features ? autonomous lin header handling ? autonomous lin response handling ? discarding of irrelevant lin resp onses using up to 16 id filters 1.4.29 serial peripheral interface (spi) the spi modules provide a synchronous serial in terface for communication between the pxs20 and external devices. a spi module provides these features: ? full duplex, synchronous transfers ? master or slave operation ? programmable master bit rates ? programmable clock polarity and phase ? end-of-transmission interrupt flag ? programmable transfer baud rate ? programmable data fram es from 4 to 16 bits ? as many as 8 chip select lines availabl e, depending on package and pin multiplexing ? 4 clock and transfer attributes registers ? chip select strobe available as alternate functi on on one of the chip select pins for de-glitching ? fifos for buffering as many as 5 tran sfers on the transmit and receive side
introduction 1-18 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? queueing operation possible through use of the edma ? general purpose i/o functionality on pins when not used for spi 1.4.30 pulse width modulator (pwm) the pwm module contains four pwm channels, each of which is configur ed to control a single half-bridge power stage. two modules are include d on 257 mapbga devices ; on the 144 lqfp package, only one module is present. additi onally, four fault input channe ls are provided per pwm module. this pwm is capable of controll ing most motor types, including: ? ac induction motors (acim) ? permanent magnet ac motors (pmac) ? brushless (bldc) and brush dc motors (bdc) ? switched (srm) and variable reluctance motors (vrm) ? stepper motors a pwm module implements the following features: ? 16 bits of resolution for center, edge aligned, and asymmetrical pwms ? maximum operating frequency as high as 120 mhz ? clock source not modulated and independent from system clock (generated via secondary fmpll) ? fine granularity control for enha nced resolution of the pwm period ? pwm outputs can operate as compleme ntary pairs or independent channels ? ability to accept signed numbers for pwm generation ? independent control of both edges of each pwm output ? synchronization to external hard ware or other pwm supported ? double buffered pwm registers ? integral reload rates from 1 to 16 ? half cycle reload capability ? multiple adc trigger events can be generated per pwm cycle via hardware ? fault inputs can be assigned to control multiple pwm outputs ? programmable filters for fault inputs ? independently programmable pwm output polarity ? independent top and botto m deadtime insertion ? each complementary pair can operate with its own pwm frequency and deadtime values ? individual software control for each pwm output ? all outputs can be forced to a value simultaneously ? pwmx pin can optionally output a third signal from each channel ? channels not used for pwm generation can be used for buffered output compare functions ? channels not used for pwm generation ca n be used for input capture functions
introduction freescale semiconductor 1-19 pxs20 microcontroller reference manual, rev. 1 ? enhanced dual edge capture functionality ? option to supply the source for each complement ary pwm signal pair from any of the following: ? external digital pin ? internal timer channel ? external adc input, taking into account valu es set in adc high- a nd low-limit registers ? dma support 1.4.31 etimer module the pxs20 provides three etimer m odules on the 257 mapbga device, and two etimer modules on the 144 lqfp package. six 16-bit general purpose up/down ti mer/counters per module are implemented with the following features: ? maximum clock frequency of 120 mhz ? individual channel capability ? input capture trigger ? output compare ? double buffer (to capture rising edge and falling edge) ? separate prescaler for each counter ? selectable clock source ? 0?100% pulse measurement ? rotation direction flag (quad decoder mode) ? maximum count rate ? equals peripheral clock divided by 2 for external event counting ? equals peripheral clock for internal clock counting ? cascadeable counters ? programmable count modulo ? quadrature dec ode capabilities ? counters can share available input pins ? count once or repeatedly ? preloadable counters ? pins available as gpio when timer functionality not in use ? dma support 1.4.32 sine wave generator (swg) a digital-to-analog converter is avai lable to generate a sine wave base d on 32 stored values for external devices (ex: resolver). ? frequency range from 1 khz to 50 khz ? sine wave amplitude from 0.47 v to 2.26 v
introduction 1-20 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 1.4.33 analog-to-digital converter module (adc) the adc module features include: analog part: ? 2 on-chip adcs ? 12-bit resolution sar architecture ? a/d channels: 9 external, 3 internal and 4 shared with other a/d (total 16 channels) ? one channel dedicated to each t-sensor to enable temperature reading during application ? separated reference for each adc ? shared analog supply voltage for both adcs ? one sample and hold unit per adc ? adjustable sampling and conversion time digital part: ? 4 analog watchdogs comparing adc results against predefined le vels (low, high, range) before results are stored in the appropriate adc result location ? 2 modes of operation: motor control mode or regular mode ? regular mode features ? register based interface with the cp u: one result register per channel ? adc state machine managing three request fl ows: regular command, hardware injected command, software injected command ? selectable priority between softwa re and hardware injected commands ? 4 analog watchdogs comparing adc results against predefin ed levels (low, high, range) ? dma compatible interface ? motor control mode features ? triggered mode only ? 4 independent result queues (1 ? 16 entries, 2 ? 8 entries, 1 ? 4 entries) ? result alignment circuitry (lef t justified; right justified) ? 32-bit read mode allows to have channel id on one of the 16-bit parts ? dma compatible interfaces ? built-in self-test featur es triggered by software 1.4.34 junction temperature sensor the junction temperature sensor provides a value via an adc channel that can be used by software to calculate the device junction temperature. the key parameters of the junc tion temperature sensor include: ? nominal temperature range from ?40 to 150 c ? software temperature alarm via analog adc comparator possible
introduction freescale semiconductor 1-21 pxs20 microcontroller reference manual, rev. 1 1.4.35 cross triggering unit (ctu) the adc cross triggering unit allows automatic generation of adc conv ersion requests on user selected conditions without cpu load du ring the pwm period and with mi nimized cpu load for dynamic configuration. the ctu implements the following features: ? cross triggering between adc, pw m, etimer, and external pins ? double buffered trigger generation unit with as many as 8 indepe ndent triggers generated from external triggers ? maximum operating frequency less than or equal to 120 mhz ? trigger generation unit configurable in sequential mode or in triggered mode ? trigger delay unit to compensate the delay of external low pass filter ? double buffered global trigger unit allowing et imer synchronization and/or adc command generation ? double buffered adc command list pointe rs to minimize adc-trigger unit update ? double buffered adc conversion command li st with as many as 24 adc commands ? each trigger capable of generating consecutive commands ? adc conversion command allows control of adc channel from ea ch adc, single or synchronous sampling, independent result queue selection ? dma support with safety features 1.4.36 cyclic redundancy checker (crc) unit the crc module is a configurable mu ltiple data flow unit to compute crc signature s on data written to its input register. the crc unit has the following features: ? 3 sets of registers to allow 3 concurrent contexts with possibly different crc computations, each with a selectable polynomial and seed ? computes 16- or 32-bit wide crc on the fly (s ingle-cycle computation) and stores result in internal register. the following standard crc polynomials are implemented: ? x 16 + x 12 + x 5 + 1 [16-bit crc-ccitt] ? x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x +1 [32-bit crc-ethernet(32)] ? key engine to be coupled with communication periphery where crc application is added to allow implementation of safe communication protocol ? offloads core from cycle-consuming crc and he lps checking configuration signature for safe start-up or periodic procedures ? crc unit connected as periphera l bus on internal peripheral bus ? dma support
introduction 1-22 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 1.4.37 redundancy control and checker unit (rccu) the rccu checks all outputs of the sphere of replicat ion (addresses, data, cont rol signals). it has the following features: ? duplicated module to guarantee highest possi ble diagnostic coverage (check of checker) ? multiple times replicated ips are used as checkers on the sor outputs 1.4.38 voltage regulator / power management unit (pmu) the on-chip voltage regulator module provides the following features: ? single external rail required ? single high supply required: nominal 3.3 v for packaged option ? packaged option requires external ballast transistor due to reduced dissipation ca pacity at high temperature but can use embedded tr ansistor if power dissipation is maintained within package dissipation capacity (lower frequency of operation) ? all i/os are at same voltage as external supply (3.3 v nominal) ? duplicated low-voltage detect ors (lvd) to guarantee proper ope ration at all stages (reset, configuration, normal operation) and, to maximize safety coverage , one lvd can be tested while the other operates (on-li ne self-testing feature) 1.4.39 built-in self-test (bist) capability this device includes the following protection against latent faults: ? boot-time memory built-in self-test (mbist) ? boot-time scan-based logic built-in self-test (lbist) ? run-time adc built-in self-test (bist) ? run-time built-in self test of lvds 1.4.40 ieee 1149.1 jtag controller (jtagc) the jtagc block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. all data input to and output from the jtagc block is communicated in serial format. the jtagc bl ock is compliant with the ieee standard. the jtag controller provides the following features: ? ieee test access port (tap) interface with 5 pins: ?tdi ?tms ?tck ?tdo ?jcomp ? selectable modes of operation include jtagc/debug or normal system operation
introduction freescale semiconductor 1-23 pxs20 microcontroller reference manual, rev. 1 ? 5-bit instruction register that supports the following ieee 1149.1-2001 defined instructions: ?bypass ?idcode ?extest ?sample ? sample/preload ? 3 test data registers: a bypass register, a boundary scan register, and a device identification register. the size of the boundary scan regist er is parameterized to support a variety of boundary scan chain lengths. ? tap controller state machine that controls the ope ration of the data register s, instruction register and associated circuitry 1.4.41 nexus port controller (npc) the npc module provides real-time de velopment support capabilities for this device in compliance with the ieee-isto 5001-2008 standard. this development support is supplied for mcus without requiring external address and data pi ns for internal visibility. the npc block interfaces to the host processor and in ternal buses to provide development support as per the ieee-isto 5001-2008 class 3+, including sel ected features from class 4 standard. the development support provided in cludes program trace, data trace, wa tchpoint trace, ownership trace, run-time access to the mcus internal memo ry map and access to the power architecture ? internal registers during halt. the nexus inte rface also supports a jtag only m ode using only the jtag pins. the following features are implemented: ? full and reduced port modes ? mcko (message clock out) pin ? 4 or 12 mdo (message data out) pins 1 ?2 mseo (message start/end out) pins ?evto (event out) pin ? auxiliary input port ?evti (event in) pin ? 5-pin jtag port (jcomp, tdi, tdo, tms, and tck) ? supports jtag mode ? host processor (e200) de velopment support features ? data trace via data write messaging (dwm) and da ta read messaging (drm). this allows the development tool to trace reads or writes, or both, to select ed internal memory resources. ? ownership trace via ownership trace messaging (otm). otm facilitates ownership trace by providing visibility of which pr ocess id or operating system ta sk is activated. an ownership trace message is transmitted wh en a new process/task is activ ated, allowing development tools 1. 4 mdo pins on 144 lq fp package, 12 mdo pins on 257 mapbga package.
introduction 1-24 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 to trace ownership flow. ? program trace via branch trac e messaging (btm). branch trac e messaging displays program flow discontinuities (direct branches, indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between the disc ontinuities. thus, static code may be traced. ? watchpoint messaging (wpm ) via the auxiliary port ? watchpoint trigger enable of pr ogram and/or data trace messaging ? data tracing of instruction fetches via private opcodes
memory map freescale semiconductor 2-1 pxs20 microcontroller reference manual, rev. 1 chapter 2 memory map table 2-1 shows the memory map for the pxs20. all addresses on the pxs20, including those that are rese rved, are identified in the table. the addresses represent the physical addresses as signed to each region or module na me. the table also identifies the associated peripheral contro l register (pctl) number a nd mode (ls, dp, or both). all memory not listed in this table is reserve d, and access to those locations may produce undesirable results. table 2-1. pxs20 memory map, ordered by start address start address size (kb) pctl number mode region / module name flash memory 0x0000_0000 16 ? ls/dp flash-memory array partition 1 (low address) or test flash memory 1 0x0000_4000 48 ? ls/dp flash-memory array partition 1 (low address) 0x0001_0000 48 ? ls/dp flash-memory array partition 1 (low address) 0x0001_c000 16 ? ls/dp flash-memory array partition 1 (low address) 0x0002_0000 64 ? ls/dp flash-memory array partition 2 (low address) 0x0003_0000 64 ? ls/dp flash-memory array partition 2 (low address) 0x0004_0000 128 ? ls/dp flash-memory array partition 3 (mid address) 0x0006_0000 128 ? ls/dp flash-memory array partition 3 (mid address) 0x0008_0000 256 ? ls/dp flash-memory array partition 4 (high address) 0x000c_0000 256 ? ls/dp flash-memory array partition 4 (high address) 0x00f0_0000 1024 ? ls/dp shadow block 0x0100_0000 507904 ? ls/dp flash-memory emulation mapping static ram 0x4000_0000 64 ? dp sram 128 ? ls sram 0x5000_0000 64 ? dp sram 2 on-platform 1 peripherals 3 0x8ff0_0000 16 ? dp pbridge_1 0x8ff0_4000 16 ? dp xbar_1 0x8ff1_0000 16 ? dp mpu_1 0x8ff2_4000 16 ? dp semaphores (sema4_1) 0x8ff3_8000 16 ? dp swt_1 0x8ff3_c000 16 ? dp stm_1 0x8ff4_0000 16 ? dp ecsm_1
memory map 2-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 0x8ff4_8000 16 ? dp intc_1 off-platform peripherals (mirrored to memory range 0xffe8_0000?0xffef_ffff) 0xc3f8_8000 16 66 ls/dp flash 0 configuration (flash0) 0xc3f9_0000 16 68 ls/dp system in tegration unit lite (siul) 0xc3f9_4000 16 69 ls/dp wakeup unit (wkpu) 0xc3fd_8000 16 86 ls/dp system status and configuration module (sscm) 0xc3fd_c000 16 87 ls/dp mode entry module (mc_me) 0xc3fe_0000 16 88 ls/dp clock generation module (mc_cgm) 0xc3fe_4000 16 89 ls/dp reset generation module (mc_rgm) 0xc3fe_8000 16 90 ls/dp power control unit (mc_pcu) 0xc3ff_0000 16 92 ls/dp periodic interrupt timer (pit) 0xc3ff_4000 16 93 ls/dp self-test control unit (stcu) off-platform peripherals 0xffe0_0000 16 32 ls/dp analog-to-digital converter 0 (adc_0) 0xffe0_4000 16 33 ls/dp analog-to-digital converter 1 (adc_1) 0xffe0_c000 16 35 ls/dp cross triggering unit (ctu) 0xffe1_8000 16 38 ls/dp etimer_0 0xffe1_c000 16 39 ls/dp etimer_1 0xffe2_0000 16 40 ls/dp etimer_2 0xffe2_4000 16 41 ls/dp flexpwm_0 0xffe2_8000 16 42 ls/dp flexpwm_1 0xffe4_0000 16 48 ls/dp linflexd_0 0xffe4_4000 16 49 ls/dp linflexd_1 0xffe6_8000 16 58 ls/dp cyclic redundancy check unit (crc) 0xffe6_c000 16 59 ls/dp fault collection and control unit (fccu) 0xffe7_8000 16 62 ls/dp sine wave generator (swg) on platform 0 peripherals 0xfff0_0000 16 ? ls pbridge_0, pbridge_1 dp pbridge_0 0xfff0_4000 16 ? ls xbar_0, xbar_1 dp xbar_0 0xfff1_0000 16 ? ls mpu_0, mpu_1 dp mpu_0 0xfff2_4000 16 ? dp semaphores (sema4_0) table 2-1. pxs20 memory map, ordered by start address (continued) start address size (kb) pctl number mode region / module name
memory map freescale semiconductor 2-3 pxs20 microcontroller reference manual, rev. 1 0xfff3_8000 16 ? ls swt_0, swt_1 dp swt_0 0xfff3_c000 16 ? ls stm_0, stm_1 dp stm_0 0xfff4_0000 16 ? ls ecsm_0, ecsm_1 dp ecsm_0 0xfff4_4000 16 ? ls edma_0, edma_1 dp edma_0 0xfff4_8000 16 ? ls intc_0, intc_1 dp intc_0 off platform peripherals 0xfff9_0000 16 4 ls/dp dspi_0 0xfff9_4000 16 5 ls/dp dspi_1 0xfff9_8000 16 6 ls/dp dspi_2 0xfffc_0000 16 16 ls/dp flexcan_0 0xfffc_4000 16 17 ls/dp flexcan_1 0xfffd_c000 16 23 ls edma channel multiplexer (dma_mux) dp edma channel multiplexer (dma_mux) 4 0xfffe_0000 16 24 ls/dp flexray controller (flexray) 0xffff_c000 16 31 ls/dp boot assist module (bam) notes: 1 test flash memory is mapped to this address if the sctr[tfe] bit in the sscm is set (see section 48.3.1.9, sscm control register (sctr) ). 2 this range cannot be accessed by dma_0. 3 these peripherals are not accessible to dma_0 in dp mode. 4 dma_mux_1 is disabled in dp mode. table 2-2. pxs20 memory map, ordered by module name start address size (kb) pctl number mode region / module name 0xffe0_0000 16 32 ls/dp analog-to-digital converter 0 (adc_0) 0xffe0_4000 16 33 ls/dp analog-to-digital converter 1 (adc_1) 0xffff_c000 16 31 ls/dp boot assist module (bam) 0xc3fe_0000 16 88 ls/dp clock generation module (mc_cgm) 0xffe0_c000 16 35 ls/dp cross triggering unit (ctu) 0xffe6_8000 16 58 ls/dp cyclic redundancy check unit (crc) table 2-1. pxs20 memory map, ordered by start address (continued) start address size (kb) pctl number mode region / module name
memory map 2-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 0xfff9_0000 16 4 ls/dp dspi_0 0xfff9_4000 16 5 ls/dp dspi_1 0xfff9_8000 16 6 ls/dp dspi_2 0x8ff4_0000 16 ? dp ecsm_1 0xfff4_0000 16 ? ls ecsm_0, ecsm_1 dp ecsm_0 0xfff4_4000 16 ? ls edma_0, edma_1 dp edma_0 0xfffd_c000 16 23 ls edma channel multiplexer (dma_mux) dp edma channel multiplexer (dma_mux) 1 0xffe1_8000 16 38 ls/dp etimer_0 0xffe1_c000 16 39 ls/dp etimer_1 0xffe2_0000 16 40 ls/dp etimer_2 0xffe6_c000 16 59 ls/dp fault collection and control unit (fccu) 0xc3f8_8000 16 66 ls/dp flash 0 configuration (flash0) 0x0000_0000 16 ? ls/dp flash-memory array partition 1 (low address) or test flash memory 2 0x0000_4000 48 ? ls/dp flash-memory array partition 1 (low address) 0x0001_0000 48 ? ls/dp flash-memory array partition 1 (low address) 0x0001_c000 16 ? ls/dp flash-memory array partition 1 (low address) 0x0002_0000 64 ? ls/dp flash-memory array partition 2 (low address) 0x0003_0000 64 ? ls/dp flash-memory array partition 2 (low address) 0x0004_0000 128 ? ls/dp flash-memory array partition 3 (mid address) 0x0006_0000 128 ? ls/dp flash-memory array partition 3 (mid address) 0x0008_0000 256 ? ls/dp flash-memory array partition 4 (high address) 0x000c_0000 256 ? ls/dp flash-memory array partition 4 (high address) 0x0100_0000 507904 ? ls/dp flash-memory emulation mapping 0xfffc_0000 16 16 ls/dp flexcan_0 0xfffc_4000 16 17 ls/dp flexcan_1 0xffe2_4000 16 41 ls/dp flexpwm_0 0xffe2_8000 16 42 ls/dp flexpwm_1 0xfffe_0000 16 24 ls/dp flexray controller (flexray) 0x8ff4_8000 16 ? dp intc_1 table 2-2. pxs20 memory map, orde red by module name (continued) start address size (kb) pctl number mode region / module name
memory map freescale semiconductor 2-5 pxs20 microcontroller reference manual, rev. 1 0xfff4_8000 16 ? ls intc_0, intc_1 dp intc_0 0xffe4_0000 16 48 ls/dp linflexd_0 0xffe4_4000 16 49 ls/dp linflexd_1 0x8ff1_0000 16 ? dp mpu_1 0xfff1_0000 16 ? ls mpu_0, mpu_1 dp mpu_0 0xc3fd_c000 16 87 ls/dp mode entry module (mc_me) 0xc3ff_0000 16 92 ls/dp periodic interrupt timer (pit) 0xc3fe_8000 16 90 ls/dp power control unit (mc_pcu) 0x8ff0_0000 16 ? dp pbridge_1 0xfff0_0000 16 ? ls pbridge_0, pbridge_1 dp pbridge_0 0xc3fe_4000 16 89 ls/dp reset generation module (mc_rgm) 0xc3ff_4000 16 93 ls/dp self-test control unit (stcu) 0x8ff2_4000 16 ? dp semaphores (sema4_1) 0xfff2_4000 16 ? dp semaphores (sema4_0) 0x00f0_0000 1024 ? ls/dp shadow block 0xffe7_8000 16 62 ls/dp sine wave generator (swg) 0x8ff3_8000 16 ? dp swt_1 0xfff3_8000 16 ? ls swt_0, swt_1 dp swt_0 0x4000_0000 64 ? dp sram 128 ? ls sram 0x5000_0000 64 ? dp sram 3 0x8ff3_c000 16 ? dp stm_1 0xfff3_c000 16 ? ls stm_0, stm_1 dp stm_0 0xc3f9_0000 16 68 ls/dp system in tegration unit lite (siul) 0xc3fd_8000 16 86 ls/dp system status and configuration module (sscm) 0xc3f9_4000 16 69 ls/dp wakeup unit (wkpu) 0x8ff0_4000 16 ? dp xbar_1 0xfff0_4000 16 ? ls xbar_0, xbar_1 dp xbar_0 table 2-2. pxs20 memory map, orde red by module name (continued) start address size (kb) pctl number mode region / module name
memory map 2-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 notes: 1 dma_mux_1 is disabled in dp mode. 2 test flash memory is mapped to this address if the sctr[tfe] bit in the sscm is set (see section 48.3.1.9, sscm control register (sctr) ). 3 this range cannot be accessed by edma_0. table 2-3. sram map for pxs20 in lsm start address end address size (kb) region 1 notes: 1 access to reserved memory space can cause unexpec ted behavior. the mpu must be configured to force a deterministic action for accesses to reserved memory space. 0x4000_0000 0x4001_ffff 128 sram 0x4002_0000 0x5fff_ffff 524160 reserved table 2-4. sram map for pxs20 in dpm start address end address size (kb) region 1 notes: 1 access to reserved memory space can cause unexpec ted behavior. the mpu must be configured to force a deterministic action for accesses to reserved memory space. 0x4000_0000 0x4000_ffff 64 sram 0x4001_0000 0x4fff_ffff 262080 reserved 0x5000_0000 0x5000_ffff 64 sram 2 2 this range cannot be accessed by edma_0. 0x5001_0000 0x5fff_ffff 262080 reserved
signal description freescale semiconductor 3-1 pxs20 microcontroller reference manual, rev. 1 chapter 3 signal description this chapter describes the signals of the pxs20. 3.1 package pinouts figure 3-1 shows the 144 lqfp pinout. figure 3-1. 144 lqfp pinout figure 3-2 shows the 257 mapbga ballmap. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 nmi a[6] d[1] f[4] f[5] vdd_hv_io vss_hv_io f[6] mdo0 a[7] c[4] a[8] c[5] a[5] c[7] vdd_hv_reg_0 vss_lv_cor vdd_lv_cor f[7] f[8] vdd_hv_io vss_hv_io f[9] f[10] f[11] d[9] vdd_hv_osc vss_hv_osc xtal extal reset d[8] d[5] d[6] vss_lv_pll0_pll1 vdd_lv_pll0_pll1 a[4] vpp_test f[12] d[14] g[3] c[14] g[2] c[13] g[4] d[12] g[6] vdd_hv_fla vss_hv_fla vdd_hv_reg_1 vss_lv_cor vdd_lv_cor a[3] vdd_hv_io vss_hv_io b[4] tck tms b[5] g[5] a[2] g[7] c[12] g[8] c[11] g[9] d[11] g[10] d[10] g[11] a[1] a[0] d[7] fccu_f[0] vdd_lv_cor vss_lv_cor c[1] e[4] b[7] e[5] c[2] e[6] b[8] e[7] e[2] vdd_hv_adr0 vss_hv_adr0 b[9] b[10] b[11] b[12] vdd_hv_adr1 vss_hv_adr1 vdd_hv_adv vss_hv_adv b[13] e[9] b[15] e[10] b[14] e[11] c[0] e[12] e[0] bctrl vdd_lv_cor vss_lv_cor vdd_hv_pmu a[15] a[14] c[6] fccu_f[1] d[2] f[3] b[6] vss_lv_cor a[13] vdd_lv_cor a[9] f[0] vss_lv_cor vdd_lv_cor vdd_hv_reg_2 d[4] d[3] vss_hv_io vdd_hv_io d[0] c[15] jcomp a[12] e[15] a[11] e[14] a[10] e[13] b[3] f[14] b[2] f[15] f[13] c[10] b[1] b[0] 144 lqfp package
signal description 3-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 3-2. 257 mapbga ballmap table 3-1 and table 3-2 provide the pin function summaries for the 144-pin and 257-pin packages, respectively, listing all the si gnals multiplexed to each pin. 1234567891011121314151617 a v ss v ss v dd_hv h[2] h[0] g[14] d[3] c[15] v dd_hv a[12] h[10] h[14] a[10] b[2] c[10] v ss v ss b v ss v ss b[6] a[14] f[3] a[9] d[4] d[0] v ss h[12] e[15] e[14] b[3] f[13] b[0] v dd_hv v ss c v dd_hv nc 1 notes: 1 nc = not connected (the pin is physically not connected to anything on the device) v ss fccu_ f[1] d[2] a[13] v dd_hv v dd_hv i[0] jcomp h[11] i[1] f[14] b[1] v ss a[4] f[12] d f[5] f[4] a[15] c[6] v ss v dd_lv f[0] v dd_hv v ss nc a[11] e[13] f[15] v dd_hv v pp _test d[14] g[3] e mdo0 f[6] d[1] nmi nc c[14] g[2] i[3] f h[1] g[12] a[7] a[8] v dd_lv v dd_lv v dd_lv v dd_lv v dd_lv v dd_lv v dd_lv nc c[13] i[2] g[4] g h[3] v dd_hv c[5] a[6] v dd_lv v ss v ss v ss v ss v ss v dd_lv d[12] h[13] h[9] g[6] h g[13] v ss c[4] a[5] v dd_lv v ss v ss v ss v ss v ss v dd_lv v ss v dd_hv v dd_hv h[6] j f[7] g[15] v dd_hv v dd_hv v dd_lv v ss v ss v ss v ss v ss v dd_lv v dd_lv v dd_hv v ss h[15] k f[9] f[8] see note 2 2 pin k3 is nc on cut1 and rdy on cut2/3. c[7] v dd_lv v ss v ss v ss v ss v ss v dd_lv nc h[8] h[7] a[3] l f[10] f[11] d[9] nc v dd_lv v ss v ss v ss v ss v ss v dd_lv nc tck h[4] b[4] m v dd_hv v dd_hv d[8] nc v dd_lv v dd_lv v dd_lv v dd_lv v dd_lv v dd_lv v dd_lv c[11] b[5] tms h[5] n xtal v ss d[5] v ss_lv_ pll nc c[12] a[2] g[5] p v ss reset d[6] v dd_lv_ pll v dd_lv v ss b[8] nc v ss v dd_hv b[14] v dd_lv v ss v dd_hv g[10] g[8] g[7] r extal fccu _f[0] v ss d[7] b[7] e[6] v refp_ hv_ad0 b[10] v refp_ hv_ad1 b[13] b[15] c[0] bctrl a[1] v ss d[11] g[9] t v ss v dd_hv nc c[1] e[5] e[7] v refn_ hv_ad0 b[11] v refn_ hv_ad1 e[9] e[10] e[12] e[0] a[0] d[10] v dd_hv v ss u v ss v ss nc e[4] c[2] e[2] b[9] b[12] v dd_hv v ss e[11] nc nc v dd_hv g[11] v ss v ss 1234567891011121314151617
signal description freescale semiconductor 3-3 pxs20 microcontroller reference manual, rev. 1 table 3-1. 144 lqfp pin function summary pin # port/function peripheral ou tput function input function 1nmi ? 2 a[6] siul gpio[6] gpio[6] dspi_1 sck sck siul ? eirq[6] 3 d[1] siul gpio[49] gpio[49] etimer_1 etc[2] etc[2] ctu_0 ext_tgr ? flexray ? ca_rx 4 f[4] siul gpio[84] gpio[84] npc mdo[3] ? 5 f[5] siul gpio[85] gpio[85] npc mdo[2] ? 6v dd_hv_io ? 7v ss_hv_io ? 8 f[6] siul gpio[86] gpio[86] npc mdo[1] ? 9mdo0 ? 10 a[7] siul gpio[7] gpio[7] dspi_1 sout ? siul ? eirq[7] 11 c[4] siul gpio[36] gpio[36] dspi_0 cs0 cs0 flexpwm_0 x[1] x[1] sscm debug[4] ? siul ? eirq[22] 12 a[8] siul gpio[8] gpio[8] dspi_1 ? sin siul ? eirq[8] 13 c[5] siul gpio[37] gpio[37] dspi_0 sck sck sscm debug[5] ? flexpwm_0 ? fault[3] siul ? eirq[23]
signal description 3-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 14 a[5] siul gpio[5] gpio[5] dspi_1 cs0 cs0 etimer_1 etc[5] etc[5] dspi_0 cs7 ? siul ? eirq[5] 15 c[7] siul gpio[39] gpio[39] flexpwm_0 a[1] a[1] sscm debug[7] ? dspi_0 ? sin 16 v dd_hv_reg_0 ? 17 v ss_lv_cor ? 18 v dd_lv_cor ? 19 f[7] siul gpio[87] gpio[87] npc mcko ? 20 f[8] siul gpio[88] gpio[88] npc mseo[1] ? 21 v dd_hv_io ? 22 v ss_hv_io ? 23 f[9] siul gpio[89] gpio[89] npc mseo[0] ? 24 f[10] siul gpio[90] gpio[90] npc evto ? 25 f[11] siul gpio[91] gpio[91] npc evti ? 26 d[9] siul gpio[57] gpio[57] flexpwm_0 x[0] x[0] linflexd_1 txd ? 27 v dd_hv_osc ? 28 v ss_hv_osc ? 29 xtalin ? 30 xtalout ? 31 reset ? table 3-1. 144 lqfp pin function summary (continued) pin # port/function peripheral ou tput function input function
signal description freescale semiconductor 3-5 pxs20 microcontroller reference manual, rev. 1 32 d[8] siul gpio[56] gpio[56] dspi_1 cs2 ? etimer_1 etc[4] etc[4] dspi_0 cs5 ? flexpwm_0 ? fault[3] 33 d[5] siul gpio[53] gpio[53] dspi_0 cs3 ? flexpwm_0 ? fault[2] 34 d[6] siul gpio[54] gpio[54] dspi_0 cs2 ? flexpwm_0 x[3] x[3] flexpwm_0 ? fault[1] 35 v ss_lv_pll0_pll1 ? 36 v dd_lv_pll0_pll1 ? 37 d[7] siul gpio[55] gpio[55] dspi_1 cs3 ? dspi_0 cs4 ? swg analog output ? 38 fccu_f[0] fccu f[0] f[0] 39 v dd_lv_cor ? 40 v ss_lv_cor ? 41 c[1] siul ? gpio[33] adc_0 ? an[2] 42 e[4] siul ? gpio[68] adc_0 ? an[7] 43 b[7] siul ? gpio[23] linflexd_0 ? rxd adc_0 ? an[0] 44 e[5] siul ? gpio[69] adc_0 ? an[8] 45 c[2] siul ? gpio[34] adc_0 ? an[3] 46 e[6] siul ? gpio[70] adc_0 ? an[4] table 3-1. 144 lqfp pin function summary (continued) pin # port/function peripheral ou tput function input function
signal description 3-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 47 b[8] siul ? gpio[24] etimer_0 ? etc[5] adc_0 ? an[1] 48 e[7] siul ? gpio[71] adc_0 ? an[6] 49 e[2] siul ? gpio[66] adc_0 ? an[5] 50 v dd_hv_adr0 ? 51 v ss_hv_adr0 ? 52 b[9] siul ? gpio[25] adc_0 adc_1 ? an[11] 53 b[10] siul ? gpio[26] adc_0 adc_1 ? an[12] 54 b[11] siul ? gpio[27] adc_0 adc_1 ? an[13] 55 b[12] siul ? gpio[28] adc_0 adc_1 ? an[14] 56 v dd_hv_adr1 ? 57 v ss_hv_adr1 ? 58 v dd_hv_adv ? 59 v ss_hv_adv ? 60 b[13] siul ? gpio[29] linflexd_1 ? rxd adc_1 ? an[0] 61 e[9] siul ? gpio[73] adc_1 ? an[7] 62 b[15] siul ? gpio[31] siul ? eirq[20] adc_1 ? an[2] 63 e[10] siul ? gpio[74] adc_1 ? an[8] table 3-1. 144 lqfp pin function summary (continued) pin # port/function peripheral ou tput function input function
signal description freescale semiconductor 3-7 pxs20 microcontroller reference manual, rev. 1 64 b[14] siul ? gpio[30] etimer_0 ? etc[4] siul ? eirq[19] adc_1 ? an[1] 65 e[11] siul ? gpio[75] adc_1 ? an[4] 66 c[0] siul ? gpio[32] adc_1 ? an[3] 67 e[12] siul ? gpio[76] adc_1 ? an[6] 68 e[0] siul ? gpio[64] adc_1 ? an[5] 69 bctrl ? 70 v dd_lv_cor ? 71 v ss_lv_cor ? 72 v dd_hv_pmu ? 73 a[0] siul gpio[0] gpio[0] etimer_0 etc[0] etc[0] dspi_2 sck sck siul ? eirq[0] 74 a[1] siul gpio[1] gpio[1] etimer_0 etc[1] etc[1] dspi_2 sout ? siul ? eirq[1] 75 g[11] siul gpio[107] gpio[107] flexray dbg3 ? flexpwm_0 ? fault[3] 76 d[10] siul gpio[58] gpio[58] flexpwm_0 a[0] a[0] etimer_0 ? etc[0] 77 g[10] siul gpio[106] gpio[106] flexray dbg2 ? dspi_2 cs3 ? flexpwm_0 ? fault[2] table 3-1. 144 lqfp pin function summary (continued) pin # port/function peripheral ou tput function input function
signal description 3-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 78 d[11] siul gpio[59] gpio[59] flexpwm_0 b[0] b[0] etimer_0 ? etc[1] 79 g[9] siul gpio[105] gpio[105] flexray dbg1 ? dspi_1 cs1 ? flexpwm_0 ? fault[1] siul ? eirq[29] 80 c[11] siul gpio[43] gpio[43] etimer_0 etc[4] etc[4] dspi_2 cs2 ? 81 g[8] siul gpio[104] gpio[104] flexray dbg0 ? dspi_0 cs1 ? flexpwm_0 ? fault[0] siul ? eirq[21] 82 c[12] siul gpio[44] gpio[44] etimer_0 etc[5] etc[5] dspi_2 cs3 ? 83 g[7] siul gpio[103] gpio[103] flexpwm_0 b[3] b[3] 84 a[2] siul gpio[2] gpio[2] etimer_0 etc[2] etc[2] flexpwm_0 a[3] a[3] dspi_2 ? sin mc_rgm ? abs[0] siul ? eirq[2] 85 g[5] siul gpio[101] gpio[101] flexpwm_0 x[3] x[3] dspi_2 cs3 ? 86 b[5] siul gpio[21] gpio[21] jtagc ? tdi 87 tms ? 88 tck ? table 3-1. 144 lqfp pin function summary (continued) pin # port/function peripheral ou tput function input function
signal description freescale semiconductor 3-9 pxs20 microcontroller reference manual, rev. 1 89 b[4] siul gpio[20] gpio[20] jtagc tdo ? 90 v ss_hv_io ? 91 v dd_hv_io ? 92 a[3] siul gpio[3] gpio[3] etimer_0 etc[3] etc[3] dspi_2 cs0 cs0 flexpwm_0 b[3] b[3] mc_rgm ? abs[2] siul ? eirq[3] 93 v dd_lv_cor ? 94 v ss_lv_cor ? 95 v dd_hv_reg_1 ? 96 v ss_hv_fla ? 97 v dd_hv_fla ? 98 g[6] siul gpio[102] gpio[102] flexpwm_0 a[3] a[3] 99 d[12] siul gpio[60] gpio[60] flexpwm_0 x[1] x[1] linflexd_1 ? rxd 100 g[4] siul gpio[100] gpio[100] flexpwm_0 b[2] b[2] etimer_0 ? etc[5] 101 c[13] siul gpio[45] gpio[45] etimer_1 etc[1] etc[1] ctu_0 ? ext_in flexpwm_0 ? ext_sync 102 g[2] siul gpio[98] gpio[98] flexpwm_0 x[2] x[2] dspi_1 cs1 ? 103 c[14] siul gpio[46] gpio[46] etimer_1 etc[2] etc[2] ctu_0 ext_tgr ? table 3-1. 144 lqfp pin function summary (continued) pin # port/function peripheral ou tput function input function
signal description 3-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 104 g[3] siul gpio[99] gpio[99] flexpwm_0 a[2] a[2] etimer_0 ? etc[4] 105 d[14] siul gpio[62] gpio[62] flexpwm_0 b[1] b[1] etimer_0 ? etc[3] 106 f[12] siul gpio[92] gpio[92] etimer_1 etc[3] etc[3] siul ? eirq[30] 107 v pp_test 1 ? 108 a[4] siul gpio[4] gpio[4] etimer_1 etc[0] etc[0] dspi_2 cs1 ? etimer_0 etc[4] etc[4] mc_rgm ? fab siul ? eirq[4] 109 b[0] siul gpio[16] gpio[16] flexcan_0 txd ? etimer_1 etc[2] etc[2] sscm debug[0] ? siul ? eirq[15] 110 b[1] siul gpio[17] gpio[17] etimer_1 etc[3] etc[3] sscm debug[1] ? flexcan_0 ? rxd flexcan_1 ? rxd siul ? eirq[16] 111 c[10] siul gpio[42] gpio[42] dspi_2 cs2 ? flexpwm_0 a[3] a[3] flexpwm_0 ? fault[1] 112 f[13] siul gpio[93] gpio[93] etimer_1 etc[4] etc[4] siul ? eirq[31] table 3-1. 144 lqfp pin function summary (continued) pin # port/function peripheral ou tput function input function
signal description freescale semiconductor 3-11 pxs20 microcontroller reference manual, rev. 1 113 f[15] siul gpio[95] gpio[95] linflexd_1 ? rxd 114 b[2] siul gpio[18] gpio[18] linflexd_0 txd ? sscm debug[2] ? siul ? eirq[17] 115 f[14] siul gpio[94] gpio[94] linflexd_1 txd ? 116 b[3] siul gpio[19] gpio[19] sscm debug[3] ? linflexd_0 ? rxd 117 e[13] siul gpio[77] gpio[77] etimer_0 etc[5] etc[5] dspi_2 cs3 ? siul ? eirq[25] 118 a[10] siul gpio[10] gpio[10] dspi_2 cs0 cs0 flexpwm_0 b[0] b[0] flexpwm_0 x[2] x[2] siul ? eirq[9] 119 e[14] siul gpio[78] gpio[78] etimer_1 etc[5] etc[5] siul ? eirq[26] 120 a[11] siul gpio[11] gpio[11] dspi_2 sck sck flexpwm_0 a[0] a[0] flexpwm_0 a[2] a[2] siul ? eirq[10] 121 e[15] siul gpio[79] gpio[79] dspi_0 cs1 ? siul ? eirq[27] table 3-1. 144 lqfp pin function summary (continued) pin # port/function peripheral ou tput function input function
signal description 3-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 122 a[12] siul gpio[12] gpio[12] dspi_2 sout ? flexpwm_0 a[2] a[2] flexpwm_0 b[2] b[2] siul ? eirq[11] 123 jcomp ? ? jcomp 124 c[15] siul gpio[47] gpio[47] flexray ca_tr_en ? etimer_1 etc[0] etc[0] flexpwm_0 a[1] a[1] ctu_0 ? ext_in flexpwm_0 ? ext_sync 125 d[0] siul gpio[48] gpio[48] flexray ca_tx ? etimer_1 etc[1] etc[1] flexpwm_0 b[1] b[1] 126 v dd_hv_io ? 127 v ss_hv_io ? 128 d[3] siul gpio[51] gpio[51] flexray cb_tx ? etimer_1 etc[4] etc[4] flexpwm_0 a[3] a[3] 129 d[4] siul gpio[52] gpio[52] flexray cb_tr_en ? etimer_1 etc[5] etc[5] flexpwm_0 b[3] b[3] 130 v dd_hv_reg_2 ? 131 v dd_lv_cor ? 132 v ss_lv_cor ? 133 f[0] siul gpio[80] gpio[80] flexpwm_0 a[1] a[1] etimer_0 ? etc[2] siul ? eirq[28] table 3-1. 144 lqfp pin function summary (continued) pin # port/function peripheral ou tput function input function
signal description freescale semiconductor 3-13 pxs20 microcontroller reference manual, rev. 1 134 a[9] siul gpio[9] gpio[9] dspi_2 cs1 ? flexpwm_0 b[3] b[3] flexpwm_0 ? fault[0] 135 v dd_lv_cor ? 136 a[13] siul gpio[13] gpio[13] flexpwm_0 b[2] b[2] dspi_2 ? sin flexpwm_0 ? fault[0] siul ? eirq[12] 137 v ss_lv_cor ? 138 b[6] siul gpio[22] gpio[22] mc_cgm clk_out ? dspi_2 cs2 ? siul ? eirq[18] 139 f[3] siul gpio[83] gpio[83] dspi_0 cs6 ? 140 d[2] siul gpio[50] gpio[50] etimer_1 etc[3] etc[3] flexpwm_0 x[3] x[3] flexray ? cb_rx 141 fccu_f[1] fccu f[1] f[1] 142 c[6] siul gpio[38] gpio[38] dspi_0 sout ? flexpwm_0 b[1] b[1] sscm debug[6] ? siul ? eirq[24] 143 a[14] siul gpio[14] gpio[14] flexcan_1 txd ? etimer_1 etc[4] etc[4] siul ? eirq[13] table 3-1. 144 lqfp pin function summary (continued) pin # port/function peripheral ou tput function input function
signal description 3-14 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 144 a[15] siul gpio[15] gpio[15] etimer_1 etc[5] etc[5] flexcan_1 ? rxd flexcan_0 ? rxd siul ? eirq[14] notes: 1 v pp_test should always be tied to ground (v ss ) for normal operations. table 3-2. 257 mapbga pin function summary pin # port/function peripheral ou tput function input function a1 v ss_hv_io_ring ? a2 v ss_hv_io_ring ? a3 v dd_hv_io_ring ? a4 h[2] siul gpio[114] gpio[114] npc mdo[5] ? a5 h[0] siul gpio[112] gpio[112] npc mdo[7] ? a6 g[14] siul gpio[110] gpio[110] npc mdo[9] ? a7 d[3] siul gpio[51] gpio[51] flexray cb_tx ? etimer_1 etc[4] etc[4] flexpwm_0 a[3] a[3] a8 c[15] siul gpio[47] gpio[47] flexray ca_tr_en ? etimer_1 etc[0] etc[0] flexpwm_0 a[1] a[1] ctu_0 ? ext_in flexpwm_0 ? ext_sync a9 v dd_hv_io_ring ? table 3-1. 144 lqfp pin function summary (continued) pin # port/function peripheral ou tput function input function
signal description freescale semiconductor 3-15 pxs20 microcontroller reference manual, rev. 1 a10 a[12] siul gpio[12] gpio[12] dspi_2 sout ? flexpwm_0 a[2] a[2] flexpwm_0 b[2] b[2] siul ? eirq[11] a11 h[10] siul gpio[122] gpio[122] flexpwm_1 x[2] x[2] etimer_2 etc[2] etc[2] a12 h[14] siul gpio[126] gpio[126] flexpwm_1 a[3] a[3] etimer_2 etc[4] etc[4] a13 a[10] siul gpio[10] gpio[10] dspi_2 cs0 cs0 flexpwm_0 b[0] b[0] flexpwm_0 x[2] x[2] siul ? eirq[9] a14 b[2] siul gpio[18] gpio[18] linflexd_0 txd ? sscm debug[2] ? siul ? eirq[17] a15 c[10] siul gpio[42] gpio[42] dspi_2 cs2 ? flexpwm_0 a[3] a[3] flexpwm_0 ? fault[1] a16 v ss_hv_io_ring ? a17 v ss_hv_io_ring ? b1 v ss_hv_io_ring ? b2 v ss_hv_io_ring ? b3 b[6] siul gpio[22] gpio[22] mc_cgm clk_out ? dspi_2 cs2 ? siul ? eirq[18] table 3-2. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
signal description 3-16 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 b4 a[14] siul gpio[14] gpio[14] flexcan_1 txd ? etimer_1 etc[4] etc[4] siul ? eirq[13] b5 f[3] siul gpio[83] gpio[83] dspi_0 cs6 ? b6 a[9] siul gpio[9] gpio[9] dspi_2 cs1 ? flexpwm_0 b[3] b[3] flexpwm_0 ? fault[0] b7 d[4] siul gpio[52] gpio[52] flexray cb_tr_en ? etimer_1 etc[5] etc[5] flexpwm_0 b[3] b[3] b8 d[0] siul gpio[48] gpio[48] flexray ca_tx ? etimer_1 etc[1] etc[1] flexpwm_0 b[1] b[1] b9 v ss_hv_io_ring ? b10 h[12] siul gpio[124] gpio[124] flexpwm_1 b[2] b[2] b11 e[15] siul gpio[79] gpio[79] dspi_0 cs1 ? siul ? eirq[27] b12 e[14] siul gpio[78] gpio[78] etimer_1 etc[5] etc[5] siul ? eirq[26] b13 b[3] siul gpio[19] gpio[19] sscm debug[3] ? linflexd_0 ? rxd b14 f[13] siul gpio[93] gpio[93] etimer_1 etc[4] etc[4] siul ? eirq[31] table 3-2. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
signal description freescale semiconductor 3-17 pxs20 microcontroller reference manual, rev. 1 b15 b[0] siul gpio[16] gpio[16] flexcan_0 txd ? etimer_1 etc[2] etc[2] sscm debug[0] ? siul ? eirq[15] b16 v dd_hv_io_ring ? b17 v ss_hv_io_ring ? c1 v dd_hv_io_ring ? c2 not connected ? c3 v ss_hv_io_ring ? c4 fccu_f[1] fccu f[1] f[1] c5 d[2] siul gpio[50] gpio[50] etimer_1 etc[3] etc[3] flexpwm_0 x[3] x[3] flexray ? cb_rx c6 a[13] siul gpio[13] gpio[13] flexpwm_0 b[2] b[2] dspi_2 ? sin flexpwm_0 ? fault[0] siul ? eirq[12] c7 v dd_hv_reg_2 ? c8 v dd_hv_reg_2 ? c9 i[0] siul gpio[128] gpio[128] etimer_2 etc[0] etc[0] dspi_0 cs4 ? flexpwm_1 ? fault[0] c10 jcomp ? ? jcomp c11 h[11] siul gpio[123] gpio[123] flexpwm_1 a[2] a[2] c12 i[1] siul gpio[129] gpio[129] etimer_2 etc[1] etc[1] dspi_0 cs5 ? flexpwm_1 ? fault[1] c13 f[14] siul gpio[94] gpio[94] linflexd_1 txd ? table 3-2. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
signal description 3-18 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 c14 b[1] siul gpio[17] gpio[17] etimer_1 etc[3] etc[3] sscm debug[1] ? flexcan_0 ? rxd flexcan_1 ? rxd siul ? eirq[16] c15 v ss_hv_io_ring ? c16 a[4] siul gpio[4] gpio[4] etimer_1 etc[0] etc[0] dspi_2 cs1 ? etimer_0 etc[4] etc[4] mc_rgm ? fab siul ? eirq[4] c17 f[12] siul gpio[92] gpio[92] etimer_1 etc[3] etc[3] siul ? eirq[30] d1 f[5] siul gpio[85] gpio[85] npc mdo[2] ? d2 f[4] siul gpio[84] gpio[84] npc mdo[3] ? d3 a[15] siul gpio[15] gpio[15] etimer_1 etc[5] etc[5] flexcan_1 ? rxd flexcan_0 ? rxd siul ? eirq[14] d4 c[6] siul gpio[38] gpio[38] dspi_0 sout ? flexpwm_0 b[1] b[1] sscm debug[6] ? siul ? eirq[24] d5 v ss_lv_core_ring ? d6 v dd_lv_core_ring ? table 3-2. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
signal description freescale semiconductor 3-19 pxs20 microcontroller reference manual, rev. 1 d7 f[0] siul gpio[80] gpio[80] flexpwm_0 a[1] a[1] etimer_0 ? etc[2] siul ? eirq[28] d8 v dd_hv_io_ring ? d9 v ss_hv_io_ring ? d10 not connected ? d11 a[11] siul gpio[11] gpio[11] dspi_2 sck sck flexpwm_0 a[0] a[0] flexpwm_0 a[2] a[2] siul ? eirq[10] d12 e[13] siul gpio[77] gpio[77] etimer_0 etc[5] etc[5] dspi_2 cs3 ? siul ? eirq[25] d13 f[15] siul gpio[95] gpio[95] linflexd_1 ? rxd d14 v dd_hv_io_ring ? d15 v pp_test 1 ? d16 d[14] siul gpio[62] gpio[62] flexpwm_0 b[1] b[1] etimer_0 ? etc[3] d17 g[3] siul gpio[99] gpio[99] flexpwm_0 a[2] a[2] etimer_0 ? etc[4] e1 mdo0 ? e2 f[6] siul gpio[86] gpio[86] npc mdo[1] ? e3 d[1] siul gpio[49] gpio[49] etimer_1 etc[2] etc[2] ctu_0 ext_tgr ? flexray ? ca_rx e4 nmi ? e14 not connected ? table 3-2. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
signal description 3-20 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 e15 c[14] siul gpio[46] gpio[46] etimer_1 etc[2] etc[2] ctu_0 ext_tgr ? e16 g[2] siul gpio[98] gpio[98] flexpwm_0 x[2] x[2] dspi_1 cs1 ? e17 i[3] siul gpio[131] gpio[131] etimer_2 etc[3] etc[3] dspi_0 cs7 ? ctu_0 ext_tgr ? flexpwm_1 ? fault[3] f1 h[1] siul gpio[113] gpio[113] npc mdo[6] ? f2 g[12] siul gpio[108] gpio[108] npc mdo[11] ? f3 a[7] siul gpio[7] gpio[7] dspi_1 sout ? siul ? eirq[7] f4 a[8] siul gpio[8] gpio[8] dspi_1 ? sin siul ? eirq[8] f6 v dd_lv_core_ring ? f7 v dd_lv_core_ring ? f8 v dd_lv_core_ring ? f9 v dd_lv_core_ring ? f10 v dd_lv_core_ring ? f11 v dd_lv_core_ring ? f12 v dd_lv_core_ring ? f14 not connected ? f15 c[13] siul gpio[45] gpio[45] etimer_1 etc[1] etc[1] ctu_0 ? ext_in flexpwm_0 ? ext_sync table 3-2. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
signal description freescale semiconductor 3-21 pxs20 microcontroller reference manual, rev. 1 f16 i[2] siul gpio[130] gpio[130] etimer_2 etc[2] etc[2] dspi_0 cs6 ? flexpwm_1 ? fault[2] f17 g[4] siul gpio[100] gpio[100] flexpwm_0 b[2] b[2] etimer_0 ? etc[5] g1 h[3] siul gpio[115] gpio[115] npc mdo[4] ? g2 v dd_hv_io_ring ? g3 c[5] siul gpio[37] gpio[37] dspi_0 sck sck sscm debug[5] ? flexpwm_0 ? fault[3] siul ? eirq[23] g4 a[6] siul gpio[6] gpio[6] dspi_1 sck sck siul ? eirq[6] g6 v dd_lv_core_ring ? g7 v ss_lv_core_ring ? g8 v ss_lv_core_ring ? g9 v ss_lv_core_ring ? g10 v ss_lv_core_ring ? g11 v ss_lv_core_ring ? g12 v dd_lv_core_ring ? g14 d[12] siul gpio[60] gpio[60] flexpwm_0 x[1] x[1] linflexd_1 ? rxd g15 h[13] siul gpio[125] gpio[125] flexpwm_1 x[3] x[3] etimer_2 etc[3] etc[3] g16 h[9] siul gpio[121] gpio[121] flexpwm_1 b[1] b[1] dspi_0 cs7 ? table 3-2. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
signal description 3-22 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 g17 g[6] siul gpio[102] gpio[102] flexpwm_0 a[3] a[3] h1 g[13] siul gpio[109] gpio[109] npc mdo[10] ? h2 v ss_hv_io_ring ? h3 c[4] siul gpio[36] gpio[36] dspi_0 cs0 cs0 flexpwm_0 x[1] x[1] sscm debug[4] ? siul ? eirq[22] h4 a[5] siul gpio[5] gpio[5] dspi_1 cs0 cs0 etimer_1 etc[5] etc[5] dspi_0 cs7 ? siul ? eirq[5] h6 v dd_lv ? h7 v ss_lv ? h8 v ss_lv ? h9 v ss_lv ? h10 v ss_lv ? h11 v ss_lv ? h12 v dd_lv ? h14 v ss_lv ? h15 v dd_hv_reg_1 ? h16 v dd_hv_fla ? h17 h[6] siul gpio[118] gpio[118] flexpwm_1 b[0] b[0] dspi_0 cs5 ? j1 f[7] siul gpio[87] gpio[87] npc mcko ? j2 g[15] siul gpio[111] gpio[111] npc mdo[8] ? j3 v dd_hv_reg_0 ? j4 v dd_hv_reg_0 ? j6 v dd_lv ? table 3-2. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
signal description freescale semiconductor 3-23 pxs20 microcontroller reference manual, rev. 1 j7 v ss_lv ? j8 v ss_lv ? j9 v ss_lv ? j10 v ss_lv ? j11 v ss_lv ? j12 v dd_lv ? j14 v dd_lv ? j15 v dd_hv_reg_1 ? j16 v ss_hv_fla ? j17 h[15] siul gpio[127] gpio[127] flexpwm_1 b[3] b[3] etimer_2 etc[5] etc[5] k1 f[9] siul gpio[89] gpio[89] npc mseo[0] ? k2 f[8] siul gpio[88] gpio[88] npc mseo[1] ? k3 (cut1) not connected ? k3 (cut2/3) rdy npc rdy ? siul gpio[132] gpio[132] k4 c[7] siul gpio[39] gpio[39] flexpwm_0 a[1] a[1] sscm debug[7] ? dspi_0 ? sin k6 v dd_lv ? k7 v ss_lv ? k8 v ss_lv ? k9 v ss_lv ? k10 v ss_lv ? k11 v ss_lv ? k12 v dd_lv ? k14 not connected ? k15 h[8] siul gpio[120] gpio[120] flexpwm_1 a[1] a[1] dspi_0 cs6 ? table 3-2. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
signal description 3-24 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 k16 h[7] siul gpio[119] gpio[119] flexpwm_1 x[1] x[1] etimer_2 etc[1] etc[1] k17 a[3] siul gpio[3] gpio[3] etimer_0 etc[3] etc[3] dspi_2 cs0 cs0 flexpwm_0 b[3] b[3] mc_rgm ? abs[2] siul ? eirq[3] l1 f[10] siul gpio[90] gpio[90] npc evto ? l2 f[11] siul gpio[91] gpio[91] npc evti ? l3 d[9] siul gpio[57] gpio[57] flexpwm_0 x[0] x[0] linflexd_1 txd ? l4 not connected ? l6 v dd_lv ? l7 v ss_lv ? l8 v ss_lv ? l9 v ss_lv ? l10 v ss_lv ? l11 v ss_lv ? l12 v dd_lv ? l14 not connected ? l15 tck ? l16 h[4] siul gpio[116] gpio[116] flexpwm_1 x[0] x[0] etimer_2 etc[0] etc[0] l17 b[4] siul gpio[20] gpio[20] jtagc tdo ? m1 v dd_hv_osc ? m2 v dd_hv_io_ring ? table 3-2. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
signal description freescale semiconductor 3-25 pxs20 microcontroller reference manual, rev. 1 m3 d[8] siul gpio[56] gpio[56] dspi_1 cs2 ? etimer_1 etc[4] etc[4] dspi_0 cs5 ? flexpwm_0 ? fault[3] m4 not connected ? m6 v dd_lv ? m7 v dd_lv ? m8 v dd_lv ? m9 v dd_lv ? m10 v dd_lv ? m11 v dd_lv ? m12 v dd_lv ? m14 c[11] siul gpio[43] gpio[43] etimer_0 etc[4] etc[4] dspi_2 cs2 ? m15 b[5] siul gpio[21] gpio[21] jtagc ? tdi m16 tms ? m17 h[5] siul gpio[117] gpio[117] flexpwm_1 a[0] a[0] dspi_0 cs4 ? n1 xtalin ? n2 v ss_hv_io_ring ? n3 d[5] siul gpio[53] gpio[53] dspi_0 cs3 ? flexpwm_0 ? fault[2] n4 v ss_lv_pll0_pll1 ? n14 not connected ? n15 c[12] siul gpio[44] gpio[44] etimer_0 etc[5] etc[5] dspi_2 cs3 ? table 3-2. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
signal description 3-26 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 n16 a[2] siul gpio[2] gpio[2] etimer_0 etc[2] etc[2] flexpwm_0 a[3] a[3] dspi_2 ? sin mc_rgm ? abs[0] siul ? eirq[2] n17 g[5] siul gpio[101] gpio[101] flexpwm_0 x[3] x[3] dspi_2 cs3 ? p1 v ss_hv_osc ? p2 reset ? p3 d[6] siul gpio[54] gpio[54] dspi_0 cs2 ? flexpwm_0 x[3] x[3] flexpwm_0 ? fault[1] p4 v dd_lv_pll0_pll1 ? p5 v dd_lv_core_ring ? p6 v ss_lv_core_ring ? p7 b[8] siul ? gpio[24] etimer_0 ? etc[5] adc_0 ? an[1] p8 not connected ? p9 v ss_hv_io_ring ? p10 v dd_hv_io_ring ? p11 b[14] siul ? gpio[30] etimer_0 ? etc[4] siul ? eirq[19] adc_1 ? an[1] p12 v dd_lv_core_ring ? p13 v ss_lv_core_ring ? p14 v dd_hv_io_ring ? p15 g[10] siul gpio[106] gpio[106] flexray dbg2 ? dspi_2 cs3 ? flexpwm_0 ? fault[2] table 3-2. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
signal description freescale semiconductor 3-27 pxs20 microcontroller reference manual, rev. 1 p16 g[8] siul gpio[104] gpio[104] flexray dbg0 ? dspi_0 cs1 ? flexpwm_0 ? fault[0] siul ? eirq[21] p17 g[7] siul gpio[103] gpio[103] flexpwm_0 b[3] b[3] r1 xtalout ? r2 fccu_f[0] fccu f[0] f[0] r3 v ss_hv_io_ring ? r4 d[7] siul gpio[55] gpio[55] dspi_1 cs3 ? dspi_0 cs4 ? swg analog output ? r5 b[7] siul ? gpio[23] linflexd_0 ? rxd adc_0 ? an[0] r6 e[6] siul ? gpio[70] adc_0 ? an[4] r7 v dd_hv_adr0 ? r8 b[10] siul ? gpio[26] adc_0 adc_1 ? an[12] r9 v dd_hv_adr1 ? r10 b[13] siul ? gpio[29] linflexd_1 ? rxd adc_1 ? an[0] r11 b[15] siul ? gpio[31] siul ? eirq[20] adc_1 ? an[2] r12 c[0] siul ? gpio[32] adc_1 ? an[3] r13 bctrl ? table 3-2. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
signal description 3-28 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 r14 a[1] siul gpio[1] gpio[1] etimer_0 etc[1] etc[1] dspi_2 sout ? siul ? eirq[1] r15 v ss_hv_io_ring ? r16 d[11] siul gpio[59] gpio[59] flexpwm_0 b[0] b[0] etimer_0 ? etc[1] r17 g[9] siul gpio[105] gpio[105] flexray dbg1 ? dspi_1 cs1 ? flexpwm_0 ? fault[1] siul ? eirq[29] t1 v ss_hv_io_ring ? t2 v dd_hv_io_ring ? t3 not connected ? t4 c[1] siul ? gpio[33] adc_0 ? an[2] t5 e[5] siul ? gpio[69] adc_0 ? an[8] t6 e[7] siul ? gpio[71] adc_0 ? an[6] t7 v ss_hv_adr0 ? t8 b[11] siul ? gpio[27] adc_0 adc_1 ? an[13] t9 v ss_hv_adr1 ? t10 e[9] siul ? gpio[73] adc_1 ? an[7] t11 e[10] siul ? gpio[74] adc_1 ? an[8] t12 e[12] siul ? gpio[76] adc_1 ? an[6] t13 e[0] siul ? gpio[64] adc_1 ? an[5] table 3-2. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
signal description freescale semiconductor 3-29 pxs20 microcontroller reference manual, rev. 1 t14 a[0] siul gpio[0] gpio[0] etimer_0 etc[0] etc[0] dspi_2 sck sck siul ? eirq[0] t15 d[10] siul gpio[58] gpio[58] flexpwm_0 a[0] a[0] etimer_0 ? etc[0] t16 v dd_hv_io_ring ? t17 v ss_hv_io_ring ? u1 v ss_hv_io_ring ? u2 v ss_hv_io_ring ? u3 not connected ? u4 e[4] siul ? gpio[68] adc_0 ? an[7] u5 c[2] siul ? gpio[34] adc_0 ? an[3] u6 e[2] siul ? gpio[66] adc_0 ? an[5] u7 b[9] siul ? gpio[25] adc_0 adc_1 ? an[11] u8 b[12] siul ? gpio[28] adc_0 adc_1 ? an[14] u9 v dd_hv_adv ? u10 v ss_hv_adv ? u11 e[11] siul ? gpio[75] adc_1 ? an[4] u12 not connected ? u13 not connected ? u14 v dd_hv_pmu ? table 3-2. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
signal description 3-30 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 3.2 supply pins u15 g[11] siul gpio[107] gpio[107] flexray dbg3 ? flexpwm_0 ? fault[3] u16 v ss_hv_io_ring ? u17 v ss_hv_io_ring ? notes: 1 v pp_test should always be tied to ground (v ss ) for normal operations. table 3-3. supply pins supply pin # symbol description 144 pkg 257 pkg vreg control and power supply pins bctrl voltage regulator external npn ballast base control pin 69 r13 v dd_lv_cor core logic supply 70 vdd_lv 1 v ss_lv_cor core regulator ground 71 vss_lv 2 v dd_hv_pmu voltage regulator supply 72 u14 adc_0/adc_1 reference voltage and adc supply v dd_hv_adr0 adc_0 high reference voltage 50 r7 v ss_hv_adr0 adc_0 low reference voltage 51 t7 v dd_hv_adr1 adc_1 high reference voltage 56 r9 v ss_hv_adr1 adc_1 low reference voltage 57 t9 v dd_hv_adv adc voltage supply for adc_0 and adc_1 58 u9 v ss_hv_adv adc ground for adc_0 and adc_1 59 u10 power supply pins (3.3 v) v dd_hv_io 3.3 v input/output supply voltage 6 vdd_hv 3 v ss_hv_io 3.3 v input/output ground 7 vss_hv 4 v dd_hv_reg_0 vdd_hv_reg_0 16 j3 v dd_hv_io 3.3 v input/output supply voltage 21 vdd_hv 3 v ss_hv_io 3.3 v input/output ground 22 vss_hv 4 v dd_hv_osc crystal oscillator amplifier supply voltage 27 m1 v ss_hv_osc crystal oscillator amplifier ground 28 p1 v ss_hv_io 3.3 v input/output ground 90 vss_hv 4 table 3-2. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
signal description freescale semiconductor 3-31 pxs20 microcontroller reference manual, rev. 1 v dd_hv_io 3.3 v input/output supply voltage 91 vdd_hv 3 v dd_hv_reg_1 vdd_hv_reg_1 95 h15 v ss_hv_fla vss_hv_fla 96 j16 v dd_hv_fla vdd_hv_fla 97 h16 v dd_hv_io vdd_hv_io 126 vdd_hv 3 v ss_hv_io vss_hv_io 127 vss_hv 4 v dd_hv_reg_2 vdd_hv_reg_2 130 c7 power supply pins (1.2 v) v ss_lv_cor vss_lv_cor decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 17 vss_hv 2 v dd_lv_cor vdd_lv_cor decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v ss_lv_cor pin. 18 vdd_lv 1 v ss 1v2 vss_lv_pll0_pll1 / 1.2 v decoupling pins for on-chip fmpll modules. decoupling capacitor must be connected between this pin and v dd_lv_pll. 35 n4 v dd 1v2 vdd_lv_pll0_pll1 decoupling pins for on-chip fmpll modules. decoupling capacitor must be connected between this pin and v ss_lv_pll. 36 p4 v dd_lv_cor vdd_lv_cor decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v ss_lv_cor pin. 39 vdd_lv 1 v ss_lv_cor vss_lv_cor decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 40 vss_lv 2 v dd_lv_cor vdd_lv_cor decoupling pins for core logic and regulator feedback. decoupling capacitor must be connected between this pins and v ss_lv_regcor. 70 vdd_lv 1 v ss_lv_cor vss_lv_regcor0 decoupling pins for core logic and regulator feedback. decoupling capacitor must be connected between this pins and v dd_lv_regcor. 71 vss_lv 2 v dd_lv_cor vdd_lv_cor decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v ss_lv_cor pin. 93 vdd_lv 1 v ss_lv_cor vss_lv_cor / 1.2 v decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 94 vss_lv 2 table 3-3. supply pins (continued) supply pin # symbol description 144 pkg 257 pkg
signal description 3-32 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 3.3 system pins v dd 1v2 vdd_lv_cor decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 131 vdd_lv 1 v ss 1v2 vss_lv_cor decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 132 vss_lv 2 v dd 1v2 vdd_lv_cor / decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 135 vdd_lv 1 v ss 1v2 vss_lv_cor / decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 137 vss_lv 2 notes: 1 vdd_lv balls are tied together on the 257 mapbga substrate. 2 vss_lv balls are tied together on the 257 mapbga substrate. 3 vdd_hv balls are tied together on the 257 mapbga substrate. 4 vss_hv balls are tied together on t he 257 mapbga substrate. table 3-4. system pins symbol description direction pin # 144 pkg 257 pkg dedicated pins mdo0 1 nexus message data output ? line output only 9 e1 nmi 2 non maskable interrupt input only 1 e4 xtal input for oscillator amplifier circuit and internal clock generator input only 29 n1 extal oscillator amplifier output output only 30 r1 tms 2 jtag state machine control input only 87 m16 tck 2 jtag clock input only 88 l15 jcomp 3 jtag compliance select input only 123 c10 table 3-3. supply pins (continued) supply pin # symbol description 144 pkg 257 pkg
signal description freescale semiconductor 3-33 pxs20 microcontroller reference manual, rev. 1 note none of system pins (except res et) provides an open drain output. 3.4 pin muxing table 3-5 defines the pin list and muxing for this device. each entry of table 3-5 shows all the possible confi gurations for each pin, via the alternate functions. the default function assigned to each pin after reset is indicated by alt0. note pins labeled ?nc? are to be left unc onnected. any connectio n to an external circuit or voltage may cause unpredic table device beha vior or damage. pins labeled ?reserved? are to be tied to ground. not doing so may cause unpredictable device behavior. reset pin reset bidirectional reset with schmitt-trigger characteristics and noise filter. this pin has medium drive strength. output drive is open drain and must be terminated by an external resistor of value 1kohm bidirectional 31 p2 test pin vpp test pin for testing purpose only. to be tied to ground in normal operating mode. 107 d15 notes: 1 this pad is configured for fast (f) pad speed. 2 this pad contains a weak pull-up. 3 this pad contains a weak pull-down. table 3-4. system pins (continued) symbol description direction pin # 144 pkg 257 pkg
pxs20 microcontroller refe rence manual, rev. 1 pin muxing freescale semiconductor 3-34 table 3-5. pin muxing port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg port a a[0] pcr[0] siul gpio[0] alt0 gpio[0] ? ? m s 73 t14 etimer_0 etc[0] alt1 etc[0] psmi[35]; padsel=0 dspi_2 sck alt2 sck psmi[1]; padsel=0 siul ? ? eirq[0] ? a[1] pcr[1] siul gpio[1] alt0 gpio[1] ? ? m s 74 r14 etimer_0 etc[1] alt1 etc[1] psmi[36]; padsel=0 dspi_2 sout alt2 ? ? siul ? ? eirq[1] ? a[2] pcr[2] siul gpio[2] alt0 gpio[2] ? pull down m s 84 n16 etimer_0 etc[2] alt1 etc[2] psmi[37]; padsel=0 flexpwm_0 a[3] alt3 a[3] psmi[23]; padsel=0 dspi_2 ? ? sin psmi[2]; padsel=0 mc_rgm ? ? abs[0] ? siul ? ? eirq[2] ?
signal description freescale semiconductor 3-35 pxs20 microcontroller refe rence manual, rev. 1 a[3] pcr[3] siul gpio[3] alt0 gpio[3] ? pull down m s 92 k17 etimer_0 etc[3] alt1 etc[3] psmi[38]; padsel=0 dspi_2 cs0 alt2 cs0 psmi[3]; padsel=0 flexpwm_0 b[3] alt3 b[3] psmi[27]; padsel=0 mc_rgm ? ? abs[2] ? siul ? ? eirq[3] ? a[4] pcr[4] siul gpio[4] alt0 gpio[4] ? pull down m s 108 c16 etimer_1 etc[0] alt1 etc[0] psmi[9]; padsel=0 dspi_2 cs1 alt2 ? ? etimer_0 etc[4] alt3 etc[4] psmi[7]; padsel=0 mc_rgm ? ? fab ? siul ? ? eirq[4] ? a[5] pcr[5] siul gpio[5] alt0 gpio[5] ? ? m s 14 h4 dspi_1 cs0 alt1 cs0 ? etimer_1 etc[5] alt2 etc[5] psmi[14]; padsel=0 dspi_0 cs7 alt3 ? ? siul ? ? eirq[5] ? a[6] pcr[6] siul gpio[6] alt0 gpio[6] ? ? m s 2 g4 dspi_1 sck alt1 sck ? siul ? ? eirq[6] ? table 3-5. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
pxs20 microcontroller refe rence manual, rev. 1 pin muxing freescale semiconductor 3-36 a[7] pcr[7] siul gpio[7] alt0 gpio[7] ? ? m s 10 f3 dspi_1 sout alt1 ? ? siul ? ? eirq[7] ? a[8] pcr[8] siul gpio[8] alt0 gpio[8] ? ? m s 12 f4 dspi_1 ? ? sin ? siul ? ? eirq[8] ? a[9] pcr[9] siul gpio[9] alt0 gpio[9] ? ? m s 134 b6 dspi_2 cs1 alt1 ? ? flexpwm_0 b[3] alt3 b[3] psmi[27]; padsel=1 flexpwm_0 ? ? fault[0] psmi[16]; padsel=0 a[10] pcr[10] siul gpio[10] alt0 gpio[10] ? ? m s 118 a13 dspi_2 cs0 alt1 cs0 psmi[3]; padsel=1 flexpwm_0 b[0] alt2 b[0] psmi[24]; padsel=0 flexpwm_0 x[2] alt3 x[2] psmi[29]; padsel=0 siul ? ? eirq[9] ? a[11] pcr[11] siul gpio[11] alt0 gpio[11] ? ? m s 120 d11 dspi_2 sck alt1 sck psmi[1]; padsel=1 flexpwm_0 a[0] alt2 a[0] psmi[20]; padsel=0 flexpwm_0 a[2] alt3 a[2] psmi[22]; padsel=0 siul ? ? eirq[10] ? table 3-5. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
signal description freescale semiconductor 3-37 pxs20 microcontroller refe rence manual, rev. 1 a[12] pcr[12] siul gpio[12] alt0 gpio[12] ? ? m s 122 a10 dspi_2 sout alt1 ? ? flexpwm_0 a[2] alt2 a[2] psmi[22]; padsel=1 flexpwm_0 b[2] alt3 b[2] psmi[26]; padsel=0 siul ? ? eirq[11] ? a[13] pcr[13] siul gpio[13] alt0 gpio[13] ? ? m s 136 c6 flexpwm_0 b[2] alt2 b[2] psmi[26]; padsel=1 dspi_2 ? ? sin psmi[2]; padsel=1 flexpwm_0 ? ? fault[0] psmi[16]; padsel=1 siul ? ? eirq[12] ? a[14] pcr[14] siul gpio[14] alt0 gpio[14] ? ? m s 143 b4 flexcan_1 txd alt1 ? ? etimer_1 etc[4] alt2 etc[4] psmi[13]; padsel=0 siul ? ? eirq[13] ? a[15] pcr[15] siul gpio[15] alt0 gpio[15] ? ? m s 144 d3 etimer_1 etc[5] alt2 etc[5] psmi[14]; padsel=1 flexcan_1 ? ? rxd psmi[34]; padsel=0 flexcan_0 ? ? rxd psmi[33]; padsel=0 siul ? ? eirq[14] ? table 3-5. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
pxs20 microcontroller refe rence manual, rev. 1 pin muxing freescale semiconductor 3-38 port b b[0] pcr[16] siul gpio[16] alt0 gpio[16] ? ? m s 109 b15 flexcan_0 txd alt1 ? ? etimer_1 etc[2] alt2 etc[2] psmi[11]; padsel=0 sscm debug[0] alt3 ? ? siul ? ? eirq[15] ? b[1] pcr[17] siul gpio[17] alt0 gpio[17] ? ? m s 110 c14 etimer_1 etc[3] alt2 etc[3] psmi[12]; padsel=0 sscm debug[1] alt3 ? ? flexcan_0 ? ? rxd psmi[33]; padsel=1 flexcan_1 ? ? rxd psmi[34]; padsel=1 siul ? ? eirq[16] ? b[2] pcr[18] siul gpio[18] alt0 gpio[18] ? ? m s 114 a14 linflex_0 txd alt1 ? ? sscm debug[2] alt3 ? ? siul ? ? eirq[17] ? b[3] pcr[19] siul gpio[19] alt0 gpio[19] ? ? m s 116 b13 sscm debug[3] alt3 ? ? linflex_0 ? ? rxd psmi[31]; padsel=0 b[4] 2 pcr[20] siul gpio[20] alt0 gpio[20] ? ? f s 89 l17 jtagc tdo alt1 ? ? table 3-5. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
signal description freescale semiconductor 3-39 pxs20 microcontroller refe rence manual, rev. 1 b[5] pcr[21] siul gpio[21] alt0 gpio[21] ? pull up m s 86 m15 jtagc ? ? tdi ? b[6] pcr[22] siul gpio[22] alt0 gpio[22] ? ? f s 138 b3 mc_cgm clk_out alt1 ? ? dspi_2 cs2 alt2 ? ? siul ? eirq[18] ? b[7] pcr[23] siul ? alt0 gpi[23] ? ? ? ? 43 r5 linflex_0 ? ? rxd psmi[31]; padsel=1 adc_0 ? ? an[0] 3 ? b[8] pcr[24] siul ? alt0 gpi[24] ? ? ? ? 47 p7 etimer_0 ? ? etc[5] psmi[8]; padsel=2 adc_0 ? ? an[1] 3 ? b[9] pcr[25] siul ? alt0 gpi[25] ? ? ? ? 52 u7 adc_0 adc_1 ? ? an[11] 3 ? b[10] pcr[26] siul ? alt0 gpi[26] ? ? ? ? 53 r8 adc_0 adc_1 ? ? an[12] 3 ? b[11] pcr[27] siul ? alt0 gpi[27] ? ? ? ? 54 t8 adc_0 adc_1 ? ? an[13] 3 ? b[12] pcr[28] siul ? alt0 gpi[28] ? ? ? ? 55 u8 adc_0 adc_1 ? ? an[14] 3 ? table 3-5. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
pxs20 microcontroller refe rence manual, rev. 1 pin muxing freescale semiconductor 3-40 b[13] pcr[29] siul ? alt0 gpi[29] ? ? ? ? 60 r10 linflex_1 ? ? rxd psmi[32]; padsel=0 adc_1 ? ? an[0] 3 ? b[14] pcr[30] siul ? alt0 gpi[30] ? ? ? ? 64 p11 etimer_0 ? ? etc[4] psmi[7]; padsel=2 siul ? ? eirq[19] ? adc_1 ? ? an[1] 3 ? b[15] pcr[31] siul ? alt0 gpi[31] ? ? ? ? 62 r11 siul ? ? eirq[20] ? adc_1 ? ? an[2] 3 ? port c c[0] pcr[32] siul ? alt0 gpi[32] ? ? ? ? 66 r12 adc_1 ? ? an[3] 3 ? c[1] pcr[33] siul ? alt0 gpi[33] ? ? ? ? 41 t4 adc_0 ? ? an[2] 3 ? c[2] pcr[34] siul ? alt0 gpi[34] ? ? ? ? 45 u5 adc_0 ? ? an[3] 3 ? c[4] pcr[36] siul gpio[36] alt0 gpio[36] ? ? m s 11 h3 dspi_0 cs0 alt1 cs0 ? flexpwm_0 x[1] alt2 x[1] psmi[28]; padsel=0 sscm debug[4] alt3 ? ? siul ? ? eirq[22] ? table 3-5. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
signal description freescale semiconductor 3-41 pxs20 microcontroller refe rence manual, rev. 1 c[5] pcr[37] siul gpio[37] alt0 gpio[37] ? ? m s 13 g3 dspi_0 sck alt1 sck ? sscm debug[5] alt3 ? ? flexpwm_0 ? ? fault[3] psmi[19]; padsel=0 siul ? ? eirq[23] ? c[6] pcr[38] siul gpio[38] alt0 gpio[38] ? ? m s 142 d4 dspi_0 sout alt1 ? ? flexpwm_0 b[1] alt2 b[1] psmi[25]; padsel=0 sscm debug[6] alt3 ? ? siul ? ? eirq[24] ? c[7] pcr[39] siul gpio[39] alt0 gpio[39] ? ? m s 15 k4 flexpwm_0 a[1] alt2 a[1] psmi[21]; padsel=0 sscm debug[7] alt3 ? ? dspi_0 ? ? sin ? c[10] pcr[42] siul gpio[42] alt0 gpio[42] ? ? m s 111 a15 dspi_2 cs2 alt1 ? ? flexpwm_0 a[3] alt3 a[3] psmi[23]; padsel=1 flexpwm_0 ? ? fault[1] psmi[17]; padsel=0 c[11] pcr[43] siul gpio[43] alt0 gpio[43] ? ? m s 80 m14 etimer_0 etc[4] alt1 etc[4] psmi[7]; padsel=1 dspi_2 cs2 alt2 ? ? table 3-5. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
pxs20 microcontroller refe rence manual, rev. 1 pin muxing freescale semiconductor 3-42 c[12] pcr[44] siul gpio[44] alt0 gpio[44] ? ? m s 82 n15 etimer_0 etc[5] alt1 etc[5] psmi[8]; padsel=0 dspi_2 cs3 alt2 ? ? c[13] pcr[45] siul gpio[45] alt0 gpio[45] ? ? m s 101 f15 etimer_1 etc[1] alt1 etc[1] psmi[10]; padsel=0 ctu_0 ? ? ext_in psmi[0]; padsel=0 flexpwm_0 ? ? ext_sync psmi[15]; padsel=0 c[14] pcr[46] siul gpio[46] alt0 gpio[46] ? ? m s 103 e15 etimer_1 etc[2] alt1 etc[2] psmi[11]; padsel=1 ctu_0 ext_tgr alt2 ? ? c[15] pcr[47] siul gpio[47] alt0 gpio[47] ? ? sym s 124 a8 flexray ca_tr_en alt1 ? ? etimer_1 etc[0] alt2 etc[0] psmi[9]; padsel=1 flexpwm_0 a[1] alt3 a[1] psmi[21]; padsel=1 ctu_0 ? ? ext_in psmi[0]; padsel=1 flexpwm_0 ? ? ext_sync psmi[15]; padsel=1 table 3-5. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
signal description freescale semiconductor 3-43 pxs20 microcontroller refe rence manual, rev. 1 port d d[0] pcr[48] siul gpio[48] alt0 gpio[48] ? ? sym s 125 b8 flexray ca_tx alt1 ? ? etimer_1 etc[1] alt2 etc[1] psmi[10]; padsel=1 flexpwm_0 b[1] alt3 b[1] psmi[25]; padsel=1 d[1] pcr[49] siul gpio[49] alt0 gpio[49] ? ? m s 3 e3 etimer_1 etc[2] alt2 etc[2] psmi[11]; padsel=2 ctu_0 ext_tgr alt3 ? ? flexray ? ? ca_rx ? d[2] pcr[50] siul gpio[50] alt0 gpio[50] ? ? m s 140 c5 etimer_1 etc[3] alt2 etc[3] psmi[12]; padsel=1 flexpwm_0 x[3] alt3 x[3] psmi[30]; padsel=0 flexray ? ? cb_rx ? d[3] pcr[51] siul gpio[51] alt0 gpio[51] ? ? sym s 128 a7 flexray cb_tx alt1 ? ? etimer_1 etc[4] alt2 etc[4] psmi[13]; padsel=1 flexpwm_0 a[3] alt3 a[3] psmi[23]; padsel=2 table 3-5. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
pxs20 microcontroller refe rence manual, rev. 1 pin muxing freescale semiconductor 3-44 d[4] pcr[52] siul gpio[52] alt0 gpio[52] ? ? sym s 129 b7 flexray cb_tr_en alt1 ? ? etimer_1 etc[5] alt2 etc[5] psmi[14]; padsel=2 flexpwm_0 b[3] alt3 b[3] psmi[27]; padsel=2 d[5] pcr[53] siul gpio[53] alt0 gpio[53] ? ? m s 33 n3 dspi_0 cs3 alt1 ? ? flexpwm_0 ? ? fault[2] psmi[18]; padsel=0 d[6] pcr[54] siul gpio[54] alt0 gpio[54] ? ? m s 34 p3 dspi_0 cs2 alt1 ? ? flexpwm_0 x[3] alt3 x[3] psmi[30]; padsel=1 flexpwm_0 ? ? fault[1] psmi[17]; padsel=1 d[7] pcr[55] siul gpio[55] alt0 gpio[55] ? ? m s 37 r4 dspi_1 cs3 alt1 ? ? dspi_0 cs4 alt3 ? ? swg analog output ? ? ? d[8] pcr[56] siul gpio[56] alt0 gpio[56] ? ? m s 32 m3 dspi_1 cs2 alt1 ? ? etimer_1 etc[4] alt2 etc[4] psmi[13]; padsel=2 dspi_0 cs5 alt3 ? ? flexpwm_0 ? ? fault[3] psmi[19]; padsel=1 table 3-5. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
pin muxing pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor 3-45 d[9] pcr[57] siul gpio[57] alt0 gpio[57] ? ? m s 26 l3 flexpwm_0 x[0] alt1 x[0] ? linflexd_1 txd alt2 ? ? d[10] pcr[58] siul gpio[58] alt0 gpio[58] ? ? m s 76 t15 flexpwm_0 a[0] alt1 a[0] psmi[20]; padsel=1 etimer_0 ? ? etc[0] psmi[35]; padsel=1 d[11] pcr[59] siul gpio[59] alt0 gpio[59] ? ? m s 78 r16 flexpwm_0 b[0] alt1 b[0] psmi[24]; padsel=1 etimer_0 ? ? etc[1] psmi[36]; padsel=1 d[12] pcr[60] siul gpio[60] alt0 gpio[60] ? m s 99 g14 flexpwm_0 x[1] alt1 x[1] psmi[28]; padsel=1 linflexd_1 ? ? rxd psmi[32]; padsel=1 d[14] pcr[62] siul gpio[62] alt0 gpio[62] ? ? m s 105 d16 flexpwm_0 b[1] alt1 b[1] psmi[25]; padsel=2 etimer_0 ? ? etc[3] psmi[38]; padsel=1 port e e[0] pcr[64] siul ? alt0 gpi[64] ? ? ? ? 68 t13 adc_1 ? ? an[5] 3 ? e[2] pcr[66] siul ? alt0 gpi[66] ? ? ? ? 49 u6 adc_0 ? ? an[5] 3 ? table 3-5. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
pxs20 microcontroller refe rence manual, rev. 1 pin muxing freescale semiconductor 3-46 e[4] pcr[68] siul ? alt0 gpi[68] ? ? ? ? 42 u4 adc_0 ? ? an[7] 3 ? e[5] pcr[69] siul ? alt0 gpi[69] ? ? ? ? 44 t5 adc_0 ? ? an[8] 3 ? e[6] pcr[70] siul ? alt0 gpi[70] ? ? ? ? 46 r6 adc_0 ? ? an[4] 3 ? e[7] pcr[71] siul ? alt0 gpi[71] ? ? ? ? 48 t6 adc_0 ? ? an[6] 3 ? e[9] pcr[73] siul ? alt0 gpi[73] ? ? ? ? 61 t10 adc_1 ? ? an[7] 3 ? e[10] pcr[74] siul ? alt0 gpi[74] ? ? ? ? 63 t11 adc_1 ? ? an[8] 3 ? e[11] pcr[75] siul ? alt0 gpi[75] ? ? ? ? 65 u11 adc_1 ? ? an[4] 3 ? e[12] pcr[76] siul ? alt0 gpi[76] ? ? ? ? 67 t12 adc_1 ? ? an[6] 3 ? e[13] pcr[77] siul gpio[77] alt0 gpio[77] ? ? m s 117 d12 etimer_0 etc[5] alt1 etc[5] psmi[8]; padsel=1 dspi_2 cs3 alt2 ? ? siul ? ? eirq[25] ? e[14] pcr[78] siul gpio[78] alt0 gpio[78] ? ? m s 119 b12 etimer_1 etc[5] alt1 etc[5] psmi[14]; padsel=3 siul ? ? eirq[26] ? table 3-5. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
pin muxing pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor 3-47 e[15] pcr[79] siul gpio[79] alt0 gpio[79] ? ? m s 121 b11 dspi_0 cs1 alt1 ? ? siul ? ? eirq[27] ? port f f[0] pcr[80] siul gpio[80] alt0 gpio[80] ? ? m s 133 d7 flexpwm_0 a[1] alt1 a[1] psmi[21]; padsel=2 etimer_0 ? ? etc[2] psmi[37]; padsel=1 siul ? ? eirq[28] ? f[3] pcr[83] siul gpio[83] alt0 gpio[83] ? ? m s 139 b5 dspi_0 cs6 alt1 ? ? f[4] pcr[84] siul gpio[84] alt0 gpio[84] ? ? f s 4 d2 npc mdo[3] alt2 ? ? f[5] pcr[85] siul gpio[85] alt0 gpio[85] ? ? f s 5 d1 npc mdo[2] alt2 ? ? f[6] pcr[86] siul gpio[86] alt0 gpio[86] ? ? f s 8 e2 npc mdo[1] alt2 ? ? f[7] pcr[87] siul gpio[87] alt0 gpio[87] ? ? f s 19 j1 npc mcko alt2 ? ? f[8] pcr[88] siul gpio[88] alt0 gpio[88] ? ? f s 20 k2 npc mseo[1] alt2 ? ? f[9] pcr[89] siul gpio[89] alt0 gpio[89] ? ? f s 23 k1 npc mseo[0] alt2 ? ? f[10] pcr[90] siul gpio[90] alt0 gpio[90] ? ? f s 24 l1 npc evto alt2 ? ? table 3-5. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
pxs20 microcontroller refe rence manual, rev. 1 pin muxing freescale semiconductor 3-48 f[11] pcr[91] siul gpio[91] alt0 gpio[91] ? ? m s 25 l2 npc evti alt2 ? ? f[12] pcr[92] siul gpio[92] alt0 gpio[92] ? ? m s 106 c17 etimer_1 etc[3] alt1 etc[3] psmi[12]; padsel=2 siul ? ? eirq[30] ? f[13] pcr[93] siul gpio[93] alt0 gpio[93] ? ? m s 112 b14 etimer_1 etc[4] alt1 etc[4] psmi[13]; padsel=3 siul ? ? eirq[31] ? f[14] pcr[94] siul gpio[94] alt0 gpio[94] ? ? m s 115 c13 linflexd_1 txd alt1 ? ? f[15] pcr[95] siul gpio[95] alt0 gpio[95] ? ? m s 113 d13 linflexd_1 ? ? rxd psmi[32]; padsel=2 fccu fccu_ f[0] ? fccu f[0] alt0 f[0] ? ? s s 38 r2 fccu_ f[1] ? fccu f[1] alt0 f[1] ? ? s s 141 c4 port g g[2] pcr[98] siul gpio[98] alt0 gpio[98] ? ? m s 102 e16 flexpwm_0 x[2] alt1 x[2] psmi[29]; padsel=1 dspi_1 cs1 alt2 ? ? table 3-5. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
pin muxing pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor 3-49 g[3] pcr[99] siul gpio[99] alt0 gpio[99] ? ? m s 104 d17 flexpwm_0 a[2] alt1 a[2] psmi[22]; padsel=2 etimer_0 ? ? etc[4] psmi[7]; padsel=3 g[4] pcr[100] siul gpio[100] alt0 gpio[100] ? ? m s 100 f17 flexpwm_0 b[2] alt1 b[2] psmi[26]; padsel=2 etimer_0 ? ? etc[5] psmi[8]; padsel=3 g[5] pcr[101] siul gpio[101] alt0 gpio[101] ? ? m s 85 n17 flexpwm_0 x[3] alt1 x[3] psmi[30]; padsel=2 dspi_2 cs3 alt2 ? ? g[6] pcr[102] siul gpio[102] alt0 gpio[102] ? ? m s 98 g17 flexpwm_0 a[3] alt1 a[3] psmi[23]; padsel=3 g[7] pcr[103] siul gpio[103] alt0 gpio[103] ? m s 83 p17 flexpwm_0 b[3] alt1 b[3] psmi[27]; padsel=3 g[8] pcr[104] siul gpio[104] alt0 gpio[104] ? ? m s 81 p16 flexray dbg0 alt1 ? ? dspi_0 cs1 alt2 ? ? flexpwm_0 ? ? fault[0] psmi[16]; padsel=2 siul ? ? eirq[21] ? table 3-5. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
pxs20 microcontroller refe rence manual, rev. 1 pin muxing freescale semiconductor 3-50 g[9] pcr[105] siul gpio[105] alt0 gpio[105] ? ? m s 79 r17 flexray dbg1 alt1 ? ? dspi_1 cs1 alt2 ? ? flexpwm_0 ? ? fault[1] psmi[17]; padsel=2 siul ? ? eirq[29] ? g[10] pcr[106] siul gpio[106] alt0 gpio[106] ? ? m s 77 p15 flexray dbg2 alt1 ? ? dspi_2 cs3 alt2 ? ? flexpwm_0 ? ? fault[2] psmi[18]; padsel=1 g[11] pcr[107] siul gpio[107] alt0 gpio[107] ? ? m s 75 u15 flexray dbg3 alt1 ? ? flexpwm_0 ? ? fault[3] psmi[19]; padsel=2 g[12] pcr[108] siul gpio[108] alt0 gpio[108] ? ? f s ? f2 npc mdo[11] alt2 ? ? g[13] pcr[109] siul gpio[109] alt0 gpio[109] ? ? f s ? h1 npc mdo[10] alt2 ? ? g[14] pcr[110] siul gpio[110] alt0 gpio[110] ? ? f s ? a6 npc mdo[9] alt2 ? ? g[15] pcr[111] siul gpio[111] alt0 gpio[111] ? ? f s ? j2 npc mdo[8] alt2 ? ? port h h[0] pcr[112] siul gpio[112] alt0 gpio[112] ? ? f s ? a5 npc mdo[7] alt2 ? ? table 3-5. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
pin muxing pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor 3-51 h[1] pcr[113] siul gpio[113] alt0 gpio[113] ? ? f s ? f1 npc mdo[6] alt2 ? ? h[2] pcr[114] siul gpio[114] alt0 gpio[114] ? ? f s ? a4 npc mdo[5] alt2 ? ? h[3] pcr[115] siul gpio[115] alt0 gpio[115] ? ? f s ? g1 npc mdo[4] alt2 ? ? h[4] pcr[116] siul gpio[116] alt0 gpio[116] ? ? m s ? l16 flexpwm_1 x[0] alt1 x[0] ? etimer_2 etc[0] alt2 etc[0] psmi[39]; padsel=0 h[5] pcr[117] siul gpio[117] alt0 gpio[117] ? ? m s ? m17 flexpwm_1 a[0] alt1 a[0] ? dspi_0 cs4 alt3 ? ? h[6] pcr[118] siul gpio[118] alt0 gpio[118] ? ? m s ? h17 flexpwm_1 b[0] alt1 b[0] ? dspi_0 cs5 alt3 ? ? h[7] pcr[119] siul gpio[119] alt0 gpio[119] ? ? m s ? k16 flexpwm_1 x[1] alt1 x[1] ? etimer_2 etc[1] alt2 etc[1] psmi[40]; padsel=0 h[8] pcr[120] siul gpio[120] alt0 gpio[120] ? ? m s ? k15 flexpwm_1 a[1] alt1 a[1] ? dspi_0 cs6 alt3 ? ? h[9] pcr[121] siul gpio[121] alt0 gpio[121] ? ? m s ? g16 flexpwm_1 b[1] alt1 b[1] ? dspi_0 cs7 alt3 ? ? table 3-5. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
pxs20 microcontroller refe rence manual, rev. 1 pin muxing freescale semiconductor 3-52 h[10] pcr[122] siul gpio[122] alt0 gpio[122] ? ? m s ? a11 flexpwm_1 x[2] alt1 x[2] ? etimer_2 etc[2] alt2 etc[2] ? h[11] pcr[123] siul gpio[123] alt0 gpio[123] ? ? m s ? c11 flexpwm_1 a[2] alt1 a[2] ? h[12] pcr[124] siul gpio[124] alt0 gpio[124] ? ? m s ? b10 flexpwm_1 b[2] alt1 b[2] ? h[13] pcr[125] siul gpio[125] alt0 gpio[125] ? ? m s ? g15 flexpwm_1 x[3] alt1 x[3] ? etimer_2 etc[3] alt2 etc[3] psmi[42]; padsel=0 h[14] pcr[126] siul gpio[126] alt0 gpio[126] ? ? m s ? a12 flexpwm_1 a[3] alt1 a[3] ? etimer_2 etc[4] alt2 etc[4] ? h[15] pcr[127] siul gpio[127] alt0 gpio[127] ? ? m s ? j17 flexpwm_1 b[3] alt1 b[3] ? etimer_2 etc[5] alt2 etc[5] ? port i i[0] pcr[128] siul gpio[128] alt0 gpio[128] ? ? m s ? c9 etimer_2 etc[0] alt1 etc[0] psmi[39]; padsel=1 dspi_0 cs4 alt2 ? ? flexpwm_1 ? ? fault[0] ? table 3-5. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
pin muxing pxs20 microcontroller refe rence manual, rev. 1 freescale semiconductor 3-53 note open drain can be configured by the pcrn for all pins used as output (except fccu_f[0] and fccu_f[1] ). i[1] pcr[129] siul gpio[129] alt0 gpio[129] ? ? m s ? c12 etimer_2 etc[1] alt1 etc[1] psmi[40]; padsel=1 dspi_0 cs5 alt2 ? ? flexpwm_1 ? ? fault[1] ? i[2] pcr[130] siul gpio[130] alt0 gpio[130] ? ? m s ? f16 etimer_2 etc[2] alt1 etc[2] psmi[41]; padsel=1 dspi_0 cs6 alt2 ? ? flexpwm_1 ? ? fault[2] ? i[3] pcr[131] siul gpio[131] alt0 gpio[131] ? ? m s ? e17 etimer_2 etc[3] alt1 etc[3] psmi[42]; padsel=1 dspi_0 cs7 alt2 ? ? ctu_0 ext_tgr alt3 ? ? flexpwm_1 ? ? fault[3] ? rdy (cut2/3 only) pcr[132] (cut2/3 only) siul gpio[132] alt0 gpio[132] ? ? f s ? k3 (cut2/3 only) npc rdy alt2 ? ? notes: 1 programmable via the src (slew rate control) bit in the respecti ve pad configuration register; s = slow, m = medium, f = fast, sym = symmetric (for flexray) 2 the default function of this pin out of reset is alt1 (tdo). 3 analog table 3-5. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
signal description 3-54 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 3.5 mapping of ports to pgpdo/i registers table 3-6. mapping of ports to pgpdo registers port pgpdo field 1 notes: 1 all fields are 16 bits. absolute address a ppdo[0] 0xc3f9_0c00 b ppdo[1] 0xc3f9_0c02 c ppdo[2] 0xc3f9_0c04 d ppdo[3] 0xc3f9_0c06 e ppdo[4] 0xc3f9_0c08 f ppdo[5] 0xc3f9_0c0a g ppdo[6] 0xc3f9_0c0c h ppdo[7] 0xc3f9_0c0e i? 2 2 port i does not have an associated pgpdo register or field. to write data to port i, execute a 32-bit write access to gpdo128_131 at the absolute address shown. 0xc3f9_0680 2 table 3-7. mapping of ports to pgpdi registers port pgpdi field 1 notes: 1 all fields are 16 bits. absolute address a ppdi[0] 0xc3f9_0c40 b ppdi[1] 0xc3f9_0c42 c ppdi[2] 0xc3f9_0c44 d ppdi[3] 0xc3f9_0c46 e ppdi[4] 0xc3f9_0c48 f ppdi[5] 0xc3f9_0c4a g ppdi[6] 0xc3f9_0c4c h ppdi[7] 0xc3f9_0c4e i? 2 2 port i does not have an associated pgpdi register or field. to read data from port i, execute a 32-bit read access from gpdi128_131 at the absolute address shown. 0xc3f9_0880 2
operating modes freescale semiconductor 4-1 pxs20 microcontroller reference manual, rev. 1 chapter 4 operating modes 4.1 overview pxs20 devices can operate in two modes of operation: ? lock step mode (lsm) ? decoupled parallel mode (dpm) one of these two operating modes is st atically selected at power-up (see section 4.4, selecting lsm or dpm ). the selected operating mode may be change d only when going through a full power-on reset. both operating mode support a numbe r of chip modes which are contro lled by the mode entry module (mc_me). these chip modes differ from one another in: ? which peripherals are enabled ? how the pins are configured ? how the clocks are configured ? their relative safety status ? their relative power consumption see section 32.1, introduction , for a complete description of the chip modes. 4.2 lock step mode (lsm) this operating mode takes its name from the ex ecution of the same commands by both cores in synchronicity (lock step). it has been implemente d to allow reaching sil3 with minimal software overhead and is the only operating mode of pxs20 for which a sil3 capability certificate has been planned. in lsm, the sphere of replication (sor) plays a major role. it contains all hardware elements which have been replicated for safety reasons resulting in the sor being a collection of pairs. each member of such a pair will execute the same operations or transactions as its partner resulting in lock step behavior. the compliance with this behavior expectation is checked only on the boundary of the sor, minimizing checker effort. this boundary check is base d on a modified version of the fault isolation concept. fault isolation requires that a fault must not cause failures outside a marked ar ea, in this case the sor. a failure in the sor, as long as it does not propagate to the outsi de of the sor and potentially cause a fault there, does not influence the effective operability of the periphery (and so the ecu). thus it can not cause a hazard. for example, an error in the alu can cause wrong cal culation results but as l ong as these results only influence core register values, they are not a hazard to the operation of the system. also, propagation inside the sor is of no immediate consequence, e.g. if the wrong register value is written to the intc, this ? in itself ? will not change the overall behavior of the system. but once the registers are written somewhere external or used as addr esses, or once the badly changed in terrupt triggers, this 'safeness' changes because the failure now propa gates to the outside of the sor.
operating modes 4-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 the redundancy control checker units (rccu) at the outputs of the sor to the periphery bus, to the flash subsystem and to the sram subsystem detect su ch propagating fa ilures due to data on the external busses being inconsistent between both processing uni ts. thus the rccus implement the modified fault isolation in that they detect but not prevent the propagation of a non-common cau se failure at the point where the two redundant channels are merged into a si ngle actuator or recipient. isolation of the overall system is then achieved by the fault collection a nd control unit (fccu) signaling an error, thereby allowing the device or applic ation to react appropriately. 4.3 decoupled parallel mode (dpm) in this operating mode, each cpu core and connected channel runs independently from the other core, and the redundancy checkers (rccu) are disabled. at a given frequency, ope rating the chip in dpm offers a perfo rmance increase of approximately 1.6 ? over operating the chip in lsm. in this operating mode, the chip boots with core_0 enabled and core_1 disabl ed directly after most resets. after a short external or s hort 'functional' reset, core1 is immediatel y enabled if it was enabled prior to the reset. software running on core_0 can enable core_1 at any time, and once core1 has been enabled, it cannot be disabled by softwa re. while core_1 is disabled, it is not clocked, thus minimizing the chip's overall current consumption during this time. see the tables in chapter 2, memory map , for information on how memory is configured and accessed in dpm. 4.4 selecting lsm or dpm the operating mode (lsm or dpm) on pxs20 is de termined by the lsm_dpm user option bit in the shadow block of the flash memory. th is user option bit is described in section 23.1.7, user option bits, and is physically accesse d using the uops[uopt] fi eld in the sscm (see section 48.3.1.8, user option status register (uops) ). 4.4.1 entering lsm by default, pxs20 is configured to start in lsm (lsm_dpm = 1). 4.4.2 entering dpm 4.4.2.1 dual-core boot concepts entering dpm implies a dual-core boot. the key concept to a du al-core boot is that it is nothing more than a typical single-core boot, except that it starts another single-core boot . the initializati on of interrupts, stack, and other parameters needs to be performed on each core. in othe r words, it is a single-core boot performed twice. figure 4-1 shows a simplification of this boot process.
operating modes freescale semiconductor 4-3 pxs20 microcontroller reference manual, rev. 1 figure 4-1. simplified boot process in dpm at power-on reset (por), core_0 begins operation wh ile core_1 remains held in reset. at this time, core_0 must initialize its set of peripherals, set up its environment (including the nmi routine), then branch to main. at this point, core_0 is essentially fully operational. now core_0 provides the reset vector and writes the dpmkey, thus releasing core_1 from reset. core_1 begins its execution. the first th ing that it must do is initialize it s set of peripherals and set up its environment, including its nmi routine. core_0 then moves the chip from drun mode to run0 mode. each core must service its own nmi routines. it is recommended to alwa ys use core_0 to control the chip modes in order to avoid conflicting or inconsistent chip mode conf iguruations and change requests. 4.4.2.2 software setup during the boot sequence, core_0 runs from reset and executes code that sets up and enables core_1. at that time, the system then begins operating in dpm. no yes core_1 core_0 main() runs on core_0, setting up the start address for core_1 place reset vector for core_1 in register p2boot. core_0 mmu setup, other initialization including nmi vector, then branch to main(). release reset for core_1 by writing dpmkey. core_0 is now operational. lsm_dpm=0 ? boot in lock step mode. core_1 runs mmu setup, other initialization including nmi vector. core_1 changes the device mode from drun to run0. power-on reset both cores manage their own nmi. branch to main() core_1 is now operational.
operating modes 4-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 to make the second core operational, you must conf igure the following two registers in the sscm: ? dpmboot (see section 48.3.1.6, dpm boot register (dpmboot) ) ? dpmkey (see section 48.3.1.7, boot key register (dpmkey) ) follow this sequence to enable dpm: ? write the reset vector into dpmboot[p2boot]. ? set dpmboot[dvle] to indicate that the se cond core will be executing in vle mode. (otherwise, the core will opera te in power architecture mode.) ? write 0x5af0 to dpmkey[key]. ? write 0xa50f to dpmkey[key]. after the second write to dpmkey[key], core_1 star ts execution from its rese t vector. repeating this sequence after core_1 is running will have no effect on core_1 until the ne xt reset, and only then if the reset is a short external or short ?functional? reset.
device boot modes freescale semiconductor 5-1 pxs20 microcontroller reference manual, rev. 1 chapter 5 device boot modes 5.1 boot mode functionality the device supports the following boot modes: ? single chip (sc) ? the device will boot from the first bootable section of the flash memory main array ? serial boot (sbl) ? the device will download boot code from eith er sci or can interface and then execute it if booting is not possible with the se lected configuration (e.g. if no boot id is f ound in the selected boot location) then the device will enter static mode (see section 5.4.6, static mode ). 5.2 hardware configuration the device will detect the boot m ode based on external pins and de vice status. the following sequence applies: ? if the fab (force alternate boot mode) pin is set to boot in serial mode, the device can be forced into an alternate boot loader m ode. the type of alternate boot m ode is selected according to the abs (alternate boot selector) pins (see table 5-1 ). for details of the seri al boot modes please see chapter 8, boot assist module (bam) . ? if the device identifies a flash memory sector wi th a valid boot signature, it will boot from the lowest sector. (see figure 5-1 .) ? if none of the flash memory sectors contains a vali d boot signature, the device will go into static mode. 5.2.1 single chip boot mode the sscm performs a sequent ial search of each bootable sector (starting at sector 0) for a valid boot_id within the rchw. if a valid boot _id is found in the rchw of such a sector , the sscm reads the vle bit and the boot vector addr ess. if a valid boot_id is not found, th e microcontroller is put into static mode. in order for the e200z4d core to be able to access its program space memory , a valid mmu tlb entry has to be created. the sscm does this automatically by r eading the reset vector (t he word after the rchw) and modifying tlb entry 0 to create a 4 kb page containing the rese t vector address. the corresponding table 5-1. hardware configuration fab abs 2,0 standby-ramb oot flag boot id boot mode 1000 ? serial boot sci 1 01 0 ? serial boot can 0 ? 0 valid sc (single chip) 0 ? 0 not found static mode
device boot modes 5-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 mmu page must be properly aligned , which is achieved by setting the 12 lsb's of the reset vector address stored into this entry to 0. the mmu vle bit of this tlb entry is set depending on the status of the vle bi t within the rchw. this means that the most efficient place to put the application code is immediately after the boot sector. the 4 kb block provides sufficient space to ? add mmu entries for the remaining program space, sram and peripherals ? perform standard system initial ization tasks (initialize the sram , setup stack, copy constant data) ? transfer execution to ram, re-define the flash memory mmu entry and transfer execution back to flash memory. 5.2.1.1 boot and alternate boot some applications require an altern ate boot sector so that the main boot can be erased and reprogrammed in the field. when an alternate boot is needed, user can create two bootable sectors; the lowest sector shall be the main boot sector and the highest shall be the alternate boot sector. the alternat e boot sector does not need to be consecutive to the main boot sector. this scheme ensures that there is always one active boot sector by erasing one of the boot sectors only: ? sector is activated (that is, program a valid bo ot_id instead of 0xff as initially programmed). ? sector is deactivated writing to 0 some of the bits boot-id bit field (bit 1 and/or bit 3, and/or bit 4, and/or bit 6). 5.3 boot-sector search 5.3.1 potential boot sectors as shown in figure 5-1 in single chip mode the device will sear ch several locations for a valid boot id. the lowest sector which starts with a vali d boot id will be used to boot the device. the flash locations 0x 0000_0000, 0x0000_4000, 0x0001_0000, 0x0001_c000, 0x0002_0000 and 0x0003_0000 will be searched.
device boot modes freescale semiconductor 5-3 pxs20 microcontroller reference manual, rev. 1 figure 5-1. flash partitioning and rchw search 5.3.2 reset configuration half-word each boot sector in the flash memo ry contains at offset 0x00 the reset configurat ion half-word (rchw). if the rchw field boot_id holds the value 0x5a then the sector is considered bootable. in addition there is a flag which indicates that the code is book e or vle code. this flag should be set to match the executable image. all other bits are reserved. (no bam code execution in this case , and bam code will not be visi ble unless the device is in sbl mode.) apps space boot information apps space apps space apps space $0000 0000 2 nd loc 3 rd loc 4 th loc .... rchw $0000 0000 $0000 0004 $0000 0008 $0000 000c apps space 5 th loc boot information boot information boot information boot information application start address application application (1 st location)
device boot modes 5-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 5-2. reset configuration half word (rchw) once the device detects that it need s to boot from flash, and finds a vali d boot_id, it will boot from the application start addre ss at offset 0x04 with in the boot sector. 5.3.3 boot and alternate boot some applications require an altern ate boot sector so that the main boot can be erased and reprogrammed in the field. when an alternate boot is needed, th e user can create two bootable sector s; the lowest sector shall be the main boot sector and the highest sha ll be the alternate boot sector. the alternate boot sector does not need to be consecutive to the main boot sector. this scheme ensures that there is always one active boot sector by erasing one of the boot sectors only: ? sector is activated (that is, program a valid bo ot_id instead of 0xff as initially programmed). ? sector is deactivated writing to 0 some of the bits boot-id bit field (bit 1 and/or bit 3, and/or bit 4, and/or bit 6). 5.4 device behavior by boot mode the following describes which security related device features are available in the device boot modes. 5.4.1 single chip mode ? unsecured in normal single chip mode, the sy stem boots from the flash memory ma in array. the device will boot from the first sector which is marked bootable. the sy stem may be configured to enable the external bus. ? nexus/jtag available ? boot from flash memory main array ? shadow block available 5.4.2 single chip mode ? secured in secured single chip mode, the system boots from th e flash memory main arra y. the device will boot from the first sector which is marked bootable. 0123456789101112131415 r 0 0 0 0 0 0 0 vle boot_id w res et: 0000000000000000 = reserved
device boot modes freescale semiconductor 5-5 pxs20 microcontroller reference manual, rev. 1 ? no nexus/jtag apart from jtag info for device and mask id (major and minor) and commands to temporarily unlock the device with a valid flash password. ? boot from flash main array ? shadow block accessible 5.4.3 serial boot loader mode ? public password enabled ? in serial boot loader mode, if public serial access is allowed, the mcu executes bam code which will check for a valid public password on the chos en interface. the interface will be selected via fab and abs pins. ? nexus/jtag available if device is not sensored. ? boot from bam ? flash main array and shadow block access is disabled if device is censored. 5.4.4 serial boot loader mode ? flash memory password enabled it is possible to boot in serial b oot loader mode when serial access with password is selected. the mcu executes bam code which will check for a valid flash memory password on the chosen interface. if the password is known, full access to the device is enabled. ? nexus/jtag available once the correct password has been received. ? boot from bam ? flash main array and shadow block access possi ble once the correct password has been received. 5.4.5 standby boot mode in standby-boot mode, the mcu can be configured to boot from internal flash memory (single chip mode) or from standby ram. if the mcu boots from standby ram th e reset sequence can be abridged - in this case the flash memory will not be av ailable. (see rgm block guide for mode selection). the device security status will be stored in the ss cm standby area, so debuggi ng will be possible if the device is unsecured. 5.4.6 static mode static mode means the device enters the safe mode and the processor executes a wait instruction. it is needed if the device can not boot in the mode which was selected. access to nexus and flash memory is as defined by the boot mode and the se curity status. eventually the swt will cause a reset and restart the boot search.
device boot modes 5-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1
device security freescale semiconductor 6-1 pxs20 microcontroller reference manual, rev. 1 chapter 6 device security 6.1 security the censorship mechanism implemented on the device is intended to increase the protection against unauthorized access to the de vice. the mechanisms employed does not provide a guarantee of a secure device. it can only be deemed effect ive if used in conjunction with an appropriately robust software and documentation infrastructure to assist in guardi ng against unauthorized access to device resources. when the flash memory is censored, the mcu is in the secured state. this feature intends to prevent the unauthorized read and writ e of memory contents. which device fe atures are enabled or disabled is determined by the chip mode and securi ty state in effect. please refer to section 5.4, device behavior by boot mode, for details. the user needs to keep in mind that part of the secur ity must lie with the appli cation code. as an extreme example: it would be possibl e to generate application c ode that dumps the contents of the internal program - obviously this code would defeat the purpose of security. however th ere may be good reasons to provide a back door in the application code. care must be taken when implementing these backdoors, since they allow paths of attack to break security on the device. 6.1.1 securing the microcontroller the device can be secured by programmi ng the flash memory nvsci register ( figure 6-1 ; also see section 23.1.6.15, nonvolatile system censor ing information register (nvsci) ). this non-volatile register will keep the device secured even when it is reset or powered down. 0123456789101112131415 r censorship control w 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r serial boot control w figure 6-1. nonvolatile system censorship information register (nvsci) for cut1
device security 6-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 a value of 0x55aa in the censhorship control word of the nvsci register determines that the device is unsecured, any other value determines that the device is secured. the f actory default of the nvsci holds the value 0x55aa55aa. (for the function of the serial boot control word see section 6.2, serial access .) the device supports a backdoor to unsecure the device via the 64 bit password re gister (nvpwd) in the flash memory block. the flash memory password can be progr ammed or modified as long as the device is unsecured. in order to modify an already pr ogrammed password the shadow block n eeds to be erased first, and all other configuration bits re-programmed as well. to protect against voltage manipula tions, each 16-bit halfword needs to contain both 1?s and 0?s. below are examples for legal and illegal passwords: to deactivate the flash memory passw ord (?swallowing the key?) the regi ster can be programmed with the value 0x0000_0000_0000_0000. however once this is done neit her the manufacturer nor the user can unlock device security again. of c ourse, application code can still im plement a differen t backdoor scheme if there are special requirements which ar e not covered by the available mechanism. 6.1.2 unsecuring the microcontroller to unsecure a secured device, the flash memory password needs to be provided. this can be done by booting in sbl mode and providing the flash memory pa ssword via the serial boot loader protocol (see refer to the bam chapter) or via jtag command. if sbl mode was used in conjunction with the fl ash memory password, the password comparison result will only be known after a delay - this is in order to avoid brute-force attacks. the data can be downloaded into sram during this delay. 0123456789101112131415 r serial boot control w 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r censorship control w figure 6-2. nonvolatile system censorship information register (nvsci) for cut2/3 illegal passwords 0x0000_0000_0000_0000 0xffff_ffff_ffff_ffff 0xffff_0000_ffff_ffff 0x0000_0000_0000_ffff 0xaaaa_aaaa_aaaa_0000 legal passwords 0x0001_0010_0100_1000 0xfffe_fffe_fffe_fffe 0xfff0_000f_0fff_0fff 0x1000_1000_1000_fffe 0xaaaa_aaaa_aaaa_0001
device security freescale semiconductor 6-3 pxs20 microcontroller reference manual, rev. 1 note the scheme used here does not prohibi t a malicious listene r from capturing the password of a valid serial downloa d, since the key is not in encrypted form. the user must take appropriate measures to protect against access by third parties during a valid download. if the password is correct, the de vice is temporarily unsecured. in this state the a new flash memory password can be programmed into the nvpwd registers or new application data can be programmed into the main flash memory array. (i n order to modify an already pr ogrammed password the shadow block needs to be erased first, and all other configuration bits re-programmed as well.) it is also possible to unlock the devi ce via jtag. for this the device n eeds to be held in reset by pulling the external reset input, once the flash memory has co mpleted its internal sequence, the jtag register censor_ctrl can be written with the password in bi ts 63:0 and with bit 64 set to 1. the password comparator will compare the password and unsecure the devi ce if it is correct, if serial access with the flash memory password is allowed, and if the device hasn ?t swallowed the key. (only one transition on bit 64 from 0 to 1 is allowed.) the debugger needs to wait until the device is unlocke d, after that a breakpoint can be set if desired, a nd the debugger can release th e reset. the device will remain unsecured until the next reset event occurs. 6.1.2.1 software unsecure since the security state of the device is determined solely by a user programmabl e location in the shadow block, any application may choose to implement a software unsecure method, through any interface. 6.2 serial access the device can be accessed via a serial interface, if it is booted in sbl mode (see section 5.2, hardware configuration ). it is possible to either use the public pass word or the flash memory password ? this is decided by programming the serial boot cont rol word in the nvsci register (see figure 6-1 ). if it contains the value 0x55aa, the flash memory password mu st be used, if it contains any other value the public password must be used. access to the flash memory depends both on the serial boot control fiel d and the censorship control field in the nvsci. an unsecured device al ways allows access to the flash memo ry regardless of the serial boot control field. for a secured device if the public passw ord access is used, the flash memory will not be visible, if flash memory pa ssword access is used then device security is disabled and the flash memory is visible. the application may wish to prohibit access via seri al line - this can be accomplished by programming nvsci to 0x55aa which mandates the use of the fl ash memory password, a nd programming nvpwd to 0x0000_0000_0000_0000 which makes the flash memory password invalid. however it should be carefully evalua ted whether this scenario is desira ble. if programmed like this there is no longer the possibility to allow the manufacturer to run diagnostic on a returned device. similarly it won?t be possible anymore to update the application. this does not apply if the us er decides to implement an alternative backdoor sc heme in software (see section 6.1.2.1, software unsecure ).
device security 6-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1
functional safety freescale semiconductor 7-1 pxs20 microcontroller reference manual, rev. 1 chapter 7 functional safety 7.1 overview this device offers a set of features to support using it for appl ications which need to fulfill functional safety requirements as defined by safety integrity le vels sil3 of iec61508 and other corresponding certifications.. also, the development processes and documentation of this device target these safety standards. this device is considered a type b subsystem (?complex?, see iec 61508-2, section 7.4.3.1. architectural constraints on hardware safety integrity) and is assumed to be used in a ?high-demand / continuous mode of operation? safety mode (see iec 61508-1, section 7.6.2, ?requirements?). 7.2 redundancy the main approach used to achieve functional safe ty requirements is redunda ncy. redundancy is applied in different ways for different modules of this device: ? processing cores: when used for a safety critical application, the two redundant cores must be used in lock-step mode. any difference between the out puts of the cores indicates a fault and triggers the according reaction to prevent pr opagation of the fault and to put the device into a fail-safe mode. ? replicated peripherals, if safety critical for the applicat ion, have to be used in a redundant way by the application software. de tails are specified in the safety application guide. ? non-replicated input periphe rals, if safety critical for the applic ation and not self-t ested, have to be read twice by the application so ftware. details are specified in the safety application guide. ? non-replicated output peripherals, if safety critical for the appli cation and not read-back, have to be written twice by the applicati on software. details are specified in the safety application guide. 7.3 built-in self-test (bist) 7.3.1 bist during boot a device bist is performed every time a destructive or external reset occurs . the device provides full reset conditions to the outside worl d while bist is executed. the bist is performed transparently for the application while the device is still under reset. in case the bist fails, the device is kept under reset. application software can only start to run when bist finished successfully without detecting a fault. the boot time bist comprises: ? memory bist for all rams and rom ? scan-based logic bist for three partitions of di gital logic (for the contents of the individual partitions see hierarchy definition).
functional safety 7-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 7.3.2 software-triggered bist during operation for some modules of this device it is required to run bist during operation, because testing every 10 hours (trip time) is not sufficient for the targeted safety in tegrity level. these bist runs need to be triggered by application software once within each process safety time (10 ms). details are specified in the safety application guide. modules which require bist runs during application are: ? adc: software triggers several se lf-tests implemented in hardware ? flash memory ecc logic test 7.3.3 software-triggered self-tests after boot in order to ensure integrity of fl ash memory for a safety application, hardware base d flash self-test needs to be triggered by software every tim e the device is booted. details are sp ecified in the safety application guide. 7.4 memory error detection and correction rams are protected against soft erro rs by a 7-bit/32 sec/ded ecc code computed over address and data at each memory access. detected faults are reported to the fccu. nvm flash is protected by 8-bit/64 parity sec/ded. 7.5 monitoring all monitoring features react within the so-cal led process safety time of 10 ms or faster. core voltage is equipped with a low voltage detector a nd a high voltage detector to indicate if voltage is out of the specified range. io voltage is monitore d by a low voltage detector. the voltage detectors themselves have a hardware based self-checking feature. this device is equipped with two temperature sensors. four clocks are monitored: ? internal oscillator clock ? fmpll-generated system clock ? flexray clock ? smc clock a memory protection unit prevents incorrect memo ry accesses based on 16 pos sibly overlapping physical memory regions.
functional safety freescale semiconductor 7-3 pxs20 microcontroller reference manual, rev. 1 7.6 software measures the safety application guid e specifies several software measures required to achieve safety integrity for this device. software has to trigger these test featur es at least every 10 ms (p rocess safety time). these are simple checks. no software based self-test routine library is necessary for this device. the following shows some examples for software ch ecks. the complete list of software measures is defined in the safety application guide. example 1: modules which require crc checks during operation are: ? siul: system configuration registers checked ? adc: configuration registers checked ? etimer: configuration registers checked example 2: the ctu unit requires the following checks: ? have all triggers been generated and served (sup ported by hardware, faults to be handled in sw)? ? do trigger times matc h expected behavior? ? is there a trigger buffer overrun (supported by hardware, faults to be handled in sw)? ? does the channel number sequen ce match expected behavior? ? are the issued commands va lid (supported by hardware, faul ts to be handled in sw)? 7.7 fault reaction all faults detected by hardware measures like the redundancy checkers, self-tes t features, ecc, voltage and clock monitors are reported to the central fault collection an d control unit (fccu). depending on the particular fault, the fccu puts the device into th e according configured fail-s afe state. this prevents fault propagation to system level. by definition, the sa fe state of this chip is either of the following: ? i/os in tristate when the device is in shutdown or reset ? device flagging an error out for critical errors the continuous switch betwee n a standard operation state and the rese t state without any shut down is not considered a safe state. safety critical ios are kept in tri-stat e when the device is in a fail-safe state. 7.8 external measures this chip requires several external measures to al low safe operation: ? external power supply and monitor ? external watchdog timer ? error out monitor to handle situations wher e this device indicates an internal fault ? pwm output monitor that monito rs and corrects the pwm outputs
functional safety 7-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1
boot assist module (bam) freescale semiconductor 8-1 pxs20 microcontroller reference manual, rev. 1 chapter 8 boot assist module (bam) 8.1 overview the boot assist module (bam ) is a block of read-only memory cont aining vle code which is executed according to the boot mode of the device. the code stored in the ba m is not executed when booting in single chip mode (see chapter 5, device boot modes ), except when entering the "static mode" in case no valid bootable sect or has been found. the bam downloads code into inte rnal sram through the following se rial protocols and executes it afterwards: ?flexcan ? linflex-uart for cut2/3, dependent on th e selected boot mode (see section 8.4.1, ente ring boot modes ), any download is performed either with a fixed baud rate or after running a short sequence to measure the selected baud rate (with ?autobaud?). see section 8.4.5, boot with aut obaud feature [cut2/3 only] , for further information about the autobaud feature. additionally, for cut2/3, the bam provides a short code sequence to retrieve factor y settings from the test flash as convenience soft ware. please refer to section 8.4.6, reading from test flash [cut2/3only] , for further information. 8.2 features the bam provides the following features: ? programmable 64-bit password pr otection for serial boot mode ? serial boot loads the application boot code from a flexcan or linflex bus into internal sram ? censorship protection for internal flash module ? detection of the selected baud rate in autobaud mode
boot assist module (bam) 8-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 8.3 memory map the bam code resides in 8 kb of rom mapped from address 0xffff_c000. the address space and memory used by the bam is shown in table 8-1 . the ram location where to download the code can be any 4 byte-aligned location in the sram starting from the address 0x4000_0100. caution do not use the ram area used by the bam code as indicated in table 8-1 . 8.4 functional description 8.4.1 entering boot modes the pxs20 detects the boot mode based on external pins and device status. the following sequence applies (see figure 8-1 ): 1. to boot either from flexcan or linflex, the device must be forced into an altern ate boot loader mode via the fab (force alternat e boot mode) pin which must be asserted before initiating the reset sequence. the type of alternate boot mode is selected according to th e abs (alternate boot selector) pins (see table 8-2 ). 2. if fab is not asserted, the devi ce boots from the first flash memory sector which contains a valid boot signature. 3. if no flash memory sector contains a valid boot signature, the device will go into static mode. table 8-1. bam memory organization entity address bam entry point 0xffff_c000 ram area used by the bam code (do not use) 0x4000_0000?0x4000_00ff downloaded code base address 0x4000_0100
boot assist module (bam) freescale semiconductor 8-3 pxs20 microcontroller reference manual, rev. 1 figure 8-1. boot mode selection 8.4.2 boot through bam 8.4.2.1 executing bam single chip boot mode (see section 5.2.1, single chip boot mode ) is managed by hardware and bam doesn?t participate in it. bam is executed only on one or both of the following cases: ? serial boot mode has been selected by fabm pin; ? hardware hasn?t found a valid boot id in any flash memory boot locations. if one of these conditions is true, the device fetches code at location 0xffff_c000 and the bam application starts. table 8-2. hardware configuration to select boot mode fab abs[2,0] standby-ram boot flag boot id boot mode 1 00 0 ? linflex without autobaud 1 01 0 ? flexcan without autobaud 1 10 0 ? scan of both serial interfaces (flexcan and linflex) with autobaud yes fabm = 1 ? por flash memory boot id in any boot sector? no static mode no value of abs ? serial boot (sbl) linflex without 00 serial boot (sbl) flexcanwithout 01 serial boot (sbl) 10 flash memory boot yes from first sector having a valid boot id the grey blocks represent action done by hardware. the white blocks represent action done by software (bam). autobaud autobaud linflex and flexcan with autobaud
boot assist module (bam) 8-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 8.4.2.2 bam software flow figure 8-2 describes the bam logic flow. figure 8-2. bam logic flow the first action is to save the initia l device configuration. in this way it is possible to restore the initial configuration after downloading the ne w code but before executing it. th is allows the new code to be executed as the device was just coming out of reset. the sscm_status[bmode] field (see section 48.3.1.1, system status register (status) ) indicates which boot has to be executed (see table 8-3 ). if bmode field shows either a single chip value (0 11) or the reserved valu es, the boot mode is not considered valid and the bam pushe s the device into static mode. in all other cases data is downloaded in serial b oot mode and saved into the correct sram location. then, the initial device configurat ion is restored and the code jumps to the address provided for the downloaded code. at this point ba m has just finished its task. table 8-3. fields of sscm status register read by bam to detect the chosen boot mode field description bmode bmode device boot mode. 000 serial boot loader (flexcan or linflex) with autobaud 001 flexcan serial boot loader (without autobaud) 010 linflex serial boot loader (without autobaud) 011 single chip other values are reserved yes no which boot mode is selected is verified by reading the sscm_status register (bmode). execute new code. static mode. restore default configuration. restore default configuration. download new code and save it into sram. boot mode valid ? check boot mode. save default configuration. bam entry 0xffff_c000
boot assist module (bam) freescale semiconductor 8-5 pxs20 microcontroller reference manual, rev. 1 if there is any error (that is, communication error, wrong boot selected, etc.), bam restores the default configuration and puts the device into static mode. st atic mode means the devi ce enters the low power mode safe and the processor executes a wait instruction. it is needed if the device can not boot in the mode which was selected. during bam executi on and after, the mode reported by the field s_current_mode of the register me_gs in the module mc_me module is ?drun?. 8.4.2.3 bam resources bam uses/initializes the following mcu resources: ? mmu is programmed to support either vle or power architecture technology (dependent on downloaded code) ? cache is disabled ? mc_me and mc_cgm modules to in itialize mode and clock sources ? can_0, linflex_0 and their pins wh en performing serial boot mode ? swt is disabled in case of a serial boot mode or when entering static mode ? pit for time measurement when performing serial boot mode ? sscm to check the boot mode and during password check (see table 8-3 and figure 8-3 ) ? external oscillator (xosc) ? siul to perform programming of the required gpio pins on cut2/3, the following hardware resources are used only when autobaud feature is selected: ? stm to measure the baud rate ? cmu to measure the external clock frequency related to the internal ircosc clock source ? fmpll to work with the system clock near the maximum allowed frequency (for higher resolution during baud rate measurement). the initial configuration is restored before executing the downloaded code. for cut2/3, when the autobaud feature is disabled, the sy stem clock is selected directly from the external oscillator. thus the frequency of the external oscillat or defines the baud rate for serial interfaces used to download the user application. for a linfle x transmission, the selected baud rate is f xosc / 833. for a flexcan transmission, the selected baud rate is f xosc / 40. 8.4.2.4 download and execute the new code from high level perspective, the download protocol follows steps: 0. (only in autobaud mode) transmit message for aut obaud measurement and subse quent baud rate selection 1. transmit 64 bits password 2. transmit start address, size of downloded code in bytes and vle bit 3. transmit download data 4. execute code from start address. each step must be completed before the next step starts.
boot assist module (bam) 8-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 the communication is done in half duplex manner, any transmission from host is foll owed by the mcu transmission: ? host sends data to mcu and starts waiting ? mcu echoes to host the data received ? host verifies if echoes are correct ? if data is correct, the hos t can continue to send data ? if data is not correct, the host stops to transmit and mcu need to be reset. all multi-byte data structures are sent with msb first. a more detailed descripti on of these steps follows. 8.4.2.5 download 64-bit password and password check the first 64 bits received represen t the password. this password is sent to the password check procedure which verifies if it is correct. password check data flow is shown in figure 8-3 where: ? sscm_status.pub = 1 specifies seri al boot mode with public password ? sscm_status.sec = 1 specifies that the flash memory is secured in case of serial boot mode with public password, the rece ived password is comp ared with the public password 0xfeed_face_cafe_beef. if public access is not allowed but th e flash is not secured, the received password is compared with the 64 bit value saved in the nvpwd0 and nvpwd1 locations in the shadow flash. in both cases, comparison is done by the bam code. if it fails, bam pushes the de vice into static mode. if the public password is not allowe d and the flash memory is secured, the received passwor d is compared by hardware against the password stored in nvpwd 0 and nvpwd1. only in this case (no public password and secured flash), the words of the provided password must be swapped (nvpwd1|nvpwd0). after a fixed time waiting: ? if the correct password was supplied, flash is now unsecured and bam continues its task ? if an incorrect password was supp lied, flash is still secured; bam puts the device in to static mode
boot assist module (bam) freescale semiconductor 8-7 pxs20 microcontroller reference manual, rev. 1 figure 8-3. password check flow 8.4.2.6 download start addre ss, vle bit and code size the next 8 bytes received by the mcu contain a 32-bit start address, th e vle mode bit and a 31-bit code length as shown in figure 8-4 . the vle bit (variable length instruction) is used to indicate for which instruction set the code has been compiled. the bam supports the do wnload of vle code (vle bit = 1) and power architecture technology (vle bit = 0). in case of power architecture technology, the mmu page for the ram space (0x4000_0000 - 0x7fff_ffff) will be modified to select power architecture. otherwise the mmu page for this page will conti nue to select vle code. note power architecture technology is su pported in cut2 and beyond only the start address defines wh ere the received data will be stored and where the mcu will branch after the download is finished. the two lsb bits of the star t address are ignored by th e bam program, such that the loaded code should be 32-bit word aligned. the length defines how many data bytes have to be loaded. sscm. status. pub = 0 = 1 = 0 sscm. status. sec = 1 compare password by hardware wait verify if flash is unsecured comparison with 0xfeedface cafebeef comparison with password saved in nvpwd
boot assist module (bam) 8-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 8-4. start address, vle bit and download size in bytes 8.4.2.7 download data each byte of data received is stored into device? s sram, starting from the address specified in the previous protocol step. it is not ve rified whether the provid ed address is a valid address in sram or is writable. the address increments until the num ber of bytes of data received matches the numbe r of bytes specified in the previous protocol step. since the sram is protected by 32-bi t wide error correction code (ecc), bam always writes bytes into sram grouped into 32-bit words. if the last byte received does not fa ll onto a 32-bit boundary, the bam fills it with 0 bytes. then a ?dummy? word (0x0000_0000) is written to a void a possible ecc error during core prefetch. 8.4.2.8 execute code the bam program waits for the last ech o message transmission being completed. then it restores the initial mcu c onfiguration and jumps to the code loaded at start address which was received in step 2 of the protocol. at this point bam has finished its tasks and mcu is controlled by new code executing from sram. 8.4.3 uart boot ? autobaud disabled 8.4.3.1 configuration boot using the uart protocol is implem ented by linflex_0 module. pins used are: ? linflex_tx corresponds to pin b[2] ? linflex_rx corresponds to pin b[3]. start_address[31:16] start_address[15:0] vle code_length[30:16] code_length[15:0]
boot assist module (bam) freescale semiconductor 8-9 pxs20 microcontroller reference manual, rev. 1 the linflex controller is configured to operate at a baud rate of f xosc / 833 , using 8 bit data frame without parity bit and 1 stop bit. for cut2/3, when autobaud fe ature is disabled, the syst em clock is driven by the external oscillator. for cut1, the system clock is dr iven by the internal rc oscillator (16 mhz), resulting in a baud rate of f xosc / 833 = 19200. 8.4.3.2 protocol table 8-5 summarizes the protocol and bam action during this boot mode. 8.4.4 can boot ? autobaud disabled 8.4.4.1 configuration boot using the can protocol is implement ed by flexcan_0 module. pins used are: ? can_tx corresponds to pin b[0] ? can_rx corresponds to pin b[1]. boot from flexcan with autobaud disabled uses th e system clock driven by the external oscillator. the flexcan controller is configured to opera te at a baud rate = sy stem clock frequency/40. table 8-4. linflex bit timing in uart mode table 8-5. uart boot mode download protocol (autobaud disabled) protocol step host sent message bam response message action 1 64-bit password (msb first) 64-bit password password checked for validity and compared against stored password. 2 32-bit store address 32-bit store address l oad address is stored for future use. 3 vle bit + 31-bit number of bytes (msb first) vle bit + 31-bit number of bytes (msb first) size of download is stored for future use. verify vle bit. 4 8 bits of raw binarydata 8 bits of raw binarydata 4 x 8 bits of data are packed into 32-bit words. these words are saved into sram starting from the ?load address?. ?load address? increments until the number of data received and stored matches the size as specified in the previous step. 5 none none branch to downloaded code
boot assist module (bam) 8-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 it uses the standard 11 bit identifier fo rmat detailed in flexcan 2.0a specification. flexcan controller bit timing is pr ogrammed with 10 time quanta, and th e sample point is 2 time quanta before the end, as shown in figure 8-5 . figure 8-5. flexcan bit timing 8.4.4.2 protocol table 8-6 summarizes the protocol and bam action during this boot mode. all data is transmitted byte wise. table 8-6. flexcan boot mode download protocol (autobaud disabled). protoco l step host sent message bam response message action 1 flexcan id 0x011+ 64-bit password flexcan id 0x001+ 64-bit password password checked for validity and compared against stored password. 2 flexcan id 0x012+ 32-bit store address+ vle bit+ 31-bit number of bytes flexcan id 0x002+ 32-bit store address+ vle bit+ 31-bit number of bytes load address is stored for future use. size of download are stored for future use. verify vle bit. 3 flexcan id 0x013+ 8 to 64 bits of raw binary data flexcan id 0x003+ 8 to 64 bits of raw binary data 4 x 8 bits of data are packed into 32-bit words. these words are saved into sram starting from the ?load address?. ?load address? increments until the number of data received and stored matches the size as specified in the previous step. 4 none none branch to downloaded code sync_seg time segment 1 time segment 2 sample point nrz signal transmit point 1 time quantum time quanta time quanta 7 2 1 bit time 1 time quantum = 4 sy stem clock periods
boot assist module (bam) freescale semiconductor 8-11 pxs20 microcontroller reference manual, rev. 1 8.4.5 boot with autobaud feature [cut2/3 only] the purpose of autobaud is to allow boot operation with a wide range of baud ra tes independent of the external oscillator frequency. note the baud rates achievable by the au tobaud feature are limited by the software based measurement method and the effects resulting from different clocking schemes used by the host and the target. the maximum baud rate for a can transmission allowing a stable transmission is in the range of 125 kbaud, assuming that the bit sampling point is programmed to be in the middle of a bit time and a maximum resynchronization jump width is select ed. this requires to select the can parameters prop_seg, phase_seg1, phase_seg2 accordingly. the maximum baud rate for an uart transmission allowing a stable transmission is in the range of 48 kba ud when using an external oscillator frequency of maximum 40mhz, a slower external clock will scale the achievable baud rate accordingly. tran smissions at higher baud rates are not recommended. 8.4.5.1 configuration and detection/measurement flow baud rate measurement is using the system timer module (stm) which is driv en by the system clock. measurement itself is pe rformed by software polling the related i nputs as general purpose io?s, resulting in a detection granularity that is directly related to the execution speed of the software. one main difference of the autobaud f eature is that the system clock is not driven directly by the external oscillator, but it is driv en by the fmpll output. the reason is that to have an optimum resolution for baud rate measurement, the system clock needs to be ne arer to the maximum allowed device?s frequency. this is achieved with the following two steps: 1. using the clock monitor unit (c mu) and the internal rc oscillator (irc), the external frequency is measured using the irc as refe rence to determine this frequency. 2. based on the result of this meas urement, the fmpll is programmed to generate a system clock that is configured to be near, but lower, to the maximum allowed frequency. after setting up the system clock, th e bam code continously searches fo r a falling edge on either the can rx input or the uart rx input; a falling edge of the can rx input takes precedence. for this purpose. the can rx and uart rx inputs are both configured as gpio inputs. in case a fal ling edge is detected on any input, the corresponding autobaud m easurement functionality is started: ? a falling edge on can rx (corresponds to pin b[1]) starts the can autobaud measurement and then sets up the flexcan baud rate accordingly ? a falling edge on uart rx (corresponds to pi n b[3]) starts the uart autobaud measurement and then sets up the linflex baud rate accordingly
boot assist module (bam) 8-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 after performing the autobaud measurement and set ting up the baud rate, the corresponding rx input is reconfigured and the related standard download process is started; in ca se of a detected can transmission a download using the can pr otocol as described in section 8.4.4, can boot ? autobaud disabled , and in case of a detected uart transmission a downl oad using the uart protocol as described in section 8.4.3, uart boot ? autobaud disabled . the following figure 8-6 identifies the corresponding flow and steps. figure 8-6. autobaud configuration and detection/measurement flow 8.4.5.2 autobaud measurement for linflex / uart protocol enabling the autobaud feature when us ing the uart protocol assumes that first an additional byte is sent from host to mcu. its va lue is 0x00, resulting in a high - low - high transition visible on the uart rx pin. determine clock frequency of external oscillator program pll accordingly falling edge at flexcan rx ? falling edge at linflex rx ? autobaud measurement for flexcan autobaud measurement for linflex set matching baud rate / flexcan set matching baud rate / linflex detected detected continue with uart download continue with can download can autobaud uart autobaud
boot assist module (bam) freescale semiconductor 8-13 pxs20 microcontroller reference manual, rev. 1 figure 8-7. autobaud measurement / uart protocol initially the uart rx pin is configured as gpio i nput and the bam code waits polling for the first falling edge. upon detection of this edge, the stm starts. subsequently, the uar t rx pin is again polled, waiting for a rising edge. upon detection of this edge, the stm is stopped and from the measured time, the used baud rate is computed. the error introduced due to this polling will be smal l, but might be visible. higher baud rates may be used, but cust omers will be requi red to ensure they fall within acceptable error ranges. this is shown in figure 8-8 which shows the effect of quantizat ion error on the ba ud rate selection. figure 8-8. baud rate deviation between host and pxs20 this additional, first byte is used to measure the transmission time fro m the falling edge until the rising edge. its length will be equivalent to a start bit (l ow), followed by eight data bits (low), followed by a stop bit (high); therefore the low transmission ti me should be equivalent to 9 bit times. from the measured time it is possible to determine the used baud rate in relation to the cu rrent system clock selection. the following e quation gives the relation be tween baud rate and linfle x register configuration: ldiv is an unsigned fixed point number and its valu e is reflected in the related linflex?s registers (linibrr, linfbrr). start bit 0x0 time measurement ldiv f cpu 16 baudrate ? ---------------------------------- =
boot assist module (bam) 8-14 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 upon reception of this zero byte and the configurat ion of the corresponding baud rate, an acknowledge byte is returned by the bam code to the host using th e selected baud rate. this acknowledge byte is the ascii char ?y? (0x59). from th is point bam follows the norm al uart mode boot protocol. 8.4.5.3 autobaud measurement for flexcan / can protocol enabling the autobaud feature when using the can protocol assumes th at the following additional can frame is sent initially from the host to the mcu for baud measurement purposes: ? standard identifier = 0x0, ? data length code (dlc) = 0x0. as all the bits to be transmitted are dominant bits, there is a successi on of 5 dominant bits and 1 stuff bit on the flexcan network (see figure 8-9 ). figure 8-9. autobaud measurement / can protocol initially the can rx pin is configur ed as gpio input and the bam code waits polling for the first falling edge. upon detection of this edge, the stm starts. subsequently, the can rx pin is again polled, waiting for a series of low-high transitions . upon detection of this sequence, the stm is stopped and from the measured time, the used baud rate is computed. the error introduced due to this polling will be small, but might be visible. the calculation of the flexcan baud rate allows th e operation of the boot loader with a wide range of baudrates. however, the upper and lower limits of related parameters have to be kept in mind, in order to ensure proper data transfer. the maximum permissible baud rate th at can be supported is 1mbit/s. from this additional frame being tr ansmitted initially, the mcu calc ulates the corresponding baud rate factor with respect to the current cpu clock and init ializes the flexcan control register (especially the fields presdiv, rjw, pseg1, pseg2, and propseg) accordingly. after measuring a predefined number of bit times, the resulting transmis sion time can be determined from the stm time base; this value is then used to select presdiv and the desired nu mber of time quanta. the number of time quanta in a fl excan bit time is given by: where ? syncseg = exactly one time quantum. ? tseg1 = progpseg + pseg1 +2 ? tseg2 = pseg2 + 1 start stuff bit stuff bit stuff bit stuff bit measured time bittime syncseg tseg 1 tseg 2 ++ =
boot assist module (bam) freescale semiconductor 8-15 pxs20 microcontroller reference manual, rev. 1 flexcan protocol specifies that the flexcan bit timing should compri se a minimum of 8 time quanta and a maximum of 25 time quanta. therefore available range is: all other values defining transmissi on parameters are derived from th e number of desired time quantas. to help compensate for any error in the calculated baud rate, the resynchronizat ion jump width will be increased from its default value of 1. tseg1 and ts eg2 times have been chosen to preserve a sample time in the second half of the bit time. upon reception of this initial can frame, the corr esponding baud rate is configured by the bam code. from this point bam follows th e normal can mode boot protocol. 8.4.5.4 shadow flash code improvements and extensions (for cut2 only) the original bam rom code delive rs minimal support of the aut obaud feature with the following limitations: ? only external oscillator frequencies larger th an the irc frequency (~ 16 mhz) are supported, lower frequencies will cause a cr itical fault during measuring the external oscill ator frequency ? measurement inaccuracies for bot h autobaud measurements (can a nd uart) may result in large quantization errors. subsequently the calculated baud rate might be not deterministic and fail to match the baud rate selected by the host ? usage of the can protocol is not possible with the autobaud feature to fully support the autobaud feature, an extension of the related bam code is provided in the shadow flash, which corrects the above issues and si gnificantly improves the measurement accuracy. note the corresponding code can only be executed on unsecured devices, on devices with a censored flash the shadow flash can not be accessed in serial boot modes. the function called by the read_f rom_tf macro is vle code. th erefore the mmu programming for the memory range occupied by the bam (which incl udes this function) needs to select vle code, otherwise calling this function will fail. since the corresponding code will also be erased when the shadow flash is eras ed, the corresponding code image is available to allow re-programming the relate d shadow flash locations. th is re-programming step is required to preserve the related code improvements in the shadow flas h. it can be skipped, if the usage of the autobaud feature is not intended. 8.4.6 reading from test flash [cut2/3only] there are some factor y settings stored duri ng final test in the test flash (mostly calibrati on information), which are needed by application software. the related data is: a) temperature sensor 1 calibration word 1 .. 4 b) temperature sensor 2 calibration word 1 .. 4 81 tseg 1 tseg 2 ++ ?? 25 ??
boot assist module (bam) 8-16 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 c) adc 0 calibration word 1 .. 8 d) adc 1 calibration word 1 .. 8 e) part id 1 l/h f) part id 2 however, accessing the test flash requires to set the sctr tfe bit in the sscm, which ? will replace the ?normal? flash memory space with the test flash block (while tfe is set), and ? is only possible one time after a reset of the device therefore retrieving these values us ually requires several steps when pe rformed by code stored in flash: 1. copying a corresponding function xyz( ) to access this data from the ? normal? flash into ram 2. switching between ?normal? flash and test flash acces s by setting the sctr tfe bit 3. executing the function xyz( ) to copy the data from test flash into ram 4. clear the sctr tfe bit to sw itch back to ?normal? flash this has been reported as inconvini ent by customers, theref ore a supporting function has been added to the bam, which will perform the corre sponding actions. this function will copy the above factory settings into a given memory location, without the need to copy the corresponding code into the ram. the location of this function is iden tified by a vector located in the location at address 0xffff_dff0. this function receives a 32-bit a ddress, which specifies the start addres s of a 1024 byte wide buffer that will receive the data to be retrieved. this function return s a 32 bit value that denotes either success (value 0), an erroneous second attempt to access the test flash (value 4), or an erroneous access due to the fact that the test flash is not available or can not be accessed due to other reasons (value 8). the provided header file specifies a c onvenience function call macro read_from_tf(,) that allows to call this function with its parameter and provides the return status in . it further specifies some convenience code to access the retrieved information. note since the ?normal? flash and related interrupt and/or exception handlers defined in this memory space are not available during the runtime of this function, it is the respons ibility of the calling code to ensure that no interrupts or exceptions can occur. 8.4.7 inhibiting bam operation under certain circumstances, you may want to inhi bit bam operation. to do this, set the error[pae] bit in the sscm (see section 48.3.1.3, error configuration (error) ). any attempt to access the memory range occupied by the bam will then result in an access error. 8.4.8 interrupt no interrupts are generated by or are enabled by the bam.
analog-to-digital converter (adc) freescale semiconductor 9-1 pxs20 microcontroller reference manual, rev. 1 chapter 9 analog-to-digital converter (adc) 9.1 introduction the analog-to-digital converter (adc ) block provides accurate and fast conversions for a wide range of applications. this device includes two adc modules , referred to as adc_0 and adc_1. external adc channels: ? 9 external channels on adc_0 (channels 0..8) ? 9 external channels on adc_1 (channels 0..8) ? 4 external channels shared betw een adc_0 and adc_1 (channels 11..14) the internal connections of peripherals to adc channels are as follows: ? tsens_0 = adc_0 channel 15 ? tsens_1 = adc_1 channel 15 ? vreg_1.2v = adc_0 channel 10 and adc_1 channel 10 9.2 features the adc contains advanced features for normal or injected conversion. a conversi on can be triggered by software or hardware (ctu). the adc on pxs20 supports 16 internal ly-multiplexed precision channels (ans), all of which have the same accuracy. the mask registers present within the adc can be programmed to configure wh ich channel has to be converted. conversion timing registers are used to configure different sampling and conversion times. on pxs20, two such registers are provided ? one for configur ing the precision channels (0?14) and one for the temperature sensor channel. analog watchdogs allow conti nuous hardware monitoring. 9.3 memory map and register descriptions table 9-1. bit access descriptions access type description read/write (rw) software can read and write to these bits. read-only (r) software can only read these bits. write-only (w) software can only write to these bits. write 1 to clear (w1c) software can clear bits by writing ?1?.
analog-to-digital converter (adc) 9-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 9.3.1 memory map table 9-2. adc memory map address offset register location 0x000 main configuration register (mcr) on page 9-4 0x004 main status register (msr) on page 9-6 0x008?0x00c reserved 0x010 interrupt status register (isr) on page 9-8 0x014 channel pending register 0 (ceocfr0) on page 9-8 0x018?0x01c reserved 0x020 interrupt mask register (imr) on page 9-9 0x024 channel interrupt mask register 0 (cimr0) on page 9-10 0x028?0x02c reserved 0x030 watchdog threshold interrupt register (wtisr) on page 9-10 0x034 watchdog threshold interrupt mask register (wtimr) on page 9-11 0x038?0x03c reserved 0x040 dma enable register (dmae) on page 9-12 0x044 dma channel select register 0 (dmar0) on page 9-12 0x048?0x05c reserved 0x060 threshold register 0 (thrhlr0) on page 9-13 0x064 threshold register 1 (thrhlr1) on page 9-13 0x068 threshold register 2 (thrhlr2) on page 9-13 0x06c threshold register 3 (thrhlr3) on page 9-13 0x070?0x07c reserved 0x080 presampling control register (pscr) on page 9-14 0x084 presampling register 0 (psr0) on page 9-15 0x088?0x090 reserved 0x094 conversion timing register 0 (ctr0) on page 9-15 0x098 conversion timing register 1 (ctr1) on page 9-16 0x09c?0x0a0 reserved 0x0a4 normal conversion mask register 0 (ncmr0) on page 9-17 0x0a8?0x0b0 reserved 0x0b4 injected conversion mask register 0 (jcmr0) on page 9-18 0x0b8?0x0c4 reserved 0x0c8 power down exit delay register (pdedr) on page 9-18
analog-to-digital converter (adc) freescale semiconductor 9-3 pxs20 microcontroller reference manual, rev. 1 0x0cc?0x0fc reserved 0x100 channel 0 data register (cdr0) on page 9-19 0x104 channel 1 data register (cdr1) on page 9-19 0x108 channel 2 data register (cdr2) on page 9-19 0x10c channel 3 data register (cdr3) on page 9-19 0x110 channel 4 data register (cdr4) on page 9-19 0x114 channel 5 data register (cdr5) on page 9-19 0x118 channel 6 data register (cdr6) on page 9-19 0x11c channel 7 data register (cdr7) on page 9-19 0x120 channel 8 data register (cdr8) on page 9-19 0x124 channel 9 data register (cdr9) on page 9-19 0x128 channel 10 data register (cdr10) on page 9-19 0x12c channel 11 data register (cdr11) on page 9-19 0x130 channel 12 data register (cdr12) on page 9-19 0x134 channel 13 data register (cdr13) on page 9-19 0x138 channel 14 data register (cdr14) on page 9-19 0x13c channel 15 data register (cdr15) on page 9-19 0x140?0x280 reserved 0x280 threshold register 4 (thrhlr4) on page 9-13 0x284 threshold register 5 (thrhlr5) on page 9-13 0x288 threshold register 6 (thrhlr6) on page 9-13 0x28c threshold register 7 (thrhlr7) on page 9-13 0x290 threshold register 8 (thrhlr8) on page 9-13 0x294 threshold register 9 (thrhlr9) on page 9-13 0x298 threshold register 10 (thrhlr10) on page 9-13 0x29c threshold register 11 (thrhlr11) on page 9-13 0x2a0 threshold register 12 (thrhlr12) on page 9-13 0x2a4 threshold register 13 (thrhlr13) on page 9-13 0x2a8 threshold register 14 (thrhlr14) on page 9-13 0x2ac threshold register 15 (thrhlr15) on page 9-13 0x2b0 channel watchdog selection register 0 (cwsel0) on page 9-20 0x2b4 channel watchdog selection register 1 (cwsel1) on page 9-20 0x2b8?0x2dc reserved table 9-2. adc memory map (continued) address offset register location
analog-to-digital converter (adc) 9-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 9.3.2 control logic registers 9.3.2.1 main configuration register (mcr) the main configuration register (mcr) pr ovides configuration settings for the adc. 0x2e0 channel watchdog enable register 0 (cwenr0) on page 9-21 0x2e4?0x2ec reserved 0x2f0 analog watchdog out of range register 0 (aworr0) on page 9-21 0x2f4?0x33c reserved 0x340 self test configurat ion register 1 (stcr1) on page 9-22 0x344 self test configurat ion register 2 (stcr2) on page 9-23 0x348 self test configurat ion register 3 (stcr3) on page 9-25 0x34c self test baud rate register (stbrr) on page 9-26 0x350 self test status register 1 (stsr1) on page 9-27 0x354 self test status register 2 (stsr2) on page 9-29 0x358 self test status register 3 (stsr3) on page 9-29 0x35c self test status register 4 (stsr4) on page 9-30 0x360?0x36c reserved 0x370 self test data register 1 (stdr1) on page 9-30 0x374 self test data register 2 (stdr2) on page 9-31 0x378?0x37c reserved 0x380 self test analog watchdog register 0 (staw0r) on page 9-31 0x384 self test analog watchdog register 1a (staw1ar) on page 9-32 0x388 self test analog watchdog register 1b (staw1br) on page 9-33 0x38c self test analog watchdog register 2 (staw2r) on page 9-33 0x390 self test analog watchdog register 3 (staw3r) on page 9-34 0x394 self test analog watchdog register 4 (staw4r) on page 9-34 0x398 self test analog watchdog register 5 (staw5r) table 9-2. adc memory map (continued) address offset register location
analog-to-digital converter (adc) freescale semiconductor 9-5 pxs20 microcontroller reference manual, rev. 1 address: base + 0x000 access: user read/write 0123456789101112131415 r owren wlside mode 0000 nstart 0 jtrgen jedge jstart ref_range_exp 0 ctuen 0 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r stcl 000000 adclk sel abort chain abort acko 0000 pwdn w reset00000000 00000001 figure 9-1. main configuration register (mcr) table 9-3. mcr field descriptions field description owren overwrite enable this bit enables or disables the functi onality to overwrite unread converted data. 0 prevents overwrite of unread converted data; new result is discarded. 1 enables converted data to be overwritten by a new conversion. wlside write left/right-aligned 0 the conversion data is written right-aligned. 1 data is left-aligned (from 15 to (15 ? resolution + 1)). mode one shot/scan 0 one shot mode?configures the nor mal conversion of one chain. 1 scan mode?configures continuous chain conversion mode; when the programmed chain conversion is finished it restarts immediately. nstart normal start conversion setting this bit starts the chain or scan conversion. clearing this bit during scan mode causes the current chain conversion to finish, then stops the operation. this bit stays high while the conversion is ongoing (or pending during injection mode). 0 causes the current chain conversion to finish and stops the operation. 1 starts the chain or scan conversion. jtrgen injection external trigger enable 0 external trigger disabled for channel inject ion (injected conversion cannot be started using an external signal). 1 external trigger enabled for channel injection. jedge injection trigger edge selection edge selection for external trigger, if jtrgen = 1. 0 selects falling edge for the external trigger. 1 selects rising edge for the external trigger. jstart injection start setting this bit will start the configured injected analog channels to be converted by software. clearing this bit has no effect, as the injected chain conversion cannot be interrupted.
analog-to-digital converter (adc) 9-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 9.3.2.2 main status register (msr) the main status register (msr) pr ovides status bits for the adc. ref_range_exp this is a control bit programmed by the user, which specifie s the expected value of msr[ref_range]. if the expected value does not match with the actual value, an isr bit is set. ctuen cross trigger unit enable 0 the cross triggering unit is disabled and the triggered injected conversion cannot occur. 1 the cross triggering unit is enabled and the triggered injected conversion can occur. stcl self testing configuration lock 0no lock 1 the self-testing configuration is locked i.e. stcr1, stcr2, stcr3, stbrr, staw0r, staw1ar, staw1br, staw2r, staw3r, staw4r, staw5r are write-protected. it can be used only in cpu and scan mode. the lock bit is cleared only by a peripheral reset. adclksel analog clock frequency selector if this bit is set the ad_clk frequency is equal to the system clock frequency. otherwise, it is half of the system clock frequency. this bit can be written in power-down mode only. abortchain abort chain when this bit is set, the ongoing chain conversion is aborted. this bit is cleared by hardware as soon as a new conversion is requested. 0 conversion is not affected. 1 aborts the ongoing chain conversion. abort abort conversion when this bit is set, the ongoing conversion is aborted and a new conversion is invoked. this bit is cleared by hardware as soon as a new conversion is invoked. 0 conversion is not affected. 1 aborts the ongoing conversion. acko auto-clock-off enable if set, this bit enables the auto clock off feature. 0 auto clock off is disabled. 1 auto clock off is enabled. pwdn power-down enable when this bit is set, the analog module is requested to enter power down mode. when adc status is pwdn, clearing this bit starts adc transition to idle mode. 0 adc is in normal mode. 1 adc has been requested to power down. table 9-3. mcr field descriptions (continued) field description
analog-to-digital converter (adc) freescale semiconductor 9-7 pxs20 microcontroller reference manual, rev. 1 address: base + 0x004 access: user read-only 0123456789101112131415 r 0000000 nstart jabort 00 jstart ref_range 00 ctustart w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r chaddr 0 00 acko 00 adcstatus w reset00000000 00000001 figure 9-2. main status register (msr) table 9-4. msr field descriptions field description nstart this status bit is used to signal that a normal conversion is ongoing. jabort this status bit is used to signal that an injected conversion has been aborted. this bit is reset when a new injected conversion starts. jstart this status bit is used to signal that an injected conversion is ongoing. ref_range this bit defines the voltage range for operation of the adc. it is provided as an output by the adc, along with data, after every conversion. 0 reference voltage is less than or equal to 3.6 v 1 reference voltage is greater than 4.5 v note: if the reference voltage is outside of the ranges specified here, the value of ref_range can be 0 or 1 depending on the supp ly, process, and temperature. ctustart this status bit is used to signal that a ctu conversion is ongoing. this bit is set when a ctu trigger pulse is received and the ctu conversion starts. when ctu trigger mode is enabled this bit is automatically reset when the conversion is completed. otherwise, if control mode is enabled this bit is reset when the ctu is disabled (ctuen set to ?0?). chaddr channel under measure address this status bit is used to signal which channel is under measure. acko auto-clock-off enable this status bit is used to signal if the auto-clock-off feature is on. adcstatus the value of this parameter depends on adc status: 000 idle 001 power-down 010 wait state 011 ? 100 sample 101 ? 110 conversion 111 ?
analog-to-digital converter (adc) 9-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 9.3.3 interrupt registers 9.3.3.1 interrupt status register (isr) the interrupt status register (isr) cont ains interrupt status bits for the adc. 9.3.3.2 channel pending register 0 (ceocfr0) address: base + 0x010 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ref_range 000000 0 000 eoctu jeo c jec h eoc ech ww1c w1c w1c w1c w1c w1c reset00000000 00000000 figure 9-3. interrupt status register (isr) table 9-5. isr field descriptions field description ref_range this bit is set if ref_range output fr om the adc does not match with the expected value programmed in the mcr. eoctu end of ctu conversion interrupt flag. it is the interrupt of the digital end of conversion for the ctu channel; active when set. when this bit is set, an eoctu interrupt has occurred. jeoc end of injected channel conversion interrupt flag. it is the interrupt of the digital end of conversion for the injected channel; active when set. when this bit is set, a jeoc interrupt has occurred. jech end of injected chain conversion interrupt flag. it is the interrupt of the digital end of chain conversion for the injected channel; active when set. when this bit is set, a jech interrupt has occurred. eoc end of channel conversion interrupt flag. it is th e interrupt of the digital end of conversion. when this bit is set, an eoc interrupt has occurred. ech end of chain conversion interrupt flag. it is th e interrupt of the digital end of chain conversion. when this bit is set, an ech interrupt has occurred.
analog-to-digital converter (adc) freescale semiconductor 9-9 pxs20 microcontroller reference manual, rev. 1 9.3.3.3 interrupt mask register (imr) the interrupt mask register (imr) contains the interrupt enable bits for the adc. address: base + 0x014 access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reoc _ch 15 eoc _ch 14 eoc _ch 13 eoc _ch 12 eoc _ch 11 eoc _ch 10 eoc _ch 9 eoc _ch 8 eoc _ch 7 eoc _ch 6 eoc _ch 5 eoc _ch 4 eoc _ch 3 eoc _ch 2 eoc _ch 1 eoc _ch 0 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 figure 9-4. channel pending register 0 (ceocfr0) table 9-6. ceocfr0 field descriptions field description eoc_ch n this field indicates the end of conversion. 0 the measure of channel n is not complete. 1 the measure of channel n is complete. address: base + 0x020 access: user read/write 0123456789101112131415 r0000000 0 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r msk_ref_range 000000 0 000 mskeoctu mskjeoc mskjech mskeoc mskech w reset00000000 00000000 figure 9-5. interrupt mask register (imr)
analog-to-digital converter (adc) 9-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 9.3.3.4 channel interrupt mask register 0 (cimr0) 9.3.4 watchdog threshold interrupt status register (wtisr) table 9-7. imr field descriptions field description msk_ref_range when set interrupt corresponding to ref_range bit in isr is enabled. mskeoctu mask bit for eoctu when set, the eoctu interrupt is enabled. mskjeoc mask bit for jeoc when set, the jeoc interrupt is enabled. mskjech mask bit for jech when set, the jech interrupt is enabled. mskeoc mask bit for eoc when set, the eoc interrupt is enabled. mskech mask bit for ech when set, the ech interrupt is enabled. address: base + 0x024 access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cim 15 cim 14 cim 13 cim 12 cim 11 cim 10 cim 9 cim 8 cim 7 cim 6 cim 5 cim 4 cim 3 cim 2 cim 1 cim 0 w reset00000000 00000000 figure 9-6. channel interrupt mask register 0 (cimr0) table 9-8. cimr0 field descriptions field description cim n this field enables the interrupt for channel n . 0 interrupt for channel n is disabled. 1 interrupt for channel n is enabled.
analog-to-digital converter (adc) freescale semiconductor 9-11 pxs20 microcontroller reference manual, rev. 1 9.3.5 watchdog threshold interr upt mask register (wtimr) address: base + 0x030 access: user read/write 0123456789101112131415 rwdg 15h wdg 15l wdg 14h wdg 14l wdg 13h wdg 13l wdg 12h wdg 12l wdg 11h wdg 11l wdg 10h wdg 10l wdg 9h wdg 9l wdg 8h wdg 8l w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rwdg 7h wdg 7l wdg 6h wdg 6l wdg 5h wdg 5l wdg 4h wdg 4l wdg 3h wdg 3l wdg 2h wdg 2l wdg 1h wdg 1l wdg 0h wdg 0l w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 figure 9-7. watchdog threshold interrupt status register (wtisr) table 9-9. wtisr field descriptions field description wdg n l reading this field indicates whether an interrupt has been generated due to the converted value being lower than the programmed lower threshold. 0 converted value is higher or equal to the programmed lower threshold (no interrupt generated) 1 converted value is lower than the programmed lower threshold (interrupt is generated) wdg n h reading this field indicates whether an interrupt has been generated due to the converted value being higher than the programmed higher threshold. 0 converted value is lower or equal to the programmed higher threshold (no interrupt generated) 1 converted value is higher than the programm ed higher threshold (interrupt is generated) address: base + 0x034 access: user read/write 0123456789101112131415 r mskwdg15h mskwdg15l mskwdg14h mskwdg14l mskwdg13h mskwdg13l mskwdg12h mskwdg12l mskwdg11h mskwdg11l mskwdg10h mskwdg10l mskwdg9h mskwdg9l mskwdg8h mskwdg8l w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r mskwdg7h mskwdg7l mskwdg6h mskwdg6l mskwdg5h mskwdg5l mskwdg4h mskwdg4l mskwdg3h mskwdg3l mskwdg2h mskwdg2l mskwdg1h mskwdg1l mskwdg0h mskwdg0l w reset00000000 00000000 figure 9-8. watchdog threshold interrupt mask register (wtimr)
analog-to-digital converter (adc) 9-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 9.3.6 dma enable register (dmae) 9.3.7 dma channel select register 0 (dmar0) table 9-10. wtimr field descriptions field description mskwdg n l mask bit for the interrupt generated due to the converted value being lower than the programmed lower threshold. 0 interrupt is not enabled 1 interrupt is enabled mskwdg n h mask bit for the interrupt generated due to the converted value being lower than the programmed lower threshold. 0 interrupt is not enabled 1 interrupt is enabled address: base + 0x040 access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000 000000 dcl r dma en w reset00000000 00000000 figure 9-9. dma enable register (dmae) table 9-11. dmae field descriptions field description dclr dma clear sequence enable 0 dma request is cleared by an acknowledge from dma controller 1 dma request is cleared when a read of data registers occurs dmaen dma global enable 0 the dma feature is disabled 1 the dma feature is enabled
analog-to-digital converter (adc) freescale semiconductor 9-13 pxs20 microcontroller reference manual, rev. 1 9.3.8 threshold registers (thrhlr n ) address: base + 0x044 access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dma 15 dma 14 dma 13 dma 12 dma 11 dma 10 dma 9 dma 8 dma 7 dma 6 dma 5 dma 4 dma 3 dma 2 dma 1 dma 0 w reset00000000 00000000 figure 9-10. dma channel select register 0 (dmar0) table 9-12. dmar0 field descriptions field description dma n dma enable 0 dma transfer for channel n is disabled 1 channel n is enabled to transfer data in dma mode address: see ta b l e 9 - 2 access: user read/write 0123456789101112131415 r0000 thrh w reset00001111 11111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000 thrl w reset00000000 00000000 figure 9-11. threshold registers (thrhlr n ) table 9-13. thrhlr n field descriptions field description thrh high threshold value for channel n (see section 9.4.6, programmable analog watchdog ) thrl low threshold value for channel n (see section 9.4.6, programmable analog watchdog )
analog-to-digital converter (adc) 9-14 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 9.3.9 presampling registers 9.3.9.1 presampling control register (pscr) address: base + 0x080 access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000 00000 preval0 pre con v w reset00000000 00000000 figure 9-12. presampling control register (pscr) table 9-14. pscr field descriptions field description preval0 internal voltage selection for presampling (see ta b l e 9 - 1 5 ) 00 select the v0 internal presampling voltage 01 select the v1 internal presampling voltage 10 reserved 11 reserved preconv convert presampled value 0 the adc will perform a sampling followed by a conversion 1 the adc will perform a presampling followed by a conversion (the sampling is bypassed, so the conversion result is that of the presampled value) table 9-15. presampling voltages pscr[preval0] voltage label voltage for adc_0 voltage for adc_1 v0 vdd_hv_adr0 vdd_hv_adr1 v1 vss_hv_adr0 vss_hv_adr1
analog-to-digital converter (adc) freescale semiconductor 9-15 pxs20 microcontroller reference manual, rev. 1 9.3.9.2 presampling register 0 (psr0) 9.3.10 conversion timing registers 9.3.10.1 conversion timing register 0 (ctr0) this register configures the c onversion timing for channels 0?14. ti mings for channel 15 (the tsens channel) are configured using ctr1 (see section 9.3.10.2, conversion timing register 1 (ctr1) ). address: base + 0x084 access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pre s15 pre s14 pre s13 pre s12 pre s11 pre s10 pre s9 pre s8 pre s7 pre s6 pre s5 pre s4 pre s3 pre s2 pre s1 pre s0 w reset00000000 00000000 figure 9-13. presampling register 0 (psr0) table 9-16. psr0 field descriptions field description pres n presampling enable 0 presampling for channel n is disabled 1 presampling for channel n is enabled address: base + 0x094 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r inp latch 0 offshift 0 inpcmp 0 inpsamp w reset00000010 00000011 figure 9-14. conversion timing register 0 (ctr0) table 9-17. ctr0 field descriptions field description inplatch configuration bit for latching phase duration (see figure 9-15 )
analog-to-digital converter (adc) 9-16 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 9-15. conversion timing 9.3.10.2 conversion timing register 1 (ctr1) this register configures th e conversion timings for channel 15 (the tsens channel). offshift configuration for offset shift characteristic 00 no shift (that is the transition between codes 000h and 001h) is reached when the a vin (analog input voltage) is equal to 1 lsb. 01 transition between code 000h and 001h is reached when the a vin is equal to1/2 lsb 10 transition between code 00h and 001h is reached when the a vin is equal to 0 11 not used inpcmp configuration bits for comparison phase duration (see ta b l e 9 - 1 8 ) inpsamp configuration bits for sampling phase duration (see figure 9-15 ) table 9-18. minimum ad_ck frequency inpcmp ad_ck min. freq (mhz) 01 3 10 6 11 9 00 12 table 9-17. ctr0 field descriptions (continued) field description inplatch=0 inpcmp inplatch=1 ad_ck =00b *internally forced tbiteval 1/2tck 1/2tck* tbiteval =1 =10b 1/2 tck 1 tck 1 tck 1.5 tck 1 tck 2 tck tbiteval =11b tbiteval
analog-to-digital converter (adc) freescale semiconductor 9-17 pxs20 microcontroller reference manual, rev. 1 9.3.11 mask registers these registers are used to program which of the input channels must be converted during normal and injected conversion. 9.3.11.1 normal conversion mask register 0 (ncmr0) address: base + 0x098 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r inp latch 0000 inpcmp 0 inpsamp tsensor_ sel w reset00000010 00000011 figure 9-16. conversion timing register 1 (ctr1) table 9-19. ctr1 field descriptions field description inplatch configuration bit for latching phase duration (see figure 9-15 ) inpcmp configuration bits for comparison phase duration (see ta bl e 9 - 1 8 ) inpsamp configuration bits for sampling phase duration (see figure 9-15 ) tsensor_ sel select the operating mode of the tsens module (see section 50.4, modes of operation ) 0 select ptat mode 1 select ctat mode address: base + 0x0a4 access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ch1 5 ch1 4 ch1 3 ch1 2 ch1 1 ch1 0 ch9 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 w reset00000000 00000000 figure 9-17. normal conversion mask register 0 (ncmr0)
analog-to-digital converter (adc) 9-18 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 9.3.11.2 injected conversion mask register 0 (jcmr0) 9.3.12 power down exit delay register (pdedr) table 9-20. ncmr0 field descriptions field description ch n sampling enable 0 sampling is disabled for channel n 1 sampling is enabled for channel n address: base + 0x0b4 access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ch1 5 ch1 4 ch1 3 ch1 2 ch1 1 ch1 0 ch9 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 w reset00000000 00000000 figure 9-18. injected conversion mask register 0 (jcmr0) table 9-21. jcmr0 field descriptions field description ch n sampling enable 0 sampling is disabled for channel n 1 sampling is enabled for channel n address: base + 0x0c8 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 0 pded w reset00000000 00000000 figure 9-19. power-down exit delay register (pdedr) table 9-22. pdedr field descriptions field description pded the delay between the power-down bit reset and the start of conversion the power down delay is calculated as: pded x (1/frequency of adc clock)
analog-to-digital converter (adc) freescale semiconductor 9-19 pxs20 microcontroller reference manual, rev. 1 9.3.13 channel data registers (cdr n ) address: see ta b l e 9 - 2 . access: user read/write 0123456789101112131415 r0000000 0 0000 va lid ove rw result [0:1] w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000 cdata (mcr[wlside] = 0) w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cdata (mcr[wlside] = 1) 0000 w reset00000000 00000000 figure 9-20. channel data register n (cdr n ) table 9-23. cdr n field descriptions field description valid used to notify when the data is valid (a new valu e has been written). it is automatically cleared when data is read. overw overwrite data this bit signals that the previous converted data has been overwritten by a new conversion. this functionality depends on the value of mcr[owren]: ? when owren = 0, then overw is frozen to 0 and cd ata field is protected aga inst being overwritten until being read. ? when owren = 1, then overw flags the cdata field overwrite status. 0 converted data has not been overwritten 1 previous converted data has been overwritten before having been read result this field reflects the mode of conversion for the corresponding channel. 00 data is a result of normal conversion mode. 01 data is a result of injected conversion mode. 10 data is a result of ctu conversion mode. 11 reserved. cdata channel n converted data. depending on the value of the mcr[wlside] bit, the position of this bitfield can be changed as shown in figure 9-20
analog-to-digital converter (adc) 9-20 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 9.3.14 channel watchdog selection registers (cwsel n ) address: base + 0x2b0 access: user read/write 0123456789101112131415 r wsel_ch7 wsel_ch6 wsel_ch5 wsel_ch4 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r wsel_ch3 wsel_ch2 wsel_ch1 wsel_ch0 w reset00000000 00000000 figure 9-21. channel watchdog selection register 0 (cwsel0) address: base + 0x2b4 access: user read/write 0123456789101112131415 r wsel_ch15 wsel_ch14 w sel_ch13 wsel_ch12 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r wsel_ch11 wsel_ch10 wsel_ch9 wsel_ch8 w reset00000000 00000000 figure 9-22. channel watchdog selection register 1 (cwsel1) table 9-24. cwsel n field descriptions field description wsel_ch n selects the threshold register that provides the values to be used for upper and lower thresholds for channel n 0000 thrhlr0 register is selected 0001 thrhlr1 register is selected ... 1110 thrhlr14 register is selected 1111 thrhlr15 register is selected
analog-to-digital converter (adc) freescale semiconductor 9-21 pxs20 microcontroller reference manual, rev. 1 9.3.15 channel watchdog enable register 0 (cwenr0) 9.3.16 analog watchdog out of range register 0 (aworr0) address: base + 0x2e0 access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cwe n15 cwe n14 cwe n13 cwe n12 cwe n11 cwe n10 cwe n9 cwe n8 cwe n7 cwe n6 cwe n5 cwe n4 cwe n3 cwe n2 cwe n1 cwe n0 w reset00000000 00000000 figure 9-23. channel watchdog enable register 0 (cwenr0) table 9-25. cwenr0 field descriptions field description cwen n enables the watchdog feature for channel n 0 the watchdog feature for channel n is disabled 1 the watchdog feature for channel n is enabled address: base + 0x2f0 access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r awor_ch15 awor_ch14 awor_ch13 awor_ch12 awor_ch11 awor_ch10 awor_ch9 awor_ch8 awor_ch7 awor_ch6 awor_ch5 awor_ch4 awor_ch3 awor_ch2 awor_ch1 awor_ch0 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 figure 9-24. analog watchdog out of range register 0 (aworr0) table 9-26. aworr0 field descriptions field description awor_ ch n out of range indicator 0 channel n converted data is in range 1 channel n converted data is out of range
analog-to-digital converter (adc) 9-22 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 9.3.17 self test registers 9.3.17.1 self test configuration register 1 (stcr1) address: base + 0x340 access: user read/write 0123456789101112131415 r inpsamp_c inpsamp_rc w reset00011000 00011000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r inpsamp_s 00000 st_ inpcmp st_inplatch w reset00100101 00000111 figure 9-25. self test configuration register 1 (stcr1) table 9-27. stcr1 field descriptions field description inpsamp_c sampling phase duration for the test conversions related to the algorithm c inpsamp_rc sampling phase duration for the test conversions related to the algorithm rc inpsamp_s sampling phase duration for the test conversions related to the algorithm s st_inpcmp configuration bits for comparison phase duration for self test channel (as in ta bl e 9 - 1 8 for normal conversion) st_inplatch configuration bits for latching phase duration for self test channel (as in figure 9-15 for normal conversion)
analog-to-digital converter (adc) freescale semiconductor 9-23 pxs20 microcontroller reference manual, rev. 1 9.3.17.2 self test configuration register 2 (stcr2) address: base + 0x344 access: user read/write 0123456789101112131415 r0000 mskwdserr 0 mskwdterr 0 mskst_eoc 0000 mskwdg_eoa_c mskwdg_eoa_rc mskwdg_eoa_s w serr reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r mskerr_c mskerr_rc mskerr_s2 mskerr_s1 mskerr_s0 00 0 en 00 fma_wdserr fma_wdterr fma_c fma_rc fma_s w reset00000000 00000101 figure 9-26. self test configuration register 2 (stcr2) table 9-28. stcr2 field descriptions field description mskwdserr interrupt enable (stsr1[wdserr] status bit) 0 interrupt disabled 1 enables the stsr1[wdserr] status bit to generate an interrupt serr error fault injection control. se tting this bit causes the stsr1[err n ] status bits to be set. mskwdterr interrupt enable (stsr1[wdterr] status bit) 0 interrupt disabled 1 enables the stsr1[wdterr] status bit to generate an interrupt mskst_eoc interrupt enable bit for stsr1[st_eoc] 0 interrupt disabled 1 if imr[mskeoc] = 1, enables t he stsr1[st_eoc] status bit to generate an interrupt indication mskwdg_eoa_c interrupt enable (stsr1[wdg_eoa_c] status bit) 0 interrupt disabled 1 enables the stsr1[wdg_eoa_c] status bit to generate an interrupt mskwdg_eoa_rc interrupt enable (stsr1[wdg_eoa_rc] status bit) 0 interrupt disabled 1 enables the stsr1[wdg_eoa_rc] stat us bit to generate an interrupt mskwdg_eoa_s interrupt enable (stsr1[wdg_eoa_s] status bit) 0 interrupt disabled 1 enables the stsr1[wdg_eoa_s] status bit to generate an interrupt mskerr_c interrupt enable (stsr1[err_c] status bit) 0 interrupt disabled 1 enables the stsr1[err_c] status bit to generate an interrupt
analog-to-digital converter (adc) 9-24 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 mskerr_rc interrupt enable (stsr1[err_rc] status bit) 0 interrupt disabled 1 enables the stsr1[err_rc] status bit to generate an interrupt mskerr_s2 interrupt enable (stsr1[err_s2] status bit) 0 interrupt disabled 1 enables the stsr1[err_s2] status bit to generate an interrupt mskerr_s1 interrupt enable (stsr1[err_s1] status bit) 0 interrupt disabled 1 enables the stsr1[err_s1] status bit to generate an interrupt mskerr_s0 interrupt enable (stsr1[err_s0] status bit) 0 interrupt disabled 1 enables the stsr1[err_s0] status bit to generate an interrupt en self-test channel enable bit. it enables the test channel only in cpu mode . in ctu trigger/control mode the enable is provided directly by ctu. this bit should be set before starting the normal conversion and should not be changed while conversion is ongoing. this bit should be cleared only after end of conversion for the last self test channel has been received. 0 test conversions are disabled 1 test conversions are enabled fma_wdserr fault mapping for the watchdog sequence error. 0 ncf mapping 1 cf mapping fma_wdterr fault mapping for the watchdog timer error. 0 ncf mapping 1 cf mapping fma_c fault mapping for the algorithm c. 0 ncf mapping 1 cf mapping fma_rc fault mapping for the algorithm rc. 0 ncf mapping 1 cf mapping fma_s fault mapping for the algorithm s. 0 ncf mapping 1 cf mapping table 9-28. stcr2 field descriptions (continued) field description
analog-to-digital converter (adc) freescale semiconductor 9-25 pxs20 microcontroller reference manual, rev. 1 9.3.17.3 self test configuration register 3 (stcr3) address: base + 0x348 access: user read/write 0123456789101112131415 r0000000 00000000 0 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000 alg 000 mstep w reset00000011 00000000 figure 9-27. self test configuration register 3 (stcr3) table 9-29. stcr3 field descriptions field description alg algorithm scheduling. this field has different functionality depending on the adc mode (one-shot or scan). for one-shot mode: 00 algorithm s (single step = mstep) 01 algorithm rc (single step = mstep) 10 algorithm c (single step = mstep) 11 algorithm s for test/debug purposes for scan mode: 00 algorithm s 01 algorithm rc 10 algorithm c 11 algorithm s + algorithm rc + algorithm c the baud rate for the execution of the selected algorithm is defined by the stbrr register. mstep for one-shot mode, defines the current step for algorithms s, rc, and c as follows: ? for algorithm s: mstep = 0 to 2 ? for algorithm c: mstep = 0 to 16 ? for algorithm rc: mstep = 0 to 18 for scan mode, this field is not used and should be programmed to 0b00. this is because in scan mode performs only single-step execution (interleaved mode).
analog-to-digital converter (adc) 9-26 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 9.3.17.4 self test baud rate register (stbrr) address: base + 0x34c access: user read/write 0123456789101112131415 r0000000 000000 wdt w reset00000000 00000101 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000 br w reset00000000 00000000 figure 9-28. self test baud rate register (stbrr) table 9-30. stbrr field descriptions field description wdt watchdog timer value. this value is used to monitor that the algorithm sequence is correctly executed within the safe time period. the self testing watchdog is enabled by setting the staw n r[wdte] control bits. a fixed pre-scaler runs on the adc clock (120 mhz). 000 0.1 ms 001 0.5 ms 010 1 ms 011 2 ms 100 5 ms 101 10 ms 110 20 ms 111 50 ms br baud rate for the selected algorithm in scan mode (mcr[mode] = 1). you should program this field before enabling the self test channel. 0x00 maximum scheduling rate (nominal rate) ... 0xff minimum scheduling rate (nominal rate scaled by 255)
analog-to-digital converter (adc) freescale semiconductor 9-27 pxs20 microcontroller reference manual, rev. 1 9.3.17.5 self test status register 1 (stsr1) address: base + 0x350 access: user read/write 0123456789101112131415 r 0000 wdserr 0 wdterr overwr st_eoc 0000 wdg_eoa_c wdg_eoa_rc wdg_eoa_s w w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r err_c err_rc err_s2 err_s1 err_s0 0 step_c step_rc w w1c w1c w1c w1c w1c reset00000000 00000000 figure 9-29. self test status register 1 (stsr1) table 9-31. stsr1 field descriptions field description wdserr watchdog sequence error of the adc sub-syst em (check for algorithm step sequence). it generates an interrupt if enabled (stcr2[mskwdserr] = 1). it provides the fault indication to the fccu, asserting cf or ncf acco rding to the stcr2[fma_wdserr] mapping. 0 no failure 1 failure occurred wdterr watchdog timer error of the adc sub-system (algorithm check for completion within safe time). it generates an interrupt if enabled (s tcr2[mskwdterr] = 1). it provides the fault indication to the fccu, asserting cf or ncf according to the stcr2[fma_wdterr] mapping. 0 no failure 1 failure occurred overwr overwrite error. used to notify when the stsr1[err n ] bit is overwritten by a newer one. the new error status is written or discarded according to the mcr[owren] bit value. to avoid overwr indication, the err n status bit must be cleared (via sw). st_eoc self test eoc bit. if imr[mskeoc] = 1, this bit is set along with eoc bit when end_of_conversion signal is received from adc analog for self test channel. it generates an interrupt if enabled by stcr2[mskst_eoc]. wdg_eoa_c this bit indicates that algorithm c has been completed. this bit is set after the last step of the algorithm is executed. it generates an interrupt if enabled (stcr2[mskwdg_eoa_c] = 1). this bit is set only if staw4r[wdte] = 1. for ctu conversions, this bit is significant only for burst mode of operation. wdg_eoa_rc this bit indicates that algorithm rc has been completed. this bit is set after the last step of the algorithm is executed. it generates an interrupt if enabled (stcr2[mskwdg_eoa_rc] = 1). this bit is set only if staw3r[wdte] = 1. for ctu conversions, this bit is significant only for burst mode of operation.
analog-to-digital converter (adc) 9-28 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 wdg_eoa_s this bit indicates that algorithm s has been completed. this bit is set after the last step of algorithm s is executed. it generates an interrupt if enabled (stcr2[mskwdg_eoa_s] = 1). this bit is set only if staw0r[wdte] = 1. for ctu conversions, this bit is significant only for burst mode of operation. err_c indicates an error on the self testing channel (algorithm c). it generates an interrupt if enabled (stcr2[mskerr_c] = 1). it provides the fault indication to the fccu, asserting the programmed fault line (stcr2[fma n ]) you can also set the err_c bit (fault injection) by setting the stcr2[serr] bit. in this case the cf or ncf lines are asserted according to the stcr2[fma n ] mapping. 0 no c-algorithm error has occurred 1 a c-algorithm error has occurred err_rc indicates an error on the self testing channel (algorithm rc). it generates an interrupt if enabled (stcr2[mskerr_rc] = 1). it provides th e fault indication to the fccu, asserting the programmed fault line (stcr2[fma n ]) you can also set the err_rc bit (fault injection) by setting the stcr2[serr] bit. in this case the cf or ncf lines are asserted according to the stcr2[fma n ] mapping. 0 no rc-algorithm error has occurred 1 an rc-algorithm error has occurred err_s2 indicates an error on the self testing channel (algorithm supply, step 2). it generates an interrupt if enabled (stcr2[mskerr_s2] = 1). it provides the fault indication to the fccu, asserting the programmed fault line (stcr2[fma n ]) you can also set the err_s2 bit (fault injection) by setting the stcr2[serr] bit. in this case the cf or ncf lines are asserted according to the stcr2[fma n ] mapping. 0 no error has occurred on the sampled signal 1 an error has occurred on the sampled signal err_s1 indicates an error on the self testing channel (algorithm supply, step 1). it generates an interrupt if enabled (stcr2[mskerr_s1] = 1). it provides the fault indication to the fccu, asserting the programmed fault line (stcr2[fma n ]) you can also set the err_s1 bit (fault injection) by setting the stcr2[serr] bit. in this case the cf or ncf lines are asserted according to the stcr2[fma n ] mapping. 0 no vdd error has occurred 1 a vdd error has occurred err_s0 indicates an error on the self testing channel (algorithm supply, step 0). it generates an interrupt if enabled (stcr2[mskerr_s0] = 1). it provides the fault indication to the fccu, asserting the programmed fault line (stcr2[fma n ]) you can also set the err_s0 bit (fault injection) by setting the stcr2[serr] bit. in this case the cf or ncf lines are asserted according to the stcr2[fma n ] mapping. 0 no vref error has occurred 1 a vref error has occurred step_c step of the algorithm c when an err_c has occurred. 0.. (num_c_steps-1) => algorithm c step_rc step of the algorithm rc when an err_rc has occurred. 0.. (num_rc_steps-1) => algorithm rc table 9-31. stsr1 field descriptions (continued) field description
analog-to-digital converter (adc) freescale semiconductor 9-29 pxs20 microcontroller reference manual, rev. 1 9.3.17.6 self test status register 2 (stsr2) 9.3.17.7 self test status register 3 (stsr3) address: base + 0x354 access: user read only 0123456789101112131415 rov fl 000 data1 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000 data0 w reset00000000 00000000 figure 9-30. self test status register 2 (stsr2) table 9-32. stsr2 field descriptions field description ovfl overflow bit. this bit is set when the diviso r is zero. if this happens, the stsr1[err_s1] bit is also set. data1 test channel converted data when the err_s1 has occurred. algorithm s (step1) => fractional part of the ratio test(step1)/test (step0) = vdd/vbgap data0 test channel converted data when the err_s1 has occurred. - algorithm s (step1) => integer part of the ratio test(step1)/t est (step0) = vdd/vbgap address: base + 0x358 access: user read only 0123456789101112131415 r0000 data1 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000 data0 w reset00000000 00000000 figure 9-31. self test status register 3 (stsr3) table 9-33. stsr3 field descriptions field description data1 test channel converted data when the err_s2 has occurred. - algorithm s (step2) => test channel data = vref/vref data0 test channel converted data when the err_s0 has occurred. - algorithm s (step0) => test channel data = vbgap/vref
analog-to-digital converter (adc) 9-30 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 9.3.17.8 self test status register 4 (stsr4) 9.3.17.9 self test data register 1 (stdr1) address: base + 0x35c access: user read only 0123456789101112131415 r0000 data1 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000 data0 w reset00000000 00000000 figure 9-32. self test status register 4 (stsr4) table 9-34. stsr4 field descriptions field description data1 test channel converted data when the err_c has occurred. - algorithm c => test channel data data0 test channel converted data when the err_rc has occurred. - algorithm rc => test channel data address: base + 0x370 access: user read only 0123456789101112131415 r 00000000 0000 vali d ove rwr 00 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000 tcdata w reset00000000 00000000 figure 9-33. self test data register 1 (stdr1) table 9-35. stdr1 field descriptions field description valid valid data. used to notify when the data is valid (a new value has been written). it is automatically cleared when data is read. overwr overwrite data. used to notify when a conv ersion data is overwritten by a newer result. the new data is written or discarded according to the mcr[owren] bit value. tcdata test channel converted data
analog-to-digital converter (adc) freescale semiconductor 9-31 pxs20 microcontroller reference manual, rev. 1 9.3.17.10 self test data register 2 (stdr2) 9.3.17.11 self test analog watchdog register 0 (staw0r) address: base + 0x374 access: user read only 0123456789101112131415 r fdata vali d ove rwr 00 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000 idata w reset00000000 00000000 figure 9-34. self test data register 2 (stdr2) table 9-36. stdr2 field descriptions field description fdata fractional part of the ratio test(step1)/t est (step0) = vdd/vbgap for the algorithm s. valid valid data. used to notify when the data is valid (a new value has been written). it is automatically cleared when data is read. overwr overwrite data. used to notify when a conv ersion data is overwritten by a newer result. the new data is written or discarded according to the mcr[owren] bit value. idata integer part of the ratio test(step1)/t est (step0) = vdd/vbgap for the algorithm s address: base + 0x380 access: user read/write 0123456789101112131415 r aw de wdt e 00 thrh w reset00000111 00100111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000 thrl w reset00000100 11000101 figure 9-35. self test analog watchdog register 0 (staw0r)
analog-to-digital converter (adc) 9-32 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 9.3.17.12 self test analog watchdog register 1a (staw1ar) table 9-37. staw0r field descriptions field description awde analog watchdog enable 0 the analog watchdog related to the algorithm s (step 0) is disabled 1 the analog watchdog related to the algorithm s (step 0) is enabled wdte watchdog timer enable. the watchdog timer verifies: ? correct sequence of the algorithm (step sequence) ? execution of the algorithm within the safe time period as defined by stbrr[wdt] as soon as the watchdog timer is enabled the al gorithm starting must be detected within the safe time period. the watchdog timer is reset each time the algorithm restarts. note: this bit should be set only in scan mode. 0 the watchdog timer related to the algorithm s is disabled 1 the watchdog timer related to the algorithm s is enabled thrh high threshold value for channel n . if the analog watchdog is enabled, the stsr1[err n ] status bit is set if stdr1[tcdata] > thrh. thrl low threshold value for channel n . if the analog watchdog is enabled, the stsr1[err n ] status bit is set if stdr1[tcdata] < thrh.. address: base + 0x384 access: user read/write 0123456789101112131415 r aw de 000 thrh w reset00000000 00000011 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000 thrl w reset00000000 00000001 figure 9-36. self test analog watchdog register 1a (staw1ar) table 9-38. staw1ar field descriptions field description awde analog watchdog enable 0 the analog watchdog related to the algorithm s (step 1) is disabled 1 the analog watchdog related to the algorithm s (step 1) is enabled thrh high threshold value (integer part) for test channel for algorithm s (step 1) (unsigned coding) thrl low threshold value (integer part) for test channel for algorithm s (step 1) (unsigned coding)
analog-to-digital converter (adc) freescale semiconductor 9-33 pxs20 microcontroller reference manual, rev. 1 9.3.17.13 self test analog watchdog register 1b (staw1br) 9.3.17.14 self test analog watchdog register 2 (staw2r) address: base + 0x388 access: user read/write 0123456789101112131415 r0000 thrh w reset00000011 11101000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000 thrl w reset00001110 11010000 figure 9-37. self test analog watchdog register 1b (staw1br) table 9-39. staw1br field descriptions field description thrh high threshold value (fractional part) for test channel for algorithm s (step 1)(unsigned coding) thrl low threshold value (fractional part) for test channel for algorithm s (step 1) (unsigned coding) address: base + 0x38c access: user read/write 0123456789101112131415 r aw de 0000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000 thrl w reset00001111 11111001 figure 9-38. self test analog watchdog register 2 (staw2r) table 9-40. staw2r field descriptions field description awde analog watchdog enable 0 the analog watchdog related to the algorithm s (step 2) is disabled 1 the analog watchdog related to the algorithm s (step 2) is enabled thrl low threshold value for channel n (unsigned coding). if the analog watchdog is enabled, the stsr1[err_s2] status bit is set if stdr1[tcdata] analog-to-digital converter (adc) 9-34 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 9.3.17.15 self test analog watchdog register 3 (staw3r) 9.3.17.16 self test analog watchdog register 4 (staw4r) address: base + 0x390 access: user read/write 0123456789101112131415 r aw de wdt e 00 thrh w reset00001000 01101101 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000 thrl w reset00000111 10010011 figure 9-39. self test analog watchdog register 3 (staw3r) table 9-41. staw3r field descriptions field description awde analog watchdog enable 0 the analog watchdog related to the algorithm rc is disabled 1 the analog watchdog related to the algorithm rc is enabled wdte watchdog timer enable. the watchdog timer verifies: ? correct sequence of the algorithm (step sequence) ? execution of the algorithm within the safe time period as defined by stbrr[wdt] as soon as the watchdog timer is enabled the al gorithm starting must be detected within the safe time period. the watchdog timer is reset each time the algorithm restarts. note: this bit should be set only in scan mode. 0 the watchdog timer related to the algorithm rc is disabled 1 the watchdog timer related to the algorithm rc is enabled thrh high threshold value for channel n . if the analog watchdog is enabled, the stsr1[err n ] status bit is set if stdr1[tcdata] > thrh. thrl low threshold value for channel n . if the analog watchdog is enabled, the stsr1[err n ] status bit is set if stdr1[tcdata] < thrh. address: base + 0x394 access: user read/write 0123456789101112131415 r aw de wdt e 00 thrh w reset00001000 00101000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000 thrl w reset00000111 11011000 figure 9-40. self test analog watchdog register 4 (staw4r)
analog-to-digital converter (adc) freescale semiconductor 9-35 pxs20 microcontroller reference manual, rev. 1 9.3.17.17 self test analog watchdog register 5 (staw5r) table 9-42. staw4r field descriptions field description awde analog watchdog enable 0 the analog watchdog related to the algorithm c is disabled 1 the analog watchdog related to the algorithm c is enabled wdte watchdog timer enable. the watchdog timer verifies: ? correct sequence of the algorithm (step sequence) ? execution of the algorithm within the safe time period as defined by stbrr[wdt] as soon as the watchdog timer is enabled the al gorithm starting must be detected within the safe time period. the watchdog timer is reset each time the algorithm restarts. note: this bit should be set only in scan mode. 0 the watchdog timer related to the algorithm c is disabled 1 the watchdog timer related to the algorithm c is enabled thrh high threshold value for channel n . if the analog watchdog is enabled, the stsr1[err n ] status bit is set if stdr1[tcdata] > thrh. note: this value is valid only for the step 0 (refer to staw5r register for the other algorithm c steps). thrl low threshold value for channel n . if the analog watchdog is enabled, the stsr1[err n ] status bit is set if stdr1[tcdata] < thrh. note: this value is valid only for the step 0 (refer to staw5r register for the other algorithm c steps). address: base + 0x398 access: user read/write 0123456789101112131415 r0000 thrh w reset00000000 00010000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000 thrl w reset00000000 00010000 figure 9-41. self test analog watchdog register 5 (staw5r) table 9-43. staw5r field descriptions field description thrh high threshold value (unsigned coding) for the algorithm c (step1 to step cs-1). if the analog watchdog is enabled (staw4r[awde] = 1), th e stsr1[err_c] status bit is set if stdr1[tcdata{stepn}] - stdr1[ tcdata {algc-step0}] > thrh. thrl low threshold value (unsigned coding) for the al gorithm c (step1 to step cs-1). if the analog watchdog is enabled (staw4r[awde] = 1), th e stsr1[err_c] status bit is set if stdr1[tcdata {algc-step0}] - st dr1[tcdata{stepn}] > thrl.
analog-to-digital converter (adc) 9-36 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 9.4 functional description 9.4.1 inter-module communication figure 9-42 shows the modules that communicate with th e adc. in the figure, ?adcd? and ?adca? refer to the digital and analog co mponents of the adc, respectively. figure 9-42. adc interact ion with other modules figure 9-43 shows the ctu / adc interface. each adc can be controlled by the cpu (cpu control mode) or by the ctu (ctu control mode). the ctu can control the adc sending an adc command only when the adc is in ctu control mode. the contro l mode is selected via a configuration bit. you can dynamically switch this mode wi thout generating a reset or a power -down; in this case, however, you must not switch the mode while a conversion is in progress. during the ctu control mode, the cpu is able to write in the adc registers but it can not start a new conversion. interrupt lines bus dma ctu adcd adca
analog-to-digital converter (adc) freescale semiconductor 9-37 pxs20 microcontroller reference manual, rev. 1 figure 9-43. ctu/adc interface 9.4.2 analog channel conversion two conversion modes are available within the adcdig: ? normal conversion ? injected conversion 9.4.2.1 normal conversion this is the normal conversion that the user program s by configuring the normal conversion mask registers (ncmrs). each channel can be individually enab led by setting ?1? in the corresponding ncmr field. mask registers must be programmed before starti ng the conversion and cannot be changed until the conversion of all the selected channe ls ends (msr[nstart] is cleared). 9.4.2.2 start of normal conversion the msr[nstart] status bit is automatically set when the normal conversion starts. at the same time the mcr[nstart] bit is cleared, allo wing the software to program a new start of conversion. in that case the new requested conversion starts afte r the running conversion is completed. dma adc_wd ch_0 adc_eoc adc_er trigger_0 next_cmd_0 adc_push_0 adc_data_0 dma adc_wd ch_1 adc_eoc adc_er trigger_1 next_cmd_1 adc_push_1 adc_data_1 adc 0 adc 1 adca_0 adca_1 adcd_0 adcd_1 ctu
analog-to-digital converter (adc) 9-38 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 if the content of all the normal conversion mask regi sters is zero (that is, no channel is selected) the conversion operation is considered co mpleted and the interrupt ech (see section 9.4.8, interrupts ) is immediately issued after the start of conversion. 9.4.2.3 normal conversion operating modes two operating modes are available for the normal conversion: ? one shot ?scan to enter one of these modes, you must program the mcr[mode] bit. the first phase of the conversion process involves sampling the analog channel and the next phase involve s the conversion phase when the sampled analog value is converted to digital as shown in figure 9-44 . figure 9-44. normal conversion flow in one shot mode (mcr[mode] = 0) a sequential conve rsion specified in the ncmrs is performed only once. at the end of each conversion, the digital result of the conversion is stored in the corresponding data register. example 9-1. one shot mode (mcr[mode] = 0) channels a-b-c-d-e-f-g-h are present in the devi ce where channels b-d-e are to be converted in the one shot mode. mcr[mode] = 0 is set fo r one shot mode. conversion starts from the channel b followed by conversion of channels d- e. at the end of conversion of channel e the scanning of channels stops. the msr[nstart] status bit is automatically set when the normal conversion starts. at the same time the mcr[nstart] bit cleared, allowing the software to program a new start of conversion. in that case the new requested conversion starts afte r the running conversion is completed. in scan mode (mode = 1), a seque ntial conversion of n channels specified in the ncmrs is continuously performed. as in the pr evious case, at the end of each c onversion the digital result of the conversion is stored in th e corresponding data register. the msr[nstart] status bit is automatically set wh en the normal conversion starts. unlike one shot mode, the mcr[nstart] bit is not cleared. it can be cleared by software when the user needs to stop scan mode. in that case, the adc completes the current scan convers ion and, after the la st conversion, also clears the msr[nstart] bit. example 9-2. scan mode (mcr[mode] = 1) channels a-b-c-d-e-f-g-h are present in the devi ce where channels b-d-e are to be converted in the scan mode. mcr[mode] = 1 is set for scan mode. conversi on starts from the channel b followed by conversion of the channels d-e. at the end of conversion of channel e the scanning sample b evaluate b sample c sample d evaluate d sample e evaluate e evaluate c
analog-to-digital converter (adc) freescale semiconductor 9-39 pxs20 microcontroller reference manual, rev. 1 of channel b starts followed by c onversion of the channels d-e. this sequence repeats itself till the mcr[nstart] bit is cleared by software. at the end of each conversion an end of conversion interr upt is issued (if enab led by the corresponding mask bit) and at the end of the co nversion sequence an end of chain inte rrupt is issued (if enabled by the corresponding mask bit). 9.4.2.4 injected channel conversion a conversion chain can be injected into the ongoi ng normal conversion by configuring the injected conversion mask registers (jcmr) . as normal conversion, each channe l can be individually selected. this injected conversion can only occur in one shot mode and interrupts the normal conversion. when an injected conversion is inserted, ongoi ng channel conversion is aborted and the injected channel request is processed. after the last channel in the injected ch ain is converted, normal conversion resumes from the channel at which the normal co nversion was stopped as shown in figure 9-45 . figure 9-45. injected sample/conversion sequence the msr[jstart] status bit is automatically set when the injected conversion starts. at the same time the mcr[jstart] bit is cleared, allowing the software to program a new start of conversion. in that case the new requested conversion starts after th e running injected conversion is completed. at the end of each injected conversion, an end of in jected conversion (jeoc) interrupt is issued (if enabled by the corresponding mask bit) and at the end of the sequence an end of injected chain (jech) interrupt is issued (if enabled by the corresponding mask bit). if the content of all the injected conversion mask registers is zero (t hat is, no channel is selected) the interrupt jech is immediately issu ed after the start of conversion. once started, injected chain conversion cannot be interrupted by any other conversion type. it can, however, be aborted; see section 9.4.2.5, abort conversion. 9.4.2.5 abort conversion two different abort functions are provided. ? the user can abort the ongoing conversion by setting the mcr[abort] bit. the current conversion is aborted and the conve rsion of the next channel of th e chain is immediately started the ongoing channel conversion is interrupted and the injected conversion chain is processed first, after the injected chain is converted the normal chain conversion resumes from the channel at which normal conversion was aborted. injected conversion of channels i and j normal conversion resumes from the last aborted channel. sample b evaluate b sample c sample d evaluate d sample e evaluate e evaluate c sample c abort c sample i sample j evaluate j sample c evaluate c evaluate i
analog-to-digital converter (adc) 9-40 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 (generating a new start pulse to the analog adc). in the case of an abort operation, the nstart/jstart bit remains set and the abort bit is cleared after the conversion of the next channel starts. the eoc corresponding to the aborte d channel is not generated. this behavior is true for normal or triggered/inject ed conversion modes. if the last channel of a chain is aborted, the end of chain is reported generating an ech interrupt. ? it is also possible to abort the current chai n conversion by setting the mcr[abortchain] bit. in that case the behavior of the adc depends on the mcr[mode] bit. in fact, if scan mode is disabled, the nstart bit is automatically cleared together with the abortchain bit. otherwise, if the mode bit is set, a new chai n conversion is started. the eoc of the current aborted conversion is not generated but an ech inte rrupt is generated to signal the end of the chain. when a chain conversion abort is requested (a bortchain bit is set) while an injected conversion is running over a suspended normal conversion, both injected chain and normal conversion chain are aborted (both the nsta rt and jstart bits are also cleared). 9.4.3 analog clock generator and conversion timings the clock frequency can be selected by programming the mcr[adclksel] bi t. when this bit is set, the adc clock has the same frequency as the system cloc k. otherwise, the adc clock is half of the system clock frequency. the mcr[adclksel] bit can be written only in power-down mode. when the internal divider is not enabled (adcclksel = 1), it is important th at the associated clock divider in the clock generation module is ?1?. th is is needed to ensure 50% clock duty cycle. the direct clock should basically be used only in low power mode when the device is using only the 16 mhz fast internal rc oscillator, but the conversi on still requires a 16 mhz clock (an 8 mhz clock is not fast enough). in all other cases, the adc should us e the clock divided by two internally. 9.4.4 adc sampling and conversion timing in order to support different loading and switching times, several different conversion timing registers (ctr) are present. there is one register per channel type. when a conversion is started, the adc connects the in ternal sampling capacitor to the respective analog input pin, allowing the capacitor to ch arge up to the input voltage value. the time to load the capacitor is referred to as sampling time. after completion of th e sampling phase, the evalua tion phase starts and all the bits corresponding to the resolution of the adc are estimated to provide the conversion result. the conversion times are pr ogrammed via the bit fields of the ct r. bit fields inplatch, inpcmp and inpsamp are used to define the total conversion duration (t conv ) and in particular the partition between sampling phase duration (t sample ) and total evaluation phase duration (t eval ). in the following equations, the unit t ck refers to the reciprocal of f ck , where f ck = (1/2 ? adc peripheral set clock).
analog-to-digital converter (adc) freescale semiconductor 9-41 pxs20 microcontroller reference manual, rev. 1 the minimum sampling phase duration is: for inpsamp > 8, the sampling phase duration is: the total evaluation phase duration is: the total conversion duration is (not including external multiplexing): 9.4.5 presampling presampling allows to precharge or discharge the adc internal capacitor before it starts sampling/conversion of the analog input coming from pads. this is useful fo r resetting information regarding the last converted data. during presampli ng, the analog adc samples the internally generated voltage while in the sampling the analog ad c samples analog input coming from pads. presampling can be enabled/disabled on a channel basis by setting the corresponding bits in the psrs. after enabling the presampling for a channe l, normal sequence of operation will be presampling+sampling+convers ion for that channel. sampling of th e channel can be bypassed by setting the pscr[preconv] bit. when samp ling of a channel is bypa ssed, the sampled data of internal voltage in the presampling state will be converted (see figure 9-46 and figure 9-47 ). figure 9-46. presampling sequence figure 9-47. presampling seq uence with preconv = 1 the presampling channels implemented on this device are: t sample 7 t ck ? = t sample inpsamp 1 ? ?? t ck ? = t eval 12 t biteval ? = t conv t sample t eval t ck ++ = presampling is enabled in the channel c and d. for channel c and d, the total number of conversion clock cycles = (presample) + (sample) + (convert). sample b evaluate b presample c evaluate c presample d sample d evaluate d sample c sample e for channel b, the total number of conversion clock cycles = (sample) + (convert). sample b evaluate b presample c presample d evaluate d sample e evaluate e evaluate c presampling enabled in channel c and d but sampling is by passed in these channels by setting pscr[preconv] = 1. for channel c and d, the total number of conversion clock cycles = (presample) + (convert).
analog-to-digital converter (adc) 9-42 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? for adc_0: ? vrefh adc_0 = presampling channel 0 ? vrefl adc_0 = presampling channel 1 ? for adc_1: ? vrefh adc_1 = presampling channel 0 ? vrefl adc_1 = presampling channel 1 9.4.6 programmable analog watchdog 9.4.6.1 introduction the analog watchdogs are used for determining whether the result of a channel conversion lies within a given guarded area (as shown in figure 9-48 ) specified by an upper and a lower threshold value named thrh and thrl respectively. figure 9-48. guarded area after the conversion of the selected channel, a comparison is perfor med between the converted value and the threshold values. if the converted value lies outside that guarded area then corresponding threshold violation interrupts are generated. the comparison resu lt is stored as wdgxh and wdgxl bits in the wtisr as explained in table 9-44 . depending on the mask bits ms kwdgxl and mskwdgxh in the wtimr, an interrupt is gene rated on threshold violation. note avoid the situation where thrh < thrl. in this case, a wdgxh or wdgxl interrupt will always be ge nerated, and this could lead to misinterpretation of the watchdog interrupts. table 9-44. values of wdgxh and wdgxl fields wdgxh wdgxl converted data 1 0 converted data > thrh 0 1 converted data < thrl 0 0 thrl ? converted data ? thrh thrh thrl analog voltage upper threshold lower threshold guarded area
analog-to-digital converter (adc) freescale semiconductor 9-43 pxs20 microcontroller reference manual, rev. 1 9.4.7 dma functionality a direct memory access (dma) request can be progr ammed after the conversion of every channel, by setting the respective masking bit in the dmar0 register. the dma masking registers must be programmed before st arting any conversion. the dma transfers can be enabled using the dmae[d maen] bit. when the dmae[dclr] bit is set, the dma request is cleared on the reading of the re gister for which dma transfer has been enabled. 9.4.8 interrupts the adc generates the followi ng maskable interrupt signals: ? eoc (end of conversion) interrupt request ? ech (end of chain) interrupt request ? jeoc (end of injected c onversion) interrupt request ? jech (end of injected chain) interrupt request ? wdgxl and wdgxh (watchdog threshold) interrupt requests ? ref_range (reference voltage comparison) interrupt request ? self test interrupts interrupts are generated during the conversion process to signal events such as end of conversion as explained in section 9.3.3.2, channel pending register 0 (ceocfr0) . two registers named ceocfr (channel pending registers) and imr (i nterrupt mask register) are provide d in order to check and enable the interrupt requests. interrupts can be individually en abled on a channel by channel base by programming the cimr (channel interrupt mask register). several channel interrupt pending registers are also provided in or der to signal which of the channels? measurement has been completed. the analog watchdog interrupts are managed by two registers: ? watchdog threshold interrupt status register (wtisr) ? watchdog threshold interrupt mask register (wtimr) the watchdog interrupt source sets two pending bits wdgxh and wdgxl in the wtisr for each of the four channels being monitored. the ceocfr contains the in terrupt pending request status . if the user wants to cl ear a particular interrupt event status, then writing a ?1? to th e corresponding status bit clears the pending interrupt flag (at this write operation all the other bits of the ce ocfr must be maintained at ?0?). end of conversion interrupts for self test channel is simi lar to normal conversion channel. same eoc and ech bits for normal conversion are set for self test channe l also. similar to other channels, self test channel has channel interrupt pending bit (s t_eoc) present in stsr1 and ch annel mask bit (mskst_eoc) in stcr2 (corresponding to bits for every channel in ceocfr and cimr register s). in addition, end of algorithm interrupts are also present whic h are handled by stsr1 and stcr2 registers.
analog-to-digital converter (adc) 9-44 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 error interrupts related to self te sting are handled by status bits in stsr1 and mask bits in stcr2 registers. if an error is generated due to analog watchdog monitoring or sequence checking of algorithm or internal watchdog timer timeout, corresponding error bi t is set in stsr1. the mask bits for these error bits are present in stcr2 register. 9.4.9 power-down mode the analog part of the adc can be put in a low- power mode, called ?power- down mode,? by setting the mcr[pwdn] bit. after releasing the reset signal th e adc analog module is kept in power-down mode by default, so this state must be exited before st arting any operation by clearing the appropriate bit in the mcr. the power-down mode can be request ed at any time by setting the mc r[pwdn] bit. if a conversion is ongoing, the adc hard macrocell cannot immediately enter the power-down mode. in fact, the adc enters power-down mode only afte r completing the ongoing conversion. otherwise, the ongoing operation should be aborted manually by clearing the ns tart bit and using the abortchain bit. bit adcstatus[0] in the msr is set on ly when adc enters power-down mode. after the power-down phase is completed, the proce ss that was occurring befo re the power-down phase must be restarted manually (by se tting the appropriate start bit). after an exit from power-down mode, the first conversion can be started after 5 ? s, otherwise the result can be affected by the improper setting of the adc analog operating point. caution you must not clear the mcr[pwdn] and set the mcr[nstart] or mcr[jstart] bits during the same cycle. see also section 9.3.12, power down exit delay register (pdedr). 9.4.10 auto-clock-off mode to reduce power consumption during the idle mode of operation (without going into power-down mode), an ?auto-clock-off? feature can be enabled by set ting the mcr[acko] bit. when enabled, the analog clock is automatically switched off when no opera tion is ongoing, that is, no conversion is programmed by the user. 9.4.11 self testing 9.4.11.1 general operation for safety devices used for very critic al applications, it is important to check at regular intervals if the adc is functioning correctly. for this purpose, self testing fe ature has been incorporated inside the adc. the self-tests use analog watchdogs to verify the resu lt of self-test conversions. the threshold of these watchdogs is saved in the test flash. before running the self test, you must copy thes e values from the test flash to the stawxr registers.
analog-to-digital converter (adc) freescale semiconductor 9-45 pxs20 microcontroller reference manual, rev. 1 three types of self testi ng algorithms have been implemented inside adc analog. ? supply self test: algorithm s. it includes th e conversion of the adc internal bandgap voltage, adc supply voltage, and adc refe rence voltage. it includes a se quence of 3 test conversions (steps). the supply test conversions must be an atomic operation (no functional conversions interleaved). ? resistive-capacitive self test: algorithm rc. it includes a sequence of 19 test conversions (steps) by setting the adc internal resistiv e digital-to-analog converter (dac). ? capacitive self test: algorithm c. it includes a sequence of 17 test convers ions (steps) by setting the capacitive elements comprising the sampling capacitor/ capacitive dac. the adc implements an additional te st channel dedicated for self test ing. it also provides signals to schedule self testing algorithms usi ng configuration registers, monitors the converted data using analog watchdog registers, flags the error to fccu in case some failure o ccurs in any of the algorithms. test channel can be activated in cpu or ctu mode as described in table 9-45 . 9.4.11.2 cpu mode in this case, test channel works similar to normal conversion. in cpu mode, test channel is enabled by setting stcr2[en]. the self testing channel conversions are carried along with the functi onal conversions. the sequencing of steps of the selected algorithm for test channel depends on the ope rating mode of nor mal conversions interleaved, selected by the mcr[mode] bit. in one shot mode, if test channel is enabled, only one step of selected self testing algorit hm is executed at the end of the chain. the step number and algorithm to be executed is progr ammed in stcr3 register. so, in one shot mode the se quence will be as follows: ? program ncmr0 to select channels to be converted for normal conversion. ? program mcr[mode] = 0 to select one shot mode. ? program sampling duration values in stcr1[inpsamp n ] field. ? select the self testing algorithm in stcr3.alg. default is algorithm s. ? enable self testing channel by sett ing en bit in the stcr2 register. ? start the normal conversion by setting nstart bit in the mcr. ? all normal conversions are executed as usual. ? at the end of all the normal conversions, step number programmed in stcr3.mstep field of self testing algorithm selected by stcr3.alg is executed similar to a normal functional channel. table 9-45. test channel activation adc mode test channel (adc) test channel (ctu) cpu mode (mcr[ctuen] = 0) yes (one shot mode and scan mode) no ctu trigger mode no yes ctu control mode no yes
analog-to-digital converter (adc) 9-46 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? on receiving end of conversion for test channel, the digital resu lt is written in stdr1.tcdata and stdr1.valid bit is set. als o, eoc and ech bits are set in th e isr and st_eoc bit is set in stsr1. ? state machine returns to idle state. example 9-3. channels a-b-c-d-e-f-g-h are present in the devi ce where channels b-d-e are to be converted in the one shot mode. mode=0 is set for one shot mode. the result is shown in figure 9-49 . conversion for channels b-d-e are done. after ch annel e test channel conversion is done and isr.ech and isr.eoc are set. figure 9-49. test channel conversion example the nstart status bit of msr is automatically set wh en the normal conversion st arts and is reset at the end of conversion for test channel. in scan mode, consecutive steps of selected self test algorithm are converted co ntinuously at the end of each chain of normal convers ions. the number of channels converted at the end of each chain is 1 (except for algorithm s, in which all the steps are pe rformed at once without any functional conversion interleaved). so, in scan mode the sequence will be as follows. ? program ncmr0 to select channels to be converted for normal conversion. ? program mode = 1 in the mcr to select scan mode. ? program sampling duration valu es in stcr1.inpsampx field. ? select the self testing algorithm in stcr3.alg. by default, all th ree algorithms are selected i.e. all algorithms will be executed step by step one after the other. ? enable self testing channel by se tting en bit in stcr2 register. ? start the normal conversion by setting mcr[nstart]. ? all normal conversions are executed as usual. ? at the end of chain of the normal conversions, (assuming default value of stcr3.alg) all steps of algorithm s are performed (as algorithm s is always atomic). msr.self_test_s is set. ? on receiving end of conversion of te st channel for last step of al gorithm s, the digital result is written in stdr1.tcdata and stdr1.valid bit is set. at the same time, msr.self_test_s is reset. for step 1, the integral part and fractional part are written in stdr2.idata and stdr2.fdata. also, eoc and ech bits are set in the isr and st_eoc is set in stsr2. ? then the next chain of normal conversion starts. ? at end of the normal conversion chain, step0 of rc algorithm is executed. ? on receiving end of conversion of test channel for st ep0 of rc algorithm, the digital result is stored in stdr1.tcdata and stdr1.valid bit is set (if mcr.overwr bit is set). also, eoc and ech bits are set in the isr and st_eoc is set (if ceocfr_exist =1) in stsr2. ? then the next chain of normal conversion starts. sample b convert b sample d sample e convert e sample test convert test convert d
analog-to-digital converter (adc) freescale semiconductor 9-47 pxs20 microcontroller reference manual, rev. 1 ? at end of the normal conversion chain, step1 of rc algorithm is executed. ? this process continues for all th e steps of all three algorithms. ? state machine returns to idle st ate when mcr[nstart] is cleared. instead of starting normal conversion by software (by setting mcr[nstart]), if it is started by external trigger, the test channel behaviour will remain same. in case of injected conversions, te st channel conversion is not perfor med. it is performed only during normal conversions. if during a test channel conversion, in jection conversion arrives, then the test channel is aborted (just as a normal functional channel) and inje cted conversions are done . after injected conve rsions are completed, the test channel resumes from the step at which it was aborted. in this case, the msr.self_test_s remains high during the injected conversion. for self testing, mode bi t should be programmed (atleast one cy cle ) before setting mcr.nstart bit and should not be changed therea fter until conversion is ongoing. 9.4.11.3 ctu mode the ctu mode is enabled by setting mcr[ctuen]. with this bit set, th e ctu operates in control mode. if ctuen is set, the test channe l conversion can be started only by ctu interface and software cannot start it. the en bit in stcr2 regi ster does not have any effect in ctu mode. the ctuen bit should not be changed while norma l conversion is ongoing. the interface between ctu and adc (for self test) is shown in figure 9-50 . figure 9-50. interface between adc and ctu to manage self test for self testing conversions in ctu mode, ctu asserts ct u_adc_st_en signal along with ctu_trigger. the algorithm and the step number to be executed is put on ctu_adc_st_alg and ct u_adc_st_step respectively. the other signals ctu_nextcmd, ct u_trigger and ctu_dataout have sa me meaning as for normal ctu functional conversion. ctu ctu_adc_st_step<4:0> ctu_adc_st_alg <1:0> ctu_trigger ctu_nextcmd ctu_dataout<9:0> ctu_adc_st_en adc
analog-to-digital converter (adc) 9-48 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 for algorithm s, the three steps must be atomic. in ctu mode, this is managed by ctu itself i.e. ctu has to send three triggers (one for ea ch step) asserting ctu_adc_st_en and updating ctu_adc_st_step for each step. channel cnversion command registers (clrx) in ctu allow to setup a self te st command, choosing also among the algorithms available. see table 9-46 and table 9-47 . the algorithm s must be executed as an atomic test without interlea ved user conversions. step 0: ? vbgap/vref test ? step1: vdd/vref test ? step2: vref/vref test ctu sends three triggers (one for each step) asserting ctu_adc_st_en and updating ctu_adc_st_step for each step. the rc and c algorithm can be executed, programming the clrx registers, in one of the following schemes: ? burst mode: when the ctu schedules the execution of the clrx register configured for the self testing, both the algorithms rc and c are executed in burst mode (step0-algrc, step1-algrc, ...stepn-algrc, step0-algc, step1-algc, ... stepm-algc). ? interleaved mode: when the ctu schedules the exec ution of the clrx regist er configured for the self testing, a single step of the algorithm rc or c is executed according to an internal counter. in this mode the adc self testing procedure is di stributed and the functio nal conversions are not stalled for a long time. table 9-46. ctu-clrx-st1, st0 meaning st1 bit st0 bit command meaning 0 0 no self test single conversion 0 1 self test command 1 0 no self test command dual conversion 1 1 no self test dual conversion table 9-47. ctu-clrx-alg1, alg0 meaning alg1 alg0 algorithm meaning 0 0 algorithm s 0 1 algorithm rc 1 1 algorithm c 1 1 algorithm full
analog-to-digital converter (adc) freescale semiconductor 9-49 pxs20 microcontroller reference manual, rev. 1 the burst mode and interleaved mode are not applicable to the s algorit hm that can be executed only as an atomic conversion. when the full algorithm is enabled the ctu will ex ecute an s algorithm followed by an rc algorithm and a c algorithm. the enabling of the trigger configured for the ad c self-testing can be performed according to the following schemes: ? triggered mode: according to the current ctu implementation ? sequential mode: according to the current ctu implementation 9.4.11.4 abort and abort chai n for self testing channel setting mcr[abort] during self test channel has no effect. in one shot mode, if mcr[abortchain] is set wh en test channel convers ion is ongoing, the test channel is aborted and ech is set. in this case, eoc for test channel is not generated. for zero baud rate in scan mode, if mcr[abortchain ] bit is set when test channel step n is ongoing, the test channel step n is aborte d and next chain conversion starts. at the end of this chain, step n conversion is performed again. (i n case of algorithm s, full algorithm is executed again). the case of non-zero baud rate is described in section 9.4.11.7.1, abort chain wh en baud rate is non-zero. 9.4.11.5 self test analog watchdog the adc also provides a monitor (watchdog) for the va lues returned by its analog portion for self test algorithms. the analog watchdogs are us ed to determine whether the resu lt of conversion for self test algorithms lie in a particular guard area. for this purpos e, seperate self test an alog watchdog registers have been provided for each algorithm. after the conversion of each step of an algorithm, a comparison is performed be tween the converted value and the threshold values if analog watchdog featur e is enabled by setting stawxr.awde bit. if the converted value does not li e between the upper and lower threshold values specified by analog watchdog register of the particular algor ithm, corresponding error bit stsr1.err _x is set and step number in which error occurred is updated in stsr1.step_x (in case of c or rc algorithm). also, erroneous data is written in stsr4.datax field. the stsr1.err_x bi ts will generate an interrupt if enabled by corresponding mask bit in stcr2 regi ster. the fault indicati on is also given to fc cu via cf and ncf, so that necessary action can be taken at soc level. analog watchdog feature works differ ently in case of algorithm s. as already mentione d, algorithm s is always an atomic operation. so, sepe rate error bits are pr ovided in stsr1 for each step of algorithm s to avoid overwrite in case error occu rs in more than one step. hence, there are seperate mask bit for each step in stcr1. for the same reason, seperate fields ex ist in status registers (s tsr2 and stsr3) to store erroneous data for each step. for algorithm s step1, a fixed point division has to be performed outside adc analog hardmacro (it takes around 26 cycles after eoc for step1 to get divided value) and it is the divided value on which analog watchdog checks are applied. so, the value to be compared for step1 contains integer as well as
analog-to-digital converter (adc) 9-50 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 fractional part and thus, two regi sters (staw1ar and staw1br) ar e provided. the comparison is done first for integer part using the threshold values program med in staw1ar. if integer part lies in the range, the fractional part comparison is skipped otherwise it is compared with th e values programmed in staw1br. table 9-48 summarizes this feature for step1. for algorithm s step2, (vref/vref) is measured in order to check the integrity of sampling signal. for this particular conversion, no highe r threshold value is required as th e ideal value is 0xfff. only lower threshold value is programmed in staw2r. for algorithm c, a separate register is provided for step0. in step0 an offset for other steps is measured. the converted data is compared with the threshol d values provided by staw5r if staw4r[awde] is set. for other steps, this offset is subtracted from converted data before performing watchdog checks. 9.4.11.6 watchdog timer the watchdog timer is an additional check which mon itors the sequence of the self testing algorithm implemented and also that the algo rithm is completed within a safe time period. the watchdog timers can be enabled for cpu as well ctu conversions. each algorithm has a di fferent watchdog timer which runs independently of the other. the watchdog timer for a particular algorithm ca n be enabled by setting staw n r[wdte] bit. the safe time value can be progr ammed in stbrr[wdt] field (default value is 10 ms assuming a 120 mhz clock). the safe time is measured starting from step0 of th e algorithm (including all nor mal chain conversions in between) to the point where step0 of the same algorithm starts again. the sequence is as follows: ? program ncmr0 to select channels to be converted for normal conversion in scan mode (mode = 1). ? select the self testing algorithm in stcr3.alg. by default, all th ree algorithms are selected i.e. all algorithms will be executed step by step one after the other. ? enable self testing channel by se tting en bit in stcr2 register. ? program safe period value in stbrr.wdt field. ? enable watchdog timer by setting stawxr.wdte bit. assume setting of wdte bit to be ?t0?. (it is important to do all the programming first and th en enable wdte bit as the safe time check is also performed between setting of wdte bit and start of step0 to check that algorithm has started within the safe time). ? start the normal conversion by setting mcr[nstart]. table 9-48. algorithm s (step1) threshold comparison stdr2[idata] (integer part) stdr2[fdata] (fractional part) stsr1[err_s1] > staw1ar[thrh] any value set < staw1ar[thrl] any value set == staw1ar[thrh] > staw1br[thrh] set == staw1ar[thrl] < staw1br[thrl] set
analog-to-digital converter (adc) freescale semiconductor 9-51 pxs20 microcontroller reference manual, rev. 1 ? after first chain conversion ends, step0 of algor ithm s is executed. assu me the start of step0 to be ?t1?. ? after this step1 and step2 of algorithm s are executed. ? then, next chain conve rsions are performed. ? when chain conversion completes, s tep0 of rc algorithm is performed. ? after each chain conversion, co nsecutive step of rc algorithm is performed. similar sequence follows for c algorithm. ? after the last step of c algorithm is performed, another chain conversion is executed. at the end of this chain conversion, step0 of algorithm s is started rep eating the whole sequence. lets assume this time (starti ng of step0) to be ?t2?. ? for s algorithm, if (t1 ? t0) > sa fe period or (t2 ? t1) > safe peri od, watchdog timer flags an error and stsr1.wdterr bit is set. crictical fault is asse rted and interrupt is al so generated if enabled by stcr2.mskwdterr bit. otherwis e, watchdog timer counter is reset and starts again to monitor the same for the next sequence. ? similar sequence is followed for wa tchdog timers for rc and c algorithms. as ctu does not incorporate any safe period checki ng mechanism, the watchdog timers can be enabled for ctu conversions also. note you must not enable the watchdog timer for the algorit hm which is not to be executed. 9.4.11.6.1 watch dog sequence checking the watchdog timer also incorporates sequence checki ng features which checks that the steps of a particular algorithm are in correct order. if steps are not in order, then error is flagged by setting stsr1[wdserr]. crictical fault is asserted a nd interrupt is also generated if enabled by stcr2[mskwdserr]. watchdog sequence error is fl agged in following cases: ? if steps of any algorithm are not executed in proper order. ? if abort chain occurs during test ch annel conversion, that step has to be repeated at the end of next chain. this will give a sequence error as s oon as test channel conversion starts again. exception : if abort chain oc curs during last step of alg-s, then sequence error is not flagged as the whole algorithm has to be repeated again. ? if, for ctu conversions, step numbers provi ded by ctu are not in order. watchdog sequence checking is significant for ctu burst mode only. if injected conversion occurs du ring the test channel, watchdog seque nce error is not flagged although the ongoing step number is abor ted and is repeated again. watchdog timer feature is applicable only for scan mode of operation and not for one shot mode.
analog-to-digital converter (adc) 9-52 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 9.4.11.7 baud rate control for test channel this control defines the scheduling of test channe l between the normal convers ions. the scheduling rate is specified by stbrr[br]. by default, if test channe l is enabled, one step of selected algorit hm is executed after every chain of normal conversion. the bandwidth consumed by test channel depends on the number of cha nnels in normal chain. e.g. if we have 100 normal conversions in a chain, then test channe l consumes only 1% of total bandwidth, which is very small. but in case the number decreases to just 4 channels, then the bandwidth consumed by test channel is 25%, which is sign ificant (and may not be desirable as it slows down the normal conversion rate). stbrr[br] field provides flexibility by scheduling the test channel convers ion to be performed not at the end of every chain but at the end of br+1 number of chains. e.g. if br = 5, a single step of selected algorithm for test channel is perfor med after 6 chain conversions, then ne xt step is performed at end of next 6 chain conversions and so on. by default, the value of br is 0. to use the baud rate feature in scan m ode, the ncmr should ha ve a non-zero value. note this feature is applicable only for s can mode of operation and not for one shot mode. the stbrr.br should be set to zero for one shot mode. 9.4.11.7.1 abort chain w hen baud rate is non-zero as already described, for non-zero value of stbrr[br ] field, the test channe l conversion is performed at the end of (br+1) number of chai ns. if abort chain occurs during th e chain in which test channel is scheduled to be converted, then test channel is converted after next (br+1) number of chains. for example, if stbrr.br field is programmed to 2, the sequence will be two normal chains (without any test channel conversion) followed by chain with te st channel converted at th e end. now, if abort chain occurs during first two chains it is treated as normal chain a bort and test channel is converted at the end of 3rd chain only (as the case without any abort chain). but if abort chain occurs during the 3rd chain in which test channel is scheduled to be converted, then test ch annel is converted after next three chains ? that is, at the end of 6th chain (counting from the beginning).
clock architecture freescale semiconductor 10-1 pxs20 microcontroller reference manual, rev. 1 chapter 10 clock architecture 10.1 clock generation the clock generation for this device is illustrated in figure 10-1 . figure 10-1. system clock generation 10.2 clock distribution table 10-1 describes the clock distribution on this chip. rc-oscillator (ircosc) oscillator (xosc) 4 mhz?16 mhz 40 mhz xosc_clk ircosc_clk mc_cgm aux clock selector 4 aux clock selector 3 fmpll_0 fmpll_1 phi_pcs phi phi fvco ? 6 fmpll_0_pcs_clk fmpll_0_clk fmpll_1d0_clk fmpll_1d1_clk mc_cgm aux clock selector 0 clock out selector aux clock selector 1 aux clock selector 2 system clock selector 0 cmu_0 cmu_1 cmu_2 legend: buffer clock gate mc_cgm ircosc_clk sor_part_0_clk sor_part_1_clk sys_clk peripheral set 0 clock system clock divider 0 ? 1, ? 2, ? 3, ... ? 16 ? 1, ? 2, ? 4, ? 8 ? 1, ? 2, ? 3, ... ? 16 ? 1, ? 2, ? 3, ... ? 16 ? 1, ? 2, ? 3, ... ? 16 ? 1, ? 2, ? 3, ... ? 16 clockout_divider clockout ? 30 mhz 50% motor control clock auxiliary clock 0 divider 0 swg clock auxiliary clock 0 divider 1 flexray clock auxiliary clock 1 divider 0 flexcan clock auxiliary clock 2 divider 0 xosc_clk 16 mhz
clock architecture 10-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 table 10-1. clock distribution module name clock frequency supports fm on pll adc_0 motor control ? 120 mhz yes adc_1 motor control ? 120 mhz yes bam system ? 120 mhz yes core_0 system ? 120 mhz yes core_1 system ? 120 mhz yes crc system ? 120 mhz yes ctu motor control ? 120 mhz yes dma_mux system ? 120 mhz yes dspi_0 peripheral set 0 ? 120 mhz yes dspi_1 peripheral set 0 ? 120 mhz yes dspi_2 peripheral set 0 ? 120 mhz yes ecsm_0 system ? 120 mhz yes ecsm_1 system ? 120 mhz yes edma_0 system ? 120 mhz yes edma_1 system ? 120 mhz yes etimer_0 motor control ? 120 mhz yes etimer_1 motor control ? 120 mhz yes etimer_2 motor control ? 120 mhz yes fccu (reg) system ? 120 mhz yes fccu (fsm) ircosc 16 mhz ? flash0 system ? 120 mhz yes flexcan_0 (biu and mbm) peripheral set 0 ? 120 mhz yes flexcan_0 (cpi) 1 flexcan ? 60 mhz yes xosc ? 40 mhz ? flexcan_1 (biu and mbm) peripheral set 0 ? 120 mhz yes flexcan_1 (cpi) 2 flexcan ? 60 mhz yes xosc ? 40 mhz ? flexpwm_0 motor control ? 120 mhz yes flexpwm_1 motor control ? 120 mhz yes flexray (chi) system ? 120 mhz yes flexray (pe) 3 flexray 80 mhz no xosc 40 mhz ? intc_0 system ? 120 mhz yes intc_1 system ? 120 mhz yes
clock architecture freescale semiconductor 10-3 pxs20 microcontroller reference manual, rev. 1 10.3 detailed module descriptions additional details on the clock-related modules on this device are provided in the following chapters: ? chapter 11, clock generation module (mc_cgm) ? chapter 12, clock monitor unit (cmu) linflexd_0 peripheral set 0 ? 120 mhz yes linflexd_1 peripheral set 0 ? 120 mhz yes mc_cgm system ? 120 mhz yes mc_me system ? 120 mhz yes mc_pcu system ? 120 mhz yes mc_rgm ircosc 16 mhz ? mpu_0 system ? 120 mhz yes mpu_1 system ? 120 mhz yes pbridge_0 system ? 120 mhz yes pbridge_1 system ? 120 mhz yes pit peripheral set 0 ? 120 mhz yes sema4_0 system ? 120 mhz yes sema4_1 system ? 120 mhz yes siul (registers) system ? 120 mhz yes siul (interrupt filters) ircosc 16 mhz ? sram system ? 120 mhz yes sscm system ? 120 mhz yes stcu system ? 120 mhz yes stm_0 system ? 120 mhz yes stm_1 system ? 120 mhz yes swg swg ? 20 mhz yes swt_0 ircosc 16 mhz ? swt_1 ircosc 16 mhz ? wkpu system ? 120 mhz yes xbar_0 system ? 120 mhz yes xbar_1 system ? 120 mhz yes notes: 1 selection between flexcan clock and xosc clock is done via the clk_src bit in the flexcan_0?s ctrl register. 2 selection between flexcan clock and xosc clock is done via the clk_src bit in the flexcan_1?s ctrl register. 3 selection between flexray clock and xosc clock is done via the clksel bit in the flexray?s fr_mcr register. table 10-1. clock distribution (continued) module name clock frequency supports fm on pll
clock architecture 10-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? chapter 27, frequency-modulated phase-locked loop (fmpll) ? chapter 35, oscillators
clock generation module (mc_cgm) freescale semiconductor 11-1 pxs20 microcontroller reference manual, rev. 1 chapter 11 clock generation module (mc_cgm) 11.1 introduction 11.1.1 overview the clock generation module (mc_cg m) generates reference clocks for all the soc blocks. the mc_cgm selects one of the system clock sources to supply the system clock. the mc_me controls the system clock selection (see chapter 32, mode entry module (mc_me) , for more details). a set of mc_cgm registers controls the cloc k dividers which are used for di vided system and peripheral clock generation. the memory spaces of sy stem and peripheral cl ock sources which have addressable memory spaces are accessed through the mc_cgm memory space . the mc_cgm also selects and generates an output clock. figure 11-1 depicts the mc_cgm block diagram.
clock generation module (mc_cgm) 11-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 11.1.2 features the mc_cgm includes th e following features: ? generates system and peripheral clocks ? selects and enables/disables the system clock supply from sy stem clock sources according to mc_me control output clock selector/divider registers platform interface core mc_cgm figure 11-1. mc_cgm block diagram mc_me system clock multiplexer/divider xosc pll0 pll1 ircosc mapped modules interface mapped peripherals peripherals port pin b[6] mc_rgm
clock generation module (mc_cgm) freescale semiconductor 11-3 pxs20 microcontroller reference manual, rev. 1 ? contains a set of registers to control cl ock dividers for divided clock generation ? supports multiple clock sources and maps their address spaces to its memory map ? generates an output clock ? guarantees glitch-less cloc k transitions when changing the system clock selection ? supports 8, 16 and 32-bit wi de read/write accesses 11.2 external signal description the mc_cgm delivers an output clock to the port pin b[6] for off-chip use and/or observation. 11.3 memory map and register definition note any access to unused registers as we ll as write accesses to read-only registers will: ? not change register content ? cause a transfer error table 11-1. mc_cgm register description address name description size access user superviso r test 0xc3fe_0370 cgm_oc_en output clock en able word read read/write read/write 0xc3fe_0374 cgm_ocds_s c output clock division select byte read read/write read/write 0xc3fe_0378 cgm_sc_ss system clock select status byte read read read 0xc3fe_037 c cgm_sc_dc0 system clock divider configuration 0 byte read read/write read/write 0xc3fe_0380 cgm_ac0_sc aux clock 0 select control word read read/write read/write 0xc3fe_0384 cgm_ac0_dc0 aux clock 0 divider co nfiguration 0 byte read read/write read/write 0xc3fe_0385 cgm_ac0_dc1 aux clock 0 divider co nfiguration 1 byte read read/write read/write 0xc3fe_0388 cgm_ac1_sc aux clock 1 select control word read read/write read/write 0xc3fe_038 c cgm_ac1_dc0 aux clock 1 divider config uration 0 byte read read/write read/write 0xc3fe_0390 cgm_ac2_sc aux clock 2 select control word read read/write read/write 0xc3fe_0394 cgm_ac2_dc0 aux clock 2 divider co nfiguration 0 byte read read/write read/write 0xc3fe_0398 cgm_ac3_sc aux clock 3 select control word read read/write read/write 0xc3fe_03a 0 cgm_ac4_sc aux clock 4 select control word read read/write read/write
clock generation module (mc_cgm) 11-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 table 11-2. mc_cgm memory map address name 01232756789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0xc3fe_0000 ? 0xc3fe_001c xosc registers 0xc3fe_0020 ? 0xc3fe_003c reserved 0xc3fe_0040 ? 0xc3fe_005c reserved 0xc3fe_0060 ? 0xc3fe_007c ircosc registers 0xc3fe_0080 ? 0xc3fe_009c reserved 0xc3fe_00a0 ? 0xc3fe_00bc pll0 registers 0xc3fe_00c0 ? 0xc3fe_00dc pll1 registers 0xc3fe_00e0 ? 0xc3fe_00fc reserved 0xc3fe_0100 ? 0xc3fe_011c cmu0 registers 0xc3fe_0120 ? 0xc3fe_013c cmu1 registers 0xc3fe_0140 ? 0xc3fe_015c cmu2 registers 0xc3fe_0160 ? 0xc3fe_017c reserved 0xc3fe_0180 ? 0xc3fe_019c reserved 0xc3fe_01a0 ? 0xc3fe_01bc reserved
clock generation module (mc_cgm) freescale semiconductor 11-5 pxs20 microcontroller reference manual, rev. 1 0xc3fe_01c0 ? 0xc3fe_01dc reserved 0xc3fe_01e0 ? 0xc3fe_01fc reserved 0xc3fe_0200 ? 0xc3fe_021c reserved 0xc3fe_0220 ? 0xc3fe_023c reserved 0xc3fe_0240 ? 0xc3fe_025c reserved 0xc3fe_0260 ? 0xc3fd_c27c reserved 0xc3fe_0280 ? 0xc3fe_029c reserved 0xc3fe_02a0 ? 0xc3fe_02bc reserved 0xc3fe_02c0 ? 0xc3fe_02dc reserved 0xc3fe_02e0 ? 0xc3fe_02fc reserved 0xc3fe_0300 ? 0xc3fe_031c reserved 0xc3fe_0320 ? 0xc3fe_033c reserved 0xc3fe_0340 ? 0xc3fe_035c reserved 0xc3fe_0360 ? 0xc3fe_036c reserved table 11-2. mc_cgm memory map (continued) address name 01232756789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
clock generation module (mc_cgm) 11-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 0xc3fe_0370 cgm_oc_en r 0000000000000000 w r000000000000000 en w 0xc3fe_0374 cgm_ocds_sc r 0 0 seldi v selctl 00000000 w r0000000000000000 w 0xc3fe_0378 cgm_sc_ss r 0000 selstat 00000000 w r0000000000000000 w 0xc3fe_037c cgm_sc_dc0 r de0 000 div0 00000000 w r0000000000000000 w 0xc3fe_0380 cgm_ac0_sc r 0000 selctl 00000000 w r0000000000000000 w 0xc3fe_0384 cgm_ac0_dc0? 1 r de0 000 div0 de1 000 div1 w r0000000000000000 w 0xc3fe_0388 cgm_ac1_sc r 0000 selctl 00000000 w r0000000000000000 w 0xc3fe_038c cgm_ac1_dc0 r de0 000 div0 00000000 w r0000000000000000 w table 11-2. mc_cgm memory map (continued) address name 01232756789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
clock generation module (mc_cgm) freescale semiconductor 11-7 pxs20 microcontroller reference manual, rev. 1 11.3.1 register descriptions all registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. the bytes are ordered according to big endian. for example, the cgm_oc_en register may be accessed as a word at address 0xc3fe_0370, as a half-word at address 0xc3fe_0372, or as a byte at address 0xc3fe_0373. 0xc3fe_0390 cgm_ac2_sc r 0000 selctl 00000000 w r0000000000000000 w 0xc3fe_0394 cgm_ac2_dc0 r de0 000 div0 00000000 w r0000000000000000 w 0xc3fe_0398 cgm_ac3_sc r 0000 selctl 00000000 w r0000000000000000 w 0xc3fe_03a0cgm_ac4_sc r0000 selctl 00000000 w r0000000000000000 w 0xc3fe_03a4 ? 0xc3fe_3ffc reserved table 11-2. mc_cgm memory map (continued) address name 01232756789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
clock generation module (mc_cgm) 11-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 11.3.1.1 output clock enable register (cgm_oc_en) this register is used to enab le and disable the output clock. 11.3.1.2 output clock division select register (cgm_ocds_sc) this register is used to select th e current output clock source and by which factor it is divi ded before being delivered at the output clock. address 0xc3fe_0370 access: user read, supervisor read/write, test read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000000000 en w reset0000000000000000 figure 11-2. output clock enable register (cgm_oc_en) table 11-3. output clock enable register (cgm_oc_en) field descriptions field description en output clock enable control 0 output clock is disabled 1 output clock is enabled address 0xc3fe_0374 access: user read-only, supervisor read/write, test read/write 01234567 r0 0 seldiv selctl w reset00000000 figure 11-3. output clock division select register (cgm_ocds_sc)
clock generation module (mc_cgm) freescale semiconductor 11-9 pxs20 microcontroller reference manual, rev. 1 11.3.1.3 system clock select status register (cgm_sc_ss) this register provides the curren t system clock source selection. table 11-4. output clock division select register (cgm_ocds_sc) field descriptions field description seldiv output clock division select 00 output selected output clock without division 01 output selected output clock divided by 2 10 output selected output clock divided by 4 11 output selected output clock divided by 8 selctl output clock source selection control ? this value selects the current source for the output clock. 0000 16 mhz int. rc osc. 0001 4-40 mhz crystal osc. 0010 system fmpll 0011 secondary (80 mhz) fmpll 0100 reserved 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved address 0xc3fe_0378 access: user read -only, supervisor read, test read 0123456789101112131415 r0000 selstat 00000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 11-4. system clock select status register (cgm_sc_ss)
clock generation module (mc_cgm) 11-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 11.3.1.4 system clock divider configuration registers (cgm_sc_dc0) this register controls the system clock dividers. table 11-5. system clock select status register (cgm_sc_ss) field descriptions field description selstat system clock source selection status ? this value indicates the current source for the system clock. 0000 16 mhz int. rc osc. 0001 reserved 0010 4?40 mhz crystal osc. 0011 reserved 0100 system fmpll 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 system clock is disabled address 0xc3fe_037c access: user read-only, supervisor read/write, test read/write 01234567 r de0 0 0 0 div0 w reset10000000 figure 11-5. system clock divider co nfiguration registers (cgm_sc_dc0) table 11-6. system clock divider configurat ion registers (cgm_sc_dc0) field descriptions field description de0 divider 0 enable 0 disable system clock divider 0 1 enable system clock divider 0 div0 divider 0 division value ? the resultant peripheral i/o clock will have a period div0 + 1 times that of the system clock. if the de0 is set to ?0? (divider 0 is disa bled), any write access to the div0 field is ignored and the peripheral i/o clock remains disabled.
clock generation module (mc_cgm) freescale semiconductor 11-11 pxs20 microcontroller reference manual, rev. 1 11.3.1.5 auxiliary clock 0 select control register (cgm_ac0_sc) this register is used to select the cu rrent clock source for the following clocks: ? undivided: (unused) ? divided by auxiliary clock 0 di vider 0: motor control clock ? divided by auxiliary clock 0 divide r 1: sine wave generator clock 11.3.1.6 auxiliary clock 0 divider configuration registers (cgm_ac0_dc0 ? 1) address 0xc3fe_0380 access: user read, supervisor read/write, test read/write 0123456789101112131415 r0000 selctl 00000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 11-6. auxiliary clock 0 select control register (cgm_ac0_sc) table 11-7. auxiliary clock 0 select control register (cgm_ac0_sc) field descriptions field description selctl auxiliary clock 0 source selection control ? this value selects the curren t source for auxiliary clock 0. 0000 16 mhz int. rc osc. 0001 reserved 0010 reserved 0011 reserved 0100 system fmpll 0101 secondary (120 mhz) fmpll 0110 reserved 0111 reserved 1000 secondary (80 mhz) fmpll 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved address0xc3fe_0384 access: user read, supervisor read/write, test read/write 01234567 r de0 000 div0 w reset10000000 figure 11-7. auxiliary clock 0 divider configuration register 0 (cgm_ac0_dc0)
clock generation module (mc_cgm) 11-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 these registers control the auxiliary clock 0 dividers. 11.3.1.7 auxiliary clock 1 select control register (cgm_ac1_sc) this register is used to select the cu rrent clock source for the following clocks: ? undivided: (unused) ? divided by auxiliary clock 1 divider 0: flexray clock address0xc3fe_0385 access: user read, supervisor read/write, test read/write 01234567 r de1 000 div1 w reset10000000 figure 11-8. auxiliary clock 0 divider configuration register 1 (cgm_ac0_dc1) table 11-8. auxiliary clock 0 divider configuration registers (cgm_ac0_dc0?1) field descriptions field description de0 divider 0 enable 0 disable auxiliary clock 0 divider 0 1 enable auxiliary clock 0 divider 0 div0 divider 0 division value ? the resultant motor control clock will have a period div0 + 1 times that of auxiliary clock 0. if the de0 is set to 0 (divider 0 is disabled), any write access to the div0 field is ignored and the motor control clock remains disabled. de1 divider 1 enable 0 disable auxiliary clock 0 divider 1 1 enable auxiliary clock 0 divider 1 div1 divider 1 division value ? the resultant sine wave generator clock will have a period div1 + 1 times that of auxiliary clock 0. if the de1 is set to 0 (divider 1 is disabled), any write access to the div1 field is ignored and the sine wave generator clock remains disabled. address 0xc3fe_0388 access: user read, supervisor read/write, test read/write 0123456789101112131415 r0000 selctl 00000000 w reset0000010000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 11-9. auxiliary clock 1 select control register (cgm_ac1_sc)
clock generation module (mc_cgm) freescale semiconductor 11-13 pxs20 microcontroller reference manual, rev. 1 11.3.1.8 auxiliary clock 1 divider configuration register (cgm_ac1_dc0) this register controls th e auxiliary clock 1 divider. table 11-9. auxiliary clock 1 select control register (cgm_ac1_sc) field descriptions field description selct l auxiliary clock 1 source selection control ? this value selects the current source for auxiliary clock 1. 0000 reserved 0001 reserved 0010 reserved 0011 reserved 0100 system fmpll 0101 secondary (120 mhz) fmpll 0110 reserved 0111 reserved 1000 secondary (80 mhz) fmpll 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved address0xc3fe_038c access: user read, supervisor read/write, test read/write 01234567 r de0 000 div0 w reset10000000 figure 11-10. auxiliary clock 1 divider configuration register (cgm_ac1_dc0) table 11-10. auxiliary clock 1 divider configuration register (cgm_ac1_dc0) field descriptions field description de0 divider 0 enable 0 disable auxiliary clock 1 divider 0 1 enable auxiliary clock 1 divider 0 div0 divider 0 division value ? the resultant flexray clock will have a period div0 + 1 times that of auxiliary clock 1. if the de0 is set to 0 (divider 0 is disabl ed), any write access to the div0 field is ignored and the flexray clock remains disabled.
clock generation module (mc_cgm) 11-14 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 11.3.1.9 auxiliary clock 2 select control register (cgm_ac2_sc) this register is used to select the cu rrent clock source for the following clocks: ? undivided: (unused) ? divided by auxiliary clock 2 divider 0: flexcan clock 11.3.1.10 auxiliary clock 2 divider configuration register (cgm_ac2_dc0) this register controls th e auxiliary clock 2 divider. address 0xc3fe_0390 access: user read, supervisor read/write, test read/write 0123456789101112131415 r0000 selctl 00000000 w reset0000010000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 11-11. auxiliary clock 2 select control register (cgm_ac2_sc) table 11-11. auxiliary clock 2 select control register (cgm_ac2_sc) field descriptions field description selctl auxiliary clock 2 sour ce selection control ? this value selects the curren t source for auxiliary clock 2. 0000 reserved 0001 reserved 0010 reserved 0011 reserved 0100 system fmpll 0101 secondary (120 mhz) fmpll 0110 reserved 0111 reserved 1000 secondary (80 mhz) fmpll 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved address0xc3fe_0394 access: user read, supervisor read/write, test read/write 01234567 r de0 000 div0 w reset10000000 figure 11-12. auxiliary clock 2 divider configuration register (cgm_ac2_dc0)
clock generation module (mc_cgm) freescale semiconductor 11-15 pxs20 microcontroller reference manual, rev. 1 11.3.1.11 auxiliary clock 3 select control register (cgm_ac3_sc) this register is used to select the cu rrent clock source for the following clocks: ? undivided: pll0 reference clock table 11-12. auxiliary clock 2 divider configuration register (cgm_ac2_dc0) field descriptions field description de0 divider 0 enable 0 disable auxiliary clock 2 divider 0 1 enable auxiliary clock 2 divider 0 div0 divider 0 division value ? the resultant flexcan clock will have a period div0 + 1 times that of auxiliary clock 2. if the de0 is set to 0 (divider 0 is disabled) , any write access to the div0 field is ignored and the flexcan clock remains disabled. address 0xc3fe_0390 access: user read, supervisor read/write, test read/write 0123456789101112131415 r0000 selctl 00000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 11-13. auxiliary clock 3 select control register (cgm_ac3_sc) table 11-13. auxiliary clock 3 select control register (cgm_ac3_sc) field descriptions field description selct l auxiliary clock 3 source selection control ? this value selects the curre nt source for auxiliary clock 3. 0000 16 mhz int. rc osc. 0001 4-40 mhz crystal osc. 0010 reserved 0011 reserved 0100 reserved 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved
clock generation module (mc_cgm) 11-16 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 11.3.1.12 auxiliary clock 4 select control register (cgm_ac4_sc) this register is used to select the curren t clock source for the fm pll1 reference clock. see figure 11-20 for details. 11.4 functional description 11.4.1 system clock generation figure 11-15 shows the block diagram of the system cl ock generation logic. the mc_me provides the system clock select and switch mask (see mc_me documentation for more de tails), and the mc_rgm provides the safe clock request (s ee mc_rgm documentation for more details). the safe clock request forces the selector to select the 16 mhz int. rc osc. as the system clock and to ignore the system clock select. address 0xc3fe_0390 access: user read, supervisor read/write, test read/write 0123456789101112131415 r0000 selctl 00000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 11-14. auxiliary clock 4 select control register (cgm_ac4_sc) table 11-14. auxiliary clock 4 select control register (cgm_ac4_sc) field descriptions field description selct l auxiliary clock 4 source selection control ? this value selects the current source for auxiliary clock 4. 0000 16 mhz int. rc osc. 0001 4-40 mhz crystal osc. 0010 reserved 0011 reserved 0100 reserved 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved
clock generation module (mc_cgm) freescale semiconductor 11-17 pxs20 microcontroller reference manual, rev. 1 11.4.1.1 system clock source selection during normal operation, the system clock selection is controlled ? on a safe mode or reset event, by the mc_rgm ? otherwise, by the mc_me 11.4.1.2 system clock disable during the test mode, the system clock can be disabled by the mc_me. 11.4.1.3 system clock dividers the mc_cgm generates the following de rived clock from the system clock: ? peripheral i/o clock - controlled by the cgm_sc_dc0 register 11.4.2 auxiliary clock generation figure 11-15 shows the block diagram of the a uxiliary clock generation logic. see section 11.3.1.5, auxiliary clock 0 select c ontrol register (cgm_ac0_sc) , section 11.3.1.7, auxiliary clock 1 select control register (cgm_ac1_sc) , section 11.3.1.9, auxiliary clock 2 select control register (cgm_ac2_sc) , section 11.3.1.11, auxiliary clock 3 sele ct control regist er (cgm_ac3_sc) , and figure 11-15. mc_cgm system clock generation overview system fmpll 4 system clock ?0? cgm_sc_ss register mc_rgm safe mode request me__mc.sysclk cgm_sc_dc0 register clock divider peripheral set 0 clock system clock is disabled if me__mc.sysclk = ?1111? ?0000? 1 0 16 mhz int. rc osc. 0
clock generation module (mc_cgm) 11-18 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 section 11.3.1.12, auxiliary clock 4 select control register (cgm_ac4_sc) for auxiliary clock selection control. cgm_ac0_dc0 register clock divider motor control clock (unused) figure 11-16. mc_cgm auxiliary clock 0 generation overview system fmpll 4 secondary (120 mhz) fmpll 5 secondary (80 mhz) fmpll 8 cgm_ac0_sc register cgm_ac0_dc1 register clock divider sine wave generator clock 16 mhz int. rc osc. 0
clock generation module (mc_cgm) freescale semiconductor 11-19 pxs20 microcontroller reference manual, rev. 1 cgm_ac1_dc0 register clock divider flexray clock (unused) figure 11-17. mc_cgm auxiliary clock 1 generation overview system fmpll 4 secondary (120 mhz) fmpll 5 secondary (80 mhz) fmpll 8 cgm_ac1_sc register cgm_ac2_dc0 register clock divider flexcan clock (unused) figure 11-18. mc_cgm auxiliary clock 2 generation overview system fmpll 4 secondary (120 mhz) fmpll 5 secondary (80 mhz) fmpll 8 cgm_ac2_sc register
clock generation module (mc_cgm) 11-20 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 pll0 reference clock figure 11-19. mc_cgm auxiliary clock 3 generation overview 4-40 mhz crystal osc. 1 cgm_ac3_sc register 16 mhz int. rc osc. 0 figure 11-20. mc_cgm auxiliary clock 4 generation overview 4-40 mhz crystal osc. 1 cgm_ac4_sc register 16 mhz int. rc osc. 0 fmpll1 reference clock
clock generation module (mc_cgm) freescale semiconductor 11-21 pxs20 microcontroller reference manual, rev. 1 11.4.2.1 auxiliary clock dividers the mc_cgm generates the following derived clocks: ? motor control clock - controlled by the cgm_ac0_dc0 register ? sine wave generator clock - controlled by the cgm_ac0_dc1 register ? flexray clock - controlled by the cgm_ac1_dc0 register ? flexcan clock - controlled by the cgm_ac2_dc0 register 11.4.3 functional description of dividers dividers are used for the generation of divided system and peripheral clocks. the mc_cgm has the following control register s for built-in dividers: ? section 11.3.1.4, system clock divider c onfiguration regist ers (cgm_sc_dc0) ? section 11.3.1.6, auxiliary clock 0 divider configuration registers (cgm_ac0_dc0?1) ? section 11.3.1.8, auxiliary clock 1 divider configuration register (cgm_ac1_dc0) ? section 11.3.1.10, auxiliary clock 2 divider configuration register (cgm_ac2_dc0) the reset value of all counters is ?1?. if a divider has its de bit in the respective configuration register set to ?0? (the divider is disabled), any value in its divn field is ignored. 11.4.4 output clock multiplexing the mc_cgm contains a mu ltiplexing function for a num ber of clock sources whic h can then be used as output clock sources. the selection is done via the cgm_ocds_sc register. 11.4.5 output clock division selection the mc_cgm provides the following output signals for the output clock generation: cgm_ocds_sc.selctl cgm_ocds_sc.seldiv 0 1 2 3 register register figure 11-21. mc_cgm output clock multiplexer and port pin b[6] generation 16 mhz int. rc osc. 0 4-40 mhz crystal osc. 1 system fmpll 2 secondary (80 mhz) fmpll 3 port pin b[6] ?0? cgm_oc_en register
clock generation module (mc_cgm) 11-22 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? port pin b[6] (see figure 11-21 ). this signal is gene rated by using one of th e 3-stage ripple counter outputs or the selected signal wi thout division. the non-divided signa l is not guaranteed to be 50% duty cycle by the mc_cgm. the mc_cgm also has an output clock enable register (see section 11.3.1.1, output clock enable register (cgm_oc_en) ) which contains the output cloc k enable/disable control bit.
clock monitor unit (cmu) freescale semiconductor 12-1 pxs20 microcontroller reference manual, rev. 1 chapter 12 clock monitor unit (cmu) 12.1 overview the clock monitor unit (c mu) serves three purposes: ? selected clock monitoring: det ect if the monitored clock leav es an upper or lower frequency boundary ? xosc clock monitoring: monitor the xosc clock, which must be greater than the ircosc clock divided by a division factor given by cmu_csr[rcdiv] ? frequency meter: measure the frequency of the ircosc clock versus the reference xosc clock frequency when a failure is detected in one of the cmus, by either the selected clock monitor or the xosc monitor, the cmu notifies the mc_rgm, the mc _me, and the fccu modules. the de fault behavior is such that a reset occurs and a status bit is set in the mc_rgm. the user also has the optio n to change the behavior of the action by disabling the reset and selecting an alternate action. th e alternate action can be either entering safe mode or generating an interrupt. 12.2 main features ? ircosc frequency measurement ? xosc clock monitoring with respect to (ircosc clock) ? n ? selected clock frequency monitori ng with respect to (ircosc clock) ? 4 ? event generation for various failur es detected insi de monitoring unit 12.3 memory map and register description the cmu registers are mapped through th e mc_cgm (see the memory map in chapter 11, clock generation module (mc_cgm) ). the base address for each cmu is shown in table 12-2 . table 12-1. cmu module summary module monitored clocks cmu_0 system clock xosc cmu_1 motor control clock cmu_2 flexray clock table 12-2. cmu base addresses module base address cmu_0 0xc3fe_0100 cmu_1 0xc3fe_0120 cmu_2 0xc3fe_0140
clock monitor unit (cmu) 12-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 the memory map of each cmu is shown in table 12-3 . 12.3.1 control status register (cmu_csr) table 12-3. cmu memory map address offset register location 0x00 control status register (cmu_csr) on page 12-2 0x04 frequency display register (cmu_fdisp) on page 12-3 0x08 high-frequency reference register a (cmu_hfrefr_a) on page 12-4 0x0c low-frequency reference register a (cmu_lfrefr_a) on page 12-4 0x10 interrupt status register (cmu_isr) on page 12-5 0x14 reserved 0x18 measurement duration register (cmu_mdr) on page 12-6 address: base + 0x00 access: user read/write 0123456789101112131415 r0000000 0 sfm 000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000 cksel1 00000 rcdiv cme _a w reset00000000 00000110 figure 12-1. control status register (cmu_csr) table 12-4. cmu_csr field descriptions field description sfm start frequency measure set this bit to start a clock frequency measure. th e bit is cleared by hardware when the measure is ready in the cmu_fdr register. software cannot clear this bit. 0 frequency measurement is completed or not yet started. 1 frequency measurement is not completed. cksel1 clock selection this fieldselects the clock to be measured by the frequency meter. for cut1 : 00 ircosc_clk is selected. 01 ircosc_clk is selected. 10 no clock is selected. 11 ircosc_clk is selected. for cut2/3: 00 ircosc_clk is selected. 01 ircosc_clk is selected. 10 ircosc_clk is selected. 11 ircosc_clk is selected.
clock monitor unit (cmu) freescale semiconductor 12-3 pxs20 microcontroller reference manual, rev. 1 12.3.2 frequency display register (cmu_fdr) rcdiv ircosc clock division factor these bits specify the ircosc clock division factor . the output clock is ircosc_clk divided by the factor 2 rcdiv . this output clock is compared with xosc_clk for crystal clock monitor feature.the clock division coding is as follows. 00 clock divided by 1 (no division). 01 clock divided by 2. 10 clock divided by 4. 11 clock divided by 8. cme_a clock monitor enable 0 monitor is disabled. 1 monitor is enabled. address: base + 0x04 access: user read-only 0123456789101112131415 r0000000 0 0000 fd[19:16] w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rfd[15:0] w reset00000000 00000000 figure 12-2. frequency display register (cmu_fdr) table 12-5. cmu_fdr field descriptions field description fd measured frequency bits this register displays the measured frequency f ircosc_clk with respect to f xosc_clk . the measured value is given by the following formula: f ircosc_clk = (f xosc_clk md) / n where n is the value in cmu_fdr register table 12-4. cmu_csr field descriptions (continued)
clock monitor unit (cmu) 12-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 12.3.3 high-frequency reference register a (cmu_hfrefr_a) 12.3.4 low-frequency referenc e register a (cmu_lfrefr_a) address: base + 0x08 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000 hfref_a w reset00001111 11111111 figure 12-3. high-frequency refere nce register a (cmu_hfrefr_a) table 12-6. cmu_hfrefr _a field descriptions field description hfref_a high-frequency reference value these bits determine the high reference value for the fmpll clock. the reference value is given by: (hfref_a ? 16) (f ircosc_clk ? 4). address: base + 0x0c access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000 lfref_a w reset00000000 00000000 figure 12-4. low-frequency reference register a (cmu_lfrefr_a) table 12-7. cmu_lfrefr_a fields descriptions field description lfref_a low-frequency reference value these bits determine the low reference value for t he fmpll clock. the reference value is given by: (lfref_a ? 16) (f ircosc_clk ? 4).
clock monitor unit (cmu) freescale semiconductor 12-5 pxs20 microcontroller reference manual, rev. 1 12.3.5 interrupt status register (cmu_isr) address: base + 0x10 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000 0 0000 flci_a fhhi_a flli_a olri w w1c w1c w1c w1c reset00000000 00000000 figure 12-5. interrupt status register (cmu_isr) table 12-8. cmu_isr field descriptions field description flci_a monitored clock frequency less than reference clock interrupt this bit is set by hardware when both of the following are true: ? the monitored clock frequency becomes lower than reference clock frequency (f ircosc_clk ? 4) value ? the selected clock source is 'on' (and lo cked in the case of fmpll_0 and fmpll_1). it can be cleared by software by writing 1. 0 no flc event. 1 flc event is pending. fhhi_a monitored clock frequency higher than high reference interrupt this bit is set by hardware when both of the following are true: ? the monitored frequency becomes higher than hfref_a value ? the selected clock source is 'on' (and lo cked in the case of fmpll_0 and fmpll_1). it can be cleared by software by writing 1. 0 no fhh event. 1 fhh event is pending. flli_a monitored clock frequency less than low reference event this bit is set by hardware when both of the following are true: ? the monitored clock frequency becomes lower than lfref_a value ? the selected clock source is 'on' (and lo cked in the case of fmpll_0 and fmpll_1). it can be cleared by software by writing 1. 0 no fll event. 1 fll event is pending. olri xosc clock frequency less than ircosc clock frequency event this bit is set by hardware when both of the following are true: ? the frequency of xosc_clk is less than ircosc_clk/2 rcdiv frequency ? xosc_clk is ?on? and stable as signaled by the mc_me. it can be cleared by software by writing 1. 0 no olr event. 1 olr event is pending.
clock monitor unit (cmu) 12-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 12.3.6 measurement duration register (cmu_mdr) 12.4 functional description the names of the clocks involved in th is block have the following meaning: ? xosc_clk: clock coming from the xosc ? ircosc_clk: clock coming from the ircosc ? ck_pll: clock coming from the fmpll ?f xosc_clk : frequency of external crystal oscillator clock ?f ircosc_clk : frequency of low frequency internal rc oscillator ? fpll: frequency of fmpll clock 12.4.1 xosc clock monitor the xosc clock is monitored by cmu_0. if f xosc_clk is smaller than f ircosc_clk divided by 2 cmu_csr[rcdiv] and the xosc is ?on? and stable as signaled by the mc_me, then: ? cmu_isr[olri] is set. ? a failure event olr is signaled to the mc_r gm and fccu, which in turn can generate a ?functional' reset, a safe mode request, or an interrupt. note the xosc monitor may produc e a false event when f xosc_clk is less than 2 ? f ircosc_clk ? 2 cmu_csr[rcdiv] due to an accuracy limitation of the compare circuitry. address: base + 0x18 access: user read/write 0123456789101112131415 r0000000 0 0000 md[19:16] w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r md[15:0] w reset00000000 00000000 figure 12-6. measurement duration register (cmu_mdr) table 12-9. cmu_mdr field descriptions field description md measurement duration bits this register displays the measured duration in terms of ircosc clock cycles. this value is loaded in the frequency meter down-counter. when cmu_csr[ sfm] = 1, the down-counter starts counting.
clock monitor unit (cmu) freescale semiconductor 12-7 pxs20 microcontroller reference manual, rev. 1 12.4.1.1 system clock monitor the system clock is monitored by cmu_0. the f sys_clk frequency can be m onitored by programming cmu_csr[cme] = 1. sys_clk monitoring starts as soon as cmu_csr[cme] = 1. this monitor can be disabled at any time by writing cme bit to 0. if f sys_clk is greater than a reference value determ ined by the cmu_hfrefr_a[hfref_a] bits and the system clock is enabled, then: ? cmu_isr[fhhi] is set ? a failure event is signaled to the mc_rgm and fccu, which in turn can generate a ?functional' reset, a safe mode request, or an interrupt if f sys_clk is less than a reference clock frequency (f ircosc_clk ? 4) and the system clock is enabled, then: ? cmu_isr[flci] is set ? a failure event flc is signaled to the mc_rgm and fault collection unit, which in turn can generate a ?functional' reset, a sa fe mode request, or an interrupt if f sys_clk is less than a reference value determined by the cmu_lfrefr_a[lfref_a] bits and the system clock is enabled, then: ? cmu_isr[flli] is set ? a failure event is signaled to the mc_rgm and fccu, which in tu rn can generate a ?functional? reset, a safe mode request, or an interrupt note the system clock monitor may produce a false event when f sys_clk is less than 2 ? f ircosc_clk /2 cmu_csr[rcdiv] due to an accuracy limitation of the compare circuitry. 12.4.1.2 motor control clock monitor the motor control clock is monitored by cmu_1. f motc_clk can be monitored by programming cmu_csr[cme] = 1. motc_clk monitoring starts as soon as cmu_csr[cme] = 1. this monitor can be disabled at any time by programming cmu_csr[cme] = 0. if f motc_clk is greater than a reference value determ ined by the cmu_hfrefr_a[hfref_a] and the currently selected motor control cl ock source is ?on? (and locked in the case of fmpll_0 or fmpll_1), then: ? cmu_isr[fhhi] is set. ? a failure event is signaled to the mc_rgm and fccu, which in tu rn can generate a ?functional? reset, a safe mode request, or an interrupt. if f motc_clk is less than a reference clock frequency (f ircosc_clk ? 4) and the currently selected motor control clock source is ?on? (and locked in the case of fmpll_0 or fmpll_1), then: ? event pending bit cmu_isr[flci] is set.
clock monitor unit (cmu) 12-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? a failure event flc is signaled to the mc_r gm and fccu, which in turn can generate a ?functional? reset, a safe m ode request, or an interrupt. if f motc_clk is less than a reference value determined by the cmu_lfrefr_a[l fref_a] bits and the currently selected motor control cl ock source is ?on? (and locked in the case of fmpll_0 or fmpll_1), then: ? cmu_isr[flli] is set. ? a failure event is signaled to the mc_rgm and fccu, which in tu rn can generate a ?functional? reset, a safe mode request, or an interrupt. note the motor control clock monitor may produce a false event when f motc_clk is less than 2 ? f ircosc_clk ? 2 cmu_csr[rcdiv] due to an accuracy limitation of the compare circuitry. 12.4.1.3 flexray clock monitor the flexray clock is monitored by cmu_2. f fr_clk can be monitored by programming cmu_csr[cme] = 1. fr_clk monitoring starts as soon as cmu_csr[cme] = 1. this monitor can be disabled at any time by programming cmu_csr[cme] = 0. if f fr_clk is greater than a reference value determ ined by the cmu_hfrefr_a[hfref_a] bits and the currently selected motor control clock source is ?on? and locked, then ? cmu_isr[fhhi] is set. ? failure event is signaled to the mc_rgm and fc cu, which in turn can generate a ?functional? reset, a safe mode request, or an interrupt. if f fr_clk is less than a reference clock frequency (f ircosc_clk ? 4) and the currently selected motor control clock source is ?on? and locked, then: ? cmu_isr[flci] is set. ? a failure event flc is signaled to the mc_r gm and fccu, which in turn can generate a ?functional? reset, a safe m ode request, or an interrupt. if f fr_clk is less than a reference value determined by the cmu_lfrefr_a[l fref_a] bits and the currently selected motor control cl ock source is ?on? locked, then: ? cmu_isr[flli] is set. ? a failure event is signaled to the mc_rgm and fccu, which in tu rn can generate a ?functional? reset, a safe mode request, or an interrupt. note the flexray clock monitor may produce a false event when f fr_clk is less than 2 ? f ircosc_clk ? 2 cmu_csr[rcdiv] due to an accuracy limitation of the compare circuitry.
clock monitor unit (cmu) freescale semiconductor 12-9 pxs20 microcontroller reference manual, rev. 1 12.4.1.4 frequency meter the frequency meter, which is part of cmu _0, calibrates the ircosc using a known frequency. note this value can then be stored in th e flash memory so that application software can reuse it later on. the reference clock is always the xosc. a simp le frequency meter returns a draft value of ircosc_clk. the measurement star ts when cmu_csr[sfm] is set. the measurement duration is given by the cmu_mdr register in terms of ircosc_clk cy cles with a width of 20 bits. the sfm bit is cleared by the hardware after the frequency meas urement is done and the c ount is loaded in the cmu_fdr. f ircosc_clk can be derived from the value loaded in the cmu_fdr register as follows: f ircosc_clk = (f xosc_clk md) ? n eqn. 12-1 where n is the value in cmu_fdr register and md is the value in cmu_mdr.
clock monitor unit (cmu) 12-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1
cross-triggering unit (ctu) freescale semiconductor 13-1 pxs20 microcontroller reference manual, rev. 1 chapter 13 cross-triggering unit (ctu) 13.1 introduction in pwm driven systems it is important to schedule th e acquisition of the state variables with respect to pwm cycle. state variables are obtained through the following peripherals: ad c, position counter (e.g. quadrature decoder, resolver and sine-c os sensor) and pwm duty cycle decoder. the cross triggering unit (ctu ) is intended to completely avoid cpu involvement in the time acquisitions of state variables during the control cycle that can be the pwm cycle, the half pwm cycle or a number of pwm cycles. in such case the pre-setting of the acquisition times needs to be completed during the previous control cycle, where the actual acquisitions are to be made , and a double-buffered structure for the ctu registers is used, in order to activate the new settings at the beginning of the next control cycle. in addition, there are 4 fifo s inside the ctu available to store the adc results. 13.2 block diagram figure 13-1. cross triggering unit block diagram 13.3 ctu overview the ctu receives various incoming signals from diff erent sources (pwm, timers, position decoder and/or external pins). these signals are then processed to ge nerate up to eight trigger events. an input can be a rising edge, a falling edge or both, edges of each incoming signal. the out put can be a puls e or a command (or a stream of consecutiv e commands for over-sampling support) or both, to one or more peripherals (e.g. adc, timers and so on). ctu clock (as pwm) trigger_0 etimer0_trg adc_cmd_0 fifo_0 trigger_1 fifo_1 next_cmd_0 next_cmd_1 adc_cmd_1 etimer1_trg ext_trg ext_in etimer1_in etimer0_in pwm_rel pwm_odd_ x pwm_even_ x rpwm_ x mrs prescaler trigger generator subunit scheduler subunit
cross-triggering unit (ctu) 13-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 the ctu interfaces to the following peripherals: (1) pwm (13 inputs); (2) timers (2 inputs); (3) gpio, i.e. an external signal (1 input). th e 16 input signals are digi tal signals and the ctu mu st be able to detect a rising and/or a falling edge for each of them. the ctu comprises the: ? input signals interface ? user interface (configurat ion registers and so on) ? adc interface ? timers interface the block diagram of the ctu is shown in figure 13-1 . the ctu consists of two subunits: ? trigger generator subunit ? scheduler subunit the trigger generator subunit handles incoming signals, selecting for each signal, the active edges to generate the master reload signal, and generates up to eight trigger even ts (signals). the scheduler subunit generates the trigger event output according to the occurred trigger event (signal). 13.4 functional description 13.4.1 interaction with other peripherals figure 13-2 shows how the ctu interacts with the following peripherals: ? adc ? dspi ?etimer ?flexpwm ?flexray
cross-triggering unit (ctu) freescale semiconductor 13-3 pxs20 microcontroller reference manual, rev. 1 figure 13-2. ctu interaction with other peripherals 13.4.2 trigger events features the tgs has the capability to generate up to eight trigger events. each trigger event has the following characteristics: ? the generation of the trigger event is sequential in time. ? the triggers list uses eight 16-bit double-buffered registers. ? on each master reload signal (mrs), the new triggers list is loaded. ? the triggers list is reloaded on a mrs occu rrence, only if the reload enable bit is set. 13.4.3 trigger generator subunit (tgs) the trigger generator subunit has the following two modes: ? triggered mode : each event source for the incoming signals can generate up to eight trigger event outputs. for the adc, a commands li st is entered by the cpu, and e ach event source can generate up to eight commands or streams of commands. flexpwm_1 pwma0 flexpwm_0 adc0 adc1 dspi1 pwmb0 pwma1 pwmb1 pwma2 pwmb2 pwma3 pwmb3 fault0 fault1 fault2 fault3 ext_sync master reload out_trig0_0 out_trig0_1 out_trig0_2 out_trig0_3 out_trig1_0 out_trig1_1 out_trig1_2 out_trig1_3 pwmx0 pwmx1 pwmx2 pwmx3 ext_force clock pwma0 pwmb0 pwma1 pwmb1 pwma2 pwmb2 pwma3 pwmb3 fault0 fault1 fault2 fault3 ext_sync master reload out_trig0_0 out_trig0_1 out_trig0_2 out_trig0_3 out_trig1_0 out_trig1_1 out_trig1_2 out_trig1_3 pwmx0 pwmx1 pwmx2 pwmx3 ext_force clock external pins external pins sck ca_tx flexray external pins external pins external pins external pins external pins external pins etimer0 etimer1 etimer2 aux_0 aux_1 aux_2 aux_0 aux_1 aux_2 aux_0 aux_1 aux_2 t0 t1 t2 t3 t4 t5 t0 t1 t2 t3 t4 t5 t0 t1 t2 t3 t4 t5 pwm_rel pwm_odd_0 pwm_odd_1 pwm_odd_2 pwm_odd_3 pwm_even_0 pwm_even_1 pwm_even_2 pwm_even_3 rpwm_0 rpwm_1 rpwm_2 rpwm_3 etimer0_trg etimer1_trg etimer2_trg etimer3_trg trigger_0 adc_cmd_0 next_cmd_0 fifo_0 trigger_0 adc_cmd_0 next_cmd_0 fifo_0 ext_in ext_trg etmr0_in etmr1_in ctu
cross-triggering unit (ctu) 13-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? sequential mode : each event source for the incoming signals can generate one trigger event output, the next event source generates the next trigger event output, and so on in a predefined sequence. for the adc, a commands list is ente red by the cpu and the se quence of the selected incoming trigger events generate co mmands or stream of commands. the tgs mode is selected using the tg s_m bit in the tgs control register. 13.4.4 tgs in triggered mode the structure of the tgs in triggered mode is shown in figure 13-3 . figure 13-3. tgs in triggered mode the tgs has 16 input signals, each of which is selected from the i nput selection register (tgsisr), selecting the states inacti ve, rising, falling or both. depending on th e selection, up to 32 input events can be enabled. these signals are or-ed in order to gene rate the mrs. the mrs, at the beginning of the control cycle "n? (defined by the mrs occurrence), is used to pre-load the tgs counter register, using the pre-load value written into the doubl e-buffered register (tgs crr), during the control cycle "n-1?, and to reload all the double-buffered registers (trigger co mpare registers, tgscr, tgscrr itself etc). the triggers list registers, consist of 8 compare registers. each triggers list register is associated with a comparator. on reload (mrs occurrence), the compar ators are disabled: 1 tgs clock cycle is necessary to enable them and to start the counting. the mrs is output together with individual tr igger signals. the mrs can be performed by hardware or by software. the mrs_sg bit in the ctu control register, if set to 1, generates equivalent software mrs (i.e. resets/reloads tgs c ounter and reloads all double-buffered registers). this bit is cleared by each hardware or software mrs occurrence. the tgs counter compare register and the tgs coun ter comparator, are used to stop the tgs counter when it reaches the value stored in the tgs c ounter compare register, before an mrs occurs. ctu clock (as pwm) ext_in etimer1_in etimer0_in pwm_rel pwm_odd_ x pwm_even_ x rpwm_ x individual inputs selection (rising/falling edges) or master reload signal (mrs) triggers compare registers (double-buffered) comparators tgs counter compare register tgs counter comparator tgs counter stop signal tgs counter tgs counter reload register prescaler (1, 2, 3, 4) input selection 32-bit register
cross-triggering unit (ctu) freescale semiconductor 13-5 pxs20 microcontroller reference manual, rev. 1 the prescaler for tgs and su can be 1,2,3,4 (p res bits in the tgs control register). an example timing for the tgs in triggered mode is shown in figure 13-4 . the red arrows indicate the mrs occurrences, while the black arrows indicate the trigger event occurrences, with the relevant delay in respect to the last mrs occurrence. figure 13-4. example timing for tgs in triggered mode 13.4.5 tgs in sequential mode the structure of the tgs in sequential mode is shown in figure 13-5 . the 32 input events (16 signals with 2 edges for signal), which can be individually enabled, are or-ed in order to generate the event signal (es) . the es is used to enable the relo ad of the tgs count er register and to pilot the 3-bits counter, in order to select the ne xt active trigger. one of the 32 input events can be selected, through the mrs_sm (master reload sele ction sequential mode) 5-bi ts in the tgs control register, to be the mrs, that enable s the reload of the triggers list a nd resets the 3-bits counter (incoming events counter), i.e. the mrs is the signal linked with the control cycle defined as the time window between two consecutive mrss. in this mode, each incoming event sequentially enables only one trigger event through the 3-bits c ounter and the mux. the m ux is a selection switch which enables, according to the number of event signals occurred, only one of the eight trigger signals to the scheduler subunit. sequences of up to eight trigger events can be supported within this control cycle. for the other features see the previous paragraphs. delay t 0 delay t 1 delay t 2 delay t 2
cross-triggering unit (ctu) 13-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 13-5. tgs in sequential mode an example timing diagra m for tgs in sequential mode is shown in figure 13-6 . the red arrows indicate the mrs occurrences and es occurrences, while the black arrows indicate the trigger event occurrences with the relevant delay in respect to the es occurrence. the first red arrow indicates the first es occurrence which is also the mrs. figure 13-6. example timing for tgs in sequential mode 13.4.6 tgs counter the tgs counter is able to count from nega tive to positive, i.e. from 0x8000 to 0x7fff. figure 13-7 shows examples in order to explain the tgs counter count s. the compare operation to stop the tgs counter is not enabled during the first counting cy cle, in order to allow the countin g, if the value of the tgscrr is the same as the value of the tgsccr. ctu clock (as pwm) ext_in etimer1_in etimer0_in pwm_rel pwm_odd_ x pwm_even_ x rpwm_ x individual inputs selection (rising/falling/both edges) master reload master reload signal (mrs) triggers compare registers (double-buffered) comparators tgs counter compare register tgs counter comparator tgs counter stop signal tgs counter tgs counter reload register prescaler (1, 2, 3, 4) input selection 32-bit register master reload selection (5 bits in tgs control register) or selection mux event signal 3-bit counter clock (es) reset (mrs) delay t 0 delay t 2 delay t 3 delay t 1
cross-triggering unit (ctu) freescale semiconductor 13-7 pxs20 microcontroller reference manual, rev. 1 figure 13-7. tgs counter cases 13.5 scheduler subunit (su) the structure of the su is shown in figure 13-8 . the su generates the trigger event output according to th e occurred trigger event, and it has the same functionality in both tgs modes (t riggered mode and sequential mode ). each of the 4 su outputs: 1. adc command or adc st ream of commands, 2. etimer1 pulse, 3. etimer2 pulse and 4. external trigger pulse) can be linked to any of 8 trigger events by the tri gger handler block. each tri gger event can be linked to one or more su outputs. if two events at the same time are linked to the sa me output only one output is generated and an error is provided. the output is gene rated using the trigger with the lowest index. for example if trigger 0 and trigger 1 are linked to the adc output and they occur together, an error is generated and the output linked with the trigger 0 is generated. when a trigger is linked to the adc, an associated adc command (or st ream of commands) is generated. the adc commands list control re gister clcrx sets the assignmen t to an adc command or to a value in tgsccr tgs counter tgs counter?case 2 tgs counter?case 3 tgs counter?case 4 tgs counter?case 1 value in tgscrr mrs value in tgscrr mrs value in tgscrr mrs value in tgscrr mrs tgs counter tgs counter value in tgsccr tgs counter value in tgsccr 0x7fff 0x8000 tgs counter is stopped value in tgsccr
cross-triggering unit (ctu) 13-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 stream of commands. when a trigger is linked to a timer or to the external trigger, a pulse with an active rising edge is generated. additional features for the external triggers are available: the external trigger output has: ? pulse mode ? toggle mode. in toggle mode, each trigger event is linked to the external trigger, th e external trigger pin toggles. the on-time for both modes (pulse mode and toggle mode) of the triggers is define d from a cotr register (control on time register). a guard time is also defined from the same register at the sa me value of the on-time. a new trigger will be generated only if th e on time + guard time ha s past. the on-time and the guard time are only used for external triggers. external signals can be asynchronous with motor c ontrol clock. for this reas on a programmable digital filter is available. the external signa l is considered at 1 if it is latche d n time at 1, and is considered at 0 if it is latched n time at 0, where n is a value in the di gital filter control register. trigger events in the su can be initiated by hardwa re or by software, and an additional software control is possible for each trigger event (as for the mrs), so 1 bit for each trigger event in the ctu control register is used to generate an e quivalent software trigger event. each of these bits will be cleared by a respective hardware or software trigger event. figure 13-8. scheduler subunit ctu clock trigger_0 etimer0_trg prescaler adc commands list registers (double-buffered) adc commands list control registers (double-buffered) adc command generator trigger handler (1, 2, 3, 4) subunit clock subunit clock tr i g g e r 0 . . 7 mrs et1 trigger generator et2 trigger generator ext. trigger generator fifos subunit clock tr i g g e r 0..7 etimer1_trg ext_trg fifo_0 fifo_1 trigger_1 adc_cmd_1 adc_cmd_0 next_cmd_1 next_cmd_0 ready ready trigger handler control register (double-buffered) ready ready etimer2_trg et3 trigger generator et4 trigger generator etimer3_trg ready ready
cross-triggering unit (ctu) freescale semiconductor 13-9 pxs20 microcontroller reference manual, rev. 1 13.5.1 adc commands list the adc can be controlled by the cpu (cpu contro l mode) and by the ctu (ctu control mode). the ctu can control the adc from sending an adc comma nd only when the adc is in ctu control mode. during the ctu control mode, the cpu is able to wr ite to the adc registers but it can not start a new conversion. a control bit is allowed to select from the classic interf ace of the ctu control mode. once selected, no change is possible unless a reset occurs. the su uses a commands list in order to select the command to se nd to the adc when a trigger event occurs. the commands list can hold 24 16-bits commands (see section 13.5.2, adc commands list format ) and it is double-buffered, i.e. the commands list can be updated at any time between two consecutive mrs, but the changes be come workable only after the next mrs occurs, and a correct reload is performed. in order to manage the commands list, 5 bits are available in the clcrx (adc commands list control register x), for the position of the firs t command in the list of commands for each trigger event. the number of commands piloted by the same tri gger event is defined directly in the commands list. for each command there is a bit which defines whether it is the first command of a commands list, or not. 13.5.2 adc commands list format the two adcs support the single conver sion mode (1 bit in the adc co mmand format allows selection of the conversion mode), and the dual conversion mode (the sa mpling phases and the conversion phases, are performed at the same time, the storage of the re sults are performed in series). the result of each conversion, in both modes, can be stored in one of the 4 available fifos. in dual conversion mode, both adcs must store the result of their conversion in the sa me fifo. if the access to the fifo is in the same clock cycle, the adc unit a has the priority, otherwise the first adc which ends it s conversion, will write as first in the fifo. 4 analog channels are shared acr oss the 2 adcs and the total number of channels is 28 (12 + 12 + 4 shared channels), i.e. 16 channels for each adc (12 + 4 shared channels). the dual conversion mode on the same physical channel is no t allowed, but the dual conve rsion mode on the same channel number is allowed. according to this, if, in dual conversion mode , the channel number is the same for both the adcs and the selected ch annel is one of the shared channels , the ctu will de tect an invalid command. in dual conversion mode 4 bi ts for each adc are used to se lect the channel number and the conversion mode selection bi t is used to select the dual conversion mode. if the single conversion mode is selected, 5 bits of the 8 bits reserved to select the channels in dual conversion mo de are re-used to select the channel (4 bits) and the adc unit (1 bit). see section 13.10.9, commands list register x (x = 1,...,24) (clrx) . the interrupt request bit is used as an interrupt request to the cpu when adc will complete the command with this bit set and it is only for ctu internal use. before the next co mmand to the ctu controls is sent, the value of the first command bit, is checked to see if it is the current command is the first command of a new stream of consecutive commands or not. if not, the ctu sends the command. according to the previous considerations, the commands in the list will allow to have control on: ? channel a: number of adc channel to sample from adc unit a (4 bits); ? channel b: number of adc channel to sample from adc unit b (4 bits); ? fifo selection bits for the adc unit a/b (2 bits); ? conversion mode selection bit: 0 single c onversion mode - 1 dual conversion mode;
cross-triggering unit (ctu) 13-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? first command bit (only for ctu internal use); ? interrupt request bit (only for ctu internal use). 13.5.3 adc results adc results can be stored in the cha nnel relevant standard result register and/or in one of the 4 fifos: the different fifos allow to dispatch adc results according to the type of acquisition (ex: phase currents, rotor position, ground-noise, other). each fifo has it s own interrupt line and dma request signal (plus an individual overflow error bit in th e fifo status register). the stor e location is specified in the adc command, i.e. the fifos are available only in ctu cont rol mode. each entry of a fifo is 32-bits. the size of the fifos are the following: fifo1 & fifo2: 16 entries (sized to avoid overflow during a full pwm period for current acqui sitions); fifo3 & fifo4: 4 entries (low acquisition rate fifos). results in each fifo can be read by 16 bits r ead transaction (only the result is read in order to minimize the cpu load before computing on results) or by 32 bits read transaction (bot h the result and the channel number are read in order to avoid blind ac quisitions), 5 bits in the upper 16 bi ts indicate the adc unit (1 bit) and the channel number (4 bits). the result registers (only for the fifos) can be read from 2 di fferent addresses in the adc memory map. the format of the result de pends on the address from which it is read. the available formats are ? unsigned right-justified (conversion result is unsigned right-j ustified data, i.e. bits [9:0] ar e used for 10-bit resolution and bits [15:10] always return zero when read). ? signed left-justified (conversion result is signed left-justified data, i.e. bit [15] is reserved for sign and is always read as zero for this adc, bits [14:5] are used for 10- bit resolution and bits [4:0] always return zero when read). 13.6 reload mechanism some ctu registers are double-buffered, and the reload is controlled by a reload enable bit, as the tgsisr_re bit or the dfe bit, but for the most of th e double-buffered registers, th e reload is controlled by the mrs occurrence, and it is synchronized wi th the beginning of the ctu control period. if the mrs occurs while the user is updating some double-buffered registers, e g. some registers of the triggers list, the new triggers list will be a mix of the old triggers list and the new triggers list, because the user has not ended the update of th e triggers list before the mrs occurrence. in order to avoid this case, one bit is used to enable the reload operati on, i.e. to inform the ctu that the user has ended updates to the double-buf fered registers, and the reload can be performed without problems of mixed scenarios. in order to guarantee the cohe rency, the reload of all double-buffered registers is enabled by setting gre (general reload enable) bit in the ctu control register. the user must ensure that all intended double-buff ered registers are updated before a ne w mrs occurrence. if an mrs occurs before a gre bit is set (e.g. wrong application timing), the update is no t performed, the previous values of all double-buffered registers remain active, the error flag is set (the mrs_re bit in the ctu error flag register) and, if enabled, ctu performs an interrupt request.
cross-triggering unit (ctu) freescale semiconductor 13-11 pxs20 microcontroller reference manual, rev. 1 all the double-buffered registers use th e same bit (general reload enable - gre) to enable the reload when the mrs occurs. gre bit is r/s (read/set) and if this bit is 1, the reload can be pe rformed, while if this bit is 0, the reload is not performed. a correct reload reset gre bit. all double-buffered registers cannot be writtento while the gre bi t remains set to 1. the gre bit can be reset by the occurrence of the next mrs (i.e. a correct reload) or by software setting cgre bit. the cgre is reset by hardware after that gre bit is re set. if the user sets the cgre bit and at the same time a mrs occurs, cgre has the priority so gre is reset and the reload is not performed. in the same way, the gre has the priority when compared with the mrs occurrence, and the cgre has the priority compared with the gre (the two bits are in the same register so they can be set in the same time). mrs has the priority compared with the re-synchronization bi t of the tgsisr. in order to verify if a reload error occurs, fgre (f lag gre bit in the ctu cont rol register) bit is used. when one of the double-buffered registers is written, this flag is set to 1 and it is rese t by a correct reload. when the mrs occurs while fgre is 1 and gre is 1, a correct reload is performed (because all intended registers have been updated be fore the mrs occurs). if fgre is 1 and gre is 0, a reload is not performed, the error flag (mrs_re) is set and (i f enabled) an interrupt for an error is performed (in this case at least one register was written but the update has not ended be fore the mrs occurrence). if fgre is 0 it is not necessary to perform a reload because all th e double-buffered registers are unchanged (see figure 13-9 ). figure 13-9. reload error scenario 13.7 power safety mode to reduce power consumption two mechanisms (t he mdis bit and stop mode) are implemented. 13.7.1 mdis bit this bit in the ctupcr register is used for st opping the clock to all non memory mapped registers. 13.7.2 stop mode to reduce power consumption, it is also possible to enable a stop request from the mc_me. the fifos are considered a lot like memory mapped registers, otherwise there could be some problems if a read operation occurs during the mdis bit se t period. when the clock is starte d after an mdis bit setting or a stop signal, some mistakes could occur. for example, a wrong tr igger could be provided because it was programmed before the stop signal was performed, and some incorrect write operations into the fifos normal case error case mrs gre fgre mrs_re mrs gre fgre mrs_re
cross-triggering unit (ctu) 13-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 could happen. for this reason after a stop signal after a mdis bit setting the fifo have to be empty. in order to avoid the problem s linked to a wrong trigger, the ctu output can be di sabled by the ctu_odis bit and the adc interface state machine can be reset by the cru_adc_r (see section 13.10.14, cross triggering unit control register (ctucr) . 13.8 interrupts and dma requests 13.8.1 dma support the dma can be used to configur e the ctu registers. one dma cha nnel is reserved for performing a block transfer, and the mrs can be used as an op tional dma request signal (mrs_dmae bit in the ctu interrupt/dma register). note if enabled, the dma request on the mr s occurrence will be performed only if a reload is performed, i.e. only if gre bit is set. moreover, this ctu implementatio n requires dma support for reading the data from the fifos. one dma channel is available for each fifo. each fi fo can perform a dma request when the number of words stored in the fifo reaches the threshold value. 13.8.2 ctu faults and errors faults and errors which coul d occur during the programming: ? a mrs occurs while user is updating the double-buffered register s and the mrs_re bit is set. ? receiving more than 8 evs before that the ne xt mrs occurs in tgs sequential mode and the sm_to bit is set. ? a trigger event occurs during the time when th e actions of the previous trigger event are not completed (user ensures no trigger event occurs during another one is processed, but if user makes a mistake and a trigger ev ent occurs when another one is proc essed, the incoming trigger event will be lost and an error occurs). there are 4 overrun flags (one for each type of output). the general mechanism shall be as in figure 13-8 . the trigger handler, when a trigger event o ccurs, and the corresponding ready signal is high, presents the respective trigger signal (one cycle high tim e + one cycle low time) to the respective generator sub-block (adc command generator, et 0 trigger generator, et 1 trigger generator or ext. trigger generator). this generator sub-block then generates the requested signal. until this real signal is generated (i ncluding guard time) the ready signal is kept low. in the case of adc command generator, the ready si gnal shall be kept low until the last conversion in the batch is finished. the respective ove rrun flag is set at the following conditions: ? ready signal is low. ? the rising edge of the respectiv e trigger signal (from trigger ha ndler to generator sub-block) occurs.
cross-triggering unit (ctu) freescale semiconductor 13-13 pxs20 microcontroller reference manual, rev. 1 this architecture allows user to pre-set, for example, a trigger to the etimer1 in the middle of an adc conversion, i.e. the su will be considered busy only if a re quest to perform the same action that the su is already performing occurs. one of the adc_oe, t0_oe, t1_oe or et_oe bit is set. ? invalid (unrecognized) adc comm and and the ice bit is set. ? the mrs occurs before the enabled trigge r events occur and the mrs_o bit is set. ? tgs overrun in sequential mode: a new incoming ev occurs before th an the trigger event selected by the previous ev occurs. the in coming ev sets an internal bus y flag. the outgoing trigger event (all line are or-ed) resets this flag to zero. tg s overrun in the sequential mode shall be generated under the following conditions: ? tgs is in sequential mode ? there is an incoming ev while the bus y flag is high. the tgs_osm bit is set. the faults/errors flags in th e ctu error flag register an d in the ctu interrupt flag register can be cleared by writing a 1 while writing a 0 has no effect. th e ctu does not support a write-protection mechanism. 13.8.3 ctu interrupt/dma requests the ctu can perform the following interrupt/dma requests (15 interrupt lines): ? error interrupt request (see section 13.8.2, ctu faults and errors ) (1 interrupt line); ? adc command interrupt reque st (1 interrupt line); ? interrupt request on mrs o ccurrence (1 interrupt line); ? interrupt request on each trigger event occurren ce (1 interrupt line for each trigger event). ? fifos interrupt requests and/or dma transfer request (1 interrupt line for each fifo). ? dma transfer request on the mrs occurrence if gre bit is set; the interrupt flags are shown in table 13-1 . table 13-1. ctu interrupts interrupt interrupt function mrs_re master reload signal reload error sm_to trigger overrun (more than 8 ev) in tgs sequential mode ice invalid command error mrs_o master reload signal overrun tgs_osm tgs overrun in sequential mode adc_oe adc command generation overrun error t0_oe timer 0 trigger generation overrun error t1_oe timer 1 trigger generation overrun error et_oe external trigger generation overrun error adc_i adc command interrupt flag mrs_i mrs interrupt flag
cross-triggering unit (ctu) 13-14 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 note: in order to reduce the number of interrupt lines, the in terupts are combined (or-ed) on the same line, as follows: mrs_re, sm_to, ice, mrs_o, tgs_osm, adc_oe, t0_oe, t1_o e & et_oe - err_i, fifo_full0, fifo_empty0, fifo_overfl ow0 and fifo_overrun0 - fifo1_i, fifo_full1, fifo_empty1, fifo_overfl ow1 and fifo_overrun1 - fifo2_i, fifo_full2, fifo_empty2, fifo_overfl ow2 and fifo_overrun2 - fifo3_i, t0_i trigger 0 interrupt flag t1_i trigger 1 interrupt flag t2_i trigger 2 interrupt flag t3_i trigger 3 interrupt flag t4_i trigger 4 interrupt flag t5_i trigger 5 interrupt flag t6_i trigger 6 interrupt flag t7_i trigger 7 interrupt flag fifo_full0 this bit is set to 1 if the fifo 0 is full. fifo_empty0 this bit is set to 1 if the fifo 0 is empty. fifo_overflow0 this bit is set to 1 if the number of words became higher of the value set in the threshold 0 fifo_overrun0 this bit is set to 1 if a write oper ation occurs when corresponding fifo_full0 flag is set fifo_full1 this bit is set to 1 if the fifo 1 is full. fifo_empty1 this bit is set to 1 if the fifo 1 is empty. fifo_overflow1 this bit is set to 1 if the number of words became higher of the value set in the threshold 1 fifo_overrun1 this bit is set to 1 if a write oper ation occurs when corresponding fifo_full1 flag is set fifo_full2 this bit is set to 1 if the fifo 2 is full. fifo_empty2 this bit is set to 1 if the fifo 2 is empty. fifo_overflow2 this bit is set to 1 if the number of words became higher of the value set in the threshold 2 fifo_overrun2 this bit is set to 1 if a write oper ation occurs when corresponding fifo_full2 flag is set fifo_full3 this bit is set to 1 if the fifo 3 is full. fifo_empty3 this bit is set to 1 if the fifo 3 is empty. fifo_overflow3 this bit is set to 1 if the number of words became higher of the value set in the threshold 3 fifo_overrun3 this bit is set to 1 if a write oper ation occurs when corresponding fifo_full3 flag is set table 13-1. ctu interrupts (continued) interrupt interrupt function
cross-triggering unit (ctu) freescale semiconductor 13-15 pxs20 microcontroller reference manual, rev. 1 fifo_full3, fifo_empty3, fifo_overfl ow3 and fifo_overrun3 - fifo4_i. according to this, the total number of interrupt lines is 15. 13.9 conversion time evaluate using the registers ctu_expected_a and ctu_expe cted_b, it is possible to check if the time between a start of conversion (adctrig) and the end of conv ersion is in a specify range. the range is obtained using the expect ed register and the ctu_cnt_range. the ctu range register is us ed to mask the least signifi cant bit of the ctu_expec ted register. if a bit of the ctu_cnt_range is at one , the correspondent bi t of the "expected regist er" becomes don't care. if the ctu_range is 00001111 and the ctu_ex pected is 10100111. the expected value became 1010---- and the range is from 10100000 - 10101111. 13.10 memory map table 13-2 lists the abbreviations used in this section. different size registers with differen t access are available for this ip: ? 32-bit registers: byte access for write opera tions and 32 bits access for read operation; ? 16-bit registers: byte access for write operati ons and 32 bits access for read operations. if a 32-bit write operation is perf ormed on a 16-bit register, the write operation is performed on the 32 aligned bits. read operation can be performed only at 32 bits. by softwa re to perform any type of read access is possible. in the following tables the ctu registers are shown. table 13-2. bit type description read/write r/w this bit can be read and written read/clear r/c this bit can be read and cleared read/set r/s this bit can be read and set set s this bit can be set read r this bit can be read table 13-3. tgs registers address offset register double-buffere d synchronizatio n reset value 0x0000 tgsisr ? trigger generator subunit input selection register yes tgsisr_re 0x0000 0000 0x0004 tgscr ? trigger generator subunit control register yes mrs 0x0000 0x0006 t0cr ? trigger 0 compare register yes mrs 0x0000 0x0008 t1cr ? trigger 1 compare register yes mrs 0x0000 0x000a t2cr ? trigger 2 compare register yes mrs 0x0000
cross-triggering unit (ctu) 13-16 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 0x000c t3cr ? trigger 3 compare register yes mrs 0x0000 0x000e t4cr ? trigger 4 compare register yes mrs 0x0000 0x0010 t5cr ? trigger 5 compare register yes mrs 0x0000 0x0012 t6cr ? trigger 6 compare register yes mrs 0x0000 0x0014 t7cr ? trigger 7 compare register yes mrs 0x0000 0x0016 tgsccr ? tgs counter compare register yes mrs 0x0000 0x0018 tgscrr ? tgs counter reload register yes mrs 0x0000 table 13-4. su registers address offset register double-buffere d synchronization reset value 0x001c clcr1 ? commands list control register 1 yes mrs 0x0000 0000 0x0020 clcr2 ? commands list control register 2 yes mrs 0x0000 0000 0x0024 thcr1 ? trigger handler control register 1 yes mrs 0x0000 0000 0x0028 thcr2 ? trigger handler control register 2 yes mrs 0x0000 0000 0x002c ... 0x005a clrx ? commands list register x (x = 1,...,24) yes mrs 0x0000 table 13-5. fifo registers address offset register double-buffered synchronization reset value 0x006c fdcr ? fifo dma c ontrol register no --- 0x0000 0x0070 fcr ? fifo control register no --- 0x0000 0000 0x0074 fth ? fifo threshold no --- 0x0000 0000 0x007c fst ? fifo status register no --- 0x0000 0000 0x0080 fr0 ? fifo right aligned data 0 no --- 0x0000 0000 0x0084 fr1 ? fifo right aligned data 1 no --- 0x0000 0000 table 13-3. tgs registers (continued) address offset register double-buffere d synchronizatio n reset value
cross-triggering unit (ctu) freescale semiconductor 13-17 pxs20 microcontroller reference manual, rev. 1 0x0088 fr2 ? fifo right aligned data 2 no --- 0x0000 0000 0x008c fr3 ? fifo right aligned data 3 no --- 0x0000 0000 0x00a0 fl0 ? fifo left aligned data 0 no --- 0x0000 0000 0x00a4 fl1 ? fifo left aligned data 1 no --- 0x0000 0000 0x00a8 fl2 ? fifo left aligned data 2 no --- 0x0000 0000 0x00ac fl3 ? fifo left aligned data 3 no --- 0x0000 0000 table 13-6. other ctu registers address offset register double-buffere d synchronization reset value 0x00c0 ctuefr ? cross triggering unit error flag register no --- 0x0000 0x00c2 ctuifr ? cross triggering unit interrupt flag register no --- 0x0000 0x00c4 ctuir ? cross triggering unit interrupt register no --- 0x0000 0x00c6 cotr ? control on-time register yes mrs 0x0000 0x00c8 ctucr ? cross triggering un it control register no ---- 0x0000 0x00ca ctudf ? cross triggering unit digital filter yes dfe 0x0000 0x00cc ctu_exp_a ? cross trig gering unit expected value a no ---- 0xffff 0x00ce ctu_exp_b ? cross trig gering unit expected value a no ---- 0xffff 0x00d0 ctu_cntrng ? cross triggering unit counter range no ---- 0x0000 table 13-5. fifo registers (continued) address offset register double-buffered synchronization reset value
cross-triggering unit (ctu) 13-18 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 13.10.1 trigger generator subunit input selection register (tgsisr) address: base + 0x0000 0123456789101112131415 i15_f e i15_r e i14_f e i14_r e i13_f e i13_r e i12_f e i12_r e i11_f e i11_r e i10_f e i10_r e i9_fe i9_re i8_fe i8_re r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 i7_fe i7_re i6_fe i6_re i5_fe i5_re i4_fe i4_re i 3_fe i3_re i2_fe i2_re i1_fe i1_re i0_fe i0_re r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0000000000000000 figure 13-10. trigger generator subunit input sel. register(tgsisr) table 13-7. tgsisr field descriptions filed description 0 i15_fe input 15 ext_signals falling edge enable (0: disabled - 1: enabled) 1 i15_re input 15 ext_signals rising edge enable (0: disabled - 1: enabled) 2 i14_fe input 14 etimers2 falling edge enable (0: disabled - 1: enabled) 3 i14_re input 14 etimers2 rising edge enable (0: disabled - 1: enabled) 4 i13_fe input 13 etimers1 falling edge enable (0: disabled - 1: enabled) 5 i13_re input 13 etimers1 rising edge enable (0: disabled - 1: enabled) 6 i12_fe input 12 real pwm ch.3 falling edge enable (0: disabled - 1: enabled) 7 i12_re input 12 real pwm ch.3 rising edge enable (0: disabled - 1: enabled) 8 i11_fe input 11 real pwm ch.2 falling edge enable (0: disabled - 1: enabled) 9 i11_re input 11 real pwm ch.2 rising edge enable (0: disabled - 1: enabled) 10 i10_fe input 10 real pwm ch.1 falling edge enable (0: disabled - 1: enabled) 11 i10_re input 10 real pwm ch.1 rising edge enable (0: disabled - 1: enabled)
cross-triggering unit (ctu) freescale semiconductor 13-19 pxs20 microcontroller reference manual, rev. 1 12 i9_fe input 9 real pwm ch.0 falling edge enable (0: disabled - 1: enabled) 13 i9_re input 9 real pwm ch.0 rising edge enable (0: disabled - 1: enabled) 14 i8_fe input 8 pwm ch.3 even falling edge enable (0: disabled - 1: enabled) 15 i8_re input 8 pwm ch.3 even rising edge enable (0: disabled - 1: enabled) 16 i7_fe input 7 pwm ch.2 even falling edge enable (0: disabled - 1: enabled) 17 i7_re input 7 pwm ch.2 even rising edge enable (0: disabled - 1: enabled) 18 i6_fe input 6 pwm ch.1 even falling edge enable (0: disabled - 1: enabled) 19 i6_re input 6 pwm ch.1 even rising edge enable (0: disabled - 1: enabled) 20 i5_fe input 5 pwm ch.0 even falling edge enable (0: disabled - 1: enabled) 21 i5_re input 5 pwm ch.0 even rising edge enable (0: disabled - 1: enabled) 22 i4_fe input 4 pwm ch.3 odd falling edge enable (0: disabled - 1: enabled) 23 i4_re input 4 pwm ch.3 odd rising edge enable (0: disabled - 1: enabled) 24 i3_fe input 3 pwm ch.2 odd falling edge enable (0: disabled - 1: enabled) 25 i3_re input 3 pwm ch.2 odd rising edge enable (0: disabled - 1: enabled) 26 i2_fe input 2 pwm ch.1 odd falling edge enable (0: disabled - 1: enabled) 27 i2_re input 2 pwm ch.1 odd rising edge enable (0: disabled - 1: enabled) 28 i1_fe input 1 pwm ch.0 odd falling edge enable (0: disabled - 1: enabled) 29 i1_re input 1 pwm ch.0 odd rising edge enable (0: disabled - 1: enabled) 30 i0_fe input 0 pwm reload falling edge enable (0: disabled - 1: enabled) 31 i0_re input 0 pwm reload rising edge enable (0: disabled - 1: enabled) table 13-7. tgsisr field descriptions (continued) filed description
cross-triggering unit (ctu) 13-20 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 13.10.2 trigger generator subu nit control register (tgscr) 13.10.3 txcr - trigger x comp are register (x = 0,...,7) address: base + 0x0004 0 1 2 3 4 5 6 7 8 9 101112131415 0000000 et_t m pres mrs_sm tgs_ m r/w r/w r/w r/w r/w r/w r/w r/w r/w 0000000000000000 figure 13-11. trigger generator subunit control register (tgscr) table 13-8. tgscr field descriptions field description 0-6 reserved 7 et_tm this bit is used for enable toggle mode for external trigger 8-9 pres tgs and su prescaler selection bits (0x00: 1 - 0x01: 2 - 0x02: 3 - 0x03: 4) 10-14 mrs_sm mrs selection in sequential mode (5 bits to select one of the 32 inputs shown in ta bl e 1 3 - 7 ) 15 tgs_m trigger generator subunit mode (0: triggered mode - 1: sequential mode) address: base + 0x0006,...,0x0014 0123456789101112131415 txcrv r/w 0000000000000000 figure 13-12. txcr - trigger x compare register (x = 0,...,7) table 13-9. txcr field descriptions field description 0-15 txcrv trigger x compare register value
cross-triggering unit (ctu) freescale semiconductor 13-21 pxs20 microcontroller reference manual, rev. 1 13.10.4 tgs counter comp are register (tgsccr) 13.10.5 tgs counter reload register (tgscrr) address: base + 0x0016 0123456789101112131415 tgsccv r/w 0000000000000000 figure 13-13. tgs counter compare register (tgsccr) table 13-10. tgsccr field format field description 0-15 tgsccv tgs counter compare value address: base + 0x0018 0123456789101112131415 tgscrv r/w 0000000000000000 figure 13-14. tgs counter reload register (tgscrr) table 13-11. tgscrr field descriptions field description tgscrv tgs counter reload value
cross-triggering unit (ctu) 13-22 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 13.10.6 commands list cont rol register 1 (clcr1) address: base + 0x001c 0123456789101112131415 000 t3_index 000 t2_index r/w r/w 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 000 t1_index 000 t0_index r/w r/w 0000000000000000 figure 13-15. commands list control register 1 (clcr1) table 13-12. clcr1 field description field description 0-2 reserved 3-7 t3_index trigger 3 commands list 1 st command address 8-10 reserved 11-15 t2_index trigger 2 commands list 1 st command address 16-18 reserved 19-23 t1_index trigger 1 commands list 1 st command address 24-26 reserved 27-31 t0_index trigger 0 commands list 1 st command address
cross-triggering unit (ctu) freescale semiconductor 13-23 pxs20 microcontroller reference manual, rev. 1 13.10.7 commands list cont rol register 2 (clcr2) address: base + 0x0020 0123456789101112131415 000 t7_index 000 t6_index r/w r/w 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 000 t5_index 000 t4_index r/w r/w 0000000000000000 figure 13-16. commands list control register 2 (clcr2) table 13-13. clcr2 field description field description 0-2 reserved 3-7 t7_index trigger 7 commands list 1 st command address 8-10 reserved 11-15 t6_index trigger 6 commands list 1 st command address 16-18 reserved 19-23 t5_index trigger 5 commands list 1 st command address 24-26 reserved 27-31 t4_index trigger 4 commands list 1 st command address
cross-triggering unit (ctu) 13-24 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 13.10.8 trigger handler contro l registers (thcr1 and thcr2) address: base + 0x0024 0123456789101112131415 0 t3_e t3_ ete t3_ t4e t3_ t3e t3_ t2e t3_ t1e t3_a dce 0 t2_e t2_ ete t2_ t4e t2_ t3e t2_ t2e t2_ t1e t2_a dce r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 t1_e t1_ ete t1_ t4e t1_ t3e t1_ t2e t1_ t1e t1_a dce 0 t0_e t0_ ete t0_ t4e t0_ t3e t0_ t2e t0_ t1e t0_a dce r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0000000000000000 figure 13-17. trigger handler control register 1 (thcr1) address: base + 0x0028 0123456789101112131415 0 t7_e t7_ ete t7_ t4e t7_ t3e t7_ t2e t7_ t1e t7_a dce 0 t6_e t6_ ete t6_ t4e t6_ t3e t6_ t2e t6_ t1e t6_a dce r/w r/w r/w r/w r/w r/w r/w r/wr/wr/wr/wr/wr/wr/w 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 t5_e t5_ ete t5_ t4e t5_ t3e t5_ t2e t5_ t1e t5_a dce 0 t4_e t4_ ete t4_ t4e t4_ t3e t4_ t2e t4_ t1e t4_a dce r/w r/w r/w r/w r/w r/w r/w r/wr/wr/wr/wr/wr/wr/w 0000000000000000 figure 13-18. trigger handler control register 2 (thcr2) table 13-14. thcr1 and thcr2 field descriptions field description t n _e trigger n enable (0: disabled - 1: enabled) t n _ete trigger n external trigger output enable (0: disabled - 1: enabled) t n _t m e trigger n timer m output enable (0: disabled - 1: enabled) t n _adce trigger n adc command output enable (0: disabled - 1: enabled)
cross-triggering unit (ctu) freescale semiconductor 13-25 pxs20 microcontroller reference manual, rev. 1 13.10.9 commands list regist er x (x = 1,...,24) (clrx) 13.10.9.1 clrx for adc single-conversion mode commands (cms = 0) 13.10.9.2 clrx for adc dual-conversion mode commands (cms = 1) address: base + 0x002c,...,0x005a 0123456789101112131415 cir lc cms fifo 0000 su 0 ch r/w r/w r/w r/w r/w r/w 0000000000000000 figure 13-19. commands list register x (x = 1,...,24) (cms=0) table 13-15. clrx (cms = 0) field descriptions field description cir command interrupt request bit (0: disabled - 1: enabled) lc last command bit (0: not last - 1: last) cms conversion mode selection (0: single conversion mode - 1: dual conversion mode) fifo fifo for adc unit a/b su selection unit bit (0: adc unit a selected - 1: adc unit b selected) ch adc unit channel number address: base + 0x002c,...,0x005a 0123456789101112131415 cir fc cms fifo 0 ch_b 0 ch_a r/w r/w r/w r/w r/w r/w 0000000000000000 figure 13-20. commands list register x (x = 1,...,24) (cms=1) table 13-16. clrx (cms = 1) field descriptions field description cir command interrupt request bit (0: disabled - 1: enabled) fc first command bit (0: not first - 1: first) cms conversion mode selection (0: single conversion mode - 1: dual conversion mode) fifo fifo for adc unit a/b
cross-triggering unit (ctu) 13-26 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 13.10.9.3 clrx for self-test commands (st1 = 0) ch_b adc unit b channel number ch_a adc unit a channel number address: base + 0x002c,...,0x005a 0123456789101112131415 cir lc st1 cms su rfu st0 alg bsize r/w r/w r/w r/w r/w r/w r/w r/w r/w 0000000000000000 figure 13-21. commands list register x (x = 1,...,24) (st1 = 0) table 13-17. clrx (cms = 1) field descriptions field description cir command interrupt request bit (0: disabled - 1: enabled) lc last command bit 0: not last 1: last st1 self test mode. st1 must equal 0 if you want to send a self test command. cms conversion mode selection 0: single conversion mode 1: dual conversion mode su selection unit bit, usable only if cms is at zero. 0: adc unit a 1: adc unit b rfu reserved for future use st0 self test mode. st0 must equal 1 if you are considering this register configuration. alg algorithm scheduled: 00: algorithm s 01: algorithm rc 10: algorithm c 11: full algorithm (s + rc + c) bsize burst size of the algorithm iteration. 0: single step execution n: n+1 step execution with one trigger table 13-16. clrx (cms = 1) field descriptions (continued) field description
cross-triggering unit (ctu) freescale semiconductor 13-27 pxs20 microcontroller reference manual, rev. 1 13.10.10 cross triggering unit error flag register (ctuefr) 13.10.11 cross triggering unit in terrupt flag register (ctuifr) address: base + 0x00c0 0123456789101112131415 0000 et_o e err cmp t4_ oe t3_ oe t2_ oe t1_ oe adc_ oe tgs_ osm mrs_ o ice sm_t o mrs_ re r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c 0000000000000000 figure 13-22. cross triggering unit error flag register (ctuefr) table 13-18. ctuefr field description field description et_oe external trigger generation overrun error t n _oe timer n trigger generation overrun error adc_oe adc command generation overrun error tgs_osm tgs overrun in sequential mode mrs_o master reload signal overrun ice invalid command error sm_to trigger overrun (more than 8 ev) in tgs sequential mode mrs_re master reload signal reload error address: base + 0x00c2 0 1 2 3 4 5 6 7 8 9 101112131415 0000 serr _b serr _a adc_ i t7_i t6_i t5_i t4_i t 3_i t2_i t1_i t0_i mrs_ i r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c 0000000000000000 figure 13-23. cross triggering unit interrupt flag register (ctuifr) table 13-19. ctuifr field descriptions field description serr_b if this bit is set means that the slice ti me between the start of conversion and the end of conversion is in the expected range serr_a if this bit is set means that the slice ti me between the start of conversion and the end of conversion is in the expected range adc_i adc command interrupt flag
cross-triggering unit (ctu) 13-28 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 13.10.12 cross triggering unit interrupt/dma register (ctuir) 13.10.13 control on time register (cotr) t n _i trigger n interrupt flag mrs_i mrs interrupt flag address: base + 0x00c4 0 1 2 3 4 5 6 7 8 9 101112131415 t7_ie t6_ie t5_ie t4_ie t3_ie t2_ie t1_ie t0_ie 00 saf_ cnt_ b_en saf_ cnt_ a_en dma_ de mrs_ dmae mrs_ ie iee r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0000000000000000 figure 13-24. cross triggering unit interrupt/dma register (ctuir) table 13-20. ctuir field description field description t n _ie trigger n interrupt enable saf_cnt_b_en if this bit is set the counter us ed to check the conversion time is enabled saf_cnt_a_en if this bit is set the counter us ed to check the conversion time is enabled dma_de if this bit is set, a dma done is like a write in the gre bit. if it is at 0 you have to write the gre bit (if something is changed in the double buff ered register) otherwise you will have an error on the next master reload. mrs_dmae dma transfer enable on mr s occurrence if gre bit is set mrs_ie mrs interrupt enable iee interrupt error enable address: base + 0x00c6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 00000000 cotr r/w 0000000000000000 figure 13-25. control on time register (cotr) table 13-19. ctuifr field descriptions field description
cross-triggering unit (ctu) freescale semiconductor 13-29 pxs20 microcontroller reference manual, rev. 1 13.10.14 cross triggering unit control register (ctucr) table 13-21. cotr field description field description 0-7 reserved 8-15 cotr control on-time and guard time for external trigger address: base + 0x00c8 0123456789101112131415 t7_s g t6_s g t5_s g t4_s g t3_s g t2_s g t1_s g t0_s g cru_ adc_ r ctu_ odis fe cgre fgre mrs_ sg gre tgsi sr_r e sssssssssr/wr/ssrsr/sr/s 0000000000000000 figure 13-26. cross triggering unit control register (ctucr) table 13-22. ctucr field descriptions field description 0 t7_sg trigger 7 software generated 1 t6_sg trigger 6 software generated 2 t5_sg trigger 5 software generated 3 t4_sg trigger 4 software generated 4 t3_sg trigger 3 software generated 5 t2_sg trigger 2 software generated 6 t1_sg trigger 1 software generated 7 t0_sg trigger 0 software generated 8 cru_adc_r ctu/adc state machine reset 9 ctu_odis ctu output disable
cross-triggering unit (ctu) 13-30 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 13.10.15 cross triggering unit digital filter (ctudf) 13.10.16 cross triggering unit expected value a (ctu_exp_a) this register is used to configur e the number of the expected clock cy cles needed for th e conversion time of adc_0. please refer section 13.9, convers ion time evaluate for more details. 10 dfe digital filter enable 11 cgre clear gre 12 fgre flag gre 13 mrs_sg mrs software generated 14 gre general reload enable 15 tgsisr_re tgs input selection register reload enable address: base + 0x00ca 0123456789101112131415 00000000 n r/w 0000000000000000 figure 13-27. cross triggering unit digital filter (ctudf) table 13-23. ctudf field descriptions field description 0-7 reserved 8-15 n digital filter value (the external signal is considered at 1 if it is latched n time at 1 and is considered at 0 if it is latched n time at 0) table 13-22. ctucr field descriptions field description
cross-triggering unit (ctu) freescale semiconductor 13-31 pxs20 microcontroller reference manual, rev. 1 13.10.17 cross triggering unit expected value b (ctu_exp_b) this register is used to configur e the number of the expected clock cy cles needed for th e conversion time of adc_1. please refer section 13.9, convers ion time evaluate for more details. 13.10.18 cross triggering unit counter rang e (ctu_cntrng) this register is used to mask the less significant bi ts in the expected clock cycles (i.e. ctu_exp_a and ctu_exp_b). in this way it is possible to define an acceptance range around these values.please refer section 13.9, conversion time evaluate for more details address: base + 0x00cc 0123456789101112131415 value r/w 1111111111111111 figure 13-28. cross triggering unit expected value a (ctu_exp_a) table 13-24. ctu_exp_a field descriptions field description value this value is the number of system clock cycle needed for the conversion time.(adc 0) address: base + 0x00ce 0123456789101112131415 value r/w 1111111111111111 figure 13-29. cross triggering unit expected value b (ctu_exp_b) table 13-25. ctu_exp_b field descriptions field description value this value is the number of system clock cycle needed for the conversion time.(adc 1) address: base + 0x00d0 0123456789101112131415 00000000 value r/w 0000000000000000 figure 13-30. cross triggering unit counter range (ctu_cntrng)
cross-triggering unit (ctu) 13-32 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 13.10.19 fifo dma cont rol register (fdcr) 13.10.20 fifo control register (fcr) table 13-26. ctu_cntrng field descriptions field description value setting at one this bit you mask the same bit of the expected counter and of the internal counter. in this way you can set a range for the expected conversion time. address: base + 0x006c 0123456789101112131415 000000000000 de3 de2 de1 de0 r/w r/w r/w r/w 0000000000000000 figure 13-31. fifo dma control register (fdcr) table 13-27. fdcr field description name description 0-11 reserved 12-15 dex this bit enables dma for the fifox address: base + 0x0070 0123456789101112131415 0000000000000000 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 or_e n3 of_e n3 empt y_en 3 full _en3 or_e n2 of_e n2 empt y_en 2 full _en2 or_e n1 of_e n1 empt y_en 1 full _en1 or_e n0 of_e n0 empt y_en 0 full _en0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0000000000000000 figure 13-32. fifo control register (fcr)
cross-triggering unit (ctu) freescale semiconductor 13-33 pxs20 microcontroller reference manual, rev. 1 table 13-28. fcr field descriptions field description 0-15 reserved 16 or_en3 fifo 3 overrun interrupt enable 17 of_en3 fifo 3 threshold overflow interrupt enable 18 empty_en3 fifo 3 empty interrupt enable 19 full_en3 fifo 3 full interrupt enable 20 or_en2 fifo 2 overrun interrupt enable 21 of_en2 fifo 2 threshold overflow interrupt enable 22 empty_en2 fifo 2 empty interrupt enable 23 full_en2 fifo 2 full interrupt enable 24 or_en1 fifo 1 overrun interrupt enable 25 of_en1 fifo 1 threshold overflow interrupt enable 26 empty_en1 fifo 1 empty interrupt enable 27 full_en1 fifo 1 full interrupt enable 28 or_en0 fifo 0 overrun interrupt enable 29 of_en0 fifo 0 threshold overflow interrupt enable 30 empty_en0 fifo 0 empty interrupt enable 31 full_en0 fifo 0 full interrupt enable
cross-triggering unit (ctu) 13-34 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 13.10.21 fifo threshold (fth) 13.10.22 fifo status register (fst) address: base + 0x0074 0 1 2 3 4 5 6 7 8 9 101112131415 th3 th2 r/w r/w 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 th1 th0 r/w r/w 0000000000000000 figure 13-33. fifo control register (fcr) field description 0-7 th3 fifo 3 threshold 8-15 th2 fifo 2 threshold 16-23 th1 fifo 1 threshold 24-31 th0 fifo 0 threshold address: base + 0x007c 0 1 2 3 4 5 6 7 8 9 101112131415 0000000000000000 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 or3 of3 emp3 full 3 or2 of2 emp2 full 2 or1 of1 emp1 full 1 or0 of0 emp0 full 0 r/crrrr/crrrr/crrrr/crrr 0000000000000000 figure 13-34. fifo status register (fst)
cross-triggering unit (ctu) freescale semiconductor 13-35 pxs20 microcontroller reference manual, rev. 1 table 13-29. fst field descriptions field description 0-15 reserved 16 or3 fifo 3 overrun interrupt flag 17 of3 fifo 3 threshold overflow interrupt flag 18 emp3 fifo 3 empty interrupt flag 19 full3 fifo 3 full interrupt flag 20 or2 fifo 2 overrun interrupt flag 21 of2 fifo 2 threshold overflow interrupt flag 22 emp2 fifo 2 empty interrupt flag 23 full2 fifo 2 full interrupt flag 24 or1 fifo 1 overrun interrupt flag 25 of1 fifo 1 threshold overflow interrupt flag 26 emp1 fifo 1 empty interrupt flag 27 full1 fifo 1 full interrupt flag 28 or0 fifo 0 overrun interrupt flag 29 of0 fifo 0 threshold overflow interrupt flag 30 emp0 fifo 0 empty interrupt flag 31 full0 fifo 0 full interrupt flag
cross-triggering unit (ctu) 13-36 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 13.10.23 fifo right aligned data x (x = 0,...,3) (frx) 13.10.24 fifo signed left alig ned data x (x = 0,...,3) (flx) address: base + 0x0080,...,0x008c 0123456789101112131415 00000000000 adc n_ch rr 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0000 data r 0000000000000000 figure 13-35. fifo right aligned data x table 13-30. frx filed descriptions field description adc this bit is used for indicate from which adc the data is coming from. 1: the data is coming from adc_0 0: the data is coming from adc_1 n_ch number of stored channel data data of stored channel address: base + 0x00a0,...,0x00ac 0123456789101112131415 00000000000 adc n_ch rr 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 data 000 r 0000000000000000 figure 13-36. fifo signed left aligned data x
cross-triggering unit (ctu) freescale semiconductor 13-37 pxs20 microcontroller reference manual, rev. 1 table 13-31. flx field description field description adc this bit is used for indicate from which adc the data is coming from. 1: the data is coming from adc_0 0: the data is coming from adc_1 n_ch number of stored channel data data of stored channel
cross-triggering unit (ctu) 13-38 freescale semiconductor pxs20 microcontroller reference manual, rev. 1
cyclic redundancy checker (crc) unit freescale semiconductor 14-1 pxs20 microcontroller reference manual, rev. 1 chapter 14 cyclic redundancy checker (crc) unit 14.1 introduction the crc computing unit is dedicated to the computation of crc of f-loading the cpu. each context has a separate crc computation engine in order to allow the concurrent computation of the crc of multiple data streams. the crc computation is performed at speed without wait states insertion. bit-swap and bit-inversion operations can be applied on the final c rc signature. each context can be configured with one of two (on cut1) or three (on cut2/3) hard-wired polynomials, normall y used for most of the standard communication protocols. th e data stream supports multiple data width (byte/half-w ord/word) formats. 14.1.1 glossary ? crc: cyclic redundancy check ? ips: internal peripheral system ? cpu: central processing unit ? dma: direct memory access ? ccitt: itu-t (for telecommunication standa rdization sector of the international telecommunications union) ? sw: software ? ws: wait state ? spi: serial peripheral interface 14.2 features ? 1 to 16 contexts (static parameter) for the conc urrent crc computation. for this application the number of context is crc_cntx_num = 3 ? separate crc engine for each context ? zero-wait states during the c rc computation (pipeline scheme) ? up to 3 hard-wired polynomials: ? crc-8 (supported on cut2/3 only) ? crc-16-ccitt ? crc-32 ethernet ? support for byte/half-word/word wi dth of the input data stream ? ips slave bus interface 14.3 block diagram the top level diagram of the crc module is given in figure 14-1 . the number of context crc_cntx_num is equal to 3 for this application.
cyclic redundancy checker (crc) unit 14-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 14-1. crc top level diagram 14.4 signal description the crc unit does not generate any external signals. 14.5 register description the crc registers are listed in table 14-1 . the n index selects the specific context and is included in the range 1 to 3. s table 14-1. crc registers address offset register location 0x0 + (n?1) ? 0x10 crc configuratio n register (crc_cfg) on page 14-3 0x4 + (n?1) ? 0x10 crc input register (crc_inp) on page 14-4 0x8 + (n?1) ? 0x10 crc current status register (crc_cstat) on page 14-5 0xc + (n?1) ? 0x10 crc output register (crc_outp) on page 14-6 context 1 context n config & data registers context 1 context n crc engine ips s
cyclic redundancy checker (crc) unit freescale semiconductor 14-3 pxs20 microcontroller reference manual, rev. 1 14.5.1 crc configuration register (crc_cfg) offset: 0x0 + (n?1) ? 0x10 access: user read/write 0123456789101112131415 r00000 0 000000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0000000 00000 polyg swap inv w reset00000000 000000/1 1 00 1 0 when n is even; 1 when n is odd figure 14-2. crc configuration register (crc_cfg) for cut1 offset: 0x0 + (n?1) ? 0x10 access: user read/write 0123456789101112131415 r00000 0 000000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0000000 0000 polyg swap inv w reset00000000 000000/1 1 00 1 0 when n is even; 1 when n is odd figure 14-3. crc configuration register (crc_cfg) for cut2/3
cyclic redundancy checker (crc) unit 14-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 14.5.2 crc input register (crc_inp) table 14-2. crc_cfg field descriptions field description polyg (for cut1) polynomial selection 0 crc-ccitt polynomial 1 crc-32 polynomial. this bit can be read and written by the software. this bit can be written only during the configuration phase. polyg (for cut2/3) polynomial selection 00 crc-ccitt polynomial 01 crc-32 polynomial 10 crc-8 polynomial 11 reserved this field can be read and written by the software. this field can be written only during the configuration phase. swap swap selection 0: no swap selection applied on the crc_outp content 1: swap selection (msb -> lsb, lsb -> msb) applied on the crc_outp content. in case of crc-ccitt polynomial the swap operation is applied on the 16 lsb bits. this bit can be read and written by the software. this bit can be written only during the configuration phase. inv inv selection 0: no inversion selection applied on the crc_outp content 1: inversion selection (bit x bit) applied on the crc_outp content. in case of crc-ccitt polynomial the inversion operation is applied on the 16 lsb bits. this bit can be read and written by the software. this bit can be written only during the configuration phase. offset: 0x4 + (n?1) ? 0x10 access: user read/write 0123456789101112131415 r inp[31:16] w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r inp[15:0] w reset00000000 00000000 figure 14-4. crc input register (crc_inp)
cyclic redundancy checker (crc) unit freescale semiconductor 14-5 pxs20 microcontroller reference manual, rev. 1 14.5.3 crc current status register (crc_cstat) table 14-3. crc_inp field descriptions field description inp input data for the crc computation the inp register can be written at byte, half-word (h igh and low) or word in any sequence. in case of half-word write operation, the bytes must be contiguous. this register can be read a nd written by the software. offset: 0x8 + (n?1) ? 0x10 access: user read/write 0123456789101112131415 r cstat[31:16] w reset11111111 11111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cstat[15:0] w reset11111111 11111111 figure 14-5. crc current status register (crc_cstat) table 14-4. crc_cstat field descriptions field description cstat status of the crc signature the cstat register includes the current status of the crc signature. no bit swap and inversion are applied to this register. in case of crc-ccitt polynomial only the16 lsb bits ar e significative. the 16 msb bits are tied at 0b during the computation. the cstat register can be written at byte, half-word or word. this register can be read and written by the software. this register can be written only during the configuration phase.
cyclic redundancy checker (crc) unit 14-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 14.5.4 crc output re gister (crc_outp) 14.6 functional description the crc module supports the crc computation for each context. each context has a own complete set of registers including the crc engine. the data flow of each context can be inte rleaved. the data stream can be structured as a sequence of byte, half-words or words. th e input data seque nce is provided, eventually mixing the data formats ( byte, half-word, word), writing to the input data register (crc_inp). the data stream is generally executed by n concurre nt dma data transfers (m em2mem) where n is less or equal to the number of contexts (3). three standard generator polynomials are given in equation 14-1 through equation 14-3 for the crc computation of each context. crc-8 (cut2/3 only) eqn. 14-1 crc-ccitt (x25 protocol) eqn. 14-2 offset: 0xc + (n?1) ? 0x10 access: user read 0123456789101112131415 r outp[31:16] w reset11111111 11111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r outp[15:0] w reset11111111 11111111 figure 14-6. crc output register (crc_outp) table 14-5. crc_outp field descriptions field description outp final crc signature the outp register includes the final signature corresponding to the crc_cstat register value eventually swapped and inverted. in case of crc-ccitt polynomial only the16 lsb bits ar e significative. the 16 msb bits are tied at 0b during the computation. this register can be read by the software. x 8 x 4 x 3 x 2 1 ++++ x 16 x 12 x 5 1 +++
cyclic redundancy checker (crc) unit freescale semiconductor 14-7 pxs20 microcontroller reference manual, rev. 1 crc-32 (ethernet protocol) eqn. 14-3 figure 14-7. crc-ccitt e ngine concept scheme the initial seed value of the cr c can be programmed initializing th e crc_cstat register. the concept scheme (serial data loading) of the crc engine is given in figure 14-7 for the crc-ccitt. the design implementation executes the crc com putation in a single clock cycle (p arallel data loading). a pipeline scheme has been adopted to de-coupl e the ips bus interface from the c rc engine in order to allow the computation of the crc at speed (zero wait states). in case of usage of the crc signature for encapsulati on in the data frame of a communication protocol (e.g. spi, ..) a bit swap (msb ? lsb, lsb ? msb) and/or bit inversion of the final crc signature can be applied (crc_outp register) before to transmit the crc. the usage of the crc module is summ arized in the flowchart given in figure 14-8 . x 32 x 26 x 23 x 22 x 16 x 12 x 11 x 10 x 8 x 7 x 5 x 4 x 2 x 1 +++++++ +++++++ serial data input (lsb first) + 40 5 11 12 15 ++
cyclic redundancy checker (crc) unit 14-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 14-8. crc computation flow 14.7 use cases and limitations the number of contexts is dependent on the applic ation. the overall number of contexts for the crc peripheral depends on the numbe r of the peripherals that require conc urrently the intervention of the crc module. 2 main use cases shall be considered: ? calculation of the crc of the configuratio n registers during the process safety time ? calculation of the crc on the incoming/outcom ing frames for the communication protocols (not protected with crc by definition of the protocol itself) used as a safety-relevant peripheral. the signature of the configuration registers is com puted in a correct way only if these registers do not contain any status bit. as suming that the dma engine has n channels (greater or equal to the number of contexts) configurable fo r the following type of data transfer: mem2mem, periph2mem, mem2periph, the following sequence, as given in figure 14-9 , shall be applied to manage the transmission data flow: no yes crc configuration (polynomial, swap, inversion) setting the crc_cfg register crc signature available in the crc_outp register all the data has been passed crc seed initialization (crc_cstat register) data is written in the crc_inp register (byte/hword/word) by cpu or dma to the crc unit ? start context = crc_cntx_num context = 1
cyclic redundancy checker (crc) unit freescale semiconductor 14-9 pxs20 microcontroller reference manual, rev. 1 ? dma/crc module configuration (context x, channel x) by cpu ? payload transfer from the mem to the crc module (crc_inp register) to calculate the crc signature (phase1) by dma (mem2m em data transfer, channel x) ? crc signature copy from the crc module (crc_ outp register) to the mem (phase 2) by cpu ? data block (payload + crc) tran sfer from the mem to the pe riph module (e.g. spi tx fifo) (phase 3) by dma (mem2peri ph data transfer, channel x) the following sequence, as given in figure 14-9 , shall be applied to manage the reception data flow: ? dma/crc module configuration (context x, channel x) by cpu ? data block (payload + crc) tr ansfer from the periph (e.g. sp i rx fifo) module to the mem (phase 1) by dma (periph2mem data transfer, channel x) ? data block transfer (payload + crc) transf er from the mem to the crc module (crc_inp register) to calculate the crc signature (phase 2) by dma (mem2mem da ta transfer, channel x) ? crc signature check from the crc modul e (crc_outp register) by cpu (phase 3)
cyclic redundancy checker (crc) unit 14-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 14-9. dma-crc (tx flow, rx flow) dma (mem2mem, channel x) crc_outp crc payload mem (context x) phase 1 (tx) crc_inp cpu crc payload mem (context x) phase 2 (tx) crc dma (mem2periph, channel x) payload mem spi phase 3 (tx) crc dma (periph2mem, channel x) payload mem spi phase 1 (rx) crc_outp crc payload mem (context x) phase 2 (rx) crc phase 3 (rx) tx flow rx flow crc crc_inp crc_outp crc (context x) dma (mem2mem, channel x) cpu check crc_inp crc_outp tx fifo rx fifo crc_inp
crossbar switch (xbar) freescale semiconductor 15-1 pxs20 microcontroller reference manual, rev. 1 chapter 15 crossbar switch (xbar) 15.1 information specific to this device this section presents device-specifi c parameterization, customization, and feature availability information not specifically referenced in the remainder of this chapter. 15.1.1 register availability not all registers listed in table 15-4 are available on this device. speci fically, this devi ce includes only registers for: ? slaves 0, 2, and 7 ? masters 0, 1, 2, 3, 5, and 6 15.1.2 mpr reset value the reset value of the mpr register on this device is 0x0540_3210. 15.1.3 max_halt signal unavailable the max_halt signal is unavailable on this device. 15.1.4 logical master ids table 15-1 defines the logical master id used for the chip masters in lock step mode (lsm) and decoupled parallel mode (dpm). th e logical master ids for the two co res are different in dpm so that they both can access the same xbar. table 15-1. logical master ids master logical master id lsm dpm core_0 instruction port core_0 load/store port 00 core_1 instruction port core_1 load/store port 1 edma_0 2 2 edma_1 6 1 core_0 nexus 8 2 8 2 core_1 nexus 9 2 flexray 3 3
crossbar switch (xbar) 15-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 15.1.5 master port allocation table 15-2 defines the xbar master por t allocation for this device. 15.1.6 slave port allocation table 15-3 defines the xbar slave por t allocation for this device. notes: 1 dma_1 is not enabled in dpm. lmid assigned he re for completeness and future enhancements. 2 the mpu cannot differentiate between core and nexus accesses to slave ports. table 15-2. xbar master port allocation xbar master port lsm dpm xbar_0 module xbar_1 module xbar_0 module xbar_1 module m0 z4d_0 core complex instruction port z4d_1 core complex instruction port z4d_0 core complex instruction port z4d_1 core complex instruction port m1 z4d_0 core complex load/store port + nexus port z4d_1 core complex load/store port + nexus port z4d_0 core complex load/store port + nexus port z4d_1 core complex load/store port + nexus port m2 dma_0 dma_1 dma_0 dma_1 1 notes: 1 dma_1 is not enabled in dpm. xbar master port a ssigned here for completeness and future enhancements. m3 flexray flexray flexray flexray m4???? m5 ? ? z4d_1 core complex instruction port z4d_0 core complex instruction port m6 ? ? z4d_1 core complex load/store port + nexus port z4d_0 core complex load/store port + nexus port m7???? table 15-3. xbar slave port allocation xbar slave port lsm dpm xbar_0 module xbar_1 module xbar_0 module xbar_1 module s0 pflash_0_port_0 pflash_1_port_1 pflash_0_port_0 pflash_1_port_0 pflash_0_port_1 pflash_1_port_1 s1???? s2 sramc_0 sramc_1 sramc_0 sramc_1 s3????
crossbar switch (xbar) freescale semiconductor 15-3 pxs20 microcontroller reference manual, rev. 1 15.2 introduction 15.2.1 overview this section provides an overview of the gene ric multi-layer ahb crossbar switch (xbar 1 ). the purpose of the xbar is to concurrently support up to ei ght simultaneous connections between master ports and slave ports. the xbar supports a 32 -bit address bus width and a 64-bit data bus width at all master and slave ports. 15.2.2 features the xbar has the ability to gain control of all the slave ports a nd prevent any masters from making accesses to the slave ports. this featur e is useful when the user wishes to turn off the clocks to the system and needs to ensure that no bus activity will be interrupted. the xbar can put each slave port in to a low power park mode so that slave port will not dissipate any power transitioning address, control or data signal s when not being actively accessed by a master port. each slave port can also support multiple master prio rity schemes. each slave port has a hardware input which selects the master priority scheme so the user can dynamically change master priority levels on a slave port by slave port basis. the xbar will allow for concurrent transactions to occur from any mast er port to any slave port. it is possible for all master ports and slave ports to be in use at the same time as a result of independent master requests. if a slave port is simultan eously requested by more than one ma ster port, arbitration logic will select the higher priority master and grant it ownershi p of the slave port. all other masters requesting that slave port will stalled until the higher prio rity master completes its transactions. 15.2.3 limitations the xbar routes bus transactions initiated on the mast er ports to the appropriate slave ports. there is no provision included to route tr ansactions initiated on the slave ports to other slave ports or to master ports. simply put, the slave ports do not support the bus request/bus grant prot ocol, the xbar assumes it is the sole master of each slave port. s4???? s5???? s6???? s7 pbridge_0 pbridge_1 pbridge_0 pbridge_1 1.an alternate abbreviatio n for this module is max. table 15-3. xbar slave port allocation (continued) xbar slave port lsm dpm xbar_0 module xbar_1 module xbar_0 module xbar_1 module
crossbar switch (xbar) 15-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 since the xbar does not s upport the bus request/bus grant protocol , if multiple masters are to be connected to a single master port an external arbiter w ill need to be used. in th e case of a single master connecting to a master port the single master?s bus gr ant signal must be tied off in the asserted state. each master and slave port is full y ahb-lite + amba v6 extensions co mpliant. the ports are not fully ahb compliant because the xbar does not support splits or retrys. 15.2.4 general operation when a master makes an access to the xbar the ac cess will be immediately ta ken by the xbar. if the targeted slave port of the access is available then the access will be immediately presented on the slave port. it is possible to make single clock (zero wait state) accesses thr ough the xbar. if the targeted slave port of the access is busy or parked on a different master port the reques ting master will simply see wait states inserted ( hready held negated) until the targeted slave port can service the ma ster?s request. the latency in servicing the request wi ll depend on each master?s priority level and th e responding peripheral?s access time. since the xbar appears to be just another slave to the master device, the master device will have no knowledge of whether or not it actual ly owns the slave port it is target ing. while the master does not have control of the slave port it is target ing it will simply be wait stated. a master will be given control of the targeted slav e port only after a previous access to a different slave port has completed, regardless of its priority on the newly targeted slave port. this prevents deadlock from occurring when a master has an out standing request to one slave port that has a long response time, has a pending access to a different slave port, and a lower prio rity master is also making a request to the same slave port as the pending access of the higher priority master. once the master has control of the slave port it is target ing the master will remain in control of that slave port until it gives up the slave port by running an idle cycle or by leaving that slave port for its next access. the master could also lose control of the slave port if another higher priority master makes a request to the slave port; however, if the master is ru nning a locked or fixed length burst transfer it will retain control of the slave port unt il that transfer is completed. ba sed on the aulb bit in the mgpcr (master general purpose control regi ster) the master will either reta in control of the slave port when doing undefined length incrementing burst transfers or will lose the bus to a higher priority master. the xbar will terminate al l master idle transfers (as opposed to al lowing the termination to come from one of the slave busses). additionally, when no master is requesting access to a slave port the xbar will drive idle transfers onto the slave bus, even though a default master ma y be granted access to the slave port. when the xbar is controlling the slave bus (that is, during low power park or halt mode) the hmaster field will indicate 4?b0000. when a slave bus is being idled by the xbar it can park the slave port on the master port indicated by the park bits in the sgpcr (slave general purpose control register). th is can be done in an attempt to save the initial clock of arbitration de lay that would otherwise be seen if the master had to arbitrate to gain control of the slave port. the slave por t can also be put into low power pa rk mode in attempt to save power.
crossbar switch (xbar) freescale semiconductor 15-5 pxs20 microcontroller reference manual, rev. 1 15.3 xbar registers this section provides info rmation on xbar registers. 15.3.1 register summary there are four registers that reside in each slave port of the xbar and one regist er that resides in each master port of the xbar. these regi sters are ip bus compliant register s. read and write transfers both require two ip bus clock cycles. the registers can only be read from a nd written to in supervisor mode. additionally, these registers can only be r ead from or written to by 32-bit accesses. the registers are fully decoded and an error response is returned if an unimplemented location is accessed within the xbar. the slave registers also feature a bit, which when wr itten with a 1, will preven t the registers from being written to again. the registers will st ill be readable, but future write at tempts will have no effect on the registers and will be termin ated with an error response. the memory map for the xbar program -visible registers is shown in table 15-4 . table 15-5 shows the xbar register summary. table 15-4. xbar register configuration summary xbar base offset register use 0x000 mpr0 master priority register for slave port 0 0x010 sgpcr0 general purpose control register for slave port 0 0x100 mpr1 master priority register for slave port 1 0x110 sgpcr1 general purpose control register for slave port 1 0x200 mpr2 master priority register for slave port 2 0x210 sgpcr2 general purpose control register for slave port 2 0x300 mpr3 master priority register for slave port 3 0x310 sgpcr3 general purpose control register for slave port 3 0x400 mpr4 master priority register for slave port 4 0x410 sgpcr4 general purpose control register for slave port 4 0x500 mpr5 master priority register for slave port 5 0x510 sgpcr5 general purpose control register for slave port 5 0x600 mpr6 master priority register for slave port 6 0x610 sgpcr6 general purpose control register for slave port 6 0x700 mpr7 master priority register for slave port 7 0x710 sgpcr7 general purpose control register for slave port 7 0x800 mgpcr0 general purpose control register for master port 0 0x900 mgpcr1 general purpose control register for master port 1 0xa00 mgpcr2 general purpose control register for master port 2 0xb00 mgpcr3 general purpose control register for master port 3 0xc00 mgpcr4 general purpose control register for master port 4 0xd00 mgpcr5 general purpose control register for master port 5 0xe00 mgpcr6 general purpose control register for master port 6 0xf00 mgpcr7 general purpose control register for master port 7
crossbar switch (xbar) 15-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 note: for n = 0 to 7 15.3.2 xbar register descriptions the following paragraphs provide detailed de scriptions of the various xbar registers. table 15-6 provides a key to the term s found in xbar registers. always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a ? bit w1c bit figure 15-1. key to register fields table 15-5. xbar register summary name 0123456789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mprn ($base + 0x000 + n*0x100) r0mstr_70mstr_60mstr_50mstr_4 w r0mstr_30mstr_20mstr_10mstr_0 w sgpcrn ($base + 0x010 + n*0x100) r0000000000000000 wro hlp hpe7hpe6hpe5hpe4hpe3hpe2hpe1hpe0 r0000000000000000 w arb pctl pa r k mgpcrn ($base + 0x800 + n*0x100 r0000000000000000 w r0000000000000000 w aulb table 15-6. register terms term description gray bit unimplemented bit; always reads as zero;writing has no effect access s supervisor mode only ? supervisor or user mode type r read only; writing to this bit has no effect w write only rw standard read/write bit. only software can change a bit?s value (other than a hardware reset). rwm a read/write bit that may be modifi ed by hardware in some fashion other than reset. w1c a status bit that can be read and cleared by writing a logic 1
crossbar switch (xbar) freescale semiconductor 15-7 pxs20 microcontroller reference manual, rev. 1 15.3.2.1 master priority register the master priority register (mpr) sets the priori ty of each master port on a per slave port basis and resides in each slave port. note: for n = 0 to 7 figure 15-2. master priority register n slfclr self-clearing bit. writing a 1 has some effect on module, but it always reads as a 0. reset 0 resets to a logic 0 1 resets to a logic 1 u unaffected by reset ? reset state is unknown. mprn master priority register n addr $base + 0x000 + n*100 wait state: 0 access: s 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mstr_7 mstr_6 mstr_5 mstr_4 type: r rw rw rw r rw rw rw r rw rw rw r rw rw rw reset: 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mstr_3 mstr_2 mstr_1 mstr_0 type: r rw rw rw r rw rw rw r rw rw rw r rw rw rw reset: 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 table 15-7. master priority register descriptions name description settings bit 0 master priority register reserved - this bit is reserved for future expansion. it is read as zero and should be written with zero for upward compatibility. na mstr_7 master 7 priority - these bits set the arbitration priority for master port 7 on the associated slave port. these bits are initialized by hardware reset. the reset value is 111 000this master has the highest priority when accessing the slave port. 111this master has the lowest priority when accessing the slave port. bit 4 master priority register reserved - this bit is reserved for future expansion. it is read as zero and should be written with zero for upward compatibility. na table 15-6. register terms (continued) term description
crossbar switch (xbar) 15-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 mstr_6 master 6 priority - these bits set the arbitration priority for master port 6 on the associated slave port. these bits are initialized by hardware reset. the reset value is 110 000this master has the highest priority when accessing the slave port. 111this master has the lowest priority when accessing the slave port. bit 8 master priority register reserved - this bit is reserved for future expansion. it is read as zero and should be written with zero for upward compatibility. na mstr_5 master 5 priority - these bits set the arbitration priority for master port 5 on the associated slave port. these bits are initialized by hardware reset. the reset value is 101 000this master has the highest priority when accessing the slave port. 111this master has the lowest priority when accessing the slave port. bit 12 master priority register reserved - this bit is reserved for future expansion. it is read as zero and should be written with zero for upward compatibility. na mstr_4 master 4 priority - these bits set the arbitration priority for master port 4 on the associated slave port. these bits are initialized by hardware reset. the reset value is 100 000this master has the highest priority when accessing the slave port. 111this master has the lowest priority when accessing the slave port. bit 16 master priority register reserved - this bit is reserved for future expansion. it is read as zero and should be written with zero for upward compatibility. na mstr_3 master 3 priority - these bits set the arbitration priority for master port 3 on the associated slave port. these bits are initialized by hardware reset. the reset value is 011 000this master has the highest priority when accessing the slave port. 111this master has the lowest priority when accessing the slave port. bit 20 master priority register reserved - this bit is reserved for future expansion. it is read as zero and should be written with zero for upward compatibility. na mstr_2 master 2 priority - these bits set the arbitration priority for master port 2 on the associated slave port. these bits are initialized by hardware reset. the reset value is 010 000this master has the highest priority when accessing the slave port. 111this master has the lowest priority when accessing the slave port. bit 24 master priority register reserved - this bit is reserved for future expansion. it is read as zero and should be written with zero for upward compatibility. na mstr_1 master 1 priority - these bits set the arbitration priority for master port 1 on the associated slave port. these bits are initialized by hardware reset. the reset value is 001 000this master has the highest priority when accessing the slave port. 111this master has the lowest priority when accessing the slave port. bit 28 master priority register reserved - this bit is reserved for future expansion. it is read as zero and should be written with zero for upward compatibility. na table 15-7. master priority register descriptions (continued) name description settings
crossbar switch (xbar) freescale semiconductor 15-9 pxs20 microcontroller reference manual, rev. 1 the master priority register can onl y be accessed in supervisor mode with 32-bit accesses. once the ro (read only) bit has been set in the slave general pur pose control register the ma ster priority register can only be read from, attempts to write to it will have no effect on the mpr and resu lt in an error response. note no two available master ports may be programmed with the same priority level. attempts to program two or mo re available masters with the same priority level will result in an er ror response and the mpr will not be updated. 15.3.2.2 slave general purpose control register the slave general purpose control register (sgpcr) controls several features of each slave port. the read only (ro) bit will prevent any registers a ssociated with this slave port from being written to once set. this bit may be written with 0 as many times as the user desire s, but once it is wr itten to a 1 only a reset condition will allow it to be written again. the halt low priority (hlp) bit will set the priority of the max_halt_request input to the lowest possible priority for initial arbitration of the slave ports. by default it is the highest priority. se tting this bit will not effect the max_halt_request from attaining highest priority on ce it has control of the slave ports. the pctl bits determine how the slave port will park when no master is actively making a request. the available options are to park on the master defined by the park bits, park on the last master to use the slave port, or go into a low power pa rk mode which will force all the ou tputs of the slave port to inactive states when no master is requesting an access. the lo w power park feature can re sult in an overall power savings if a the slave port is not saturated; however, it will force an extra clock of latency whenever any master tries to access it when it is not in us e because it will not be parked on any master. the park bits determine which master the slave will park on when no master is making an active request and the max_halt_request input is negated. please use caution to onl y select master ports that are actually present in the design. if the user programs the park bits to a master not present in the current design implementation undefined behavior will result. mstr_0 master 0 priority - these bits set the arbitration priority for master port 0 on the associated slave port. these bits are initialized by hardware reset. the reset value is 000 000this master has the highest priority when accessing the slave port. 111this master has the lowest priority when accessing the slave port. table 15-7. master priority register descriptions (continued) name description settings
crossbar switch (xbar) 15-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 note: for n = 0 to 7 figure 15-3. slave general purpose control register n sgpcrn slave general purpose control register n addr $base + 0x010 + n*100 wait state: 0 access: s 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ro hlp hpe 7 hpe 6 hpe 5 hpe 4 hpe 3 hpe 2 hpe 1 hpe 0 type: rw rw r r r r r r rw rw rw rw rw rw rw rw reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 note: once the ro bit is written to a 1, only hardware reset will return it to a 0. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 arb pctl pa r k type: r r r r r r rw rw r r rw rw r rw rw rw reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 note: - - - - - - - - - - - - - - - - table 15-8. slave general purpose control register descriptions name description setting ro read only - this bit is used to force all of a slave port?s registers to be read only. once written to 1 it can only be cleared by hardware reset. this bit is initialized by hardware reset. the reset value is 0 0 all this slave port?s registers can be written. 1 all this slave port?s registers are read only and cannot be written (attempted writes have no effect and result in an error response). hlp halt low priority - this bit is used to set the initial arbitration priority of the max_halt_request input. this bit is initialized by hardware reset. the reset value is 0 0 the max_halt_request input has the highest priority for arbitration on this slave port 1 the max_halt_request input has the lowest initial priority for arbitration on this slave port. bits 2?7 slave general purpose control register reserved - these bits are reserved for future expansion. they read as zero and should be written with zero for upward compatibility. na hpex high priority enable - these bits are used to enable the mx_high_priority inputs for the respective master. these bits are initialized by hardware reset. the reset value is 0 0 the mx_high_priority input is disabled on this slave port 1 the mx_high_priority input is enabled on this slave port. bits 16?21 slave general purpose control register reserved - these bits are reserved for future expansion. they are read as zero and should be written with zero for upward compatibility. na
crossbar switch (xbar) freescale semiconductor 15-11 pxs20 microcontroller reference manual, rev. 1 the sgpcr can only be accessed in supervisor mode with 32-bit acce sses. once the ro (read only) bit has been set in the sgpcr the sgpcr can only be read, attempts to write to it will have no effect on the sgpcr and result in an error response. 15.3.2.3 master general purpose control register the master general purpose contro l register (mgpcr) presently c ontrols only whether or not the master?s undefined length burst accesses will be allowed to complete uninterrupted or whether they can be broken by requests from hi gher priority masters. the aulb (arbitrate on undefined le ngth bursts) bit field determines whether (and when) or not the xbar will arbitrate away the slav e port the master owns when the ma ster is performing undefined length burst accesses. if the user has configured the xbar to have less than eight master port s only the registers associated with the remaining master ports will be present, all other registers will become reserved locations in memory. arb arbitration mode - these bits are used to select the arbitration policy for the slave port. these bits are initialized by hardware reset. the reset value is 00 00 fixed priority. 01 round robin (rotating) priority. 10 reserved 11 reserved bits 24?25 slave general purpose control register reserved - these bits are reserved for future expansion. they are read as zero and should be written with zero for upward compatibility. na pctl parking control - these bits determine the parking control used by this slave port. these bits are initialized by hardware reset. the reset value is 00. 00 when no master is making a request the arbiter will park the slave port on the master port defined by the park bit field. 01 when no master is making a request the arbiter will park the slave port on the last master to be in control of the slave port. 10 when no master is making a request the arbiter will park the slave port on no master and will drive all outputs to a constant safe state. 11 reserved bit 28 slave general purpose control register reserved - this bit is reserved for future expansion. it is read as zero and should be written with zero for upward compatibility. na pa r k park - these bits are used to determine which master port this slave port parks on when no masters are actively making requests and the pctl bits are set to 00. these bits are initialized by hardware reset. the reset value is 000 000park on master port 0 001park on master port 1 010park on master port 2 011park on master port 3 100park on master port 4 101park on master port 5 110park on master port 6 111park on master port 7 table 15-8. slave general purpose contro l register descriptions (continued) name description setting
crossbar switch (xbar) 15-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 note: for n = 0 to 7 figure 15-4. master general purpose control register n the mgpcr can only be accessed in supervisor mode with 32-bit accesses. 15.3.3 coherency since the content of the regi sters has a real time effect on the operation of the xbar it is important for the user to understand that any register m odifications take effect as soon as the register is wr itten. the values of the registers do not track with slave port related ahb accesses but instead track only with ip bus accesses. mgpcrn master general purpose control register n addr $base + 0x800 + n*100 wait state: 0 access: s 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 type: r r r r r r r r r r r r r r r r reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 note: - - - - - - - - - - - - - - - - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 aulb type: r r r r r r r r r r r r r rw rw rw reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 note: - - - - - - - - - - - - - - - - table 15-9. master general purpose control register descriptions name description setting bits 0?28 master general purpose control register reserved - these bits are reserved for future expansion. they read as zero and should be written with zero for upwa rd compatibility. na aulb arbitrate on undefined length bursts - these bits are used to select the arbitration policy during undefined length bursts by this master. these bits are initialized by hardware reset. the reset value is 000 000no arbitration will be allowed during an undefined length burst. 001arbitration will be allowed at any time during an undefined length burst. 010arbitration will be allowed after four beats of an undefined length burst. 011arbitration will be allowed after eight beats of an undefined length burst. 100arbitration will be allowed after 16 beats of an undefined length burst. 101reserved 110reserved 111reserved
crossbar switch (xbar) freescale semiconductor 15-13 pxs20 microcontroller reference manual, rev. 1 the exception to this rule are the aulb bits in the mgpcr. these update of these bits is only recognized when the master on that master port runs an idle cycle, even though the ip bus cycle to write them will have long since terminated successful ly. if the aulb bits in the mgp cr are written in between two burst accesses the new aulb encodings will not take effect until an idle cycle has been initiated by the master on that master port. 15.4 function this section describes in more deta il the functionality of the xbar. 15.4.1 arbitration the xbar supports two arbi tration schemes; a simple fixed-priori ty comparison algorithm, and a simple round-robin fairness algorithm. the arbitration scheme is independe ntly programmable for each slave port. 15.4.1.1 arbitration during undefined length bursts arbitration points during an undefined length burst are defined by the current master?s mgpcr aulb field setting. when a defi ned length is imposed on th e burst via the aulb bits the undefined length burst will be treated as a single or series of si ngle back to back fixed length burst accesses. example: a master runs an undefine d length burst and the aulb bits in the mgpcr indicate arbitration will occur after the fourth beat of the burst. the master runs two sequential beats and then starts what will be an 12 beat undefined length burst access to a new address within the same slave port region as the previous access. the xbar will not allow an arbitration point until the fourth ove rall access (second beat of the second burst). at that point all remaining accesse s will be open for arbitration until the master loses control of the slave port. assume the master loses control of the slave port after the fifth beat of the second burst. once the master regains control of the slave port no ar bitration point will be available unt il after the master has run four more beats of its burst. after the fourth beat of the (now continued) burst (ninth beat of the second burst from the master?s perspective) is taken all beats of the burst will once again be open for arbitration until the master loses control of the slave port. assume the master again loses control of the slave port on the fifth beat of the th ird (now continued) burst (10th beat of the second bur st from the master?s perspective). once the master regains control of the slave port it will be allowed to complete its final two beats of its burst wi thout facing arbitration. note that fixed length bur st accesses are not affected by the aulb bits. all fixed length burst accesses lock out arbitration until the last beat of the fixed length burst.
crossbar switch (xbar) 15-14 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 15.4.1.2 fixed priority operation when operating in fixed-priority mode , each master is assi gned a unique priority le vel in the mpr (master priority register). if two masters both request access to a slave port th e master with the highest priority in the selected priority register will gain control over the slave port. any time a master makes a re quest to a slave port the sl ave port checks to see if the new requesting master?s priority level is higher than that of the master that currently has contro l over the slave port (unless the slave port is in a parked state). the slave port does an arbitr ation check at every clock edge to ensure that the proper master (if any) has control of the slave port. if the new requesting master?s priority level is higher than th at of the master that currently has control of the slave port the new requesting master will be granted cont rol over the slave port at the next clock edge. the exception to this rule is if the master that cu rrently has control over the slave port is running a fixed length burst transfer or a locked transfer. in this case the new re questing master will ha ve to wait until the end of the burst transfer or locked transfer before it will be gr anted control of the slave port. if the master is running an undefined length burst tr ansfer the new requesti ng master must wait unt il an arbitration point for the undefined length burst transfer before it will be granted control of the sl ave port. arbitration points for an undefined length burst are defi ned in the mgpcr for each master. if the new requesting master?s priority level is lower than that of the ma ster that currently has control of the slave port the new requesting master will be forced to wait until th e master that currently has control of the slave port either runs an idle cycle or runs a non idle cycle to a location other than the current slave port. 15.4.1.3 round-robin priority operation when operating in round-robin mode, each master is assigned a relative priority based on the master number.this relative priority is compared to the id of the last master to perform a transfer on the slave bus. the highest priority requesting mast er will become owner of the slav e bus as the next transfer boundary (accounting for locked and fi xed-length burst transfers). priority is based on how far ahead the id of the requesting master is to the id of the last mast er (id is defined by master port number, not the hmaster field). once granted access to a slave port, a master may perf orm as many transfers as de sired to that port until another master makes a request to the same slave port. the next master in line wi ll be granted access to the slave port at the next assertion of sx_hready , or possibly on the next clock cycle if the current master has no pending access request. as an example of arbitration in round-robin mode, assume the xbar is implemented with master ports 0, 1, 4 and 5. if the last master of the slave port was master 1, and ma ster 0, 4 and 5 make simultaneous requests, they will be serviced in the order 4, 5 and then 0. parking may still be used in a round-robin mode, but will not affect the r ound-robin pointer unless the parked master actually perf orms a transfer. handoff will occur to the ne xt master in line after one cycle of arbitration. if the slave port is put into low power park mode the round-r obin pointer will be reset to point at master port 0, giving it the highest priority.
crossbar switch (xbar) freescale semiconductor 15-15 pxs20 microcontroller reference manual, rev. 1 each master port has an mx_high_priority input which can be enabled by wr iting the correct data to the sgpcr. if a master?s mx_high_priority input is enabled for a slav e port programmed for round-robin mode, that master can force the slave port into fixed priority mode by asserting its mx_high_priority input while making a request to th at particular slave port. while that (or any enabled) master?s mx_high_priority input is asserted while making an access attempt to that pa rticular slave port, the slave port will remain in fixed priority mode. once that (or any enabled) master?s mx_high_priority input is negated, or the master no l onger attempts to make accesse s to that particular slave port, the slave port will revert back to round-robin priority mode and the pointer will be set on the last master to access the slave port. 15.4.2 priority assignment each master port needs to be assigned a unique 3-bit pr iority level. if an atte mpt is made to program multiple master ports with the same priority level within a regist er (mpr) the xbar w ill respond with an error and the register s will not be updated. 15.4.2.1 context switching the xbar has a hardware input per slave port ( sx_ampr_sel ) which is used to sele ct which registers the master priority levels and general purpos e control bits will be taken from. when sx_ampr_sel is 0 the mpr and sgpcr will be selected. this hardware input is usef ul for context switchi ng so the user does not have to rewrite the mpr or sgpcr if a particular slave port would te mporarily benefit from modifying the master priority levels or functi ons affected by the bits in the sgpcr. 15.4.2.2 priority elevation the xbar has a hardware input per master port ( mx_high_priority ) which is used to temporarily elevate the master?s priority level on all slave ports. when the master?s mx_high_priority input is asserted the master port will automatically have higher priority than all other ma ster ports that do not have their mx_high_priority input asserted regardless of the priority levels program med in the mpr and ampr. if multiple master ports have their mx_high_priority input asserted they will ha ve higher priority than all master ports which do not have their mx_high_priority inputs asserted. the mpr priority level (dependent on the state of sx_ampr_sel ) will determine which ma ster port that has its mx_high_priority input asserted has the highest prior ity on a slave port by slave port basis. this functionality is useful because it allows the user to automatically el evate a master port?s priority level throughout the xbar in order to quickly perform temporary tasks such as servicing interrupts. please note that the hpex bits must be set in the sgpcr in the slave port in order for the mx_high_priority inputs to be received by the slave port. 15.4.3 master port functionality 15.4.3.1 general each master port consists of two de coders, a capture unit, a register sl ice, a mux and a small state machine.
crossbar switch (xbar) 15-16 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 the first decoder is used to decode the mx_hsel_slv and control signals coming directly from the master, telling the state machine where the mast er?s next access will be and if it is in fact a legal access. the second decoder receives its input from the capture unit, so it may be looking di rectly at the signals coming from the master or it may be looking at captured signals coming from the master, depe nding entirely on the state of the targeted slave port. the second decoder is then used to generate the acces s requests that go to the slave ports. the capture unit is used to capture the address and control information co ming from the master in the event that the targeted slave port cannot immediately service the master. the capture unit is controlled by outputs from the state machine which tell it to either pass through the original master signals or the captured signals. the register slice contains the registers associated with the specific master port. the registers have a quasi-ip bus interface at this level for reads and writes and the outputs fe ed directly into the state machine. the mux is used simply to select which slave?s read da ta is sent back to the ma ster. the mux is controlled by the state machine. the state machine controls all aspe cts of the master port. it knows wh ich slave port the master wants to make a request to and controls when that request is made. it also has knowledge of each slave port, knowing whether or not the slave port is ready to ac cept an access from the ma ster port. this will determine whether or not the master may immediately have its request taken by the slave port or whether the master port will have to capture the master?s request and queue it at the slave port boundary. 15.4.3.2 master port decoders the decoders are very simple as they ensure an access request is allowed to be made and that the slave port targeted is actually present in th e design. the decoders feeding the st ate machine are always enabled. the decoders that select the slave are enabled only when the master port controlli ng state machine wants to make a request to a slave port. this is necessary so th at if a master port is making an access to a slave port and is being wait stated, and its next access is to a different slave port, the request to the second slave port can be held off until the access to the first slave port is terminated. the decoders also output a ?hole de code? or illegal access signal whic h tells the state machine that the master is trying to access a slave port that does not exist. 15.4.3.3 master port capture unit the capture unit simply capt ures the state of the mast er?s address and control si gnals if the xbar cannot immediately pass the master?s request through to the proper slave port. the capture unit consists of a set of flops and a mux which selects either the asynchr onous path from address a nd control or the flopped (captured) address a nd control information. 15.4.3.4 master port registers the registers in the master port are only those registers as sociated with this particul ar master port. the read and write interface for the registers is a quasi-ip bus interface. it is not a full ip bus interface at this level because not all the ip bus signals ar e routed this deep in the design.
crossbar switch (xbar) freescale semiconductor 15-17 pxs20 microcontroller reference manual, rev. 1 there is a register control block at the same level of the master port and slav e port instantiations in the xbar. this control block ensures th at all accesses are 32-bit supervis or accesses before passing them on to the master ports. the register outputs are connected directly to the state machine. 15.4.3.5 master port state machine 15.4.3.5.1 master port state machine states the master side state machine?s main function is to monitor the activities of the master port. the state machine has six states: busy , idle , waiting , stalled , steady state , first cycle error response and second cycle error response . the busy state is used when the master runs a busy cy cle to the master port. the master port maintains its request to the slave port if it cu rrently owns the slave port; however, if it loses control of the slave port it will no longer maintain its request. if the master port loses control of the slave port it will not be allowed to make another request to the slave por t until it runs a nseq or seq cycle. the idle state is used when the master runs a valid idle cycle to the ma ster port. the master port makes no requests to the slave ports (disables the slav e port decoder) and terminates the idle cycle. the waiting state is used when the hsel signal is negated to the master port, indicating the master is running valid cycles to a local slav e other than the xbar. in this cas e the max disables the slave port decoder and holds hresp and hready negated. the stalled state is used when the master makes a request to a slave port th at is not immediately ready to receive the request. in this case the state machine will direct the capture unit to send out the captured address and control signals and will enable the sl ave port decoder to indicate a pending request to the appropriate slave port. the steady state state is used when the master port and sl ave port are in fully asynchronous mode, making the xbar completely transparent in the access. the state machine selects the appropriate slave?s hresp, hready and hrdata to pass back to the master. the first cycle error response and second cycle error response states are self explanatory. the xbar will respond with an error response to the master if the master tries to access an unimplemented memory location through the xbar (that is, a slave port that does not exist). 15.4.3.5.2 master port stat e machine slave swapping the design of the master side state machine is fairly strai ghtforward. the one real de cision to be made is how to handle the master moving from one slave por t access to another slave port access. the approach that was taken is to minimize or eliminate when pos sible any ?bubbles? that woul d be inserted into the access due to switching slave ports. the state machine will not allow th e master to request access to anot her slave port until the current access being made is terminated. this prevents a single master from owning two slave ports at the same time (the slave port it is currently accessing and the slave port it wishes to access next).
crossbar switch (xbar) 15-18 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 the state machine also maintains watch on the slave po rt the master is accessing as well as the slave port the master wishes to switch to. if the new slave port is parked on the mast er then the master will be able to make the switch without incurri ng any delays. the termination of the current access will also act as the launch of the new access on the new sl ave port. if the new slave port is not parked on the master then the master will incur a minimum one clock delay befo re it can launch its acce ss on the new slave port. this is the same for switching from the busy, idle or waiting state to actively acces sing a slave port. if the slave port is parked on the master the state machine will go to the steady state state and the access will begin immediately. if the slave port is not parked on the ma ster (serving a nother master, parked on another master or in low power park mode) then the state machine will transition to the stalled state and at least a one clock penalty will be paid. 15.4.4 slave port functionality 15.4.4.1 general each slave port consists of a register sl ice, a bank of muxes and a state machine. the register slice contains the registers associated with the specific slave port. the registers have a quasi-ip bus interface at this level for reads and writes and the outputs fe ed directly into the state machine. the muxes are a series of 8 to 1 muxe s that take in all the address, cont rol and write data information from each of the master ports and then pass the correct master?s signals to the slave port. the state machine controls all the muxes. the state machine is where the main slave port arbitrati on occurs, it decides which master is in control of the slave port and which master will be in c ontrol of the slave port in the next bus cycle. 15.4.4.2 slave port muxes the xbar instantiates many 8 to 1 muxes, one for each master-to-slav e signal in fact. all the muxes are designed in an and - or fashion, so that if no master is selected the output of the muxes will be zero. (this is an important feature for low power park mode.) the muxes also have an override signal which is used by the slave port to asynchronously force idle cycles onto the slave bus. when the state machine forces an idle cycle it zeros out htrans and hmastlock , making sure the slave bus sees a va lid idle cycle being run by the xbar. the enable to the mux controlling htrans also contains an a dditional control signal from the state machine so that a nseq transaction can be forced. this is done any time the slave por t switches masters to ensure that no idle-seq, busy-seq or ns eq-seq transactions are seen on the slave port when they shouldn?t be. if the state machine indicates to run both an idle and an nseq cycl e, the idle directive will have priority. note idle-seq is in fact an illegal acce ss, but a possible sc enario given the multi-master environment in the xbar unless corrected by the xbar.
crossbar switch (xbar) freescale semiconductor 15-19 pxs20 microcontroller reference manual, rev. 1 15.4.4.3 slave port registers there is a register control block at the same level of the master port and slav e port instantiations in the xbar. this control block ensures th at all accesses are 32-bit supervis or accesses before passing them on to the master and slave ports. the registers in the slave port are onl y those registers associated with th is particular slave port. the read and write interface for the registers is a quasi-ip bus interface. it is not a full ip bus interface at this level because not all the ip bus signals ar e routed this deep in the design. the register outputs are connected direct ly to the slave state machine with the sx_ampr_sel input determining which priority register values, halt priority value, arbitr ation algorithm an d parking control bits are passed to the state machine. the registers ca n be read from an unlimited number of times. the registers can only be written to as l ong as the ro bit is writte n to 0 in the sgpcr, onc e it is written to a 1 only a hardware reset will allow th e registers to be written again. 15.4.4.4 slave port state machine 15.4.4.4.1 slave port state machine states at the heart of the slave port is the state machine. th e state machine is simplicity itself, requiring only four states - steady state , transition state, tr ansition hold state and hold state . either the slave port is owned by the same master it was in the last clock cycle (eith er by active use or by parki ng), it is transitioning to a new master (either for active use or parking), it is transitioning to a new master during wait states or it is being held on the same master pe nding a transition to a new master. 15.4.4.4.2 slave port stat e machine arbitration the real work in the state machine is determining which master port will be in cont rol of the slave port in the next clock cycle, the arbitration. each master is programmed with a fixed 3 bit priority level. a fourth priority bit is derived from the mx_high_priority inputs on the master ports , effectively making each master?s priority level a 4 bit field with mx_high_priority being the msb. the xbar uses these bits in determining priority levels when programmed for fixed priority mode of operation or wh en one of the enabled mx_high_priority inputs is asserted. arbitration always occurs on a clock edge, but only occurs on edges when a change in mastership will not violate ahb-lite protocols. valid arbitrations points incl ude any clock cycle in which sx_hready is asserted (provide the master is not performing a burst or locked cycle) and any wait state in which the master owning the bus indicates a tr ansfer type of idle (provided the master is not performing a locked cycle). since arbitration can occur on every clock cycle the slave port masks off all master requests if the current master is performing a locked transfer or a protec ted burst transfer, guaranteei ng that no matter how low its priority level it will be allowed to finish its locked or protected portion of a burst sequence. 15.4.4.4.3 slave port stat e machine master handoff the only times the slave port will switch masters when programmed for fixed priority mode of operation is when a higher priority master make s a request or when the current mast er is the highest priority and it
crossbar switch (xbar) 15-20 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 gives up the slave port by either running and idle cycle to the slave port or r unning a valid access to a location other than the slave port. if the current master loses control of the slave port because a higher prio rity master takes it away, the slave port will not incur any wasted cycles. the current mast er has its current cycle terminated by the slave port at the same time the new master?s address and control information ar e recognized by the slave port. this appears as a seamless transition on the slave port. if the current master is being wait-stated when the hi gher priority master makes it s request, then the current master will be allowed to make one more transaction on the slave bus before givi ng it up to the new master. figure 15-5 illustrates the effect of a higher priority mast er taking control of the bus when the slave port is programmed for a fixed pr iority mode of operation. figure 15-5. low to high priority mastership change if the current master is the highest priority master and it gives up the slave port by running an idle cycle or by running a valid cycle to another location other th an the slave port the next highest priority master will gain control of the slave port. if the current acce ss incurs any wait states then the transition will be seamless and no bandwidth will be lost; however, if the current transaction is terminated without wait states then one idle cycle will be forced onto the sl ave bus by the xbar before the new master will be able to take control of th e slave port. if no other master is requestin g the bus then idle cycles will be run by the xbar but no bandwidth will truly be lost since no master is making a request. figure 15-6 illustrates the effect of a higher priority master giving up control of the bus. 123456789 master 5 master 5 master 4 master 3 master 2 master 3 master 4 none xbar master 5 master 5 master 2 master 3 master 4 xbar idle nseq nseq nseq nseq nseq idle hclk m2 request m3 request m4 request m5 request htrans hready requester priority highest address/cntrl owner 10
crossbar switch (xbar) freescale semiconductor 15-21 pxs20 microcontroller reference manual, rev. 1 figure 15-6. high to low priority mastership change when the slave port is programmed for round-robin mode of arbitration then th e slave port will switch masters any time there is more than one master acti vely making a request to th e slave port. this will happen because any master other than the one which pr esently owns the bus will be considered to have higher priority. figure 15-7 shows an example of round-robin mode of operation. figure 15-7. round-robin mastership change 123456789 master 0 master 2 none master 4 none xbar master 0 xbar master 2 xbar master 4 xbar idle nseq idle nseq idle nseq idle hclk m0 request m2 request m4 request highest address/cntrl htrans hready priority requester owner 12345678910 master 1 master 4 master 0 master 4 master 5 none xbar master 1 master 4 master 5 master 0 master 4 master 5 xbar idle nseq nseq nseq nseq nseq nseq idle hclk m0 request m1 request m4 request m5 request highest address/cntrl htrans hready priority requester owner master 5
crossbar switch (xbar) 15-22 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 15.4.4.4.4 slave port state machine parking if no master is currently making a request to the slave port then the slave port will be parked. it will park in one of four places, dictated by the pctl and park bits in the gpcr or agpcr (depending on the state of the sx_ampr_sel ) and the locked state of the last master to access it. if the last master to access the slave port ran a lo cked cycle and continues to r un locked cycles even after leaving the slave port the slav e port will park on that mast er without regard to the bit settings in the gpcr and without regard to pending request s from other masters. this is done so a master can run a locked transfer to the slave port, leave it, and return to it and be guaranteed th at no other master has had access to it (provided the master maintains all transfers are lock ed transfers). if locking is not an issue for parking the gpcr bits will dict ate the parking method. if the pctl bits are set for ?low power park? mode th en the slave port will ente r low power park mode. it will not recognize any master as bein g in control of it and it will not se lect any master?s signals to pass through to the slave bus. in this case al l slave bus activity will effectivel y halt because all slave bus signals being driven from the xbar will be 0. this of course can save quite a bit of power if the slave port will not be in use for some time. the down side is that wh en a master does make a request to the slave port it will be delayed by one cl ock since it will have to arbitrate to acquire ownership of the slave port. if the pctl bits are set to ?park on last? mode then the slave port will park on the last master to access it, passing all that masters signals through to the slave bus. the xbar will asynchronously force htrans[1:0] , hmaster[3:0] , hburst[2:0] and hmastlock to 0 for all access that the master does not run to the slave port. when that master access the slave port again it will not pay any ar bitration penalty; however, if any other master wishes to access the slave por t a one clock arbitration penalty will be imposed. if the pctl bits are set to ?use park/apark? m ode then the slave port will park on the master designated by the park bits. the beha vior here is the same as for the ?park on last? mode with the exception that a specific master will be parked on instead of the last master to a ccess the slave port. if the master designated by the park bits tries to access the slave port it wi ll not pay an arbitration penalty while any other master will pay a one clock penalty. figure 15-8 illustrates parking on a specific master.
crossbar switch (xbar) freescale semiconductor 15-23 pxs20 microcontroller reference manual, rev. 1 figure 15-8. parking on a specific master figure 15-9 illustrates parking on the last master. note that in cycle 6 s imultaneous requests are made by master 2 and master 4. although master 2 has higher priority, the slave bus is parked on mast er 4 so master 4?s access will be taken first. the slave port parks on master 2 once it ha s given control to master 2. this same situation can occur when parking on a specific master as well. figure 15-9. parking on last master 123456789 master 2 master 0 none master 2 none master 4 none master 2 none xbar master 0 master 2 xbar xbar master 4 master 2 xbar idle nseq nseq idle idle nseq nseq idle hclk m0 request m2 request m4 request park highest address/cntrl htrans hready priority requester owner 123456789 last master master 0 master 4 master 2 master 0 none master 4 none master 2 none xbar master 0 xbar master 4 xbar master 4 master 2 xbar idle nseq idle nseq idle nseq nseq idle hclk m0 request m2 request m4 request park highest address/cntrl htrans hready priority requester owner
crossbar switch (xbar) 15-24 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 15.4.4.4.5 slave port st ate machine halt mode if the max_halt_request input is asserted the slave port will ev entually halt all slave bus activity and go into halt mode, which is almost iden tical to low power park mode. the hlp bit in the gpcr controls the priority level of the max_halt_request in the arbitration algorithm. if the hlp bit is cleared then the max_halt_request will have the highest priority of any master and will gain control of the slave port at the next arbitration point (most likely the next bus cy cle, unless the current mast er is running a locked or fixed length burst transf er). if the hlp bit is set then the slave port will wait until no masters are actively making requests before moving to halt mode. regardless of the state of the hlp bit, once the sl ave port has gone into halt mode as a result of max_halt_request being asserted, it will re main in halt mode until max_halt_request is negated, regardless of the priority level of any masters that may make requests. in halt mode no master is selected to own the slave port so all the out puts of the slave port are set to 0. 15.5 initialization/application information no initialization is required by or for the xbar. hardwa re reset ensures all the register bits used by the xbar are properl y initialized. 15.6 interface this section provides information on the xbar interface. 15.6.1 overview the main goal of the xbar is to increase overall system performance by allowing multiple masters to communicate in parallel with multiple slaves. in order to maximize da ta throughput it is essential to keep arbitration delays to a minimum. this section examines data throughput from the point of view of mast ers and slaves, detailing when the xbar will stall the masters or insert bubbles on the slave side. 15.6.2 master ports master accesses will receive one of four responses from the xbar. they will either be ignored, terminated, taken, stalled or responded to with an error. 15.6.2.1 ignored accesses a master access will be ignored if the hsel input of the xbar is not asse rted. the xbar will respond to idle transfers when the hsel input is asserted but will not allo w the access to pass through the xbar. 15.6.2.2 termina ted accesses a master access will be terminated if the hsel input of the xbar is asserted and the transfer type is idle. the xbar will terminated the access and it wi ll not be allowed to pass through the xbar.
crossbar switch (xbar) freescale semiconductor 15-25 pxs20 microcontroller reference manual, rev. 1 15.6.2.3 taken accesses a master access will be taken if the hsel input of the xbar is asserted and the transfer type is non idle and the slave port to which the access decodes is either currently servicing the master or is parked on the master. in this case the xbar will be completely tr ansparent and the master?s access will be immediately seen on the slave bus and no arbi tration delays will be incurred. 15.6.2.4 stalled accesses a master access will be stalled if the hsel input of the xbar is asserted and the transfer type is non idle and the access decodes to a slave port that is busy serv ing another master, parked on another master or is in low power park mode. the xbar will indicate to the master that the address phase of the access has been taken but will then queue the access to the appropriate slave port to enter into arbitration for access to that slave port. if the slave port is currently parked on another master or is in low power park mode and no other master is requesting access to the slave port then only one clock of ar bitration will be incurre d. if the slave port is currently serving another master of a lower priority and the master ha s a higher priority than all other requesting masters then the master will gain control over the slave port as soon as the data phase of the current access is completed (burst and locked transfer s excluded). if the slave port is currently servicing another master of a hi gher priority then the master will gain c ontrol of the slave port once the other master releases control of the slave port if no other higher priority master is also waiting for the slave port. 15.6.2.5 error respons e terminated accesses a master access will be responded to with an error if the hsel input of the xbar is a sserted and the transfer type is non idle and the access decode s to a location not occupied by a sl ave port. this is the only time the xbar will respond with an erro r response. all other error respons es received by the master are the result of error responses on the slav e ports being passed through the xbar. 15.6.3 slave ports the goal of the xbar with respect to the slave ports is to keep them 100% sa turated when masters are actively making requests. in order to do this the xbar must not in sert any bubbles onto the slave bus unless absolutely necessary. there is only one instance when the xbar will force a bubble onto the slave bus when a master is actively making a request. this occurs when a higher priority master has control of the slave port and is running single clock (zero wait state) accesses while a lower pr iority master is stalled waiting for control of the slave port. when the higher priority master either leaves the slave port or runs an idle cycle to the slave port the xbar will take control of the slave bus and run a single idle cycle before giving the slave port to the lower priority master that was waiting for control of the slave port. the only other times the xbar will ha ve control of the slave port is wh en the xbar is halting or when no masters are making access requests to the slave port and the xbar is fo rced to either park the slave port on a specific master or put the sl ave port into low power park mode.
crossbar switch (xbar) 15-26 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 in most instances when the xbar has control of the slave port it will indicate idle for the transfer type, negate all control signals and indicate ownership of the slave bus via the hmaster encoding of 4?b0000. one exception to this rule is when a master running lo cked cycles has left the slave port but continues to run locked cycles. in this case the xbar will contro l the slave port and will indicate idle for the transfer type but it will not aff ect any other signals. note when a master runs a locked cycle through the xbar, the master will be guaranteed ownership of all slave por ts it accesses while running locked cycles for one cycle beyond when the ma ster finishes running locked cycles.
deserial serial peripheral interface (dspi) freescale semiconductor 16-1 pxs20 microcontroller reference manual, rev. 1 chapter 16 deserial serial peripheral interface (dspi) 16.1 introduction 16.1.1 overview the deserial serial peripheral interface (dspi) module provides a synchronous serial bus for communication between an soc and an external peripheral device. the pxs20 device has three dspi modules, referred to as dspi_0, dspi_1, and dspi_2. the dspi modules interact wi th the ctu as described in section 13.4.1, interaction with other peripherals. figure 16-1 is a block diagram of the dspi module.
deserial serial peripheral interface (dspi) 16-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 16-1. dspi block diagram 16.1.2 features the dspi provides these features: ? full-duplex, synchr onous transfers ? master or slave operation ? data streaming operation in the slave mode with continuous slave selection ? buffered transmit operation usi ng the tx fifo with 5 entries ? buffered receive operation using the rx fifo with 5 entries ? programmable transfer attributes on a per-frame basis: ? 4 transfer attribute registers ? serial clock with programmable polarity and phase baud rate, delay & transfer control sout sin pcs[x]/ss /pcss shift register spi sck spi 32 32 8 cmd data dma and interrupt control data tx fifo rx fifo edma intc dspi_pushr dspi_popr
deserial serial peripheral interface (dspi) freescale semiconductor 16-3 pxs20 microcontroller reference manual, rev. 1 ? various programmable delays ? programmable serial frame size of 4 to 16 bits, expa ndable by software control ? programmable master bit rates ? end-of-transmission interrupt flag ? programmable transfer baud rate ? as many as 8 chip select lines availabl e, depending on package and pin multiplexing ? 4 clock and transfer attributes registers ? chip select strobe available as alternate functi on on one of the chip select pins for de-glitching ? fifos for buffering as many as 5 tran sfers on the transmit and receive side ? queueing operation possible through use of the edma ? general-purpose i/o functionalit y on pins when not used for spi 16.1.3 dspi configurations the dspi module on this device operates only in the spi configuration. 16.1.3.1 spi configuration the spi configuration allows the dspi to send and recei ve serial data. this conf iguration allows the dspi to operate as a basic spi block with internal fifo s supporting external queues operation. transmit data and received data re side in separate fifos. the host cpu or a dma cont roller read the received data from the receive fifo and write transm it data to the transmit fifo. for queued operations the spi queues can reside in sy stem ram, external to the dspi. data transfers between the queues and the dspi fifos are accomplished by a dma controller or host cpu. figure 16-2 shows a system example with dma, dspi and external queues in system ram. figure 16-2. dspi with queues and dma system ram dspi dma controller tx queue rx fifo tx fifo shift register data data addr/ctrl rx queue data data addr/ctrl done req
deserial serial peripheral interface (dspi) 16-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 16.1.4 modes of operation the dspi has five modes of operation that can be divi ded into two categories; ? module-specific modes: ? master mode ? slave mode ? module disable mode ? soc-specific modes: ? external stop mode ? debug mode the dspi enters module-specific modes when the hos t writes a dspi register. the soc-specific modes are controlled by signals, external to the dspi. th e soc-specific modes are modes that the entire soc may enter in parallel to the dspi block-specific modes. 16.1.4.1 master mode master mode allows the dspi to initiate and control serial communi cation. in this mode, the sck signal and the pcs[ x ] signals are controlled by the dspi and configured as outputs. 16.1.4.2 slave mode the slave mode allows the dspi to communicate with spi bus masters. in this mode the dspi responds to externally controlled serial tran sfers. the sck signa l and the pcs[0]/ss signal are configured as inputs and driven by a spi bus master. note if the dspi operates in slave mode and the external master has selected this module with the ss signal, stop mode can't be acknowledged until the module is deselected. 16.1.4.3 module disable mode the module disable mode can be used for soc powe r management. the clock to the non-memory mapped logic in the dspi can be stopped while in the module disable mode. 16.1.4.4 external stop mode the external stop mode is used for soc power management. the dspi supports the peripheral bus stop mode mechanism. when a request is made to ente r external stop mode, the dspi block acknowledges the request and completes the transfer in progress. when the dspi reache s the frame boundary it signals that the system clock to the dspi module may be shut off. no register access is possible in this mode.
deserial serial peripheral interface (dspi) freescale semiconductor 16-5 pxs20 microcontroller reference manual, rev. 1 16.1.4.5 debug mode the debug mode is used for system development and debugging. in this mode, you can read the last data from the fifo without any changes. the dspi_mcr[frz] bit controls dspi behavior in the debug mode. if the bit is set, the dspi stops all serial transfers, when the soc in the debug m ode. if the bit is cleared the soc debug mode has no effect on the dspi. the distinguishing feature of debug m ode is that if the tx/rx fifos ha ve valid entries, the module will still not initiate any serial transf er and all registers can be accessed. 16.2 external signal description table 16-1 lists the dspi signals. see section 3.4, pin muxing , for details of what signals are available on the dspi modules on this chip. 16.2.1 pcs[0]/ss ? peripheral chip select/slave select in master mode, the pcs[0] signal is a peripheral ch ip select output that sel ects which slave device the current transmissi on is intended for. in slave mode, the active low ss signal is a slave select input signal that allows a spi master to select the dspi as the target for transmission. 16.2.2 pcs[1] - pcs[3] ? pe ripheral chip selects 1?3 in master mode, pcs[1] - pcs[3] are peripheral chip sel ect output signals. in slave mode these signals are not used. 16.2.3 pcs[4] ? peripheral chip select 4 pcs[4] is a peripheral chip select output signal. table 16-1. signal properties name i/o type function master mode slave mode pcs[0]/ss output / input peripheral chip select 0 slave select pcs[1] - pcs[3] output peripheral chip select 1 - 3 unused pcs[4] output peripheral chip select 4 unused pcs[5]/pcss output peripheral chip select 5 / peripheral chip select strobe unused pcs[6] - pcs[7] output peripheral chip select 6- 7 unused sin input serial data in serial data in sout output serial data out serial data out sck output / input serial clock (output) serial clock (input)
deserial serial peripheral interface (dspi) 16-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 16.2.4 pcs[5]/pcss ? peripheral chip select 5/peripheral chip select strobe pcs[5] is a peripheral ch ip select output signal. when the dspi is in master mode and the dspi_mcr[pcsse] bit is cleared, this signal selects which slave device the current transfer is intended for. when the dspi is in master mode and the dspi_mcr[pcsse] bit is set, the pcss signal acts as a strobe to external peripheral chip select demultiplexer, which decodes the pcs[ 0] - pcs[4] and pcs[6] - pcs[7] signals, preventing glitches on the demultiplexer outputs. this signal is not used in slave mode. 16.2.5 pcs[6] - pcs[7] ? peri pheral chip selects 6 - 7 in master mode, pcs[6] - pcs[7] are peripheral chip sel ect output signals. in slave mode these signals are not used. 16.2.6 sin ? serial input sin is a serial data input signal. 16.2.7 sout ? serial output sout is a serial data output signal. 16.2.8 sck ? serial clock sck is a serial communication clock signal. in master mode, the dspi generates the sck. in slave mode, sck is an input from an external bus master. 16.3 memory map and register definition 16.3.1 memory map register accesses to memory addresses that are reserv ed or undefined result in a transfer error. write access to the dspi_popr register al so result in a transfer error. table 16-2 shows the dspi memory map.
deserial serial peripheral interface (dspi) freescale semiconductor 16-7 pxs20 microcontroller reference manual, rev. 1 16.3.2 register descriptions 16.3.2.1 dspi module configuration register (dspi_mcr) the dspi_mcr contains bits that configure various attributes associ ated with dspi operation. the halt and mdis bits can be cha nged at any time, but only take effect on the next frame boundary. only the halt and mdis bits in the dspi_mcr are allowed to be changed, while the dspi is in the running state. table 16-2. dspi memory map address offset register name location 0x0 dspi module configuration register (dspi_mcr) on page 16-7 0x4 dspi hardware configuration register (dspi_hcr) 1 [cut2/3 only] notes: 1 the dspi_hcr register provides parametization informat ion about particular instance of the dspi module. on page 16-10 0x8 dspi transfer count register (dspi_tcr) on page 16-11 0xc?0x18 dspi clock and transfer attributes register 0 (dspi_ctar0) - dspi clock and transfer attributes register 3(dspi_ctar3) on page 16-12 0x2c dspi status register (dspi_sr) on page 16-17 0x30 dspi dma/interrupt request select and enable register (dspi_rser) on page 16-19 fifo registers 0x34 dspi push tx fifo register (dspi_pushr) on page 16-21 0x38 dspi pop rx fifo register (dspi_popr) on page 16-24 0x3c?0x4c dspi transmit fifo register 0 (dspi_txfr0) - dspi transmit fifo re gister 4 (dspi_txfr4) on page 16-24 0x7c - 0x8c dspi receive fifo register 0 (dspi_rxfr0) - dspi receive fifo register 4 (dspi_rxfr4) on page 16-25
deserial serial peripheral interface (dspi) 16-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 address: dspi_base access: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r mstr cont_scke dconf frz mtfe pcsse rooe pcsis7 pcsis6 pcsis5 pcsis4 pcsis3 pcsis2 pcsis1 pcsis0 w reset0 00000 0 000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 mdis dis_txf dis_rxf 00 smpl_pt 0000000 halt w clr_txf clr_rxf reset0 00000 0 000000001 figure 16-3. dspi module configuration register (dspi_mcr) for cut1 address: dspi_base access: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r mstr cont_scke dconf frz mtfe pcsse rooe pcsis7 pcsis6 pcsis5 pcsis4 pcsis3 pcsis2 pcsis1 pcsis0 w reset0 00000 0 000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 mdis dis_txf dis_rxf 00 smpl_pt 000000 pes halt w clr_txf clr_rxf reset0 10000 0 000000001 figure 16-4. dspi module configuration register (dspi_mcr) for cut2/3
deserial serial peripheral interface (dspi) freescale semiconductor 16-9 pxs20 microcontroller reference manual, rev. 1 table 16-3. dspi_mcr field descriptions field description mstr master/slave mode select. the mstr bit configures the dspi for either master mode or slave mode. 0 dspi is in slave mode 1 dspi is in master mode cont_scke continuous sck enable. the cont_scke bit enables the serial communication clock (sck) to run continuously. see section 16.4.5, continuous serial communications clock , for details. 0 continuous sck disabled 1 continuous sck enabled dconf dspi configuration. the dconf field selects betw een the three different configurations of the dspi: 00 spi 01 reserved 10 reserved 11 reserved frz freeze. the frz bit enables the dspi transfers to be stopped on the next frame boundary when the soc enters debug mode. 0 do not stop serial transfers 1 stop serial transfers mtfe modified timing format enable. the mtfe bit enables a modified transfer format to be used. see section 16.4.4.4, modified spi tran sfer format (mtfe = 1, cpha = 1) , for more information. 0 modified spi transfer format disabled 1 modified spi transfer format enabled pcsse peripheral chip select strobe enable . the pcsse bit enables the pcs[5]/pcss to operate as an pcs strobe output signal. see section 16.4.3.5, peripheral chip select strobe enable (pcss) , for more information. 0 pcs[5]/pcss is used as the peripheral chip select[5] signal 1 pcs[5]/pcss is used as an active-low pcs strobe signal rooe receive fifo overflow overwrite enable. the rooe bit enables in rx fifo overflow condition to ignore the incoming serial data or to overwrite ex isting data. if the rx fifo is full and new data is received, the data from the transfer, generated the overflow, is ignored or shifted in to the shift register. see section 16.4.6.6, receive fifo overflow interrupt request , for more information. 0 incoming data is ignored 1 incoming data is shifted in to the shift register pcsis x peripheral chip select inactive state. the pc sis bit determines the inac tive state of the pcs x signal. 0 the inactive state of pcs x is low 1 the inactive state of pcs x is high mdis module disable. the mdis bit allows the clock to be stopped to the non-memory mapped logic in the dspi effectively putting the dspi in a software controlled power-saving state. see section 16.4.7, power saving features , for more information. the reset value of the mdis bit is parameterized, with a default reset value of ?0?. 0 enable dspi clocks. 1 allow external logic to disable dspi clocks. dis_txf disable transmit fifo. when dis_txf is set, the tx fifo acts as a si ngle-entry (unit depth) fifo. therefore, serial operation is performed as if the fifo has only one valid entry space for serial-word transfer. see section 16.4.2.3, fifo disable operation , for details. 0 tx fifo is enabled 1 tx fifo is disabled
deserial serial peripheral interface (dspi) 16-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 16.3.2.2 dspi hardware configuration register (dspi_hcr) [cut2/3 only] the dspi_hcr provides particular implementation details about th e dspi module, i.e. number of receive and transmit fifo entries, and the number of ctar regi sters. it is a read-only register. dis_rxf disable receive fifo. when dis_rxf is set, the rx fifo acts as a single-entry (unit depth) fifo. therefore, serial operation is performed as if the fifo has only one valid entry space for serial-word transfer. see section 16.4.2.3, fifo disable operation , for details. 0 rx fifo is enabled 1 rx fifo is disabled clr_txf clear tx fifo. clr_txf is used to flush the tx fifo. writing a ?1? to clr_txf clears the tx fifo counter. the clr_txf bit is always read as zero. 0 do not clear the tx fifo counter 1 clear the tx fifo counter clr_rxf clear rx fifo. clr_rxf is used to flush the rx fifo. writing a ?1? to clr_rxf clears the rx counter. the clr_rxf bit is always read as zero. 0 do not clear the rx fifo counter 1 clear the rx fifo counter smpl_pt sample point. smpl_pt field controls when the dspi master samples sin in modified transfer format. figure 16-25 shows where the master can sample the sin pin. 00 dspi samples sin at driving sck edge. 01 dspi samples sin one system clock after driving sck edge 10 dspi samples sin two system clocks after driving sck edge 11 reserved pes (on cut2/3 only) parity error stop. this bit controls spi operation when a parity error detected in received spi frame. 0 spi frames transmission continue. 1 spi frames transmission stop. halt halt. the halt bit starts and stops dspi transfers. see section 16.4.1, start and stop of dspi transfers , for details on the operation of this bit. 0 start transfers 1 stop transfers address: dspi_base + 0x4 access: 0123456789101112131415 r0pisr000 ctar txfr rxfr w reset ? 1 ? 0 0 0 ??????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 16-5. dspi hardware configurat ion register (dspi_hcr) [cut2/3 only] table 16-3. dspi_mcr field descriptions (continued) field description
deserial serial peripheral interface (dspi) freescale semiconductor 16-11 pxs20 microcontroller reference manual, rev. 1 16.3.2.3 dspi transfer co unt register (dspi_tcr) the dspi_tcr contains a counter, that indicates the number of spi transfers ma de. the transfer counter is intended to assist in queue ma nagement. do not write the dspi_tcr , when the dspi is in the running state. notes: 1 the reset bits in the dspi_hcr are set by configuration parameters in the chip. table 16-4. dspi_hcr field descriptions field description pisr pisr, pisr0-3 and parallel inputs frame positions selection logic are implemented for the module. 0 - dspi_pisr0-3 registers are not implemented. 1 - dspi_pisr0-3 registers are implemented ctar ctar, maximum implemented dspi_ctar register number. txfr txfr, maximum implemented dspi_txfr register number. rxfr rxfr, maximum implemented dspi_rxfr register number. address: dspi_base + 0x8 access: 0123456789101112131415 r spi_tcnt w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 16-6. dspi transfer count register (dspi_tcr) table 16-5. dspi_tcr field descriptions field description 0?15 spi_tcnt[0:15] spi transfer counter. the spi_tcnt field counts the number of spi transfers the dspi makes. the spi_tcnt field increments every time the last bit of a spi frame is transmitted. a value written to spi_tcnt presets the counte r to that value. spi_tcnt is reset to zero at the beginning of the frame when the ctcnt field is set in the executing spi command. the transfer counter ?wraps around? i.e. incrementing the counter past 65535 resets the counter to zero. 16?31 reserved, should be cleared.
deserial serial peripheral interface (dspi) 16-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 16.3.2.4 dspi clock and transfer attributes registers 0?3 (dspi_ctar0?dspi_ctar3) the dspi_ctar registers are used to define different transfer attr ibutes. do not write to the dspi_ctar registers while the dspi is in the running state. in master mode, the dspi_ctar0 - dspi_ctar3 registers define combin ations of transf er attributes such as frame size, clock phase and polarity, da ta bit ordering, baud ra te, and various delays. in slave mode, a subset of the bitf ields in the dspi_ctar0 and dspi_cta r1 registers are used to set the slave transfer attributes. when the dspi is configured as a spi master, the ctas field in the command portion of the tx fifo entry selects which of the dspi_ctar register is used. when the dspi is configured as a spi bus slave, the dspi_ctar0 register is used. address: dspi_base + 0xc?dspi_base + 0x18 access: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r dbr fmsz cpol cpha lsbfe pcssck pasc pdt pbr w reset0 1111 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cssck asc dt br w reset0 0000 0 0 0 0 0 0 0 0 0 0 0 figure 16-7. dspi clock and transfer attributes register 0?3 (dspi_ctar0?dspi_ctar3) in master mode address: dspi_base + 0xc /0x10 access: 01234 5 6 789101112131415 r fmsz cpol cpha 000000000 w reset01111 0 0 000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000 0 0 000000000 w reset00000 0 0 000000000 figure 16-8. dspi clock and transfer attributes register 0, 1 (dspi_ctar0 for cut1, dspi_ctar1) in slave mode
deserial serial peripheral interface (dspi) freescale semiconductor 16-13 pxs20 microcontroller reference manual, rev. 1 address: dspi_base + 0xc access: 01234 5 6 789101112131415 r slave_fmsz slave_cpol slave_cpha slave_pe slave_pp 0000000 w reset01111 0 0 000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000 0 0 000000000 w reset00000 0 0 000000000 figure 16-9. dspi clock and transfer attributes register 0 (dspi_ctar0) in slave mode for cut2/3 table 16-6. dspi_ctar n field descriptions in master mode field descriptions dbr double baud rate. the dbr bit doubles the effect ive baud rate of the serial communications clock (sck). this field is only used in master mode. it effectively halves the baud rate division ratio supporting faster frequencies and odd division ratios for the serial communications clock (sck). when the dbr bit is set, the duty cycle of the serial communications clock (sck) depends on the value in the baud rate prescaler and the clock phase bit as listed in ta bl e 1 6 - 7 . see the br field description for details on how to calculate the baud rate. if the overall baud rate is divide by two or divi de by three of the system clock then neither the continuous sck enable or the modified timing format enable bits should be set. 0 the baud rate is computed normally with a 50/50 duty cycle 1 the baud rate is doubled with the duty cycle depending on the baud rate prescaler fmsz frame size. the number of bits transferred per fr ame is equal fmsz field value plus 1. minimum valid fmsz field value is 3. cpol clock polarity. the cpol bit selects the inactive state of the serial communications clock (sck). this bit is used in both master and slave mode. for successful communication between serial devices, the devices must have id entical clock polarities. when the continuous selection format is selected, switching between clock polarities with out stopping the dspi can cause errors in the transfer due to the peripheral device interpreting the switch of clock polarity as a valid clock edge. 0 the inactive state value of sck is low 1 the inactive state value of sck is high cpha clock phase. the cpha bit selects which ed ge of sck causes data to change and which edge causes data to be captured. this bit is used in both master and sl ave mode. for successful communication between serial devices, the devices must have identical clock phase settings. in continuous sck mode the bit value is ignored and the transfers are done as cpha bit is set to 1. 0 data is captured on the leading edge of sck and changed on the following edge 1 data is changed on the leading edge of sck and captured on the following edge lsbfe lsb first. the lsbfe bit se lects if the lsb or msb of the frame is transferred first. 0 data is transferred msb first 1 data is transferred lsb first
deserial serial peripheral interface (dspi) 16-14 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 pcssck pcs to sck delay prescaler. the pcssck field selects the prescaler value for the delay between assertion of pcs and the first edge of the sck. see the cssck field description how to compute the pcs to sck delay. 00 pcs to sck prescaler value is 1 01 pcs to sck prescaler value is 3 10 pcs to sck prescaler value is 5 11 pcs to sck prescaler value is 7 pasc after sck delay prescaler. the pasc field selects the prescaler value for the delay between the last edge of sck and the negation of pcs. see the asc field description how to compute the after sck delay. 00 after sck delay prescaler value is 1 01 after sck delay prescaler value is 3 10 after sck delay prescaler value is 5 11 after sck delay prescaler value is 7 pdt delay after transfer prescaler. the pdt field selects the prescaler value for the delay between the negation of the pcs signal at the end of a frame and the assertion of pcs at the beginning of the next frame. the pdt field is only used in master mode. see the dt field description for details on how to compute the delay after transfer. 00 delay after transfer prescaler value is 1 01 delay after transfer prescaler value is 3 10 delay after transfer prescaler value is 5 11 delay after transfer prescaler value is 7 pbr baud rate prescaler. the pbr field selects the prescaler value for the baud rate. this field is only used in master mode. the baud rate is the freque ncy of the serial communications clock (sck). the system clock is divided by the prescaler value before the baud rate sele ction takes place. see the br field description for details on how to compute the baud rate. 00 baud rate prescaler value is 2 01 baud rate prescaler value is 3 10 baud rate prescaler value is 5 11 baud rate prescaler value is 7 table 16-6. dspi_ctar n field descriptions in master mode (continued) field descriptions
deserial serial peripheral interface (dspi) freescale semiconductor 16-15 pxs20 microcontroller reference manual, rev. 1 cssck pcs to sck delay scaler. the cssck field selects the scaler val ue for the pcs to sck delay. this field is only used in master mode. the pcs to sck delay (t csc ) is the delay between the assertion of pcs and the first edge of the sck. table 16-8 list the scaler values.the pcs to sck delay is a multiple of the system clock period and it is computed according to the following equation: eqn. 16-1 see section 16.4.3.2, pcs to sck delay (tcsc) , for more details. asc after sck delay scaler. the asc field selects the scaler value for the after sck delay. this field is only used in master mode. the after sck delay (t asc ) is the delay between the last edge of sck and the negation of pcs. ta b l e 1 6 - 8 list the scaler values.the after sc k delay is a multiple of the system clock period, and it is computed according to the following equation: eqn. 16-2 see section 16.4.3.3, after sck delay (tasc) , for more details. dt delay after transfer scaler. the dt field selects the delay after transfer scaler. this field is only used in master mode. the delay after transfer (t dt ) is the time between the negation of the pcs signal at the end of a frame and the assertion of pcs at the beginning of the next frame. ta bl e 1 6 - 8 lists the scaler values. in the continuous serial communications clock operation the dt value is fixed to one sck clock period, the delay after transfer is a multiple of the system clock per iod and it is computed according to the following equation: eqn. 16-3 see section 16.4.3.4, dela y after transfer (tdt) , for more details. br baud rate scaler. the br field selects the scaler value for the baud rate. this field is only used in master mode. the prescaled system clock is divi ded by the baud rate scaler to generate the frequency of the sck. ta b l e 1 6 - 9 lists the baud rate scaler values.the baud rate is computed according to the following equation: eqn. 16-4 see section 16.4.3.1, baud rate generator , for more details. table 16-7. dspi sck duty cycle dbr cpha pbr sck duty cycle 0 any any 50/50 1 0 00 50/50 1 0 01 33/66 1 0 10 40/60 1 0 11 43/57 table 16-6. dspi_ctar n field descriptions in master mode (continued) field descriptions t csc 1 f sys --------- pcssck cssck ? ? = t asc 1 f sys --------- pasc ? asc ? = t dt 1 f sys --------- pdt ? dt ? = sck baud rate f sys pbr ----------- 1 dbr + br --------------------- ? =
deserial serial peripheral interface (dspi) 16-16 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 1 1 00 50/50 1 1 01 66/33 1 1 10 60/40 1 1 11 57/43 table 16-8. delay scaler encoding field value scaler value field value scaler value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048 0011 16 1011 4096 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536 table 16-9. dspi baud rate scaler br baud rate scaler value br baud rate scaler value 0000 2 1000 256 0001 4 1001 512 0010 6 1010 1024 0011 8 1011 2048 0100 16 1100 4096 0101 32 1101 8192 0110 64 1110 16384 0111 128 1111 32768 table 16-7. dspi sck duty cycle (continued) dbr cpha pbr sck duty cycle
deserial serial peripheral interface (dspi) freescale semiconductor 16-17 pxs20 microcontroller reference manual, rev. 1 16.3.2.5 dspi status register (dspi_sr) the dspi_sr contains status and fl ag bits. the bits reflect the stat us of the dspi and indicate the occurrence of events that can generate interrupt or dma requests. software can clear flag bits in the dspi_sr by writing a ?1? to it. writing a ?0? to a flag bit has no effect. this re gister may not be writable in module disable mode due to th e use of power saving mechanisms. table 16-10. dspi_ctar0, dspi_ctar1 field descriptions in slave mode field descriptions slave_ fmsz slave frame size. the number of bits transferred per frame is equal slave_fmsz field value plus 1. minimum valid slave_fmsz field value is 3. slave_cpo l clock polarity. the cpol bit selects the inactive state of the serial communications clock (sck). 0 the inactive state value of sck is low 1 the inactive state value of sck is high slave_cph a clock phase. the cpha bit selects which edge of sck causes data to change and which edge causes data to be captured. 0 data is captured on the leading edge of sck and changed on the following edge 1 data is changed on the leading edge of sck and captured on the following edge slave_pe (for cut2/3 only) parity enable. pe bit enables parity bit transmission and reception for the frame 0 no parity bit included/checked. 1 parity bit is transmitted instead of last data bit in frame, parity checked for received frame. slave_pp (for cut2/3 only) parity polarity. pp bit controls polarity of the parity bit transmitted and checked 0 even parity: number of ?1? bits in the transmitted frame is even. the dspi_sr[ spef] bit is set if in the received frame number of ?1? bits is odd. 1 odd parity: number of ?1? bits in the transmitt ed frame is odd. the dspi_sr[spef] bit is set if in the received frame number of ?1? bits is even. address: dspi_base + 0x2c access: 0123456789101112131415 r tcf txrxs 0 eoqf tfuf 0 tfff 0 0 0 0 0 rfof 0 rfdf 0 w w1c w1c w1c w1c w1c w1c w1c reset0 0 0 0 00000 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r txctr txnxtptr rxctr popnxtptr w reset0 0 0 0 00000 0 0 0 0 0 0 0 figure 16-10. dspi status register (dspi_sr) for cut1
deserial serial peripheral interface (dspi) 16-18 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 address: dspi_base + 0x2c access: 0123456789101112131415 r tcf txrxs 0 eoqf tfuf 0 tfff 0 0 0 spef 0 rfof 0 rfdf 0 w w1c w1c w1c w1c w1c w1c w1c w1c reset0 0 0 0 00000 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r txctr txnxtptr rxctr popnxtptr w reset0 0 0 0 00000 0 0 0 0 0 0 0 figure 16-11. dspi status register (dspi_sr) for cut2/3 table 16-11. dspi_sr field descriptions field description tcf transfer complete flag. a value of tcf = 1 indicates that at least one serial-data-word (frame) from the fifo has been transferred/received over the serial link. for example, if after 4 transfer words are written, then tcf would be set after the first word has been completely transferred. 0 transfer not complete 1 transfer complete note: it is recommended not to write this bit when the transfer is occurring, since the update from the serial-link side has a higher priority than the regist er access. in other words, register access is ignored if it occurs in the same clock cycl e as the completion of any serial transfer. txrxs tx & rx status. the txrxs bit reflects the run status of the dspi. see section 16.4.1, start and stop of dspi transfers , what causes this bit to be set or cleared. 0 tx and rx operations are disabled (dspi is in stopped state) 1 tx and rx operations are enabled (dspi is in running state) eoqf end of queue flag. the eoqf bi t indicates that the la st entry in a queue has been transmitted when the dspi in the master mode. the eoqf bit is se t when tx fifo entry has the eoq bit set in the command halfword (dspi push tx fifo) and the e nd of the transfer is reached. the eoqf bit remains set until cleared by writing 1 to it. when th e eoqf bit is set, the txrxs bit is automatically cleared. 0 eoq is not set in the executed command 1 eoq bit is set in the executed spi command note: eoqf does not function in slave mode. tfuf transmit fifo underflow flag. the tfuf bit indicate s that an underflow condition in the tx fifo has occurred. the transmit underflow condition is detected only for dspi blocks operating in slave mode and spi configuration. the tfuf bit is set when the tx fifo of a dspi operating in spi slave mode is empty, and a transfer is initiated by an external spi master. the tfuf bit remains set until cleared by writing 1 to it. 0 tx fifo underflow has not occurred 1 tx fifo underflow has occurred tfff transmit fifo fill flag. the tff f bit provides a method for the dspi to request more entries to be added to the tx fifo. the tfff bit is set while the tx fifo is not full. the tfff bit can be cleared by writing 1 to it or by acknowledgement from the dma controller to the tx fifo full request. 0 tx fifo is full 1 tx fifo is not full
deserial serial peripheral interface (dspi) freescale semiconductor 16-19 pxs20 microcontroller reference manual, rev. 1 16.3.2.6 dspi dma/interrupt request select and enable register (dspi_rser) the dspi_rser register contro ls dma and interrupt requests. do not write to the dspi_rser whil e the dspi is in the running state. you are allowed to write to this register in module disable mode. spef (on cut2/3 only) spi parity error flag. the spef fl ag indicates that a spi frame wi th parity error had been received. the bit remains set until cleared by writing 1 to it. 0 parity error has not occurred 1 parity error has occurred rfof receive fifo overflow flag. the rfof bit indica tes that an overflow condit ion in the rx fifo has occurred. the bit is set when the rx fifo and shift re gister are full and a transfer is initiated. the bit remains set until cleared by writing 1 to it. 0 rx fifo overflow has not occurred 1 rx fifo overflow has occurred rfdf receive fifo drain flag. the rfdf bit provides a method for the dspi to request that entries be removed from the rx fifo. the bit is set while t he rx fifo is not empty. the rfdf bit can be cleared by writing 1 to it or by acknowledgement fr om the dma controller when the rx fifo is empty. 0 rx fifo is empty 1 rx fifo is not empty txctr tx fifo counter. the txctr field indicates the number of valid entries in the tx fifo. the txctr is incremented every time the dspi _pushr is wr itten. the txctr is decremented every time a spi command is executed and the spi data is transferred to the shift register. txnxtptr transmit next pointer. the txnxtptr field in dicates which tx fifo entry is transmitted during the next transfer. the txnxtptr field is updated every ti me spi data is transferred from the tx fifo to the shift register. see section 16.4.6.4, transmit fifo underflow interrupt request , for more details. rxctr rx fifo counter. the rxctr field indicates the number of entries in t he rx fifo. the rxctr is decremented every time the dspi _popr is read. the rxctr is incremented every time data is transferred from the shift register to the rx fifo. popnxtptr pop next pointer. the popnxtptr field contains a pointer to the rx fifo entry that will be returned when the dspi_popr is read. the popnxtptr is updated when the dspi_popr is read. see section 16.4.2.5, receive first in fi rst out (rx fifo) buffering mechanism , for more details. table 16-11. dspi_sr field descriptions (continued) field description
deserial serial peripheral interface (dspi) 16-20 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 address: dspi_base + 0x30 access: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r tcf_re 00 eoqf_re tfuf_re 0 tfff_re tfff _dirs 00 0 0 rfof_re 0 rfdf_re rfdf _dirs w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 16-12. dspi dma/interrupt request select and enable register (dspi_rser) for cut1 address: dspi_base + 0x30 access: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r tcf_re 00 eoqf_re tfuf_re 0 tfff_re tfff _dirs 00 spef_re 0 rfof_re 0 rfdf_re rfdf _dirs w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 16-13. dspi dma/interrupt request select and enable register (dspi_rser) for cut2/3
deserial serial peripheral interface (dspi) freescale semiconductor 16-21 pxs20 microcontroller reference manual, rev. 1 16.3.2.7 dspi push tx fifo register (dspi_pushr) the dspi_pushr register provides m eans to write to the tx fifo. data written to this register is transferred to the tx fifo. see section 16.4.2.4, transmit first in first out (tx fifo) buffering mechanism for more information. eight or sixteen bit write accesses to the dspi_pushr transfers all 32 table 16-12. dspi_rser field descriptions field description tcf_re transmission complete request enable. the tcf_re bit enables tcf flag in the dspi_sr to generate an interrupt request. 0 tcf interrupt requests are disabled 1 tcf interrupt requests are enabled eoqf_re dspi finished request enable. the eoqf_r e bit enables the eoqf flag in the dspi_sr to generate an interrupt request. 0 eoqf interrupt requests are disabled 1 eoqf interrupt requests are enabled tfuf_re transmit fifo underflow request enable. the tfuf_re bit enables the tfuf flag in the dspi_sr to generate an interrupt request. 0 tfuf interrupt requests are disabled 1 tfuf interrupt requests are enabled tfff_re transmit fifo fill request enable. the tfff_r e bit enables the tfff flag in the dspi_sr to generate a request. the tfff_dirs bit selects betw een generating an interrupt request or a dma requests. 0 tfff interrupt requests or dma requests are disabled 1 tfff interrupt requests or dma requests are enabled tfff_dirs transmit fifo fill dma or interrupt request select. the tfff_dirs bit selects between generating a dma request or an interrupt request. when the tfff flag bit in the dspi_sr is set, and the tfff_re bit in the dspi_rser register is set, this bit selects between generating an interrupt request or a dma request. 0 interrupt request will be generated 1 dma request will be generated spef_re (for cut2/3 only) spi parity error request enable. the spef_re bits enables spef flag in the dspi_sr to generate an interrupt requests. 0 pef interrupt requests are disabled 1 pef interrupt requests are enabled rfof_re receive fifo overflow request enable. the rfof_re bit enables the rfof flag in the dspi_sr to generate an interrupt requests. 0 rfof interrupt requests are disabled 1 rfof interrupt requests are enabled rfdf_re receive fifo drain request enable. the rfdf_re bit enables the rfdf flag in the dspi_sr to generate a request. the rfdf_dirs bit selects be tween generating an interrupt request or a dma request. 0 rfdf interrupt requests or dma requests are disabled 1 rfdf interrupt requests or dma requests are enabled rfdf_dirs receive fifo drain dma or interrupt r equest select. the rfdf_dirs bit selects between generating a dma request or an interrupt request. when the rfdf flag bit in the dspi_sr is set, and the rfdf_re bit in the dspi_rser register is se t, the rfdf_dirs bit selects between generating an interrupt request or a dma request. 0 interrupt request will be generated 1 dma request will be generated
deserial serial peripheral interface (dspi) 16-22 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 register bits to the tx fifo.the re gister structure is different in mast er and slave modes. in master mode the register provides 16-bit command and 16-bit data to the tx fifo. in slave mode all 32 register bits can be used as data, supporting up to 32-bit spi frame operation. address: dspi_base + 0x34 access: 0 1 2 3 4 5 6 7 8 9 101112131415 r cont ctas eoq ctcnt 00 pcs7 pcs6 pcs5 pcs4 pcs3 pcs2 pcs1 pcs0 w reset00000 0 0000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r txdata w reset00000 0 0000000000 figure 16-14. dspi push tx fifo register (dspi_pushr) in master mode for cut1 address: dspi_base + 0x34 access: 0 1 2 3 4 5 6 7 8 9 101112131415 r cont ctas eoq ctcnt pushr_pe pushr_pp pcs7 pcs6 pcs5 pcs4 pcs3 pcs2 pcs1 pcs0 w reset00000 0 0000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r txdata w reset00000 0 0000000000 figure 16-15. dspi push tx fifo register (dspi_pushr) in master mode for cut2/3
deserial serial peripheral interface (dspi) freescale semiconductor 16-23 pxs20 microcontroller reference manual, rev. 1 table 16-13. dspi_pushr field descriptions in master mode field descriptions cont continuous peripheral chip select enable. the cont bit selects a continuous selection format. the bit is used in spi master mode. the bit enables the selected pcs signals to remain asserted between transfers. see section 16.4.4.5, continuous selection format , for more information. 0 return peripheral chip select signals to their inactive state between transfers 1 keep peripheral chip select signals asserted between transfers ctas clock and transfer attributes select. the ctas field selects number of the dspi_ctar register be used to set the transfer attributes for the associated spi frame. the field is only used in spi master mode. in spi slave mode dspi_ctar0 is used . the number of dspi _ctar registers is implementation specific and the ctas shoul d be set to select only implemented one. eoq end of queue. the eoq bit provides a means for host software to signal to the dspi that the current spi transfer is the last in a queue. at the end of the transfer the eoqf bit in the dspi_sr is set. 0 the spi data is not the last data to transfer 1 the spi data is the last data to transfer ctcnt clear transfer counter. the ctcnt bit clears the spi_tcnt field in the dspi_tcr register. the spi_tcnt field is cleared before transm ission of the current spi frame begins. 0 do not clear spi_tcnt field in the dspi_tcr 1 clear spi_tcnt field in the dspi_tcr pushr_pe (for cut2/3 only) parity enable. pe bit enables parity bit transmission and parity reception check for the spi frame 0 no parity bit included/checked. 1 parity bit is transmitted instead of last data bit in frame, parity checked for received frame. pushr_pp (for cut2/3 only) parity polarity. pp bit controls polarity of the parity bit transmitted and checked 0 even parity: number of ?1? bits in the transmitted frame is even. the dspi_sr[ spef] bit is set if in the received frame number of ?1? bits is odd. 1 odd parity: number of ?1? bits in the transmitt ed frame is odd. the dspi_sr[spef] bit is set if in the received frame number of ?1? bits is even. pcs x peripheral chip select 0?7. the pcs bits select which pcs signals will be asserted for the transfer. 0 negate the pcs[x] signal 1 assert the pcs[x] signal txdata transmit data. the txdata field holds spi data to be transferred according to the associated spi command. address: dspi_base + 0x34 access: 0123456789101112131415 r txdata[31:16] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r txdata[15:0] w reset0000000000000000 figure 16-16. dspi push tx fifo register (dspi_pushr) in slave mode
deserial serial peripheral interface (dspi) 16-24 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 16.3.2.8 dspi pop rx fifo register (dspi_popr) the dspi_popr provides means to read the rx fifo. see section 16.4.2.5, receive first in first out (rx fifo) buffering mechanism for a description of the rx fifo operations. eight or sixteen bit read accesses to the dspi_popr have the same ef fect on the rx fifo as 32-bit read access. 16.3.2.9 dspi transmit fifo regist ers 0?4 (dspi_txfr0?dspi_txfr4) these registers provide visibility in to the tx fifo for debugging purposes . each register is an entry in the tx fifo. the registers are r ead-only and cannot be modified. r eading the dspi_txfrx registers does not alter the stat e of the tx fifo. table 16-14. dspi_pushr field descriptions in slave mode field descriptions txdata transmit data. the txdata field holds spi data to be transferred. address: dspi_base + 0x38 access: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rrxdata w reset00 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rrxdata w reset00 00000000000000 figure 16-17. dspi pop rx fifo register (dspi_popr) table 16-15. dspi_popr field descriptions field description 0?31 rxdata[0:31] received data. the rxdata field contains the spi data from the rx fifo entry pointed to by the pop next data pointer.
deserial serial peripheral interface (dspi) freescale semiconductor 16-25 pxs20 microcontroller reference manual, rev. 1 16.3.2.10 dspi receive fi fo registers 0?4 (dspi_rxfr0?dspi_rxfr4) these registers provide visibility in to the rx fifo for debugging purposes. each register is an entry in the rx fifo. the dspi_rxfr regist ers are read-only. reading the d spi_rxfrx registers does not alter the state of the rx fifo. address: dspi_base+0x 3c?dspi_base+0x4c access: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r txcmd/txdata w reset00 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rtxdata w reset00 00000000000000 figure 16-18. dspi transmit fifo register 0?4 (dspi_txfr0?dspi_txfr4) table 16-16. dspi_txfr n field descriptions field description 0?15 txcmd[0:15]/ txdata[0:15] transmit command or transmit da ta. in master mode the txcmd fi eld contains the command that sets the transfer attributes for the spi data. see section 16.3.2.7, dspi pu sh tx fifo register (dspi_pushr) , for details on the command field. in slave mode the txdata contains 16 msb bits of the spi data to be shifted out 16?31 txdata[16:31] transmit data. the txdata field contains the spi data to be shifted out. address: dspi_base + 0x7c?dspi_base + 0x8c access: 0123456789101112131415 r rxdata w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rxdata w reset 0000000000000000 figure 16-19. dspi receive fifo re gisters 0?4 (dspi_rxfr0?dspi_rxfr4)
deserial serial peripheral interface (dspi) 16-26 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 16.4 functional description the dspi block supports full-dupl ex, synchronous serial communications between mcus and peripheral devices. the dspi can also be used to reduce the number of pins required for i/o by serializing and deserializing up to 32 parallel i nput/output signals. all communications are done with spi-like protocol. the dspi has one configuration: ? spi configuration in which the dspi operates as a basic spi or a queued spi. the dspi_mcr[dconf] field determin es the dspi configuration. see table 16-3 for the dspi configuration values. the dspi_ctar0 - dspi_ctar3 registers hol d clock and transfer attributes (see section 16.3.2.4, dspi clock and transfer attributes re gisters 0?3 (dspi_ctar0?dspi_ctar3) ). the spi configuration allows to select which ctar to use on a frame by frame basis by se tting a field in the spi command. see section 16.3.2.4, dspi clock and tr ansfer attributes register s 0?3 (dspi_ctar0?dspi_ctar3) , for information on the fields of the dspi_ctar registers. typical master to slave c onnections are shown in the figure 16-20 . when a data transfer operation is performed, data is serially shif ted a predetermined number of bi t positions. because the modules are linked, data is exchanged between the master and the slave. the data that was in the master shift register is now in the shift register of the slave, and vice versa. at the end of a transfer, the tcf bit in the dspi_sr is set to indicate a completed transfer. figure 16-20. spi serial protocol overview generally more than one slave device can be connected to the dspi ma ster. eight peripheral chip select (pcs) signals of the dspi masters can be used to select which of the slaves to communicate with. the three dspi configurations share transfer pr otocol and timing propert ies which are described independently of the configuration in section 16.4.4, transfer formats . the transfer rate and delay settings are described in section 16.4.3, dspi baud rate and clock delay generation . table 16-17. dspi_rxfr n field descriptions field description 0?31 rxdata[0:31] receive data. the rxdata field contains the received spi data. shift register baud rate generator shift register sin sin sout sout sck sck ss pcsx dspi master dspi slave
deserial serial peripheral interface (dspi) freescale semiconductor 16-27 pxs20 microcontroller reference manual, rev. 1 the shifting of data between fifo and shift registers is more dependent upon the state of the internal fsm rather than the exact number of elapsed clock cycles . for example, tx-data is loaded into the shift register whenever the ?next state? of fsm is pcs-to -sck delay stage while the current state is idle, ?after sck delay,? ?delay after transfer,? or stall. 16.4.1 start and stop of dspi transfers the dspi has two operating states: stopped and running. the states are independent of dspi configuration. the default state of the dspi is stopped. in the sto pped state no serial transfers are initiated in master mode and no tr ansfers are responded to in slave mode. the stopped state is also a safe state for writing the various c onfiguration registers of the dspi without causin g undetermined results. in the running state serial transfers take place. the txrxs bit in the dspi_sr indicates in what st ate the dspi is. the bit is set if the module in running state. the dspi is started (dspi transi tions to running) when all of th e following conditions are true: ? dspi_sr[eoqf] bit is clear ? soc is not in the debug mode is or the dspi_mcr[frz] bit is clear ? dspi_mcr[halt] bit is clear the dspi stops (transitions from running to sto pped) after the current fr ame when any one of the following conditions exist: ? dspi_sr[eoqf] bit is set ? soc in the debug mode and th e dspi_mcr[frz] bit is set ? dspi_mcr[halt] bit is set state transitions from running to stopped occur on the next frame boundary if a transfer is in progress, or immediately if no transfers are in progress. 16.4.2 serial peripheral in terface (spi) configuration the spi configuration transfers data serially using a shift register and a selection of programmable transfer attributes. the dspi is in spi configuration when the dc onf field in the dspi_mcr is 0b00. the spi frames can be from four to sixteen bits long. host cpu or a dma controller transf er the spi data from the external to dspi ram queues to a transmit first-in first-out (tx fifo) buffer. the received data is stored in entries in the receive fifo (rx fifo) buffer. host cpu or the dma controller transfer the received data from the rx fifo to memory exte rnal to the dspi. the fi fo buffers operation is described in section 16.4.2.4, transmit firs t in first out (tx fifo ) buffering mechanism , and section 16.4.2.5, receive first in first out (rx fifo) buffering mechanism . the interrupt and dma request conditions are described in section 16.4.6, interrupts/dma requests . the spi configuration supports two block-specific modes - master mode and slave mode. the fifo operations are similar for both modes. the main difference is that in ma ster mode the dspi initiates and controls the transfer according to th e fields in the spi comm and field of the tx fifo entry. in slave mode
deserial serial peripheral interface (dspi) 16-28 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 the dspi only responds to transfers initiated by a bus master external to the dspi and the spi command field space is used for 16 most si gnificant bit of the transmit data. 16.4.2.1 master mode in spi master mode the dspi initia tes the serial transfers by control ling the serial communications clock (sck) and the peripheral chip sel ect (pcs) signals. the spi command field in the executing tx fifo entry determines which ctar register s will be used to set the transfer attributes and which pcs signal to assert. the command field also cont ains various bits that help with queue management and transfer protocol. see section 16.3.2.7, dspi push tx fi fo register (dspi_pushr) , for details on the spi command fields. the data field in the executing tx fifo entry is loaded into the shift register and shifted out on the serial out (sout) pin. in spi master mode, each spi frame to be tran smitted has a command associated with it allowing for transfer attribute control on a frame by frame basis. 16.4.2.2 slave mode in spi slave mode the dspi responds to transfers initiated by a spi bus master. the dspi does not initiate transfers. certain transfer attributes such as clock polarity, clock phase and frame size must be set for successful communication with a spi master. the spi slave mode transfer attributes are set in the dspi_ctar0. 16.4.2.3 fifo disable operation the fifo disable mechanisms allo w spi transfers without using the tx fifo or rx fifo. the dspi operates as a double-buffered simplified spi when the fifos are disabled. the fifos are disabled separately; setting the dspi_mcr[dis_txf] bi t disables the tx fi fo, and setting the dspi_mcr[dis_rxf] bit disables the rx fifo. the fifo disable mechanisms are transparent to the user and to host software; transmit data and commands are written to the dspi_p ushr and received data is read from the dspi_popr.when the tx fifo is disabled the tfff, tfuf a nd txctr fields in dspi_sr behave as if there is a one-entry fifo but the contents of the dspi_txfr registers a nd txnxtptr are undefined. likewise, when the rx fifo is disabled, the rfdf, rfof and rxctr fields in the dspi_sr behave as if there is a one-entry fifo, but the contents of the dspi_rxf r registers and popnxtptr are undefined. 16.4.2.4 transmit first in first ou t (tx fifo) buffering mechanism the tx fifo functions as a buffer of spi data and spi commands fo r transmission. the tx fifo holds 1?5 words, each consisting of a comm and field and a data field. the numbe r of entries in the tx fifo is soc specific. spi commands and data are added to the tx fifo by writ ing to the dspi push tx fifo register (dspi_pushr). tx fifo entries can only be removed from the tx fi fo by being shifted out or by flushing the tx fifo. the tx fifo counter field (txctr ) in the dspi status register (dspi_sr) indicates the number of valid entries in the tx fifo. the txctr is updated ev ery time the dspi _pushr is written or spi data is transferred into the shift register from the tx fifo.
deserial serial peripheral interface (dspi) freescale semiconductor 16-29 pxs20 microcontroller reference manual, rev. 1 the txnxtptr field indicates which tx fifo entry will be transmitted during the next transfer. the txnxtptr contains the positive offs et from dspi_txfr0 in number of 32-bit registers. for example, txnxtptr equal to two means that the dspi_txfr2 contains the spi data and command for the next transfer. the txnxtptr field is incr emented every time spi da ta is transferred from the tx fifo to the shift register. the maximum value of the field is equal to dspi_hcr[txfr] and it rolls over after reaching the maximum. because the pushr is a 32-bit register , any writes to pushr will transfer the all 32 bits of data from the write data bus to the register . data byte strobes are ignored. 16.4.2.4.1 filling the tx fifo host software or other intelligent blocks can add (push) entries to the tx fifo by writing to the dspi_pushr. when the tx fi fo is not full, the tx fi fo fill flag (tfff) in the dspi_sr is set. the tfff bit is cleared when tx fifo is full and the dma controller indicates that a wr ite to dspi_pushr is complete. writing a ?1? to the tfff bit also cl ears it. the tfff can genera te a dma request or an interrupt request. see section 16.4.6.2, transmit fifo f ill interrupt or dma request , for details. the dspi ignores attempts to push data to a full tx fifo, the state of the tx fifo does not change and no error condition is indicated. 16.4.2.4.2 draining the tx fifo the tx fifo entries are re moved (drained) by shifting spi data out through the sh ift register. entries are transferred from the tx fifo to the shift register and shifted out as l ong as there are valid entries in the tx fifo. every time an entry is transferred from the tx fifo to the shift regi ster, the tx fifo counter decrements by one. at the end of a transfer, the tcf bit in the dspi_sr is set to indicate the completion of a transfer. the tx fifo is flushed by wr iting a ?1? to the clr_txf bit in dspi_mcr. if an external bus master initiates a transfer with a dspi slave while th e slave?s dspi tx fifo is empty, the transmit fifo underflow flag (tfuf) in the slave?s dspi_sr is set. see section 16.4.6.4, transmit fifo underflow interrupt request , for details. the tfff and tcf bits in the dspi _sr are independent of each other. the tx fifo is updated (and the tfff field is updated) whenever the tx data is loaded into the shift register. the tcf bit is updated when all of the tx data is shifted out. 16.4.2.5 receive first in first ou t (rx fifo) buffering mechanism the rx fifo functions as a buffer for data receiv ed on the sin pin. the rx fifo holds from one to sixteen received spi data fr ames. the number of entries in the rx fi fo is soc specific. spi data is added to the rx fifo at the completion of a transfer when th e received data in the shift register is transferred into the rx fifo. spi data are removed (popped) fr om the rx fifo by reading the dspi pop rx fifo register (dspi_popr). rx fifo entries can only be removed from the rx fifo by reading the dspi_popr or by flushing the rx fifo. the rx fifo counter field (rxctr) in the dspi st atus register (dspi_sr) indicates the number of valid entries in the rx fifo. the rxctr is updated ev ery time the dspi _popr is read or spi data is copied from the shift re gister to the rx fifo.
deserial serial peripheral interface (dspi) 16-30 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 the popnxtptr field in the dspi_sr points to th e rx fifo entry that is returned when the dspi_popr is read. the popnxtptr contains the positive offset from dspi_rxfr0 in number of 32-bit registers. for example, popnxtptr equal to two means that the dspi_rxfr2 contains the received spi data that will be retu rned when dspi_popr is read. th e popnxtptr field is incremented every time the dspi_popr is read. the maximum va lue of the field is equa l to dspi_hcr[rxfr] and it rolls over after reaching the maximum. 16.4.2.5.1 filling the rx fifo the rx fifo is filled with the rece ived spi data from the shift regist er. while the rx fifo is not full, spi frames from the shift register are transferred to th e rx fifo. every time a sp i frame is transferred to the rx fifo the rx fifo counter is incremented by one. if the rx fifo and shift register are full and a transf er is initiated, the rfof bit in the dspi_sr is set indicating an overflow condition. depend ing on the state of the rooe bit in the dspi_mcr, the data from the transfer that generated the overflow is either ignored or shifted in to the shif t register. if the rooe bit is set, the incoming data is shifted in to the shift register. if the rooe bit is cleared, the incoming data is ignored. 16.4.2.5.2 draining the rx fifo host cpu or a dma can remove (pop) entries from the rx fifo by reading the dspi pop rx fifo register (dspi_popr). a read of the dspi_popr decrements the rx fifo counter by one . attempts to pop data from an empty rx fifo are ignored and the rx fifo counter remains unchanged. the data, read from the empty rx fifo, is undetermined. when the rx fifo is not empty, the rx fifo drain flag (rfdf) in the dspi_s r is set. the rfdf bit is cleared when the rx_fifo is empty and the dma co ntroller indicates that a read from dspi_popr is complete or by writing a ?1? to it. 16.4.3 dspi baud rate an d clock delay generation the sck frequency and the delay values for serial tr ansfer are generated by dividing the system clock frequency by a prescaler and a scaler wi th the option for doubling the baud rate. figure 16-21 shows conceptually how the sck signal is generated. figure 16-21. communications cl ock prescalers and scalers 16.4.3.1 baud rate generator the baud rate is the frequency of the serial comm unication clock (sck). the system clock is divided by a prescaler (pbr) and scal er (br) to produce sck with the possibi lity of halving the scaler division. the dbr, pbr and br fields in the dspi_ctars (see section 16.3.2.4, dspi clock and transfer sck system clock prescaler 1 scaler 1+dbr
deserial serial peripheral interface (dspi) freescale semiconductor 16-31 pxs20 microcontroller reference manual, rev. 1 attributes registers 0?3 (dspi_ctar0?dspi_ctar3) ) select the frequency of sck by the formula in the br field description. table 16-18 shows an example of how to compute the baud rate. 16.4.3.2 pcs to sck delay (t csc ) the pcs to sck delay is the length of time from as sertion of the pcs signal to the first sck edge. see figure 16-23 for an illustration of the pcs to sck de lay. the pcssck and cssck fields in the dspi_ctar x registers select the pcs to sck delay by the formula in the cssck field description (see section 16.3.2.4, dspi clock and tr ansfer attributes register s 0?3 (dspi_ctar0?dspi_ctar3) ). table 16-19 shows an example of how to compute the pcs to sck delay. 16.4.3.3 after sck delay (t asc ) the after sck delay is the length of time between th e last edge of sck and the negation of pcs. see figure 16-23 and figure 16-24 for illustrations of the after sck de lay. the pasc and asc fields in the dspi_ctar x registers select the after sck delay by the formula in the asc fi eld description (see section 16.3.2.4, dspi clock and tr ansfer attributes register s 0?3 (dspi_ctar0?dspi_ctar3) ). table 16-20 shows an example of how to compute the after sck delay. 16.4.3.4 delay after transfer (t dt ) the delay after transfer is the minimum time betw een negation of the pcs si gnal for a frame and the assertion of the pcs signal for the next frame. see figure 16-23 for an illustration of the delay after transfer. the pdt and dt fields in the dspi_ctar x registers select the delay after transfer by the formula in the dt field description (see section 16.3.2.4, dspi clock and tran sfer attributes registers 0?3 (dspi_ctar0?dspi_ctar3) ). table 16-21 shows an example of how to compute the delay after transfer. table 16-18. baud rate computation example f sys pbr prescaler br scaler dbr baud rate 100 mhz 0b00 2 0b0000 2 0 25 mb/s 20 mhz 0b00 2 0b0000 2 1 10 mb/s table 16-19. pcs to sck delay computation example f sys pcssck prescaler cssck sca ler pcs to sck delay 100 mhz 0b01 3 0b0100 32 0.96 ? s table 16-20. after sck delay computation example f sys pasc prescaler asc scaler after sck delay 100 mhz 0b01 3 0b0100 32 0.96 ? s table 16-21. delay after transfer computation example f sys pdt prescaler dt scaler delay after transfer 100 mhz 0b01 3 0b1110 32768 0.98 ms
deserial serial peripheral interface (dspi) 16-32 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 when in non-continuous clock mode the t dt delay is configured according equation 16-3 . when in continuous clock mode the de lay is fixed at 1 sck period. 16.4.3.5 peripheral chip sele ct strobe enable (pcss ) the pcss signal provides a delay to allow the pcs signals to settle after a transition occurs thereby avoiding glitches. when the dspi is in master mode and pcsse bit is set in the dspi_mcr, pcss provides a signal for an exte rnal demultiplexer to decode the pcs[ 0] -pcs[4] and pcs[6] -pcs[7] signals into as many as 128 glitch-free pcs signals. figure 16-22 shows the timing of the pcss signal relative to pcs signals. figure 16-22. peripheral chip select strobe timing the delay between the assertion of the pcs signals and the assertion of pcss is selected by the pcssck field in the dspi_ctar based on the following formula: eqn. 16-5 at the end of the transf er the delay between pcss negation and pcs negation is selected by the pasc field in the dspi_ctar based on the following formula: eqn. 16-6 table 16-22 shows an example of how to compute the t pcssck delay. table 16-23 shows an example of how to compute the t pasc delay. the pcss signal is not supported when continuous serial communicati on sck is enabled. table 16-22. peripheral chip select strobe assert computation example f sys pcssck prescaler delay before transfer 100 mhz 0b11 7 70.0 ns table 16-23. peripheral chip select strobe negate computation example f sys pasc prescaler delay after transfer 100 mhz 0b11 7 70.0 ns t pcssck pcss pcsx t pasc t pcssck 1 f sys -------- - pcssck ? = t pasc 1 f sys -------- - pasc ? =
deserial serial peripheral interface (dspi) freescale semiconductor 16-33 pxs20 microcontroller reference manual, rev. 1 16.4.4 transfer formats the spi serial communication is c ontrolled by the serial communicat ions clock (sck) signal and the pcs signals. the sck signal provided by the master de vice synchronizes shifting and samplin g of the data on the sin and sout pins. the pcs signals serv e as enable signals for the slave devices. when the dspi is the bus master, the cpol and cpha bits in the dspi clock and transfer attributes registers (dspi_ctarx) select the pol arity and phase of the serial cl ock, sck. the polarity bit selects the idle state of the sck. the clock phase bit selects if the data on sout is valid before or on the first sck edge. when the dspi is the bus slave, cpol and cpha bits in the dspi_cta r0 select the polarity and phase of the serial clock. even though the bus slave does not control the sck si gnal, clock polarity, clock phase and number of bits to transfer must be identical for the master and the slave devices to ensure proper transmission. the dspi supports four different transfer formats: ? classic spi with cpha=0 ? classic spi with cpha=1 ? modified transfer format with cpha = 0 ? modified transfer format with cpha = 1 a modified transfer format is supported to allow for high-speed communication with peripherals that require longer setup times. the dspi can sample the incoming data later than halfway through the cycle to give the peripheral more se tup time. the mtfe bit in the dspi_mcr selects between classic spi format and modified transfer format. the dspi provides the option of keeping the pcs signals a sserted between frames. see section 16.4.4.5, continuous selection format , for details. 16.4.4.1 classic spi transfer format (cpha = 0) the transfer format shown in figure 16-23 is used to communicate with peripheral spi slave devices where the first data bit is available on the first clock edge. in this format , the master and slave sample their sin pins on the odd-num bered sck edges and change the data on their sout pi ns on the even-numbered sck edges.
deserial serial peripheral interface (dspi) 16-34 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 16-23. dspi transfer timing diagram (mtfe=0, cpha=0, fmsz=8) the master initiates the transfer by placing its first data bi t on the sout pin and a sserting the appropriate peripheral chip select signals to th e slave device. the slave responds by placing its first data bit on its sout pin. after the t csc delay elapses, the master outputs the firs t edge of sck. the master and slave devices use this edge to sample the first input data b it on their serial da ta input signals. at the second edge of the sck the master and slave devi ces place their second data bit on their serial da ta output signals. for the rest of the frame the master and the slave sample their sin pins on the odd-numbered clock edges and changes the data on their sout pins on the even-numbered clock edges. after the last clock edge occurs a delay of t asc is inserted before the master ne gates the pcs signals. a delay of t dt is inserted before a new frame transfer can be initiated by the master. 16.4.4.2 classic spi transfer format (cpha = 1) this transfer format shown in figure 16-24 is used to communicate with pe ripheral spi slav e devices that require the first sck edge before th e first data bit becomes available on the slave sout pin. in this format the master and slave devices change the data on th eir sout pins on the odd -numbered sck edges and sample the data on their sin pins on the even-numbered sck edges t csc sck master and slave pcsx/ss sck msb first (lsbfe = 0): lsb first (lsbfe = 1): msb lsb lsb msb bit 5 bit 2 bit 6 bit 1 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 master sout/ master sin/ t dt t csc t csc = pcs to sck delay t dt = delay after transfer (minimum cs idle time) (cpol = 0) (cpol = 1) t asc slave sin slave sout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sample t asc = after sck delay
deserial serial peripheral interface (dspi) freescale semiconductor 16-35 pxs20 microcontroller reference manual, rev. 1 figure 16-24. dspi transfer timing diagram (mtfe=0, cpha=1, fmsz=8) the master initiates the tran sfer by asserting the pcs signal to the slave. after the t csc delay has elapsed, the master generates the first sck edge and at the same time places valid data on the master sout pin. the slave responds to the first sck edge by pl acing its first data bit on its slave sout pin. at the second edge of the sck the master and slave sa mple their sin pins. for the rest of the frame the master and the slave change the data on their sout pins on the odd-numbered clock edges and sample their sin pins on the even-numbere d clock edges. after the last clock edge occurs a delay of t asc is inserted before the master negates the pcs signal. a delay of t dt is inserted before a ne w frame transfer can be initiated by the master. 16.4.4.3 modified spi transfer format (mtfe = 1, cpha = 0) in this modified transfer format both the master a nd the slave sample later in the sck period than in classic spi mode to allow tolerate more delays in device pads and board traces. these delays become a more significant fraction of the sc k period as the sck period decr eases with increasing baud rates. the master and the slave place data on the sout pins at the assertion of the pcs signal. after the pcs to sck delay has elapsed the first sck edge is gene rated. the slave samples the master sout signal on every odd numbered sck edge. the dspi in the slave mode when the mtfe bit is set also places new data on the slave sout on every odd numbered clock edge. regular external slave, configured with cpha=0 format drives its sout output at every even numbered sck clock edge. t csc t dt sck sck msb first (lsbfe = 0): lsb first (lsbfe = 1): msb lsb lsb msb bit 5 bit 2 bit 6 bit 1 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 t csc = pcs to sck delay t dt = delay after transfer (minimum cs negation time) (cpol = 0) (cpol = 1) t asc master sout/ master sin/ slave sin slave sout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 pcsx/ss master and slave sample t asc = after sck delay
deserial serial peripheral interface (dspi) 16-36 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 the dspi master places it s second data bit on the sout line one system cl ock after odd numbered sck edge if the system frequency to sck frequency ratio is higher than three. if this ratio is below four the master changes sout at odd numbered sck edge. the po int where the master samples the sin is selected by the dspi_mcr[smpl_pt] field. the table 16-3 lists the number of system clock cycles between the active edge of sck and the master sample point. the master sample point can be delayed by one or two system clock cycles. the smpl_pt field should be set to 0 if the system to sc k frequency ratio is less than 4. following timing diagrams illustrate the dspi operation with mtfe=1. timing delays shown are: ? t csc - pcs to sck assertion delay ? t acs - after sck pcs negation delay ? t su_ms - master sin setup time ? t hd_ms - master sin hold time ? t vd_sl - slave data output valid time, time between slave data output sck driving edge and data becomes valid. ? t su_sl - data setup time on slave data input ? t hd_sl - data hold time on slave data input ? t sys - system clock period. figure 16-25 shows the modified transfer format for cpha = 0 and fsys/fsck = 4. only the condition where cpol = 0 is illustrated. soli d triangles show the da ta sampling clock edges. the two possible slave behavior are shown. ? signal, marked ?sout of ext slave?, pr esents regular spi slave serial output. ? signal, marked ?sout of dspi slave?, presents dspi in the slave mode with mtfe bit set. other mtfe = 1 diagrams show dspi sin input as being driven by a regular external spi slave, configured according dspi master cpha programming.
deserial serial peripheral interface (dspi) freescale semiconductor 16-37 pxs20 microcontroller reference manual, rev. 1 figure 16-25. dspi modified transfer format (mtfe=1, cpha=0, f sck = f sys /4) figure 16-26. dspi modified transfer format (mtfe=1, cpha=0, f sck = f sys /2) d0 d1 d2 dn d0 d1 d2 dn d0 d1 d2 dn slave samples sout smpl_pt=2 smpl_pt=1 dspi samples sin, smpl_pt=0 tvd_sl tsys tcsc tvd_sl tasc thd_sl tsu_sl thd_ms tsu_ms 13 24 5 6 2n+2 2n+1 sys clk pcs sout of ext slave sck sout sout of dspi slave d0 d1 d2 dn d0 d1 d2 dn slave samples sout dspi samples sin tcsc tvd_sl tasc thd_sl tsu_sl tsu_ms thd_ms sys clk pcs sin sck sout
deserial serial peripheral interface (dspi) 16-38 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 16-27. dspi modified transfer format (mtfe=1, cpha=0, f sck = f sys /3) 16.4.4.4 modified spi transfer format (mtfe = 1, cpha = 1) figure 16-28 - 16-30 show the modified transfer format for cpha = 1. only th e condition, where cpol = 0 is shown. at the start of a tran sfer the dspi asserts th e pcs signal to the slave device. after the pcs to sck delay has elapsed the master and the slave put data on their sout pins at the first edge of sck. the slave samples the master sout signal on the even numbered edges of sck. the master samples the slave sout signal on the odd numbered sck edges starting with th e third sck edge. the slave samples the last bit on the last edge of th e sck. the master samples the last slave sout bit one half sck cycle after the last edge of sck. no cl ock edge will be visibl e on the master sck pin dur ing the sampling of the last bit. the sck to pcs delay must be greater or equal to half of the sck period. figure 16-28. dspi modified transfer format (mtfe=1, cpha=1, f sck = f sys /2) d0 d1 d2 dn d0 d1 d2 dn slave samples sout dspi samples sin tcsc tvd_sl tasc thd_sl tsu_sl thd_ms tsu_ms sys clk pcs sin sck sout d0 d1 d2 dn d0 d1 d2 dn slave samples sout dspi samples sin tcsc tvd_sl tasc thd_sl tsu_sl thd_ms tsu_ms sys clk pcs sin sck sout 1 2 3 4 5 6 7 8 2n+1 2n+2
deserial serial peripheral interface (dspi) freescale semiconductor 16-39 pxs20 microcontroller reference manual, rev. 1 figure 16-29. dspi modified transfer format (mtfe=1, cpha=1, f sck = f sys /3) figure 16-30. dspi modified transfer format (mtfe=1, cpha=1, f sck = f sys /4) 16.4.4.5 continuous selection format some peripherals must be deselected between every transfer. other peripherals must remain selected between several sequential se rial transfers. the continuous selecti on format provides the flexibility to handle both cases. the continuous sel ection format is enabled for the spi configuration by setting the cont bit in the spi command. when the cont bit = 0, the dspi drives the asserted ch ip select signals to thei r idle states in between frames. the idle states of the ch ip select signals are selected by the pcsisn bits in the dspi_mcr. figure 16-31 shows the timing diagram for two four-bit transfers with cpha = 1 and cont = 0. d0 d1 d2 dn d0 d1 d2 dn slave samples sout dspi samples sin tcsc tvd_sl tasc thd_sl tsu_sl thd_ms tsu_ms sys clk pcs sin sck sout d0 d1 d2 dn d0 d1 d2 dn slave samples sout dspi samples sin tcsc tvd_sl tasc thd_sl tsu_sl thd_ms tsu_ms sys clk pcs sin sck sout
deserial serial peripheral interface (dspi) 16-40 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 16-31. example of non-continuous format (cpha=1, cont=0) when the cont bit = 1, the pcs signal remains asserted for the duration of the two transfers. the delay between transfers (t dt) is not inserted between the transfers. figure 16-32 shows the timing diagram for two four-bit transfers with cpha = 1 and cont = 1. figure 16-32. example of continuous transfer (cpha=1, cont=1) you must fill the txfifo with the number of entrie s that will be concatenat ed together under one pcs assertion for both master and slav e before the txfifo becomes empty. for example: while transmitting in master mode, you should ensure th at the last entry in the txfifo, after which txfifo becomes empty, must have the cont bit in command frame as deasse rted (i.e. cont bit = 0) .while operating in slave mode, it should be ensured that when the last-entry in the txfifo is complete ly transmited (i.e. the t csc t dt t csc sck pcsx sck master sout master sin t csc = pcs to sck delay t dt = delay after transfer (mi nimum cs negation time) (cpol = 0) (cpol = 1) t asc t asc = after sck delay t csc t csc sck pcs sck master sout master sin t csc = pcs to sck delay (cpol = 0) (cpol = 1) t asc (cpol = 0) sck t asc = after sck delay
deserial serial peripheral interface (dspi) freescale semiconductor 16-41 pxs20 microcontroller reference manual, rev. 1 corresponding tcf flag is as serted and txfifo is empt y) the slave should be de -selected for any further serial communication; else an underflow error occurs. the tx fifo must be cleared before in itiating any spi configuration transfer. when the dspi is in spi configurat ion, ctar0 must be used initially. at the start of each spi frame transfer, the ctar specified by the ctas for the frame must be ctar0. when the dspi is in dsi configur ation, the ctar specified by the dsic tas field must be used at all times. when the dspi is in csi configurat ion, the ctar selected by the dsicta s field must be used initially. at the start of a spi frame transfer, the ctar specif ied by the ctas value (which is ctar0) for the frame shall be used. at the star t of a dsi frame transfer, the ctar spec ified by the dsictas fi eld must be used. note when in continuous sck mode, for th e spi transfer ctar0 must always be used, and the tx-fifo must be clear using the mcr.clr_txf field before initiating transfer. when using dspi with continuous selection follow these rules: ? all transmit commands must have the same pcsn bits programming ? the dspi_ctars, selected by transmit commands , must be programmed with the same transfer attributes. only fmsz field can be progr ammed differently in these dspi_ctars. 16.4.5 continuous serial communications clock the dspi provides the option of ge nerating a continuous sck signal for slave peripherals that require a continuous clock. continuous sck is enabled by setting the cont_sck e bit in the dspi_mcr. co ntinuous sck is valid in all configurations. continuous sck is only supported for cpha=1. clearing cpha is ignored if the cont_scke bit is set. continuous sck is supported for modified transfer format. clock and transfer attributes fo r the continuous sck mode are set according to the following rules: ? ctar0 is used initially. at th e start of each spi fr ame transfer, the ctar specified by the ctas for the frame is used. ? the currently selected ctar remains in use unt il the start of a frame with a different ctar specified, or the continuous sck mode is terminated. it is recommended to keep the baud rate the same while using the continuous sck. switching clock polarity between frames while usi ng continuous sck can cause errors in the transfer. continuous sck operation is not guaranteed if the dspi is put into the external stop mode or module disable mode. enabling continuous sck disables the pcs to sck delay and the delay after transfer (t dt ) is fixed to one sck cycle. figure 16-33 shows timing diagram for conti nuous sck format with continuous selection disabled.
deserial serial peripheral interface (dspi) 16-42 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 note when in continuous sck mode, for th e spi transfer ctar0 must always be used, and the tx-fifo must be clear using the mcr.clr_txf field before initiating transfer. figure 16-33. continuous s ck timing diagram (cont=0) if the cont bit in the tx fifo en try is set, pcs remains asserted be tween the transfers. under certain conditions, sck can continue with pcs asserted, but with no data being shifted out of sout (sout pulled high). this can cause the slave to recei ve incorrect data. those conditions include: ? continuous sck with cont bit set, but no data in the transmit fifo. ? continuous sck with cont bit set a nd entering stopped state (refer to section 16.4.1, start and stop of dspi transfers ). ? continuous sck with cont bit set and en tering stop mode or module disable mode. figure 16-34 shows timing diagram for continuous sck fo rmat with continuous selection enabled. figure 16-34. continuous s ck timing diagram (cont=1) t dt sck pcs sck master sout master sin (cpol = 0) (cpol = 1) sck pcs sck master sout master sin (cpol = 0) (cpol = 1) transfer 1 transfer 2
deserial serial peripheral interface (dspi) freescale semiconductor 16-43 pxs20 microcontroller reference manual, rev. 1 16.4.6 interrupts/dma requests the dspi has several conditions th at can only generate interrupt re quests and two conditions that can generate interrupt or dma request. table 16-24 lists these conditions. each condition has a flag bit in the dspi status register (dspi_sr) and an request enable bit in the dspi dma/interrupt request select and enable register (dspi_rser). the tx fifo fill flag (tfff) and rx fifo drain flag (rfd f) generate interrupt requests or dma requests dependi ng on the tfff_dirs and rfdf_dirs bits in the dspi_rser. the dspi module also provides a globa l interrupt request line, which is asserted when any of individual interrupt requests lines is asserted. 16.4.6.1 end of queue interrupt request the end of queue request indicates that the end of a transmit queue is reached. the end of queue request is generated when the eoq bit in the executing spi command is set and the eoqf_re bit in the dspi_rser is set. 16.4.6.2 transmit fifo fill interrupt or dma request the transmit fifo fill reque st indicates that the tx fifo is not fu ll. the transmit fifo fill request is generated when the number of entries in the tx fifo is less than the maximum number of possible entries, and the tfff_re bit in the dspi_rser is set. th e tfff_dirs bit in the d spi_rser selects whether a dma request or an interrupt request is generated. 16.4.6.3 transfer complete interrupt request the transfer complete request indicates the end of th e transfer of a serial frame. the transfer complete request is generated at the end of each frame tran sfer when the tcf_re bit is set in the dspi_rser. 16.4.6.4 transmit fifo unde rflow interrupt request the transmit fifo underflow re quest indicates that an underflo w condition in the tx fifo has occurred. the transmit underfl ow condition is detected only for the dspi, operating in slave mode and spi configuration. the tfuf bit is set when the tx fifo of a dspi is empty, and a tr ansfer is initiated from table 16-24. interrupt and dma request conditions condition flag interrupt dma end of queue (eoq) eoqf x tx fifo fill tfff x x transfer complete tcf x tx fifo underflow tfuf x rx fifo drain rfdf x x rx fifo overflow rfof x
deserial serial peripheral interface (dspi) 16-44 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 an external spi master. if th e tfuf bit is set while the tfuf_re bit in the dspi_rser is set, an interrupt request is generated. 16.4.6.5 receive fifo drai n interrupt or dma request the receive fifo drain request indicates that the rx fifo is not empty. the receive fifo drain request is generated when the number of entries in th e rx fifo is not zero, and the rfdf_re bit in the dspi_rser is set. the rfdf_dirs bit in the ds pi_rser selects whether a dma request or an interrupt request is generated. 16.4.6.6 receive fifo o verflow interrupt request the receive fifo overflow request indicates that an overflow condition in the rx fifo has occurred. a receive fifo overflow reque st is generated when rx fifo and shift regi ster are full and a transfer is initiated. the rfof_re bit in the dspi_rser must be set for the interrupt request to be generated. depending on the state of the rooe bit in the dspi_mcr, the data from the transfer that generated the overflow is either ignored or shifted in to the shift re gister. if the rooe bit is set, the incoming data is shifted in to the shift register. if the rooe bit is cleared, the in coming data is ignored. 16.4.7 power saving features the dspi supports two power-saving strategies: ? external stop mode ? module disable mode - clock gating of non-memory mapped logic 16.4.7.1 . stop mode (external stop mode) the dspi supports the stop mode prot ocol. when a request is made to enter external stop mode, the dspi block acknowledges the request . if a se rial transfer is in pr ogress, the dspi waits unt il it reaches the frame boundary before it is ready to have its clocks s hut off .while the clocks are shut off, the dspi memory-mapped logic is not accessible. the states of the interrupt and dma request signals cannot be changed while in external stop mode. 16.4.7.2 module disable mode module disable mode is a block-spec ific mode that the dspi can ente r to save power. host cpu can initiate the module disable mode by se tting the mdis bit in the dspi_mcr. when the mdis bit is set, the dspi negates clock enable signal at the next frame boundary. if implemented, the clock enable signal can stop the cl ock to the non-memory mapped logic. when clock enable is negated, the dspi is in a dormant state, but the memory mapped regi sters are still accessible. certain read or write operations ha ve a different effect when the d spi is in the module disable mode. reading the rx fifo pop re gister does not change the state of the rx fifo. like wise, writing to the tx fifo push register does not change the state of the tx fi fo. clearing either of the fifos has no effect in the module disable mode. changes to the dis_tx f and dis_rxf fields of the dspi_mcr have no effect in the module disable mode. in the module disable mode, al l status bits and regist er flags in the dspi
deserial serial peripheral interface (dspi) freescale semiconductor 16-45 pxs20 microcontroller reference manual, rev. 1 return the correct values when r ead, but writing to them has no ef fect. writing to the dspi_tcr during module disable mode has no effect. interrupt and dm a request signals cannot be cleared while in the module disable mode. 16.5 initialization/application information 16.5.1 how to manage dspi queues the queues are not part of the dspi, but the dspi includes features in s upport of queue management. queues are primarily supported in spi configuration. 1. when dspi executes last comm and word from a queue, the eoq bit in the command word is set to indicate to the dspi that this is the last entry in the queue. 2. at the end of the tran sfer, corresponding to the command word with eoq set is sampled, the eoq flag (eoqf) in the dspi_sr is set. 3. the setting of the eoqf flag disables serial transmission and reception of data, putting the dspi in the stopped state. the txrxs bit is cleared to indicate the stopped state. 4. the dma can continue to fill tx fifo until it is full or step 5 occurs. 5. disable dspi dma transfers by disabling the dma enable request for the dma channel assigned to tx fifo and rx fifo. this is done by clea ring the corresponding dma en able request bits in the dma controller. 6. ensure all received data in rx fifo has been transferred to me mory receive queue by reading the rxcnt in dspi_sr or by checking rfdf in th e dspi_sr after each read operation of the dspi_popr. 7. modify dma descriptor of tx and rx channels for new queues 8. flush tx fifo by writing a ?1? to the clr_tx f bit in the dspi_mcr. flush rx fifo by writing a ?1? to the clr_rxf bit in the dspi_mcr. 9. clear transfer count eith er by setting ctcnt bit in the command word of the first entry in the new queue or via cpu writing directly to spi_tcnt field in the dspi_tcr. 10. enable dma channel by enabling the dma enable request for th e dma channel assigned to the dspi tx fifo, and rx fifo by setting th e corresponding dma set enable request bit. 11. enable serial transmission and serial reception of data by clearing the eoqf bit. 16.5.2 switching master and slave mode when changing modes in the dspi, follow the steps below to gua rantee proper operation. 1. halt the dspi by se tting dspi_mcr[halt]. 2. clear the transmit and receive fifos by writ ing a 1 to the clr_txf and clr_rxf bits in dspi_mcr. 3. set the appropriate mode in dspi_mcr [mstr] and enable the dspi by clearing dspi_mcr[halt].
deserial serial peripheral interface (dspi) 16-46 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 16.5.3 baud rate settings table 16-25 shows the baud rate that is ge nerated based on the combination of the baud rate prescaler pbr and the baud rate scaler br in the dspi_ctar regist ers. the values calculated assume a 100 mhz system frequency and the double baud rate dbr bit is clear. 16.5.4 delay settings table 16-26 shows the values for th e delay after transfer (t dt ) and cs to sck delay (t csc ) that can be generated based on the prescaler values and the scaler values set in th e dspi_ctar registers. the values calculated assume a 100 mhz system frequency. table 16-25. baud rate values (bps) baud rate divider prescaler values 2357 baud rate scaler values 2 25.0m 16.7m 10.0m 7.14m 4 12.5m 8.33m 5.00m 3.57m 6 8.33m 5.56m 3.33m 2.38m 8 6.25m 4.17m 2.50m 1.79m 16 3.12m 2.08m 1.25m 893k 32 1.56m 1.04m 625k 446k 64 781k 521k 312k 223k 128 391k 260k 156k 112k 256 195k 130k 78.1k 55.8k 512 97.7k 65.1k 39.1k 27.9k 1024 48.8k 32.6k 19.5k 14.0k 2048 24.4k 16.3k 9.77k 6.98k 4096 12.2k 8.14k 4.88k 3.49k 8192 6.10k 4.07k 2.44k 1.74k 16384 3.05k 2.04k 1.22k 872 32768 1.53k 1.02k 610 436
deserial serial peripheral interface (dspi) freescale semiconductor 16-47 pxs20 microcontroller reference manual, rev. 1 16.5.5 calculation of fifo pointer addresses complete visibility of the tx and rx fifo contents is available th rough the fifo registers, and valid entries can be identified through a memory mapped pointer and a memory mapped counter for each fifo. the pointer to the first-in entry in each fifo is me mory mapped. for the tx fifo the first-in pointer is the transmit next pointer (txnxtptr). for the rx fi fo the first-in pointer is the pop next pointer (popnxtptr). figure 16-35 illustrates the concept of first-in and last-in fifo entries along with the fifo counter. the tx fifo is chosen for the illust ration, but the concepts carry over to the rx fifo. see section 16.4.2.4, transmit first in first out (tx fifo) buffering mechanism , and section 16.4.2.5, receive first in first out (rx fifo) buffering mechanism , for details on the fifo operation. table 16-26. delay values delay prescaler values 1357 delay scaler values 2 20.0 ns 60.0 ns 100.0 ns 140.0 ns 4 40.0 ns 120.0 ns 200.0 ns 280.0 ns 8 80.0 ns 240.0 ns 400.0 ns 560.0 ns 16 160.0 ns 480.0 ns 800.0 ns 1.1 ? s 32 320.0 ns 960.0 ns 1.6 ? s2.2 ? s 64 640.0 ns 1.9 ? s3.2 ? s4.5 ? s 128 1.3 ? s3.8 ? s6.4 ? s9.0 ? s 256 2.6 ? s7.7 ? s 12.8 ? s 17.9 ? s 512 5.1 ? s 15.4 ? s 25.6 ? s 35.8 ? s 1024 10.2 ? s 30.7 ? s 51.2 ? s 71.7 ? s 2048 20.5 ? s 61.4 ? s 102.4 ? s 143.4 ? s 4096 41.0 ? s122.9 ? s 204.8 ? s 286.7 ? s 8192 81.9 ? s245.8 ? s 409.6 ? s 573.4 ? s 16384 163.8 ? s491.5 ? s 819.2 ? s 1.1 ms 32768 327.7 ? s983.0 ? s 1.6 ms 2.3 ms 65536 655.4 ? s 2.0 ms 3.3 ms 4.6 ms
deserial serial peripheral interface (dspi) 16-48 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 16-35. tx fifo pointers and counter 16.5.5.1 address calculation for the firs t-in entry and last-i n entry in the tx fifo the memory address of the first-in entry in th e tx fifo is computed by the following equation: eqn. 16-7 the memory address of the last-in entry in the tx fifo is computed by the following equation: eqn. 16-8 tx fifo base - base address of tx fifo txctr - tx fifo counter txnxtptr - transmit next pointer tx fifo depth - transmit fifo depth, implementation specific 16.5.5.2 address calculation for the firs t-in entry and last-i n entry in the rx fifo the memory address of the first-in entry in th e rx fifo is computed by the following equation: eqn. 16-9 the memory address of the last-in entry in th e rx fifo is computed by the following equation: eqn. 16-10 rx fifo base - base address of rx fifo - - entry a (first in) entry b entry c entry d (last in) - - push tx fifo register transmit next data pointer shift register sout +1 -1 tx fifo counter tx fifo base first-in entry address tx fifo base 4 txnxtptr ? ?? + = last-in entry address tx fifo base 4 txctr txnxtptr 1 ? + ?? ? mod txfifodepth ?? + = first-in entry address rx fifo base 4 popnxtptr ? ?? + = last-in entry address rx fifo base 4 rxctr popnxtptr 1 ? + ?? ? mod (rxfifodepth) + =
deserial serial peripheral interface (dspi) freescale semiconductor 16-49 pxs20 microcontroller reference manual, rev. 1 rxctr - rx fifo counter popnxtptr - pop next pointer rx fifo depth - receive fifo depth, implement ation specific
deserial serial peripheral interface (dspi) 16-50 freescale semiconductor pxs20 microcontroller reference manual, rev. 1
e200z4d core complex overview freescale semiconductor 17-1 pxs20 microcontroller reference manual, rev. 1 chapter 17 e200z4d core complex overview this chapter provides an overview of the e200z4d microprocessor core pres ent in this device. it includes the following: ? an overview of the core, including the block diagram ( figure 17-1 ) ? a summary of the feature set for this core (see section 17.2, features ) ? a description of th e execution units (see section 17.2.1, execution unit features ) ? a description of the memory management architecture (see section 17.2.3, memory management unit features ) ? high-level details of the external core compex interface (see section 17.2.4, exernal core complex interface features ) ? high-level details of the nexus 3+ features (see section 17.2.5, nexus 3+ features ) ? a summary of the programming model for this core (see section 17.3, programming model ) ? an overview of the register set (see section 17.3.1, register set ) ? an overview of the instruction set (see section 17.3.2, instruction set) ? an overview of interrupts and exception handling (see section 17.3.3, interrupts and exception handling ) ? a summary of instruction pipeline and flow (see section 17.4, microarchitecture summary ) 17.1 overview the e200z4d processor family is a set of cpu core s that implement low-cost versions of power architecture technology. the e200z4d core is a dual- issue, 32-bit design with 64-bit general-purpose registers (gprs). the e200z4d integrates a cpu co re, a memory management unit (mmu), a 4-kbyte instruction cache, and a nexus class 3+ real-tim e debug unit. separate instruction and data ahb 2.v6 system interfaces are provided. the e200z4d is compliant with the power architectur e instruction set architecture (isa). it does not support power architecture isa floating- point instructions in hardware, but traps them so they can be emulated by software. instructions of the embedded floating-point categor y are provided to support r eal-time single-precision embedded numerics operations usi ng the general-purpose registers. instructions of the signal processing extension ( spe) category are provided to support real-time simd fixed-point and single-precision embe dded numerics operations using the general-purpose registers. all arithmetic instructions that execut e in the core operate on data in the general-purpose registers (gprs). the gprs have been extended to 64-bits in order to support vector instruc tions defined by the spe category. these instructions operate on a vector pair of 16-bit or 32-bit data types and de liver vector and scalar results. in addition to the base power architecture isa em bedded category instruction set, the core also implements the variable-l ength encoding category (vle), which pr ovides improved code density. see the
e200z4d core complex overview 17-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 eref and supplementary vle program ming environments manual ( vlepem) for more information about the vle extension. the processor integrates a pair of integer execution units, a branch control unit, instruction fetch unit and load/store unit, and a multi-ported re gister file capable of sustaining si x read and three wr ite operations per clock cycle. most integer instructions execute in a single clock cycle. branch target prefetching is performed by the branch unit to allow single-cycle branches in many cases. throughout the remainder of this document, the core is referred to as the ?e200z4d? when speaking of e200z4d-specific implementations, the ?e200z4xx? when speaking of a specific variety of e200z4 core, or ?e200? when referring to the whole e200 family. figure 17-1 shows the block diagram for the device. figure 17-1. e200z4d block diagram 17.2 features key features of the e200z4d are summarized as follows: ? dual-issue, 32-bit power isa-compliant core ? implementation of the vle cate gory for reduced code footprint ? in-order execution and retirement instruction bus interface unit software-managed instruction memory unit mas registers 32 gprs (64-bit) xer cr 1-, 4-, 16-, 64-, 256 kb, 1-, 4-, 16-, 64-, 256 mb, 1-, 4 gb page sizes execution units additional load/store write-back stage two/four instructions 32 64 n address data control additional features ? once/nexus 1/nexus 3 control logic ? dual ahb 2.v6 buses ? spe (simd) ? embedded scalar/ vector floating-point ? power management ?time base/decrementer counter + l1 unified mmu unit ctr lr two-instruction, in-order dispatch two-instruction, in-order write-back ? ? ? 16-entry fully associative tlb ea calc two stages of instruction executions fetch unit branch processing unit instruction/control unit instruction buffer (8/16 instructions) decode 8-entry branch stage + ea calc one-stage fetch program counter target buffer data bus interface unit execute stage 32 64 n address data control sprs 2- or 4-way set-associative 4-kbyte instruction cache executes all e200z4d instructions (including power isa base, spe, and vle categories). as many as two instructions can execute simultaneously.
e200z4d core complex overview freescale semiconductor 17-3 pxs20 microcontroller reference manual, rev. 1 ? precise exception handling ? branch processing unit (bpu) ? dedicated branch address calculation adder ? branch target prefetching using an 8-entry branch target buffer (btb) ? supports independent instruction and data accesse s to different memory subsystems, such as sram and flash memory by means of independent instruction and data bus interface units. ? load/store unit ? 64-bit general-purpose register file ? dual advanced high-performanc e (ahb) 2.v6 64-bit system buses ? memory management unit (mmu) with 16-entry fu lly associative tlb and multiple page-size support ? 4 kb, 2/4-way set-associative instruction cache ? signal processing extension uni t, version 1.1 supporting simd fi xed-point operations using the 64-bit general-purpose register file ? embedded floating-point (fpu) unit, vers ion 2 supporting scalar and vector simd single-precision floating-point operations using the 64-bit general-purpose register file ? nexus class 3+ real -time development unit ? power management ? low power design?extensive clock gating ? power saving modes: doze, nap, sleep, wait ? dynamic power management of execution units, cache, and mmu see the following sections for more details about specific units. 17.2.1 execution unit features the following subsections describes the execution units? main features. 17.2.1.1 instructi on unit features the instruction unit feat ures the following: ? 64-bit path to cache supports fetching of two 32-bit power isa instructions or four 16-bit vle instructions per clock cycle. ? instruction buffer holds up to eight 32-bit po wer isa instructions or sixteen 16-bit vle instructions. ? dedicated program counter (pc) increm enter supports instruction prefetches. ? branch unit with dedicated branch address adde r and branch target buffer supports single-cycle execution of successfully predicted branches.
e200z4d core complex overview 17-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 17.2.1.2 integer unit features the integer units feature support fo r single-cycle execution of most integer instructions, as follows: ? 32-bit au for arithmetic and comparison operations ? 32-bit lu for logical operations ? 32-bit priority encoder fo r count-leading-zeros function ? 32-bit single-cycle barrel shifte r for static shifts and rotates ? 32-bit mask unit for data masking and insertion ? divider logic for signed and unsigned divide in ? 14 clock cycles with minimized execution timing ? pipelined 32 ? 32 hardware multiplier array supports 32 ? 32 ? 32 multiply with 2 clock latency, 1 clock throughput 17.2.1.3 load/store unit features the load/store unit supports load, store, and load mu ltiple/store multiple instructions by means of the following: ? 32-bit effective address adder fo r data memory address calculations ? pipelined operation supports throughput of one load or store operation per cycle ? dedicated 64-bit interface to me mory supports saving and restoring of up to two regi sters per cycle for load multiple and store multiple word instructions ? two-cycle load latency ? big- and little-endian support ? misaligned access support 17.2.2 l1 cache features the l1 cache features the following: ? 4 kb, 2- or 4-way configurable set-associative instruction cache ? 64-bit data, 32-bit address bus plus attributes and control ? 32-byte line size ? cache line locking ? way allocation ? tag and data parity or multi-bit edc protec tion with correction/auto-invalidation capability ? virtually indexed, physically tagged ? pseudo round-robin replacement algorithm ? line-fill buffer ? hit under fill
e200z4d core complex overview freescale semiconductor 17-5 pxs20 microcontroller reference manual, rev. 1 17.2.3 memory management unit features the memory management unit features the following: ? virtual memory support ? 32-bit virtual and physical addresses ? 8-bit process identifier ? 16-entry fully associative tlb ? hardware assist for tlb miss exceptions ? per-entry multiple page size support from 1 kbyte to 4 gbyte ? entry flush protection ? software managed by tlbre , tlbwe , tlbsx , tlbsync , and tlbivax instructions ? freescale eis mmu ar chitecture compliant ? support for external control of en try matching for a subset of ti d values to support non-intrusive runtime mapping modifications 17.2.4 exernal core complex interface features the core complex interface features the following: ? independent instruction and data buses ? advanced microcontroller bus arch itecture (amba) ahb 2.v6 protocol ? 32-bit address bus, 64-bit data bus , plus attributes and control ? separate unidirectional 64-bi t read and write data buses ? support for hclk running at a slower rate than cpu clock 17.2.5 nexus 3+ features the nexus 3+ module provide s real-time development ca pabilities for e200z4d pro cessors in compliance with the ieee-isto 5001?-2003. the ?3+? suffix indi cates that some nexus class 4 features are available. a portion of the pin interface (the jtag port) is also shared with the once/nexus 1 unit. the following features are implemented: ? program trace by means of branch trace messaging. ? branch trace messaging displays program flow di scontinuities (direct a nd indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between the discontinuities. thus, stat ic code may be traced. ? data trace by means of data write messaging and data read messaging. ? provides the capability for the de velopment tool to trace reads and/ or writes to selected internal memory resources. ? ownership trace by means of ow nership trace messaging (otm).
e200z4d core complex overview 17-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? otm facilitates ownership trace by providing vi sibility of which pr ocess id or operating system task is activated.an owne rship trace message is transmitte d when a new process/task is activated, allowing the developmen t tool to trace ownership flow. ? allows enhanced download/upload capabilities. ? data acquisition messaging ? allows code to be instrumented to export cust omized information to the nexus auxiliary output port. ? watchpoint messaging by means of the auxiliary interface ? watchpoint trigger enable of pr ogram and/or data trace messaging ? run-time access to the processor me mory map by means of the jtag port all features are controllable and conf igurable by means of the jtag port. 17.3 programming model this section describes the register model, instruction model, and the in terrupt model as they are defined by the power isa, freescale eis, and the e200z4d implementation. 17.3.1 register set figure 17-2 and figure 17-3 show the complete e200z4d re gister set, including the se ts of the registers that are accessible in supervisor mode and the set of regist ers that are accessible in user mode. the number to the right of the special-purpose regi sters (sprs) is the decimal number us ed in the instruction syntax to access the register. for example, the inte ger exception register (xer) is spr 1. figure 17-2 shows the registers that can be accessed by supervisor-level soft ware. user-level software can access only those registers listed in figure 17-3 .
e200z4d core complex overview freescale semiconductor 17-7 pxs20 microcontroller reference manual, rev. 1 figure 17-2. e200z4d supervisor mode programmer?s model esr spr 62 exception syndrome data exception address spr general exception handling/control registers save and restore mmu assist memory management registers machine state msr pvr processor control registers decrementer timers time base (writeonly) mas0 mas1 mas2 mas3 mas4 mas6 spr 624 spr 625 spr 626 spr 627 spr 628 spr 630 sprg0 sprg1 sprg2 sprg3 sprg4 sprg5 sprg6 sprg7 sprg8 sprg9 spr 272 spr 273 spr 274 spr 275 spr 276 spr 277 spr 278 spr 279 spr 604 spr 605 dear spr 61 spr 26 spr 27 spr 58 spr 59 spr 574 spr 575 spr 570 spr 571 tbl spr 284 tbu spr 285 dec spr 22 process id pid0 spr 48 processor id pir spr 286 decar spr 54 ivor0 ivor1 ivor15 spr 400 spr 401 spr 415 interrupt vector prefix ivpr spr 63 interrupt vector offset control and status tcr spr 340 tsr spr 336 spr 528 spr 530 ivor32 2 ivor34 2 processor version control & configuration spr 1012 spr 1015 spr 688 spr 689 hardware implementation dependent 1 hid0 hid1 spr 1008 spr 1009 mmucsr0 mmucfg tlb0cfg tlb1cfg spr 9 general-purpose registers count register ctr spr 8 link register lr condition register cr gpr0 gpr1 gpr31 spr 1 xer xer general registers spr 256 user spr usprg0 sp e status and control spr 512 spefscr spe register spr 287 system version 2 svr spr 1023 machine check syndrome register mcsr spr 572 btb control 1 spr 1013 bucsr btb register srr0 srr1 csrr0 csrr1 dsrr0 2 dsrr1 2 mcsrr0 2 mcsrr1 2 machine check address register mcar spr 573 accumulator acc cache control spr 1011 l1csr1 cache registers spr 515 cache configuration (read-only) l1cfg0 spr 959 l1finv1 spr 516 l1cfg1 iac1 iac2 iac3 iac4 iac5 iac6 iac7 iac8 debug registers 2 debug control dbcr0 dbcr1 dbcr2 dbcr3 1 dbcr4 1 dbcr5 1 dbcr6 1 dberc0 1 spr 308 spr 309 spr 310 spr 561 spr 563 spr 564 spr 603 spr 569 instruction address compare spr 312 spr 313 spr 314 spr 315 spr 565 spr 566 spr 567 spr 568 data address compare dac1 dac2 spr 316 spr 317 debug status dbsr spr 304 debug counter 1 dbcnt spr 562 data value compare (64-bit) dvc1 dvc2 spr 318 spr 319 1 - these e200-specific registers may not be supported by ot her processors built on power architecture technology 2 - optional registers defined by the power isa embedded architecture 3 - read-only registers cache access registers cdacntl cdadata dcr 351 dcr 350 psu registers pscr pssr pshr pslr dcr 272 dcr 273 dcr 274 dcr 275 device control registers (dcrs) 1 psctr psuhr psulr dcr 276 dcr 277 dcr 278
e200z4d core complex overview 17-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 17-3 shows the user-mode special-purpose registers. figure 17-3. e200z4d user mode programmer?s model sprs the gprs are accessed through instru ction operands. access to other regi sters can be explicit, by using instructions for that purpose such as the move to special -purpose register ( mtspr ) and move from special-purpose register ( mfspr ) instructions. access to ot her registers can also be implicit, as part of the execution of an instruction. some registers are accessed both explic itly and implicitly. 17.3.1.1 processor vers ion register (pvr) the pvr contains the processor version identification for the cpu core. 012345678910111213141516171819202122232425262728293031 r 1 0 0 0 0 0 type version 0 0 0 0 minrev majrev 0 0 0 1 w reset10000001010101000000000000000001 figure 17-4. processor version register (pvr) table 17-1. pvr field descriptions field description type processor type 010101 = e200z4d core version processor version 0100 e200z4d core on this device minrev minor revision number majrev major revision number timers (read only) time base spr 515 cache configuration l1cfg0 tbl spr 268 tbu spr 269 cache register (read-only) spr 9 general-purpose registers count register ctr spr 8 link lr condition register cr spr 1 xer xer general registers spr general (read-only) control registers sprg4 sprg5 sprg6 sprg7 spr 260 spr 261 spr 262 spr 263 spr 256 user spr usprg0 spe status and control register spr 512 spefscr category registers gpr0 gpr1 ? ? gpr31 accumulator acc spr 516 l1cfg1 ?
e200z4d core complex overview freescale semiconductor 17-9 pxs20 microcontroller reference manual, rev. 1 17.3.1.2 processor id register (pir) the processor id for each of the two cpu cores is contained in its own processor id register (pir). the contents of the pir are a re flection of hardware input si gnals to the core following reset. this register may be written by software to mo dify the default reset value. this register value can be used by the application software to determine the core actually running the software. 17.3.1.3 system version register (svr) the svr contains system versio n information for this device. 17.3.2 instruction set the e200z4d supports the power is a instruction set for 32-bit embedded implementations. this is composed primarily of the user-level instructions defined by the user instruction set architecture (uisa). the e200z4d does not include the power isa floating-po int, load string, or stor e string instructions. the e200z4d core implements the fo llowing architectural extensions: ? the vle category ? the integer select category (isel) ? enhanced debug and the debug notif y halt instruction categories ? the machine check category 012345678910111213141516171819202122232425262728293031 r 0 0 0 0 0 0 cpuid w reset000000000000000000000000 core-depe ndent figure 17-5. processor id register (pir) table 17-2. pir field descriptions field description cpuid processor id 012345678910111213141516171819202122232425262728293031 r 0 0 0 0 0 0 ver w reset00000000000000000000000000000000 figure 17-6. system version register (svr) table 17-3. svr field descriptions field description ver device version
e200z4d core complex overview 17-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? the wait category ? the volatile context save/restore category ? the embedded floating- point unit, version 2 ? the signal processing extension unit, version 1.1 ? the cache line locking category ? the enhanced reservations category 17.3.3 interrupts and exception handling the e200z4d core supports an extended exception handl ing model with nested interrupt capability and extensive interrupt vector programmabi lity. in general, interrupt processi ng begins with an exception that occurs due to external conditions, errors, or program execution problems. when an exception occurs, the processor checks whether interrupt processing is enabled for that pa rticular exception. if enabled, the interrupt causes the state of the processor to be save d in the appropriate registers and begins execution of the handler located at the associated vect or address for that particular exception. once the handler is executing, the implementation may need to check bits in the exception syndrome register (esr), the machine check syndrome register (mcsr), or the signal processing and embedded floating-point status and control regi ster (spefscr) to verify the specific cause of the exception and take appropriate action. the core complex supports the interrupts described in table 17-4. table 17-4. interrupt registers register description noncritical interrupt registers srr0 save/restore register 0?on noncritical interrupts, stores either the address of the instruction causing the exception or the address of the in struction that executes after the rfi instruction. srr1 save/restore register 1?saves machine state on noncritical interrupts and restores machine state after an rfi instruction is executed. critical interrupt registers csrr0 critical save/restore register 0?on critical in terrupts, stores either t he address of the instruction causing the exception or the address of th e instruction that executes after the rfci instruction. csrr1 critical save/restore register 1?saves machine stat e on critical interrupts and restores machine state after an rfci instruction is executed. debug interrupt registers dsrr0 debug save/restore register 0?on debug interrup ts, stores either the ad dress of the instruction causing the exception or the address of th e instruction that executes after the rfdi instruction. dsrr1 debug save/restore register 1?saves machine st ate on debug interrupts and restores machine state after an rfdi instruction is executed. machine check interrupts mcsrr0 machine check save/restore register 0?on machi ne check interrupts, stores either the address of the instruction causing the exceptio n or the address of the instruction that executes after the rfmci instruction.
e200z4d core complex overview freescale semiconductor 17-11 pxs20 microcontroller reference manual, rev. 1 each interrupt has an associated interrupt vector address, obtained by concatenating iv pr[32?47] with the address index in the associated ivor (that is, ivpr[32?47] || ivor n [48?59] || 0b0). the resulting address is that of the instruction to be executed wh en that interrupt occurs. ivpr and ivor values are indeterminate on reset and must be ini tialized by the system software using mtspr . table 17-5 lists ivor registers implemented on th e e200z4d and the associated interrupts. mcsrr1 machine check save/restore register 1?saves machine state on machine check interrupts and restores those values when an rfmci instruction is executed syndrome registers mcsr machine check syndrome register?saves machine check syndrome information on machine check interrupts. esr exception syndrome register?provides a syndrome to differentiate among the different kinds of exceptions that generate the same interrupt type. upon generation of a specific exception type, the associated bits are set and all other bits are cleared. spe interrupt registers spefscr signal processing and embedded floating-point stat us and control register?provides interrupt control and status as well as various condition bits as sociated with the operations performed by the spe. see ta bl e 1 7 - 5 for a list of the associated ivors. other interrupt registers dear data exception address register?contains the addre ss that was referenced by a load, store, or cache management instruction that caused an alignm ent, data tlb miss, or data storage interrupt. ivpr ivors together, ivpr[32?47] || ivor n [48?59] || 0b0 define the address of an interrupt-processing routine. see ta bl e 1 7 - 5 for more information. msr machine state register?defines t he state of the processor. when an interrupt occurs, it is updated to preclude unrecoverable interrupts from occurring during the initial portion of the interrupt handler table 17-5. exceptions and conditions ivor n interrupt type ivor n interrupt type none 1 system reset (not an interrupt) 9 ap un available (not used by this core) 0 2 critical input 10 decrementer 1 machine check 11 fixed-interval timer machine check (non-maskable interrupt) 12 watchdog timer 2 data storage 13 data tlb error 3 instruction storage 14 instruction tlb error 4 2 external input 15 debug 5 alignment 16?31 reserved 6 program 32 spe unavailable 7 floating-point unavailab le 33 spe data exception 8 system call 34 spe round exception table 17-4. interrupt registers (continued) register description
e200z4d core complex overview 17-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 17.4 microarchitecture summary the e200z4d processor utilizes a five-s tage pipeline for instruction exec ution. these stages operate in an overlapped fashion, allowing single clock-cycle instruction execution for most instructions. the stages are as follows: 1. instruction fetch 2. instruction decode/register file read/effective address calculation 3. execute 0/memory access 0 4. execute 1/memory access 1 5. register write-back the integer execution units consist of a 32-bit arithmetic unit, a logic unit, a 32-bit barrel shifter, a mask-insertion unit, a condition register manipulation unit, a count-leading-zer os unit, a 32 ? 32 hardware multiplier array, and result feed-forward hardwa re. integer unit 1 also s upports hardware division. most arithmetic and logical operations are executed in a single cycle with the exce ption of multiply, which is implemented with a 2-cycle pipeli ned hardware array, and the divide instructions. a c ount-leading-zeros unit operates in a single clock cycle. the instruction unit contains a pr ogram counter incrementer and dedi cated branch address adder to minimize delays during change-of-flow operations. sequential prefetching is performed to ensure a supply of instructions into the execution pipeline. branch target prefetching using the btb is performed to accelerate taken branches. prefetched instructions are placed into an 8-en try instruction buffer, with each entry capable of holding a single 32-bit inst ruction or a pair of 16-bit instructions. branch target addresses are calculat ed in parallel with branch inst ruction decode. c onditional branches that are not taken execute in a single clock cycle. br anches with successful bt b target prefetching have an effective execution time of one clock cycle if correctly predicted. all other taken branches have an execution time of two clock cycles. memory load and store operations are provided for byte, ha lf-word, word (32-bit) , and double-word data with automatic zero or sign extensi on of byte and half-word load data as well as optional byte reversal of data. these instructions can be pipelined to allow effective single-cycle throughput. load and store multiple word instructions allow low-overhead cont ext save and restore operations. the load/store unit contains a dedicated effective addr ess adder to allow effective addre ss generation to be optimized. there is a single load-to-use bubble for load instructions. the condition register unit supports the condition regist er (cr) and condition regi ster operations defined by the architecture. the conditio n register consists of eight 4-bit fiel ds that reflect the results of certain operations, such as move, integer and floating-point compare, arithmetic, and logical instructions. it also provides a mechanism for testing and branching. notes: 1 vector to [ p_rstbase[0:29] ] || 0b0. 2 autovectored external and critical input interrupts use this ivor. vectored interrupts supply an interrupt vector offset directly.
e200z4d core complex overview freescale semiconductor 17-13 pxs20 microcontroller reference manual, rev. 1 vectored and autovectored interrupt s are supported by the cpu. vectored interrupt support is provided to allow multiple interrupt sources to have unique in terrupt handlers invoked with no software overhead. the 64-bit general-purpose register fi le is used for source and destinat ion operands, and there is a unified storage model for single-precision fl oating-point data types of 32-bits and the normal integer type. low latency fixed-point and floating- point add, subtract, multiply, mu ltiply-add, multiply-sub, divide, compare, and conversion opera tions are provided. most ope rations can be pipelined. 17.5 availability of detailed documentation detailed documentation of the e200z4d core is provided in a separate co re reference manu al (crm). this crm is available online at http://www.freescale.com.
e200z4d core complex overview 17-14 freescale semiconductor pxs20 microcontroller reference manual, rev. 1
edma channel mux (dma_mux) freescale semiconductor 18-1 pxs20 microcontroller reference manual, rev. 1 chapter 18 edma channel mux (dma_mux) 18.1 introduction 18.1.1 overview the dma_mux allows to route 27 dma peripheral sour ces (called slots) to 16 dma channels. this is illustrated in figure 18-1 . figure 18-1. dma_mux block diagram 18.1.2 features the dma_mux provides these features: ? 27 peripheral slots (plus 6 always-on slots) can be routed to 16 channels ? 16 independently selectab le dma channels routers ? the first 4 channels additionally provide a trigger functionality source #1 source #2 source #3 dma channel #1 dma channel #0 dma_mux always #1 trigger #1 dma channel #15 trigger #4 always #6 source #27
edma channel mux (dma_mux) 18-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? each channel router can be assigned to one of 27 possible peri pheral dma slots or to one of the 6 always-on slots. 18.1.3 modes of operation the following operation modes are available: ? disabled mode in this mode, the dma channel is disabled. sinc e disabling and enabling of dma channels is done primarily via the dma conf iguration registers, this mode is us ed mainly as the reset state for a dma channel in the dma_mux. it may also be used to temporarily suspend a dma channel while reconfiguration of the sy stem takes place (e.g. changing the period of a dma trigger). ? normal mode in this mode, a dma source (such as dspi transmit or dspi rece ive for example) is routed directly to the specified dma channel. the operation of the dma_mux in this mode is completely transparent to the system. ? periodic trigger mode in this mode, a dma source may only request a dma transfer (such as when a transmit buffer becomes empty or a receive buffer becomes full) periodically. conf iguration of th e period is done in the registers of the periodic interrupt timer (p it). this mode is only available for channels 0?3. 18.2 external signal description 18.2.1 overview the dma_mux has no external pins. 18.3 memory map and register definition this section provides a detailed description of all memory-mapped registers in the dma_mux. table 18-1 shows the memory map for the dma_mux. all addresses are offsets; the absolute address may be computed by adding the specified offs et to the base address of the dma_mux. table 18-1. dma_mux memory map address use access base + 0x00 channel #0 configuration (chconfig0) r/w base + 0x01 channel #1 configuration (chconfig1) r/w .. .. .. base + #n-1 channel #n configuration (chconfig #n-1 ) 1 notes: 1 in the table n refers to the number of channels - 1 r/w
edma channel mux (dma_mux) freescale semiconductor 18-3 pxs20 microcontroller reference manual, rev. 1 all registers are accessible via 8-bit, 16-bit or 32-bit accesses. ho wever, 16-bit accesses must be aligned to 16-bit boundaries, and 32-bit accesses must be aligned to 32-bit boundaries. as an example, chconfig0 through chconfig3 are accessible by a 32-bit read/write to address ?base + 0x00?, but performing a 32-bit access to address ?base + 0x01? is illegal. 18.3.1 register descriptions the following memory-mapped regist ers are available in the dma_mux. 18.3.1.1 channel configuration registers each of the dma channels can be independently enab led/disabled and associat ed with one of the dma slots (peripheral slots or alwa ys-on slots) in the system. address: base + #n access: user read/write 01234567 r enbl trig source w reset00000000 figure 18-2. channe l configuration re gisters (chconfig #n ) table 18-2. chconfig xx field descriptions field description 7 enbl dma channel enable. enbl enables the dma channel 0 dma channel is disabled. this mode is primarily used during configuratio n of the dma_mux. the dma has separate channel enables/disables, which should be used to disable or re-configure a dma channel. 1 dma channel is enabled 6 trig dma channel trigger enable (for triggered channels only). trig enables the periodic trigger capability for the dma channel 0 triggering is disabled. if triggering is disabled, and the enbl bit is set, the dma channel will simply route the specified source to the dma channel. 1 triggering is enabled 5?0 source dma channel source (slot). source specifies which dma source, if any, is routed to a particular dma channel (see section 18.4, dma_mux request source slot mapping ). table 18-3. channel and trigger enabling enbl trig function mode 0 x dma channel is disabled disabled mode 1 0 dma channel is enabled with no triggering (transparent) normal mode 1 1 dma channel is enabled with triggering periodic trigger mode
edma channel mux (dma_mux) 18-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 note setting multiple chconf ig registers with the same source value will result in unpredictable behavior. note before changing the trigger or sour ce settings a dma ch annel must be disabled via the chconfig[ #n ].enbl bit. 18.4 dma_mux request source slot mapping table 18-4 defines the mapping of the dma_mux source sl ots to the interrupt request sources on the device. table 18-4 is valid for both instantiations of the dma_mux module. table 18-4. dma_mux source slot mapping dma_mux source slot # sour ce module source resource 1 dspi_0 dspi_tfff 2 dspi_0 dspi_rfdf 3 dspi_1 dspi_tfff 4 dspi_1 dspi_rfdf 5 dspi_2 dspi_tfff 6 dspi_2 dspi_rfdf 7ctu ctu 8 ctu fifo1 9 ctu fifo2 10 ctu fifo3 11 ctu fifo4 12 flexpwm_0 comp_val 13 flexpwm_0 capt 14 etimer_0 channel 0 15 etimer_0 channel 1 16 etimer_1 channel 0 17 etimer_1 channel 1 18 etimer_2 channel 0 19 etimer_2 channel 1 20 adc_0 dma 21 adc_1 dma 22 linflex_0 transmit 23 linflex_0 receive 24 linflex_1 transmit 25 linflex_1 receive
edma channel mux (dma_mux) freescale semiconductor 18-5 pxs20 microcontroller reference manual, rev. 1 18.5 dma_mux trigger inputs table 18-5 defines the signal sources for the trigger suppor t of the first 4 channels of the dma_mux. table 18-5 is valid for both instantiations of the dma_mux module. 18.6 functional description the primary purpose of the dma_mux is to provide fl exibility in the system?s use of the available dma channels. as such, configuration of the dma_mux is intended to be a static procedure done during execution of the system boot code. howe ver, if the procedure outlined in section 18.7.2, enabling and configuring sources, is followed, the configuration of the dma_mux may be changed during the normal operation of the system. functionally, the dma_mux channels may be divided into two classes: ? channels that implement the normal routing f unctionality plus peri odic triggering capability ? channels that implement only the normal routing functionality 18.6.1 dma channels with peri odic triggering capability besides the normal routing functionality, the first 4 channels of the dma_mux provide a special periodic triggering capability that can be used to provide an automatic mechanism to transmit bytes, frames or packets at fixed intervals without the need for pr ocessor intervention. the trigger is generated by the periodic interrupt timer (pit); as such, the configuration of the peri odic triggering interval is done via 26 flexpwm_1 comp_val 27 flexpwm_1 capt 28 always requestor - 29 always requestor - 30 always requestor - 31 always requestor - 32 always requestor - 33 always requestor - table 18-5. dma_mux trigger sources source module source signal dmachmux channel trigger # pit trigger channel 0 0 pit trigger channel 1 1 pit trigger channel 2 2 pit trigger channel 3 3 table 18-4. dma_mux source slot mapping (continued) dma_mux source slot # sour ce module source resource
edma channel mux (dma_mux) 18-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 configuration registers in the pit. please refer to the periodic inte rrupt timer block guide for more information on this topic. note because of the dynamic nature of the system (i.e. dma ch annel priorities, bus arbitration, interrupt service routin e lengths, etc.), the number of clock cycles between a trigger and the actual dma transf er cannot be guaranteed. figure 18-3. dma_mux triggered channels the dma channel triggering capability allows the syst em to ?schedule? regula r dma transfers, usually on the transmit side of certain periphe rals, without the intervention of th e processor. this trigger works by gating the request from the peripheral to the dma until a trigger event has been s een. this is illustrated in figure 18-4 . dma channel #0 tr i g g e r # 2 tr i g g e r # 1 source #1 source #2 source #3 always #1 dma channel #3 always #4 trigger #4 source #27
edma channel mux (dma_mux) freescale semiconductor 18-7 pxs20 microcontroller reference manual, rev. 1 figure 18-4. dma_mux channel triggering: normal operation once the dma request has been servic ed, the peripheral will negate its request, effectively resetting the gating mechanism until the periphe ral re-asserts its request and the next trigger event is seen. this means that if a trigger is seen, but the peripheral is not re questing a transfer, that tri gger will be ignored. this situation is illustrated in figure 18-5 . figure 18-5. dma_mux channel triggering: ignored trigger this triggering capability may be used with any periphe ral that supports dma transf ers, and is most useful for two types of situations: ? periodically polling external devices on a particular bus. as an exampl e, the transmit side of an spi is assigned to a dma channel with a trigger, as described above. once setup, the spi will request dma transfers (presumably from memory) as long as its transmit buffer is empty. by using a trigger on this channel, the spi transfer s can be automatically performed every 5 ? s (as an example). on the receive side of the spi, the spi and dma can be configured to transfer receive data into memory, effectively implementing a met hod to periodically read data from external devices and transfer the results into memory without processor intervention. ? using the gpio ports to drive or sample waveform s. by configuring the dma to transfer data to one or more gpio ports, it is possible to create complex waveforms using ta bular data stored in on-chip memory. conversely, using the dma to peri odically transfer data from one or more gpio ports, it is possible to sample co mplex waveforms and store the resu lts in tabular form in on-chip memory. a more detailed description of the capability of each trigger (i.e.-resolu tion, range of values, etc.) may be found in the periodic interrupt timer (pit) block guide. 18.6.2 dma channels with no triggering capability the other channels of the dma mux provide the normal routing functionali ty as described in section 18.1.3, modes of operation . periph request tr i g g e r dma request periph request tr i g g e r dma request
edma channel mux (dma_mux) 18-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 18.6.3 "always enabled" dma sources in addition to the peripherals that can be used as dma sources, there are 6 a dditional dma sources that are "always enabled". unlike the peri pheral dma sources, where the peripheral controls the flow of data during dma transfers, the "always enabled" sources pr ovide no such "throttling" of the data transfers. these sources are most useful in the following cases: ? doing dma transfers to/from gpio - moving data from/to one or more gpio pins, either un-throttled (i.e.-as fast as possible), or pe riodically (using the dma triggering capability). ? doing dma transfers from memory to memory - moving data from memory to memory, typically as fast as possible, sometimes with software activation. ? doing dma transfers from memory to the external bus (or vice-versa) - similar to memory to memory transfers, this is typi cally done as quickly as possible. ? any dma transfer that requires so ftware activation - any dma transf er that should be explicitly started by software. in cases where software s hould initiate the start of a dma transfer, a "always enabled" dma source can be used to provide maximum flexibility. when activating a dma channel via software, subsequent executions of the minor loop require a new "start" ev ent be sent. this can ei ther be a new software activation, or a transfer request from the dma_mux. the options for doing this are: ? transfer all data in a si ngle minor loop. by configuring the dma to transfer all of the data in a single minor loop (i.e.-major loop counter = 1), no re-activation of the channel is necessary. the disadvantage to this option is the reduced granularity in determining the load that the dma transfer will incur on the system. for th is option, the dma channel should be disabled in the dma_mux. ? use explicit software re-activati on. in this option, the dma is confi gured to transfer the data using both minor and major loops, but the processor is re quired to re-activate the channel (by writing to the dma registers) after every minor loop . for this option, the dma channel should be disabled in the dma_mux. ? use a "always enabled" dma source. in this opti on, the dma is configured to transfer the data using both minor and major loops, and the dma_mu x does the channel re-activation. for this option, the dma channel shoul d be enabled and pointing to an "a lways enabled" source. note that the re-activation of the channel can be continuous (dma triggeri ng is disabled) or can use the dma triggering capability. in this manner, it is possible to execute periodic transfers of packets of data from one source to another, without processor intervention. 18.7 initialization/application information 18.7.1 reset the reset state of each individual bit is show n within the register description section ( section 18.3.1, register descriptions ). in summary, after reset, all channels ar e disabled and must be explicitly enabled before use.
edma channel mux (dma_mux) freescale semiconductor 18-9 pxs20 microcontroller reference manual, rev. 1 18.7.2 enabling and configuring sources enabling a source with periodic triggering 1. determine with which dma channel the source will be associated. note th at only the first 4 dma channels have periodi c triggering capability. 2. clear the enbl and trig bits of the dma channel 3. ensure that the dma channel is properly conf igured in the dma. the dma channel may be enabled at this point 4. configure the corresponding timer 5. select the source to be routed to the dm a channel. write to the corresponding chconfig register, ensuring that the enbl and trig bits are set example 18-1. configure source #5 transmit for use with dma channel 2, with peri odic triggering capability 1. write 0x00 to chconfig2 (base address + 0x02) 2. configure channel 2 in the dm a, including enabling the channel 3. configure a timer for the desired trigger interval 4. write 0xc5 to chconfig2 (base address + 0x02) the following code example il lustrates steps #1 and #4 above: in file registers.h: #define dmamux_base_addr 0xfc084000/* example only ! */ /* following example assumes char is 8-bits */ volatile unsigned char *chconfig0 = (volatile unsigned char *) (dmamux_base_addr+0x0000); volatile unsigned char *chconfig1 = (volatile unsigned char *) (dmamux_base_addr+0x0001); volatile unsigned char *chconfig2 = (volatile unsigned char *) (dmamux_base_addr+0x0002); volatile unsigned char *chconfig3 = (volatile unsigned char *) (dmamux_base_addr+0x0003); volatile unsigned char *chconfig4 = (volatile unsigned char *) (dmamux_base_addr+0x0004); volatile unsigned char *chconfig5 = (volatile unsigned char *) (dmamux_base_addr+0x0005); volatile unsigned char *chconfig6 = (volatile unsigned char *) (dmamux_base_addr+0x0006); volatile unsigned char *chconfig7 = (volatile unsigned char *) (dmamux_base_addr+0x0007); volatile unsigned char *chconfig8 = (volatile unsigned char *) (dmamux_base_addr+0x0008); volatile unsigned char *chconfig9 = (volatile unsigned char *) (dmamux_base_addr+0x0009); volatile unsigned char *chconfig10= (volatile unsigned char *) (dmamux_base_addr+0x000a); volatile unsigned char *chconfig11= (volatile unsigned char *) (dmamux_base_addr+0x000b); volatile unsigned char *chconfig12= (volatile unsigned char *) (dmamux_base_addr+0x000c); volatile unsigned char *chconfig13= (volatile unsigned char *) (dmamux_base_addr+0x000d); volatile unsigned char *chconfig14= (volatile unsigned char *) (dmamux_base_addr+0x000e); volatile unsigned char *chconfig15= (volatile unsigned char *) (dmamux_base_addr+0x000f); in file main.c: #include "registers.h" : : *chconfig2 = 0x00; *chconfig2 = 0xc5; enabling a source without periodic triggering 1. determine with which dma channel the source will be associated. note th at only the first 4 dma channels have periodi c triggering capability.
edma channel mux (dma_mux) 18-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 2. clear the enbl and trig bits of the dma channel 3. ensure that the dma channel is properly conf igured in the dma. the dma channel may be enabled at this point 4. select the source to be routed to the dm a channel. write to the corresponding chconfig register, ensuring that the enbl is set and the trig bit is cleared example 18-2. configure source #5 transmit for use with dma channel 2, with no periodic triggering capability. 1. write 0x00 to chconfig2 (base address + 0x02) 2. configure channel 2 in the dm a, including enabling the channel 3. write 0x85 to chconfig2 (base address + 0x02) the following code example il lustrates steps #1 and #3 above: in file registers.h: #define dmamux_base_addr 0xfc084000/* example only ! */ /* following example assumes char is 8-bits */ volatile unsigned char *chconfig0 = (volatile unsigned char *) (dmamux_base_addr+0x0000); volatile unsigned char *chconfig1 = (volatile unsigned char *) (dmamux_base_addr+0x0001); volatile unsigned char *chconfig2 = (volatile unsigned char *) (dmamux_base_addr+0x0002); volatile unsigned char *chconfig3 = (volatile unsigned char *) (dmamux_base_addr+0x0003); volatile unsigned char *chconfig4 = (volatile unsigned char *) (dmamux_base_addr+0x0004); volatile unsigned char *chconfig5 = (volatile unsigned char *) (dmamux_base_addr+0x0005); volatile unsigned char *chconfig6 = (volatile unsigned char *) (dmamux_base_addr+0x0006); volatile unsigned char *chconfig7 = (volatile unsigned char *) (dmamux_base_addr+0x0007); volatile unsigned char *chconfig8 = (volatile unsigned char *) (dmamux_base_addr+0x0008); volatile unsigned char *chconfig9 = (volatile unsigned char *) (dmamux_base_addr+0x0009); volatile unsigned char *chconfig10= (volatile unsigned char *) (dmamux_base_addr+0x000a); volatile unsigned char *chconfig11= (volatile unsigned char *) (dmamux_base_addr+0x000b); volatile unsigned char *chconfig12= (volatile unsigned char *) (dmamux_base_addr+0x000c); volatile unsigned char *chconfig13= (volatile unsigned char *) (dmamux_base_addr+0x000d); volatile unsigned char *chconfig14= (volatile unsigned char *) (dmamux_base_addr+0x000e); volatile unsigned char *chconfig15= (volatile unsigned char *) (dmamux_base_addr+0x000f); in file main.c: #include "registers.h" : : *chconfig2 = 0x00; *chconfig2 = 0x85; disabling a source a particular dma source may be disabled by not writing the correspon ding source value into any of the chconfig registers. additionally, some module spec ific configuration may be necessary. please refer to the appropriate section for more details. switching the source of a dma channel 1. disable the dma channel in the dma and re-configure the channel for the new source 2. clear the enbl and trig bits of the dma channel
edma channel mux (dma_mux) freescale semiconductor 18-11 pxs20 microcontroller reference manual, rev. 1 3. select the source to be routed to the dm a channel. write to the corresponding chconfig register, ensuring that the enbl and trig bits are set example 18-3. switch dma channel 8 from source #5 transmit to source #7 transmit 1. in the dma configuration registers, disable dma channel 8 and re-con figure it to handle the transfers to peripheral slot 7. this example assu mes channel 8 doesn?t have triggering capability. 2. write 0x00 to chconfig8 (base address + 0x08) 3. write 0x87 to chconfig8 (base ad dress + 0x08). (in this example, setting the tr ig bit would have no effect, due to the assumption that ch annels 8 does not support the periodic triggering functionality). the following code example il lustrates steps #2 and #4 above: in file registers.h: #define dmamux_base_addr 0xfc084000/* example only ! */ /* following example assumes char is 8-bits */ volatile unsigned char *chconfig0 = (volatile unsigned char *) (dmamux_base_addr+0x0000); volatile unsigned char *chconfig1 = (volatile unsigned char *) (dmamux_base_addr+0x0001); volatile unsigned char *chconfig2 = (volatile unsigned char *) (dmamux_base_addr+0x0002); volatile unsigned char *chconfig3 = (volatile unsigned char *) (dmamux_base_addr+0x0003); volatile unsigned char *chconfig4 = (volatile unsigned char *) (dmamux_base_addr+0x0004); volatile unsigned char *chconfig5 = (volatile unsigned char *) (dmamux_base_addr+0x0005); volatile unsigned char *chconfig6 = (volatile unsigned char *) (dmamux_base_addr+0x0006); volatile unsigned char *chconfig7 = (volatile unsigned char *) (dmamux_base_addr+0x0007); volatile unsigned char *chconfig8 = (volatile unsigned char *) (dmamux_base_addr+0x0008); volatile unsigned char *chconfig9 = (volatile unsigned char *) (dmamux_base_addr+0x0009); volatile unsigned char *chconfig10= (volatile unsigned char *) (dmamux_base_addr+0x000a); volatile unsigned char *chconfig11= (volatile unsigned char *) (dmamux_base_addr+0x000b); volatile unsigned char *chconfig12= (volatile unsigned char *) (dmamux_base_addr+0x000c); volatile unsigned char *chconfig13= (volatile unsigned char *) (dmamux_base_addr+0x000d); volatile unsigned char *chconfig14= (volatile unsigned char *) (dmamux_base_addr+0x000e); volatile unsigned char *chconfig15= (volatile unsigned char *) (dmamux_base_addr+0x000f); in file main.c: #include "registers.h" : : *chconfig8 = 0x00; *chconfig8 = 0x87;
edma channel mux (dma_mux) 18-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1
enhanced direct memory access (edma) freescale semiconductor 19-1 pxs20 microcontroller reference manual, rev. 1 chapter 19 enhanced direct memory access (edma) 19.1 introduction the edma is a second-generation pl atform module capable of performi ng complex data transfers with minimal intervention from a host processor via 16 progr ammable channels. intended for use as part of the standard product platform (spp), the hardware microarchitecture include s a edma engine which performs source and destination addr ess calculations, and the actual da ta movement operations, along with a local memory containing the transfer control descriptors (tcd) for the channels. this sram-based implementation is used to mi nimize the overall module size. dma channel muxing is provided in chapter 18, edma channel mux (dma_mux) . figure 19-1 is a block diagram of the edma module. figure 19-1. edma block diagram j j+1 n-1 sram transfer control descriptor (tcd) edma engine addr_path data_path edma peripheral bus amba ahb ipd_req[n-1:0] dma_ipi_int[n-1:0] 0 c o n t r o l pmodel_charb addr wdata[31:0] rdata[31:0] hrdata[63:0] hwdata[63:0] haddr[31:0] bus 64 dma_ipd_done[n-1:0]
enhanced direct memory access (edma) 19-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 19.1.1 overview the edma is a highly-programmable data transfer engine, which has been optimized to minimize the required intervention from the host pro cessor. it is intended for use in a pplications where the data size to be transferred is st atically known, and is not defined within the data pack et itself. the edma hardware supports: ? 16-channel implementation ? connection to the amba-ahb cr ossbar switch (xbar) for bus mastering the data movement ? 64-bit amba-ahb datapath width ? connection to the slave bus for programming the module ? parameterized support for 32- and 64-bit amba-ahb datapath widths ? 32-byte transfer control descriptor per channel stored in local memory ? 32 bytes of data registers, used as te mporary storage to support burst transfers throughout this document, n is used to reference the channel numbe r. additionally, data sizes are defined as byte (8-bit), halfword (16-bit), word (32-bit) and doubleword (64-bit). 19.1.2 features the edma module supports the following features: ? all data movement via dual-address transfer s: read from source, write to destination ? programmable source, destinat ion addresses, transfer size, plus support for enhanced addressing modes ? transfer control descriptor organized to support two-deep, nested transfer operations ?an inner data transfer loop defined by a ?minor? byte transfer count ?an outer data transfer loop define d by a ?major? iteration count ? channel service request via one of three methods: ? explicit software initiation ? initiation via a channel-to-channel li nking mechanism for c ontinuous transfers ? independent channel linking at e nd of minor loop and/or major loop ? peripheral-paced hardware requests (one per channel) ? for all three methods, one service request per execution of the minor loop is required ? support for fixed-priority and round-robin channel arbitration ? channel completion reported vi a optional interrupt requests ? one interrupt per channel, optionally asse rted at completion of major iteration count ? error terminations are optionally enabled per ch annel, and logically summed together to form a small number of error interrupt outputs ? support for scatter/gath er edma processing ? support for complex data structures ? support to cancel transfers via software
enhanced direct memory access (edma) freescale semiconductor 19-3 pxs20 microcontroller reference manual, rev. 1 the basic operation of a channel is defined as: 1. the channel is initialized by software loading th e transfer control descriptor into the edma?s programming model, memory-mappe d through the ips space, and implemented as local memory. 2. the channel requests service; either explicitly by software, a peripheral re quest or a linkage from another channel. note the major loop executes one iteration per service request. 3. the contents of the transfer cont rol descriptor for the activated cha nnel is read from the local memory and loaded into the edma engine?s internal register file. 4. the edma engine executes the data transfer defined by the transfer c ontrol descriptor, reading from the source and writing to the destinat ion. the number of iterations in the minor loop is automatically calculated by the edma engi ne. the number of iterations within the minor loop is a function of the number of bytes to transfer (nbytes), the source size (ssize) and the destinati on size (dsize). the completion of the minor loop is equal to one iteration of the major loop. 5. at the conclusion of the minor loop?s execution, certa in fields of the transfer control descriptor are written back to the local tcd memory. the process (steps 2-5) is repeated until the outer major loop?s itera tion count is exhausted. at that time, additional processing steps are comple ted, e.g., the optional asse rtion of an interrupt request signaling the transfer?s completion, final adjustments to the source and destination addresses, etc. for more details, consult section 19.2.1, register descriptions, and section 19.3, functional description. 19.2 memory map/register definition the edma?s programming model is partitioned into tw o sections, both mapped into the slave bus space: the first region defines a number of registers providing control f unctions, while the second region corresponds to the local transfer control descriptor memory. reading an unimplemented register bit or memory location will return the value of zero. write the value of zero to unimplemented register bits. any access to a reserved memory location will result in a bus error. reserved memory locations are indicated in the memory map. many of the control registers have a bit width that matches the number of channels implemented in the module. the unused bits are not implemented: reads return zeroes, and writes are ignored. the edma does not include any logi c which provides access control. rather, this function is supported using the standard access control logic provided by the pbridge controller. table 19-1 is a 32-bit view of the edma?s memory map. table 19-1. edma 32-bit memory map address offset register 0x0000 edma control register (dmacr) 0x0004 edma error status (dmaes)
enhanced direct memory access (edma) 19-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 19.2.1 register descriptions 19.2.1.1 edma control register (dmacr) the 32-bit dmacr defines the basic ope rating configuratio n of the edma. the edma arbitrates channel servic e requests. this arbitration can be configured to use either a fixed-priority or a round-robin se lection. in fixed-priority arbitrat ion, the highest priority channel requesting service is selected to ex ecute. the priorities are a ssigned by the channel pr iority registers (see section 19.2.1.16, edma channel n pr iority (dchprin), n = 0?15 ). in round-robin ar bitration mode, the channel priorities are ignored a nd the channels are cycled through without regard to priority. minor loop offsets are address offset values added to the fina l source address (saddr) or destination address (daddr) upon minor loop completion. wh en minor loop offsets are enable d, the minor loop offset (mloff) is added to the final source address (saddr), or the final destination address (da ddr), or both prior to the addresses being written back into the tcd. if the ma jor loop is complete, the minor loop offset is ignored 0x0008 reserved 0x000c edma enable request low (dmaerql, channels 15?0) 0x0010 reserved 0x0014 edma enable error interrupt low (dmaeeil, channels 15?0) 0x0018 edma set enable request (dmaserq) edma clear enable request (dmacerq) edma set enable error interrupt (dmaseei) edma clear enable error interrupt (dmaceei) 0x001c edma clear interrupt request (dmacint) edma clear error (dmacerr) edma set start bit (dmassrt) edma clear done status bit (dmacdne) 0x0020 reserved 0x0024 edma interrupt request low (dmaintl, channels 15?0) 0x0028 reserved 0x002c edma error low (dmaerrl, channels 15?0) 0x0030 reserved 0x0034 edma hardware request status low (dmahrsl, channels 15?0) 0x0038?0x00fc reserved 0x0100 edma channel 0 priority (dchpri0) edma channel 1 priority (dchpri1) edma channel 2 priority (dchpri2) edma channel 3 priority (dchpri3) 0x0104 edma channel 4 priority (dchpri4) edma channel 5 priority (dchpri5) edma channel 6 priority (dchpri6) edma channel 7 priority (dchpri7) 0x0108 edma channel 8 priority (dchpri8) edma channel 9 priority (dchpri9) edma channel 10 priority (dchpri10) edma channel 11 priority (dchpri11) 0x010c edma channel 12 priority (dchpri12) edma channel 13 priority (dchpri13) edma channel 14 priority (dchpri14) edma channel 15 priority (dchpri15) 0x0110?0x0ffc reserved 0x1000-0x11fc tcd0?tcd15 0x1200-0x17fc reserved table 19-1. edma 32-bit memory map (continued) address offset register
enhanced direct memory access (edma) freescale semiconductor 19-5 pxs20 microcontroller reference manual, rev. 1 and the major loop address offsets (slast and dlast_sga) are used to compute the next saddr and daddr values. when minor loop mapping is enabled (dmacr[emlm] = 1), tcdn word2 is redefined. a portion of tcdn word2 is used to specify multiple fields: an sour ce enable bit (smloe) to sp ecify the minor loop offset should be applied to the source a ddress (saddr) upon minor loop comple tion, an destination enable bit (dmloe) to specify the minor loop offset should be applied to the destinatio n address (daddr) upon minor loop completion, and the sign extended mi nor loop offset value (mloff). the same offset value (mloff) is used for both source and des tination minor loop offsets. when either minor loop offset is enabled (smloe set or dmloe set), the nbytes field is redu ced to 10 bits. when both minor l oop offsets are disabled (smloe cleared and dmloe cleared), the nbytes field is a 30-bit vector. when minor loop mapping is disabled (dmacr[emlm] = 0), all 32 bits of tcdn word2 are assigned to the nbytes field. see section 19.2.1.17, transfer co ntrol descriptor (tcd), for more details. see figure 19-2 and table 19-2 for the dmacr definition. figure 19-2. edma control register (dmacr) register address: dma_offset + 0x0000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cx ecx w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 eml m clm halt hoe 0 erc a edb g ebw w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented table 19-2. edma control register (dmacr) field descriptions name description value cx cancel transfer 0 normal operation. 1 cancel the remaining data transfer. stop the executing channel and force the minor loop to be finished. the cancel takes effect after the last write of the current read/write sequence. the cxfr bit clears itself after the ca ncel has been honored. this cancel retires the channel normally as if the minor loop was completed.
enhanced direct memory access (edma) 19-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ecx error cancel transfer 0 normal operation. 1 cancel the remaining data transfer in the same fashion as the cx cancel transfer. stop the executing channel and force the minor loop to be finished. the cancel takes effect after the last write of the current read/write sequence. the ecx bit clears itself after the cancel cancel has been honored. in addition to cancelling the transfer, the ecx treats the cancel as an error condition; thus updating the dmaes regist er and generating an optional error interrupt (see section 19.2.1.2, edma error status (dmaes) ). emlm enable minor loop mapping 0 minor loop mapping disabled. tcdn.word2 is defined as a 32-bit nbytes field. 1 minor loop mapping enabled. when set, tcdn.word2 is redefined to include individual enable fields, an offset field and the nbytes field. the individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. the nbytes field is reduced when either offset is enabled. clm continuous link mode 0 a minor loop channel link made to itself will go through channel arbitration before being activated again. 1 a minor loop channel link made to itself will not go through channel arbitration before being activated again. upon minor loop completion the channel will active again if that channel has has a minor loop channel link enabled and the link channel is itself. this effectively applies the minor loop offsets and restarts the next minor loop. halt halt edma operations 0 normal operation. 1 stall the start of any new channels. executing channels are allowed to complete. channel execution will resume when the halt bit is cleared. hoe halt on error 0 normal operation. 1 any error will cause the halt bit to be set. subsequently, all service requests will be ignored until the halt bit is cleared. erca enable round robin channel arbitration 0 fixed priority arbitration is used for channel selection. 1 round robin arbitration is used for channel selection. edbg enable debug 0 the assertion of the ipg_debug input is ignored. 1 the assertion of the ipg_debug input causes the edma to stall the start of a new channel. executing channels are allowed to complete. channel execution will resume when either the ipg_debug input is negated or the edbg bit is cleared. table 19-2. edma control register (dmacr) field descriptions name description value
enhanced direct memory access (edma) freescale semiconductor 19-7 pxs20 microcontroller reference manual, rev. 1 19.2.1.2 edma error status (dmaes) the dmaes register provides informat ion concerning the last recorded ch annel error. channel errors can be caused by a configuration error (an illegal setting in the transfer contro l descriptor or an illegal priority register setting in fixed arbitration mode) or an error terminati on to a bus master re ad or write cycle. a configuration error is caused when the starting source or destinati on address, source or destination offsets, minor loop byte count and th e transfer size represent an incons istent state. the addresses and offsets must be aligned on 0-modulo-transfer_size boundaries, and the minor loop byte count must be a multiple of the source and destinat ion transfer sizes. all source read s and destination writes must be configured to the natural boundary of the programmed transfer size respect ively. in fixed arbitration mode, a configuration error is cau sed by any two channel priorities being e qual. all channel priority levels must be unique when fixed arbitration mode is enabled. if a scatter/gather opera tion is enabled upon channel completion, a configurat ion error is reported if the scatter/gather address (dlast_sga) is not aligned on a 32-byte boundary. if minor loop channe l linking is enabled upon channel completion, a configuration error is reported when the link is attempted if the tcd.ci ter.e_link bit does not equal the tcd.biter.e_link bit. all configuration error conditions except scatter/gather and minor l oop link error are reported as the channel is activated and assert an er ror interrupt request, if enabled. a sc atter/gather configuration error is reported when the scatter/gather operation begins at major loop co mpletion when properly enabled. a minor loop channel link configuration error is reported when the link ope ration is serviced at minor loop completion. if a system bus read or write is terminated with an error, the data transfer is stopped and the appropriate bus error flag set. in this case, the state of the channel?s transfer control descriptor is updated by the edma engine with the current source addr ess, destination address and current iteration count at the point of the fault. when a system bus error occurs, the channel is terminated after the read or write transaction which is already pipelined after errant access, has complete d. if a bus error occurs on the last read prior to beginning the write sequence, the write will execute using the data cap tured during the bus error. if a bus error occurs on the last write prior to switching to the next read sequenc e, the read seque nce will execute before the channel is terminated due to the destination bus error. a transfer may be cancelled by software via the dmacr[cx ] bit or hardware via the dma_cancel_xfer input signal. when a cancel transfer request is recognized, the edma e ngine stops processing the channel. the current read-write sequence is allowed to finish. if the cancel occurs on th e last read-write sequence of a major or minor loop, the ca ncel request is discarded and the channel retires normally. the error cancel transfer is the sa me as a cancel transfer except the dmaes register is updated with the cancelled channel number and error cancel bit is set. the tcd of a cancelled channel has the source address and destination address of the last transfer saved in the tcd. it is the responsibility of the user to initialize the tcd again should the channel need to be restarted because the aforementioned fields have ebw enable buffered writes 0 the buffer able write signal (hprot[2]) is not asserted during amba ahb writes. 1 the bufferable write signal (hprot[2]) is asserted on all amba ahb writes except for the last write sequence. table 19-2. edma control register (dmacr) field descriptions name description value
enhanced direct memory access (edma) 19-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 been modified by the edma engine and no longer represent the original parameters. when a transfer is cancelled via the error cancel tran sfer mechanism (setting the dmac r[ecx]), the channel number is loaded into the errchn field and the ecx and vld bits are set are set in the dmaes register. in addition, an error interrupt may be generated if enabled. see section 19.2.1.14, edma error low (dmaerrl) register, for error interrupt details. the occurrence of any type of error causes the ed ma engine to immediatel y stop, and the appropriate channel bit in the edma error regist er to be asserted. at the same time, the detail s of the error condition are loaded into the dmaes register. the major loop complete indicators, sett ing the transfer control descriptor done flag and the possible a ssertion of an interrupt request, are not affected when an error is detected. see figure 19-3 and table 19-3 for the dmaes definition. figure 19-3. edma error status (dmaes) register register address: dma_offset + 0x0004 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r vld 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ecx w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 cpe errchn[0:5] sae soe dae doe nce sge sbe dbe w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented table 19-3. edma error status (dmaes) field descriptions name description value vld logical or of all dmaerrh and dmaerrl status bits. 0 no dmaerr bits are set. 1 at least one dmaerr bit is set indicating a valid error exists that has not been cleared. ecx transfer cancelled 0 no cancelled transfers. 1 the last recorded entry was a cancelled transfer via the error cancel transfer input. cpe channel priority error 0 no channel priority error. 1 the last recorded error was a configuration error in the channel priorities. all channel priorities are not unique. errchn[0:5] error channel number or cancelled channel number the channel number of the last recorded error (excluding gpe and cpe errors) or last recorded transfer that was error cancelled. sae source address error 0 no source address c onfiguration error. 1 the last recorded error was a configuration error detected in the tcd.saddr field. tcd.saddr is inconsistent with tcd.ssize.
enhanced direct memory access (edma) freescale semiconductor 19-9 pxs20 microcontroller reference manual, rev. 1 19.2.1.3 edma enable request low (dmaerql) the dmaerql register provi des a bit map for the implemented channe ls to enable the request signal for each channel. the state of a ny given channel enable is directly affected by writes to this register; it is also affected by writes to the dmaserq and dmacer q registers. the edma{s,c}erq registers are provided so that the request enable for a single channel can easily be modified without the need to perform a read-modify-write sequence to the dmaerql register. both the edma request input signal and this enable request flag must be asse rted before a channel?s hardware service request is accepted. the state of the edma enable request flag does not affect a channel service request made explicitly through software or a linked channel request. see figure 19-4 and table 19-4 for the dmaerql definition. soe source offset error 0 no source offset configuration error. 1 the last recorded error was a configuration error detected in the tcd.soff field. tcd.soff is inconsistent with tcd.ssize. dae destination address error 0 no destination address configuration error. 1 the last recorded error was a configuration error detected in the tcd.daddr field. tcd.daddr is inconsistent with tcd.dsize. doe destination offset error 0 no destination offset configuration error. 1 the last recorded error was a configuration error detected in the tcd.doff field. tcd.doff is inconsistent with tcd.dsize. nce nbytes/citer configuration error 0 no nbytes/citer configuration error. 1 the last recorded error was a configuration error detected in the tcd.nbytes or tcd.citer fields. tcd.nbytes is not a multiple of tcd.ssize and tcd.dsize, or tcd.citer is equal to zero, or tcd.citer.e_link is not equal to tcd.biter.e_link. sge scatter/gather configuration error 0 no scatter/gather configuration error. 1 the last recorded error was a configuration error detected in the tcd.dlast_sga field. this field is checked at the beginning of a scatter/gather operation after major loop completion if tcd.e_sg is enabled. tcd.dlast_sga is not on a 32 byte boundary. sbe source bus error 0 no source bus error. 1 the last recorded error was a bus error on a source read. dbe destination bus error 0 no destination bus error. 1 the last recorded error was a bus error on a destination write. table 19-3. edma error status (dmaes) field descriptions (continued) name description value
enhanced direct memory access (edma) 19-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 register address: dma_offset + 0x000c as a given channel completes the processing of its majo r iteration count, there is a flag in the transfer control descriptor that may affect the ending state of the dm aerq bit for that channel. if the tcd.d_req bit is set, then the corresponding dmaerq bit is clear ed, disabling the edma request; else if the d_req bit is cleared, the state of the dmaerq bit is unaffected. 19.2.1.4 edma enable error interrupt low (dmaeeil) the dmaeeil register provides a bit map for the impl emented channels to enable the error interrupt signal for each channel. the state of any given channel?s error interrupt enable is directly affected by writes to this register; it is also affected by wr ites to the dmaseei and dmaceei registers. the edma{s,c}eei registers are provided so that the error interrupt enable for a single channel can easily be modified without the need to perform a read-modify-write seque nce to the dmaeeil register. both the edma error indicator and this error interrupt enable flag must be asserted before an error interrupt request for a gi ven channel is asserted. see figure 19-5 and table 19-5 for the dmaeeil definition. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r erq 15 erq 14 erq 13 erq 12 erq 11 erq 10 erq 9 erq 8 erq 7 erq 6 erq 5 erq 4 erq 3 erq 2 erq 1 erq 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented figure 19-4. edma enable request low (dmaerql) register table 19-4. dmaerql field descriptions name description value erqn, n = 0,... 15 enable edma request n 0 the edma request signal for channel n is disabled. 1 the edma request signal for channel n is enabled.
enhanced direct memory access (edma) freescale semiconductor 19-11 pxs20 microcontroller reference manual, rev. 1 register address: dma_offset + 0x0014 19.2.1.5 edma set enable request (dmaserq) the dmaserq register provides a simple memory -mapped mechanism to set a given bit in the dmaerql register to enable the edma request for a given channel. the data value on a register write causes the corresponding bit in the dmaerql register to be set. a data value of 64 to 127 (regardless of the number of implemented channels ) provides a global se t function, forcing the entire contents of dmaerql to be asserted. if the nop bit is set, the command is ignored. this allows multiple byte registers to be written as a 32-bit word. reads of this regist er return all zeroes. see figure 19-6 and table 19-6 for the dmaserq definition. register address: dma_offset + 0x0018 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eei1 5 eei1 4 eei1 3 eei1 2 eei1 1 eei1 0 eei0 9 eei0 8 eei0 7 eei0 6 eei0 5 eei0 4 eei0 3 eei0 2 eei0 1 eei0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented figure 19-5. edma enable error interrupt low (dmaeeil) register table 19-5. dmaeeil field descriptions name description value eein, n = 0,... 15 enable error interrupt n 0 the error signal for channel n does not generate an error interrupt. 1 the assertion of the error signal for channel n generate an error interrupt request. 0 1 2 3 4 5 6 7 r 0 0 0 0 0 0 0 0 w nop serq reset: 0 0 0 0 0 0 0 0 = unimplemented figure 19-6. edma set enable request (dmaserq) register table 19-6. dmaserq field descriptions name description value nop no operation 0 normal operation 1 no operation, ignore the other bits in the register serq set enable request see the field structure in ta b l e 1 9 - 7
enhanced direct memory access (edma) 19-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 19.2.1.6 edma clear enab le request (dmacerq) the dmacerq register provides a simple memory-m apped mechanism to clea r a given bit in the dmaerql register to disable the ed ma request for a given channel. th e data value on a register write causes the corresponding bit in the dmaerql register to be cleared. a data va lue of 64 to 127 (regardless of the number of implemented channe ls) provides a global clear function, fo rcing the entire contents of the dmaerql to be zeroed, disabling al l edma request inputs. if the no p bit is set, the command is ignored. this allows multiple byte regist ers to be written as a 32-bit word. reads of this register return all zeroes. see figure 19-7 and table 19-8 for the dmac erq definition. register address: dma_offset + 0x0019 table 19-7. dmaserq[serq] field structure bit number description 0 ?set all? bit: 0 affects only the channel specified in bit numbers 4?7 1 affects all channels (bit numbers 4?7 are ignored) 1?2 reserved 3?6 set the corresponding bit in dmaerql 0 1 2 3 4 5 6 7 r 0 0 0 0 0 0 0 0 w nop cerq reset: 0 0 0 0 0 0 0 0 = unimplemented figure 19-7. edma clear enable request (dmacerq) register table 19-8. dmacerq field descriptions name description value nop no operation 0 normal operation 1 no operation, ignore the other bits in the register cerq clear enable request see the field structure in ta b l e 1 9 - 9 table 19-9. dmacerq[cerq] field structure bit number description 0 ?clear all? bit: 0 affects only the channel specified in bit numbers 4?7 1 affects all channels (bit numbers 4?7 are ignored) 1?2 reserved 3?6 clear the corresponding bit in dmaerql
enhanced direct memory access (edma) freescale semiconductor 19-13 pxs20 microcontroller reference manual, rev. 1 19.2.1.7 edma set enable error interrupt (dmaseei) the dmaseei register provides a si mple memory-mapped mechanism to set a given bit in the dmaeeil register to enable the error interrupt for a given ch annel. the data value on a register write causes the corresponding bit in the dmaeeil regist er to be set. a data value of 64 to 127 (regardles s of the number of implemented channels) provides a global set function, forcing the en tire contents of dmaeeil to be asserted. if the nop bit is set, the command is ignored. this allows multiple byte registers to be written as a 32-bit word. reads of this register return all zeroes. see figure 19-8 and table 19-10 for the dmaseei definition. register address: dma_offset + 0x001a 19.2.1.8 edma clear enable error interrupt (dmaceei) the dmaceei register provides a simple memory-m apped mechanism to clear a given bit in the dmaeeil register to disable the er ror interrupt for a given channel. the data value on a register write causes the corresponding bit in the dm aeeil register to be cleared. a da ta value of 64 to 127 (regardless of the number of implemented channe ls) provides a global clear function, fo rcing the entire contents of the dmaeeil to be zeroed, disabling all edma request inputs. if the nop is set, the command is ignored. this allows multiple byte registers to be written as a 32-bit word. reads of this register return all zeroes. see figure 19-9 and table 19-12 for the dmaceei definition. 0 1 2 3 4 5 6 7 r 0 0 0 0 0 0 0 0 w nop seei reset: 0 0 0 0 0 0 0 0 = unimplemented figure 19-8. edma set enable er ror interrupt (dmaseei) register table 19-10. dmaseei field descriptions name description value nop no operation 0 normal operation 1 no operation, ignore the other bits in the register seei set enable error interrupt see the field structure in table 19-11 table 19-11. dmaseei[ seei] field structure bit number description 0 ?set all? bit: 0 affects only the channel specified in bit numbers 4?7 1 affects all channels (bit numbers 4?7 are ignored) 1?2 reserved 3?6 set the correspon ding bit in dmaeeil
enhanced direct memory access (edma) 19-14 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 register address: dma_offset + 0x001b 19.2.1.9 edma clear interrupt request (dmacint) register the dmacint register provides a simple memory-mapped mechanism to clear a given bit in the dmaintl register to disable the interrupt request for a given channel. the given value on a register write causes the corresponding bit in the dm aintl register to be cleared. a da ta value of 64 to 127 (regardless of the number of implemented channe ls) provides a global clear function, fo rcing the entire contents of the dmaintl to be zeroed, disabling all edma interrupt requests. if the nop bit is set, the command is ignored. this allows multiple byte regist ers to be written as a 32-bit word. reads of this register return all zeroes. see figure 19-10 and table 19-14 for the dmacint definition. register address: dma_offset + 0x001c 0 1 2 3 4 5 6 7 r 0 0 0 0 0 0 0 0 w nop ceei reset: 0 0 0 0 0 0 0 0 = unimplemented figure 19-9. edma clear enable error interrupt (dmaceei) register table 19-12. dmaceei field descriptions name description value nop no operation 0 normal operation. 1 no operation, ignore the other bits in the register ceei clear enable error interrupt see the field structure in table 19-13 table 19-13. dmaceei[ceei] field structure bit number description 0 ?clear all? bit: 0 affects only the channel specified in bit numbers 4?7 1 affects all channels (bit numbers 4?7 are ignored) 1?2 reserved 3?6 clear the correspon ding bit in dmaeeil 0 1 2 3 4 5 6 7 r 00000000 w nop cint reset: 0 0 0 0 0 0 0 0 = unimplemented figure 19-10. edma clear interrupt request (dmacint) register
enhanced direct memory access (edma) freescale semiconductor 19-15 pxs20 microcontroller reference manual, rev. 1 19.2.1.10 edma clear error (dmacerr) register the dmaceer register provides a simple memory-mapped mechanism to clear a given bit in the dmaerrl register to disable the e rror condition flag for a given channe l. the given value on a register write causes the corresponding bit in the dmaerrl re gister to be cleared. a data value of 64 to 127 (regardless of the number of impl emented channels) provides a global clear function, forcing the entire contents of the dmaerrl to be zeroed, clearing all ch annel error indicators. if the nop bit is set, the command is ignored. this allo ws multiple byte register s to be written as a 32- bit word. reads of this register return all zeroes. see figure 19-11 and table 19-16 for the dmacerr definition. register address: dma_offset + 0x001d table 19-14. dmacint field descriptions name description value nop no operation 0 normal operation 1 no operation, ignore the other bits in the register cint clear interrupt request see the field structure in table 19-15 table 19-15. dmacint[cint] field structure bit number description 0 ?clear all? bit: 0 affects only the channel specified in bit numbers 4?7 1 affects all channels (bit numbers 4?7 are ignored) 1?2 reserved 3?6 clear the corresponding bit in dmaintl 0 1 2 3 4 5 6 7 r 0 0 0 0 0 0 0 0 w nop cerr reset: 0 0 0 0 0 0 0 0 = unimplemented figure 19-11. edma clear error (dmacerr) register table 19-16. dmacerr field descriptions name description value nop no operation 0 normal operation 1 no operation, ignore the other bits in the register cerr clear error indicator see the field structure in table 19-17
enhanced direct memory access (edma) 19-16 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 19.2.1.11 edma set start bit (dmassrt) register the dmassrt register provides a simple memory-mapped mechanism to set the start bit in the tcd of the given channel. the data valu e on a register write causes the st art bit in the corresponding transfer control descriptor to be set. a data value of 64 to 127 (regardless of the numbe r of implemented channels) provides a global set function, forcing all start bits to be set. if the nop bit is set, the command is ignored. this allows multiple byte regist ers to be written as a 32-bit word. reads of this register return all zeroes. see table 19-35 for the tcd start bit definition. register address: dma_offset + 0x001e table 19-17. dmacerr[cerr] field structure bit number description 0 ?clear all? bit: 0 affects only the channel specified in bit numbers 4?7 1 affects all channels (bit numbers 4?7 are ignored) 1?2 reserved 3?6 clear the corresponding bit in dmaerrl 0 1 2 3 4 5 6 7 r 0 0 0 0 0 0 0 0 w nop ssrt reset: 0 0 0 0 0 0 0 0 = unimplemented figure 19-12. edma set start bit (dmassrt) register table 19-18. dmassrt field descriptions name description value nop no operation 0 normal operation 1 no operation, ignore the other bits in the register ssrt set start bit (channel service request) see the field structure in table 19-19 table 19-19. dmassrt[ssrt] field structure bit number description 0 ?set all? bit: 0 affects only the channel specified in bit numbers 4?7 1 affects all channels (bit numbers 4?7 are ignored) 1?2 reserved 3?6 set the corresponding channel?s tcd.start
enhanced direct memory access (edma) freescale semiconductor 19-17 pxs20 microcontroller reference manual, rev. 1 19.2.1.12 edma clear done status (dmacdne) register the dmacdne register provides a s imple memory-mapped mechanism to clear the done bit in the tcd of the given channel. the data value on a regi ster write causes the done bit in the corresponding transfer control descriptor to be cleared. a data value of 64 to 127 (regardless of the number of implemented channels) provides a globa l clear function, forcing all done bi ts to be cleared. if the nop bit is set, the command is ignored. this allows multipl e byte registers to be wri tten as a 32-bit word. reads of this register return all zeroes. see table 19-35 for the tcd done bit definition. register address: dma_offset + 0x001f 19.2.1.13 edma interrupt request low (dmaintl) register the dmaintl register provides a bit map for the im plemented channels signaling the presence of an interrupt request for each channel. the edma engine signals the occurrence of a programmed interrupt upon the completion of a data transfer as defined in the transfer control descriptor by setting the appropriate bit in this register. the outputs of this register are directly routed to the platform?s interrupt controller. during the execution of the interrupt service routine associated with any given channel, it is software?s responsibility to clear th e appropriate bit, negating the inte rrupt request. typi cally, a write to the dmacint register in the interrupt se rvice routine is used for this purpose. the state of any given channel?s interr upt request is directly affected by wr ites to this register; it is also affected by writes to the dmacint register. on writ es to the dmaintl, a one in any bit position clears 0 1 2 3 4 5 6 7 r 0 0 0 0 0 0 0 0 w nop cdne reset: 0 0 0 0 0 0 0 0 = unimplemented figure 19-13. edma clear done status (dmacdne) register table 19-20. dmacdne field descriptions name description value nop no operation 0 normal operation 1 no operation, ignore the other bits in the register cdne clear done status bit see the field structure in table 19-21 table 19-21. dmacdne[cdne] field structure bit number description 0 ?clear all? bit: 0 affects only the channel specified in bit numbers 4?7 1 affects all channels (bit numbers 4?7 are ignored) 1?2 reserved 3?6 clear the corresponding channel?s done bit
enhanced direct memory access (edma) 19-18 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 the corresponding channel?s interrupt request. a zero in any bit position has no affect on the corresponding channel?s current interrupt status . the dmacint register is provided so the in terrupt request for a single channel can easily be clea red without the need to perform a read -modify-write sequen ce to the dmaintl register. see figure 19-14 and table 19-22 for the dmaintl definition. register address: dma_offset + 0x0024 19.2.1.14 edma error low (dmaerrl) register the dmaerrl register provides a bit map for the im plemented channels signaling the presence of an error for each channel. the edma engine signals the occurrence of a error condition by setting the appropriate bit in this register. th e outputs of this register are enab led by the contents of the dmaeeil register, then logically summed to fo rm an error interrupt request which is then routed to the platform?s interrupt controller. during the execution of the interr upt service routine associated with any edma errors, it is software?s responsibility to clear the appropriate bit, negating the error interrupt request. typically, a write to the dmacerr register in the interrupt servic e routine is used for this purpose. recall the normal edma channel completion indicators, setting the tran sfer control descriptor done flag and the possible assertion of an in terrupt request, are not affected when an error is detected. the contents of this register can also be polled a nd a non-zero value indicates th e presence of a channel error, regardless of the state of the dmaeeil register. the state of any given cha nnel?s error indicators is affected by writes to this register; it is also affected by writes to the dmacerr register. on writes to the dmaerrl, a one in any bit positi on clears the corresponding channel?s error status. a zero in any bit position has no affect on the corresponding channel?s current error status. the dmacerr register is provided so the error indicator for a single channel can easily be cleared. see figure 19-15 and table 19-23 for the dmaerrl definition. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r int1 5 int1 4 int1 3 int1 2 int1 1 int1 0 int9 int8 int7 int6 int5 int4 int3 int2 int1 int0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented figure 19-14. edma interrupt request low (dmaintl) register table 19-22. dmaintl field descriptions name description value intn, n = 0,... 15 dma interrupt request n 0 the interrupt request for channel n is cleared. 1 the interrupt request for channel n is active.
enhanced direct memory access (edma) freescale semiconductor 19-19 pxs20 microcontroller reference manual, rev. 1 register address: dma_offset + 0x002c 19.2.1.15 edma hardware request status low (dmahrsl) register the dmahrsl register provides a bit map for the impl emented channels to show the current hardware request status for each channel. hardware request stat us reflects the current stat e of the registered and qualified (via the dmaerq field) ipd_req lines as seen by the edma?s arbitration logic. this view into the hardware request signals may be used for debug purposes. see figure 19-16 and figure 19-24 for the dmahrsl definition. register address: dma_offset + 0x0034 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r err 15 err 14 err 13 err 12 err 11 err 10 err 9 err 8 err 7 err 6 err 5 err 4 err 3 err 2 err 1 err 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented figure 19-15. edma error low (dmaerrl) register table 19-23. dmaerrl field descriptions name description value errn, n = 0,... 15 dma error n 0 an error in channel n has not occurred. 1 an error in channel n has occurred. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r hrs 15 hrs 14 hrs 13 hrs 12 hrs 11 hrs 10 hrs 9 hrs 8 hrs 7 hrs 6 hrs 5 hrs 4 hrs 3 hrs 2 hrs 1 hrs 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented figure 19-16. edma hardware request status low (dmahrsl) register
enhanced direct memory access (edma) 19-20 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 19.2.1.16 edma channel n pr iority (dchprin), n = 0?15 when the fixed-priority channel ar bitration mode is enab led (dmacr[erca] = 0), th e contents of these registers define the unique priorities associated with each channel. th e channel priorities are evaluated by numeric value, i.e., 0 is the lowest priority, 1 is th e next higher priority, then 2, 3, etc. software must program the channel priorities with unique values, otherwise a configur ation error will be reported. the range of the priority value is limited to the values of 0?15. channel preemption is enabled on a per channel basi s by setting the ecp bit in the dchprin register. channel preemption allows the executin g channel?s data transfers to be temporarily suspended in favor of starting a higher priority channel. after the preempting channel has comp leted all of its minor loop data transfers, the preempted channel is restored and resumes execution. af ter the restored channel completes one read/write sequence, it is agai n eligible for preemption. if any hi gher priority channel is requesting service, the restored channel will be suspended and the higher priority channel will be serviced. nested preemption (attempting to preempt a preempting channel) is not su pported. after a preempting channel begins execution, it cannot be preempt ed. preemption is only available wh en fixed arbitration is selected for channel arbitration mode. a channel?s ability to preempt a nother channel can be disabled by setting the dpa bit in the dchprin register. when a channel?s preempt ability is disa bled, that channel cannot suspend a lower priority channel?s data transfer; regardless of the lower priority channel?s ecp setting. this allo ws for a pool of low priority, large data moving channels to be define d. these low priority channe ls can be configured to not preempt each other, thus preven ting a low priority channel from c onsuming the preempt slot normally available a true, high priority channel. see figure 19-17 and table 19-25 for the dchprin definition. figure 19-17. edma channel n priority (dchprin) register table 19-24. dmahrsl field descriptions name description value hrsn, n = 0,... 15 dma hardware request status n 0 a hardware service request for channel n is not present. 1 a hardware service request for channel n is present. note: the hardware request status reflects the state of the request as seen by the arbitration logic. therefore, this status is affected by the dmaerqn bit. register address: dma_offset + 0x100 + n 0 1 2 3 4 5 6 7 r ecp dpa * chpri[0:3] w reset: 0 0 * * * * * * = unimplemented, * = defaults to channel number (n) after reset
enhanced direct memory access (edma) freescale semiconductor 19-21 pxs20 microcontroller reference manual, rev. 1 table 19-25. edma channel n prio rity (dchprin) field descriptions 19.2.1.17 transfer control descriptor (tcd) each channel requires a 32-byte tr ansfer control descriptor for de fining the desired data movement operation. the tcd structure was prev iously discussed in detail in section 19.1.2, features. the channel descriptors are stored in the local memory in sequential order: ch annel 0, channel 1, ... channel [n-1]. the definitions of the tcd are pres ented as eight 32-bit values. table 19-26 is a 32-bit view of the basic tcd structure. figure 19-18 and table 19-27 define word 0 of the tcdn structure, the saddr field. name description value ecp enable channel preemption 0 channel n cannot be suspended by a higher priority channel?s service request. 1 channel n can be temporarily suspended by the service request of a higher priority channel. dpa disable preempt ability 0 channel n can suspend a lower priority channel. 1 channel n cannot suspend any channel, regardless of channel priority. chpri[0:3] channel n arbitration priority channel priority when fixed-priority arbitration is enabled. table 19-26. tcdn 32-bit memory structure edma offset tcdn field 0x1000 + (32 x n) + 0x00 source address (saddr) 0x1000 + (32 x n) + 0x04 transfer attributes (smod, ssize, dmod, dsize) signed source address offset (soff) 0x1000 + (32 x n) + 0x08 signed minor loop offset (smloe, dmloe, mloff) inner ?minor? byte count (nbytes) 0x1000 + (32 x n) + 0x0c last source address adjustment (slast) 0x1000 + (32 x n) + 0x10 destination address (daddr) 0x1000 + (32 x n) + 0x14 current ?major? iteration co unt (citer) signed destinat ion address offset (doff) 0x1000 + (32 x n) + 0x18 last destination addre ss adjustment/scatter gath er address (dlast_sga) 0x1000 + (32 x n) + 0x1c beginning ?major? iteration count (biter) channel control/status (bwc, major.linkch, done, active, major.e_link, e_sg, d_req, int_half, int_maj, start)
enhanced direct memory access (edma) 19-22 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 19-18. tcdn word 0 (tcdn.saddr) field table 19-27. tcdn word 0 (tcdn.saddr) field description figure 19-19 and table 19-28 define word 1 of the tcdn structure, the soff and transfer attribute fields. figure 19-19. tcdn word 1 (tcdn.{soff,smod,ssize,dmod,dsize}) fields register address: dma_offset + 0x1000 + (32 x n) + 0x00 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r saddr[0:15] w reset: - - - - - - - - - - - - - - - - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r saddr[16:31] w reset: - - - - - - - - - - - - - - - - = unimplemented name description value saddr[0:31] source address memory address pointing to the source data. register address: dma_offset + 0x1000 + (32 x n) + 0x04 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r smod[0:4] ssize[0:2] dmod[0:4] dsize[0:2] w reset: - - - - - - - - - - - - - - - - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r soff[16:31] w reset: - - - - - - - - - - - - - - - - = unimplemented
enhanced direct memory access (edma) freescale semiconductor 19-23 pxs20 microcontroller reference manual, rev. 1 figure 19-20 and table 19-29 define word 2 of the tcdn structure, the nbytes field. figure 19-20. tcdn word 2 (tcdn.nbytes) field (dmacr[emlm] = 0) table 19-28. tcdn word 1 (tcdn.{smod,ssize,dmod,dsize,soff}) field descriptions name description value smod[0:4] source address modulo 0 sourc e address modulo feature is disabled. non-0 the value defines a specific address bit which is selected to be either the value after saddr + soff calculation is performed or the original register value. this feature provides the ability to easily implement a circular data queue. for data queues requiring power-of-2 ?size? bytes, the queue should be based at a 0-modulo-size address and the smod field set to the appropriate value to freeze the upper address bits. the bit select is defined as ((1 << smod[4:0]) - 1) where a resulting 1 in a bit location selects the next state address for the corresponding address bit location and a 0 selects the original register value for the corresponding address bit location. for this application, the soff is typically set to the transfer size to implement post-increment addressing with the smod function constraining the addresses to a 0-modulo-size range. ssize[0:2] source data transfer size 000 8-bit 001 16-bit 010 32-bit 011 64-bit 100 reserved 101 32-byte burst (64-bit 4) 110 reserved 111 reserved dmod[0:4] destination address modul o see the smod[5:0] definition. dsize[0:2] destination data transfer size see the ssize[2:0] definition. soff[16:31] source address signed offset sign-extended offset applied to the current source address to form the next-state value as each source read is completed. register address: dma_offset + 0x1000 + (32 x n) + 0x08 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r nbytes[0:15] w reset: - - - - - - - - - - - - - - - - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r nbytes[16:31] w reset: - - - - - - - - - - - - - - - - = unimplemented
enhanced direct memory access (edma) 19-24 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 table 19-29. tcdn word 2 (tcdn.nbytes) field description when minor loop mapping (dmacr[emlm] = 1) is enab led, tcd word2 is redefi ned as four fields: a source minor loop offset enable, a destination minor loop offset enable, a minor loop offset field and a nbytes field. figure 19-21. tcdn word 2 (tcdn.nbytes) field (dmacr[emlm] = 1) name description value nbytes[0:31] inner ?minor? byte transfer count nu mber of bytes to be transferred in each service request of the channel. as a channel is activat ed, the contents of the appropriate tcd is loaded into the edma engine, and the appropriate reads and wr ites performed until the complete byte transfer count has been transferred. this is an indivisible operation and cannot be stalled or halted. after the minor count is exhausted, the current values of the saddr and daddr are written back into the local memory, the major iteration count is decremented and restored to the local memory. if the major iteration count is completed, additional processing is performed. the nbytes value 0x0000_0000 is interpreted as 0x1_0000_0000, thus specifying a 4 gb transfer. register address: dma_offset + 0x1000 + (32 x n) + 0x08 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r smlo e dmlo e mloff[0:13] or nbytes[0:13] w reset: - - - - - - - - - - - - - - - - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r mloff[14:19] or nbytes[14:19] nbytes[20:29] w reset: - - - - - - - - - - - - - - - - = unimplemented table 19-30. tcdn word 2 (tcdn.nbytes) field descriptions name description value smloe source minor loop offset enable this flag selects whether the minor loop offset is applied to the source address upon minor loop completion. 0 the minor loop offset is not applied to the saddr. 1 the minor loop offset is applied to the saddr.
enhanced direct memory access (edma) freescale semiconductor 19-25 pxs20 microcontroller reference manual, rev. 1 figure 19-22 and table 19-31 define word 3 of the tcdn structure, the slast field. figure 19-22. tcdn word 3 (tcdn.slast) field dmloe destination minor loop offset enable this flag selects whether the minor loop offset is applied to the destination address upon minor loop completion. 0 the minor loop offset is not applied to the daddr. 1 the minor loop offset is applied to the daddr. nbytes[0:19] or mloff[0:19] inner ?minor? byte transfer count or minor loop offset if both smloe and dmloe are cleared, this field is part of the byte transfer count. if either smloe or dmloe are set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop is completed. nbytes[0:9] inner ?minor? byte transfer count numb er of bytes to be transferred in each service request of the channel. as a channel is activat ed, the contents of the appropriate tcd is loaded into the edma engine, and the appropriate reads and wr ites performed until the complete byte transfer count has been transferred. this is an indivisible operation and cannot be stalled or halted. once the minor count is exhausted, the current values of the saddr and daddr are written back into the local memory, the major iteration count is decremented and restored to the local memory. if the major iteration count is completed, additional processing is performed. this field is extended to 30 bits when both smloe and dmloe are cleared (disabled). register address: dma_offset + 0x1000 + (32 x n) + 0x0c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r slast[0:15] w reset: - - - - - - - - - - - - - - - - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r slast[16:31] w reset: - - - - - - - - - - - - - - - - = unimplemented table 19-30. tcdn word 2 (tcdn.nbytes) field descriptions (continued) name description value
enhanced direct memory access (edma) 19-26 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 table 19-31. tcdn word 3 (tcdn.slast) field descriptions figure 19-23 and table 19-32 define word 4 of the tcdn structure, the daddr field. figure 19-23. tcdn word 4 (tcdn.daddr) field table 19-32. tcdn word 4 (tcdn.daddr) field description figure 19-24 and table 19-33 define word 5 of the tcdn stru cture, the citer and doff fields. figure 19-24. tcdn word 5 (tcdn.{citer,doff}) fields name description value slast[0:31] last source address adjustment adjust ment value added to the source address at the completion of the outer major iteration count. this value can be applied to ?restore? the source address to the initial value, or adjust the address to reference the next data structure. register address: dma_offset + 0x1000 + (32 x n) + 0x10 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r daddr[0:15] w reset: - - - - - - - - - - - - - - - - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r daddr[16:31] w reset: - - - - - - - - - - - - - - - - = unimplemented name description value daddr[0:31] destination address memory addr ess pointing to the destination data. register address: dma_offset + 0x1000 + (32 x n) + 0x14 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r citer. e_link citer[0:5] or citer.linkch[0:5] citer[6:14] w reset: - - - - - - - - - - - - - - - - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r doff[16:31] w reset: - - - - - - - - - - - - - - - - = unimplemented
enhanced direct memory access (edma) freescale semiconductor 19-27 pxs20 microcontroller reference manual, rev. 1 figure 19-25 and table 19-34 define word 6 of the tcdn structure, the dlast_sga field. table 19-33. tcdn word 5 (tcdn.{doff,citer}) field descriptions name description value citer.e_link enable channel-to-channel linking on minor loop complete as the channel completes the inner minor loop, this flag enables the linking to another channel, defined by citer.linkch[5:0]. the link target channel initiates a channel service request via an internal mechanism that sets the tcd.start bit of the specified channel. if channel linking is disabled, the citer value is extended to 15 bits in place of a link channel number. if the "major" loop is exhausted, this link mechanism is suppressed in favor of the major.e_link channel linking. this bit must be equal to the biter.e_link bit otherwise a configuration error will be reported. 0 the channel-to-channel linking is disabled. 1 the channel-to-channel linking is enabled. citer[0:5] or citer.linkch[0:5] current ?major? iteration count or link channel number if (tcd.citer.e_link = 0) then no channel-to-channel linking (or chaining) is performed after the inner "minor" loop is exhausted. tcd word 5, bits [30:25] are used to form a 15 bit citer field. else after the "minor" loop is exhausted, the edma engine initiates a channel service request at the channel defined by citer.linkch[5:0] by setting that channel?s tcd.start bit. the value contained in citer.linkch[5:0] must not exceed the number of implemented channels. for this device, bits 0:1 of this field are reserved. citer[6:14] current ?major? iterat ion count this 9 or 15-bit count represents the current major loop count for the channel. it is decremented each time the minor loop is completed and updated in the transfer control descriptor memory. once the major iteration count is exhausted, the channel performs a number of operations (e.g., final source and destination address calculations), optionally generating an interrupt to signal channel completion before reloading the citer field from the beginning iteration count (biter) field. when the citer field is initially loaded by software, it must be set to the same value as that contained in the biter field. if the channel is configured to execute a single service request, the initial values of biter and citer should be 0x0001. doff[16:31] destination address signed offset sign-extended offset applied to the current destination address to form the next-state value as each destination write is completed.
enhanced direct memory access (edma) 19-28 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 19-25. tcdn word 6 (tcdn.dlast_sga) field table 19-34. tcdn word 6 (tcdn.dlast_sga) field description figure 19-26 and table 19-35 define word 7 of the tcdn structure, the biter and control/status fields. figure 19-26. tcdn word 7 (tcdn.{biter,control/status}) fields register address: dma_offset + 0x1000 + (32 x n) + 0x18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r dlast_sga[0:15] w reset: - - - - - - - - - - - - - - - - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dlast_sga[16:31] w reset: - - - - - - - - - - - - - - - - = unimplemented name description value dlast_sga[31:0 0:31] last destination address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) if (tcd.e_sg = 0) then adjustment value added to the destination address at the completion of the outer major iteration count. this value can be applied to ?restore? the destination address to the initial value, or adjust the address to reference the next data structure. else this address points to the beginning of a 0-modulo-32 region containing the next transfer control descriptor to be loaded into this channel. this channel reload is performed as the major iteration count completes. the scatter/gather address must be 0-modulo-32, else a configuration error is reported. register address: dma_offset + 0x1000 + (32 x n) + 0x1c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r biter. e_lin k biter[0:5] or biter.linkch[0:5] biter[6:14] w reset: - - - - - - - - - - - - - - - - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r bwc major.linkch[0:5] done active major. e_link e_sg d_req int_ha lf int_m aj start w reset: - - - - - - - - 0 0 - - - - - 0 = unimplemented
enhanced direct memory access (edma) freescale semiconductor 19-29 pxs20 microcontroller reference manual, rev. 1 table 19-35. tcdn word 7 (tcdn.{biter, control/status}) field descriptions name description value biter.e_link enable channel-to-channel linking on minor loop complete this is the initial value copied into the citer.e_link field when the major loop is completed. the citer.e_link field controls channel linking during channel execution. this bit must be equal to the citer.e_link bit otherwise a configuration error will be reported. 0 the channel-to-channel linking is disabled. 1 the channel-to-channel linking is enabled. biter[0:5] or biter.linkch[0:5] beginning ?major? iteration count or beginning link channel number this is the initial value copied into the citer field or citer.linkch field when the major loop is completed. the citer fields controls the iteration count and linking during channel execution. if (tcd.biter.e_link = 0) then no channel-to-channel linking (or chaining) is performed after the inner "minor" loop is exhausted. tcd word 5, bits [30:25] are used to form a 15 bit biter field. else after the "minor" loop is exhausted, the edma engine initiates a channel service request at the channel defined by biter.linkch[5:0] by setting that channel?s tcd.start bit. the value contained in biter.linkch[5:0] must not exceed the number of implemented channels. for this device, bits 0:1 of this field are reserved. biter[6:14] beginning ?major? iteration count this is the initial value copied into the citer field or citer.linkch field when the major loop is completed. the citer fields controls the iteration count and linking during channel execution. this 9- or 15-bit count represents the beginning major loop count for the channel. as the major iteration count is exhausted, the contents of the entire 16-bit biter entry is reloaded into the 16-bit citer entry. when the biter field is initially loaded by software, it must be set to the same value as that contained in the citer field. if the channel is configured to execute a single service request, the initial values of biter and citer should be 0x0001.
enhanced direct memory access (edma) 19-30 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 bwc[0:1] bandwidth control this two-bit fi eld provides a mechanism to effectively throttle the amount of bus bandwidth consumed by the edma. in general, as the edma processes the inner minor loop, it continuously generates read/write, read/write, ... sequences until the minor count is exhausted. this field forces the edma to stall after the completion of each read /write access to control the bus request bandwidth seen by the platform?s cross-bar arbitration switch. to minimize start-up latency, bandwidth control stalls are suppressed for the first two ahb bus cycles a nd after the last write of each minor loop. the dynamic priority elevation setting elevates the priority of the edma as seen by the cross-bar arbitration switch for the executing channel. dynamic priority elevation is suppressed during the first two ahb bus cycles. 00 no edma engine stalls 01 dynamic priority elevation 10 edma engine stalls for 4 cycles after each r/w 11 edma engine stalls for 8 cycles after each r/w major.linkch[0:5] link channel number if (tcd.major.e_link = 0) then no channel-to-channel linking (or chaining) is performed after the outer "major" loop counter is exhausted. else after the "major" loop counter is exhausted, the edma engine initiates a channel service request at the channel defined by major.linkch[5:0] by setting that channel?s tcd.start bit. the value contained in major.linkch[5:0] must not exceed the number of implemented channels. for this device, bits 0:1 of this field are reserved. done channel done this flag indicates the edma has completed the outer major loop. it is set by the edma engine as the citer count reaches zero; it is cleared by software, or the hardware when the channel is activated. this bit must be cleared in order to write the major.e_link or e_sg bits. active channel active this flag signals the channel is currently in execution. it is set when channel service begins, and is cleared by the edma engine as the inner minor loop completes or if any error condition is detected. table 19-35. tcdn word 7 (tcdn.{biter, control/status}) field descriptions (continued) name description value
enhanced direct memory access (edma) freescale semiconductor 19-31 pxs20 microcontroller reference manual, rev. 1 major.e_link enable channel-to-channel linking on major loop complete as the channel completes the outer major loop, this flag enables the linking to another channel, defined by major.linkch[5:0]. the link target channel initiates a channel service request via an internal mechanism that sets the tcd.start bi t of the specified channel. to support the dynamic linking coherency model, this field is forced to zero when written to while the tcd.done bit is set. 0 the channel-to-channel linking is disabled. 1 the channel-to-channel linking is enabled. e_sg enable scatter/gather processing as the channel completes the outer major loop, this flag enables scatter/gather processing in the current channel. if enabled, the edma engine uses dlast_sga as a memory pointer to a 0-modulo-32 address containing a 32-byte data structure which is loaded as the transfer control descriptor into the local memory. to support the dynamic scatter/gather coherency model, this field is forced to zero when written to while the tcd.done bit is set. 0 the current channel?s tcd is ?normal? format. 1 the current channel?s tcd specifies a scatter gather format. the dlast_sga field provides a memory pointer to the next tcd to be loaded into this channel after the outer major loop completes its execution. d_req disable request if this flag is set, the edma hardware automatically clears the corresponding dmaerq bit when the current major iteration count reaches zero. 0 the channel?s dmaerq bit is not affected. 1 the channel?s dmaerq bit is cleared when the outer major loop is complete. int_half enable an interrupt when major counter is half complete if this flag is set, the channel generates an interrupt request by setting the appropriate bit in the dmaint register when the current major iteration count reaches the halfway poi nt. specifically, the comparison performed by the edma engine is (citer == (biter >> 1)). this halfway point interrupt request is provided to support double-buffered schemes or other types of data movement where the processor needs an early indication of the transfer?s progress. the halfway complete interrupt is disabled when biter values are less than two. 0 the half-point interrupt is disabled. 1 the half-point interrupt is enabled. table 19-35. tcdn word 7 (tcdn.{biter, control/status}) field descriptions (continued) name description value
enhanced direct memory access (edma) 19-32 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 19.3 functional description this section provides an overview of the microarchi tecture and functi onal operation of the edma module. 19.3.1 edma microarchitecture the edma module is partitioned into two major mo dules: the edma engine and the transfer control descriptor local memory. additionall y, the edma engine is further partitioned into four submodules, which are detailed below. ? edma engine ? addr_path : this module implements registered vers ions of two channel transfer control descriptors: channel "x" and channel ?y?, and is responsible for all the master bus address calculations. all the implemen ted channels provide the exact same functionality. this hardware structure allows the data transfers asso ciated with one channel to be preempted after the completion of a read/write sequence if a highe r priority channel service request is asserted while the first channel is active. once a channel is activated, it runs until the minor loop is completed unless preempted by a higher prio rity channel. this capability provides a mechanism (optionally enabled by dchprin[ecp ]) where a large data move operation can be preempted to minimize the time anothe r channel is blocke d from execution. when any other channel is activated, the contents of its transfer control descriptor is read from the local memory and loaded into the regist ers of the other addr _path.channel_{x,y}. once the inner minor loop completes execut ion, the addr_path hardware wr ites the new values for the tcdn.{saddr, daddr, citer} back into the loca l memory. if the major iteration count is exhausted, additional processing is performed, including the final address pointer updates, reloading the tcdn.citer field, a nd a possible fetch of the next tc dn from memory as part of a scatter/gather operation. ? data_path : this module implements the actual bus ma ster read/write datapath. it includes 32 bytes of register storage (match ing the maximum transfer size) and the necessary mux logic to support any required data alignm ent. the amba-ahb read data bus is the primary input, and int_maj enable an interrupt when major iteration count completes if this flag is set, the channel generates an interrupt request by setting the appropriate bit in the dmaint register when the current major iteration count reaches zero. 0 the end-of-major loop interrupt is disabled. 1 cthe end-of-major loop interrupt is enabled. start channel start if this flag is set, the channel is requesting service. the edma hardware automatically clears this flag after the channel begins execution. 0 the channel is not explicitly started. 1 the channel is explicitly started via a software initiated service request. table 19-35. tcdn word 7 (tcdn.{biter, control/status}) field descriptions (continued) name description value
enhanced direct memory access (edma) freescale semiconductor 19-33 pxs20 microcontroller reference manual, rev. 1 the ahb write data bus is the primary output. the addr_ and data_path modules directly support the 2-stage pipelined amba-ahb bus. the addr_path module represents the 1st stage of th e bus pipeline (the address phase), while the data_path module implements the 2nd stag e of the pipeline (the data phase). ? pmodel_charb : this module implements the first s ection of edma?s programming model as well as the channel arbitration logic. the pr ogramming model registers are connected to the ips bus (not shown). the ipd_req[n] inputs and dma_ipi_int[n] outputs are also connected to this module (via the control logic). ? control : this module provides all the control functions for the edma engine. for data transfers where the source and destination si zes are equal, the edma engine performs a series of source read, destination write ope rations until the number of bytes specified in the inner ?minor loop? byte count has been moved. for de scriptors where the sizes are not equal, multiple access of the smaller size data are required for each refere nce of the larger size. as an example, if the source size references 16-bit data and the des tination is 32-bit data, two reads are performed, then one 32-bit write. ? transfer_control_descriptor local memory ? memory controller : this logic implements the require d dual-ported controller, handling accesses from both the edma engine as well as references from the ips bus. as noted earlier, in the event of simultaneous accesses, the edma engine is given priority and the ips transaction is stalled. the hooks to a bist cont roller for the local tcd memory are included in this module. ? memory array : the tcd is implemented using a single-ported, synchr onous compiled ram memory array 19.3.2 edma basic data flow the basic flow of a data transfer can be pa rtitioned into three se gments. as shown in figure 19-27 , the first segment involves the channel service request. in the diagram, this example uses the assertion of the ipd_req[n] signal to request service for channel n. channel service re quest via software and the tcdn.start bit follows the same basic flow as an ipd_req. the ipd_req[n] input signal is registered internally and then routed to through the edma engine, first through the control module, then into the programming model/channel arbitration (pmodel_char b) module. in the next cycle, th e channel arbitration is performed, either using the fixed-priority or round-robin algorithm. after the arb itration is complete, the activated channel number is sent through the a ddress path (addr_path) and convert ed into the required address to access the tcd local memory. next, the tcd memory is accessed and the required descriptor read from the local memory and loaded into the dma_engi ne.addr_path.channel_{x,y} regi sters. the tcd memory is organized 64-bits in width to mi nimize the time needed to fetch the activated channel?s descriptor and load it into the dma_engine .addr_path.channel_{x,y} registers.
enhanced direct memory access (edma) 19-34 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 19-27. edma operation, part 1 in the second part of the basic data flow as shown in figure 19-28 , the modules associated with the data transfer (addr_path, data_path a nd control) sequence through the requi red source reads and destination writes to perform the actual data movement. the source reads are in itiated and the fetched data is temporarily stored in the data_pa th module until it is gated on to the amba-ahb bus during the destination write. this source re ad/destination write pro cessing continues until th e inner minor byte count has been transferred. the dma_ipd_done[n ] signal is asserted at the end of the minor byte count transfer. j j+1 n-1 sram transfer control descriptor (tcd) edma engine addr_path data_path edma peripheral bus amba bus ipd_req[n-1:0] dma_ipi_int[n-1:0] 0 c o n t r o l pmodel_charb addr wdata[31:0] rdata[31:0] hrdata[63:0] hwdata[63:0] haddr[31:0] dma_ipd_done[n-1:0]
enhanced direct memory access (edma) freescale semiconductor 19-35 pxs20 microcontroller reference manual, rev. 1 figure 19-28. edma operation, part 2 once the inner minor byte count has been moved, the fina l phase of the basic data flow is performed. in this segment, the addr_path logic performs the required updates to ce rtain fields in the channel?s tcd, e.g., saddr, daddr, citer. if the outer ma jor iteration count is exhausted, th en there are additional operations which are performed. these in clude the final addr ess adjustments and reloading of the biter field into the citer. additionally, asserti on of an optional interrupt request occurs at this time, as doe s a possible fetch of a new tcd from memory using the s catter/gather address poi nter included in the descriptor. the updates to the tcd memory and the assertion of an interrupt request are shown in figure 19-29 . j j+1 n-1 sram transfer control descriptor (tcd) edma engine addr_path data_path edma peripheral bus amba bus ipd_req[n-1:0] dma_ipi_int[n-1:0] 0 c o n t r o l pmodel_charb addr wdata[31:0] rdata[31:0] hrdata[63:0] hwdata[63:0] haddr[31:0] dma_ipd_done[n-1:0]
enhanced direct memory access (edma) 19-36 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 19-29. edma operation, part 3 19.3.3 edma performance this section addresses the performance of the edma module, focusing on two separate metrics. in the traditional data movement context, pe rformance is best expressed as the peak data transfer rates achieved using the edma. in most implementa tions, this transfer rate is limit ed by the speed of the source and destination address spaces. in a s econd context where device-paced m ovement of single data values to/from peripherals is dominant, a me asure of the requests which can be se rviced in a fixed time is a more interesting metric. in this environment, the speed of the source and destination address spaces remains important, but the microarchitecture of the edma also factors signifi cantly into the resulting metric. the peak transfer rates for several different source and destination tr ansfers are shown in table 19-36 . the following assumptions apply to table 19-36 and table 19-37 : ? platform sram can be accessed with zero wait-states when viewed from the amba-ahb data phase ? all ips reads require two wait-states, and ips wr ites three wait-states, again viewed from the system bus data phase ? all ips accesses are 32 bits in size j j+1 n-1 sram transfer control descriptor (tcd) edma engine addr_path data_path edma peripheral bus amba bus ipd_req[n-1:0] dma_ipi_int[n-1:0] 0 c o n t r o l pmodel_charb addr wdata[31:0] rdata[31:0] hrdata[63:0] hwdata[63:0] haddr[31:0] dma_ipd_done[n-1:0]
enhanced direct memory access (edma) freescale semiconductor 19-37 pxs20 microcontroller reference manual, rev. 1 table 19-36 presents a peak transfer rate comparison, measured in megabyte s per second. in this table, the platform_sram-to-platform_sram tran sfers occur at the native platform datapath width, i.e., either 32- or 64-bits per access. for a ll transfers involving the ips bus, 32-bit transfer sizes are used. in all cases, the transfer rate includes the time to read the s ource plus the time to write the destination. the second performance metric is a measure of the number of edma requests which ca n be serviced in a given amount of time. for this metric, it is assumed the peripheral request cause s the channel to move a single ips-mapped operand to/from the platform sram. the same timing assumptions used in the previous example apply to this calculation. in partic ular, this metric also re flects the time required to activate the channel. the edma design supports the following hardware service request sequence: ? cycle 1: ipd_req[n] is asserted ? cycle 2: the ipd_req[n] is registered locally in the edma module and qua lified (tcd.start bit initiated requests start at this point with th e registering of the ip s write to tcd word7) ? cycle 3: channel arbitration begins ? cycle 4: channel arbitration completes. the tran sfer control descriptor local memory read is initiated. ? cycle 5 - 6: the first two parts of the activated channel?s tcd is read from the local memory. the memory width to the edma engine is 64 bits, so the entire descriptor ca n be accessed in four cycles. ? cycle 7: the first amba-ahb read cycle is initiated, as the third pa rt of the channe l?s tcd is read from the local memory. depending on the state of the platform?s cros sbar switch, arbi tration at the system bus may insert an ad ditional cycle of delay here. ? cycle 8 - ?: the last part of the tcd is read in. this cycle represen ts the 1st data phase for the read, and the address phase for the destination write. the exact timing from this point is a function of the response ti mes for the channel?s read and write accesses. in this case of an ips read and a plat form sram write, the comb ined data phase time is 4 cycles. for an sram read a nd ips write, it is 5 cycles. ? cycle ?+1: this cycle represents the da ta phase of the last destination write table 19-36. edma peak transfer rates [mb/s] platform speed, width platform sram-to- platform sram 32-bit ips-to- platform sram platform sram-to- 32-bit ips 66.7 mhz, 32-bit 133.3 66.7 53.3 66.7 mhz, 64-bit 266.7 66.6 53.3 83.3 mhz, 32-bit 166.7 83.3 66.7 83.3 mhz, 64-bit 333.3 83.3 66.7 100.0 mhz, 32-bit 200.0 100.0 80.0 100.0 mhz, 64-bit 400.0 100.0 80.0 133.3 mhz, 32-bit 266.7 133.3 106.7 133.3 mhz, 64-bit 533.3 133.3 106.7 150.0 mhz, 32-bit 300.0 150.0 120.0 150.0 mhz, 64-bit 600.0 150.0 120.0
enhanced direct memory access (edma) 19-38 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? cycle ?+2: the edma engine completes the execu tion of the inner minor loop and prepares to write back the required tcdn fields into the local memory. tcd word7 is read and checked for channel linking or scat ter/gather requests. ? cycle ?+3: the appropriate fields in the first pa rt of the tcdn are written back into the local memory ? cycle ?+4: the fields in the second part of the tcdn are written back into the local memory. this cycle coincides with the next channel arbitration cycle start. ? cycle ?+5: the next channel to be activated performs the read of th e first part of its tcd from the local memory. this is equivalent to cycle 4 for the first channel?s service request. assuming zero wait states on the ahb system bus, edma requests can be pr ocessed every 9 cycles. assuming an average of the access times associated with ips-to-sram (4 cycles) and sram-to-ips (5 cycles), edma requests can be pro cessed every 11.5 cycles (4 + (4+5) ? 2 + 3). this is the time from cycle 4 to cycle ??+5?. the resulting peak request rate, as a function of the platform frequency, is shown in table 19-37 . this metric represents millions of requests per second. a general formula to compute the peak re quest rate (with overl apping requests) is: peakreq = freq ? [ entry + (1 + read_ws) + (1 + write_ws) + exit ] where: peakreq - peak request rate freq - platform frequency entry - channel startup (4 cycles) read_ws - wait states seen during the system bus read data phase write_ws - wait states seen duri ng the system bus write data phase exit - channel shutdown (3 cycles) for example: consider a platform with the following characteristics: ? platform sram can be accessed with one wait-state when view ed from the amba-ahb data phase table 19-37. edma peak request rate [mreq/sec] platform speed request rate (zero wait state) request rate (with wait states) 66.6 mhz 7.4 5.8 83.3 mhz 9.2 7.2 100.0 mhz 11.1 8.7 133.3 mhz 14.8 11.6 150.0 mhz 16.6 13.0
enhanced direct memory access (edma) freescale semiconductor 19-39 pxs20 microcontroller reference manual, rev. 1 ? all ips reads require two wait-states, and ips wr ites three wait-states, again viewed from the system bus data phase ? platform operates at 150 mhz for an sram to ips transfer: peakreq = 150 mhz ? [ 4 + (1 + 1) + (1 + 3) + 3 ] cycles = 11.5 mreq/sec for an ips to sram transfer: peakreq = 150 mhz ? [ 4 + (1 + 2) + (1 + 1) + 3 ] cycles = 12.5 mreq/sec assuming an even distribution of the two transfer types, the average peak request rate would be: peakreq = (11.5 mreq/sec + 12.5 mreq/sec) ? 2 = 12.0 mreq/sec the minimum number of cycles to pe rform a single read/write, zero wait states on the system bus, from a cold start (where no channel is executing, edma is idle) are: ? 11 cycles for a software (tcd.start bit) request ? 12 cycles for a hardware (ipd_req signal) request two cycles account for the arbitratio n pipeline and one extra cycle on th e hardware request resulting from the internal registering of the ipd_re q signals. for the peak request rate calculations above, the arbitration and request registering is absorbed in or overlap the previous executing channel. note when channel linking or scatter/gather is enabled, a two cycle delay is imposed on the next channel selecti on and startup. this allows the link channel or the scatter/gather channel to be eligible and considered in the arbitration pool for ne xt channel selection. 19.4 initialization/application information 19.4.1 edma initialization a typical initialization of the edma is: 1. write the dmacr register if a configuration other than the default is desired. 2. write the channel priority levels into the dchp rin registers if a conf iguration other than the default is desired. 3. enable error interrupts in the dmaeei registers if so desired. 4. write the 32 byte tcd for each ch annel that may request service. 5. enable any hardware service requests via the dmaerq register. 6. request channel service by either software (setting the tcd.start bit) or by hardware (slave device asserting its ipd_req signal).
enhanced direct memory access (edma) 19-40 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 after any channel requests service, a channel is select ed for execution based on th e arbitration and priority levels written into the programmer's model. the edma engine will read the entire tcd for the selected channel into its internal address path module. as the tc d is being read, the first transfer is initiated on the ahb bus unless a configuration erro r is detected. transfers from th e source (as defined by the source address, tcd.saddr) to the destinat ion (as defined by the destination address, tcd.daddr ) continue until the specified number of bytes (tcd.nbytes) have been transferred. when the transfer is complete, the edma engine's local tcd.saddr, tc d.daddr, and tcd.citer are written back to the main tcd memory and any minor loop channel linking is performed, if enabled. if the major loop is exhausted, further post processing is executed, i.e. interrupt s, major loop channel li nking, and scatter/gather operations, if enabled. 19.4.2 edma programming errors the edma performs various tests on the transfer c ontrol descriptor to veri fy consistency in the descriptor data. most programming er rors are reported on a per channel basis with the exception of two errors; channel priority error, gpe and cpe in the dmaes register respectively. for all error types other than channe l priority errors, the channel numbe r causing the error is recorded in the dmaes register. if the error sour ce is not removed before the next activation of the problem channel, the error will be detected and recorded again. in general, if priority levels are not unique, the highest channel priority that has an active request will be selected, but the lowest numbered channel with that pr iority will be selected by arbitration and executed by the edma engine. the hardware service request handshake signals, error interrupts and error reporting will be associated with the selected channel. 19.4.3 edma arbitration mode considerations 19.4.3.1 fixed channel arbitration in this mode, the channel service requ est from the highest priority channel will be selected to execute. if the edma is programmed so the ch annels use "fixed" priorities. the advantage of this scenario is that latency can be small for channels that need to be serviced quickly. preemption is available in this scenario only. 19.4.3.2 round-robin ch annel arbitration channels are serviced starting with the highest channel number and rota ting through to the lowest channel number without regard to the ch annel priority levels assigned. this scenario could cause the same bandwid th consumption problem as indicated in section 19.4.3.1, fixed channel arbitration, but all the channels will be serviced.
enhanced direct memory access (edma) freescale semiconductor 19-41 pxs20 microcontroller reference manual, rev. 1 19.4.4 edma transfer 19.4.4.1 single request to perform a simply transfer of ?n? bytes of data w ith one activation, set the major loop to one (tcd.citer = tcd.biter = 1). the data transf er will begin after the channel serv ice request is acknowledged and the channel is selected to exec ute. once the transfer is co mplete, the tcd.done bit will be set and an interrupt will be generated if properly enabled. for example, the following tcd entry is configured to transfer 16 bytes of data. the edma is programmed for one iterati on of the major loop transferring 16 byt es per iteration. the source memory has a byte wide memory port located at 0x1000. the dest ination memory has a word wide port located at 0x2000. the address offsets ar e programmed in increments to match the size of the transfer; one byte for the source and four bytes for the de stination. the final source and destin ation addresses are adjusted to return to their beginning values. tcd.citer = tcd.biter = 1 tcd.nbytes = 16 tcd.saddr = 0x1000 tcd.soff = 1 tcd.ssize = 0 tcd.slast = -16 tcd.daddr = 0x2000 tcd.doff = 4 tcd.dsize = 2 tcd.dlast_sga= -16 tcd.int_maj = 1 tcd.start = 1 (tcd.word7 should be written last after all other fields have been initialized) all other tcd fields = 0 this generates the following sequence of events: 1. ips write to the tcd.start bit requests channel service 2. the channel is selected by arbitration for servicing 3. edma engine writes: tcd.done = 0, tcd.start = 0, tcd.active = 1 4. edma engine reads: channel tcd data from local memory to internal register file 5. the source to destination transfers are executed as follows: a. read_byte(0x1000), rea d_byte(0x1001), read_byte( 0x1002), read_byte(0x1003) b. write_word(0x2000) -> first iteration of the minor loop
enhanced direct memory access (edma) 19-42 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 c. read_byte(0x1004), rea d_byte(0x1005), read_byte( 0x1006), read_byte(0x1007) d. write_word(0x2004) -> second iteration of the minor loop e. read_byte(0x1008), rea d_byte(0x1009), read_byte(0 x100a), read_byte(0x100b) f. write_word(0x2008) -> third iteration of the minor loop g. read_byte(0x100c), r ead_byte(0x100d), read_byte (0x100e), read_byte(0x100f) h. write_word(0x200c) -> last iteration of the minor loop -> major loop complete 6. edma engine writes: tcd.saddr = 0x1000, tc d.daddr = 0x2000, tcd.citer = 1 (tcd.biter) 7. edma engine writes: tcd.active = 0, tcd.done = 1, dmaint[n] = 1 8. the channel retires the edma goes idle or services next channel. 19.4.4.2 multiple requests the next example is the sa me as the previous example, with the exception of transfer ring 32 bytes via two hardware requests. the only fields that change are the major loop iteration count and the final address offsets. the dmais programmed for two iterations of the major loop transferri ng 16 bytes per iteration. after the channel?s hardware requests is enabled in the dmaerq register, channel service requests are initiated by the slave device. tcd.citer = tcd.biter = 2 tcd.slast = -32 tcd.dlast_sga = -32 this would generate the fo llowing sequence of events: 1. first hardware (ipd_req) request for channel service 2. the channel is selected by arbitration for servicing 3. edma engine writes: tcd.done = 0, tcd.start = 0, tcd.active = 1 4. edma engine reads: channel tcd data from local memory to internal register file 5. the source to destination transfers are executed as follows: a. read_byte(0x1000), rea d_byte(0x1001), read_byte( 0x1002), read_byte(0x1003) b. write_word(0x2000) -> first iteration of the minor loop c. read_byte(0x1004), rea d_byte(0x1005), read_byte( 0x1006), read_byte(0x1007) d. write_word(0x2004) -> second iteration of the minor loop e. read_byte(0x1008), rea d_byte(0x1009), read_byte(0 x100a), read_byte(0x100b) f. write_word(0x2008) -> third iteration of the minor loop g. read_byte(0x100c), r ead_byte(0x100d), read_byte (0x100e), read_byte(0x100f) h. write_word(0x200c) -> last iteration of the minor loop
enhanced direct memory access (edma) freescale semiconductor 19-43 pxs20 microcontroller reference manual, rev. 1 6. edma engine writes: tcd.saddr = 0x1010, tcd.daddr = 0x2010, tcd.citer = 1 7. edma engine writes: tcd.active = 0 8. the channel retires -> one iteration of the major loop the edma goes idle or services next channel. 9. second hardware (ipd_req) requests channel service 10. the channel is selected by arbitration for servicing 11. edma engine writes: tcd.done = 0, tcd.start = 0, tcd.active = 1 12. edma engine reads: channel tcd data from local memory to internal register file 13. the source to destination transfers are executed as follows: a. read_byte(0x1010), rea d_byte(0x1011), read_byte( 0x1012), read_byte(0x1013) b. write_word(0x2010) -> first iteration of the minor loop c. read_byte(0x1014), rea d_byte(0x1015), read_byte( 0x1016), read_byte(0x1017) d. write_word(0x2014) -> second iteration of the minor loop e. read_byte(0x1018), rea d_byte(0x1019), read_byte(0 x101a), read_byte(0x101b) f. write_word(0x2018) -> third iteration of the minor loop g. read_byte(0x101c), r ead_byte(0x101d), read_byte (0x101e), read_byte(0x101f) h. write_word(0x201c) -> last iteration of the minor loop -> major loop complete 14. edma engine writes: tcd.saddr = 0x1000, tc d.daddr = 0x2000, tcd.citer = 2 (tcd.biter) 15. edma engine writes: tcd.active = 0, tcd.done = 1, dmaint[n] = 1 16. the channel retires -> major loop complete the edma goes idle or se rvices the next channel. 19.4.5 tcd status 19.4.5.1 minor loop complete there are two methods to test for minor loop completi on when using software init iated service requests. the first method is to read the tcd.citer field and test for a change. anothe r method may be extracted from the sequence shown below. the second method is to test the tcd.start bit an d the tcd.active bit. the minor loop complete condition is indicated by both bits reading zer o after the tcd.start was written to a one. polling the tcd.active bit may be inconclusi ve because the active status may be missed if the channel execution is short in duration. the tcd status bits execute the following sequence for a software activated channel: 1. tcd.start = 1, tcd.active = 0, tcd.done = 0 (channel service request via software) 2. tcd.start = 0, tcd.active = 1, tc d.done = 0 (channel is executing)
enhanced direct memory access (edma) 19-44 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 3. tcd.start = 0, tcd.active = 0, tc d.done = 0 (channel has complete d the minor loop and is idle) or tcd.start = 0, tcd.active = 0, tc d.done = 1 (channel has complete d the major loop and is idle) the best method to test for minor loop completion wh en using hardware initiate d service requests is to read the tcd.citer field and test for a change. the hardware request and acknowledge handshakes signals are not visible in the programmer?s model. the tcd status bits execute the following sequence for a hardware activated channel: 1. ipd_req asserts (channel se rvice request via hardware) 2. tcd.start = 0, tcd.active = 1, tc d.done = 0 (channel is executing) 3. tcd.start = 0, tcd.active = 0, tc d.done = 0 (channel has complete d the minor loop and is idle) or tcd.start = 0, tcd.active = 0, tc d.done = 1 (channel has complete d the major loop and is idle) for both activation types, the major loop complete stat us is explicitly indica ted via the tcd.done bit. the tcd.start bit is cleared automatically when th e channel begins execution regardless of how the channel was activated. 19.4.5.2 active channel tcd reads the edma will read back the 'true' tcd.saddr, tcd .daddr, and tcd.nbytes values if read while a channel is executing. the 'true' values of the saddr, daddr, and nbytes are the values the edma engine is currently using in its internal register file and not the values in the tcd local memory for that channel. the addresses (saddr and daddr) and nbyt es (decrements to zero as the tr ansfer progresses) can give an indication of the progress of the tr ansfer. all other values are read back from the tcd local memory. 19.4.5.3 preemption status preemption is only available when fixed arbitration is selected for channel arbitration modes. a preempt-able situation is one in wh ich a preempt-enabled channel is r unning and a higher priority request becomes active. when the edma engine is not operating in fixe d channel arbitration mode, the determination of the relative priority of the actively running and the out standing requests become undefined. channel priorities are treated as equa l (constantly rotatin g) when round-robin arbitration mode is selected. the tcd.active bit for the preempted channel remain s asserted throughout the preemption. the preempted channel is temporarily suspended wh ile the preempting channel executes one iteration of the major loop. two tcd.active bits set at the same time in the overa ll tcd map indicates a high er priority channel is actively preempting a lo wer priority channel. the worst case latency when switching to a preempt channel is the summation of: ? arbitration latency (2 cycles) ? bandwidth control stalls (if enabled)
enhanced direct memory access (edma) freescale semiconductor 19-45 pxs20 microcontroller reference manual, rev. 1 ? the time to execute two read/write sequences (including ahb bus holds ; a system dependency driven by the slave devices or the crossbar) 19.4.6 channel linking channel linking (or chaining) is a m echanism where one channel sets the tcd.start bit of another channel (or itself) thus initiating a service request for that channel. this operation is automatically performed by the edma engine at the conclusion of the major or minor loop when properly enabled. the minor loop channel linking occurs at the completio n of the minor loop (or one iteration of the major loop). the tcd.citer.e_link field are used to determ ine whether a minor loop link is requested. when enabled, the channel link is made after each iterati on of the major loop except for the last. when the major loop is exhausted, only the major loop channel link fields are used to determine if a channel link should be made. for example, with the initial fields of: tcd.citer.e_link = 1 tcd.citer.linkch = 0xc tcd.citer value = 0x4 tcd.major.e_link = 1 tcd.major.linkch = 0x7 will execute as: 1. minor loop done -> set channel 12 tcd.start bit 2. minor loop done -> set channel 12 tcd.start bit 3. minor loop done -> set channel 12 tcd.start bit 4. minor loop done, major loop done -> set channel 7 tcd.start bit when minor loop linking is enabled (t cd.citer.e_link = 1), the tcd.citer field uses a nine bit vector to form the current iteration count. when minor loop linking is disabled (t cd.citer.e_link = 0), the tcd.citer fi eld uses a 15 bit vector to form the current iteration count. the bits associated with the tcd.citer.linkch field are concatenated onto the citer value to increase the range of the citer. note the tcd.citer.e_link bit and the tcd .biter.e_link bit must equal or a configuration error will be reported. th e citer and biter vector widths must be equal to calculate the major loop, half-way done interrupt point. 19.4.7 dynamic programming this section provides recommended methods to cha nge the programming model during channel execution.
enhanced direct memory access (edma) 19-46 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 19.4.7.1 dynamic priority changing the following two options are r ecommended for dynamically changing channel priority levels: 1. switch to round-robin channel arbi tration mode, change the channel priorities, then switch back to fixed arbitration mode. 2. disable all the channels, then ch ange the channel priorities, then enable the appropriate channels. 19.4.7.2 dynamic channel linki ng and dynamic scatter/gather dynamic channel linking and dynamic scatter/gather is the process of changing the tcd.major.e_link or tcd.e_sg bits during channel execution. these bits are read from the tcd local memory at the end of channel execution thus allowing the user to en able either feature dur ing channel execution. because the user is allowed to change the configur ation during execution, a c oherency model is needed. consider the scenario where the user attempts to execute a dynamic channel link by enabling the tcd.major.e_link bit at the same time the edma engi ne is retiring the channel. the tcd.major.e_link would be set in the programmer?s m odel, but it would be unclear whet her the actual link was made before the channel retired. the following coherency model is recommended when executing a dynamic channel link or dynamic scatter/gather request: 1. set the tcd.major.e_link bit. 2. read back the tcd.major.e_link bit. 3. test the tcd.major.e_link request status: a. if the bit is set, the dynamic link attempt was successful. b. if the bit is cleared, the attempted dynami c link did not succeed, the channel was already retiring. this same coherency model is tr ue for dynamic scatter/gather opera tions. for both dynamic requests, the tcd local memory controller forces the tcd.major.e_ link and tcd.e_sg bits to zero on any writes to a channel?s tcd.word7 after that channel?s tcd.done bit is set indicating the major loop is complete. note the user must clear the tcd.done bi t before writing th e tcd.major.e_link or tcd.e_sg bits. the tcd.done bit is cleared automati cally by the edma engine after a channel begins execution.
enhanced motor control timer (etimer) freescale semiconductor 20-1 pxs20 microcontroller reference manual, rev. 1 chapter 20 enhanced motor control timer (etimer) 20.1 introduction this device contains up to three 1 etimer modules, referred to as etimer_0, etimer_1, and etimer_2. all etimer modules have 6 channels. et imer_0 also has a watchdog timer function. each 16 bit counter/timer channel c ontains a prescaler, a counter, a lo ad register, a hold register, two queued capture registers, two compare registers, two compare pr eload registers, and four control registers. note this document uses the terms ?tim er? and ?counter? interchangeably because the counter/timers may perform either or both tasks. the load register provides the initialization value to the counter when the counter?s terminal value has been reached. for true modulo counting the counter can also be initialized by the cmpld1 or cmpld2 registers. the hold register captures the counter?s value when other counters are being r ead. this feature supports the reading of cascaded counters coherently. the capture registers enable an external signal to take a ?snap shot? of the counter?s current value. the comp1 and comp2 registers provide the values to which the counter is compared. if a match occurs, the oflag signal can be set, cleared, or toggled. at match time, an inte rrupt is generated if enabled, and the new compare value is loaded into the comp1 or comp2 registers from cmpld1 and cmpld2 if enabled. the prescaler provides different time base s useful for clocking the counter/timer. the counter provides the ability to c ount internal or external events. within the etimer module (set of 6 timer/c ounter channels) the input pins are shareable. the etimer block diagram is shown in figure 20-1 . 1.two in the 144-pin package, three in the 257-pin package.
enhanced motor control timer (etimer) 20-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 20-1. etimer block diagram each of the timer/counter channels within the etimer are shown in figure 20-2 . watchdog timer channel 0 channel n channel 1 channel 2 filter filter filter filter =1 error signal oflag 0 oflag 1 oflag 2 oflag n wdf count ipbus clock reset dma inp 0 inp n inp 2 inp 1 filter aux inp 0 filter aux inp 1 filter aux inp 2 filter aux inp n
enhanced motor control timer (etimer) freescale semiconductor 20-3 pxs20 microcontroller reference manual, rev. 1 figure 20-2. etimer channel block diagram 20.2 features the etimer module design include s these distinctive features: ? 6 16-bit counters/timers ? count up/down ? counters are cascadable ? enhanced programmable up/down modulo counting ? max count rate equals peripher al clock/2 for external clocks ? max count rate equals periph eral clock for internal clocks ? count once or repeatedly ? counters are preloadable ? compare registers are preloadable ? counters can share available input pins ? separate prescaler for each counter ? each counter has capture and compare capability ? continuous and single shot capture for enhanced speed measurement ? dma support of capture registers and compare registers ? 24-bit watchdog capability to de tect stalled quadrature counting ? oflag comparison for safe ty critical applications ? programmable operation duri ng debug mode and stop mode switch matrix/ polarity select input filter prescaler edge detect control status & dma i/f control counter load hold capture1 comp1 comp2 cmpld1 cmpld2 oflag control comparator comparator up/dn wd count peripheral clock output output disable primary input secondary input other counters capture1 capture1 capture1 capture1 capture1 capture1 capture2
enhanced motor control timer (etimer) 20-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? programmable input filter ? counting start can be s ynchronized across counters 20.3 external signal descriptions the etimer module has 6 external signals that can be used as either in puts or outputs. there are also 3 auxiliary inputs. the etimer also interfaces to the peripheral bus. 20.3.1 tio[5:0] - timer input/outputs these pins can be independently configured to be either time r input sources or output flags. 20.3.2 tai[2:0] - ti mer auxiliary inputs these pins act as alternate input choices for the timer channels. the module-to-module input signals are described in table 20-1 . additional information on module-to-module interaction is shown in figure 13-2 . table 20-1. etimer module-to-module input signals source (output ports) destination (input ports) module name port name module name port name ctu etimer0_trg etimer_0 aux_0 etimer_1 t2 etimer_0 aux_1 dspi_1 sck etimer_0 aux_2 ctu etimer1_trg etimer_1 aux_0 etimer_0 t2 etimer_1 aux_1 flexray fr_ca_tx etimer_1 aux_2 ctu etimer2_trg etimer_2 aux_0 ctu etimer3_trg etimer_2 aux_1
enhanced motor control timer (etimer) freescale semiconductor 20-5 pxs20 microcontroller reference manual, rev. 1 20.4 memory map and register definition 20.4.1 module memory map table 20-2. etimer memory map address reg name description timer channel registers (repeated for each channel as chnl goes from 0 to 5) etimer_base + ($20 * chnl) + $0 comp1 compare register 1 etimer_base + ($20 * chnl) + $2 comp2 compare register 2 etimer_base + ($20 * chnl) + $4 capt1 capture register 1 etimer_base + ($20 * chnl) + $6 capt2 capture register 2 etimer_base + ($20 * chnl) + $8 load load register etimer_base + ($20 * chnl) + $a hold hold register etimer_base + ($20 * chnl) + $c cntr counter register etimer_base + ($20 * chnl) + $e ctrl1 control register 1 etimer_base + ($20 * chnl) + $10 ctrl2 control register 2 etimer_base + ($20 * chnl) + $12 ctrl3 control register 3 etimer_base + ($20 * chnl) + $14 sts status register etimer_base + ($20 * chnl) + $16 intdma interrupt and dma enable register etimer_base + ($20 * chnl) + $18 cmpld1 comparator load register 1 etimer_base + ($20 * chnl) + $1a cmpld2 comparator load register 2 etimer_base + ($20 * chnl) + $1c ccctrl compare and capture control register etimer_base + ($20 * chnl) + $1e filt input filter register watchdog timer registers etimer_base + $100 wdtol 1 notes: 1 exists only on etimer_0 watchdog time-out low register etimer_base + $102 wdtoh 1 watchdog time-out high register configuration registers etimer_base + $10c enbl channel enable register etimer_base + $110 dreq0 dma request 0 select register etimer_base + $112 dreq1 dma request 1 select register
enhanced motor control timer (etimer) 20-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 20.4.2 register descriptions the address of a register is the sum of a base address and an address offs et. the base addres s is defined at the chip level and the address offset is defined at the module level. there are a set of registers for each timer channel, a set for the watchdog ti mer, a set for the fault inputs, an d a set of configuration registers. 20.4.3 timer channel registers these registers are repeated for each timer channel. th e base address of channel 0 is the same as the base address of the etimer module as a whole. the base ad dress of channel 1 is $20. this is the base address of the etimer module plus an offset based on the number of bytes of registers in a timer channel. the base address of each subsequent timer ch annel is equal to the base address of the previous channel plus this same offset of $20. 20.4.3.1 compare register 1 (comp1) figure 20-3. compare register 1 (comp1) this read/write register stores the value used for comparison with the c ounter value. this register is not byte accessible. more explanation on the use of comp1 can be found in section 20.5.2.13, usage of compare registers. 20.4.3.2 compare register 2 (comp2) figure 20-4. compare register 2 (comp2) this read/write register stores the value used for comparison with the c ounter value. this register is not byte accessible. more explanation on the use of comp2 can be found in section 20.5.2.13, usage of compare registers. 20.4.3.3 capture register 1 (capt1) figure 20-5. capture register 1 (capt1) etimer_chnl _base + $0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 read comp1[15:0] write reset 00000 0000000000 0 etimer_chnl _base + $2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 read comp2[15:0] write reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 etimer_chnl_ base + $4 0123456789101112131415 read capt1[15:0] write reset 0000000000000000
enhanced motor control timer (etimer) freescale semiconductor 20-7 pxs20 microcontroller reference manual, rev. 1 this read only register stores the value captured fr om the counter. exactly when a capture occurs is defined by the cpt1mode bits. this is actually a 2-deep fifo and not a single register. this register is not byte accessible. 20.4.3.4 capture register 2 (capt2) figure 20-6. capture register 2 (capt2) this read only register stores the value captured fr om the counter. exactly when a capture occurs is defined by the cpt2mode bits . this is actually a 2-deep fifo and not a single register. this register is not byte accessible. 20.4.3.5 load register (load) figure 20-7. load register (load) this read/write register stores the value used to initialize th e counter. this register is not byte accessible. 20.4.3.6 hold register (hold) figure 20-8. hold register (hold) this read only register st ores the counter?s value whenever any of the other counters within a module are read. this is used to support c oherent reading of cascaded counters. 20.4.3.7 counter register (cntr) figure 20-9. counter (cntr) etimer_chnl_ base + $6 0123456789101112131415 read capt2[15:0] write reset 0000000000000000 etimer_chnl _base + $8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 read load[15:0] write reset 00000 00000000000 etimer_chnl _base + $a 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 read hold[15:0] write reset 0000 0 00000000000 etimer_chnl _base + $c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 read cntr[15:0] write reset 0000 0 00000000000
enhanced motor control timer (etimer) 20-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 this read/write register is the counter for this cha nnel of the timer module. this register is not byte accessible. 20.4.3.8 control register 1 (ctrl1) figure 20-10. control register 1 (ctrl1) cntmode - count mode these bits control the basic count ing and behavior of the counter. prisrc - primary count source these bits select the primary count source. etimer_chnl _base + $e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 read cntmode[2:0] prisrc[4:0] once len gth dir secsrc[4:0] write reset 00000 000 0 0000000 table 20-3. count mode values value meaning 000 no operation 001 count rising edges of primary source 1 notes: 1 rising edges counted only when pips = 0. falling edges counted when pips = 1. if primary count source is ip bus clock, only rising edges are counted regardless of pips value. 010 count rising and falling edges of primary source 2 2 ip bus clock divide by 1 can not be used as a primary count source in edge count mode. 011 count rising edges of primary source while secondary input high active 100 quadrature count mode, uses primary and secondary sources 101 count primary source rising edges, secondary source specifies direction (1 = minus) 3 3 rising edges counted only when pips = 0. falling edges counted when pips = 1. 110 edge of secondary source triggers primary count till compare 111 cascaded counter mode, up/down 4 4 primary count source must be set to one of the counter outputs. table 20-4. primary count source values value meaning 00000 counter #0 input pin 00001 counter #1 input pin 00010 counter #2 input pin 00011 counter #3 input pin 00100 counter #4 input pin 00101 counter #5 input pin
enhanced motor control timer (etimer) freescale semiconductor 20-9 pxs20 microcontroller reference manual, rev. 1 note a timer selecting its own output as it s primary count source is not a legal choice. the result is no counting. once - count once this bit selects continuous or one shot counting mode. 1 = count until compare and then st op. when output mode $4 is used, the counter re-initializes after reaching the comp1 value and continues to count to the comp2 value then stops. 0 = count repeatedly. 00110 reserved 00111 reserved 01000 auxiliary input #0 pin 01001 auxiliary input #1 pin 01010 auxiliary input #2 pin 01011 reserved 01100 reserved 01101 reserved 01110 reserved 01111 reserved 10000 counter #0 output 10001 counter #1 output 10010 counter #2 output 10011 counter #3 output 10100 counter #4 output 10101 counter #5 output 10110 reserved 10111 reserved 11000 ip bus clock divide by 1 prescaler 11001 ip bus clock divide by 2 prescaler 11010 ip bus clock divide by 4 prescaler 11011 ip bus clock divide by 8 prescaler 11100 ip bus clock divide by 16 prescaler 11101 ip bus clock divide by 32 prescaler 11110 ip bus clock divide by 64 prescaler 11111 ip bus clock divide by 128 prescaler table 20-4. primary count source values (continued) value meaning
enhanced motor control timer (etimer) 20-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 length - count length this bit determines whether the counter counts to the compare value and then re-i nitializes itself to the value specified in the load, cmpld1, or cmpld2 registers, or the counter continues counting past the compare value, to the binary roll over. 1 = count until compare, then reinitialize. the value that the counter is reinitialized with depends on the settings of clc1 and clc2. if neither of these indicates the count er is to be loaded from one of the cmpld registers, then the load register is used to rein itialize the counter upon matching ei ther comp register. if one of clc1 or clc2 indicates that the counter is to be loaded from one of the cmpld registers, then the counter will reinitiali ze to the value in the appropria te cmpld regist er upon a match with the appropriate comp register. if both of the clc1 and clc2 fields indicate that the counter is to be loaded from the cmpld regist ers, then cmpld1 will have priority if both compares happen at the same value. when output mode $4 is used, alternating values of comp1 and comp2 are used to generate successful comparisons. for example, the c ounter counts until comp1 value is reached, re-initializes, then counts until comp2 value is reached, re-initializ es, then counts until comp1 value is reached, etc. 0 = continue counting to roll over. dir - count direction this bit selects either the normal count direction up , or the reverse direction, down . 1 = count down 0 = count up secsrc - secondary count source these bits identify the source to be used as a count command or timer command. the selected input can trigger the timer to capture the current value of the cntr register. the select ed input can also be used to specify the count direction. the polarity of the signal can be inverted by the sips bit of the ctrl2 register. table 20-5. secondary count source values value meaning 00000 counter #0 input pin 00001 counter #1 input pin 00010 counter #2 input pin 00011 counter #3 input pin 00100 counter #4 input pin 00101 counter #5 input pin 00110 reserved 00111 reserved 01000 auxiliary input #0 pin 01001 auxiliary input #1 pin
enhanced motor control timer (etimer) freescale semiconductor 20-11 pxs20 microcontroller reference manual, rev. 1 20.4.3.9 control register 2 (ctrl2) figure 20-11. control register 2 (ctrl2) oen - output enable. this bit determines the dire ction of the external pin. 1 = oflag output signal will be driven on the extern al pin. other timer channels using this external pin as their input will see the driven value. th e polarity of the signal wi ll be determined by the ops bit. 0 = the external pin is configured as an input. rdnt - redundant channel enable. this bit enables redundant channel checking between adjacent channels (0 and 1, 2 and 3, 4 and 5). when this bit is clear, the rcf bit in this channel cannot be set. when this bit is set, the rcf bit will be set by a miscompare between th e oflag of this channe l and the oflag of it s redundant adjacent channel which will cause the output of this channel to go inactive (logi c 0 prior to consideration of the ops bit). 1 = enable redundant channel checking. 0 = disable redundant channel checking. 01010 auxiliary input #2 pin 01011 reserved 01100 reserved 01101 reserved 01110 reserved 01111 reserved 10000 counter #0 output 10001 counter #1 output 10010 counter #2 output 10011 counter #3 output 10100 counter #4 output 10101 counter #5 output 10110?11111 reserved etimer_chnl _base + $10 0123456789101112131415 read oen rdn t in- put val 0 cof rc coinit sips pips ops mst r outmode[3:0] write for ce reset 00000000000 0 0000 table 20-5. secondary count source values (continued) value meaning
enhanced motor control timer (etimer) 20-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 input - external input signal this read only bit reflects the curr ent state of the signal selected via secsrc after application of the sips bit and filtering. val - forced oflag value this bit determines the value of the oflag ou tput signal when a soft ware triggered force command occurs. force- force the oflag output this write only bit forces the current value of the val bit to be written to the oflag output. this bit always reads as a zero. the val and force bits can be written simultaneously in a single write operation. write to the force bit onl y if outmode is 0000 (software c ontrolled). setting this bit while the outmode is a different va lue may yield unpredictable results. cofrc - co-channel oflag force this bit enables the compare from a nother channel within the module to force the state of this counter?s oflag output signal. 1 = other channels may force the oflag of this channel. 0 = other channels cannot for ce the oflag of this channel. coinit - co-channel initialization these bits enable another channel within the module to force the re-initializat ion of this channel when the other channel has an active compare event. sips - secondary source input polarity select this bit inverts the polarity of the si gnal selected by the secsrc bits. 1 = inverted polarity. 0 = true polarity. pips - primary source input polarity select this bit inverts the polarity of the signal selected by the prisrc bits. this only applies if the signal selected by prisrc is not the prescaled ip bus clock. 1 = inverted polarity. 0 = true polarity. ops - output polarity select. table 20-6. values for co-channel initilization value meaning 00 other channels cnnot force re -initialization of this channel. 01 other channels may force a re-initialization of this channel?s counter using the load reg. 10 other channels may force a re-initializati on of this channel?s counter with the cmpld2 reg when this channel is counting down or the cmpld1 reg when this channel is counting up. 11 reserved.
enhanced motor control timer (etimer) freescale semiconductor 20-13 pxs20 microcontroller reference manual, rev. 1 this bit inverts the oflag output signal polarity. 1 = inverted polarity. 0 = true polarity. mstr - master mode this bit enables the compare functi on?s output to be broadcasted to th e other channels in the module. the compare signal then can be used to reinitialize the other counter s and/or force th eir oflag signal outputs. 1 = enable broadcast of compare events from this channel. 0 = disable broadcast of compare events from this channel. outmode - output mode these bits determine the mode of operation for the oflag output signal. 20.4.3.10 control register 3 (ctrl3) figure 20-12. control register 3 (ctrl3) stpen - stop actions enable table 20-7. outmode values value meaning 0000 software controlled 0001 clear oflag output on successful compare (comp1 or comp2) 0010 set oflag output on successful compare (comp1 or comp2) 0011 toggle oflag output on successful compare (comp1 or comp2) 0100 toggle oflag output using alternating compare registers 0101 set on compare with comp1, cleared on secondary source input edge 0110 set on compare with comp2, cleared on secondary source input edge 0111 set on compare, cleared on counter roll-over 1000 set on successful compare on comp1, clear on successful compare on comp2 1001 asserted while counter is active , cleared when counter is stopped. 1010 asserted when counting up, cleared when counting down. 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 enable gated clock output while counter is active etimer_chnl _base + $12 0 1 2 3 4 5 6 7 8 9 101112131415 read stp en roc 0 1 1 1 1 c2fcnt[2:0] c1fcnt[2:0] dbgen [1:0] write reset 0000111100000000
enhanced motor control timer (etimer) 20-14 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 this bit allows the tri-stating of the timer output during stop mode. 1 = output enable is disabled during stop mode. 0 = output enable is unaffected by stop mode. roc - reload on capture these bits enable the capture function to cause the counter to be reloaded from the load register. c2fcnt - capt2 fifo word count this field reflects the number of words in the capt2 fifo. c1fcnt - capt1 fifo word count this field reflects the number of words in the capt1 fifo. dbgen - debug actions enable these bits allow the counter channel to perform certain actions in response to the chip entering debug mode. 20.4.3.11 status register (sts) figure 20-13. status register (sts) wdf - watchdog time-out flag table 20-8. values for reload on capture value meaning 00 do not reload the counter on a capture event. 01 reload the counter on a capture 1 event. 10 reload the counter on a capture 2 event. 11 reload the counter on both a capture 1 event and a capture 2 event. table 20-9. values for dbgen value meaning 00 continue with normal operation during debug mode. (default) 01 halt channel counter during debug mode. 10 force oflag to logic 0 (prior to consideration of the ops bit) during debug mode. 11 both halt counter and force oflag to 0 during debug mode. etimer_chnl _base + $14 0 1 2 3 4 5 6 7 8 9 101112131415 read 00 0 0 0 0 wdf rcf icf2 icf1 iehf ielf tof tcf2 tcf1 tcf write reset 0000000000000000
enhanced motor control timer (etimer) freescale semiconductor 20-15 pxs20 microcontroller reference manual, rev. 1 this bit is set when the watchdog times out by c ounting down to zero. the watchdog must be enabled for time-out to occur and channe l 0 must be in quadrature decode count mode (cntmode = 100). this bit is cleared by writing a 1 to this bit posit ion after either writing a non-zero value to wdtol and/or wdtoh or exiting quadrature decode c ounting mode. this bit is only in channel 0. rcf - redundant channel flag this bit is set when there is a miscompare between this channel? s oflag value and the oflag value of the corresponding redundant channel. corres ponding channels are grouped together in the following pairs: 0 and 1, 2 and 3, or 4 and 5. this bit can only be set if the rdnt bit is set. this bit is cleared by writing a 1 to this bit position. th is bit is only in even channels (0, 2, and 4). icf2 - input capture 2 flag this bit is set when an input capture event (as defined by cpt2mode) occurs while the counter is enabled and the word count of the capt2 fifo exc eeds the value of the cfwm field. this bit is cleared by writing a one to this bit position if icf2de is cl ear (no dma) or it is cleared automatically by the dma access if icf2de is set (dma). icf1 - input capture 1 flag this bit is set when an input capture event (as defined by cpt1mode) occurs while the counter is enabled and the word count of the capt1 fifo exc eeds the value of the cfwm field. this bit is cleared by writing a one to this bit position if icf1de is cl ear (no dma) or it is cleared automatically by the dma access if icf1de is set (dma). iehf - input edge high flag this bit is set when a positive input transition o ccurs (on an input selected by secsrc) while the counter is enabled. this bit is cleared by writing a one to this bit position. ielf - input edge low flag this bit is set when a negative input transition occurs (on an i nput selected by secsrc) while the counter is enabled. this bit is cleared by writing a one to this bit position. tof - timer overflow flag this bit is set when the counter rolls over it s maximum value $ffff or $0000 (depending on count direction). this bit is cleared by writing a one to this bit location. tcf2 - timer compare 2 flag this bit is set when a successful compare occurs with comp2. this bit is cleared by writing a one to this bit location. tcf1 - timer compare 1 flag this bit is set when a successful compare occurs with comp1. this bit is cleared by writing a one to this bit location. tcf - timer compare flag this bit is set when a successful compare occurs. this bit is cleared by writing a one to this bit location.
enhanced motor control timer (etimer) 20-16 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 20.4.3.12 interrupt and dma enable register (intdma) figure 20-14. interrupt and dma enable register (intdma) icf2de - input capture 2 flag dma enable setting this bit enables dma read requests for capt2 when the icf2 bit is set. do not set both this bit and the icf2ie bit. icf1de - input capture 1 flag dma enable setting this bit enables dma read requests for capt1 when the icf1 bit is set. do not set both this bit and the icf1ie bit. cmpld2de - comparator load register 2 flag dma enable setting this bit enables dma write requests to the cmpld2 register whenever data is transferred out of the cmpld2 reg into either the cntr, comp1, or comp2 registers. cmpld1de - comparator load register 1 flag dma enable setting this bit enables dma write requests to the cmpld1 register whenever data is transferred out of the cmpld1 reg into either the cntr, comp1, or comp2 registers. wdfie - watchdog flag interrupt enable setting this bit enables interrupts when the wdf bit is set. this bit is only in channel 0. rcfie - redundant channel flag interrupt enable setting this bit enables interrupts when the rcf bit is set. this bit is only in even channels (0, 2, 4, and 6). icf2ie - input capture 2 flag interrupt enable setting this bit enables inte rrupts when the icf2 bit is set. do not set both this bit and the icf2de bit. icf1ie - input capture 1 flag interrupt enable setting this bit enables inte rrupts when the icf1 bit is set. do not set both this bit and the icf1de bit. iehfie - input edge high flag interrupt enable setting this bit enables interrupts when the iehf bit is set. ielfie - input edge low flag interrupt enable setting this bit enables interrupts when the ielf bit is set. tofie - timer overflow flag interrupt enable etimer_chnl _base + $16 0 1 2 3 4 5 6 7 8 9 101112131415 read icf2 de icf1 de cmp ld2 de cmp ld1 de 0 0 wdf ie rcf ie icf2 ie icf1 ie iehf ie ielf ie tof ie tcf 2ie tcf 1ie tcf ie write reset 0000000000000000
enhanced motor control timer (etimer) freescale semiconductor 20-17 pxs20 microcontroller reference manual, rev. 1 setting this bit enables interrupts when the tof bit is set. tcf2ie - timer compare 2 flag interrupt enable setting this bit enables interrupts when the tcf2 bit is set. tcf1ie - timer compare 1 flag interrupt enable setting this bit enables interrupts when the tcf1 bit is set. tcfie - timer compare flag interrupt enable setting this bit enables interrupts when the tcf bit is set. 20.4.3.13 comparator load register 1 (cmpld1) figure 20-15. comparator load 1 (cmpld1) this read/write register is the prel oad value for the comp1 register. this register can also be used to load into the cntr register. this regist er is not byte accessible. more information on th e use of this register can be found in section 20.5.2.14, usage of compare load registers. 20.4.3.14 comparator load register 2 (cmpld2) figure 20-16. comparator load 2 (cmpld2) this read/write register is the prel oad value for the comp2 register. this register can also be used to load into the cntr register. this regist er is not byte accessible. more information on th e use of this register can be found in section 20.5.2.14, usage of compare load registers. 20.4.3.15 compare and capture control register (ccctrl) figure 20-17. compare and capture control register (ccctrl) clc2 - compare load control 2 etimer_chnl _base + $18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 read cmpld1[15:0] write reset 0000 0 00000000000 etimer_chnl _base + $1a 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 read cmpld2[15:0] write reset 0000 0 0000000000 0 etimer_chnl _base + $1c 0123456789101112131415 read clc2[1:0] clc1[1:0] cmpmode [1:0] cpt2 mode[1:0] cpt1 mode[1:0] cfwm[1:0] one shot arm write reset 00000000000000 0 0
enhanced motor control timer (etimer) 20-18 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 these bits control when comp2 is preloaded. it also controls the loading of cntr. clc1 - compare load control 1 these bits control when comp1 is preloaded. it also controls the loading of cntr. cmpmode - compare mode these bits control when the comp1 and comp2 re gisters are used in regards to the counting direction. table 20-10. values for compare load control 2 value meaning 000 never preload 001 reserved 010 load comp2 with cmpld1 upon successf ul compare with the value in comp1. 011 load comp2 with cmpld1 upon successf ul compare with the value in comp2. 100 load comp2 with cmpld2 upon successf ul compare with the value in comp1. 101 load comp2 with cmpld2 upon successf ul compare with the value in comp2. 110 load cntr with cmpld2 upon successful compare with the value in comp1. 111 load cntr with cmpld2 upon successful compare with the value in comp2. table 20-11. values for compare load control 1 value meaning 000 never preload 001 reserved 010 load comp1 with cmpld1 upon successful compare with the value in comp1. 011 load comp1 with cmpld1 upon successful compare with the value in comp2. 100 load comp1 with cmpld2 upon successful compare with the value in comp1. 101 load comp1 with cmpld2 upon successful compare with the value in comp2. 110 load cntr with cmpld1 upon successful compare with the value in comp1. 111 load cntr with cmpld1 upon successful compare with the value in comp2. table 20-12. values for compare mode value meaning 00 comp1 register is used when the counter is counting up. comp2 register is used when the counter is counting up. 01 comp1 register is used when the counter is counting down. comp2 register is used when the counter is counting up. 10 comp1 register is used when the counter is counting up. comp2 register is used when the counter is counting down. 11 comp1 register is used when the counter is counting down. comp2 register is used when the counter is counting down.
enhanced motor control timer (etimer) freescale semiconductor 20-19 pxs20 microcontroller reference manual, rev. 1 cpt2mode - capture 2 mode control these bits control the operation of the capt2 register as well as the operation of the icf2 flag by defining which input edges cause a capture event. the input source is the secondary count source. cpt1mode - capture 1 mode control these bits control the operation of the capt1 register as well as the operation of the icf1 flag by defining which input edges cause a capture event. the input source is the secondary count source. cfwm - capture fifo water mark this field represents the water ma rk level for the capt1 and capt2 fi fos. the capture flags, icf1 and icf2, won?t be set until the wo rd count of the corres ponding fifo is greater than this water mark level. oneshot - one s hot capture mode this bit selects between free running and one shot mode for the i nput capture circuitry. 1 = one shot mode is selected. if both capture circuits are enabled, then capture ci rcuit 1 is armed first after the arm bit is set. once a capture occurs, capture circ uit 1 is disarmed and capture ci rcuit 2 is armed. after capture circuit 2 performs a capture , it is disarmed and the arm bit is cleared. no further captures will be performed until the arm bit is set again. if only one of the capture circui ts is enabled, then a single ca pture will occur on the enabled capture circuit and the ar m bit is then cleared. 0 = free running mode is selected if both capture circuits are enabled, then capture ci rcuit 1 is armed first after the arm bit is set. once a capture occurs, capture circ uit 1 is disarmed and capture ci rcuit 2 is armed. after capture circuit 2 performs a capture, it is disarmed and capture circui t 1 is re-armed. the process continues indefinitely. table 20-13. values for capture 2 mode control value meaning 00 disabled 01 capture falling edges 10 capture rising edges. 11 capture any edge. table 20-14. values for capture 1 mode control value meaning 00 disabled 01 capture falling edges 10 capture rising edges. 11 capture any edge.
enhanced motor control timer (etimer) 20-20 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 if only one of the capture circuits is enabled, th en captures continue indefinitely on the enabled capture circuit. arm - arm capture setting this bit high starts the input capture process. this bit can be cleared at any ti me to disable input capture operation. this bit is self cleared when in one shot mode and the enabled capture circuit(s) has had a capture event(s). 1 = input capture operation as specified by th e cpt1mode and cpt2mode bits is enabled. 0 = input capture operation is disabled. 20.4.3.16 input filter register (filt) figure 20-18. input filter register (filt) filt_cnt - input filter sample count these bits represent the number of consecutive sa mples that must agree prior to the input filter accepting an input transition. a value of 0 represents 3 samples. a value of 7 represents 10 samples. the value of filt_cnt affects the input latency as described in section 20.4.3.16.1, input filter considerations. filt_per - input filter sample period these bits represent the sampling period (in ipbus cloc k cycles) of the etimer in put signal. each input is sampled multiple times at the rate specified by filt_per. if fi lt_per is $00 (default), then the input filter is bypassed. the value of filt_p er affects the input latency as described in section 20.4.3.16.1, input filter considerations. 20.4.3.16.1 input fi lter considerations the filt_per value should be set such that the sampling period is la rger the period of the expected noise. this way a noise spike will only corrupt one sample . the filt_cnt value should be chosen to reduce the probability of noisy samples cau sing an incorrect transition to be recognized. the probability of an incorrect transition is defined as the probability of an incorrect sample raised to the filt_cnt + 3 power. the values of filt_per and filt_cnt must also be traded off against the desire for minimal latency in recognizing input transitions. turn ing on the input filter (setting filt_per to a non-zero value) introduces a latency of: (((filt_cnt + 3) x filt_per) + 2) ipbus clock periods. 20.4.4 watchdog timer registers the base address of the watchdog timer registers is equal to the base address of th e etimer plus an offset of $100. etimer_chnl _base + $1e 0 1 2 3 4 5 6 7 8 9 101112131415 read 0 0 0 0 0 filt_cnt[2:0] filt_per[7:0] write reset 0000 0 00000000000
enhanced motor control timer (etimer) freescale semiconductor 20-21 pxs20 microcontroller reference manual, rev. 1 20.4.4.1 watchdog time-out registers (wdtol and wdtoh) these registers are available only on etimer_0. figure 20-19. watchdog time-out low word register (wdtol) figure 20-20. watchdog time-out high word register (wdtoh) wdto - watchdog time-out these registers are combined to form the 32 bit time-out count for the timer watchdog function. this time-out count is used to monitor for inactivity on the inputs when channel 0 is in the quadrature decode count mode. the watchdog function is en abled whenever wdto co ntains a non-zero value (although actual counting only occurs if channel 0 is in quadrature decode counting mode). the watchdog time-out down counter is lo aded whenever wdtoh is writte n. these registers are not byte accessible. see section 20.5.3.5, watchdog timer, for more information on the use of the watchdog timer. 20.4.5 configuration registers the base address of the conf iguration registers is equal to the base address of the etimer plus an offset of $10c. 20.4.5.1 channel enable register (enbl) figure 20-21. channel enable register (enbl) enbl - timer channel enable these bits enable the prescaler (i f it is being used) and counter in each channel (enbl[x] controls channel number x). multiple enbl b its can be set at the same time to synchronize the start of separate channels. if an enbl bit is set, then the co rresponding channel will star t counting as soon as the cntmode field has a value other than 000. when an en bl bit is clear, th e corresponding channel maintains its current value. 1 = timer channel is enabled. (default) etimer_base + $100 0 1 2 3 4 5 6 7 8 9 101112131415 read wdtol write reset 0000 0 00000000000 etimer_base + $102 0 1 2 3 4 5 6 7 8 9 101112131415 read wdtoh write reset 0000 0 00000000000 etimer_base + $10c 0 1 2 3 4 5 6 7 8 9 101112131415 read 0 0 0 0 0 0 0 0 0 0 enbl write reset 0000 0 00000111111
enhanced motor control timer (etimer) 20-22 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 0 = timer channel is disabled. 20.4.5.2 dma request select registers (dreq0, dreq1) figure 20-22. dma request 0 select register (dreq0) figure 20-23. dma request 1 select register (dreq1) dreqn_en- dma request each of these fields enables dma request outputs. program the dreq fields prior to setting the corresponding enable bit. clearing this enable bit will remove the request but won?t clear the flag that is causing the request. 1 = dma request enabled. 0 = dma request disabled.. dreqn - dma request select each of these two fields is used to select the s ource of one of the etimer?s dma requests. enable a dma request in the channel specific intdma register and then use th ese registers to mux that request onto the module level dma request outputs. etimer_base + $110 0 1 2 3 4 5 6 7 8 9 101112131415 read dre q0_ en 0 0 0 0 0 0 0 0 0 0 dreq0[4:0] write reset 0000 0 00000000000 etimer_base + $112 0 1 2 3 4 5 6 7 8 9 101112131415 read dre q1_ en 0 0 0 0 0 0 0 0 0 0 dreq1[4:0] write reset 0000 0 00000000000 table 20-15. values for dreqn value selected dma request 00000 channel 0 capt1 dma read request 00001 channel 0 capt2 dma read request 00010 channel 0 cmpld1 dma write request 00011 channel 0 cmpld2 dma write request 00100 channel 1 capt1 dma read request 00101 channel 1 capt2 dma read request 00110 channel 1 cmpld1 dma write request 00111 channel 1 cmpld2 dma write request 01000 channel 2 capt1 dma read request 01001 channel 2 capt2 dma read request
enhanced motor control timer (etimer) freescale semiconductor 20-23 pxs20 microcontroller reference manual, rev. 1 20.5 functional description 20.5.1 general each channel has two basic modes of ope ration: it can count in ternal or external even ts, or it can count an internal clock source while an external input signal is asserted, thus timing the wi dth of the external input signal. ? the counter can count the rising, falling, or both edges of the selected input pin. ? the counter can decode and count quadrature encoded input signals. ? the counter can count up and down using dual inputs in a ?count with direction? format. ? the counter?s terminal count value (modulo) is programmable. ? the value that is loaded into the counter af ter reaching its terminal count is programmable. ? the counter can count repeatedly, or it can stop after completing one count cycle. ? the counter can be progr ammed to count to a programmed value and then immediately reinitialize, or it can count through the compare value until the count ?rolls over? to zero. the external inputs to each counter /timer are shareable among each of th e six channels within the module. the external inputs can be used as: ? count commands ? timer commands ? they can trigger the current counter value to be ?captured? 01010 channel 2 cmpld1 dma write request 01011 channel 2 cmpld2 dma write request 01100 channel 3 capt1 dma read request 01101 channel 3 capt2 dma read request 01110 channel 3 cmpld1 dma write request 01111 channel 3 cmpld2 dma write request 10000 channel 4 capt1 dma read request 10001 channel 4 capt2 dma read request 10010 channel 4 cmpld1 dma write request 10011 channel 4 cmpld2 dma write request 10100 channel 5 capt1 dma read request 10101 channel 5 capt2 dma read request 10110 channel 5 cmpld1 dma write request 10111 channel 5 cmpld2 dma write request 11000?11111 reserved table 20-15. values for dreqn (continued) value selected dma request
enhanced motor control timer (etimer) 20-24 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? they can be used to ge nerate interrupt requests the polarity of the external inputs is selectable. the primary output of each channel is the output signal oflag. the oflag output signal can be: ? set, cleared, or toggled when the counter reaches the programmed value. ? the oflag output signal may be output to an extern al pin instead of having that pin serve as a timer input. ? the oflag output signal enables each counter to generate square waves, pwm, or pulse stream outputs. ? the polarity of the oflag output signal is programmable. ? the response of the oflag output to a fault input is programmable. any channel can be assigned as a ?master?. a master ?s compare signal can be broadcasted to the other channels within the module. the othe r channels can be configured to re initialize their counters and/or force their oflag output signals to predetermined values when a master channel?s compare event occurs. 20.5.2 counting modes the selected external signals are sa mpled at the etimer?s base clock ra te and then run through a transition detector. the maximum count rate is one-half of the etimer?s base clock rate when using an external signal. internal clock sources can be used to cl ock the counters at the etimer?s base clock rate. if a counter is programmed to count to a specific value and then stop, the cntmode field in the ctrl1 register is cleared when the count terminates. 20.5.2.1 stop mode if the cntmode field is set to ?000?, the counter is inert. no counting will occur. stop mode will also disable the interrupts caused by input transitions on a selected input pin. 20.5.2.2 count mode if the cntmode field is set to ?001? , the counter will count the rising e dges of the selected clock source. this mode is useful for generating periodic interrupts for tim ing purposes, or counting external events such as ?widgets? on a conveyor belt passi ng a sensor. if the selected input is inverted by setting the pips bit, then the negative edge of the select ed external input signal is counted. see section 20.5.2.9, cascade-count mode, through section 20.5.2.12, variable-frequency pwm mode, for additional capabilities of this operating mode. 20.5.2.3 edge-count mode if the cntmode field is set to ?010?, the counter wi ll count both edges of the selected external clock source. this mode is useful for counting the changes in the extern al environment such as a simple encoder wheel.
enhanced motor control timer (etimer) freescale semiconductor 20-25 pxs20 microcontroller reference manual, rev. 1 20.5.2.4 gated-count mode if the cntmode field is set to ?011 ?, the counter will count while the selected s econdary input signal is high. this mode is used to time the duration of external events. if the selected input is invert ed by setting the pips bit, then the counter will count while the selected secondary input is low. note in the following counting modes an incorrect counti ng of 1 tick is possible: - gated-count mode, th e cntmode field is '0 11' (count rising edges of primary source while se condary input is high); -signed-count mode, the cntmode field is '101' (count primary source rising edges, secondary sour ce specifies dire ction (up/down)). delays in the edge detection circuitry lead to behavior where the rising edge on the primary source is compared to the secondary source value one clock later in time. this means that if ther e is a rising edge on the primary source followed immediately by the secondary source going high, the etimer logic could see this as a rising primary e dge while the secondary is high even though the secondary input was low at th e time of the rising primary edge. this behavior can occur when the tr ansition on the secondary edge occurs within 1 ipbus clock cycle of the transition on the primary input. the counter will also increment if the pr imary source is already high when the secondary source goes high. to prevent this problem the source se lected as the secondary input to the etimer channel needs to ha ve an additional clock cycl e of delay added to it. this can be done by using the input filters. for the primary source set filt_per==1 and filt_cnt==0. for the secondary source set filt_per==1 and filt_cnt==1. this will introduce a 5 clock cycle latency on the primary source and a 6 cy cle latency on the secondary source which will properly align the two signa ls for count modes '011' and '101'. to prevent this problem ensure that the primary source is low before the secondary source goes high to avoid a false count. 20.5.2.5 quadrature-count mode if the cntmode field is set to ?100?, the counter wi ll decode the primary and secondary external inputs as quadrature encoded signals . quadrature signals are usually genera ted by rotary or linear sensors used to monitor movement of motor shafts or mechanical equipment. the quadrature signals are square waves that are 90 degrees out of phase. the decoding of quadrature signal provides both count and direction information. figure 20-24 shows a timing diagram illustrating the basic op eration of a quadratur e incremental position encoder.
enhanced motor control timer (etimer) 20-26 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 20-24. quadrature incremental position encoder 20.5.2.6 signed-count mode if the cntmode field is set to ?101?, the counter counts the primary clock s ource while the selected secondary source provides the sele cted count direction (up/down). 20.5.2.7 triggered-count mode if the cntmode field is set to ?1 10?, the counter will begin counting the primary clock source after a positive transition (negative if sips = 1) of the secondary input occu rs. the counting will continue until a compare event occurs or another positive input tran sition is detected. subsequent secondary positive input transitions will continue to restart and stop the counting until a compare event occurs. figure 20-25. triggered count mode (length=1) 20.5.2.8 one-shot mode if the cntmode field is set to ?110?, and the counter is set to reinitialize at a compare event (length =1), and the oflag outmode is set to ?0101? (clear ed on init, set on compare), the counter works in a ?one-shot mode?. an external ev ents causes the counter to count, wh en terminal count is reached, the output is asserted. this ?delayed? output can be used to provide timing delays. figure 20-26. one-shot mode (length=1) +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 -1 phaseb count up/dn phasea 12 13 14 15 16 comp1 = 18 17 18 primary secondary cntr oflag 01234 load = 0, comp1 = 4 01 primary secondary cntr oflag
enhanced motor control timer (etimer) freescale semiconductor 20-27 pxs20 microcontroller reference manual, rev. 1 20.5.2.9 cascade-count mode if the cntmode field is set to ?111?, the counter?s input is connected to the output of another selected counter. the counter will c ount up and down as compare ev ents occur in the selected source counter. this ?cascade? or ?daisy-chain ed? mode enables multiple counters to be cascaded to yield longer counter lengths. when operating in cascade mode, a special high speed signal path is used between modules rather than the oflag output signal. if th e selected source count er is counting up and it experiences a compare event, the counter will be incremen ted. if the selected source counter is counting down and it experiences a compare event, the count er will be decremented. up to two counters may be cascaded to create a 32 bit wide synchronous counter. whenever any counter is read within a counter module, all of the count ers? values within the module are captured in their respective hold re gisters. this action supports the reading of a cascaded counter chain. first read any counter of a cascaded counter chain, then read the hold registers of the other counters in the chain. the cascaded counter mode is synchronous. note it is possible to connect counters toge ther by using the other (non-cascade) counter modes and selecting the outputs of other counters as a clock source. in this case, the counters are opera ting in a ?ripple? mode, where higher order counters will transition a cloc k later than a purely synchronous design. note a channel can be cascaded with any other channel, but you can?t cascade more than 2 channels together. you can create separate casc ades of pairs of channels. for example, you can cascade channels 0 and 1 and separately cascade channels 6 and 5. you can?t cascade channels 0, 1, and 5. 20.5.2.10 pulse-output mode if the counter is setup for cntmode = 001, and the oflag outmode is set to ?1111? (gated clock output), and the once bit is set, then the counter will output a pulse stream of pulses that has the same frequency of the selected clock s ource, and the number of output pulses is equal to the compare value minus the init value. this mode is useful for driving step motor systems. note this does not work if the prisrc is set to 11000 (ip_bus/1). figure 20-27. pulse output mode pulse stream init 0 1 0 1 2 3 4 0 load = 0, comp1 = 4 cntmode primary cntr oflag
enhanced motor control timer (etimer) 20-28 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 20.5.2.11 fixed-frequency pwm mode if the counter is setup for cntmode = 001, count through roll-over (length = 0), continuous count (once = 0) and the oflag outmode is ?0111? (set on compare, cleared on counter ro ll-over) then the counter output yields a pulse widt h modulated (pwm) signal with a fr equency equal to the count clock frequency divided by 65,536 and a pulse width duty cy cle equal to the compare value divided by 65,536. this mode of operation is often used to drive pw m amplifiers used to po wer motors and inverters. 20.5.2.12 variable-frequency pwm mode if the counter is setup for cntmode = 001, count til l compare (length = 1), continuous count (once = 0) and the oflag outmmode is ?0100? (toggle of lag and alternate compare registers) then the counter output yields a pulse wi dth modulated (pwm) signal whose frequency and pulse width is determined by the values program med into the comp1 and comp2 registers, and the input clock frequency. this method of pwm generation has the advantage of allowing almost any desired pwm frequency and/or constant on or off periods. this mode of operation is often used to drive pwm amplifiers used to power motors and inverters. the cmpld1 and cmpld2 register s are especially useful for this mode, as they allow the programmer time to calculate values for the next pwm cycle while the pwm current cycle is underway. figure 20-28. variable pwm waveform figure 20-29. variable frequency pwm mode timing comp1 comp2 pwm period 2 3 0 1 clock cntr oflag 2 0 0 1 1 2 1 0 comp1 comp2 cmpld1 cmpld2 1 4 comp1 match comp2 match ignored since oflag=1 ignored since oflag=1 ignored since oflag=0 clc1=010, load comp1 when cntr=comp1 clc2=101, load comp2 when cntr=comp2 3 1 2 4 1
enhanced motor control timer (etimer) freescale semiconductor 20-29 pxs20 microcontroller reference manual, rev. 1 20.5.2.13 usage of compare registers the dual compare registers (comp1 and comp2) provide a bidirectional modulo count capability. the comp1 register should be set to the desired maximum count value or $ffff to indicate the maximum unsigned value prior to roll-over, and the comp2 regi ster should be set to the minimum count value or $0000 to indicate the minimum unsi gned value prior to roll-under. if the output mode is set to 0100, the oflag will toggle while using al ternating compare registers. in this variable frequency pwm m ode, the comp2 value defines the desire d pulse width of the on time, and the comp1 register defines the off time. comp1 is used when oflag=0 and comp2 is used when oflag=1. oflag can be forced to a va lue using ctrl2[force] and ctrl2[val]. use caution when changing comp1 and comp2 while the counter is active. if the counter has already passed the new value, it will count to $ffff or $0000, roll over, then begi n counting toward the new value. the check is: cntr = compx, not cntr > comp1 or cntr < comp2. the use of the cmpld1 and cmpld2 registers to prel oad compare values will help to minimize this problem. figure 20-30. compare register and oflag timing 20.5.2.14 usage of compare load registers the cmpld1, cmpld2 and ccctrl registers offer a high degree of flexibility for loading compare registers with user-defined values on different compare events. to ensu re correct functionality while using these registers we strongly suggest using the following method described in this section. the purpose of the compare load featur e is to allow quicker updating of the compare registers. a compare register can be updated using interrupts. however, because of the latency be tween an interrupt event occurring and the service of that interrupt, there is the possibility that the counter may have already counted past the new compare value by the time the compare register is updated by the interrupt service routine. the counter woul d then continue counting unt il it rolled over and reached the new compare value. 2 3 4 5 clock cntr oflag 6 1 0 comp1 comp2 comp1 match comp2 match unsuccessful 3 2 cmpmode 10, use com1 when counting up, use comp2 when counting down compare since cmpmode[0]=0 successful compare since cmpmode[1]=1 outmode 0010, set oflag on successful compare
enhanced motor control timer (etimer) 20-30 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 to address this, the compare registers are updated in hardware in the same way the counter register is re-initialized to the value stored in the load register. the compare load feature allows the user to calculate new compare values and store them in to the comparator load registers. wh en a compare event occurs, the new compare values in the comparator lo ad registers are written to the compare registers eliminating the use of software to do this. the compare load feature is intended to be used in variable frequency pwm m ode. the comp1 register determines the pulse width for the logic low part of ofla g and comp2 determines the pulse width for the logic high part of oflag. the period of th e waveform is determined by the comp1 and comp2 values and the frequency of the primary clock source. see figure 20-28 . 20.5.2.15 modulo counting mode to create a modulo counter using comp1 and comp2 as the counter boundaries (instead of $0000 and $ffff), set the registers in the following manner. set cntmode to either 100 (quadrature count mode) or 101 (count with direction mode). use count through roll-over (l ength = 0) and continuous count (once = 0). set comp1 and cmpl d1 to the upper boundary value. set comp2 and cmpld2 to the lower boundary value. set cmpmode = 10 (comp1 is used when counting up a nd comp2 is used when counting down). set clc2 = 110 (load cntr with value of cmpld2 on comp1 compare) and clc1 = 111 (load cntr with value of cmpld1 on comp2 compare). 20.5.3 other features 20.5.3.1 redundant oflag checking this mode allows the user to bundl e two timer functions ge nerating any pattern to compare their resulting oflag behaviors (output signal). the redundant mode is used to support online checks fo r functional safety reasons . whenever a mismatch between the two adjacent channels o ccurs, it is reported via an interrupt to the core and the two outputs are put into their inactive states. an error is flagged via the rcf flag. this feature can be tested by fo rcing a transition on one of the of lags using the val and force bits of the channel. 20.5.3.2 loopback checking this mode is always available in that one channel can generate an of lag while another channel uses the first channels oflag as its input to be m easured and verified to be as expected. 20.5.3.3 input capture mode input capture is used to measur e pulse width (by capturing the c ounter value on two successive input edges) or waveform period (by ca pturing the counter value on two consecutive rising edges or two consecutive falling edges). the capt ure registers store a copy of the c ounter?s value when an input edge (positive, negative, or both) is detected. the type of edge to be captured by each circuit is determined by the cpt1mode and cpt2mode bits w hose functionality is listed in table 20-14 . also, controlling the
enhanced motor control timer (etimer) freescale semiconductor 20-31 pxs20 microcontroller reference manual, rev. 1 operation of the capture circu its is the arming logic which allows capt ures to be performed in a free running (continuous) or one shot fashion. in free running mode, the capture sequences will be performed indefinitely. if both capture circ uits are enabled, they will work t ogether in a ping-pong style where a capture event from one circuit leads to the arming of the other and vice ve rsa. in one shot mode, only one capture sequence will be performed. if both capture circuits are enable d, capture circuit 0 is first armed and when a capture event occurs, capture circuit 1 is armed. once the second capture occurs, further captures are disabled until another ca pture sequence is initiated. both ca pture circuits are also capable of generating an interrupt to the cpu. 20.5.3.4 master/slave mode any timer channel can be assigned as a master (mstr = 1). a master?s compare signal can be broadcasted to the other channels wi thin the module. the other counters can be configured to reinitialize their counters (coinit = 1) and/or force their of lag output signals (cofrc = 1) to predetermined values when a master count er compare event occurs. 20.5.3.5 watchdog timer the watchdog timer is used to monitor for a stalled c ount when channel 0 is in quadrature count mode. when the watchdog is enabled, it loads the time-out value into a down counter. the down counter counts as long as channel 0 is in quadrature decode count m ode. if this down counter reaches zero, an interrupt is asserted. the down counter is re loaded to the time-out value each time the c ounter value from channel 0 changes. if the channel 0 count value is toggl ing between two values (i ndicating a possibly stalled encoder), then the down counter is not reloaded. 20.6 interrupts each of the channels within the et imer can generate an interrupt fr om several sources. the watchdog and the fault logic also generate interrupts. the interrupt service routine (isr) must check the related interrupt enables and interrupt flags to determ ine the actual cause of the interrupt.
enhanced motor control timer (etimer) 20-32 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 20.7 dma each channel can request a dma read access for each of the capture registers and a dma write request for each of the compare preload registers. the dreq registers select amongst these 24 dma request sources to generate the 2 to p level dma request outputs. table 20-17. dma summary table 20-16. interrupt summary core interrupt interrupt flag interrupt enable name description tc0ir? tc5ir 1 notes: 1 all flags are ored together to generate the interrupt tc n ir. tcf tcfie compare interrupt compare of counter and related compare register tcf1 tcf1ie compare 1 interrupt compare of the counter and comp1 register tcf2 tcf2ie compare 2 interrupt compare of the counter and comp2 register tof tofie overflow interrupt generated on counter roll-over or roll-under ielf ielfie input low edge interrupt fa lling edge of the secondary input signal iehf iehfie input high edge interrupt rising edge of the secondary input signal icf1 icf1ie input capture 1 interr upt input capture event for capt1 icf2 icf2ie input capture 2 interr upt input capture event for capt2 wtif 2 2 only for etimer_0. wdf wdfie watchdog time-out interrupt watchdog has timed out rcf rcf rcfie redundant channel fault interrupt miscompare with redundant channel dma request dma enable name description channels 0-5 icf1de capt1 read request capt1 contains a value icf2de capt2 read request capt2 contains a value cmpld1de cmpld1 write request cmpld1 needs an update cmpld2de cmpld2 write request cmpld2 needs an update
error correction status module (ecsm) freescale semiconductor 21-1 pxs20 microcontroller reference manual, rev. 1 chapter 21 error correction status module (ecsm) 21.1 introduction the error correction status module (ecsm) provides miscellaneous c ontrol functions for the device standard product platform (spp) incl uding program-visible information about the platform configuration and revision levels, a re set status register, and wakeup control for exiting sleep modes, and optional features such as informat ion on memory errors reporte d by error-correcting codes. 21.2 overview the error correction status module is mapped into the ips space and s upports a number of miscellaneous control functions for the platform device. 21.3 features the ecsm includes these features: ? program-visible informati on on the platform device configuration and revision ? reset status register (mrsr) ? registers for capturing informat ion on platform memory errors if error-correcting codes (ecc) are implemented ? registers to specify the generation of single- and double-bit memory data inversions for test purposes if error-correcti ng codes are implemented 21.4 memory map and register description this section details the pr ogramming model for the error correction status module. this is an on-platform 128-byte space mapped to the region servic ed by an ips bus controller. some of the control registers have a 64-bit width. these 64-bit registers are implemented as two 32-bit registers, and include an ?h? and ?l? suffixes, indicating the ?high? and ?l ow? portions of th e control function. the error correction status module does not include a ny logic which provides acces s control. rather, this function is supported using the standard access control logic pr ovided by the ips controller. 21.4.1 memory map table 21-1 is a 32-bit view of the ecsm?s memory map. the addresses presented here are the offsets relative to the controller base address 0xfff4_0000. in dpm, ecsm_1 is located at base address 0x8ff4_0000. table 21-1. ecsm memory map ecsm offset register 0x0000 processor core type (pct) chip-defined platform revision (plrev)
error correction status module (ecsm) 21-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 21.4.2 register description attempted accesses to reserved addresses result in an error termination, while attempted writes to read-only registers are ignored and do not terminate with an error. unless noted otherwise, writes to the programming model must match the size of the register , e.g., an n -bit register only supports n -bit writes, etc. attempted writes of a different size than the re gister width produce an erro r termination of the bus cycle and no change to the targeted register. 0x0004 platform crossbar master configuration (pla mc) platform crossbar slave configuration (plasc) 0x0008 ips on-platform module configuration (iopmc) 0x000c reserved misc reset status (mrsr) 0x0010? 0x0023 reserved 0x0024 miscellaneous user-defined control register (mudcr) 0x0028 reserved 0x002c - 0x003c reserved 0x0040 reserved ecc configuration (ecr) 0x0044 reserved ecc status (esr) 0x0048 reserved ecc error generation (eegr) 0x004c reserved 0x0050 platform flash memory ecc address (pfear) 0x0054 reserved platform flash memory ecc master (pfemr) platform flash memory ecc attributes (pfeat) 0x0058 platform flash memory ecc data high (pfedrh) 0x005c platform flash memory ecc data low (pfedrl) 0x0060 platform ram ecc address (prear) 0x0064 reserved platform ram ecc syndrome (presr) platform ram ecc master (premr) platform ram ecc attributes (preat) 0x0068 platform ram ecc data high (predrh) 0x006c platform ram ecc data low (predrl) 0x0070 - 0x007c reserved table 21-1. ecsm memory map (continued) ecsm offset register
error correction status module (ecsm) freescale semiconductor 21-3 pxs20 microcontroller reference manual, rev. 1 21.4.2.1 processor core type (pct) register the pct is a 16-bit read-onl y register specifying the architecture of the processor core in the device. the state of this register is define d by a module input signal; it can onl y be read from the ips programming model. any attempted write is ignored. see figure 21-1 and table 21-2 for the processor core type definition. 21.4.2.2 chip-defined platfo rm revision (rev) register the rev is a 16-bit read-only register specifying a revision number. the st ate of this register is defined by an input signal; it can only be r ead from the ips programming model. any attempted wr ite is ignored. see figure 21-2 and table 21-3 for the rev definition. register address: ecsm base + 0x0000 0123456789101112131415 rpct w reset:1110010001000110 = unimplemented figure 21-1. processor core type (pct) register table 21-2. processor core type (pct) field descriptions name description pct processor core type 0xe446: e200z4d power architecture core register address: ecsm base + 0x0002 0123456789101112131415 rplrev w reset:0000000000000000 = unimplemented figure 21-2. chip-defined platform revision (rev) register table 21-3. rev field descriptions field description plrev revision this field is specified by an input signal to define a software-visible revision number.
error correction status module (ecsm) 21-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 21.4.2.3 platform crossbar master configuration (plamc) the plamc is a 16-bit read-only regi ster identifying the presence/absen ce of bus master connections to the platform?s xbar. the state of this register is defined by a module input signal; it can only be read from the ips programming model. any attempted write is ignored. see figure 21-3 and table 21-4 for the plamc definition. 21.4.2.4 platform crossbar slave configuration (plasc) the plasc is a 16-bit read-only regist er identifying the presence/absence of bus slave connections to the platform?s xbar, plus a 1-bi t flag defining the internal platform datapath width. th e state of this register is defined by a module input signal; it can only be read fr om the ips programming model. any attempted write is ignored. see figure 21-4 and table 21-5 for the plasc definition. register address: ecsm base + 0x0004 0123456789101112131415 r 00000000 amc w reset:0000000001101111 = unimplemented figure 21-3. platform crossbar master configuration (plamc) table 21-4. plamc field descriptions field description amc[n] xbar master configuration 0 bus master to xbar input port n is absent 1 bus master to xbar input port n is present register address: ecsm base + 0x0006 0123456789101112131415 rdp640000000 asc w reset:1000000010000101 = unimplemented figure 21-4. platform crossbar slave configuration (plasc)
error correction status module (ecsm) freescale semiconductor 21-5 pxs20 microcontroller reference manual, rev. 1 21.4.2.5 ips on-platform module configuration (iopmc) register the iopmc is a 32-bit read-only register identifyi ng the presence or absence of the 32 low-order ips peripheral modules connected to the pr imary slave bus controller. the state of this register is defined by a module input signal; it can only be r ead from the ips programming model. any attempted write is ignored. see figure 21-5 and table 21-6 for the iopmc definition. 21.4.2.6 miscellaneous reset status register (mrsr) the mrsr contains a bit for each of the reset sources to the device. an asserted bit indica tes the last type of reset that occurred. only one bit is set at any time in the mrsr , reflecting the cause of the most recent reset as signalled by device rese t input signals. the mrsr can only be read from the ips programming model. any attempted write is ignored. table 21-5. plasc field descriptions field description dp64 64-bit datapath 0 platform datapath width is 32 bits 1 platform datapath width is 64 bits asc[n] xbar slave configuration 0 bus slave to xbar input port n is absent 1 bus slave to xbar input port n is present register address: ecsm base + 0x0008 0123456789101112131415 r pmc[31:16] w reset:1100100001000011 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pmc[15:0] w reset:1110000000000000 = unimplemented figure 21-5. ips on-platform module configuration (iopmc) register table 21-6. iopmc field descriptions field description pmc ips module configuration pmc[n] = 0 if an ips module connect ion to decoded slot ?n? is absent pmc[n] = 1 if an ips module connectio n to decoded slot ?n? is present
error correction status module (ecsm) 21-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 see figure 21-6 and table 21-7 for the miscellaneous reset status register definition. 21.4.2.7 miscellaneous user-defined control register (mudcr) the mudcr provides a program-v isible register for user-defined contro l functions. it typi cally is used as configuration control for miscellaneous soc-level modules. the contents of this register is simply output from ecsm to other modules where the user-d efined control functions are implemented. see figure 21-7 and table 21-8 for the miscellaneous user-defin ed control register definition. register address: ecsm base + 0x000f 01234567 rporofplr000000 w reset: * * 0 00000 = unimplemented figure 21-6. miscellaneous reset status (mrsr) register table 21-7. mrsr field descriptions field description por power-on reset 1 = last recorded event was caused by a power-on reset (based on a device input signal) ofplr off-platform reset 1 = last recorded event was a reset caused by an off-platform reset. register address: ecsm base + 0x0024 0123456789101112131415 r 0 mudc r 00000000000000 w reset: 0100000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000000000000 w reset: 0000000000000000 = unimplemented figure 21-7. miscellaneous user-d efined control (mudcr) register
error correction status module (ecsm) freescale semiconductor 21-7 pxs20 microcontroller reference manual, rev. 1 note in dpm, the chip has an additional ec sm (ecsm_1) that also contains a mudcr. applications changing this c onfiguration should take this fact into account. 21.4.2.8 platform ecc registers there are a number of program-visi ble registers for the sole purpose of reporting and logging of memory failures. these registers include the following: ? ecc configurati on register (ecr) ? ecc status register (esr) ? ecc error generation register (eegr) ? platform flash memory ecc address register (pfear) ? platform flash memory ecc mast er number register (pfemr) ? platform flash memory ecc at tributes register (pfeat) ? platform flash memory ecc data registers (pfedrl and pfedrh) ? platform ram ecc address register (prear) ? platform ram ecc syndr ome register (presr) ? platform ram ecc master number register (premr) ? platform ram ecc attributes register (preat) ? platform ram ecc data registers (predrl and predrh) the details on the ecc registers are provided in the subsequent sections. the 32-bit ecc organization essen tially provides two completely inde pendent error checking mechanisms for the total 64-bit pram width. the ecc logic provide s a 1-of-3 error response vector for each 32 bits of memory: no error, single-bit correctable error, multi-bit non-correctable error. table 21-9 defines the association between the reported ecc re sult and the pram bank chip selects. table 21-8. mudcr field descriptions field description mudcr platform ram wait-state control this bit is used to select whether the platform ram controller will insert 1-wait state into every read access made to the platform ram arrays. 0 the platform ram controller operates as a 0-wait state controller 1 the platform ram controller operates as a 1-wait state controller
error correction status module (ecsm) 21-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 as shown in table 21-9 , accesses of only a single memory bank re port the ecc from that bank directly. for accesses involving both banks, the "m ost severe" ecc response is repor ted with the even bank taking priority if the responses are equivalent. this a pproach also provides impr oved correction capabilities compared to the 64-bi t ecc implementation. 21.4.2.9 ecc configuration register (ecr) the ecc configuration register is an 8-bit control register for specifying which t ypes of memory errors are reported. in all systems with ecc, the occurrence of a non-correctable error causes the current access to be terminated with an error condition. in many cases , this error termination is reported directly by the initiating bus master. however, there are certain si tuations where the occurrence of this type of non-correctable error is not reported by the master. examples include speculative instruction fetches which are discarded due to a change-of-f low operation, and buffered operand wr ites. the ecc reporting logic in the ecsm provides an optional error interrupt mechanism to signal all non-correctable memory errors. in addition to the interrupt generation, the ecsm captures specific inform ation (memory address, attributes and data, bus master number, etc.) which may be useful for subsequent failure analysis. see figure 21-8 and table 21-10 for the ecc configura tion register definition. table 21-9. ahb response and ecc reporting for even and odd ecc pram valid ecc reported ecc pram bus response ahb hresp even odd even odd even odd 0 0 x x no access, no_error xxxx xxxx okay 1 0 none x no_error data xxxx okay 1 0 single x even_single corrected xxxx okay 1 0 multi x even_multi n on-corrected xxxx err 0 1 x none no_error xxxx data okay 0 1 x single odd_single xxxx corrected okay 0 1 x multi odd_multi xxxx non-corrected err 1 1 none none no_error data data okay 1 1 single none even_single corrected data okay 1 1 multi none even_multi non-corrected data err 1 1 none single odd_single data corrected okay 1 1 single single even_single corrected corrected okay 1 1 multi single even_multi non-corrected corrected err 1 1 none multi odd_multi data non-corrected err 1 1 single multi odd_multi corrected non-corrected err 1 1 multi multi even_multi non-corrected non-corrected err
error correction status module (ecsm) freescale semiconductor 21-9 pxs20 microcontroller reference manual, rev. 1 21.4.2.10 ecc status register (esr) the ecc status register is an 8-bit control regist er for signaling which types of properly-enabled ecc events have been detected. the es r signals the last, prope rly-enabled memory event to be detected. ecc interrupt generation is separated in to single-bit error detection/correc tion, uncorrectable error detection and the combination of the two as de fined by the following boolean equations: ecsm_ecc1bit_irq register address: ecsm base + 0x0043 01234567 r0 0 epr1br epf1br 00 eprncr epfncr w reset:00000000 = unimplemented figure 21-8. ecc configuration (ecr) register table 21-10. ecr field descriptions field description epr1br enable platform ram 1-bit reporting 0 = reporting of single-bit platform ram corrections is disabled. 1 = reporting of single-bit platform ram corrections is enabled. this bit can only be set if the soc-configurable input enable signal is asserted. the occurrence of a single-bit platform ram correction generates a non-critical fault as signalled by the assertion of esr[r1bc]. the address, attributes and data are also captured in the prear, presr, premr, preat, predrl, and predrh registers. epf1br enable platform flash memory 1-bit reporting 0 = reporting of single-bit platform flash memory corrections is disabled. 1 = reporting of single-bit platform flash memory corrections is enabled. this bit can only be set if the soc-configurable input enable signal is asserted. the occurrence of a single-bit platform flash memory correction generates a non-critical fault as signalled by the assertion of esr[f1bc]. the address, attributes and data are also captured in the pfear, pfemr, pfeat, pfedrl, and pfedrh registers. eprncr enable platform ram no n-correctable reporting 0 = reporting of non-correctable platform ram errors is disabled. 1 = reporting of non-correctable platform ram errors is enabled. the occurrence of a non-correctable multi-bit platform ram error generates a critical fault as signalled by the assertion of esr[rnce]. the faulting addr ess, attributes and data are also captured in the prear, presr, premr, preat, predrl, and predrh registers. epfncr enable platform flash memory non-correctable reporting 0 = reporting of non-correctable platform flash memory errors is disabled. 1 = reporting of non-correctable platform flash memory errors is enabled. the occurrence of a non-correctable multi-bit platform flash memory error generates a critical fault as signalled by the assertion of esr[fnce]. the faulting address, attributes and data are also captured in the pfear, pfemr, pfeat, pf edrl, and pfedrh registers.
error correction status module (ecsm) 21-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 = ecr[er1br] & esr[r1bc] // ram, 1-bit correction | ecr[ef1br] & esr[f1bc] // platform flash memory , 1-bit correction ecsm_eccrncr_irq = ecr[erncr] & esr[rnce] // ram, noncorrectable error ecsm_eccfncr_irq = ecr[efncr] & esr[fnce] // platform flash memory , noncorrectable error ecsm_ecc2bit_irq = ecsm_eccrncr_irq // ram, noncorrectable error | ecsm_eccfncr_irq // platform flash memory , noncorrectable error ecsm_ecc_irq = ecsm_ecc1bit_irq // 1-bit correction | ecsm_ecc2bit_irq // noncorrectable error where the combination of a correct ly-enabled category in the ecr a nd the detection of the corresponding condition in the esr produces the interrupt request. the ecsm allows a maximum of one b it of the esr to be asserted at any given time. this preserves the association between the esr and the corresponding addr ess and attribute registers, which are loaded on each occurrence of an properly-enabled ecc event. if there is a pending ecc interrupt and another properly-enabled ecc event occurs, the ecsm ha rdware automatically handles the esr reporting, clearing the previous data and loading the new state and thus gua ranteeing that only a single flag is asserted. to maintain the coherent software view of the reported event and ensure a correct handling in case of an ecc error, the following sequence in the ecsm error interrupt service routine is suggested: 1. 1. read the esr and save its content. 2. check what error(s) are flagged. 3. depending on the originator (ram or flash memo ry) read and save all the address and attribute reporting registers to this originator: ? platform ram error: prear, presr, premr, preat, predrl, predrh ? platform flash error: pfear, pfemr, pfeat, pfedrl, pfedrh 4. re-read the esr and verify the current contents matches the original contents. if the two values are different, go back to step 1 and repeat. 5. when the values are identical, write a 1 to the a sserted esr flag to negate the interrupt request. it is not recommended to read any of the following registers outside the ecsm error interrupt service routine (that is, without a previous ecc error event): ? pfear, pfemr, pfeat, pfedrl, pfedrh ? prear, presr, premr, preat, predrl, predrh if no flash memory ecc event is de fined to be handled for this modul e, accesses to the registers pfear, pfemr, pfeat, pfedrl, and pfedrh will terminate with an error. if no ram ecc event is defined to be handled for this module, accesses to the registers prear, presr, premr, preat, predrl, and predrh will terminate with an error. see figure 21-9 and table 21-11 for the ecc status register definition.
error correction status module (ecsm) freescale semiconductor 21-11 pxs20 microcontroller reference manual, rev. 1 in the event that multiple status flags are signale d simultaneously, ecsm records the event with the pr1bc as highest priority, then pf1 bc, then prnce, and finally pfnce. register address: ecsm base + 0x0047 01234567 r 0 0 pr1bc pf1bc 0 0 prnce pfnce w reset:00000000 = unimplemented figure 21-9. ecc status (esr) register table 21-11. esr field descriptions name description ppr1bc platform ram 1-bit correction 0 = no reportable single-bit platform ram correction has been detected. 1 = a reportable single-bit platfo rm ram correction has been detected. this bit can only be set if ecr[epr1br] is asserted. the occurrence of a properly-enabled single-bit platform ram correction generates a ecsm ecc interrupt request. the address, attributes and data are also captured in the prear, presr, premr, preat, predrl, and predrh registers. to clear this interrupt flag, write a 1 to this bit. writing a 0 has no effect. pf1bc platform flash memory 1-bit correction 0 = no reportable single-bit platform flash memory correction has been detected. 1 = a reportable single-bit platform flash memory correction has been detected. this bit can only be set if ecr[epf1br] is assert ed. the occurrence of a properly-enabled single-bit platform flash memory correction generates a ecsm ecc interrupt request. the address, attributes and data are also captured in the pfear, pfemr, pfeat, pfedrl, and pfedrh registers. to clear this interrupt flag, write a 1 to this bit. writing a 0 has no effect. prnce platform ram non-correctable error 0 = no reportable non-correctable platform ram error has been detected. 1 = a reportable non-correctable pl atform ram error has been detected. the occurrence of a properly-enabled non-correctab le platform ram error generates a ecsm ecc interrupt request. the faulting address, attributes and data are also captured in the prear, presr, premr, preat, predrl, and predrh registers. to clear this interrupt flag, write a 1 to this bit. writing a 0 has no effect. pfnce platform flash memory non-correctable error 0 = no reportable non-correctable platform flash memory error has been detected. 1 = a reportable non-correctable platform flash memory error has been detected. the occurrence of a properly-enabled non-correctable platform flash memory error generates a ecsm ecc interrupt request. the faulting address, attr ibutes and data are also captured in the pfear, pfemr, pfeat, pfedrl, and pfedrh registers. to clear this interrupt flag, write a 1 to this bit. writing a 0 has no effect.
error correction status module (ecsm) 21-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 21.4.2.11 ecc error gene ration register (eegr) the ecc error generation register is a 16-bit control register used to force the generati on of single- and double-bit data inversions in the memo ries with ecc, most notably the platform ram. this capability is provided for two purposes: ? it provides a software-controlled mechanism for ?injecting? errors into the memories during data writes to verify the integrity of the ecc logic. ? it provides a mechanism to allow testing of the so ftware service routines associated with memory error logging. platform flash memory includes an ecc logic check to verify the integrity of its ecc logic (see section 23.1.5.12, ecc logic check ). for platform ram, the intent is to generate errors during da ta write cycles, such th at subsequent reads of the corrupted address locations generate ecc events, either si ngle-bit corrections or double-bit non-correctable errors th at are terminated with an error response. the enabling of these error generation modes requires the same soc-configurable input enable signal (as that used to enable single-bit correction reporting) be asserted. see figure 21-10 and table 21-12 for the ecc configura tion register definition. register address: ecsm base + 0x004a 0123456789101112131415 r frca p 0frc1 bi fr11 bi 00frcn ci fr1 nci 0errbit[0:6] w reset: 0000000000000000 = unimplemented figure 21-10. ecc error ge neration (eegr) register table 21-12. ecc error generation (eegr) field descriptions name description frcap force platform ram erro r injection access protection 0 = all masters are able to generate platform ram ecc errors via the eegr register. 1 = only the master defined with as having hmaste r=0 (usually the core) can generate platform ram ecc errors via the eegr register. the assertion of this bit ensures that platform ra m data inversions can only occur from the master module with the master id of 0. since this is us ually the core, this protects the platform ram from errant or multiple simultaneous attempted data invers ions from other master modules and, in the case of a multi-core system, ensures that only one core can issue a platform ram data inversion. the reset value of the bit is 0 and as a result, platform ram data inversions can be requested from any master module. it is the responsibility of the so ftware to ensure the proper setting of this bit.
error correction status module (ecsm) freescale semiconductor 21-13 pxs20 microcontroller reference manual, rev. 1 frc1bi force platform ram continuo us 1-bit data inversions 0 = no platform ram continuous 1-bit data inversions are generated. 1 = 1-bit data inversions in the platform ram are continuously generated. the assertion of this bit forces the platform ram controller to create 1-bit data inversions, as defined by the bit position specified in errbit[0:6 ], continuously on every write operation. the normal ecc generation takes place in the platform ram controller, but then the polarity of the bit position defined by errbit is inverted to in troduce a 1-bit ecc event in the platform ram. after this bit has been enabled to generate another co ntinuous 1-bit data inversion, it must be cleared before being set again to correctly re-enable the error generation logic. this bit can only be set if the same soc configurable input enable signal (as that used to enable single-bit correction reporting) is asserted. fr11bi force platform ram one 1-bit data inversion 0 = no platform ram single 1-bit data inversion is generated. 1 = one 1-bit data inversion in the platform ram is generated. the assertion of this bit forces the platform ram controller to create one 1-bit data inversion, as defined by the bit position specified in errbit[0:6], on the first write operation after this bit is set. the normal ecc generation takes place in the platform ram controller, but then the polarity of the bit position defined by errbit is inverted to in troduce a 1-bit ecc event in the platform ram. after this bit has been enabled to generate a single 1- bit data inversion, it must be cleared before being set again to properly re-enable the error generation logic. this bit can only be set if the same soc configurable input enable signal (as that used to enable single-bit correction reporting) is asserted. frcnci force platform ram continuous no n-correctable data inversions 0 = no platform ram continuous 2-bit data inversions are generated. 1 = 2-bit data inversions in the platform ram are continuously generated. the assertion of this bit forces the platform ram controller to create 2-bit data inversions, as defined by the bit position specified in errbit[0:6] and the overall odd parity bit, continuously on every write operation. after this bit has been enabled to generate another co ntinuous non-correctable data inversion, it must be cleared before being set again to properly re-enable the error generation logic. the normal ecc generation takes place in the platform ram controller, but then the polarity of the bit position defined by errbit and the overall odd parity bit are inverted to introduce a 2-bit ecc error in the platform ram. table 21-12. ecc error generation (eeg r) field descriptions (continued) name description
error correction status module (ecsm) 21-14 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 fr1nci force platform ram one non-correctable data inversions 0 = no platform ram single 2-bit data inversions are generated. 1 = one 2-bit data inversion in the platform ram is generated. the assertion of this bit forces the platform ram controller to create one 2-bit data inversion, as defined by the bit position specified in errbit[0:6] and the overall odd parity bit, on the first write operation after this bit is set. the normal ecc generation takes place in the platform ram controller, but then the polarity of the bit position defined by errbit and the overall odd parity bit are inverted to introduce a 2-bit ecc error in the platform ram. after this bit has been enabled to generate a single 2-bit error, it must be cleared before being set again to properly re-enable the error generation logic. errbit the vector defines the bit position which is co mplemented to create the data inversion on the write operation. for the creation of 2-bit data inversions, th e bit specified by this field plus the odd parity bit of the ecc code are inverted. the platform ram controller follows a vector bit ordering scheme where lsb=0. errors in the ecc syndrome bits can be generated by setting this field to a value greater than the platform ram width. for example, consider a 64-bit platform ram implementation and ecc organized on a 32-bit boundary. the 32-bit ecc approach requires 7 code bits for each 32-bit word. for platform ram data width of 64 bits, the actual sram is 2x (32b data + 7b for ecc) = 78 bits which is organized as two 39-bit memory banks, "even" bank and "odd" bank. the following association between the errbit field and the corrupted memory bit is defined: if errbit = 0, t hen ram[0] of the odd bank is inverted if errbit = 1, t hen ram[1] of the odd bank is inverted ... if errbit = 31, then ram[31] of the odd bank is inverted if errbit = 32, then ram[0] of the even bank is inverted if errbit = 33, then ram[1] of the even bank is inverted ... if errbit = 63, then ram[31] of the even bank is inverted if errbit = 64,then ecc parity[0 ] of the odd bank is inverted if errbit = 65,then ecc parity[1 ] of the odd bank is inverted ... if errbit = 70,then ecc parity[6 ] of the odd bank is inverted if errbit = 71,then ecc parity[0] of the even bank is inverted if errbit = 72,then ecc parity[1] of the even bank is inverted ... if errbit = 77,then ecc parity[6] of the even bank is inverted for errbit values between 78 and 98, no bit position is inverted. to accommodate address bus inversions, the errbit values start at 99 as defined: if errbit = 99, then addr[3] is inverted if errbit = 100, then addr[4] is inverted ... if errbit = 114, then addr[18] is inverted if errbit = 115, then addr[19] is inverted for errbit values greater than 115, the address bus inversion has no effect as only the lower 20 bits are used by the platform ram controller. table 21-12. ecc error generation (eeg r) field descriptions (continued) name description
error correction status module (ecsm) freescale semiconductor 21-15 pxs20 microcontroller reference manual, rev. 1 inversions of the address bus must be defined as non-correctable fo r the inversion to work and to resolve properly as a non-correctable error. one-bit data inversions of the address bus are ignored. if an attempt to force a non-correctable invers ion (by asserting eegr[f rcnci] or eegr[frc1nci]) and eegr[errbit] equals 64, then no data inversion will be generated. the only allowable values for the four control bit enables {fr11b i, frc1bi, frcnci, fr1nci} are {0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0,0,1,0} and {0,0,0,1}. all other values result in unpredictable operations. 21.4.2.12 platform flash memory ecc address register (pfear) the pfear is a 32-bit register for capturing the addr ess of the last, properly-enabled ecc event in the platform flash memory. depending on the state of the ecc configuration register, an ecc event in the platform flash memory causes the address, attributes and data associated with the access to be loaded into the pfear, pfemr, pfeat, pfedrl, a nd pfedrh registers, and the appr opriate flag (f1bc or fnce) in the ecc status register to be asserted. this register can only be read from the ips programming model; any attempted write is ignored. if no flash memory ecc event is defined to be handled for this module, accesses to this register wi ll terminate with an error. see figure 21-11 and table 21-13 for the pfear definition. register address: ecsm base + 0x0050 0123456789101112131415 r pfear[0:15] w reset:---------------- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pfear[16:31] w reset:---------------- = unimplemented figure 21-11. platform flash memory ecc address (pfear) register table 21-13. pfear field descriptions field description pfear platform flash memory ecc address this 32-bit register contains the faulting acce ss address of the last, properly-enabled platform flash memory ecc event.
error correction status module (ecsm) 21-16 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 21.4.2.13 platform flash ecc mast er number register (pfemr) the pfemr is a 4-bit register for capturing the xbar bus master number of th e last, properly-enabled ecc event in the platform flash memory. depending on the state of the ecc conf iguration register, an ecc event in the platform flash memo ry causes the address, attributes a nd data associated with the access to be loaded into the pfear, pfemr, pfeat, pfedrl, and pfedrh registers, a nd the appropriate flag (pf1bc or pfnce) in the ecc status register to be asserted. this register can only be read from the ips programming model; any attempted write is ignored. if no flash memory ecc event is defined to be handled for this module, accesses to this register wi ll terminate with an error. see figure 21-12 and table 21-14 for the pfemr definition. 21.4.2.14 platform flash memory ec c attributes (pfeat) register the pfeat is an 8-bit register for capturing the xbar bus master attri butes of the last, properly-enabled ecc event in the platform flash memory. depending on the state of the ecc conf iguration register, an ecc event in the platform flash memo ry causes the address, attributes a nd data associated with the access to be loaded into the pfear, pfemr, pfeat, pfedrl, and pfedrh registers, a nd the appropriate flag (f1bc or fnce) in the ecc stat us register to be asserted. this register can only be read from the ips programming model; any attempted write is ignored. if no flash memory ecc event is defined to be handled for this module, accesses to this register wi ll terminate with an error. see figure 21-13 and table 21-15 for the pfeat definition. register address: ecsm base + 0x0056 01234567 r0 0 0 0 pfemr w reset: 0 0 0 0 - - - - = unimplemented figure 21-12. platform flash memory ecc master number (pfemr) register table 21-14. pfemr field descriptions field description pfemr platform flash memory ecc master number this 4-bit field contains the xbar bus master number of the faulti ng access of the last, properly-enabled platform flash memory ecc event.
error correction status module (ecsm) freescale semiconductor 21-17 pxs20 microcontroller reference manual, rev. 1 21.4.2.15 platform flash memory ecc data registers (pfedrl and pfedrh) these two 32-bit registers contain a 64-bit field, pfedr, for capturing the data associated with the last, properly-enabled ecc event in the platform flash memory. de pending on the state of the ecc configuration register, an e cc event in the platform flash memory ca uses the address, at tributes and data associated with the access to be loaded into the pfear, pfemr, pfeat, pfedrh, and pfedrl registers, and the appropriate flag (f1bc or fnce ) in the ecc status register to be asserted. the data captured on a multi-bit non- correctable ecc error is undefined. these registers can only be read from the ips progr amming model; any attempte d write is ignored. if no flash memory ecc event is de fined to be handled for this module, ac cesses to these regist ers will terminate with an error. register address: ecsm base + 0x0057 01234567 r write size protection w reset: -------- = unimplemented figure 21-13. platform flash memory ecc attributes (pfeat) register table 21-15. pfeat field descriptions field description write amba-ahb hwrite 0 = amba-ahb read access 1 = amba-ahb write access size amba-ahb hsize[0:2] 0b000 = 8-bit amba-ahb access 0b001 = 16-bit amba-ahb access 0b010 = 32-bit amba-ahb access 0b1xx = reserved protection amba-ahb hprot[0:3] protection[3]: cacheable 0 = non-cacheable,1 = cacheable protection[2]: bufferable 0 = non-bufferable,1 = bufferable protection[1]: mode 0 = user mode, 1 = supervisor mode protection[0]: type 0 = i-fetch, 1 = data
error correction status module (ecsm) 21-18 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 21.4.2.16 platform ram ecc address register (prear) the prear is a 32-bit register for capturing the addr ess of the last, properly-e nabled ecc event in the platform ram. depending on the state of the ecc configurati on register, an ecc event in the platform register address: ecsm base +0x0058 0123456789101112131415 r pfedr[63:48] w reset:---------------- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pfedr[47:32] w reset:---------------- = unimplemented figure 21-14. platform flash memory ecc data high register (pfedrh) register address: ecsm base +0x005c 0123456789101112131415 r pfedr[31:16] w reset:---------------- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pfedr[15:0] w reset:---------------- = unimplemented figure 21-15. platform flash memory ecc data low register (pfedrl) table 21-16. pfedrl and pfedrh field descriptions field description pfedr platform flash memory ecc data this 64-bit field contains the data associated with the faulting access of the last, properly-enabled platform flash memory ecc event. the field contains the data value taken directly from the data bus.
error correction status module (ecsm) freescale semiconductor 21-19 pxs20 microcontroller reference manual, rev. 1 ram causes the address, attributes and data associat ed with the access to be loaded into the prear, presr, premr, preat, predrl, and predrh regist ers, and the appropriate flag (r1bc or rnce) in the ecc status register to be asserted. this register can only be read fr om the ips programming model; any attempted write is ignored. if no ram ecc event is defined to be handled for this module , accesses to this register will terminate with an error. see figure 21-16 and table 21-17 for the prear definition. 21.4.2.17 platform ram ecc sy ndrome register (presr) the presr is an 8-bit register fo r capturing the error syndrome of th e last, properly-enabled ecc event in the platform ram. depending on the state of th e ecc configuration register, an ecc event in the platform ram causes the address, at tributes and data associ ated with the access to be loaded into the prear, presr, premr, preat, predrl, and predrh registers, and the appr opriate flag (r1bc or rnce) in the ecc status register to be asserted. this register can only be read fr om the ips programming model; any attempted write is ignored. if no ram ecc event is defined to be handled for this module , accesses to this register will terminate with an error. see figure 21-17 and table 21-18 for the presr definition. register address: ecsm base + 0x0060 0123456789101112131415 r prear[0:15] w reset:---------------- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r prear[16:31] w reset:---------------- = unimplemented figure 21-16. platform ram ecc address (prear) register table 21-17. prear field descriptions field description prear platform ram ecc address this 32-bit field contains the faulting access addr ess of the last, properly-enabled platform ram ecc event.
error correction status module (ecsm) 21-20 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 note table 21-18 associates the 8 bits of the syndrome value with the data or ecc bit in error. this table follows the bit vectoring notation where the lsb=0. register address: ecsm base + 0x0065 01234567 r presr w reset:-------- = unimplemented figure 21-17. platform ram ecc syndrome (presr) register table 21-18. presr field descriptions field description presr platform ram ecc syndrome this 8-bit syndrome field includes 6 bits of hamming decoded parity plus an odd-parity bit for the entire 39-bit (32-bit data + 7 ecc) code word. the upper 7 bits of the syndrome specify the exact bit position in error for single-bit correctable code words, and the combination of a non-zero 7-bit syndrome plus overall incorrect parity bit signal a multi-bit, non-correctable error. for correctable single-bit errors, the mapping shown in table 21-18 associates the upper 7 bits of the syndrome with the data bit in error. table 21-19. platform ram syndrome mapping for single-bit correctable errors presr data bit in error 0x01 ecc odd[0] 0x02 ecc odd[1] 0x04 ecc odd[2] 0x07 data odd bank[31] 0x08 ecc odd[3] 0x10 ecc odd[4] 0x20 ecc odd[5] 0x40 ecc odd[6] 0x43 data odd bank[0] 0x45 data odd bank[1] 0x46 data odd bank[2] 0x49 data odd bank[3] 0x4a data odd bank[4] 0x4c data odd bank[5] 0x4f data odd bank[21] 0x51 data odd bank[6] 0x52 data odd bank[7] 0x54 data odd bank[8]
error correction status module (ecsm) freescale semiconductor 21-21 pxs20 microcontroller reference manual, rev. 1 0x57 data odd bank[22] 0x58 data odd bank[9] 0x5b data odd bank[23] 0x5d data odd bank[24] 0x5e data odd bank[25] 0x61 data odd bank[10] 0x62 data odd bank[11] 0x64 data odd bank[12] 0x67 data odd bank[26] 0x68 data odd bank[13] 0x6b data odd bank[27] 0x6d data odd bank[28] 0x6e data odd bank[29] 0x70 data odd bank[14] 0x73 data odd bank[15] 0x75 data odd bank[16] 0x76 data odd bank[17] 0x79 data odd bank[18] 0x7a data odd bank[19] 0x7c data odd bank[20] 0x7f data odd bank[30] 0x81 ecc even[0] 0x82 ecc even[1] 0x84 ecc even[2] 0x87 data even bank[31] 0x88 ecc even[3] 0x90 ecc even[4] 0xa0 ecc even[5] 0xc0 ecc even[6] 0xc3 data even bank[0] 0xc5 data even bank[1] 0xc6 data even bank[2] 0xc9 data even bank[3] 0xca data even bank[4] 0xcc data even bank[5] 0xcf data even bank[21] 0xd1 data even bank[6] 0xd2 data even bank[7] 0xd4 data even bank[8] 0xd7 data even bank[22] 0xd8 data even bank[9] 0xdb data even bank[23] table 21-19. platform ram syndrome mapping for single-bit correctable errors (continued) presr data bit in error
error correction status module (ecsm) 21-22 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 21.4.2.18 platform ram ecc master number register (premr) the premr is a 4-bit register for capturing the xbar bus master number of th e last, properly-enabled ecc event in the platform ram. de pending on the state of the ecc conf iguration register, an ecc event in the platform ram causes the addre ss, attributes and data associated with the access to be loaded into the prear, presr, premr, preat, predrl, and predrh registers, and the appropriate flag (r1bc or rnce) in the ecc stat us register to be asserted. this register can only be read fr om the ips programming model; any attempted write is ignored. if no ram ecc event is defined to be handled for this module , accesses to this register will terminate with an error. see figure 21-18 and table 21-20 for the premr definition. 0xdd data even bank[24] 0xde data even bank[25] 0xe1 data even bank[10] 0xe2 data even bank[11] 0xe4 data even bank[12] 0xe7 data even bank[26] 0xe8 data even bank[13] 0xeb data even bank[27] 0xed data even bank[28] 0xee data even bank[29] 0xf0 data even bank[14] 0xf3 data even bank[15] 0xf5 data even bank[16] 0xf6 data even bank[17] 0xf9 data even bank[18] 0xfa data even bank[19] 0xfc data even bank[20] 0xff data even bank[30] register address: ecsm base + 0x0066 01234567 r0 0 0 0 premr w reset: 0 0 0 0 - - - - = unimplemented figure 21-18. platform ram ecc master number (premr) register table 21-19. platform ram syndrome mapping for single-bit correctable errors (continued) presr data bit in error
error correction status module (ecsm) freescale semiconductor 21-23 pxs20 microcontroller reference manual, rev. 1 21.4.2.19 platform ram ecc a ttributes (preat) register the preat is an 8-bit register for capturing the xbar bus master attributes of the last, properly-enabled ecc event in the platform ram. de pending on the state of the ecc conf iguration register, an ecc event in the platform ram causes the addre ss, attributes and data associated with the access to be loaded into the prear, presr, premr, preat, predrl, and predrh registers, and the appropriate flag (r1bc or rnce) in the ecc stat us register to be asserted. this register can only be read fr om the ips programming model; any attempted write is ignored. if no ram ecc event is defined to be handled for this module , accesses to this register will terminate with an error. see figure 21-19 and table 21-21 for the preat definition. table 21-20. premr field descriptions field description premr platform ram e cc master number this 4-bit field contains the xbar bus master number of the faulting access of the last, correctly-enabled ram ecc event. register address: ecsm base + 0x0067 01234567 r write size protection w reset:-------- = unimplemented figure 21-19. platform ram ecc attributes (preat) register table 21-21. preat field descriptions field description write amba-ahb hwrite 0 = amba-ahb read access 1 = amba-ahb write access size amba-ahb hsize[0:2] 0b000 = 8-bit amba-ahb access 0b001 = 16-bit amba-ahb access 0b010 = 32-bit amba-ahb access 0b1xx = reserved protection amba-ahb hprot[0:3] protection[3]: cacheable 0 = non-cacheable, 1 = cacheable protection[2]: bufferable 0 = non-bufferable,1 = bufferable protection[1]: mode 0 = user mode, 1 = supervisor mode protection[0]: type 0 = i-fetch, 1 = data
error correction status module (ecsm) 21-24 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 21.4.2.20 platform ram ecc data registers (predrl and predrh) these two 32-bit registers contain a 64-bit field, predr, for capturing the data associated with the last, properly-enabled ecc event in th e platform ram. depending on the state of the ecc configuration register, an ecc event in the platform ram causes th e address, attributes and data associated with the access to be loaded into the prear, presr, pr emr, preat, predrl, and predrh registers, and the appropriate flag (r1bc or rnce) in th e ecc status register to be asserted. the data captured on a multi-bit non- correctable ecc error is undefined. these registers can only be read from the ips progr amming model; any attempte d write is ignored. if no ram ecc event is defined to be handled for this modul e, accesses to these regist ers will terminate with an error. register address: ecsm base +0x0068 0123456789101112131415 r predr[63:48] w reset: ---------------- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r predr[47:32] w reset: ---------------- = unimplemented figure 21-20. platform ram ecc data high register (predrh) register address: ecsm base +0x006c 0123456789101112131415 r predr[31:16] w reset: ---------------- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r predr[15:0] w reset: ---------------- = unimplemented figure 21-21. platform ram ecc data low register (predrl)
error correction status module (ecsm) freescale semiconductor 21-25 pxs20 microcontroller reference manual, rev. 1 table 21-22. predrl and predrh field descriptions field description predr platform ram ecc data this 64-bit field contains the data asso ciated with the faulting access of the last, properly-enabled platform ram ecc event. the field contains the data value taken directly from the data bus.
error correction status module (ecsm) 21-26 freescale semiconductor pxs20 microcontroller reference manual, rev. 1
fault collection and control unit (fccu) freescale semiconductor 22-1 pxs20 microcontroller reference manual, rev. 1 chapter 22 fault collection and control unit (fccu) 22.1 introduction the fault collection and control un it (fccu) offers a programmable redundant hardware channel to collect errors and to lead the device in a controlled way to a safe state when a failure is present in the device. no cpu intervention is request ed for collection and control operation. the fccu offers a systematic approach to manage fault detection and control. the main functions supported by the module are: ? redundant collection of hardware ch ecker (for exampl e, rccu) results ? redundant collection of error information from cr itical modules on the chip (such as the flash memory or the stcu) ? collection of test results ? configurable and graded fault c ontrol via user software control ? internal reactions: ? no reset reaction ?irq ? short ?functional? reset ? long ?functional? reset ? safe mode request ? external reaction (failure is reported to the outside world via output pins) ? watchdog timer for the re-configuration phase ? configuration lock ? nvm configuration loading ? self checking capabilities: ? fccu internal control logic redundancy ? additional parity check for the a ssociated configuration registers the fccu circuitry is chec ked at start-up by the self -checking procedure. the fc cu is operative with a default configuration (without cpu intervention) immediately after th e completion of the self-checking procedure. two classes of faults ? critical a nd non-critical ? are iden tified based on the criticality and the related reactions. internal (short or long ?f unctional? reset, interrupt request ) and external (fccu_f signaling) reactions are statically defined or programmable based on the fault crit icality. the default configuration can be modified only in a specific fccu state for application/ test/debugging purposes.
fault collection and control unit (fccu) 22-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 22.1.1 glossary and acronyms 22.2 main features ? management of: ? 32 critical faults ? 32 non-critical faults ? hardware or software fa ult recovery management ? fault detection collection ? fault injection (fake faults) ? external reaction via fau lt-state dedicated system signals (fccu_f pins) ? internal (chip) reactions (a larm state): interrupt request ? internal (chip) reactions (fault state): ? long ?functional? reset ? short ?functional? reset ? non-maskable interrupt (nmi) ? safe mode request ? bi-stable, dual-rail and time switch ing output protocols using fccu_f pins ? internal (to the fccu) watchdog ti mer for the re-configuration phase ? configuration lock ? nvm configuration loading ? self-checking capabilities: table 22-1. acronyms term description rcc redundancy control checkers rccu redundancy control checker unit ips internal peripheral system nmi non-maskable interrupts irq interrupt request stcu self testing control unit fsm finite state machine cf critical fault ncf non-critical fault ws wait state sw software nvm nonvolatile memory cpu central processing unit
fault collection and control unit (fccu) freescale semiconductor 22-3 pxs20 microcontroller reference manual, rev. 1 ? fsm redundancy ? parity check for the configuration registers 22.3 block diagram the top-level diagram of the fccu is shown in figure 22-1 . figure 22-1. fccu top-level diagram as shown in figure 22-1 , the fccu includes the following sub-modules: ? reg if: it includes the register file, the register interface, the irq interface and the parity block (pb) for the configuration registers. ? hnshk blocks (master and slave blocks): it includes the fsms to support the handshake between the reg if and the fsm unit due to the usage of 2 asynchronous cl ocks (system clock and ircosc clock). ? finite state machine (fsm) units implement the main functions of the fccu. these units also include also the watchdog timer (wdog), the safe mode request timer (smrt), and the alarm timer (alrt). ? fault if: implements the interface fo r the fault conditioning and management ? fccu_fx units implement the output stage to manage the fccu_f pins. ? rccx units implement the redundancy control ch ecker to monitor the fsm unit state and its configuration. ips mc_rgm, intc fccu_f[1] fccu_f[0] mc_rgm, intc mc_rgm, nmi fault if fault system clock pb hnshk (master) reg if alrt smrt wdog fsm0 wdog smrt alrt fsm1 rcc1 rcc0 fccu_f1 if fccu_f0 if hnshk (slave)
fault collection and control unit (fccu) 22-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 note the fccu redundancy control checker s (rcc) should not be confused with the redundancy control checke r units (rccu) instantiated on the pxs20 to detect critical lockstep failure). 22.4 signal description the fccu generates two external signals, fccu _f[0] and fccu_f[1]. these are described in section 22.7.10, fccu_f interface . 22.5 register interface the register interface is a slave bus us ed for configuration purposes via the cpu. the following bus operations are supported: ? word (32-bit) data write/read operations to any registers ? low and high half-words (16-bit, data[0:15] or data[16:31]) data write/read operations to any registers ? byte (8 bits, data[0:7] or data[8:15] or data[16:23] or data[ 24:31]) data write/rea d operations to any registers any other operation (free byte enables, misaligned wo rd or half-word access or other operations) are not supported. the fccu generates a transfer error in the following cases: ? any write/read access executed outside the address space of the peripheral ? any write/read operation different from byte/halfwo rd/word (free byte enab les, misaligned access, or other operations) on each register ? any write access to the configuration registers not executed while the fccu is not in config state the registers of the fccu are accessible (read/wri te) in each access mode: user, supervisor, or test. 22.6 memory map and register description the fccu registers are listed in table 22-2 . the contents of the configurati on registers (labeled as ?w in config state only? in the access column) can be locked by the op16 operation as defined in the fccu_ctrl register.
fault collection and control unit (fccu) freescale semiconductor 22-5 pxs20 microcontroller reference manual, rev. 1 table 22-2. fccu memory map address offset register access 1 location 0x00 fccu control register (fccu_ctrl) r/w always on page 22-6 0x04 fccu ctrl key register (fccu_ctrlk) w always on page 22-8 0x08 fccu configuration register (fccu_cfg) r always; w in config state only on page 22-9 0x0c fccu cf configuration regi ster 0 (fccu_cf_cfg0) r always; w in config state only on page 22-11 0x10 fccu cf configuration register 1 (fccu_cf_cfg1) 0x14 fccu cf configuration register 2 (fccu_cf_cfg2) 0x18 fccu cf configuration register 3 (fccu_cf_cfg3) 0x1c fccu ncf configuration regi ster 0 (fccu_ncf_cfg0) r always; w in config state only on page 22-12 0x20 fccu ncf configuration register 1 (fccu_ncf_cfg1) 0x24 fccu ncf configuration register 2 (fccu_ncf_cfg2) 0x28 fccu ncf configuration register 3 (fccu_ncf_cfg3) 0x2c fccu cfs configuration regi ster 0 (fccu_cfs_cfg0) r always; w in config state only on page 22-13 0x30 fccu cfs configuration register 1 (fccu_cfs_cfg1) 0x34 fccu cfs configuration register 2 (fccu_cfs_cfg2) 0x38 fccu cfs configuration register 3 (fccu_cfs_cfg3) 0x3c fccu cfs configuration register 4 (fccu_cfs_cfg4) 0x40 fccu cfs configuration register 5 (fccu_cfs_cfg5) 0x44 fccu cfs configuration register 6 (fccu_cfs_cfg6) 0x48 fccu cfs configuration register 7 (fccu_cfs_cfg7) 0x4c fccu ncfs configuration regi ster 0 (fccu_ncfs_cfg0) r always; w in config state only on page 22-15 0x50 fccu ncfs configuration register 1 (fccu_ncfs_cfg1) 0x54 fccu ncfs configuration register 2 (fccu_ncfs_cfg2) 0x58 fccu ncfs configuration register 3 (fccu_ncfs_cfg3) 0x5c fccu ncfs configuration register 4 (fccu_ncfs_cfg4) 0x60 fccu ncfs configuration register 5 (fccu_ncfs_cfg5) 0x64 fccu ncfs configuration register 6 (fccu_ncfs_cfg6) 0x68 fccu ncfs configuration register 7 (fccu_ncfs_cfg7) 0x6c fccu cf status regist er 0 (fccu_cfs0) r/w always on page 22-15 0x70 fccu cf status register 1 (fccu_cfs1) 0x74 fccu cf status register 2 (fccu_cfs2) 0x78 fccu cf status register 3 (fccu_cfs3) 0x7c fccu cf key register (fccu_cfk) w always on page 22-17
fault collection and control unit (fccu) 22-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 22.6.1 fccu control re gister (fccu_ctrl) the fccu_ctrl register allows ex ecution of the following operations: ? move the fccu state from the nor mal state into the config state ? move the fccu state from the config state into the normal state ? read or clear the cf status register ? read or clear the ncf status register ? read the fccu fsm status register 0x80 fccu ncf status register 0 (fccu_ncfs0) r/w always on page 22-18 0x84 fccu ncf status r egister 1 (fccu_ncfs1) 0x88 fccu ncf status r egister 2 (fccu_ncfs2) 0x8c fccu ncf status r egister 3 (fccu_ncfs3) 0x90 fccu ncf key register (fccu_ncfk) w always on page 22-19 0x94 fccu ncf enable register 0 (fccu_ncfe0) r always; w in config state only on page 22-20 0x98 fccu ncf enable register 1 (fccu_ncfe1) 0x9c fccu ncf enable register 2 (fccu_ncfe2) 0xa0 fccu ncf enable register 3 (fccu_ncfe3) 0xa4 fccu ncf time-out enable register 0 (fccu_ncf_toe0) r always; w in config state only on page 22-21 0xa8 fccu ncf time-out enable register 1 (fccu_ncf_toe1) 0xac fccu ncf time-out enable register 2 (fccu_ncf_toe2) 0xb0 fccu ncf time-out enable register 3 (fccu_ncf_toe3) 0xb4 fccu ncf time-out register (fccu_ncf_to) r always; w in config state only on page 22-21 0xb8 fccu cfg timeout register (fccu_cfg_to) r always; w in config state only on page 22-22 0xc0 fccu status register (fccu_stat) r always on page 22-23 0xd8 fccu cf fake register (fccu_cff) w always on page 22-24 0xdc fccu ncf fake register (fccu_ncff) w always on page 22-24 0xe0 fccu irq status register (fccu_irq_stat) r/w always on page 22-25 0xe4 fccu irq enable register (fccu_irq_en) r/w always on page 22-26 0xe8 fccu xtmr register (fccu_xtmr) r always on page 22-27 0xec fccu mcs register (fccu_mcs) r always on page 22-28 notes: 1 in this column, r/w = read/write, r = read-only, and w = write-only. table 22-2. fccu memory map (continued) address offset register access 1 location
fault collection and control unit (fccu) freescale semiconductor 22-7 pxs20 microcontroller reference manual, rev. 1 ? read or clear the fc cu freeze registers ? lock the fccu conf iguration registers ? read the alarm timer ? read the smrt timer ? read the watchdog timer ? load the nvm configuration (only for test purposes) some critical operations (op1, op 2, op16, and op31) require a key as defined in the fccu_ctrlk register. offset: 0x00 access: user read/write 0123456789101112131415 r00000 0 000000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 000000 nvml ops 0 opr w reset00000000/1 1 0/1 1 0/1 1 000000 1 1 when nvm interface is used, 0 otherwise. figure 22-2. fccu contro l register (fccu_ctrl) table 22-3. fccu_ctrl field descriptions field description nvml nvm configuration loaded 0 no nvm configuration loaded. 1 nvm configuration loaded. at the end of the reset phase3, nvml = 1 and ops = 11 if the nvm interface of the fccu is correctly driven by the sscm interface. this bit can be read and cleared (via op15 operation) by the software. ops operation status 00 idle. 01 in progress. 10 aborted. 11 successful. this bit can be read and cleared (via op15 operation) by the software.
fault collection and control unit (fccu) 22-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 22.6.2 fccu ctrl key register (fccu_ctrlk) the fccu_ctrlk register impl ements the key access for th e operations op1, op2, op16, op31 according to the following sequence: 1. write the key into the fccu_ctrlk register. opr operation run 00000 no operation [op0]. 00001 set the fccu into the config state [op1]. 00010 set the fccu into t he normal state [op2]. 00011 read the fccu state (refer to the fccu_stat register) [op3]. 00100 read the fccu frozen status flags [op4]. 00101 read the fccu frozen status flags [op5]. 00110 read the fccu frozen status flags [op6]. 00111 read the fccu frozen status flags [op7]. 01000 read the fccu frozen status flags [op8]. 01001 read the cf status register (re fer to the fccu_cfs register) [op9]. 01010 read the ncf status register (refer to the fccu_ncfs register) [op10]. 01011 cf status clear operation in progre ss (refer to the fccu_cfs register) [op11]. 01100 ncf status clear operation in progress (refer to the fccu_nc fs register) [op12]. 01101 clear the freeze status registers (re fer to the freeze registers) [op13]. 01110 config to normal fccu state (confi guration timeout) in progress [op14]. 01111 clear the operation status (ops = idle, nvml = 0) [op15]. 10000 lock the fccu configuration [op16]. 10001 read the alarm timer (refer to the fccu_xtmr register) [op17]. 10010 read the smrt timer (refer to the fccu_xtmr register) [op18]. 10011 read the cfg timer (refer to the fccu_xtmr register) [op19]. 10100?11111 reserved [op20?op30]. 11111 run the nvm loading operation (only for test purposes) [op31]. the software must not modify the opr field unt il the completion of the operation (any write operation will be ignored until then). after the op eration has been completed, the ops field is set and the opr field is automatically cleared (opr = 000). your software must not program the following opcodes: ? op11 and op12 (these opcodes are automa tically selected when the fccu_cfs or fccu_ncfs registers are cleared by a write-cl ear operation into the related register) ? op14 (this opcode is automatically selected when the timeout occurs [fccu_cfg_to] during the configuration procedure. in this case, t he fccu state is automatic ally forced in normal mode setting the default configuration. in this phase any write operation to the fccu configuration registers is inhibited.) ? op20?op30 (these are reserved; if you atte mpt to use them, they will return an abort response without any side effect) the abort response occurs in the following cases: ? wrong access (missing or wrong key) to the fccu_cfs register (clear operation op11) ? wrong access (missing or wrong key) to the fccu_ncfs register (clear operation op12) ? wrong access (missing or wrong key) to the fccu_ctrl register (op1, op2, op16 operation) ? op1 (config command) execution when fccu state ? normal or configuration locked ? op20?op30 (reserved operations) execution the op31 opcode executes the nvm configuration loading via the software. it should be used only for test/debug purposes. table 22-3. fccu_ctrl field descriptions (continued) field description
fault collection and control unit (fccu) freescale semiconductor 22-9 pxs20 microcontroller reference manual, rev. 1 2. write the fccu_ctrl register ( operations op1, op2, op16, or op31). the fccu_ctrlk register is not readable. a read operation al ways returns 0x0000_0000. the key must be written by a word (32-bi t) data write operation. 22.6.3 fccu configuratio n register (fccu_cfg) the fccu_cfg register is accessibl e in write mode only in the conf ig state. it defines the global configuration for the fccu. offset: 0x04 access: user write-only 0123456789101112131415 r w ctrlk[31:16] reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r w ctrlk[15:0] reset00000000 00000000 figure 22-3. fccu ctrl ke y register (fccu_ctrlk) table 22-4. fccu_ctrl k field descriptions field description ctrlk control register key: ctrlk value function 0x9137_56af key for operation op1 0x825a_132b key for operation op2 0x7acb_32f0 key for operation op16 0x29af_8752 key for operation op31
fault collection and control unit (fccu) 22-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 offset: 0x008 access: user read/write 1 0123456789101112131415 r 0 0 0 0 0 0 0 0 0 0 rcce1 rcce0 smrt w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 fcc u_c fg.c m fcc u_c fg.s m fcc u_c fg.p s fccu_cfg.fom fccu_cfg.fop w reset00000000 00111111 1 writable only in the config state figure 22-4. fccu configurat ion register (fccu_cfg) table 22-5. fccu_cfg field descriptions field description rcce1 rcc1 enable 0 rcc1 disabled. 1 rcc1 enabled. note: in case a single checker (rcc1 or rcc0 unit) is enabled, both the checkers assert a fault condition (destructive reset). rcce0 rcc0 enable 0 rcc0 disabled. 1 rcc0 enabled. note: in case a single checker (rcc1 or rcc0 unit) is enabled, both the checkers assert a fault condition (destructive reset). smrt safe mode request timer 0000 safe mode request delay = 1 period (ircosc clock). 0001 safe mode request delay = 2 periods (ircosc clock). 0010 safe mode request delay = 4 periods (ircosc clock). ... 1111 safe mode request delay = 32768 periods (ircosc clock). fccu_cfg.cm configuration mode 0 configuration labelling: a specific fccu_f co nfiguration is assig ned in config state. 1 configuration transparency: the fccu_f prot ocol is the same in config and normal states. fccu_cfg.sm switching mode 0 fccu_f protocol (dual-rail, time-s witching) slow switching mode. 1 fccu_f protocol (dual-rail, time-switching) fast switching mode. sm has no effect on the bi-stable protocol. fccu_cfg.ps polarity selection 0 fccu_f[1] active high, fccu_f[0] active high. 1 fccu_f[1] active low, fccu_f[0] active low.
fault collection and control unit (fccu) freescale semiconductor 22-11 pxs20 microcontroller reference manual, rev. 1 22.6.4 fccu cf configuration register (fccu_cf_cfg0..3) the fccu_cf_cfgx register is acces sible in write mode only in the config state. it contains the configuration of each critic al fault in terms of fa ult recovery management. the configuration depends on the type of signaling following a fault even t. hardware recoverable faults should be configured only if a pr evious latching stage captures and hold the physical fault otherwise the fault can be lost. all the other faults should be configur ed as sw fault. fccu_cfg.fo m fault output mode selection 000 dual-rail (default stat e; fccu_f[1: 0]= outputs). 001 time switching (f ccu_f[1:0]= outputs). 010 bi-stable (fccu_f[1:0]= outputs). 011 reserved. 100 reserved. 101 test0 (fccu_f[0] = input, fccu_f[1]= output) 110 test1 (fccu_f[0] = output, fccu_f[1]= output) 111 test2 (fccu_f[0] = output, fccu_f[1]= input) note: in test n mode, a simple double-stage resynchroniza tion stage is used to resynchronize the fccu_f input/outp uts on the system/ircosc clock. fccu_cfg.fop fault output prescaler fop defines the prescaler setting used to generate the fccu_f protocol frequency. 00 0000 input clock frequency (ircosc clock) is divided by 2 00 0001 input clock frequency (ircosc clock) is divided by 4 00 0010 input clock frequency (ircosc clock) is divided by 6 00 0011 input clock frequency (ircosc clock) is divided by 8 00 0100 input clock frequency (ircosc clock) is divided by 10 00 0101 input clock frequency (ircosc clock) is divided by 12 00 0110 input clock frequency (ircosc clock) is divided by 14 the following equation gives the fccu_f frequency: table 22-5. fccu_cfg field descriptions (continued) field description f fccu_f f ircosc 1024 fop 1 + ?? ? 2 ? ?? ? =
fault collection and control unit (fccu) 22-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 22.6.5 fccu ncf configuration register (fccu_ncf_cfg0..3) the fccu_ncf_cfgx register is acces sible in write mode only in the config state. it contains the configuration of each non-cr itical fault in terms of fault recovery management. the configuration depends on the type of signaling of a fault event. hw recovera ble faults should be confi gured only if a previous latching stage captures and hold the phys ical fault otherwise the fault can be lost. all the ot her faults should be configured as sw fault. offset: 0x00c?0x018 (4 registers) access: user read/write 1 0123456789101112131415 r cfc 31 cfc 30 cfc 29 cfc 28 cfc 27 cfc 26 cfc 25 cfc 24 cfc 23 cfc 22 cfc 21 cfc 20 cfc 19 cfc 18 cfc 17 cfc 16 w reset 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cfc 15 cfc 14 cfc 13 cfc 12 cfc 11 cfc 10 cfc 9 cfc 8 cfc 7 cfc 6 cfc 5 cfc 4 cfc 3 cfc 2 cfc 1 cfc 0 w reset 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 1 writable only in the config state 2 1 for fccu_cf_cfg0; 0 otherwise figure 22-5. fccu cf configurat ion register (fccu_cf_cfg0..3) table 22-6. fccu_cf_cfg0 ..3 field descriptions field description cfcx critical fault configuration 0 hardware recoverable fault. 1 software recoverable fault. the critical fault configuration defines the fault recovery mode. hardware-recoverable faults are self recovered (status flag clearing) if the root cause has been removed. sw recoverable faults are recovered (status flag cl earing) by software clearing the related status flag.
fault collection and control unit (fccu) freescale semiconductor 22-13 pxs20 microcontroller reference manual, rev. 1 22.6.6 fccu cfs configuration register (fccu_cfs_cfg0..7) the fccu_cf_fs_cfgx register is accessible in write mode only in the config state. it contains the configuration of each cr itical fault in terms of fault reaction (short or long ?functional? rese t) when it is the root cause for the fault state transition. offset: 0x01c?0x028 (4 registers) access: user read/write 1 0123456789101112131415 r ncfc31 ncfc30 ncfc29 ncfc28 ncfc27 ncfc26 ncfc25 ncfc24 ncfc23 ncfc22 ncfc21 ncfc20 ncfc19 ncfc18 ncfc17 ncfc16 w reset 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ncfc15 ncfc14 ncfc13 ncfc12 ncfc11 ncfc10 ncfc9 ncfc8 ncfc7 ncfc6 ncfc5 ncfc4 ncfc3 ncfc2 ncfc1 ncfc0 w reset 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 1 writable only in the config state 2 1 for fccu_ncf_cfg0; 0 otherwise figure 22-6. fccu ncf configurat ion register (f ccu_ncf_cfg0..3) table 22-7. fccu_ncf_cfg0..3 field descriptions field description ncfcx non-critical fault configuration 0: hw recoverable fault 1: sw recoverable fault the non-critical fault configuration defines the fault recovery mode. hw recoverable faults are self recovered (status flag clearing and related) if the root cause has been removed. sw recoverable faults are recovered (status flag clearing) by sw clearing of the related status flag. this register can be read and written by the software.
fault collection and control unit (fccu) 22-14 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 offset: 0x02c access: user read/write 1 0123456789101112131415 r cfsc15 cfsc14 cfsc13 cfsc12 cfsc11 cfsc10 cfsc9 cfsc8 w reset10101010 10101010 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cfsc7 cfsc6 cfsc5 cfsc4 cfsc3 cfsc2 cfsc1 cfsc0 w reset10101010 10101010 1 writable only in the config state figure 22-7. fccu cfs configurat ion register 0 (fccu_cfs_cfg0) offset: 0x030 access: user read/write 1 0123456789101112131415 r cfsc15 cfsc14 cfsc13 cfsc12 cfsc11 cfsc10 cfsc9 cfsc8 w reset10101010 10000010 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cfsc7 cfsc6 cfsc5 cfsc4 cfsc3 cfsc2 cfsc1 cfsc0 w reset10000000 00001010 1 writable only in the config state figure 22-8. fccu cfs configurat ion register 1 (fccu_cfs_cfg1) offset: 0x034?0x048 (6 registers) access: user read/write 1 0123456789101112131415 r cfsc15 cfsc14 cfsc13 cfsc12 cfsc11 cfsc10 cfsc9 cfsc8 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cfsc7 cfsc6 cfsc5 cfsc4 cfsc3 cfsc2 cfsc1 cfsc0 w reset00000000 00000000 1 writable only in the config state figure 22-9. fccu cfs configuration register 2..7 (fccu_cfs_cfg2..7)
fault collection and control unit (fccu) freescale semiconductor 22-15 pxs20 microcontroller reference manual, rev. 1 22.6.7 fccu ncfs configuration register (fccu_ncfs_cfg0..7) the fccu_ncf_fs_cfgx register is accessible in write mode only in the config st ate. it contains the configuration of each non-crit ical fault in terms of fa ult reaction (short or long ?f unctional? reset) when it is the root cause for the fault state transition. 22.6.8 fccu cf status re gister (fccu_cfs0..3) the fccu_cfsx register contains the latched fault i ndication collected from the critical fault sources. faults are latched even if the fccu is in the co nfig state and independent ly from the enabling or reactions programmed for the cf. no reactions are executed until th e fccu moves in the normal state. fccu reacts and moves from the normal or alarm state into the fault state if a crit ical fault is triggered. the status bits of the table 22-8. fccu_cfs_cfg0..7 field descriptions field description cfscx critical fault state configuration 00: no reset reaction 01: short functional reset (fault state reaction) 10: long functional reset (fault state reaction) 11: no reset reaction this register can be read and written by the software. offset: 0x04c?0x068 (8 registers) access: user read/write 1 0123456789101112131415 r ncfsc15 ncfsc14 ncfsc13 ncfsc12 ncfsc11 ncfsc10 ncfsc9 ncfsc8 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ncfsc7 ncfsc6 ncfsc5 ncfsc4 ncfsc3 ncfsc2 ncfsc1 ncfsc0 w reset 0/1 2 00/1 2 00/1 2 00/1 2 00/1 2 00/1 2 00/1 2 00/1 2 0 1 writable only in the config state 2 1 for fccu_ncfs_cfg0; 0 otherwise figure 22-10. fccu ncfs configurat ion register (fccu_ncfs_cfg0..7) table 22-9. fccu_ncfs_cfg0..7 field descriptions field description ncfscx non-critical fault state configuration 00: no reset reaction 01: short ?functional? reset (fault state reaction) 10: long ?functional? reset (fault state reaction) 11: no reset reaction this register can be read and written by the software.
fault collection and control unit (fccu) 22-16 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 fccu_cfsx register, configured as sw recoverabl e faults, can be cleared by the following locked sequence: ? to write the proper key into the fccu_cfk register ? to clear the status (flag) bit cfsx ? the opcode op11 is automatically set into the fccu_ctrl.opr field ? to wait for the completion of th e operation (fccu_ctrl.ops field) ? to read the fccu_cfsx register in order to verify the effective deletion and in case of failure to repeat the sequence as result of the above sequence, in addition the fault interface provides suppor t to clear the external fault root. the fccu moves from the fault state into the no rmal state if the source fault which caused the transition into the fault state ha s been removed (hw recoverable fault) or cleared via sw (sw recoverable fault). concurrently th e fault interface provides support to clear the fault root. in case of nested faults that are not al l recovered, the fccu remains into the fault state or moves into the alarm state. the sw application executes the fccu_cfsx read operation by the following sequence: ? to set the op9 operation into the fccu_ctrl.opr field ? to wait for the completion of th e operation (fccu_ctrl.ops field) ? to read the fccu_cfsx register the following errors are ignored: ? to write a wrong key into the fccu_cfk register ? to attempt to clear a hw recoverable error note register fccu_cfs0 show s status of cf[0:31]. register fccu_cfs1 shows status of cf [37] (bit26). all ot her register bits of fccu_cfs1 are unused. offset: 0x06c?0x078 (4 registers) access: user read/write 0123456789101112131415 r cfs31 cfs30 cfs29 cfs28 cfs27 cfs26 cfs25 cfs24 cfs23 cfs22 cfs21 cfs20 cfs19 cfs18 cfs17 cfs16 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cfs15 cfs14 cfs13 cfs12 cfs11 cfs10 cfs9 cfs8 cfs7 cfs6 cfs5 cfs4 cfs3 cfs2 cfs1 cfs0 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 figure 22-11. fccu cf status register (fccu_cfs0..3)
fault collection and control unit (fccu) freescale semiconductor 22-17 pxs20 microcontroller reference manual, rev. 1 register fccu_cfs2 and register fccu_cfs3 are implemented but are not used. they do not show any status. 22.6.9 fccu cf key re gister (fccu_cfk) the fccu_cfk register implements th e key access to clear the status flags of the fccu_cfsx register. the status bits of the fccu_cfsx register, configured as sw recove rable faults, can be cleared by the following locked sequence: ? write the cfck key into the fccu_cfk register ? clear the status (flag) bit cfsx note the key must be written for each fccu_cfsx clear operation. the fccu_cfk register is not read able, a 0x00000000 value is always returned in case of read operation. table 22-10. fccu_cfs0..3 field descriptions field description cfsx critical fault status 0: no critical fault latched 1: critical fault latched the status bits related to the critical fault conf igured as hw recoverable faults are read-only and the flag is self cleared when the fault source is removed. the status bits related to the critical fault conf igured as sw recoverable faults are write-clear and the sw application can recover from a faulty condition. offset: 0x07c access: user write 0123456789101112131415 r w cfk[31:16] reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r w cfk[15:0] reset00000000 00000000 figure 22-12. fccu cf key register (fccu_cfk) table 22-11. fccu_cfk field descriptions field description cfk critical fault key = 0x618b7a50
fault collection and control unit (fccu) 22-18 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 22.6.10 fccu ncf status re gister (fccu_ncfs0..3) the fccu_ncfsx register contains the latched faul t indication collected from the non- critical fault sources. faults are latched also in the config state and independently from the enabling or reactions programmed for the ncf. no reactions are executed until the fccu moves in the normal state. fccu reacts and moves from the no rmal state into the alarm state only if the respective enable bit for a fault is set in the fccu_ncfex register and the respective enable bit for the time-out is set in the fccu_toex register. fccu reacts and moves from the normal or alarm state into the fault state if the respective enable bit for a fault is set in the fccu_ncfex regist er and the respective enable bit for the time-out is disabled in the fccu_toex register. fccu reacts and moves from the al arm state into the fault state if the time-out (fccu_to register) is elapsed before to recovery the fault. the time-out is stopped only when th e fccu returns in the normal state. the status bits of the fccu_ncfsx register, configured as sw recove rable faults, can be cleared by the following locked sequence: ? write the proper key into the fccu_ncfk register ? clear the status (flag) bit ncfsx ? the opcode op12 is automatically set into the fccu_ctrl.opr field ? wait for the completion of the operation (fccu_ctrl.ops field) ? read the fccu_ncfsx register in order to verify the effective deletion and in case of failure to repeat the sequence as result of the above sequence, in addition the fault interface provides suppor t to clear the external fault root. the fccu moves from the fault or alarm state into the normal state if all the source faults which caused the transition into the fault state has been removed (hw recoverable fa ult) or cleared via sw (sw recoverable fault). in ca se of nested faults that are not all recovered, the fccu will remain in the fault or alarm state. the sw application executes the fccu_ncfsx read operation by the following sequence: ? to set the op10 operation into the fccu_ctrl.opr field ? to wait for the completion of th e operation (fccu_ctrl.ops field) ? to read the fccu_ncfsx register in case of re-configuration of the fccu (config state), before to re turn in normal state the pending status bits into the fccu_ncfsx must be cleared in order to avoid a false transition in alarm/fault state. the following errors are ignored: ? to write a wrong key into the fccu_ncfk register ? to attempt to clear a hw recoverable error
fault collection and control unit (fccu) freescale semiconductor 22-19 pxs20 microcontroller reference manual, rev. 1 22.6.11 fccu ncf key re gister (fccu_ncfk) the fccu_ncfk register implements the key access to clear the status flags of the fccu_ncfsx register. the status bits of the fccu_ncfsx register, configured as sw recove rable faults, can be cleared by the following locked sequence: ? to write the key into the fccu_ncfk register ? to clear the status (flag) bit ncfsx note the key must be written for re ach fccu_ncfsx clear operation. the fccu_ncfk register is not readable, a 0x00000000 value is always returned in case of read operation. offset: 0x080?0x08c (4 registers) access: user read/write 0123456789101112131415 r ncfs31 ncfs30 ncfs29 ncfs28 ncfs27 ncfs26 ncfs25 ncfs24 ncfs23 ncfs22 ncfs21 ncfs20 ncfs19 ncfs18 ncfs17 ncfs16 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ncfs15 ncfs14 ncfs13 ncfs12 ncfs11 ncfs10 ncfs9 ncfs8 ncfs7 ncfs6 ncfs5 ncfs4 ncfs3 ncfs2 ncfs1 ncfs0 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 figure 22-13. fccu ncf status register (fccu_ncfs0..3) table 22-12. fccu_ncfs0..3 field descriptions field description ncfsx non-critical fault status 0: no ?non-critical? fault latched 1: ?non-critical fault? latched the status bits related to the non-critical fault co nfigured as hw recoverable faults are read-only and the flag is self cleared when the fault source is removed. the status bits related to the critical fault conf igured as sw recoverable faults are write-clear and the sw application can recover from a faulty condition.
fault collection and control unit (fccu) 22-20 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 22.6.12 fccu ncf enable register (fccu_ncfe0..3) the fccu_ncfex register enables th e critical fault sources to allow a transition from the normal into the fault or alarm state. in case of fault maski ng, the respective status bit into the fccu_ncfsx register is anyway set (for debugging purposes), only the r eaction is masked. the fccu_ncfes register is accessible in write mode only in the config state. offset: 0x090 access: user write 0123456789101112131415 r w ncfk[31:16] reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r w ncfk[15:0] reset00000000 00000000 figure 22-14. fccu ncf ke y register (fccu_ncfk) table 22-13. fccu_ncfk field descriptions field description ncfk critical fault key = 0xab3498fe offset: 0x094?0x0a0 (4 registers) access: user read/write 1 0123456789101112131415 r ncfe31 ncfe30 ncfe29 ncfe28 ncfe27 ncfe26 ncfe25 ncfe24 ncfe23 ncfe22 ncfe21 ncfe20 ncfe19 ncfe18 ncfe17 ncfe16 w reset00000000/1 2 0/1 2 0/1 2 00/1 2 000/1 2 0/1 2 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ncfe15 ncfe14 ncfe13 ncfe12 ncfe11 ncfe10 ncfe9 ncfe8 ncfe7 ncfe6 ncfe5 ncfe4 ncfe3 ncfe2 ncfe1 ncfe0 w reset 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 000/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 1 writable only in the config state 2 1 for fccu_ncfe0; 0 otherwise figure 22-15. fccu ncf enable register (fccu_ncfe0..3) table 22-14. fccu_ncfe0..3 field descriptions field description ncfex non-critical fault enable 0: no actions following the respective critical fault assertion 1: fccu moves to alarm or fault state
fault collection and control unit (fccu) freescale semiconductor 22-21 pxs20 microcontroller reference manual, rev. 1 22.6.13 fccu ncf time-out enable register (fccu_ncf_toe0..3) the fccu_ncftoex register enable s a transition from the normal st ate into the alarm state if the respective non-critical faul t is enabled (ncfex and ncftoex are set) . in case the respective time-out is disabled (ncftoex is cleared) and the non-critical fault is enabled (ncf ex is set) the fccu moves into the fault state if the related non-critical fault is asserted. the timer (preset with the time-out value defined by fccu_to register) is star ted when the fccu moves into the alarm state. if the fault is not recovered within the time-out the fccu move s from the alarm state to the fault state. the fccu_ncftoex register is accessible in write mode, only in the config state. 22.6.14 fccu ncf time-out register (fccu_ncf_to) the fccu_ncf_to register defines th e preset value of the timer for th e recovery of the non-critical faults (enabled). once fccu ente rs in alarm state, following the assertion of a non-critical fault enabled (ncfex and ncftoex are set) , the timer starts the count down. if the fault is not recovered with in the time-out the fccu moves fr om the alarm state to the fault state. the fccu_ncf_to register is accessible in write mode, only in the config state. offset: 0x0a4?0x0b0 (4 regist ers) access: user read/write 1 0123456789101112131415 r ncftoe31 ncftoe30 ncftoe29 ncftoe28 ncftoe27 ncftoe26 ncftoe25 ncftoe24 ncftoe23 ncftoe22 ncftoe21 ncftoe20 ncftoe19 ncftoe18 ncftoe17 ncftoe16 w reset00000000/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 00/1 2 0/1 2 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ncftoe15 ncftoe14 ncftoe13 ncftoe12 ncftoe11 ncftoe10 ncftoe9 ncftoe8 ncftoe7 ncftoe6 ncftoe5 ncftoe4 ncftoe3 ncftoe2 ncftoe1 ncftoe0 w reset 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 1 writable only in the config state 2 1 for fccu_ncf_toe0; 0 otherwise figure 22-16. fccu ncf time-out enable register (fccu_ncf_toe0..3) table 22-15. fccu_ncf_toe0. .3 field descriptions field description ncftoex non-critical fault time-out enable 0: fccu moves into the fault state if the resp ective fault is disabled (ncfex is cleared) 1: fccu moves into the alarm state if the respective fault is enabled (ncfex is set)
fault collection and control unit (fccu) 22-22 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 22.6.15 fccu cfg timeout register (fccu_cfg_to) the fccu_cfg_to register defines the preset value of the watchdog tim er for the recovery from the config state. once fccu enters in config state, following a sw request (op1 opcode), the watchdog timer is initialized and starts the c ountdown if the reset is not asserted. if the configuration is not completed within the time-out, the fccu moves automatically from the config state to the normal state a nd the default values for the confi guration register is restored. the watchdog time-out is clocked with the ircosc clock (16 mhz). the default time-out value is 4,096 ms. the fccu_cfg_to register is accessible in write mode, in any state excluded the config state as follows the execution of the op1 opcode (normal to config state) and until the completion of the op2 opcode (config to normal state). in case of watchdog time-out the fccu_cfg_to regi ster is not accessible until the op14 operation (config to normal) has been completed. offset: 0x0b4 access: user read/write 1 0123456789101112131415 r to[31:16] w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r to[15:0] w reset11111111 11111111 1 writable only in the config state figure 22-17. fccu ncf time-o ut register (fccu_ncf_to) table 22-16. fccu_ncf_to field descriptions field description to non-critical fault timeout timeout to ?? t ? rc 16 mhz =
fault collection and control unit (fccu) freescale semiconductor 22-23 pxs20 microcontroller reference manual, rev. 1 22.6.16 fccu status re gister (fccu_stat) the fccu_stat register includes the fccu status for debugging/test purposes. the fccu finite state machine operates by the ircosc clock asynchronous wi th the system clock. the fccu status read operation requires a safe mechanism operated by a hw/sw synchronization sequence. the sw application executes a fccu status r ead operation by the following sequence: ? to set the op3 operation into the fccu_ctrl.opr field ? to wait for the completion of th e operation (fccu_ctrl.ops field) ? to read the fccu status (fccu_stat register) offset: 0x0b8 access: user read/write 0123456789101112131415 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 to w reset00000000 00000110 figure 22-18. fccu cfg time out register (fccu_cfg_to) table 22-17. fccu_cfg_to field descriptions field description to configuration time-out 000: time-out = 64 ? s .... 111: time-out = 8,192 ms offset: 0x0c0 access: user read 0123456789101112131415 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 status w reset00000000 00000000 figure 22-19. fccu status register (fccu_stat) timeout t rc 16 mhz 2 ? to 10 + ?? =
fault collection and control unit (fccu) 22-24 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 22.6.17 fccu cf fake register (fccu_cff) the fccu_cff register contains a uni que code to set a ?criti cal fault? in mutually exclusive mode by the external fault interface. it allows the sw emulation of the critical fa ults, by the injection of the fault directly in the fault root, in orde r to verify the en tire path and reaction. the fault injection mechanism is optional. the reaction following a fake critical fault cannot be ma sked. the fccu_cff is a write-only register with a set of codes corres ponding to each critical fault injection. 22.6.18 fccu ncf fake register (fccu_ncff) the fccu_ncff register contains a uni que code to set a ?non-critical fa ult? in mutually exclusive mode by the external fault interface. it allows the sw emul ation of the non-critical fa ults, by the injection of table 22-18. fccu_stat field descriptions field description status fccu status 000: normal state. 001: config state 010: alarm state 011: fault state other: unknown state this bit can be read by the software. offset: 0x0d8 access: user write 0123456789101112131415 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 w fcfc reset00000000 00000000 figure 22-20. fccu cf fake register (fccu_cff) table 22-19. fccu_cff field descriptions field description fcfc fake critical fault code 00h: fake critical fault injection at critical fault source 0 01h: fake critical fault injection at critical fault source 1 02h: fake critical fault injection at critical fault source 2 .. 1fh: fake critical fault injection at critical fault source 31 others: no fault injection these bits are always read as ?0? by software.
fault collection and control unit (fccu) freescale semiconductor 22-25 pxs20 microcontroller reference manual, rev. 1 the fault directly in the fault root, in order to ve rify the entire path and reaction. the fault injection mechanism is optional. the reacti on following a fake non-critical fa ult can be masked. the fccu_ncff is a write-only register with a set of codes co rresponding to each non-cr itical fault injection. 22.6.19 fccu irq status register (fccu_irq_stat) the fccu_irq_stat register defines the fccu interrupt status register related to the following events: ? configuration time-out error ? alarm interrupt ? nmi interrupt the external interrupt is asserted if any interrupt status bit of the fccu_irq_stat is set and the respective enable bit of the f ccu_irq_en register is also set. the nmi and alarm inte rrupts are asserted and cleared according to the fccu st ate. the status bits of the fccu_irq_stat trace the status of the related interrupt lines. offset: 0x0dc access: user write 0123456789101112131415 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 w fncfc reset00000000 00000000 figure 22-21. fccu ncf fake register (fccu_ncff) table 22-20. fccu_ncff field descriptions field description fncfc fake non-critical fault code 00h: fake non-critical fault injection at non-critical fault source 0 01h: fake non-critical fault injection at non-critical fault source 1 02h: fake non-critical fault injection at non-critical fault source 2 .. 1fh: fake non-critical fault injection at non-critical fault source 31 others: no fault injection these bits are always read as ?0? by software.
fault collection and control unit (fccu) 22-26 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 22.6.20 fccu irq enable register (fccu_irq_en) the fccu_irq_en register defines th e fccu interrupt enable register related to the following events: ? configuration time-out error the external interrupt is asserted if any interrupt status bit of the fccu_irq_stat is set and the respective enable bit of the f ccu_irq_en register is also set. offset: 0x0e0 access: user read/write 0123456789101112131415 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 nmi_status alrm_stat cfg_to_stat w w1c reset00000000 00000000 figure 22-22. fccu irq status register (fccu_irq_stat) table 22-21. fccu_irq_stat field descriptions field description cfg_to_stat configuration time-out status 0: no configuration time-out error 1: configuration time-out error this bit can be read and cleared by the software. alrm_stat alarm interrupt status 0: alarm interrupt is off 1: alarm interrupt is on this bit can be only read by the software. nmi_stat nmi interrupt status 0: nmi interrupt is off 1: nmi interrupt is on this bit can be only read by the software.
fault collection and control unit (fccu) freescale semiconductor 22-27 pxs20 microcontroller reference manual, rev. 1 22.6.21 fccu xtmr re gister (fccu_xtmr) the fccu_xtmr register contains th e read values of the alarm, watc hdog or safe mode request timer. these timers are clocked on the ircosc clock. the sw application executes the timer read operation by the following sequence: ? to set the op17 or op18 or op19 opera tion into the fccu_ctrl.opr field ? to wait for the completion of th e operation (fccu_ctrl.ops field) ? to read the fccu_xtmr register offset: 0x0e4 access: user read/write 0123456789101112131415 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cfg_to_ien w reset00000000 00000000 figure 22-23. fccu irq enable register (fccu_irq_en) table 22-22. fccu_irq_en field descriptions field description cfg_to_ien configuration time-out interrupt enable 0: configuration time-out interrupt disabled 1: configuration time-out interrupt enabled this bit can be read and written by the software. table 22-23. timer state/value timer config state normal state alarm state fault state alarm 00000000h initial value running idle/end of count smrt 00000001h initial value ? running/end of count cfg running 0001ffffh 0 001ffffh 0001ffffh
fault collection and control unit (fccu) 22-28 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 22.6.22 fccu mcs register (fccu_mcs) the fccu_mcs register contains a qu eue of the last 4 chip modes. mc s0 is the latest one, while mcs3 is the oldest one. in addition a quali fier indicates if the fccu is in the fault state when the chip mode has been captured. the chip mode is synchronous to the system clock and provided by a different module while the fccu state is synchronous to the ircosc clock, therefore some uncertainty must be considered regarding the fault state indication. offset: 0x0e8 access: user read 0123456789101112131415 r xtmr[31:16] w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r xtmr[15:0] w reset00000000 00000000 figure 22-24. fccu xtmr register (fccu_xtmr) table 22-24. fccu_xtmr field descriptions field description xtmr alarm/watchdog/safe request timer the current timer value is meas ured in ircosc clock cycles. these bits can be read by the software. offset: 0x0ec access: user read 0123456789101112131415 r vl3 fs3 0 0 mcs3 vl2 fs2 0 0 mcs2 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r vl1 fs1 0 0 mcs1 vl0 fs0 0 0 mcs0 w reset00000000 00000000 figure 22-25. fccu mcs register (fccu_mcs) table 22-25. fccu_mcs field descriptions field description vlx valid it indicates that the correspondent mcsx and fsx fields are valid. 0: mcsx, fsx fields are not significative 1: mcsx, fsx fields are significative these bits can be read by the software.
fault collection and control unit (fccu) freescale semiconductor 22-29 pxs20 microcontroller reference manual, rev. 1 22.7 functional description 22.7.1 definitions in general, the following definitions ar e applicable for the fault management: ? hw recoverable fault: the fault i ndication is a level sens itive signal that is asserted as long as the fault cause has not been removed. typically the faul t signal is latched in a external module at the fccu. the fccu state tr ansitions are consequently executed on the state changes of the input fault signal. no sw intervention in the fccu is required to recover the fault condition. ? sw recoverable fault: th e fault indication is a si gnal asserted without a de fined time duration. the fault signal is captured in the fccu. the fault recovery is executed following a sw recovery procedure (status/flag register clearing). the following type of reset are applicable (see chapter 41, reset generation module (mc_rgm) ): ? ?destructive? reset: any type of reset related to a power failure condition that implies a complete system reinitialization ? long ?functional? reset: it implies the flash memory and digital circ uitry (most of it with some exceptions fccu, stcu) initialization ? short functional reset: it impl ies the digital circuitry (most of it with some exceptions fccu, stcu) initialization. 22.7.2 fsm description the fccu functionality is depicted by the fsm diagram given in figure 22-26 . basically four states are identi fied with the following meaning: ? config: the configuration state is used only to modify the default confi guration of the fccu. a sub-set of the fccu registers, dedicated to define the fccu c onfiguration (globa l configuration, reactions to fault, time-out, non- critical fault masking) can be a ccessed in write mode only in the config state. fsx fault status it indicates that the correspondent mcsx field has been captured when the fccu is in fault state. 0: mcsx field captured in any stat e different from the fault state 1: mcsx field captured in fault state these bits can be read by the software. mcsx chip mode the mcsx is the chip mode. mcs0 = latest state mcs3 = oldest state on any chip mode change the previous chip modes are shifted (mcs3 = mcs2, mcs2= mcs1, mcs1= mcs0) and the latest one is captured in mcs0. these bits can be read by the software. table 22-25. fccu_mcs field descriptions (continued) field description
fault collection and control unit (fccu) 22-30 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 the config state is accessible onl y from normal state and if th e configuration is not locked. the configuration lock can be disabled only by a global reset of the fccu. the configuration shall always be locked when running a safety critical application. the config to normal state tr ansition can be executed by sw or automatically following a time-out condition of the watchdog. the incoming faults, occurring during the configurat ion phase (config state) are latched in order to process them when the fccu is moved into the normal state, according to the selected configuration. ? normal: the fccu operating state when no faults are occurring. it is also the default state on the reset exit. the fsm will leave the norm al state following one of these events: ? critical faults ? the fccu moves to the fault state ? unmasked non-critical faults with the time-out disabled ? the fccu moves to the fault state ? unmasked non-critical faults with the time-out enabled ? the fccu moves to the alarm state ? masked non-critical faults ? the fccu stays in normal state ? alarm: the fccu moves into th e alarm state when an unmasked non-critical fault occurs and the time-out is enabled. the transition to th e alarm state goes along with an interrupt. by definition, this fault may be recovered within a pr ogrammable time-out period , before it generates a transition to the fault state. the time-out is reinitialized if the fccu state moves to the normal state. the time-out is stopped if the fc cu state moves to the fault state due to a critical-fault occurring when the fccu is in al arm state. the time-out restarts following the recovery from the fault state. ? fault: the fccu moves into the fault state when one of the following condition occurs: ? critical fault ? time-out related to a non-cr itical fault when the fccu is in the alarm state ? unmasked non-critical faults with the time-out disabled ? the transition from normal/alarm st ate goes along with the generation of: ? nmi interrupt ? fccu_f signalling ? safe mode request after a certain amount of time ? sw option: soft reaction (short ?functional? reset) ? sw option: hard reaction (long ?functional? reset)
fault collection and control unit (fccu) freescale semiconductor 22-31 pxs20 microcontroller reference manual, rev. 1 figure 22-26. fccu state diagram 22.7.3 self-checking capabilities the fccu includes some feat ures to support self-check ing capabalities of the ma in fsm in running mode. the fsm unit is duplicated and its state (internal st ate and relevant outputs) is checked by 2 rccx units (cycle accurate). the following checks (per irco sc clock cycle) are provided by the rccux units: ? all the fsm outputs and its internal state for th e redundant fsm instances are checked to detect runtime faults on the fsm out puts and its internal state ? parity bits (computed at byte leve l) on the configuration registers are checked to detect run time faults on the configuration inputs of the fsm ? parity bits (computed at byte level) on the interface used to clear the fccu_cfsx and fccu_ncfsx status registers ? fccu_f protocol state in dual-rail , time-switching and bi-stable mode ? common mode signals (handshake interface signa ls activated only in config state) congruence with the fsm state in case of failure, each rccx unit provides an interrupt request. the rccx state is frozen in a status register. config normal fault alarm configuration exit or timeout configuration entry and not (configuration locked) non-critical fault (masked) reset non-critical fault (unmasked and timeout disabled) or critical fault all fault recovered all non-critical fault recovered non-critical fault (unmasked and timeout enabled) non-critical fault not recovered on time or critical fault or non-critical fault (unmasked and timeout disabled) (critical fault recovered) and (any non-critical fault unrecovered)
fault collection and control unit (fccu) 22-32 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 to guarantee the self checking capabilities through the fa ult interface, each critical fault source must be duplicated on a couple of cf inputs. two separate ircosc clock inputs are routed to the redundant sub-m odules (fsmx, rccx, fccu_fx, fault-if). an external (to the fccu) monitor of the ircosc clocks and an external reaction (?functional? reset to the mc_r gm) is required to cover potenti al fault on the ircosc clocks. self checking capabilities cover the hw reaction of the fccu due to the as sertion of an external fault. the register interface and the handshak e modules are not covered by self-c hecking capabilities. any operation executed by sw (configuration, fa ult recovery) must be cross-ve rified by redundancy checks via sw (registers read following a write/clear ope ration, internal fccu state, and so on). a typical sequence with self checking fa ilure and related r eaction is given in figure 22-27 . figure 22-27. self-checking reaction 22.7.4 reset interface the fccu has two input resets and two ou tput resets related to the fault state. 22.7.5 fault priority scheme and nesting the fault state has a higher priority than the alarm state in case of concurrent fault events (critical and non-critical) that occur in the no rmal state. in case of concurrent critical faults, the fault reaction corresponds to the worst case (that is , a long ?functional? reset is asserted in case it has been programmed). the alarm to fault state transition o ccurs if a critical faul t or a non-critical fa ult (unmasked and with time-out disabled) is asse rted in the alarm state. any critical fault (programme d to react with a hard or soft reaction) that occurs when the fccu is already in the fault state causes an immediate hard or soft reaction (long or s hort ?functional? reset). table 22-26. reset sources reset source support external reset enabled por enabled stcu enabled ?functional? reset disabled ?destructive? reset enabled chip mode fccu sc state rccx interrupt request run ok nok ok sw clear
fault collection and control unit (fccu) freescale semiconductor 22-33 pxs20 microcontroller reference manual, rev. 1 the alarm to normal state transiti on occurs only if all the non-criti cal faults (including the faults that have been collected after the entry in the al arm state) have been clea red (sw or hw recovery) otherwise the fccu will re main in the alarm state. the fault to normal state transition occurs only if all the critical and non- critical faults (including the faults that have been collected after the entry in the fault/alarm state) have been cleared (sw or hw recovery) otherwise the fccu will remain in the fa ult state (if any critical fault is stil l pending) or will return in the alarm state (if any non-critical fa ult is still pending and the time-out is not elapsed). in general, no fault nesting is supported except for th e non-critical versus criti cal faults that causes a alarm to fault state transition. in this case the nct timer is stopped until the fault state is recovered. 22.7.6 fault recovery the following timing diagrams describe the main use cases of the fccu in terms of fault events and related recovery. a typical sequence related to a crit ical fault management, given in figure 22-28 or figure 22-29 , is following described: ? critical fault assertion ? fccu state transition (automatic): normal ? fault ? short ?functional? reset ? nmi assertion ? safe mode request (delayed) ? chip mode transition: run ? reset ? safe ? nmi interrupt management ? fault recovery (by sw): fccu state transition fault ? normal ? chip mode transition: safe ? run
fault collection and control unit (fccu) 22-34 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 22-28. critical fault recovery (a) figure 22-29. critical fault recovery (b) a typical sequence related to a non-critical fault management (alarm state), given in figure 22-30 and figure 22-31 , is following described: ? non-critical fault assertion ? fccu state transition (automatic): normal ? alarm ? alarm interrupt request fccu reset critical fault event chip mode fccu state short ?functional? safe mode request nmi fccu_f reset run safe run normal fault normal idle error on idle sw fault recovery delay reset request fccu reset critical fault event chip mode fccu state short ?functional? safe mode request nmi fccu_f reset run safe run normal fault normal idle error on idle delay reset request
fault collection and control unit (fccu) freescale semiconductor 22-35 pxs20 microcontroller reference manual, rev. 1 ? time-out running ? chip mode: run ? alarm interrupt management ? fault recovery (by sw): fccu state transition alarm ? normal figure 22-30. non-critical fault (alarm state) recovery (a) figure 22-31. non-critical fault (alarm state) recovery (b) a typical sequence related to a non- critical fault management (alarm ? fault state), given in figure 22-32 , is following described: ? non-critical fault assertion ? fccu state transition (automatic): normal ? alarm ? alarm interrupt request ? time-out running ? fccu state transition (following the time-out trigger): alarm ? fault ? nmi assertion fccu reset non-critical fault event chip mode fccu state alarm interrupt ncf timer run normal alarm normal idle timer on idle sw alarm recovery request fccu reset non-critical fault event chip mode fccu state alarm interrupt ncf timer run normal alarm normal idle timer on idle request
fault collection and control unit (fccu) 22-36 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? safe mode request (delayed) ? chip mode transition: run ? safe ? nmi interrupt management ? fault recovery (by sw): fccu state transition fault ? normal ? system state transition: safe ? run figure 22-32. non-critical fault (alarm -> fault state) recovery a typical sequence related to a critical fa ult (with nesting) ma nagement, given in figure 22-33 , is following described: ? critical fault asser tion (no short or l ong ?functional? reset) ? fccu state transition (automatic): normal ? fault ? nmi assertion ? safe mode request (delayed) ? chip mode state transition: run ? safe ? critical fault assertion ? short ?functional? reset ? chip mode transition: safe ? reset ? nmi interrupt management ? fault recovery (by sw): fccu state transition fault ? normal non-critical fault event fccu reset chip mode fccu state alarm interrupt short or long ?functional? safe mode request fccu_f ncf timer reset request nmi run safe run normal alarm fault normal idle timer on timeout idle idle error on idle sw fault recovery request
fault collection and control unit (fccu) freescale semiconductor 22-37 pxs20 microcontroller reference manual, rev. 1 ? system state transition: safe ? run figure 22-33. critical fault (nesting) recovery a typical sequence related to a critical fault (with non-critical fault nesting) management (alarm ? fault ? alarm state), given in figure 22-34 , where the faults are recovered sequentially, is following described: ? non-critical fault assertion ? fccu state transition (automatic): normal ? alarm ? alarm interrupt request ? time-out running ? critical fault assertion ? fccu state transition (automatic): alarm ? fault ? nmi assertion ? safe mode request ? chip mode transition: run ? safe ? nmi interrupt management ? fault (cf) recovery (by sw): fccu state transition fault ? alarm, because only the critical fault has been recovered ? chip mode transition: safe ? run ? time-out is still running ? alarm interrupt management critical fault event (no fccu reset critical fault event chip mode fccu state short ?functional? safe mode request nmi fccu_f run safe reset safe run normal fault normal idle error on idle sw fault recovery delay short or long ?functional? reset) reset request
fault collection and control unit (fccu) 22-38 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? fault (ncf) recovery (by sw): fccu state transition alarm ? normal figure 22-34. critical fault (and non- critical fault nesting) recovery 22.7.7 wkup/nmi interface the nmi signal internally generated by fccu is masked when: ? fccu asynchronous reset ? chip mode = reset and un-masked when: ? a sw change request of th e chip mode is triggered the logical scheme is given in figure 22-35 . fccu reset critical fault event non-critical fault event chip mode fccu state alarm interrupt safe mode request nmi fccu_f ncf timer short or long ?functional? reset request run safe run sw ncf recovery sw cf recovery normal alarm fault alarm normal idle timer on idle idle error on idle request
fault collection and control unit (fccu) freescale semiconductor 22-39 pxs20 microcontroller reference manual, rev. 1 figure 22-35. nmi/wkup scheme 22.7.8 stcu interface the stcu interface includes: ? a set of signals resulting from the self-check ing procedure connected externally at the fccu critical/non-critical faults. the stcu fault signals are processed by the fccu when the chip is re-booted following the self testi ng procedure. the stcu includes also a status register that stores the self-testing results (flags). ? a mask that inhibits the fccu_f dummy signa ling until the stcu self-checking procedure has been completed. ? during the self testing procedure, depending on the stcu results, 3 cases are applicable: ? stcu completes the self testing procedure su ccessfully. the chip re-boots and the fccu is responsible to provide a reaction. (see figure 22-36 .) ? stcu completes the self testing procedure with low severity fail ures. the fccu is responsible to provide the proper reactions acco rding to the fault occurred. (see figure 22-37 .) ? stcu completes the self testing procedure with serious failures. the f ccu or other critical parts of the chip could not be able to pr ovide the proper reaction. stcu should keep permanently the chip in reset state. this feature is optionally programmable inside the stcu. (see figure 22-38 .) rsynch system clock internally- fsm unit ircosc clock nmi mask nmi to cores nmi from wkpu wake-up request to wkpu generated nmi note: all nmi signals are shown active-low.
fault collection and control unit (fccu) 22-40 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 22-36. st cu-fccu (case a) figure 22-37. stcu-fccu (case b) figure 22-38. st cu-fccu (case c) for details related to the stcu refer to [3]. 22.7.9 nvm interface the nvm provides the fccu with the ini tial configuration in formation shown in table 22-27 . table 22-27. nvm configuration flash memory option bit locations description biu4[20] initial fccu_cfg.cm value biu4[21] initial fccu_cfg.sm value biu4[22] initial fccu_cfg.ps value biu4[23:25] initial fccu_cfg.fom value biu4[26:31] initial fccu_cfg.fop value reset unknown reset run end (good) run reset fault good normal reset unknown chip mode stcu state stcu flags fccu state (to fccu) reset unknown reset run end (failure) run reset fault fault normal reset unknown chip mode stcu state stcu flags fccu state (to fccu) fault/alarm reset unknown reset end (serious failure) run reset fault fault normal reset unknown chip mode stcu state stcu flags fccu state (to fccu)
fault collection and control unit (fccu) freescale semiconductor 22-41 pxs20 microcontroller reference manual, rev. 1 figure 22-39 shows the fccu configurati on sequence after a power-on, ?des tructive?, or external reset. figure 22-39. nvm interface 22.7.10 fccu_f interface the fccu provides 2 external bidi rectional signals (fccu_f interf ace). different protocols for the fccu_f interface are supported, selecti ng the fccu_cfg.fom register field: ? dual rail protocol ? time switching protocol ? bi-stable protocol ? test mode the signal polarity and the frequency can be programmed, setting the fccu_cfg.ps and fccu_cfg.fop register fields. all the diagrams a nd tables are related to the default configuration selection (fccu_cfg.fop = 0b), switching m ode (fccu_cfg.sm = 0b) and config mode (fccu_cfg.cm = 0b). in cas e of inverted polarity (f ccu_cfg.fop = 1b) all th e values on the fccu_f output pins are inverted. 2 modes can be programmed to define the fccu_f pr otocol transitions in dua l-rail or time-switching mode: ? slow switching mode: no fccu _f frequency violation duri ng the fccu state transition (normal to error or viceversa and config to normal). the fccu_f protocol transition occurs after a max delay equal to the duration of the semi-period of the fccu_f frequency. ? fast switching mode: the fccu _f protocol transition (norma l to error or viceversa and config to normal) occurs i mmediately. a pulse with the minimum duration corresponding to 16 mhz / 1024 (ircosc clock) period can occurs in fast switching mode. it implies a frequency violation of the fccu_f protocol. prot2 reset fccu configuration fccu _cfg.ps, fccu state stcu state power-on, ?destructive?, external, or self-test fccu_cfg.fom, fccu_cfg.fop fccu_f[1:0] (from fccu) fccu_f[1:0] (top) prot1 config default (reset value) default (reset value) config normal config normal reset normal reset stdby init self-checking idle (running) xxx (stcu running) xxx (stcu running) high-z (reset) high-z high-z (stcu control) high-z (mc control) phase1 phase2 phase3 phase1 phase2 phase3 run asynch asynch reset self test completed reset from nvm prot2
fault collection and control unit (fccu) 22-42 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 two modes, depending on the fccu_c fg.cm bit setting, can be progra mmed to define the fccu_f protocol in config state: ? configuration labelling: the config stat e is marked by a spec ific fccu_f setting ? configuration transparency: the conf ig and normal state are equivalent the fccu_f frequency is programmable based on the ircosc clock frequency divided by a fixed prescaler (1024). the external monitor of the fccu_f protocol s hould oversample the fccu_f signals in order to synchronize periodically the external clock (used by the monitor) and the i rcosc clock detecting the edge transition of the fccu_f protocol in dual-rail or time-switching mode. note the initial values, after the reset phase, of the fccu_cfg.cm, fccu_cfg.sm, fccu_cfg.ps, fccu_cfg.fop, fccu_cfg.fom registers are set by th e nvm interface (see section 22.7.9, nvm interface ). 22.7.10.1 dual-rail protocol dual-rail encoding is an alternate method for encodi ng bits. in contrast with classical encoding, where each signal carries a single-bit value, dual-rail enc oded circuits use two wires to carry each bit. the encoding scheme is given in table 22-28 and the related timing diagram is given in figure 22-40 and figure 22-41 . as long as fccu is in normal or alarm state, out put will show ?no-faulty?signal. output pins fccu_f[0] and fccu_f[1] will toggle between 01 and 10 with a given frequency. by default the frequency is the ircosc clock frequency divided by 18*1024. during the reset phase and during self testing the output pins are set as ?high impedance?. note figure 22-40 and figure 22-41 are formatted to display the behavior in all four phases (reset, normal, error, and config), not to imply transitions between one phase to another. in part icular, transition from error phase to config phase is not possible. table 22-28. dual-rail encoding logical state dual-rail encoding (output pins fccu_f[1:0]) note non-faulty 10 toggling non-faulty 01 faulty 00 toggling faulty 11 reset high-z no toggling configuration high-z when fccu_cfg.cm = 0 = non-faulty when fccu_cfg.cm = 1
fault collection and control unit (fccu) freescale semiconductor 22-43 pxs20 microcontroller reference manual, rev. 1 figure 22-40. dual-rail protocol (slow switching mode) figure 22-41. dual-rail protocol (fast switching mode) 22.7.10.2 time switching protocol the encoding scheme is given in table 22-29 and the related timing diagram is given in figure 22-42 . table 22-29. time switching encoding logical state time switching encoding (output pins fccu_f[1:0]) note non-faulty 10 toggling non-faulty 01 faulty 10 no toggling reset high-z no toggling configuration 01 when fccu_cfg.cm = 0 = non-faulty when fccu_cfg.cm = 1 fccu_f[0] fccu_f[1] reset phase normal phase error phase config phase input output high-z or self-test or high-z fccu_f[0] fccu_f[1] reset phase normal phase error phase config phase input output high-z or self-test or high-z
fault collection and control unit (fccu) 22-44 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 as long as fccu is in normal or alarm state, out puts will show ?non-faulty ? signal. output pins #0, #1 will toggle between ?01? and ?10? with a given frequency. by default the frequency is the ircosc clock frequency divided by 18*1024. in the fault state, the output pin fccu_f[0] is set as low. in time switching mode the second output (fccu_ f[1]) is the inverted signal of first output (fccu_f[0]). values 00 on the outputs indicate a fault in the er ror out protocol itself . this state must be considered as critical fault, because no reliab le error out indication is available any more. in the reset phase the output pins are set as ?high impedance?. note figure 22-42 is formatted to display the beha vior in all four phases (reset, normal, error, and config), not to im ply transitions between one phase to another. in particular, transition from error phase to config phase is not possible. figure 22-42. time-switching protocol 22.7.10.3 bi-stable protocol the encoding scheme is given in table 22-30 and the related timing diagram is given in figure 22-43 . table 22-30. bi-stable encoding logical state bi-stable encoding (output pins fccu_f[1:0]) note non-faulty 01 no toggling faulty 10 no toggling reset high-z no toggling configuration 10 when fccu_cfg.cm = 0 = non-faulty when fccu_cfg.cm = 1 fccu_f[0] fccu_f[1] reset phase normal phase error phase config phase input output or self-test or high-z
fault collection and control unit (fccu) freescale semiconductor 22-45 pxs20 microcontroller reference manual, rev. 1 in the fault state, the faulty logical state is indi cated. in normal or alarm state, ?no-faulty? state is indicated. in bi-stable mode the second output (fccu_f[1]) is th e inverted signal of first output (fccu_f[0]). in the reset phase the output pins are set as ?high impedance?. note figure 22-43 is formatted to display the beha vior in all four phases (reset, normal, error, and config), not to im ply transitions between one phase to another. in particular, transition from error phase to config phase is not possible. figure 22-43. bi-stable protocol 22.7.11 fault mapping table 22-31 and table 22-32 show the source of the fa ult signals and the type of fault input these signals are connected to at the fccu. table 22-31. fccu mapping of critical faults critical fault source signal description short / long / none default func reset set / clear injection nmi safe mode request cf[0] rccuo[0] cores out of lock long yes yes yes cf[1] rccu1[0] cores out of lock long yes yes yes cf[2] rccuo[1] dma_muxes out of lock long yes yes yes cf[3] rccu1[1] dma_muxes out of lock long yes yes yes cf[4] rccuo[2] pbridges out of lock long yes yes yes cf[5] rccu1[2] pbridges out of lock long yes yes yes fccu_f[0] fccu_f[1] reset phase normal phase error phase config phase input output or self-test or high-z
fault collection and control unit (fccu) 22-46 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 cf[6] rccuo[3] xbars out of lock long yes yes yes cf[7] rccu1[3] xbars out of lock long yes yes yes cf[8] rccuo[4] sram arrays out of lock long yes yes yes cf[9] rccu1[4] sram arrays out of lock long yes yes yes note: cf[0] and cf[9] donot run in dp mode cf[10] rccuo[5] pflashc out of lock (run in dp mode) long yes yes yes cf[11] rccu1[5] pflashc out of lock (run in dp mode) long yes yes yes cf[12] ? ? ? no no no cf[13] ? ? ? no no no cf[14] swt_0 software watchdog timer long no yes yes cf[15] swt_1 software watchdog timer long no yes yes cf[16] ecsm_nce_0 flash/sram ecc not correctable error long no yes yes cf[17] ecsm_nce_1 flash/sram ecc not correctable error long no yes yes cf[18] adc_cf_0 internal self test (critical fault) ? yes (by adc itself) ye s ye s cf[19] adc_cf_1 internal self test (critical fault) ? yes (by adc itself) ye s ye s cf[20] stcu bist results (critical faults) ? yes yes yes cf[21] lvd_hvd_ 1.2v lvd/hv d bist failure result in test mode ? yes yes yes cf[22] sscm_xfer_e rr sscm transfer error (during the stcu config loading) ?noyesyes cf[23] lsm_dpm_err 0 lsm <-> dpm runtime switch long yes yes yes cf[24] lsm_dpm_err 1 lsm <-> dpm runtime switch long yes yes yes cf[25] ? ? ? no no no cf[26] ? ? ? no no no table 22-31. fccu mapping of critical faults (continued) critical fault source signal description short / long / none default func reset set / clear injection nmi safe mode request
fault collection and control unit (fccu) freescale semiconductor 22-47 pxs20 microcontroller reference manual, rev. 1 cf[27] stcu stcu fault condition (run in application mode) long no yes yes cf[28] dft0 combination of safety critical signals from test control unit (tcu) long no yes yes cf[29] dft1 combination of safety critical signals from test control unit (tcu) long no yes yes cf[30] dft2 combination of safety critical signals from test control unit (tcu) long no yes yes cf[31] dft3 combination of safety critical signals from test control unit (tcu) long no yes yes cf[37] jtag/nexus combination of safety critical signals from jtag and nexus long no yes yes table 22-32. fccu mapping of non-critical faults non-critical fault source signal description short / long / none default func reset set / clear injection fault enabled time-out enabled ncf[0] core_0 watchdog p_wrs_core0[0] long no yes yes ncf[1] core_1 watchdog p_wrs_core1[0] long no yes yes ncf[2] fm_pll_0 loss of lock long no yes yes ncf[3] fm_pll_1 loss of lock long no yes yes ncf[4] cmu_0 loss of xosc clock long no yes yes ncf[5] cmu_0 sysclk frequency out of range long no yes yes ncf[6] cmu_1 motc_clk frequency out of range long no yes yes ncf[7] cmu_2 frpe_clk frequency out of range long no yes yes ncf[8] ecsm_ecn_0 ecc 1-bit error correction notification ?nonoyes ncf[9] ecsm_ecn_1 ecc 1-bit error correction notification ?nonoyes ncf[10] adc_ncf_0 internal se lf test (non critical fault) ?yes (by adc itself) ye s ye s table 22-31. fccu mapping of critical faults (continued) critical fault source signal description short / long / none default func reset set / clear injection nmi safe mode request
fault collection and control unit (fccu) 22-48 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ncf[11] adc_ncf_1 internal se lf test (non critical fault) ?yes (by adc itself) ye s ye s ncf[12] stcu_ncf bist results (non critical faults) ? yes yes yes ncf[13] lvd_ 1.2v lvd bist ok in test mode/ lvd nok in user mode ?yesyesyes ncf[14] hvd_ 1.2v hvd bist ok in test mode/ hvd nok in user mode ?yesyesyes ncf[15] lvd vreg lvd vreg fault detected by self-checking. (refer ta b l e 3 9 - 2 for further clarifications) ?yesyesyes ncf[16] lvd flash lvd flash fault detected by self-checking (refer ta b l e 3 9 - 2 for further clarifications) ?yesyesyes ncf[17] lvd io lvd io fault detected by self-checking (refer ta b l e 3 9 - 2 for further clarifications) ?yesyesyes ncf[18] ? ? ? no no no ncf[19] flexr_ecn ecc 1-bit error correction notification from flexray ?nonoyes ncf[20] flexr_nce ecc not correctable error from flexray(combination of lram and dram ecc errors) ?noyesyes ncf[21] mc_me software device reset ? no no yes ncf[22] bp_ballast0 1 bypass ballast0 ? no yes yes ncf[23] bp_ballast1 1 bypass ballast1 ? no yes yes ncf[24] bp_ballast2 1 bypass ballast2 ? no yes yes ncf[25] ? ? ? no no no ncf[26] ? ? ? no no no ncf[27] ? ? ? no no no ncf[28] ? ? ? no no no ncf[29] ? ? ? no no no ncf[30] ? ? ? no no no ncf[31] ? ? ? no no no table 22-32. fccu mapping of non-critical faults (continued) non-critical fault source signal description short / long / none default func reset set / clear injection fault enabled time-out enabled
fault collection and control unit (fccu) freescale semiconductor 22-49 pxs20 microcontroller reference manual, rev. 1 notes: 1 if one of these non-critical faults is tr iggered, ballast is no more available to supply the device and device enters "non-customer" test mode.
fault collection and control unit (fccu) 22-50 freescale semiconductor pxs20 microcontroller reference manual, rev. 1
flash memory freescale semiconductor 23-1 pxs20 microcontroller reference manual, rev. 1 chapter 23 flash memory 23.1 flash memory block (c90fl) 23.1.1 c90fl block overview the primary function of the c90fl flash memory block is to serve as electrically programmable and erasable non-volatile memory (nvm). the nvm can be used for instruction a nd/or data storage. the block is a non-volatile solid- state silicon memory device consisting of blocks of single-transistor storage elements, an electrical means for se lectively adding (progr amming) and removing (erasing) charge from these elements, and a means of selectively sensing (r eading) the charge stored in these elements. the c90fl is addressable by word (32 bits) and page (128 bits). the c90fl block is arranged as tw o functional units. the fi rst functional unit is the c90fl flash core (fc). the fc is composed of arra yed non-volatile storage el ements, sense amplifiers, row selects, column selects and charge pumps. the arrayed storage elements in the fc are subdivided into physically separate units referred to as blocks. the second functional unit of the c90f l is the memory interface (mi). th e mi contains th e registers and logic which control the operation of th e fc. the mi is also the interfac e to the pflash bus interface unit (pflash_c90fl). the pflash_c90fl interfaces the system bus on this device to the c90fl memory block. the pflash biu is described in section 23.2, dual-ported platform fl ash memory controller (pflash2p) . the base address for the flash bus and flash registers is 0xc3f8_8000. there are three address spaces: ? low address space (256 kb) ? mid address space (256 kb) ? high address space (512 kb) for block configurations overview see figure 23-1 .
flash memory 23-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 23-1. c90fl flash memory array diagram 23.1.2 c90fl block features ? support for a 64-bit data bus for instruction fetch ? support for a 32-bit data bus for cpu loads and dma access. byte, halfword, word and doubleword reads are supported. only aligned word and doubleword wr ites are supported. ? configurable read buffering and line prefetch support. four line re ad buffers (128 bits wide) and a prefetch controller are used to support single-cy cle read responses for hits in the buffers. ? hardware and software configur able read and write access prot ections on a per-master basis ? interface to the flash array c ontroller is pipelined with a dept h of 1, allowing overlapped accesses to proceed in parallel for interlea ved or pipelined flash array designs ? configurable access timing allowing use in a wide range of system frequencies ? multiple-mapping support and mapping-based bl ock access timing (0-31 additional cycles) allowing use for emulati on of other memory types ? software programmable block progr am/erase restriction control for low, mid and high address spaces ? erase of selected block(s) ? read page and program page size of 128 bits (4 words) ? ecc with single-bit corr ection, double-bit detection low address space high address space mid address space c90fl flash memory array blocks low address space - 256 kb mid address space - 256 kb high address space - 512 kb 16 kb 48 kb 48 kb 16 kb 64 kb 64 kb 128 kb 128 kb 256 kb 256 kb
flash memory freescale semiconductor 23-3 pxs20 microcontroller reference manual, rev. 1 ? minimum program size is 2 c onsecutive 32-bit words, aligned on a 0-modulo-8 byte address, due to ecc ? embedded hardware program and erase algorithm ? read while write with multiple partitions ? erase suspend, program suspe nd and erase-suspended program ? automotive c90fl which meets automotive endurance and reliability requirements ? shadow information stored in non-volatile shadow block ? independent program/erase of the shadow block 23.1.3 c90fl modes of operation 23.1.3.1 c90fl user mode user mode is the default operating mode of the c90f l module. in this mode, it is possible to read and write, program and er ase the c90fl module. 23.1.3.2 stop mode in stop mode, all dc current sour ces in the c90fl are disabled. 23.1.4 c90fl block diagram figure 23-2 shows a block diagram of the c90fl flash memory block. figure 23-2. c90fl flash memory system block diagram 23.1.5 c90fl flash memory functi onal description (user mode) in user mode the c90fl m odule can be read and writte n (register writes and inte rlock writes), programmed or erased. the following subsections define all actions that can be performed in user mode. c90fl memory interface (mi) c90fl flash core (fc) system c90fl memory block (pflash2p) control/status registers periphera bus bus pxs20
flash memory 23-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 23.1.5.1 c90fl read and write the default state of the c90fl modul e is read. the main and shadow address space can be read only in the read state. the module configur ation register (mcr) is always available for read. the c90fl module enters the read state on reset. the c90fl module is in the read state under four sets of conditions: ? the read state is active when pgm=1 or ers=1 in the mcr (read while write) note reads done to the partition(s) be ing operated on (either erased or programmed) will result in an error and the rwe bit in the mcr will be set. ? the read state is active when pgm=1 a nd psus=1 in the mcr. (program suspend) ? the read state is active when ers=1 and es us=1 and pgm=0 in the mcr. (erase suspend) note fc reads are done through the biu. in many cases the biu will do ?page buffering? to allow sequential reads to be done with higher performance. this can create a data cohe rency issue that must be handled with software. data coherency can be an issue after a program or erase operation, as well as shadow row operations. in c90fl user mode, registers can be written. array can be wr itten to do interlock writes. reads attempted to invalid locations will result in indeterminate data. inva lid locations occur when addressing is done to blocks that do not exist in non 2 n array sizes. interlock writes attempted to invalid locations (due to bloc ks that do not exist in non 2 n array sizes), will result in an interlock occurring, but attempts to program or erase these bl ocks will not occur since they are forced to be locked. 23.1.5.2 read while write (rww) the flash core is divided into part itions. partitions always comprise two or more blocks. partitions are used to determine read while wr ite (rww) groupings. while a write (p rogram or erase) is being done within a given partition, a read can be simultaneously executed to any ot her partition. partitions are listed in table 23-1 . note that the shadow block has unique r ead while write restrictions described in section 23.1.5.8, c90fl shadow block . the fc is also divided into blocks to implement independent erase or progr am protection. the shadow block exists outside the normal address space and is programmed, erased and read independently of the other blocks. the shadow block is included to support systems that requi re nvm for security or system initialization information. a software mechanism is provided to independently lock or unlock each block in high, mid, and low address space against program and erase. in addition, two hardware locks are provided to enable/disable the fc for program/erase. see section 23.1.5.4, software locking , for more information.
flash memory freescale semiconductor 23-5 pxs20 microcontroller reference manual, rev. 1 23.1.5.3 c90fl program a flash program sequence operates on any page within the fc. up to 4 words within the page may be altered in a single program operati on. whenever the array is program, the ecc bits also get programmed. ecc is handled on a 64 bit boundary. thus, if onl y 1 word in any given 64 bit ecc segment is programmed, the adjoining word (in that segment) should not be pr ogrammed since ec c calculation has already completed for that 64-bit segment. attempts to program the adjoining word results in an operation failure (most likely). it is recomm ended that all programming operations be from 64 bits to 128 bits, and be 64 bit aligned. the programming operation should co mpletely fill selected ecc segments within the page. only one program is allowed pe r 64 bit ecc segment between erases. caution the chosen ecc algorithm allows some bit manipulations so that a double word can be re-written seve ral times without needing an erase of the sector. this allows to use a double word to store flags useful for the eeprom emulation. as an example the chosen ecc algorithm allows to start from an all ?1?s double word value and re write whichever of its four 16-bit half-words to an all ?0?s content by keeping the same ecc value. programming changes the value stored in an array b it from logic 1 to logic 0 only. programming cannot change a stored logic 0 to a logic 1. note if a logic 0 is attempted to be ?over programmed? by a logic 1, the resulting operation will fail (mcr[pe g] = 0), and the 0?s that are interlocked will be merged (ored) with 0?s that are alr eady present in the 64 bit ecc segment. addresses in locked/disabled blocks cannot be progra mmed. the user may program the values in any or all of 4 words, within a page, with a single progr am sequence. page-bound words have addresses which differ only in address bits [3:2]. the program opera tion consists of the following sequence of events: 1. change the value in the mcr[pgm] bit from a 0 to a 1. note ensure the block that contains the address to be programmed is unlocked. 2. write the first address to be programmed with th e program data. the flash module latches address bits [20:4] and chip-specific sha dow enable at this time. the flas h module latches data written as well. this write is referr ed to as a program data interlock write. an interlock write may be as large as 64 bits, and as small as 32 bits. 3. if more than 1 word or double word is to be programmed, write eac h additional address in the page with data to be programmed. this is referred to as a program data write. the flash module ignores address bits [20:4] and chip-spe cific shadow enable for program data writes. all unwritten data words default to 0xffff ffff. 4. write a logic 1 to the mcr[ehv] bit to start the internal program sequence or skip to step to terminate. 5. wait until the mcr[done] bit goes high. 6. confirm mcr[peg] = 1.
flash memory 23-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 7. write a logic 0 to the mcr[ehv] bit. 8. if more addresses are to be programmed, return to step 2. 9. write a logic 0 to the mcr[pgm] bi t to terminate the program sequence. the first write after a program is initiated determines the page addr ess to be programmed. program may be initiated with the 0 to 1 transition of the mcr[ pgm] bit or by clearing the mcr[ehv] bit at the end of a previous program. this first writ e is referred to as an interlock write. the interlock write determines if the shadow or normal array space is to be pr ogrammed by sampling chip-specific shadow enable and causing mcr[peas] to be set/cleared. in the case of an erase-suspende d program, the values in mcr[peas] may be modified via the program interlock write, enabling erase-suspende d programs to and from shadow space. an interlock write must be perfor med before setting ehv. the user may terminate a pr ogram sequence by clearing mcr[pgm] prior to setting mcr[ehv]. after the interlock write, additiona l writes only affect the data to be programmed at the word location determined by address bits [3:2]. unwritten locations default to a data value of 0xffff_ffff. if multiple writes are done to the same lo cation the data for the last write is used in programming. while done is low, ehv is high and psus is low the user may clear ehv, result ing in a program abort. a program abort forces the module to step 8 of the program sequenc e. an aborted program results in peg being set low, indicating a failed operation. the data space being operated on before the abort contains indeterminate data. the user may not abort a program sequence while in program suspend. caution aborting a program operation leaves the fc addresses being programmed in an indeterminate data state. this may be recovered by executing an erase on the affected blocks. 23.1.5.4 software locking a software mechanism is provided to independently lock/unlock each high, mi d, and low address space against program and erase. software locking is done through th e lbl (low/mid addres s space block lock) or hbl (high address space block lock) registers. these can be written thro ugh register writes, and can be read through register reads. 23.1.5.5 c90fl program suspend/resume the program sequence may be suspende d to allow read access to the fc. it is not possibl e to erase during a program suspend, or program during a program suspend. read while write may also be used to read the array during a program sequence providin g the read is to a different partition. a program suspend can be initiated by changing th e value of the mcr[psus] bit from a 0 to a 1. mcr[psus] can be set high at any time when mcr[pgm] and mcr[e hv] are high. a 0 to 1 transition of mcr[psus] causes the flash module to start the sequence to enter program suspend, which is a read state. the user must wait until mcr[done] = 1 before the module is suspended. at this time fc reads
flash memory freescale semiconductor 23-7 pxs20 microcontroller reference manual, rev. 1 may be attempted. mcr[done] goes high no more th an tpsus after mcr[psus] is set to a 1. once suspended, the fc may only be read. reads to the bloc k(s) being programmed/era sed return indeterminate data. the program sequence is resumed by writing a logic 0 to mcr[psus]. mcr[ehv] must be set to a 1 before clearing mcr[psus] to resume operation. when the operation resumes, the flash module continues the program sequen ce from one of a set of predefined points. this may extend the time required for the program operation. caution repeated suspends at a high frequenc y may result in the operation timing out, and the flash module will respond by completing the operation with a fail code (mcr[peg] = 0) . the minimum time between suspends to ensure this does not occur is 100 ? s. 23.1.5.6 c90fl erase erase changes the value stored in all bits of the selected bl ock(s) to logic 1. an erase sequence operates on any combination of blocks in the low, mid or high address space, or the shadow block. the erase sequence is fully automated within the flash. the user only needs to select the blocks to be erased and initiate the erase sequence. locked/disabled blocks ca nnot be erased. if multiple blocks are selected for erase during an erase sequence, the blocks are erased sequentially star ting with the lowest numbered block and terminating with the highest. the erase sequenc e consists of the following sequence of events: 1. change the value in the mc r[ers] bit from 0 to a 1. 2. select the block, or blocks to be erased by writing ones to the a ppropriate registers in lms or hbs registers. if the shadow block is to be erased, this step ma y be skipped, and lms and hbs are ignored. for shadow block erase, see section 23.1.5.8, c90fl shadow block , for more information. note lock and select are independent. if a block is selected and locked, no erase occurs. 3. write to any address in flash. th is is referred to as an erase interlock write. the interlock write causes the values of soc specific shadow enable to be captured and causing mcr[peas] to be set/cleared. 4. write a logic 1 to the mcr[ehv] bit to start an internal erase sequence or skip to step 9 to terminate. 5. wait until the mcr[done] bit goes high. 6. confirm mcr[peg] = 1. 7. write a logic 0 to the mcr[ehv] bit. 8. if more blocks are to be erased, return to step 2. 9. write a logic 0 to the mcr[ers] bit to terminate the erase. after setting ers, one write, referred to as an inte rlock write, must be perfor med before ehv can be set to a 1. this interlock causes the values of soc specifi c shadow enable to be ca ptured. data words written
flash memory 23-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 during erase sequence interlock writ es are ignored. the user may ter minate the erase sequence by clearing ers before setting ehv. an erase operation may be aborted by clearing ehv assuming done is low, ehv is high and esus is low. an erase abort forces the module to step 8 of the erase sequence. an abor ted erase results in peg being set low, indicating a failed operation. the block(s) being operated on before the abort contain indeterminate data. the user may not abort an erase sequence while in erase suspend. caution aborting an erase operation leaves th e fc blocks being erased in an indeterminate data state. this may be recovered by executing an erase on the affected blocks. 23.1.5.7 c90fl erase suspend/resume the erase sequence may be suspended to allow read access to the fc. the erase sequence may also be suspended to program (erase-suspe nded program) the fc. a program started during erase suspend can in turn be suspended. only one eras e suspend and one program suspend are allowed at a time during an operation. it is not possible to eras e during an erase suspend, or prog ram during a program suspend. during suspend, all reads to fc locations targeted for program and blocks targeted for erase return indeterminate data. programming locations in blocks targeted for erase during erase- suspended program may result in corrupted data. read while write may also be used to read the array during an erase sequence providing the read is to a partiti on not selected for erase. an erase suspend can be initiated by changing th e value of the mcr[esus] bit from a 0 to a 1. mcr[esus] can be set to a 1 at any time when mcr[er s] and mcr[ehv] are high and mcr[pgm] is low. a 0 to 1 transition of mcr[esus] causes the m odule to start the sequence which places it in erase suspend. the user must wa it until mcr[done] = 1 before the modul e is suspended and further actions are attempted. mcr[done] goes high no more than tesus afte r mcr[esus] is set to a 1. once suspended, the array may be read or a program se quence may be initiated (e rase-suspended program). before initiating a program sequence the user must first clear mcr[ehv]. if a program sequence is initiated the values of soc specific shadow enable is recaptured. once the erase-suspended program is completed, the value of peas is returned to its ?e rase? value. fc reads while mcr[esus] = 1 from the block(s) being erased re turn indeterminate data. the erase sequence is resumed by wr iting a logic 0 to mcr[esus]. mc r[ehv] must be set to a 1 and mcr[pgm] must be cleared (in the event of an erase suspended program) before mcr[esus] can be cleared to resume the operation. the module continues the erase sequence fr om one of a set of predefined points. this may extend the time required for the erase operation. caution repeated suspends at a high frequenc y may result in the operation timing out, and the flash module will respond by completing the operation with a fail code (mcr[peg] = 0) . the minimum time between erase suspends to ensure this does not occur is 200 ? s.
flash memory freescale semiconductor 23-9 pxs20 microcontroller reference manual, rev. 1 caution in an erase-suspended program, program ming fc locations in blocks which were being operated on in th e erase may corrupt fc data. 23.1.5.8 c90fl shadow block the c90fl shadow block is a memo ry-mapped block in the c90fl me mory map. program and erase of the shadow block are enabled only when peas=1 in the mcr. once the user has begun an erase operation on the shadow block, it cannot be suspended to program the main address space and vice-versa. the user must terminate the shadow erase operation to program or erase the main address space. the shadow block can not utilize the rww feature. on ce an operation is started in the shadow block, a read can not be done to the shadow block, or any ot her block. likewise, once an operation is started in a block in low/mid/high addres s space, a read can not be done in the shadow block. the shadow block contains information on how the lock registers are reset. the first and second words can be used for reset configuration words. all other word s can be used for user defined functions or other configuration words. 23.1.5.9 c90fl reset a reset is the highest priority operation for the c90fl and terminates all other operations. the c90fl uses reset to initialize register and status bits to their default reset values. if the c90fl is executing a program or erase operation and a reset is issued, the operati on will be aborted and the c90fl will disable the high voltage logic without damage to the high voltage circuits. re set aborts all operations and forces the c90fl into user mode ready to receive accesses. after reset is negated, register acce sses can be performed, although it shoul d be noted that registers that require updating from shadow inform ation, or other inputs, cannot be read until c90fl exits reset. 23.1.5.10 factory margin read factory margin read must be done after the following ?initial fact ory conditions? are met: ? < 100 program/erase cycles ? nominal supply values ? operation at 25 ? c one factory margin read is allowed per erase. factory margin read may be done to selected and unlocked blocks by combining ut0[mre] and ut0[mrv] with the array integrity check. if ut0[mre] is set, ut0[ ais] has no affect, and the reads will be done sequentially. the data to be read is customer specific. thus, a cu stomer can provide user code into the flash memory and the correct misr value is calculated. the custom er is free to provide a ny random or non-random code, and a valid misr signature is calculated. once the operations is co mpleted, the results of the reads can be checking by reading the misr value. factory margin re ad is a self timed event, and is independent of
flash memory 23-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 system clocks, or wait st ates selected. margin ecc corrections or detections are not done during the factory margin read test. 1. enable utest mode. 2. select the block, or blocks to be receive marg in read check by writing ones to the appropriate registers in lms or hbs/ehs re gisters. make sure that sel ected blocks are also unlocked. note it is not possible to do utest operations on the shadow block. it is possible to do user mode array reads during the factory margin read test, if desired, but the partition ru les for read while write used during program and erase are in effect during factory margin reads. 3. set the ut0[mre] bit. 4. set the ut0[mrv] bit to desired value depending on it is desired to do one?s margin or zero?s margin. 5. seed the misr um0 thru um4 with desired values. 6. set the ut0[aie] bit. if desired, the margin read operation may be a borted prior to ut0[aid] going high. this may be done by clearing the ut0[ai e] bit and then continuing to the next step. in the event of an aborted margin read check the misr regi sters will contain a signature fo r the portion of the operation that was completed prior to the abort, and will not be deterministic. 7. wait until the ut0[aid] bit goes high. 8. read values in the misr registers (um0 through um4) to ensure correct signature. 9. write a logic 0 to the ut0[aie] bit. note if it is desired to do 2 or more margin reads, and it is desired to re-seed the misr, a reset must be done between operations. if the subsequent margin reads can be done with the previously calculated misr value, then a reset is not required. 23.1.5.11 array integrity self check array integrity is checked using a pre-defined addr ess sequence (based on ut0[ais]), and this operation is executed on selected and unlocked blocks. the data to be read is customer spec ific, thus a customer can provide user code into the flash and the correct misr value is calculated. the cust omer is free to provide any random or non-random code, a nd a valid misr signature is ca lculated. after the operation is completed, the results of the reads ca n be checking by reading the misr va lue, to determine if an incorrect read, or ecc detection was noted. array integrity is co ntrolled by the system clock, and it is required that the read wait states and address pi pelined control registers in the biu be set to match the user defined frequency being used. the array integrity check consists of the following sequence of events: 1. enable utest mode.
flash memory freescale semiconductor 23-11 pxs20 microcontroller reference manual, rev. 1 2. select the block, or blocks to be receive arra y integrity check by writi ng ones to the appropriate registers in lms or hbs registers. note locked blocks can be tested with ar ray integrity if se lected in lms and hbs. it is not possible to do utest operations on the shadow block. while array integrity is being executed, flash memory array accesses thru the biu should not be requested. 3. if desired, set the ut0[ais] bit to 1 for sequential addressing only. note for normal integrity checks of the fl ash memory, sequential addressing is recommended. if it is required to more fully check th e read path (in a diagnostic mode), it is recommend that ais be left at 0, to use the addr ess sequence that checks the read path more fully, and examin e read transitions. this sequence takes more time. 4. seed the misr um0 thru um4 with desired values. 5. set the ut0[aie] bit. if desired, the array integrity operation may be aborted prior to ut0[aid] going high. this may be done by clearing the ut0[aie] bi t and then continuing to the next step. it should be noted that in the event of an aborted array integrity check th e misr registers will c ontain a signature for the portion of the operation that was comp leted prior to the abort, and w ill not be deterministic. prior to doing another array integrity operation, the um0, um1, um2 and um3 registers may need to be initialized to the desired seed value by doing register writes. 6. wait until the ut0[aid] bit goes high. 7. read values in the misr registers (um0 through um4) to ensure correct signature. 8. write a logic 0 to the ut0[aie] bit. 23.1.5.12 ecc logic check ecc logic can be checked by providing data to be r ead in the ut0[dsi], ut1[dai] and/or ut2[dai] registers. then array reads can be done, ensuring expe cted results. the ecc logic check consists of the following sequence of events: 1. enable utest mode. 2. write ut0[eie] to 1. 3. write ut0[dsi], ut1[dai] and/or ut2[dai] bits to provide data a nd check bit values to be read. single or double bit det ections/corrections can be simulated by properly choosing data and check bit combinations. 4. write double word address to receive the data inputted in step 3 into the adr register.
flash memory 23-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 5. reads can now be done through the biu in a read request type fash ion. in the event of a biu read requested from an address that matches the a ddress in the adr register, expected data, and corrections or detections shoul d be observed based on data writ ten into the ut0[dsi], ut1[dai] and/or ut2[dai] registers. mcr[ee r] and mcr[sbc] can be checked to evaluate the status of reads done. note in the event of an ecc error or si ngle bit correction, dur ing the ecc logic check (uto[eie] high), the adr regist er will not be loaded, and the address tagged to receive the ut0[ dsi], ut1[dai] and/or ut2[dai] values will be persevered. 6. once completed, clear the ut0[eie] bit to 0. 23.1.6 c90fl memory map and register definition table 23-1 shows how the array is memory mapped. table 23-2 shows how the registers are mapped. caution software executing from flash memory must not write to registers that control flash behavior (such as wa it state settings or prefetch enable/disable). doing so can cause data corruption. on this chip, these registers include pfcr0 and pfapr. note flash memory configuration registers should be written only with 32-bit write operations to avoid any issues associated with re gister incoherency caused by bit fields spanning sm aller size (8-, 16-bit) boundaries. table 23-1. c90fl flash memory map flash_base address offset use block size (kb) partition 0x0 low address space l0 16 1 0x0000_4000 l1 48 0x0001_0000 l2 48 0x0001_c000 l3 16 0x0002_0000 l4 64 2 0x0003_0000 l5 64 0x0004_0000 mid address space m0 128 3 0x0006_0000 m1 128 0x0008_0000 high address space h0 256 4 0x000c_0000 h1 256 0x0010_0000 ? 0x00ef_ffff reserved
flash memory freescale semiconductor 23-13 pxs20 microcontroller reference manual, rev. 1 23.1.6.1 module configur ation register (mcr) the mcr register is defined in figure 23-3 and table 23-3 . 0x00f0_0000 flash memory shadow block, for general use s 16 all 1 0x00f0_3dd8 system censoring passcode 0x00f0_3de0 system censoring 0x00f0_3de8 lml default 0x00f0_3df0 hbl default 0x00f0_3df8 sll default 0x00f0_3e00 pfapr 0x00f0_3e08 biu3 default 0x00f0_3e10 biu4 default 0x00f0_4000 ? 0x00ff_ffff reserved 0x0100_0000 ? 0x1fff_ffff flash me mory emulation mapping ? 496 ? notes: 1 for read while write operations, shadow block behaves as if it is in all partitions. table 23-2. register memory map address use location flash_regs_base + 0x0 mcr on page 23-13 flash_regs_base + 0x4 lml register (lml) on page 23-18 flash_regs_base + 0x8 hbl register (hbl) on page 23-20 flash_regs_base + 0xc sll register (sll) on page 23-21 flash_regs_base + 0x10 lms register (lms) on page 23-22 flash_regs_base + 0x14 hbs register (hbs) on page 23-23 flash_regs_base + 0x18 adr register (adr) on page 23-24 flash_regs_base + 0x1c pflash conf iguration register 0 (pfcr0) on page 23-40 flash_regs_base + 0x24 pflash access protection register (pfapr) on page 23-44 flash_regs_base + 0x2c biu4 on page 23-25 flash_regs_base + 0x3c ut0 on page 23-25 flash_regs_base + 0x40 ut1 on page 23-27 flash_regs_base + 0x44 ut2 on page 23-27 flash_regs_base + 0x48 um0 on page 23-28 flash_regs_base + 0x4c um1 on page 23-28 flash_regs_base + 0x50 um2 on page 23-28 flash_regs_base + 0x54 um3 on page 23-28 flash_regs_base + 0x58 um4 on page 23-28 flash_shadow_base + 0x3dd8 nvpwd0 on page 23-31 flash_shadow_base + 0x3ddc nvpwd1 on page 23-32 flash_shadow_base + 0x3de0 nvsci on page 23-32 table 23-1. c90fl flash memory map (continued) flash_base address offset use block size (kb) partition
flash memory 23-14 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 offset 0x0000 access: user read/write 0123456789101112131415 r 00000 size 0 las 000mas w reset: 0000001101100000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eerrwesbc0peasdonepeg0000pgmpsusersesusehv w w1c w1c w1c reset: 0000011 0 0 0000000 = unimplemented or reserved figure 23-3. module configuration register (mcr) table 23-3. mcr field descriptions field description size array space size. the value of the size field is dependent upon the size of the c90f module. size is read only. 000 reserved 001 reserved 010 reserved 011 1.0 mb (256 kb of las, 256 kb of mas, and 512 kb of has) 100 reserved 101 reserved 110 reserved 111 reserved las low address space. the value of the las fi eld corresponds to the configuration of the low address space. las is read only. 000 one 256 kbyte blocks 001 two 128 kbyte blocks 010 four 16 kbyte, four 48 kbyte blocks 011 reserved 100 eight 16 kbyte, two 64 kbyte blocks 101 reserved 110 two 16 kbyte, two 48 kbyte, two 64 kbyte blocks 111 reserved mas mid address space. the value of the mas fiel d corresponds to the configuration of the mid address space. mas is read only. 0 two 128 kbyte blocks 1 one 256 kbyte blocks (only available if las =0)
flash memory freescale semiconductor 23-15 pxs20 microcontroller reference manual, rev. 1 eer ecc event error. eer provides information on prev ious reads. if a double bit detection occurred, the eer bit is set to a 1. this bit must then be cleared, or a reset must occur before this bit returns to a 0 state. this bit may not be set by the user. in the event of a single bit detection and correction, this bit is not be set. if eer is not set, or remains 0, this indicate s that all previous reads (from the last reset, or clearing of eer) are correct. since this bit is an error flag, it must be cleared to a 0 by writing a 1 to the register lo cation. a write of 0 has no effect. 0 reads are occurring normally 1 an ecc error occurred during a previous read rwe read while write event error. rwe provides in formation on previous rww reads. if a read while write error occurs, this bit is set to 1. this bit must then be cleared, or a reset must occur before this bit returns to a 0 state. this bit may not be written to a 1 by the user. if rwe is not set, or remains 0, this indicates that all previous rww r eads (from the last reset, or clearing of rwe) are correct. since this bit is an error fl ag, it must be cleared to a 0 by writing a 1 to the register location. a write of 0 has no effect. 0 reads are occurring normally 1 a read while write error occurred during a previous read sbc single bit correction. sbc provides information on previous reads provided the ut0[spce] is set. if a single bit correction occurred, the sbc bit is set to a 1. this bit must then be cleared, or a reset must occur before this bit re turns to a 0 state. if sbc is not set, or remains 0, this indicates that all previous reads (from the last reset, or cl earing of sbc) did not require a correction. since this bit is an error flag, it must be cleared to a 0 by writing a 1 to the register location. a write of 0 has no effect. 0 reads are occurring without corrections 1 a single bit correction occurred during a previous read peas program/erase access space. peas is used to indicate which space is valid for program and erase operations, either main array space or shadow space. peas = 0 indicates that the main address space is active for all fc program and erase operations. peas = 1 indicates the shadow address space is active for program/erase. t he value in peas is captured and held when the shadow block is enabled with the first interlock write done for program or erase operations. the value of peas is retained between sampling events (i.e. subsequent first interlock writes). the value in peas may be changed during erase-suspended program, and reverts back to its? original state once the erase-suspended progra m is completed. peas is read only. 0 shadow address space is disabled for program/erase and main address space enabled 1 shadow address space is enabled for program/erase and main address space disabled done state machine status. done i ndicates if the flash module is performing a high voltage operation. done is set to a 1 on termination of the flash m odule reset. done is read only. done is cleared within tdone (appendix a) of a 0 to 1 transition of ehv which initiates a high voltage operation. done is cleared within tres (appendix a) of re suming a suspended operation. done is set to a 1 at the end of program and erase high voltage sequences. done is set to a 1 within tdones (appendix a) of a 1 to 0 transition of ehv which aborts a high voltage operation. 0 flash is executing a high voltage operation 1 flash is not executing a high voltage operation table 23-3. mcr field descriptions (continued) field description
flash memory 23-16 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 peg program/erase good. the peg bit indicates the completion status of the last flash program or erase sequence for which high voltage operations were initiated. the value of peg is updated automatically during the program and erase high voltage operations. aborting a program/erase high voltage operation causes peg to be cleared, in dicating the sequence failed. peg is set to a 1 when the module is reset. peg is read only. the value of peg is valid only when pgm = 1 and/or ers = 1 and after done transitions from 0 to 1 due to an abort or the completion of a prog ram/erase operation. peg is valid until pgm/ers makes a 1 to 0 transition or ehv makes a 0 to 1 transition. the value in peg is not valid after a 0 to 1 transition of done caused by psus or esus being set to logic 1. if pgm and ers are both 1 when done makes a qualifying 0 to 1 transitio n the value of peg indicates the completion status of the pgm sequence. this happens in an erase-suspended program operation. 0 program or erase operation failed 1 program or erase operation successful note: if program or erases are attempted on blocks that are locked, the response from c90fl is peg = 1, indicating that the operation was su ccessful, and the contents of the block are properly protected from the program or erase operation. pgm program. pgm is used to setup c90fl for a program operation. a 0 to 1 transition of pgm initiates a program sequence. a 1 to 0 transition of pgm ends the program sequence. pgm can be set only under one of the following conditions: ? user mode read (ers is low and ute is low) ? erase suspend (ers and esus are 1) with ehv low pgm can be cleared by the user only when psus and ehv are low and done is high. pgm is cleared on reset. 0 flash is not executing a program sequence 1 flash is executing a program sequence note: in an erase-suspended program, programming flash locations in blocks which were being operated on in the erase may corrupt fc data. this should be avoided due to reliability implications. psus program suspend. psus is used to indicate the flash module is in program suspend or in the process of entering a suspend state. the module is in program suspend when psus = 1 and done = 1. psus can be set high only when pgm and ehv are high. a 0 to 1 transition of psus starts the sequence which sets done and plac es the flash module in program suspend. the module enters suspend within tpsus (appendix a) of this transition. psus can be cleared only when done and ehv are high. a 1 to 0 transition of psus with ehv = 1 starts the sequence which clears done and re turns the flash module to program. the module cannot exit program suspend and clear done while ehv is low. psus is cleared on reset. 0 program sequence is not suspended 1 program sequence is suspended ers erase. ers is used to setup c90fl for an erase operation. a 0 to 1 transition of ers initiates an erase sequence. a 1 to 0 transition of ers ends the erase sequence. ers can only be set only in user mode read (pgm is low and ute is low). ers can be cleared by the user only when esus and ehv are low and done is high. ers is cleared on reset. 0 flash is not executing an erase sequence 1 flash is executing an erase sequence table 23-3. mcr field descriptions (continued) field description
flash memory freescale semiconductor 23-17 pxs20 microcontroller reference manual, rev. 1 23.1.6.1.1 mcr simult aneous register writes a number of mcr bits are protected agai nst write when another bit, or set of bits, is in a specific state. these write locks are covered on a bi t by bit basis in the preceding sectio n. the write locks detailed in the previous section do not consider the effects of trying to write two or more bits simultaneously. the effects of writing bits simultaneously which put the module in an illegal state are detailed here. the flash module does not allow the user to write bits simultaneously wh ich put the device into an illegal state. this is implemented through a priority mech anism among the bits. the bit changing priorities are detailed in table 23-4 . esus erase suspend. esus is used to indicate that the flash module is in erase suspend or in the process of entering a suspend state. the module is in erase suspend when esus = 1 and done = 1. esus can be set high only when ers and ehv are high and pgm is low. a 0 to 1 transition of esus starts the sequence which sets done and places the flash in erase suspend. the flash module enters suspend within tesus (appendix a) of this transition. esus can be cleared only when done and ehv are high and pgm is low. a 1 to 0 transition of esus with ehv = 1 starts the se quence which clears done and returns the module to erase. the flash module cannot exit erase suspend and clear done while ehv is low. esus is cleared on reset. 0 erase sequence is not suspended 1 erase sequence is suspended ehv enable high voltage. the ehv bit enables the flash module for a high voltage program/erase operation. ehv is cleared on reset. ehv must be set after an interlock write to start a program/erase sequence. ehv may be set, initiating a program/erase, after an interlock under one of the following conditions: ? erase (ers = 1, esus = 0). ? program (ers = 0, esus = 0, pgm = 1, psus = 0). ? erase-suspended program (ers = 1, esus = 1, pgm = 1, psus = 0). if a program operation is to be initiated while an erase is suspended the user must clear ehv while in erase suspend before setting pgm. in normal operation, a 1 to 0 transition of ehv with done high, psus and esus low terminates the current program/erase high voltage operation. when an operation is aborted, there is a 1 to 0 transition of ehv with done low and the suspend bit for the current program/erase sequence low. an abort causes the value of peg to be cleared, indicating a failed program/erase; address loca tions being operated on by the aborted operation contain indeterminate data after an abort. a suspended operation cannot be aborted. ehv ma y be written during suspend. ehv must be high for the flash module to exit suspend. ehv may not be written after a suspend bit is set high and before done transitions high. ehv may not be set low after the current suspend bit is set low and before done transitions low. 0 flash is not enabled to perform a high voltage operation 1 flash is enabled to perform a high voltage operation note: aborting a high voltage operation leaves fc addr esses in an indeterminate data state. this may be recovered by executing an erase on the affected blocks. table 23-3. mcr field descriptions (continued) field description
flash memory 23-18 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 if the user attempts to write two or more mcr bits simultaneously then only the bit with the lowest priority level is written. setting two bits wi th the same priority level is prev ented by existing write locks or do not put the flash in an illegal state. for example, setting ers and pgm simultaneously re sults in only ers being set. attempting to clear ehv while setting psus results in ehv being cleared, while psus is unaffected. 23.1.6.2 low/mid address space block locking register (lml) the low/mid address block locking register (lml) provides a means to protect blocks from being modified. these bits, along with bits in the seconda ry llock (sll), determine if the block is locked from program or erase. an ?or? of lml and sll determine the final lock status. note a reset value of 1* in figure 23-4 indicates that the reset value of these registers is determined by flash valu es in the shadow block. an erased shadow block causes th e reset value to be 1. lml register functions are shown in table 23-5 . table 23-4. mcr bit set/clear priority levels priority level mcr bit(s) 1ers 2pgm 3ehv 4 esus, psus offset 0x0004 access: user read/write 0123456789101112131415 r lme0000000000slock00 mlock w reset: 000000000001*001*1* 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000 llock w reset: 0000001*1*1*1*1*1*1*1*1*1* = unimplemented or reserved figure 23-4. lml register
flash memory freescale semiconductor 23-19 pxs20 microcontroller reference manual, rev. 1 table 23-5. lml field descriptions field description 0 lme low/mid address lock enable. this bit is used to enable the lock registers (slock, mlock and llock) to be set or cleared by register writes. this bit is a status bit only, and may not be written or cleared, and the reset value is 0. the method to set this bit is to write a password, and if the password matches, the lme bit is set to reflect the status of enabled, and is enabled until a reset operation occurs. for lme, the password 0xa1a1_1111 must be written to the lml register. 0 low/mid address locks are disabled, and can not be modified 1 low/mid address locks are enabled to be written 1-10 reserved, reset to 0 11 slock shadow lock. this bit is used to lock the shadow block from programs and erases. a value of 1 in the slock register signifies that the shadow bl ock is locked for program and erase. a value of 0 in the slock register signifies that the shadow block is available to receive program and erase pulses. the slock register is not writable once an interlock write is completed until mcr[done] is set at the completion of the requested operation . likewise, slock register is not writable if a high voltage operation is suspended. slock is also not writeable during utest operations, when aie is high. upon reset, information from the shadow block is loaded into the slock register. the slock bit may be written as a register. reset causes the bits to go back to their shadow block value. the default value of the slock bits (assuming erased shadow location) is locked. slock is not writable unless lme is high. 12-13 reserved, reset to 0 14-15 mlock[1:0] mid address space block lock. a value of 1 in a bit of the lock register signifies that the corresponding block is locked for program and erase. a value of 0 in the lock register signifies that the corresponding block is available to receive program and erase pulses. the block numbering for mid address space starts with mlock[0] and continues until all blocks are accounted. the lock register is not writable once an interloc k write is completed until mcr[done] is set at the completion of the requested operati on. likewise, the lock register is not writable if a high voltage operation is suspended. mlock is also not writeable during utest operations, when aie is high. upon reset, information from the shadow block is loaded into the block registers. the lock bits may be written as a register. reset causes the bits to go back to their shadow block value. the default value of the lock bits (assuming erased shadow location) is locked. in the event that blocks are not present (due to c onfiguration or total memory size), the lock bits default to be locked, and are not writable. the reset value is always 1 (independent of the shadow block), and register writes have no effect. mlock is not writable unless lme is high. 16-21 reserved, reset to 0 22-31 llock[9:0] low address space block lock. a value of 1 in a bit of the lock register signifies that the corresponding block is locked for program and erase. a value of 0 in the lock register signifies that the corresponding block is available to receive program and erase pulses. the block numbering for low address space starts with llock[0] and continues until all blocks are accounted. for more details on llock, please see mlock bit description. llock is not writable unless lme is high.
flash memory 23-20 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 23.1.6.3 high address space block locking register (hbl) the high address space block lock ing register (hbl) provides a mean s to protect blocks from being modified. note a reset value of 1* in figure 23-5 indicates that the reset value of these registers is determined by flash valu es in the shadow block. an erased shadow block causes th e reset value to be 1. hbl register functions are shown in table 23-6 . offset 0x0008 access: user read/write 0123456789101112131415 r hbe000000000000000 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000000 hlock w reset: 00000000001*1*1*1*1*1* = unimplemented or reserved figure 23-5. hbl register table 23-6. hbl field descriptions field description 0 hbe high address lock enable this bit is used to enable the lock registers (hlock) to be set or cleared by register writes. this bit is a status bit only, and may not be written or cleared, and the reset value is 0. the method to set this bit is to provide a passw ord, and if the password matches, the hbe bit is set to reflect the status of enabled, and is enabled un til a reset operation occurs. for hbe, the password b2b2_2222h must be written to the hbl register. 0 high address locks are disabled, and can not be modified 1 high address locks are enabled to be written 1-25 reserved, reset to 0 26-31 hlock[5:0] high address space block lock. hlock has the same characteristics as llock. please see this description for more information. the block number ing for high address space starts with hlock[0] and continues until all blocks are accounted. hlock is not writable unless hbe is high.
flash memory freescale semiconductor 23-21 pxs20 microcontroller reference manual, rev. 1 23.1.6.4 secondary low/mid address sp ace block locking register (sll) the secondary low/mid addr ess block locking register (sll) provides an alte rnative means to protect blocks from being modified. this ha s the effect of creating a ?tiered? locking scheme to enable different flash users to provide different default locking on bloc ks. these bits, along with bits in the llock (lml), determine if the block is locked from program or erase. an ?or? of lml a nd sll determine the final lock status. note a reset value of 1* in figure 23-6 indicates that the reset value of these registers is determined by flash valu es in the shadow block. an erased shadow block causes th e reset value to be 1. sll register functions are shown in table 23-7 . offset 0x000c access: user read/write 0123456789101112131415 r sle0000000000ssloc k 00 smlock w reset: 000000000001*001*1* 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000 sllock w reset: 0000001*1*1*1*1*1*1*1*1*1* = unimplemented or reserved figure 23-6. sll register table 23-7. sll field descriptions field description 0 sle secondary low/mid address lock enable. this bi t is used to enable the lock registers (sslock, smlock, and sllock) to be set or cleared by register writes. this bit is a status bit only, and may not be written or cleared, and the rese t value is 0. the method to set this bit is to provide a password, and if the password matches, the sl e bit is set to reflect the status of enabled, and is enabled until a reset operation occurs. for sle, the password 0xc3c3_3333 must be written to the sll register. 0 secondary low/mid address locks are disabled, and can not be modified 1 secondary low/mid address locks are enabled to be written 1-10 reserved, reset to 0 11 sslock secondary shadow lock. this bit is an alternative method that may be used to lock the shadow block from programs and erases. sslock has the same de scription as slock. sslock is not writable unless sle is high.
flash memory 23-22 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 23.1.6.5 low/mid address space block select register (lms) the low/mid address space block se lect register (lms) provides a m eans to select blocks to be operated on during erase. lms register functions are shown in table 23-8 . 12-13 reserved, reset to 0 14-15 smlock[1:0] secondary mid address block lock. this bit is an alternative method that may be used to lock the mid address space blocks from programs and er ases. smlock has the same description as mlock. smlock is not writable unless sle is high. 16-21 reserved, reset to 0 22-31 sllock[9:0] secondary low address block lock. this bit is an alternative method that may be used to lock the low address space blocks from programs and erases. sllock has the same description as llock. sllock is not writable unless sle is high. offset 0x0010 access: user read/write 0123456789101112131415 r 00000000000000 msel w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000 lsel w reset: 0000000000000000 = unimplemented or reserved figure 23-7. lms register table 23-7. sll field descriptions (continued) field description
flash memory freescale semiconductor 23-23 pxs20 microcontroller reference manual, rev. 1 23.1.6.6 high address space block select register (hbs) the high address space block select register (hbs) provides a means to select blocks to be operated on during erase. table 23-8. lms field descriptions field description 0-13 reserved, reset to 0. 14-15 msel[1:0] mid address space block select. a value of 1 in the sele ct register signifies that the block is selected for erase. a value of 0 in the select register signifies that the block is not selected. the reset value for the select registers is 0, or unselected. the blocks must be selected (or unselected) before doing an erase interlock write as part of the erase sequence. the select register is not writable once an interlock write is completed until mcr[done] is set at the completion of the requested operation, or if a high voltage operation is suspended. msel is also not writeable during utest operations, when aie is high. in the event that blocks are not present (due to c onfiguration or total memory size), the corresponding select bits default to unselected, and are not writab le. the reset value is always 0, and register writes have no effect. 16-21 reserved, reset to 0. 22-31 lsel[9:0] low address space block select. a value of 1 in the se lect register signifies that the block is selected for erase. a value of 0 in the select register signifies that the block is not selected. the reset value for the select registers is 0, or unselected. the blocks must be selected (or unselected) before doing an erase interlock write as part of the erase sequence. the select register is not writable once an interlock write is completed until mcr[done] is set at the completion of the requested operation, or if a high voltage operation is suspended. lsel is also not writeable during utest operations, when aie is high. in the event that blocks are not present (due to c onfiguration or total memory size), the corresponding select bits default to unselected, and are not writab le. the reset value is always 0, and register writes have no effect. offset 0x0014 access: user read/write 0123456789101112131415 r 0000000000000000 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000000 hsel w reset: 0000000000000000 = unimplemented or reserved figure 23-8. hbs register
flash memory 23-24 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 hbs register functions are shown in table 23-9 . 23.1.6.7 address register (adr) the address register (adr) provides the first fail ing address in the event module failures (ecc or pgm/erase state machine) adr register functions are shown in table 23-10 . table 23-9. hbs field descriptions field description 0-25 reserved, reset to 0. 26-31 hsel[5:0] high address space block select. high address block select has the same characteristics as lsel. offset 0x0018 access: user read/write 0123456789101112131415 r sad0000000000 addr w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r addr 0 0 0 w reset: 0000000000000000 = unimplemented or reserved figure 23-9. adr register table 23-10. adr field descriptions field description 0 sad shadow address. the sad bit qualifies the address captured during an ecc event error, single bit correction, or state machine operation. the sad register is not writable. 0 address captured is from main array space. 1 address captured is from shadow array space. 1-10 reserved, reset to 0.
flash memory freescale semiconductor 23-25 pxs20 microcontroller reference manual, rev. 1 23.1.6.8 bus interface un it 4 register (biu4) the biu4 register implements th e user option bits described in section 23.1.7, user option bits . 23.1.6.9 user test 0 register the user test 0 register (ut0) provi des a means to control utest. the utest mode gives the users of the flash module the ability to perform te st features on the flash. this register is only wr itable when the flash is put into utest mode by writing a passcode. the following field and bit descriptio ns fully define the ut0 register. ut0 register functions, as shown in table 23-11 . 11-28 addr[17:0] address. the adr register provides the first failing address in the event of ecc event error (mcr[eer] set), single bit correction (mcr[sbc] set), as well as providing the address of a failure that may have occurred in a state machine operation (mcr[peg] clea red). ecc event errors take priority over single bit corrections, which take priority over state machine errors. this is especially valuable in the event of a rww operation, where the read senses an ecc erro r or single bit correction, and the state machine fails simultaneously. this address is always a double word address that selects 64 bits. the adr register is writable, and can be used in th e utest ecc logic check. if the ecc logic check is enabled (ut0[eie] = 1) then the adr register will not update for ecc event error, single bit correction or state machine errors. if mcr[eer] or mcr[sbc] are set, the adr register is locked from writing. mcr[peg] does not affect the writability of the adr register. 29-31 reserved, reset to 0. offset 0x003c access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r ute sbc e 000000 dsi w reset0000000000000000 1514131211109876543210 r 0 00000000 0 mre mrv eie ais aie aid w reset0000000000000001 figure 23-10. ut0 register table 23-10. adr field descriptions (continued) field description
flash memory 23-26 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 table 23-11. ut0 field descriptions field description 31 ute u-test enable. this status bit gives indication when u- test is enabled. all bits in ut0, ut1, ut2, um0, um1, um2, um3, and um4 are locked when this bit is 0. this bit is not writeable to a 1, but may be cleared. the reset value is 0. the method to set this bit is to provide a password, and if the password matches, the ute bit is set to reflect the status of enab led, and is enabled until it is cleared by a register write. the ute password will only be accepted if mcr[pgm] = 0 and mcr [ers] = 0 (program and erase are not being requested). ute can only be clear ed if ut0[aid] = 1, ut0[aie] and ut0[eie] = 0. while clearing ute, writes to set aie or set ei e will be ignored. for ute, the password 0xf9f9_9999 must be written to the ut0 register. 31 sbce single bit correction enable. sbc enables single bit correction results to be observed in mcr[sbc]. also is used as an enable for interrupt signals crea ted by the c90fl module. ecc corrections that occur when sbce is cleared will not be logged. 0 single bit corrections observation is disabled. 1 single bit correction observation is enabled. 29?24 reserved, reset to 0. 23-16 dsi[7:0] data syndrome input. these bits enable checks of ec c logic by allowing check bits to be input into the ecc logic and then read out by doing array reads or array integrity checks. the dsi[7:0] correspond to the 8 ecc check bits on a double word. 15-6 reserved, reset to 0. 5 mre margin read enable. mre combined with mrv enables factory margin reads to be done. margin reads are only active during array integrity checks. normal user reads are not affected by mre. mre is not writable if aid is low. 0 margin reads are not enabled. 1 margin reads are enabled during array integrity checks. 4 mrv margin read value. mrv selects the margin level th at is being checked. margin can be checked to an erased level (mrv=1) or to a programmed level (mrv=0). in order for this value to be valid, mre must also be set. mrv is not writable if aid is low. 0 zero?s margin reads are requested. 1 one?s margin reads are requested. 3 eie ecc data input enable. eie enables the input registers (dsi and dai) to be the source of data for the array. this is useful in the ecc logic check. if this bit is set, data read thru a biu read request will be from the dsi and dai registers when an address matc h is achieved to the a dr register. eie is not simultaneously writable to a 1 as uti is being cleared to a 0. 0 data read is from the flash array. 1 data read is from the dsi and dai registers. 2 ais array integrity sequence. ais determines the address sequence to be used during array integrity checks. the default sequence (ais = 0) is meant to r eplicate sequences normal ?user? code follows, and thoroughly checks the read propagation paths. this se quence is proprietary. the alternative sequence (ais = 1) is just logically sequential. it should be noted that the time to run a sequential sequence is significantly shorter than the time to run the propr ietary sequence. if mre is set, ais has no effect. 0 array integrity sequence is proprietary sequence. 1 array integrity sequence is sequential.
flash memory freescale semiconductor 23-27 pxs20 microcontroller reference manual, rev. 1 23.1.6.10 user test 1 register the user test 1 register (ut1) provi des added controlability to utest. the following field and bit descriptio ns fully define the ut1 register. ut1 register functions, as shown in table 23-12 . 23.1.6.11 user test 2 register the following field and bit descriptio ns fully define the ut2 register. 1 aie array integrity enable. aie set to one starts the array integrity check done on all selected and unlocked blocks. the address sequence selected is determined by ais, and the misr (um0 through um4) can be checked after the operation is complete, to determine if a correct signature is obtained. once an array integrity operation is requested (aie=1), it may be terminated by clearing aie if the operation has finished (aid = 1) or aborted by clearing aie if the operation is ongoing (aid = 0). aie is not simultaneously writable to a 1 as uti is being cleared to a 0. 0 array integrity checks are not enabled. 1 array integrity checks are enabled. 0 aid array integrity done. aid is cleared upon an array inte grity check being enabled (to signify the operation is ongoing). once completed, aid is set to indicate that the array integrity check is complete. at this time the misr (umr registers) can be checked. aid can not be written, and is status only. 0 array integrity check is ongoing. 1 array integrity check is done. offset 0x0040 access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r dai w reset0000000000000000 1514131211109876543210 r dai w reset0000000000000000 figure 23-11. ut1 register table 23-12. ut1 field descriptions field description 31-0 dai[31:0] data array input. these bits enable checks of ecc lo gic by allowing data bits to be input into the ecc logic and then read out by doing array reads or arra y integrity checks. the dai[31:0] correspond to the 32 array bits representing word 0 of the double word selected in the adr register. table 23-11. ut0 field descriptions (continued) field description
flash memory 23-28 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ut2 register functions, as shown in table 23-13 . 23.1.6.12 user multiple in put signature registers the multiple input signat ure registers (um0, um1, um2, um3 and um4) provide a means to evaluate array integrity. 23.1.6.12.1 um0 register the following field and bit descriptio ns fully define the um0 register. misr register functions are shown in table 23-14 . offset 0x0044 access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r dai w reset0000000000000000 1514131211109876543210 r dai w reset0000000000000000 figure 23-12. ut2 register table 23-13. ut2 field descriptions field description 31-0 dai[63:32] data array input. these bits enable checks of ecc logic by allowing data bits to be input into the ecc logic and then read out by doing array reads or array integrity checks. the dai[63:32] correspond to the 32 array bits representing word 1of the double word selected in the adr register. offset 0x0048 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r misr w reset 00000000000000000000000000000000 figure 23-13. um0 register
flash memory freescale semiconductor 23-29 pxs20 microcontroller reference manual, rev. 1 23.1.6.12.2 um1 register the following field and bit descriptio ns fully define the um1 register ( figure 23-14 ). misr register functions are shown in table 23-15 . table 23-14. um0 field descriptions field description 0-31 misr[31:0] the misr registers accumulate a signature from an array integrity event. the misr captures all data fields, as well as ecc fields, and the read transfer error signal. the misr can be seeded to any value by writing the misr registers. the misr register provides a means to calcul ate a misr during array integrity operations. the misr can be represented by the following polynomial: x 145 + x 6 + x 5 + x 1 + 1 the misr is calculated by taking the previous misr value and then ?exclusive oring? the new data. in addition the most significant bit (in this case it is misr[144]), is then ?exclusive ored? into input of misr[6], misr[5], misr[1], and misr[0]. the result of the ?exclusive or? is shifted left on each read. the misr register is used in array integrity operations. if during address sequencing, reads extend into an invalid address location (i.e. greater than the maximum address for a given array size) or locked/unselected blocks, reads are still executed to the array but the results from the array read are not determinis tic. in this instance, th e misr registers are not recalculated, and the previous value is retained. after running the user-test-mode margin read (also refe renced as factory margin read) sequence on the c90fl flash module, the misr registers cannot be wr itten such that the following user-test-mode margin read sequence cannot seed the misrs as desired . this will cause the generated misrs to be unexpected for the following user margin read sequences, in case customers want to run the user margin read more than once. to be able to write the misr registers: 1) assert reset after each user margin read sequence so that misrs can be written again. 2) do a dummy program to a locked block after user margin read. offset 0x004c access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r misr w reset 00000000000000000000000000000000 figure 23-14. um1 register
flash memory 23-30 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 23.1.6.12.3 um2 register the following field and bit descriptio ns fully define the um2 register. misr register functions are shown in table 23-16 . 23.1.6.12.4 um3 register the following field and bit descriptio ns fully define the um3 register. misr register functions are shown in table 23-17 . table 23-15. um1 field descriptions field description 0-31 misr[63:32] see the description of the misr field in table 23-14 . offset 0x0050 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r misr w reset 00000000000000000000000000000000 figure 23-15. um2 register table 23-16. um2 field descriptions field description 0-31 misr[95:64] see the description of the misr field in ta b l e 2 3 - 1 4 . offset 0x0054 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r misr w reset 00000000000000000000000000000000 figure 23-16. um3 register
flash memory freescale semiconductor 23-31 pxs20 microcontroller reference manual, rev. 1 23.1.6.12.5 um4 register the following field and bit descriptio ns fully define the um4 register. misr register functions are shown in table 23-18 . 23.1.6.13 nonvolatile private censorship password 0 register (nvpwd0) the nonvolatile private cens orship password 0 register (nvpwd0) contains the 32 ls b of the password used to validate the censorship inform ation contained in the nvsci register. table 23-17. um3 field descriptions field description 0-31 misr[127:96] see the description of the misr in ta b l e 2 3 - 1 4 . offset 0x0058 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000000000000 misr w reset 00000000000000000000000000000000 figure 23-17. um4 register table 23-18. um4 field descriptions field description misr[144:128] see the description of the misr in table 23-14 . offset 0x3dd8 access: user read/write 0123456789101112131415 r pwd[31:16] w reset11111110 11101101 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pwd[15:0] w reset11111010 11001110 figure 23-18. nonvolatile private censorship password 0 register (nvpwd0) table 23-19. nvpwd0 field descriptions field description pwd these bits represent the private censorship password.
flash memory 23-32 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 23.1.6.14 nonvolatile private censorship password 1 register (nvpwd1) the nonvolatile private censorship password 1 register (nvpwd1) c ontains the 32 msb of the password used to validate the censorship inform ation contained in the nvsci register. 23.1.6.15 nonvolatile system censor ing information register (nvsci) offset 0x3ddc access: user read/write 0123456789101112131415 r pwd[63:48 w reset11001010 11111110 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pwd[47:32] w reset10111110 11101111 figure 23-19. nonvolatile private censorship password 1 register (nvpwd1) table 23-20. nvpwd1 field descriptions field description pwd these bits represent the private censorship password. offset 0x3de0 access: user read/write 0123456789101112131415 r cw w reset01010101 10101010 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r sc w reset01010101 10101010 figure 23-20. nonvolatile system censoring information register (nvsci) for cut1
flash memory freescale semiconductor 23-33 pxs20 microcontroller reference manual, rev. 1 the nonvolatile system censoring info rmation register (nvsci) stores the censorship control word of the device. it is read during the reset phase of th e flash memory module and the protection mechanisms are activated consequently. the devices are delivered uncensored to the user. 23.1.7 user option bits table 23-22 describes the user option bits on this device. these are programme d in the biu4 register (see section 23.1.6.8, bus interface unit 4 register (biu4) ) and verified using the uop s register in the sscm (see section 48.3.1.8, user option status register (uops) ). offset 0x3de0 access: user read/write 0123456789101112131415 r sc w reset01010101 10101010 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cw w reset01010101 10101010 figure 23-21. nonvolatile system censoring information register (nvsci) for cut2/3 table 23-21. nvsci field descriptions field description sc serial censorsh ip control word. these bits represent the serial censorship control word (sccw). if sc[15:0] = 0x55aa, the public access is disabled. if sc[15:0] ? 0x55aa, the public access is enabled. cw censorship control word. these bits represent the censorship control word (ccw). if cw = 0x55aa, the censored mode is disabled. if cw ? 0x55aa, the censored mode is enabled. table 23-22. user option bits bit number function name description 31?20 fccu_cfg fccu configuration bits 26?31: fccu_cfg.fop bits 23?25: fccu_cfg.fom bit 22: fccu_cfg.ps bit 21: fccu_cfg.sm bit 20: fccu_cfg.cm 19?10 reserved
flash memory 23-34 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 the default states of the swt modules depend on the valu e of the watc hdog_enable and lsm_dpmb bits as described in table 23-23 . 23.1.8 test flash memory test flash memory contains calibration and other chip -specific data. this inform ation is summarized in table 23-24 . 9 lsm_dpmb 0 selects single core/dpm 1 selects lsm (default value) 8?2 reserved 1 xosc_margin xosc oscillation margin select 0 selects lower xosc consumption and lower oscillator margin 1 selects higher xosc consumption and higher oscillator margin 0 watchdog_enable 0 disable swt 1 enable swt table 23-23. swt default states lsm_dpmb (mode) watchdog_enable swt default state 1 (ls mode) 1 enable swt_0 enable swt_1 0disable swt_0 disable swt_1 0 (dp mode) 1 enable swt_0 disable swt_1 0disable swt_0 disable swt_1 table 23-24. test flash information address word name function note 0x0000 tsens_0_cal w2/w4 tsens_0 calibration data w2 (p2/ptat) and w4 (c2/ctat) at cold temperature 2x12bits words 0x0004 tsens_1_cal w2/w4 tsens_1 calibration data w2 (p2/ptat) and w4 (c2/ctat) at cold temperature 2x12bits words 0x0008 tsens_0_cal w1/w3 tsens_0 calibration data w1 (p2/ptat) and w3 (c2/ctat) at hot temperature 2x12bits words 0x000c tsens_1_cal w1/w3 tsens_1 calibration data w1 (p2/ptat) and w3 (c2/ctat) at hot temperature 2x12bits words 0x0010 adc0_cal w1 adc0 self-test calibration 2x12bits words 0x0014 adc0_cal w2 adc0 self-test calibration 2x12bits words table 23-22. user option bits (continued) bit number function name description
flash memory freescale semiconductor 23-35 pxs20 microcontroller reference manual, rev. 1 23.2 dual-ported platform flash memory controller (pflash2p) 23.2.1 introduction this section provides an overview of the dual ported platform flash controller (pflash2p) for standard product platforms (spp). the pflash2p acts as an interface between the system bus (ahb-lite 2.v6) and the integrated flash memory arra y. it intelligently converts the pr otocols between the system bus and the dedicated flash array interface. the pflash2p block supports a 64-bit da ta bus width at the ah b ports, and a 128-bit read data interface from the flash memory array. the pflash2p has tw o ahb ports with dedicated line buffers for each interface. each port has four, 128-bit line buffers and an associated c ontroller which prefetches sequential lines of data from the flash array into the buffers . line buffer hits support zero-wait ahb data phase responses. ahb read requests which miss the buffers generate the needed flash array access and are 0x0018 adc0_cal w3 adc0 self-test calibration 2x12bits words 0x001c adc0_cal w4 adc0 self-test calibration 2x12bits words 0x0020 adc0_cal w5 adc0 self-test calibration 2x12bits words 0x0024 adc0_cal w6 adc0 self-test calibration 2x12bits words 0x0028 adc0_cal w7 adc0 self-test calibration 2x12bits words 0x002c adc0_cal w8 adc0 self-test calibration 2x12bits words 0x0030 adc0 reserved adc0 reserved for future expansion 0x0034 adc1_cal w1 adc1 self-test calibration 2x12bits words 0x0038 adc1_cal w2 adc1 self-test calibration 2x12bits words 0x003c adc1_cal w3 adc1 self-test calibration 2x12bits words 0x0040 adc1_cal w4 adc1 self-test calibration 2x12bits words 0x0044 adc1_cal w5 adc1 self-test calibration 2x12bits words 0x0048 adc1_cal w6 adc1 self-test calibration 2x12bits words 0x004c adc1_cal w7 adc1 self-test calibration 2x12bits words 0x0050 adc1_cal w8 adc1 self-test calibration 2x12bits words 0x0054 adc1 reserved adc1 reserved for future expansion 0x0058 part id1 low plant and lot number ascii format needed for kgd 0x005c part id1 high plant and lot number ascii format needed for kgd 0x0060 part id2 wafer number and coordinates needed for kgd 0x0064 spare 1 reserved for future usage 0x0068 spare 2 reserved for future usage table 23-24. test flash information (continued) address word name function note
flash memory 23-36 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 forwarded to the ahb upon completi on, typically incurring multiple wa it-states at the maximum operating frequency. the pflash2p module supports soc designs based on a ahb system bus. in particular, this memory controller is designed to support mult iple core designs such as those th at include an i/o processor. the design of the line buffers ca n accommodate processor core s with or without caches. 23.2.1.1 features the following list summarizes th e key features of the pflash2p: ? the pflash2p has two ahb ports wi th buffering and arbitration logi c to efficiently share a single flash array in a multi-core system. ? the pflash2p system bus ahb interfaces su pport 64-bit data buses. all ahb aligned and unaligned reads are supported.o nly aligned word and doublew ord writes are supported. ? the pflash2p array interface supports a 128-bit read data bus a 64-bit write data bus. ? the pflash2p provides configur able, independent read buffering for each ahb port. there are four line read buffers and a prefetch controller for each port. the buffers implement a least-recently-used replacement algorithm to maximize performan ce. the nomenclature ?page buffers and ?line buffers? are used interchangeably. ? the pflash2p provides read and write a ccess protections on a per master basis. ? the pflash2p provides configurable access timing a llowing use in a wide range of platforms and frequencies. ? the pflash2p provides multiple-mapping s upport and mapping-base d block access timing allowing use for emulati on of other memory types. ? the pflash2p uses one single async hronous reset and one global clock. ? the pflash2p is implemented using a pos-edge, fully-synthesizable methodology, and uses a muxed-dff scan methodology for testability. 23.2.1.2 block diagrams figure 23-22 provides a system block diagram show ing a dual ported flash controller and figure 23-23 is a high-level block diagram for the pflash2p module.
flash memory freescale semiconductor 23-37 pxs20 microcontroller reference manual, rev. 1 figure 23-22. system block diagram with pflash controller xbar eim pbridge controller interrupt controller ecsm spp i/o on-platform irqs off-platform irqs m1 s7 s1 s0 s2 pflash platform sram m0 ips off-platform appl ication-specific peripherals external bus soc sram flash s3 processor main processor
flash memory 23-38 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 23-23. pflash2p high level block diagram 23.2.1.3 general operation the pflash2p block provides two ahb -lite slave ports for system bus masters to access the flash array. the pflash2p generates read and write enables, the fl ash array address, write size, and write data as inputs to the flash array controller. the pflash2p capt ures read data from the flash array interface and drives it onto the proper ah b port. up to four lines of data are buff ered by the pflash2p for each ahb port. each line buffer holds 128 bits. lines may be pr efetched in advance of being requested by the ahb interface, allowing single-cycle read data (zero ahb wait-s tate) responses on buffe r hits. accesses may be overlapped on the flash array in terface with the address and contro l signals transitioning to the next pending request (if any). read request addresses from the ahb are compared to the values stored in the tags in the prefetch controller. access hits result in zero wait-state return of buffered data to the ahb. the prefetch controllers use one of several programmable algorithms to dete rmine when to prefetch information from the flash array into one of the line buffers. prefetching may be restricted to instruction-only triggering, data-only triggering, or instruction and data tr iggering. line buffers are configured for use by in struction and/or data prefetches, allowing for exclusive or shared use by these access types.in addi tion, prefetching may be restricted to one or more ahb bus masters to improve the prefetch effi ciency. in many systems, it may be flash interface system bus port 0 fl_addr fl_rdata fl_wdata p0_haddr p0_hrdata p0_hwdata line buffers and control port 1 p1_haddr p1_hrdata p1_hwdata line buffers and control
flash memory freescale semiconductor 23-39 pxs20 microcontroller reference manual, rev. 1 desirable to only enable prefetches for the processor core to limit the number of buffers used for other masters. the pflash2p occupies a 512 mbyt e region of the address space. the actual flash array is multiply-mapped within this space. upper address lines haddr[28:24] are used to provide additional control which allows the pflash2p responses on the ah b to be varied in orde r to provide for timing emulation of alternate memory types. see section 23.2.3.6, wait-state emulation for additional information. the pflash2p memory map is shown in figure 23-24 . recall the pflash2p supports a 16 mbyte (24 address bits) physical flash array size. figure 23-24. pflash2p memory map write accesses must be either word or doubleword in size, and must be aligned. unaligned writes and byte or halfword writes result in an error termination on the ahb side, and no flash array write is initiated. write addresses are captured from the ahb, and a writ e to the flash is initiated once data from the ahb is available on the following cycle. write data is held valid until the flash write cycle completes. 23.2.2 registers caution software executing from flash memory must not write to registers that control flash behavior (such as wa it state settings or prefetch enable/disable). doing so can cause data corruption. note flash memory configuration registers should be written only with 32-bit write operations to avoid any issues associated with re gister incoherency caused by bit fields spanning sm aller size (8-, 16-bit) boundaries. within the module?s programming model, there are a vari ety of control and confi guration fields. some are associated with the operating confi guration of the flash memory array, while others are related to the behavior of the ahb master ports. the pflash controller does not provide completely symmetric capabilities for the flash memory array. first, consider the operating configuration of the fl ash memory array. in part icular, there are 4 unique configuration fields that are associat ed with the array. these include all the parameters associated with the timing (read and write wait states, a ddress pipeline control) as well as the read-while-write control field. flash array 0byyyzz_0000_0000_0000_0000_0000_0000 - access 0byyyzz_1111_1111_1111_1111_1111_1111 yyyzz - additional primary (yyy) and secondary (zz) wait-states for emulation
flash memory 23-40 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 second, there are a total of 6 configur ation fields that relate to the operation of the controller?s page buffers. these fields are defined on a ?per port? basis since the control needs to be associated with the ahb master port and not the destination flash memory array . 23.2.2.1 platform flash confi guration register 0 (pfcr0) this register defines the configur ation associated with the flash memory array. additionally, it includes fields that provide specific information for the two sepa rate ahb ports (p0 and p1). figure 23-25 shows the pfcr0. the fields in this register are described in table 23-25 . offset 0x01c access: read/write 0123456789101112131415 r 0 0 b02_apc 0 0 0 b02_wws c 0 0 b02_rwsc 1 w reset0001100011000111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 1 b02_p1_b cfg b02_ p1_ dpf e b02_ p1_i pfe b02_p1_pf lm b02_ p1_b fe 1 b0_p0_bc fg b02_ p0_ dpf e b02_ p0_i pfe b02_p0_pf lm b02_ p0_b fe w reset1110110111101101 figure 23-25. pflash configurati on register 0 (pfcr0) for port 0
flash memory freescale semiconductor 23-41 pxs20 microcontroller reference manual, rev. 1 table 23-25. pfcr0 field descriptions field description b02_apc address pipelining cont rol. this field is used to control the number of cycles between flash array access requests. this field must be set to a value appropriate to the operating frequency of the pflash. the value of this field must be greater than or equal to the values in the wwsc and rwsc fields. higher operating frequencies require non-zero settings for this field for proper flash operation. 000 accesses may be initiated on consecutive (back-to-back) cycles 001 access requests require one additional hold cycle 010 access requests require two additional hold cycles ... 110 access requests requir e six additiona l hold cycles 111 no address pipelining note: apc must equal rwsc. refer pflash configuration register 0 (pfcr0) se ttings for different frequencies table for values at different frequencie. b02_wwsc write wait state control. this field is used to control the number of wait-states to be added to the flash array access time for writes. this field must be set to a value appropriate to the operating frequency of the pflash. higher operating frequencies require non-zero settings for this field for proper flash operation. this field is set to an appropriate value by hardware reset. 00 no additional wait-states are added 01 1 additional wait-state is added 10 2 additional wait-states are added 11 3 additional wait-states are added refer pflash configuration register 0 (pfcr0) se ttings for different frequencies table for values at different frequencies . b02_rwsc read wait state control. this field is used to control the number of wait-states to be added to the flash array access time for reads. this field must be set to a value corresponding to the operating frequency of the pflash and the actual read access time of the pflash. higher operating frequencies require non-zero settings for this field for proper flash operation. the integrator is strongly encouraged to verify these sett ings based on actual silicon results. 000 no additional wait-states are added 001 1 additional wait-state is added 010 2 additional wait-states are added ... 111 7 additional wait-states are added refer pflash configuration register 0 (pfcr0) se ttings for different frequencies table for values at different frequencies.
flash memory 23-42 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 b02_p1_bcf g port 1 page buffer configuration. this field controls the configuration of the four page buffers in the pflash controller. the buffers can be organized as a ?pool? of available resources, or with a fixed partition between instruction and data buffers. if enabled, when a buffer miss occurs, it is allocated to the least-recently-used buffer within the group and the just-fetched entry then marked as most-recently-used. if the flash access is for the next-sequential line, the buffer is not marked as most-recently-used until the given address produces a buffer hit. 00 all four buffers are available for any flash access, that is, there is no partitioning of the buffers based on the access type. 01 reserved 10 the buffers are partitioned into two groups wit h buffers 0 and 1 allocated for instruction fetches and buffers 2 and 3 for data accesses. 11 the buffers are partitioned into two groups with buffers 0,1,2 allocated for instruction fetches and buffer 3 for data accesses. b02_p1_dpf e port 1 data prefetch enable. this field enables or disables prefetching initiated by a data read access. this field is set by hardware reset. 0 no prefetching is triggered by a data read access 1 if page buffers are enabled (b02_p1_bfe = 1), prefetching is triggered by any data read access b02_p1_ipfe port 1 instruction prefetch enable. this field enables or disables prefetching initiated by an instruction fetch read access. this field is cleared by hardware reset. 0 no prefetching is triggered by an instruction fetch read access 1 if page buffers are enabled (b02_p1_bfe = 1), prefetching is triggered by any instruction fetch read access b02_p1_pfl m port 1 prefetch limit. this field controls the pr efetch algorithm used by the pflash controller. this field defines the prefetch behavior. in all situations when enabled, only a single prefetch is initiated on each buffer miss or hit. this field is set to 2b01 by hardware reset. 00 no prefetching is performed. 01 the referenced line is prefetched on a buffer miss, that is, prefetch on miss . 1- the referenced line is prefetched on a buffer miss, or the next sequential page is prefetched on a buffer hit (if not already present), that is, prefetch on miss or hit . b02_p1_bfe port 1 buffer enable. this bit enables or disables page buffer read hits. it is also used to invalidate the buffers. this bit is set by hardware reset, enabling the page buffers. 0 the page buffers are disabled from satisfying read requests, and all buffer valid bits are cleared. 1 the page buffers are enabled to satisfy read requests on hits. buffer valid bits may be set when the buffers are successfully filled. table 23-25. pfcr0 field descriptions (continued) field description
flash memory freescale semiconductor 23-43 pxs20 microcontroller reference manual, rev. 1 b02_p0_bcf g port 0 page buffer configuration. this field controls the configuration of the four page buffers in the pflash controller. the buffers can be organized as a ?pool? of available resources, or with a fixed partition between instruction and data buffers. if enabled, when a buffer miss occurs, it is allocated to the least-recently-used buffer within the group and the just-fetched entry then marked as most-recently-used. if the flash access is for the next-sequential line, the buffer is not marked as most-recently-used until the given address produces a buffer hit. 00 all four buffers are available for any flash access, that is, there is no partitioning of the buffers based on the access type. 01 reserved 10 the buffers are partitioned into two groups wit h buffers 0 and 1 allocated for instruction fetches and buffers 2 and 3 for data accesses. 11 the buffers are partitioned into two groups with buffers 0,1,2 allocated for instruction fetches and buffer 3 for data accesses. this field is set to 2b11 by hardware reset. b02_p0_dpf e port 0 data prefetch enable. this field enables or disables prefetching initiated by a data read access. this field is cleared by hardware reset. 0 no prefetching is triggered by a data read access 1 if page buffers are enabled (b0_p0_bfe = 1), prefetching is triggered by any data read access b02_p0_ipfe port 0 instruction prefetch enable. this field enables or disables prefetching initiated by an instruction fetch read access. this field is set by hardware reset. 0 no prefetching is triggered by an instruction fetch read access 1 if page buffers are enabled (b0_p0_bfe = 1), pref etching is triggered by any instruction fetch read access b02_p0_pfl m port 0 prefetch limit. this field controls the pr efetch algorithm used by the pflash controller. this field defines the prefetch behavior. in all situations when enabled, only a single prefetch is initiated on each buffer miss or hit. this field is set to 2b10 by hardware reset. 00 no prefetching is performed. 01 the referenced line is prefetched on a buffer miss, that is, prefetch on miss . 1- the referenced line is prefetched on a buffer miss, or the next sequential page is prefetched on a buffer hit (if not already present), that is, prefetch on miss or hit . b02_p0_bfe port 0 buffer enable. this bit enables or disables page buffer read hits. it is also used to invalidate the buffers. this bit is set by hardware reset. 0 the page buffers are disabled from satisfying read requests, and all buffer valid bits are cleared. 1 the page buffers are enabled to satisfy read requests on hits. buffer valid bits may be set when the buffers are successfully filled. table 23-25. pfcr0 field descriptions (continued) field description
flash memory 23-44 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 note the fields apc, wwsc and rwsc of the pflash configuration register 0 (pfcr0) should be set to the same value. the ram ws are configured by the mudcr bit in the miscellaneous user-defined control register (mudcr). 23.2.2.2 platform flas h access protection register (pfapr) the pflash access protection register (pfapr) is used to control read and write accesses to the flash based on system master number. pref etching capabilities are defined on a per master basis. this register also defines the arbitration mode between the 2 ahb ports for the pflash2p _lca. the register is described below in figure 23-26 and table 23-27 . the contents of the register are loaded from location 0x203e00 of the sh adow region in the flash memory array at reset. to tempor arily change the values of any of the fields in the pfapr, a write to the ips-mapped register is performed. to change the values loaded into the pfapr at reset , the word location at address 0x203e00 of the shadow region in the flash array must be programmed using the normal sequence of operations. the reset value shown in figure 23-26 reflects an erased or unprogrammed value from the shadow region. table 23-26. pflash configuration register 0 (pfcr0) settings for different frequencies frequency flash wait state apc field wwsc field rwsc fiel d ram wait state <=120mhz33330 <=80mhz22220 <=60mhz11110 offset 0x024 access: read/write 0123456789101112131415 r 0 0 0 0 0 0 arbm m7p fd m6p fd m5p fd m4p fd m3p fd m2p fd m1p fd m0p fd w reset* * * * * *1111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r m7ap m6ap m5ap m4ap m3ap m2ap m1ap m0ap w reset1111111111111111 figure 23-26. pflash access protection register (pfapr)
flash memory freescale semiconductor 23-45 pxs20 microcontroller reference manual, rev. 1 23.2.3 functional description the pflash2p has two ahb-lite slave ports and a single flash array interf ace. the dual ported design of the pflash2p enables efficient us e of a single flash memory array by two processor cores. each ahb port has dedicated line buffers to support single-cycle read accesses and to limit acce sses to the flash array. the pflash2p generates read and write enables, the fl ash array address, write size, and write data as inputs to the flash array controller. the pflash2p capt ures read data from the flash array interface and drives it onto the proper ahb port. if line buffering is enabled, when data is read from the array it is stored in a line buffer. up to four lines of data ( 128 bits) are buffered by the pflash2p for each ahb port. if pre-fetching is enabled, data is read in advance and stored in the li ne buffers allowing single-cycle (zero ahb wait-states) read data responses on buffer hits. prefetch triggering may be restricted to instruction accesses only, data accesses only, or may be unrestricted. prefetch tri ggering may also be controlled on a per-master basis. arbitration between the two ahb ports for access to the flash interface is primaril y based on the type of access; writes have priority over reads which have prio rity over prefetches. if bo th ports are doing the same type of access, priority is based on the settings of th e arbitration and priority bi ts in the pfcrp0 register. 23.2.3.1 basic interface protocol the pflash2p interfaces to the flash array by driv ing addresses and read or write enable signals. table 23-27. pfapr field descriptions field description arbm arbitration mode. this 2-bit field controls the arbitration for pflash controllers supporting 2 ahb ports. the port arbitration mode is used only when accesses from the 2 ahb ports attempt to simultaneously reference the same flash memory array. 00 fixed priority arbitration with ahb p0 > p1 01 fixed priority arbitration with ahb p1 > p0 1 x round-robin arbitration mxpfd master x prefetch disable (x = 0,1,2,...,7). these bits control whether prefetching may be triggered based on the master number of the requesting ahb master. this field is further qualified by the pfcrn[b02_px_dpfe, b02_px_i pfe, bx_py_bfe] bits. 0 prefetching may be triggered by this master 1 no prefetching may be triggered by this master mxap master x access protection (x = 0,1,2,...,7). th ese fields control whether read and write accesses to the flash are allowed based on the ma ster number of the initiating module. 00 no accesses may be performed by this master 01 only read accesses may be performed by this master 10 only write accesses may be performed by this master 11 both read and write accesses may be performed by this master
flash memory 23-46 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 accesses are terminated based on timing parameters contained in th e pfcr0. the correct setting of the wait-state control bits in the pfcr0 is determined by the access time of the flas h array and the platform clock frequency. the pflash2p also has the capability of extending the normal ahb access timing by inserting additional wait states for reads. this capabilit y is provided to allow emulation of other memories whic h have different access time characteristics. these wait-states are applied in addition to the normal wait-states incurred for flash accesses. refer to section 23.2.3.6, wait-state emulation for more detail on wait-state emulation. prefetching of next sequential line can be blocked. buffer hits can be blocked as well, regardless of whether the access corresponds to valid data in one of th e line read buffers. these steps are taken to ensure that timing emulation is correct and that excessive prefetching is avoided. 23.2.3.2 read cycles read cycles from the flash array ar e initiated by driving a valid access address and then asserting a read enable. the pflash2p then wa its for the flash array to provide read data. this data is normally stored in the least-recently updated li ne read buffer in parallel with the requested data being forwarded to the ahb. single clock read responses to th e ahb are possible with the pflash2p when the requested read access is buffered. in these cases, read data is returned to the ahb data phas e with a zero wait-state response. 23.2.3.3 write cycles write cycles to the flash array ar e initiated by driving a valid access address, driving write data, and indicating the size of the write data.the pflash2p th en waits for the indicate d number of wait states before the cycle has terminated. 23.2.3.4 flash error response operation the flash array may signal an error response. this may occur due to an uncorrectable ecc error, or because of improper sequenc ing during program/erase ope rations. when an error re sponse is received, the pflash2p will not update or valida te a line read buffer. an error response may be signaled on read or write operations. 23.2.3.5 line read buffers and prefetch operation the pflash2p contains four read buf fers per ahb port which are used to hold line and ecc data read from the flash array. each buffer operates independent ly, and is filled using a single array access. the buffers are used for both prefetch and normal demand fetches. prefetch triggering is controllable on a per-master and access-type basi s. bus masters may be enabled or disabled from triggering prefetches , and triggering may be further re stricted based on whether a read access is for instruction or data. a read access to the pflash2p may trigger a prefetch to the next sequential line of array da ta on the cycle following the request. th e access address is incremented to the next-higher 16 byte boundary, and a flash array prefetch is initiated if the data is not already resident in a line read buffer. prefetched data is always loaded into the least-recently-used buffer. buffers may be in one of six states , listed here in prioritized order:
flash memory freescale semiconductor 23-47 pxs20 microcontroller reference manual, rev. 1 ? invalid - the buffer contains no valid data ? used - the buffer contains valid data which has been provided to satisfy an ahb burst type read ? valid - the buffer contains valid data which has been provided to satisfy an ahb single type read ? prefetched - the buffer contains valid data whic h has been prefetched to satisfy a potential future ahb access ? busy ahb - the buffer is currently being used to satisfy an ahb burst read ? busy fill - the buffer has been allocated to re ceive data from the flash array, and the array access is still in progress selection of a buffer to be loaded on a miss is based on the following replacement algorithm: 1. first, the buffers are examined to determine if there are any invalid buffers. if there are multiple invalid buffers, the one to be used is selected using a reverse num eric priority, where buffer 0 is selected first, then buffer 1, etc. 2. if there are no invalid buffers, the least-re cently-used buffer is se lected for replacement. once the candidate line buffer has been selected, the fl ash array is accessed and read data loaded into the buffer. if the buffer load was in response to a miss , the just-loaded buffer is immediately marked as most-recently-used. if the buffer load was in response to a speculative fetch to the next-sequential line address after a buffer hit, the recently-used status is not changed . rather, it is marked as most-recently-used only afte r a subsequent buffer hit. this policy maximizes performance based on refere nce patterns of flash accesses and allows for prefetched data to remain valid when non-prefe tch enabled bus masters are granted flash access. several algorithms are available for prefetch c ontrol which trade off performance for power. more aggressive prefetching increases power due to the number of wasted (discarded) prefetches, but may increase performance by lowe ring average read latency. in order for prefetching to occur, pfcrpx[bfen] mu st be set to ?1?; pfcrpx[pflim] must be non-zero; either pfcrpx[ipfen] or pfcrpx[dpfen] must be ?1? and pfcrpx[mxpfe] must be ?1?. 23.2.3.5.1 inst/data prefetch triggering prefetch triggering may be enabled for instruction reads via the pfcr0[ipfen] control bit, while prefetching for data reads is enabled via th e pfcr0[dpfen] control bit. additionally, the pfcrpx[pflim] must also be set to enable prefetching. prefetches ar e never triggered by write cycles. 23.2.3.5.2 per-master prefetch triggering prefetch triggering may be contro lled for individual bus masters vi a the pfcr0[mxpfd] control field. 23.2.3.5.3 buffer allocation allocation of the line read buffers is controlled vi a the pfcrpx control register for each ahb port. the lbcfg field of this regist er defines the operating orga nization of the four line buffers. the buffers can be organized as a ?pool? of ava ilable resources with all four buffers av ailable for either in struction or data.
flash memory 23-48 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 they can also be conf igured with a fixed partition between buffers allocated to instructi on or data accesses. for the fixed partition, two configur ations are supported. in one configuration, buffers 0 and 1 are allocated for instruction fetches and buffers 2 and 3 for data accesses. in the second configurati on, buffers 0, 1 and 2 are allocated for instruction fetches and buffer 3 rese rved for data accesses. in this configuration data prefetching is disabled. 23.2.3.5.4 buffer invalidation the line read buffers may be i nvalidated under hardware and software contro l. assertion of the fl_invbuf input signal causes the line re ad buffers to be marked as invalid. to ensure that st ale data is not read from the buffers, software should invalidate the buffers after writing to the array. this is done by clearing the pfcrpx[bfen] bit, which also disables the buffers . software may then restore the pfcrpx[bfen] bit to its previous state, and the buf fers will have been invalidated. also, the buffers are invalidated by hardware on any non-sequential (nseq) access with a non-zero wait state value to support wait-state emulation. 23.2.3.6 wait-state emulation emulation of other memory array ti mings are supported by th e pflash2p on read cycl es to the flash. this functionality may be useful to main tain the access timing for blocks of memory which were used to overlay flash blocks for the purpose of system calib ration or tuning during code development. the pflash2p inserts additional wait-states according to the values of the pfcr0 read wait state control fields plus the value on the address line bits 28-24. wait-states ar e applied to the initial access of a burst fetch or to single-beat re ad accesses on the ahb system bus. note there is an inherent 2-cycle delay added when using non-zero values for address line bits 28-24. when the address line bi ts 28-24 are non-zero, normal ahb termination is extende d only for read cycles. write cycles are not affected. in a ddition, no line read buffer prefetches are initiated, and buffer hits are ignored. see the description of the read wait stat e control field in the pfcr0 register for further information on read wait states. wait states are applied to the initial access of a burst fetch or to single-beat read accesses on the ahb system bus. table 23-28. additional wait-state encoding memory address additional wait-stats flash address + 0x0000_0000 0 flash address + 0x0100_0000 10 flash address + 0x0200_0000 18 flash address + 0x0300_0000 26 flash address + 0x0400_0000 3 flash address + 0x0500_0000 11
flash memory freescale semiconductor 23-49 pxs20 microcontroller reference manual, rev. 1 flash address + 0x0600_0000 19 flash address + 0x0700_0000 27 flash address + 0x0800_0000 4 flash address + 0x0900_0000 12 flash address + 0x0a00_0000 20 flash address + 0x0b00_0000 28 flash address + 0x0c00_0000 5 flash address + 0x0d00_0000 13 flash address + 0x0e00_0000 21 flash address + 0x0f00_0000 29 flash address + 0x1000_0000 6 flash address + 0x1100_0000 14 flash address + 0x1200_0000 22 flash address + 0x1300_0000 30 flash address + 0x1400_0000 7 flash address + 0x1500_0000 15 flash address + 0x1600_0000 23 flash address + 0x1700_0000 31 flash address + 0x1800_0000 8 flash address + 0x1900_0000 16 flash address + 0x1a00_0000 24 flash address + 0x1b00_0000 32 flash address + 0x1c00_0000 9 flash address + 0x1d00_0000 17 flash address + 0x1e00_0000 25 flash address + 0x1f00_0000 33 table 23-28. additional wait-state encoding (continued) memory address additional wait-stats
flash memory 23-50 freescale semiconductor pxs20 microcontroller reference manual, rev. 1
flexcan module freescale semiconductor 24-1 pxs20 microcontroller reference manual, rev. 1 chapter 24 flexcan module 24.1 introduction the flexcan module is a communication controller implementing the can protocol according to the can 2.0b protocol specification. a ge neral block diagram is shown in figure 24-1 , which describes the main sub-blocks implemented in the flexcan module, including two embedded memories, one for storing message buffers (mb) and another one for st oring rx individual mask registers. this device supports 32 message buffers. the functions of the s ub-modules are described in subsequent sections. figure 24-1. flexcan block diagram 544- bus interface unit max mb # (0?31) ip bus interface can message can tx can rx mb1 mb0 mb30 mb31 clocks, address & data buses, interrupt and test signals buffer management protocol interface byte ram message buffer storage 128- rximr1 rximr0 rximr30 rximr31 byte ram id mask storage
flexcan module 24-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 24.1.1 overview the can protocol was primarily, but not only, designed to be used as a vehicle serial data bus, meeting the specific requirements of this fi eld: real-time processing, reliable operation in the emi environment of a vehicle, cost-effectiveness and required bandwidth. the flexcan module is a full implementation of the can protocol specification, vers ion 2.0 b, which supports both standa rd and extended message frames. the message buffers are stored in an embe dded ram dedicated to the flexcan module. the can protocol interface (cpi) sub-module ma nages the serial comm unication on the can bus, requesting ram access for receiving and transmitting message frames, va lidating received messages and performing error handling. the me ssage buffer management (mbm ) sub-module handles message buffer selection for reception and transmission, taking care of arbitrat ion and id matching algorithms. the bus interface unit (biu) sub-module controls the acce ss to and from the internal interface bus, in order to establish connecti on to the cpu and to other bl ocks. clocks, address and data buses, interrupt outputs and test signals are accessed through the bus interface unit. 24.1.2 flexcan module features the flexcan module includes these distinctive features: ? full implementation of the can pr otocol specification, version 2.0b ? standard data and remote frames ? extended data and remote frames ? zero to eight bytes data length ? programmable bit rate up to 1 mbit/s ? content-related addressing ? 32 message buffers of zero to eight bytes data length ? each mb configurable as rx or tx, al l supporting standard and extended messages ? individual rx mask registers per message buffer ? includes 544 bytes of ram used for mb storage ? includes 128 bytes (32 mbs) of ram us ed for individual rx mask registers ? full featured rx fifo with storage capacity for 6 frames and internal pointer handling ? powerful rx fifo id filtering, capable of ma tching incoming ids against either 8 extended, 16 standard or 32 partial (8 bits) id s, with individual masking capability ? selectable backwards compatibilit y with previous flexcan version ? programmable clock source to th e can protocol interface, either bus clock or crystal oscillator ? unused mb and rx mask register space ca n be used as general purpose ram space ? listen only mode capability ? programmable loop-back mode supporting self-test operation ? programmable transmission priority scheme: lowest id, lowest buffer number or highest priority ? time stamp based on 16-bit free-running timer ? global network time, synchr onized by a specific message
flexcan module freescale semiconductor 24-3 pxs20 microcontroller reference manual, rev. 1 ? maskable interrupts ? independent of the transm ission medium (an external transceiver is assumed) ? short latency time due to an arbitration scheme for high-priority messages ? low power modes, with progra mmable wake up on bus activity note the individual rx mask per message buff er feature may not be available in low cost mcus. please consult the specific mcu documentation to find out if this feature is supported. 24.1.3 modes of operation the flexcan module has four func tional modes: normal mode (use r and supervisor), freeze mode, listen-only mode and loop-back mode. there are al so two low power modes: disable mode and stop mode. 24.1.3.1 normal mode (u ser or supervisor) in normal mode, the module operates receiving and/or transmitting message fram es, errors are handled normally and all the can protocol f unctions are enabled. user and superv isor modes differ in the access to some restricted control registers. 24.1.3.2 freeze mode it is enabled when the frz bit in the mcr register is asserted. if enabled, freez e mode is entered when the halt bit in mcr is set or when debug mode is requested at mcu le vel. in this mode, no transmission or reception of frames is done and sync hronicity to the can bus is lost. see section 24.4.9.1, freeze mode, for more information. 24.1.3.3 listen-only mode the module enters this mode when the lom bit in the control register is asserted. in this mode, transmission is disabled, all erro r counters are frozen and the module operates in a can error passive mode. only messages acknowledged by another can st ation will be received. if flexcan detects a message that has not been acknowledge d, it will flag a bit0 error (wit hout changing the rec), as if it was trying to acknowledge the message. 24.1.3.4 loop-back mode the module enters this mode when the lpb bit in the control register is assert ed. in this mode, flexcan performs an internal loop back that can be used fo r self test operation. the bit stream output of the transmitter is internally fed back to the receiver input. the rx can input pin is ignored and the tx can output goes to the recessive state (logic ?1?). flexc an behaves as it normally does when transmitting and treats its own transmitted messag e as a message received from a re mote node. in this mode, flexcan ignores the bit sent duri ng the ack slot in the can frame acknowle dge field to ensure proper reception of its own message. both transmit and receive interrupts are generated.
flexcan module 24-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 24.1.3.5 module disable mode: this low power mode is en tered when the mdis bit in the mcr register is asse rted. when disabled, the module shuts down the clocks to the can protocol interface a nd message buffer management sub-modules. exit from this mo de is done by negating the mdis bit in the mcr register. see section 24.4.9.2, module disable mode, for more information. 24.1.3.6 stop mode this low power mode is entered when stop mode is requested at mcu level. when in stop mode, the module puts itself in an inactive state and then inform s the cpu that the clocks can be shut down globally. exit from this mode happens when the stop mode request is removed or when activity is detected on the can bus and the self wake up mechanism is enabled. see section 24.4.9.3, stop mode, for more information. 24.2 external signal description the flexcan module has two i/o si gnals connected to the external mcu pins. these signals are summarized in table 24-1 and described in more detail in the next subsections. 24.2.1 can rx this pin is the receive pin from the can bus transceive r. dominant state is represented by logic level ?0?. recessive state is represented by logic level ?1?. 24.2.2 can tx this pin is the transmit pin to th e can bus transceiver. dominant stat e is represented by logic level ?0?. recessive state is represented by logic level ?1?. 24.3 memory map and register definition this section describes the registers and data structures in the flexca n module. the base address of the module depends on the particul ar memory map of the mcu. the addres ses presented here are relative to the base address. the address space occupied by flexcan has 96 bytes fo r registers starting at the module base address, followed by mb storage space in embedded ram st arting at address 0x0060, and an extra id mask storage space in a separate em bedded ram starting at address 0x0880. table 24-1. flexcan signals signal name 1 notes: 1 the actual mcu pins may have different names. please consult the device user guide for the actual signal names. direction description can rx input can receive pin can tx output can transmit pin
flexcan module freescale semiconductor 24-5 pxs20 microcontroller reference manual, rev. 1 24.3.1 flexcan memory mapping the memory map for the fl excan module is shown in table 24-2 . each individual register is identified by its complete name and the corresponding mnemon ic. the access type can be supervisor (s) or unrestricted (u). most of the regist ers can be configured to have either supervisor or unrestricted access by programming the supv bit in the mcr register. thes e registers are identified as s/u in the access column of table 24-2 . the rx global mask (rxgmask), rx buffer 14 mask (rx14mask) and the rx buffer 15 mask (rx15mask) registers are provided for backwards compatibility, a nd are not used when the bcc bit in mcr is asserted. the address ranges 0x0060?0x047f a nd 0x0880?0x097f are occupied by two separate embedded memories. the memory sizes are 544 and 128 bytes, so the address ranges 0x0280?0x047f and 0x0900?0x097f are considered reserved space. furthermore, if the bcc bit in mcr is negated, then the whole rx individual mask registers address range (0x0880?0x097f) is considered reserved space. note the individual rx mask per message buff er feature may not be available in low cost mcus. please consult the specific mcu documentation to find out if this feature is supported. if not supported, the address range 0x0880-0x097f is considered reserved spac e, independent of the value of the bcc bit.
flexcan module 24-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 the flexcan module stores can messages for tran smission and reception us ing a message buffer structure. each individual mb is formed by 16 bytes mapped on memory as described in table 24-3 . table 24-3 shows a standard/extended message buffer (mb0) memory map, using 16 bytes total (0x80 ? 0x8f space). 24.3.2 message buffer structure the message buffer structure used by the flexcan module is represented in figure 24-2 . both extended and standard frames (29-bit identifier and 11-bit identifier, re spectively) used in the can specification (version 2.0 part b) are represented. table 24-2. module memory map address use access type affected by hard reset affected by soft reset base + 0x0000 module configuration (mcr) s yes yes base + 0x0004 control register (ctrl) s/u yes no base + 0x0008 free running timer (timer) s/u yes yes base + 0x000c reserved base + 0x0010 rx global mask (rxgmask) s/u yes no base + 0x0014 rx buffer 14 mask (rx14mask) s/u yes no base + 0x0018 rx buffer 15 mask (rx15mask) s/u yes no base + 0x001c error counter register (ecr) s/u yes yes base + 0x0020 error and status register (esr) s/u yes yes base + 0x0024 reserved base + 0x0028 interrupt masks 1 (imask1) s/u yes yes base + 0x002c reserved base + 0x0030 interrupt flags 1 (iflag1) s/u yes yes base + 0x0034?0x005f reserved base + 0x0060?0x007f reserved base + 0x0080?0x017f message buffers mb0 ? mb15 s/u no no base + 0x0180?0x027f message buffers mb16 ? mb31 s/u no no base + 0x0280-087f reserved base + 0x0880-0x08bf rx individual mask registers rximr0-rximr15 s/u no no base + 0x08c0-0x08ff rx individual mask registers rximr16-rximr31 s/u no no base + 0x0900-0x097f reserved table 24-3. message buffer mb0 memory mapping address offset mb field 0x80 control and status (c/s) 0x84 identifier field 0x88 ? 0x8f data field 0 ? data field 7 (1 byte each)
flexcan module freescale semiconductor 24-7 pxs20 microcontroller reference manual, rev. 1 code ? message buffer code this 4-bit field can be accessed (re ad or write) by the cpu and by the flexcan module itself, as part of the message buffer matching and arbitra tion process. the encoding is shown in table 24-4 and table 24-5 . see section 24.4, functi onal description, for additional information. 0 2 3 4 7 8 9 10 11 12 13 14 15 16 23 24 31 0x0 code s r r i d e r t r length time stamp 0x4 prio id (standard/extended) id (extended) 0x8 data byte 0 data byte 1 data byte 2 data byte 3 0xc data byte 4 data byte 5 data byte 6 data byte 7 = unimplemented or reserved figure 24-2. message buffer structure table 24-4. message buffer code for rx buffers rx code before rx new frame description rx code after rx new frame comment 0000 inactive: mb is not active. ? mb does not participate in the matching process. 0100 empty: mb is active and empty. 0010 mb participates in the matching process. when a frame is received successfully, the code is automatically updated to full. 0010 full: mb is full. 0010 the act of reading the c/s word followed by unlocking the mb does not make the code return to empty. it remains full. if a new frame is written to the mb after the c/s word was read and the mb was unlocked, the code still remains full. 0110 if the mb is full and a new frame is overwritten to this mb before the cpu had time to read it, the code is automatically updated to overrun. refer to section 24.4.5, matching process, for details about overrun behavior. 0110 overrun: a frame was overwritten into a full buffer. 0010 if the code indicates overrun but the cpu reads the c/s word and then unlocks the mb, when a new frame is written to the mb the code returns to full. 0110 if the code already indicates overrun, and yet another new frame must be written, the mb will be overwritten again, and the code will remain overrun. refer to section 24.4.5, matching process, for details about overrun behavior. 0xy1 1 busy: flexcan is updating the contents of the mb. the cpu must not access the mb. 0010 an empty buffer was written with a new frame (xy was 01). 0110 a full/overrun buffer was overwritten (xy was 11).
flexcan module 24-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 srr ? substitute remote request fixed recessive bit, used only in extended format. it must be set to ?1? by the user for transmission (tx buffers) and will be stored with the value received on th e can bus for rx receiv ing buffers. it can be received as either recessive or dominant. if flexcan receives this bi t as dominant, then it is interpreted as arbitration loss. 1 = recessive value is compulsory for transmission in extended format frames 0 = dominant is not a valid value for transmission in extended format frames ide ? id extended bit this bit identifies whether the fram e format is sta ndard or extended. 1 = frame format is extended 0 = frame format is standard rtr ? remote transmission request this bit is used for requesting transmissions of a data frame. if flexcan transmits this bit as ?1? (recessive) and receives it as ?0? (dominant), it is interpreted as arbitration loss. if this bit is transmitted as ?0? (dominant), then if it is received as ?1? (recessive), the flex can module treats it as bit error. if the value received matches the value transmitted, it is considered as a su ccessful bit transmission. notes: 1 note that for tx mbs (see ta b l e 2 4 - 5 ), the busy bit should be ignored up on read, except when aen bit is set in the mcr register. table 24-5. message buffer code for tx buffers rtr initial tx code code after successful transmission description x 1000 ? inactive: mb does not partic ipate in the arbitration process. x 1001 ? abort: mb was configured as tx and cpu aborted the transmission. this code is only valid when aen bit in mcr is asserted. mb does not participate in the arbitration process. 0 1100 1000 transmit data frame unconditionally once. after transmission, the mb automatically returns to the inactive state. 1 1100 0100 transmit remote frame unconditionally once. after transmission, the mb automatically becomes an rx mb with the same id. 0 1010 1010 transmit a data frame whenever a remote request frame with the same id is received. this mb participates simultaneously in both the matching and arbitration processes. the matching process compares the id of the incoming remote request frame with the id of the mb. if a match occurs this mb is allowed to participate in the current arbitration process and the code field is automatically updated to ?1110? to allow the mb to participate in future arbitration runs. when the frame is eventually transmitted successfully, the code automatically returns to ?1010? to restart the process again. 0 1110 1010 this is an intermediate code t hat is automatically written to the mb by the mbm as a result of match to a remote request frame. the data frame will be transmitted unconditionally once and then the code will automatically return to ?1010?. the cpu can also write this code with the same effect.
flexcan module freescale semiconductor 24-9 pxs20 microcontroller reference manual, rev. 1 1 = indicates the current mb has a remote frame to be transmitted 0 = indicates the current mb has a data frame to be transmitted length ? length of data in bytes this 4-bit field is the le ngth (in bytes) of the rx or tx data, wh ich is located in offset 0x8 through 0xf of the mb space (see figure 24-2 ). in reception, this field is writ ten by the flexcan module, copied from the dlc (data length code) fiel d of the received frame. in tran smission, this fiel d is written by the cpu and corresponds to the dlc field value of the frame to be transmitted. when rtr=1, the frame to be transmitted is a remo te frame and does not include the da ta field, regardle ss of the length field. time stamp ? free-running counter time stamp this 16-bit field is a copy of the free-running timer, captured for tx and rx frames at the time when the beginning of the identifier field appears on the can bus. prio ? local priority this 3-bit field is only used when lprio_en bit is set in mcr and it only makes sense for tx buffers. these bits are not transmitted. they are appended to the regular id to define the transmission priority. see section 24.4.3, arbitration process. id ? frame identifier in standard frame format, only the 11 most significant bits (3 to 13) are used for frame identification in both receive and transmit cases. the 18 least significant bits are ignored. in extended frame format, all bits are used for fram e identification in both receive and transmit cases. data ? data field up to eight bytes can be used for a data frame. for rx frames, the data is stored as it is received from the can bus. for tx frames, the cpu prepares the data field to be transm itted within the frame. 24.3.3 rx fifo structure when the fen bit is set in the mcr, the memory ar ea from 0x80 to 0xfc (which is normally occupied by mbs 0 to 7) is used by the reception fifo engine. figure 24-3 shows the rx fifo data structure. the region 0x80-0x8c contains an mb stru cture which is the port through whic h the cpu reads data from the fifo (the oldest frame r eceived and not read yet). the region 0x90- 0xdc is reserved for internal use of the fifo engine. the region 0xe0-0xfc contains an 8-en try id table that specifies filtering criteria for accepting frames into the fifo. figure 24-4 shows the three different format s that the elements of the id table can assume, depending on the idam field of the mcr. note that all elements of the table must have the same format. see section 24.4.7, rx fifo, for more information.
flexcan module 24-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 rem ? remote frame this bit specifies if remote frames are accepte d into the fifo if they match the target id. 1 = remote frames can be accepte d and data frames are rejected 0 = remote frames are rejected and data frames can be accepted ext ? extended frame specifies whether extended or standard frames are a ccepted into the fifo if they match the target id. 1 = extended frames can be accepted and standard frames are rejected 0 = extended frames are rejected and standard frames can be accepted 0 3 7 8 9 10 11 12 13 14 15 16 23 24 31 0x80 s r r i d e r t r length time stamp 0x84 id (standard/extended) id (extended) 0x88 data byte 0 data byte 1 data byte 2 data byte 3 0x8c data byte 4 data byte 5 data byte 6 data byte 7 0x90 reserved to 0xdc 0xe0 id table 0 0xe4 id table 1 0xe8 id table 2 0xec id table 3 0xf0 id table 4 0xf4 id table 5 0xf8 id table 6 0xfc id table 7 = unimplemented or reserved figure 24-3. rx fifo structure 0 1 2 7 8 12 13 15 16 17 18 23 24 28 30 31 a r e m e x t rxida (standard = 2-12, extended = 2-30) b r e m e x t rxidb_0 (standard = 29-19, extended = 29-16) r e m e x t rxidb_1 (standard = 13-3, extended = 13-0) c rxidc_0 (std/ext = 31-24) rxidc_1 (std/ext = 23-16) rxidc_2 (std/ext = 15-8) rxidc_3 (std/ext = 7-0) = unimplemented or reserved figure 24-4. id table 0 - 7
flexcan module freescale semiconductor 24-11 pxs20 microcontroller reference manual, rev. 1 rxida ? rx frame identifier (format a) specifies an id to be used as acc eptance criteria for the fifo. in the standard frame format, only the 11 most significant bits (2 to 12) are used for fr ame identification. in the extended frame format, all bits are used. rxidb_0, rxidb_1 ? rx fram e identifier (format b) specifies an id to be used as acceptance criteria for the fifo. in the standard frame format, the 11 most significant bits (a full standard id) (2 to 12 and 18 to 28) are used for frame identification. in the extended frame format, all 14 bits of the field are compared to the 14 most significant bits of the received id. rxidc_0, rxidc_1, rxidc_2, rxidc_3 ? rx frame identifier (format c) specifies an id to be used as acceptance criteria for the fifo. in both standard and extended frame formats, all 8 bits of the field are compared to the 8 most significant bits of the received id. 24.3.4 register descriptions the flexcan registers are described in this section in as cending address order. 24.3.4.1 module configur ation register (mcr) this register defines global system configurations, such as the m odule operation mode (e.g., low power) and maximum message buffer configur ation. this register can be acce ssed at any time, however some fields must be changed only during freeze mode. find more information in the fields de scriptions ahead. figure 24-5. module configuration register (mcr) base + 0x0000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r mdis frz fen halt not_ rdy wak _msk soft _rst frz_ ack supv slf_ wak wrn _en lpm_ ack 0 0 srx _dis bcc w reset: note 1 notes: 1 reset value of this bit is different on various platfo rms. consult the specific m cu documentation to determine its value. 1 0 1 1 0 0 note 2 2 different on various platforms, but it is always the opposite of the mdis reset value. 1 0 0 note 3 3 different on various platforms, but it is always the same as the mdis reset value. 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 lpri o_en aen 0 0 idam 0 0 maxmb w reset: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 = unimplemented or reserved
flexcan module 24-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 mdis ? module disable this bit controls whether flexca n is enabled or not. wh en disabled, flexcan shuts down the clocks to the can protocol interface a nd message buffer management sub-m odules. this is the only bit in mcr not affected by soft reset. see section 24.4.9.2, module disable mode, for more information. 1 = disable the flexcan module 0 = enable the flexcan module frz ? freeze enable the frz bit specifies the flexcan behavior when th e halt bit in the mcr regi ster is set or when debug mode is requested at mcu level. when frz is asserted, flexcan is enabled to enter freeze mode. negation of this bit field causes flexcan to exit from freeze mode. 1 = enabled to enter freeze mode 0 = not enabled to enter freeze mode fen ? fifo enable this bit controls whether the fifo feature is enab led or not. when fen is set, mbs 0 to 7 cannot be used for normal reception and transmission because the corresponding memory region (0x80-0xff) is used by the fifo engine. see section 24.3.3, rx fifo structure and rx fifo , for more information. this bit must be writ ten in freeze mode only. 1 = fifo enabled 0 = fifo not enabled halt ? halt flexcan assertion of this bit puts the flexcan module in to freeze mode. the cpu should clear it after initializing the message buffers and control regist er. no reception or tran smission is performed by flexcan before this bit is cleared. while in fr eeze mode, the cpu has write access to the error counter register, that is otherw ise read-only. freeze mode can not be entered while flexcan is in any of the low power modes. see section 24.4.9.1, freeze mode, for more information. 1 = enters freeze mode if the frz bit is asserted. 0 = no freeze mode request. not_rdy ? flexcan not ready this read-only bit indicates that flexcan is either in disable mode , stop mode or freeze mode. it is negated once flexcan has exited these modes. 1 = flexcan module is either in di sable mode, stop m ode or freeze mode 0 = flexcan module is either in normal mode, listen-only mode or loop-back mode wak_msk ? wake up interrupt mask this bit enables the wake up interrupt generation. 1 = wake up interrupt is enabled 0 = wake up interrupt is disabled
flexcan module freescale semiconductor 24-13 pxs20 microcontroller reference manual, rev. 1 soft_rst ? soft reset when this bit is asserted, flexca n resets its internal state machin es and some of the memory mapped registers. the following regist ers are reset: mcr (except the mdis bit), timer, ecr, esr, imask1, iflag1. configuration regi sters that control the interface to the can bus are not affected by soft reset. the followi ng registers are unaffected: ? ctrl ? rximr0?rximr31 ? rxgmask, rx14mask, rx15mask ? all message buffers the soft_rst bit can be a sserted directly by the cpu when it wr ites to the mcr register, but it is also asserted when global soft rese t is requested at mcu level. sin ce soft reset is synchronous and has to follow a request/acknowledge procedure across clock domains, it may take some time to fully propagate its effect. the soft_rst bit remains asse rted while reset is pending, and is automatically negated when reset completes. therefore, software can poll this bit to know when the soft reset has completed. soft reset cannot be applied while clocks are shut down in any of the low power modes. the module should be first removed from low power m ode, and then soft reset can be applied. 1 = resets the registers marked as ?affected by soft reset? in table 24-2 0 = no reset request frz_ack ? freeze mode acknowledge this read-only bit indicat es that flexcan is in freeze mode and its presca ler is stopped. the freeze mode request cannot be granted until current tran smission or reception pr ocesses have finished. therefore the software can poll th e frz_ack bit to know when flexca n has actually entered freeze mode. if freeze mode requ est is negated, then this bit is negated once the flexcan prescaler is running again. if freeze mode is re quested while flexcan is in any of the low power modes, then the frz_ack bit will only be set when the low power mode is exited. see section 24.4.9.1, freeze mode, for more information. 1 = flexcan in freeze mode, prescaler stopped 0 = flexcan not in freeze mode, prescaler running supv ? supervisor mode this bit configures some of the fl excan registers to be ei ther in supervisor or unrestricted memory space. the registers affected by this bit are marked as s/u in the access type column of table 24-2 . reset value of this bit is ?1?, so the affected registers st art with supervisor acce ss restrictions. this bit should be written in freeze mode only. 1 = affected registers are in supervisor memory space. any acce ss without supervisor permission behaves as though the access was done to an unimplemented register location 0 = affected registers are in unrestricted memory space
flexcan module 24-14 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 slf_wak ? self wake up this bit enables the self wake up f eature when flexcan is in stop mode . if this bit had been asserted by the time flexcan entered stop m ode, then flexcan will look for a recessive to dominant transition on the bus during these modes. if a transition from re cessive to dominant is detected during stop mode, then flexcan generates, if enabled to do so, a wake up interrupt to the cpu so that it can resume the clocks globally. this bit can not be wr itten while the module is in stop mode. 1 = flexcan self wake up feature is enabled 0 = flexcan self wake up feature is disabled wrn_en ? warning interrupt enable when asserted, this bit enables the generation of the twrn_int a nd rwrn_int flags in the error and status register. if wrn_en is negated, the twrn_int and rwrn_int flags will always be zero, independent of the values of the error counter s, and no warning interrupt will ever be generated. this bit must be writ ten in freeze mode only. 1 = twrn_int and rwrn_int bits are set when the respective e rror counter transition from <96 to ? 96. 0 = twrn_int and rwrn_int bits are zero, inde pendent of the values in the error counters. lpm_ack ? low power mode acknowledge this read-only bit indicates that fl excan is either in disable mode or stop mode. eith er of these low power modes can not be entered until all current transmissi on or reception processe s have finished, so the cpu can poll the lpm_ack bit to know when flexcan has actually entered low power mode. see section 24.4.9.2, module disable mode, and section 24.4.9.3, stop mode, for more information. 1 = flexcan is either in disable mode or stop mode 0 = flexcan not in any of the low power modes srx_dis ? self reception disable this bit defines whether flexcan is allowed to rece ive frames transmitted by itself. if this bit is asserted, frames transmitted by th e module will not be stored in any mb, regardless if the mb is programmed with an id that matches the transmitted frame, and no interrupt flag or interrupt signal will be generated due to the frame reception. this bit must be written in freeze mode only. 1 = self reception disabled 0 = self reception enabled bcc ? backwards compatibility configuration this bit is provided to support ba ckwards compatibility with previ ous flexcan versions. when this bit is negated, the following configuration is applied: ? for mcus supporting individual rx id masking, this featur e is disabled. instead of individual id masking per mb, flexcan uses its previous masking scheme with rxgmask, rx14mask and rx15mask. ? the reception queue feature is disabled. upon receiving a message, if the first mb with a matching id that is found is still occupied by a previous unread message, flexcan wi ll not look for another matching mb. it will override this mb with the new message and set the code field to ?0110? (overrun).
flexcan module freescale semiconductor 24-15 pxs20 microcontroller reference manual, rev. 1 upon reset this bit is negated, allowing legacy softwa re to work without modi fication. this bit must be written in freeze mode only. 1 = individual rx masking and queue feature are enabled. 0 = individual rx masking and queue feature are disabled. lprio_en? local priority enable this bit is provided for backwards compatibility reas ons. it controls whether th e local priority feature is enabled or not. it is used to extend the id used during the arbitration process. with this extended id concept, the arbitration process is done based on the full 32-bit word, but the actual tran smitted id still has 11-bit for standard fram es and 29-bit for extended frames. this bit must be writte n in freeze mode only. 1 = local priority enabled 0 = local priority disabled aen? abort enable this bit is supplied for backward s compatibility reasons. when asse rted, it enables the tx abort feature. this feature gua rantees a safe procedure for aborting a pending transm ission, so that no frame is sent in the can bus without notification. th is bit must be written in freeze mode only. 1 = abort enabled 0 = abort disabled idam ? id acceptance mode this 2-bit field identifies the format of the elem ents of the rx fifo filter table, as shown in table 24-6 . note that all elements of the tabl e are configured at the same time by this field (they are all the same format). see section 24.3.3, rx fifo structure . this bit must be written in freeze mode only. maxmb ? maximum number of message buffers this 6-bit field defines the maximu m number of message buffers that will take part in the matching and arbitration processes. the rese t value (0x0f) is equiva lent to 16 mb configur ation. this field must be changed only while th e module is in freeze mode. maximum mbs in use = maxmb + 1. note maxmb must be programmed with a va lue smaller or equal to the number of available message buffers, otherw ise flexcan can tran smit and receive wrong messages. table 24-6. idam coding idam format explanation 0b00 a one full id (standard or extended) per filter element. 0b01 b two full standard ids or two partia l 14-bit extended ids per filter element. 0b10 c four partial 8-bit ids (standard or extended) per filter element. 0b11 d all frames rejected.
flexcan module 24-16 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 24.3.4.2 control register (ctrl) this register is defined for specifi c flexcan control features related to the can bus, such as bit-rate, programmable sampling point within an rx bit, loop back mode, listen only mode, bus off recovery behavior and interrupt enabling (bus-off, error, warni ng). it also determines th e division factor for the clock prescaler. this register can be accessed at any time, however some fields must be changed only during either disable mode or fr eeze mode. find more information in the fields descriptions ahead. figure 24-6. control register (ctrl) presdiv ? prescaler division factor this 8-bit field defines the ratio between the cp i clock frequency and the serial clock (sclock) frequency. the sclock period defines the time quantum of the can protocol. for the reset value, the sclock frequency is equal to the cpi clock freque ncy. the maximum value of this register is 0xff, that gives a minimum sclock frequency equal to the cpi clock frequency divided by 256. for more information refer to section 24.4.8.4, protocol timing. this bit must be written in freeze mode only. sclock frequency = cpi clock frequency / (presdiv + 1) rjw ? resync jump width this 2-bit field defines the maximum number of time quanta 1 that a bit time can be changed by one re-synchronization. the valid pr ogrammable values are 0 ? 3 . this bit must be wr itten in freeze mode only. resync jump width = rjw + 1. pseg1 ? phase segment 1 this 3-bit field defines the length of phase buffer segment 1 in the bit time. the valid programmable values are 0 ? 7 . this bit must be writ ten in freeze mode only. phase buffer segment 1 = ( pseg1 + 1) x time-quanta. base + 0x0004 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r presdiv rjw pseg1 pseg2 w re- set: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r boff _msk err_ msk clk_ src lpb twr n_ms k rwr n_ms k 0 0 smp boff _rec tsyn lbuf lom propseg w re- set: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved 1. one time quantum is equal to the sclock period.
flexcan module freescale semiconductor 24-17 pxs20 microcontroller reference manual, rev. 1 pseg2 ? phase segment 2 this 3-bit field defines the length of phase buffer segment 2 in the bit time. the valid programmable values are 1 ? 7 . this bit must be writ ten in freeze mode only. phase buffer segment 2 = ( pseg2 + 1) x time-quanta. boff_msk ? bus off mask this bit provides a mask for the bus off interrupt. 1 = bus off interrupt enabled 0 = bus off interrupt disabled err_msk ? error mask this bit provides a mask for the error interrupt. 1 = error interrupt enabled 0 = error interrupt disabled clk_src ? can engine clock source this bit selects the clock source to the can protocol interface (cpi) to be either the peripheral clock (driven by the fmpll) or the crystal oscillator clock. the selected cloc k is the one fed to the prescaler to generate the serial clock (scl ock). in order to guarantee reliab le operation, this bit must only be changed while the module is in disable mode. see section 24.4.8.4, protocol timing, for more information. 1 = the can engine clock source is the bus clock 0 = the can engine clock source is the oscillator clock note this clock selection featur e may not be available in all mcus. a particular mcu may not have a fmpll, in which case it would have only the oscillator clock, or it may use only the fmpll clock feeding the flexcan module. in these cases, this bit has no effect on the module operation. in order to guarantee reliable operat ion, the selected ca n protocol interface (cpi) clock should not be faster as the the peripheral clock. twrn_msk ? tx warning interrupt mask this bit provides a mask for the tx warning interrupt associated with the twrn_int flag in the error and status register. this bit has no effect if the wrn_en bit in mcr is negated and it is read as zero when wrn_en is negated. 1 = tx warning interrupt enabled 0 = tx warning interrupt disabled rwrn_msk ? rx warning interrupt mask this bit provides a mask for the rx warning interrupt associated with the rwrn_int flag in the error and status register. this bit has no effect if the wrn_en bit in mcr is negated and it is read as zero when wrn_en is negated.
flexcan module 24-18 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 1 = rx warning interrupt enabled 0 = rx warning interrupt disabled lpb ? loop back this bit configures flexcan to operate in loop-back mode. in this mode, flexcan performs an internal loop back that can be used for self test operation. the bit stream output of the transmitter is fed back internally to the receiver input. the rx can input pin is ignored and the tx can output goes to the recessive state (logic ?1?). flexcan behaves as it normally does when transmitting, and treats its own transmitted message as a message received from a remote node. in this mode, flexcan ignores the bit sent during the ack slot in the can frame acknowledge field, generating an internal acknowledge bit to ensure proper reception of its own message. both transmit and receive interrupts are generated. this bit must be written in freeze mode only. 1 = loop back enabled 0 = loop back disabled smp ? sampling mode this bit defines the sampling mode of can bits at the rx input. this bit must be written in freeze mode only. 1 = three samples are used to dete rmine the value of the received bit: the regul ar one (sample point) and 2 preceding samples, a majority rule is used 0 = just one sample is used to determine the bit value boff_rec ? bus off recovery mode this bit defines how flexca n recovers from bus off state. if this bit is negated, au tomatic recovering from bus off state occurs according to the can sp ecification 2.0b. if the bit is asserted, automatic recovering from bus off is disabled and the module remains in bus off state until the bit is negated by the user. if the negation occurs before 128 sequences of 11 recessi ve bits are dete cted on the can bus, then bus off recovery happens as if the boff_ rec bit had never been as serted. if the negation occurs after 128 sequences of 11 rece ssive bits occurred, then flexca n will re-synchroni ze to the bus by waiting for 11 recessive bits before joining the bus. after negation, the boff_rec bit can be re-asserted again during bus off, but it will only be effective the next time the module enters bus off. if boff_rec was negated when the module entered bus off, asserting it during bus of f will not be effective for the current bus off recovery. 1 = automatic recovering from bus off state disabled 0 = automatic recovering from bus off stat e enabled, according to can spec 2.0 part b tsyn ? timer sync mode this bit enables a mechanism that resets the fr ee-running timer each time a message is received in message buffer 0. this feature provides means to synchronize multiple flex can stations with a special ?sync? message (i.e., global network time). if the fen bit in mcr is set (fifo enabled), mb8 is used for timer synchronizatio n instead of mb0. this bit must be written in freeze mode only. 1 = timer sync feature enabled 0 = timer sync feature disabled
flexcan module freescale semiconductor 24-19 pxs20 microcontroller reference manual, rev. 1 lbuf ? lowest buffer transmitted first this bit defines the ordering mechanism for messa ge buffer transmission. when asserted, the lprio_en bit does not affect the pr iority arbitration. this bit must be written in freeze mode only. 1 = lowest number buffer is transmitted first 0 = buffer with highest priority is transmitted first lom ? listen-only mode this bit configures flexcan to operate in listen only mode. in this mode, transmission is disabled, all error counters are frozen and the module opera tes in a can error passive mode. only messages acknowledged by another can station will be received. if flexcan de tects a message that has not been acknowledged, it will flag a bit0 error (without changing the rec), as if it was trying to acknowledge the message. this bit mu st be written in freeze mode only. 1 = flexcan module operates in listen only mode 0 = listen only mode is deactivated propseg ? propagation segment this 3-bit field defines the lengt h of the propagation segment in th e bit time. the va lid programmable values are 0 ? 7. this bit must be written in freeze mode only. propagation segment time = (propseg + 1) * time-quanta. time-quantum = one sclock period. 24.3.4.3 free running timer (timer) this register represents a 16-bit free running counter that can be read and written by the cpu. the timer starts from 0x0000 after reset, counts linearly to 0xffff, and wraps around. the timer is clocked by the flex can bit-clock (which de fines the baud rate on the can bus). during a message transmission/recepti on, it increments by one for each bit that is received or transmitted. when there is no message on the bus, it counts using the previously program med baud rate. du ring freeze mode, the timer is not incremented. the timer value is captured at the beginning of the identifier field of any frame on the can bus. this captured value is written into the time stamp entry in a message buffer after a successful reception or transmission of a message. writing to the timer is an indirect operation. the data is first written to an auxili ary register and then an internal request/acknowledge procedur e across clock domains is executed. all this is transparent to the user, except for the fact that the da ta will take some time to be actuall y written to the register. if desired, software can poll the register to discove r when the data was actually written.
flexcan module 24-20 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 24-7. free running timer (timer) 24.3.4.4 rx global mask (rxgmask) this register is provided for legacy support and for lo w cost mcus that do not have the individual masking per message buffer feature. for mcus supporting individua l masks per mb, setti ng the bcc bit in mcr causes the rxgmask regi ster to have no effect on the m odule operation. for mcus not supporting individual masks per mb, this re gister is always effective. rxgmask is used as acceptance mask for all rx mbs, excluding mbs 14 ? 15, which have individual mask registers. when the fen bit in mcr is set (fifo enabled), the rxgmask also applies to all elements of the id filter table, except elements 6-7, which have individual masks. refer to section 24.4.7, rx fifo for important details on usage of rxgm ask on filtering process for rx fifo. the contents of this register must be programmed while the module is in freeze mode, and must not be modified when the module is tr ansmitting or r eceiving frames. figure 24-8. rx global mask register (rxgmask) mi31?mi0 ? mask bits for normal rx mbs, the mask bits affect the id filter programmed on the mb. for the rx fifo, the mask bits affect all bits programmed in the filter table (id, ide, rtr). base + 0x0008 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r timer w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved base + 0x0010 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r mi31 mi30 mi29 mi28 mi27 mi26 mi25 mi24 mi23 mi22 mi21 mi20 mi19 mi18 mi17 mi16 w reset: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r mi15 mi14 mi13 mi12 mi11 mi10 mi9 mi8 mi7 mi6 mi5 mi4 mi3 mi2 mi1 mi0 w reset: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 = unimplemented or reserved
flexcan module freescale semiconductor 24-21 pxs20 microcontroller reference manual, rev. 1 1 = the corresponding bit in the filter is checked against the one received 0 = the corresponding bit in the filter is ?don?t care? 24.3.4.5 rx 14 mask (rx14mask) this register is provided for legacy support and for lo w cost mcus that do not have the individual masking per message buffer feature. for mcus supporting individua l masks per mb, setti ng the bcc bit in mcr causes the rx14mask register to ha ve no effect on the module operation. rx14mask is used as acceptance mask for the identi fier in message buffer 14. when the fen bit in mcr is set (fifo enabled), the rxg14mask also applies to element 6 of the id filt er table. this register has the same structure as th e rx global mask register. refer to section 24.4.7, rx fifo for important details on usage of rx14mask on filtering process for rx fifo. the contents of this register must be programmed while the module is in freeze mode, and must not be modified when the module is tr ansmitting or r eceiving frames. ? address offset: 0x14 ? reset value: 0xffff_ffff 24.3.4.6 rx 15 mask (rx15mask) this register is provided for legacy support and for lo w cost mcus that do not have the individual masking per message buffer feature. for mcus supporting individua l masks per mb, setti ng the bcc bit in mcr causes the rx15mask register to ha ve no effect on the module operation. when the bcc bit is negated, rx15mask is used as ac ceptance mask for the identifier in message buffer 15. when the fen bit in mcr is set (fifo enabled), the rxg15mask also applies to element 7 of the id filter table. this register has the same structure as the rx global mask register. refer to section 24.4.7, rx fifo for important details on usage of rx15mask on filtering process for rx fifo. the contents of this register must be programmed while the module is in freeze mode, and must not be modified when the module is tr ansmitting or r eceiving frames. ? address offset: 0x18 ? reset value: 0xffff_ffff 24.3.4.7 error counte r register (ecr) this register has two 8-bit fields reflecting the value of two flex can error counters: transmit error counter (tx_err_counter field) and recei ve error counter (rx_err_counter field) . the rules for increasing and decreasing these c ounters are described in the can protocol and are completely implemented in the flexcan module. both counters are read only except in freeze mode, where they can be written by the cpu.
flexcan module 24-22 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 writing to the error counter register while in free ze mode is an indirect ope ration. the data is first written to an auxiliary register an d then an internal request/acknowle dge procedure acro ss clock domains is executed. all this is transparent to the user, except for the fact that the data wi ll take some time to be actually written to the register. if desired, software can poll the regist er to discover when the data was actually written. flexcan responds to any bus state as described in th e protocol, e.g. transmit ?e rror active? or ?error passive? flag, delay its transmission start time (?error passive?) and avoid any influence on the bus when in ?bus off? state. the following are the basic rules for flexcan bus state transitions. ? if the value of tx_err_counter or rx_err_counter increases to be greater than or equal to 128, the flt_conf field in the error and status register is updated to reflect ?error passive? state. ? if the flexcan state is ?error passive?, and either tx_err_counter or rx_err_counter decrements to a value less than or equal to 127 while the other already sati sfies this condition, the flt_conf field in the error and status register is updated to reflect ?error active? state. ? if the value of tx_err_c ounter increases to be greater than 255, the flt_conf field in the error and status register is updated to reflect ?bus off? state, and an interrupt may be issued. the value of tx_err_counter is then reset to zero. ? if flexcan is in ?bus off? state, then tx_err_co unter is cascaded together with another internal counter to count the 128th occurrences of 11 consecutive recessive bits on the bus. hence, tx_err_counter is reset to zero a nd counts in a manner where the in ternal counter counts 11 such bits and then wraps around wh ile incrementing the tx_err_counter. when tx_err_counter reaches the value of 128, the flt_conf field in th e error and status register is updated to be ?error active? and both error counters are reset to zero. at any instance of dominant bit following a stream of less than 11 consecutive recessive bits, the internal coun ter resets itself to zero without affecting the tx_err_counter value. ? if during system start-up, only one node is operati ng, then its tx_err_counter increases in each message it is trying to transmit, as a result of acknowledge erro rs (indicated by the ack_err bit in the error and status register). after the transi tion to ?error passive? state, the tx_err_counter does not increment anymore by acknow ledge errors. therefore the device never goes to the ?bus off? state. ? if the rx_err_counter increases to a value greater than 127, it is not incremented further, even if more errors are detected while being a receiver. at the next successful message reception, the counter is set to a value between 119 and 127 to resume to ?error active? state.
flexcan module freescale semiconductor 24-23 pxs20 microcontroller reference manual, rev. 1 figure 24-9. error counter register (ecr) 24.3.4.8 error and status register (esr) this register reflects various error conditions, some genera l status of the de vice and it is th e source of four interrupts to the cpu. the reported er ror conditions (bits 16-21) are those th at occurred since the last time the cpu read this register. the cpu read acti on clears bits 16-23. bits 22-28 are status bits. most bits in this register are read only, ex cept twrn_int, rwrn_int, boff_int, wak_int and err_int, that are interrupt flags th at can be cleared by writ ing ?1? to them (writing ?0? has no effect). see section 24.4.10, interrupts, for more details. figure 24-10. error and status register (esr) twrn_int ? tx warning interrupt flag if the wrn_en bit in mcr is a sserted, the twrn_int bit is set when the tx_wrn flag transition from ?0? to ?1?, meaning that the tx error coun ter reached 96. if the corresponding mask bit in the control register (twrn_msk) is se t, an interrupt is generated to the cpu. this bit is cleared by writing it to ?1?. writing ?0? has no effect. 1 = the tx error counter transition from < 96 to ? 96 0 = no such occurrence base + 0x001c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rx_err_counter tx_err_counter w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved base + 0x0020 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 twrn _int rwrn _int w w1c w1c reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r bit1_ err bit0_ err ack_ err crc_ err frm_ err stf_ err tx_w rn rx_ wrn idle txrx flt_conf 0 boff _int err_ int wak_ int w w1c w1c w1c reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved
flexcan module 24-24 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 rwrn_int ? rx warning interrupt flag if the wrn_en bit in mcr is a sserted, the rwrn_int bi t is set when the rx_wrn flag transition from ?0? to ?1?, meaning that the rx error count ers reached 96. if the corresponding mask bit in the control register (rwrn_msk) is se t, an interrupt is generated to the cpu. this bit is cleared by writing it to ?1?. writing ?0? has no effect. 1 = the rx error counter transition from < 96 to ? 96 0 = no such occurrence bit1_err ? bit1 error this bit indicates when an inconsistency occurs between the transmitted and the received bit in a message. 1 = at least one bit sent as recessive is received as dominant 0 = no such occurrence note this bit is not set by a transmitter in ca se of arbitration fi eld or ack slot, or in case of a node sending a passive er ror flag that detects dominant bits. bit0_err ? bit0 error this bit indicates when an inconsistency occurs between the transmitted and the received bit in a message. 1 = at least one bit sent as dominant is received as recessive 0 = no such occurrence ack_err ? acknowledge error this bit indicates that an acknowle dge error has been detected by th e transmitter node, i.e., a dominant bit has not been detected during the ack slot. 1 = an ack error occurred since last read of this register 0 = no such occurrence crc_err ? cyclic redundancy check error this bit indicates that a crc error has been detect ed by the receiver node, i.e ., the calculated crc is different from the received. 1 = a crc error occurred since last read of this register. 0 = no such occurrence frm_err ? form error this bit indicates that a form erro r has been detected by the receiver node, i.e., a fixed-form bit field contains at least one illegal bit. 1 = a form error occurred since last read of this register 0 = no such occurrence stf_err ? stuffing error this bit indicates that a stuf fing error has been detected.
flexcan module freescale semiconductor 24-25 pxs20 microcontroller reference manual, rev. 1 1 = a stuffing error occurred sin ce last read of this register. 0 = no such occurrence. tx_wrn ? tx error warning this bit indicates when repetitive erro rs are occurring during message transmission. 1 = tx_err_counter ? 96 0 = no such occurrence rx_wrn ? rx error warning this bit indicates when repetitive er rors are occurring during message reception. 1 = rx_err_counter ?? 96 0 = no such occurrence idle ? can bus idle state this bit indicates when can bus is in idle state. 1 = can bus is now idle 0 = no such occurrence txrx ? current flexcan stat us (transmitti ng/receiving) this bit indicates if flexcan is transmitting or receiving a message when the can bus is not in idle state. this bit has no mean ing when idle is asserted. 1 = flexcan is transm itting a message (idle=0) 0 = flexcan is receiving a message (idle=0) flt_conf ? fault confinement state this 2-bit field indicates the confinement state of the flexcan module, as shown in table 24-7 . if the lom bit in the control register is asserted, the flt_conf field will indicate ?error passive?. since the control register is not affected by soft reset, the flt_c onf field will not be affected by soft reset if the lom bit is asserted. boff_int ? ?bus off? interrupt this bit is set when flexcan enters ?bus off? state. if the corresponding mask bit in the control register (boff_msk) is set, an in terrupt is generated to the cpu. th is bit is cleared by writing it to ?1?. writing ?0? has no effect. 1 = flexcan module ente red ?bus off? state 0 = no such occurrence table 24-7. fault confinement state value meaning 00 error active 01 error passive 1x bus off
flexcan module 24-26 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 err_int ? error interrupt this bit indicates that at least one of the error bits (bits 16-21) is set. if the corresponding mask bit in the control register (err_msk) is set, an interrupt is generated to the cpu. this bit is cleared by writing it to ?1?.writing ?0? has no effect. 1 = indicates setting of any error b it in the error a nd status register 0 = no such occurrence wak_int ? wake-up interrupt when flexcan is in stop mode and a recessive to dominant transition is detected on the can bus and if the wak_msk bit in the mcr register is set, an interrupt is generated to the cpu. this bit is cleared by writing it to ?1?. writing ?0? has no effect. 1 = indicates a recessive to dominant transiti on received on the can bus when the flexcan module is in stop mode 0 = no such occurrence 24.3.4.9 interrupt mas ks 1 register (imask1) this register allows to enable or disable any number of a ra nge of 32 message buffer interrupts. it contains one interrupt mask bit per buffer, en abling the cpu to determine which bu ffer generates an interrupt after a successful transmission or re ception (i.e., when the corresponding iflag1 bit is set). figure 24-11. interrupt masks 1 register (imask1) buf31m ? buf0m ? buffer mb i mask each bit enables or disables the respective fl excan message buffer (mb0 to mb31) interrupt. 1 = the corresponding buffer interrupt is enabled 0 = the corresponding buffer interrupt is disabled note setting or clearing a bit in the imask1 register can assert or negate an interrupt request, if the corresponding iflag1 bit is set. base + 0x0028 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r buf 31m buf 30m buf 29m buf 28m buf 27m buf 26m buf 25m buf 24m buf 23m buf 22m buf 21m buf 20m buf 19m buf 18m buf 17m buf 16m w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r buf 15m buf 14m buf 13m buf 12m buf 11m buf 10m buf 9m buf 8m buf 7m buf 6m buf 5m buf 4m buf 3m buf 2m buf 1m buf 0m w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
flexcan module freescale semiconductor 24-27 pxs20 microcontroller reference manual, rev. 1 24.3.4.10 interrupt flag s 1 register (iflag1) this register defines the flags fo r 32 message buffer interrupts and fi fo interrupts. it contains one interrupt flag bit per buffer. each successful transm ission or reception sets the corresponding iflag1 bit. if the corresponding imask1 bit is set, an interrupt will be generated. th e interrupt flag must be cleared by writing it to ?1?. writing ?0? has no effect. when the aen bit in the mcr is se t (abort enabled), while the iflag1 bit is set for an mb configured as tx, the writing access do ne by cpu into the corresponding mb will be blocked. when the fen bit in the mcr is se t (fifo enabled), the function of th e 8 least significant interrupt flags (buf7i - buf0i) is changed to support the fifo operati on. buf7i, buf6i and bu f5i indicate operating conditions of the fifo, while buf4i to buf0i are not used. figure 24-12. interrupt flags 1 register (iflag1) buf31i ? buf8i ? buffer mb i interrupt each bit flags the respective flexcan me ssage buffer (mb8 to mb31) interrupt. 1 = the corresponding mb has successfully completed transmission or reception 0 = no such occurrence buf7i ? buffer mb7 interrupt or ?fifo overflow? if the fifo is not enabled, this bi t flags the interrupt for mb7. if the fifo is enabled, this flag indicates an overflow condition in the fifo (f rame lost because fifo is full). 1 = mb7 completed transmission/reception or fifo overflow 0 = no such occurrence buf6i ? buffer mb6 interrupt or ?fifo warning? if the fifo is not enabled, this bi t flags the interrupt for mb6. if the fifo is enabled, this flag indicates that 5 out of 6 buffers of the fifo are already occupied (fifo almost full). 1 = mb6 completed transmission/re ception or fifo almost full 0 = no such occurrence base + 0x0030 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r buf 31i buf 30i buf 29i buf 28i buf 27i buf 26i buf 25i buf 24i buf 23i buf 22i buf 21i buf 20i buf 19i buf 18i buf 17i buf 16i w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r buf 15i buf 14i buf 13i buf 12i buf 11i buf 10i buf 9i buf 8i buf 7i buf 6i buf 5i buf 4i buf 3i buf 2i buf 1i buf 0i w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
flexcan module 24-28 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 buf5i ? buffer mb5 interrupt or ?frames available in fifo? if the fifo is not enabled, this bi t flags the interrupt for mb5. if the fifo is enabled, this flag indicates that at least one frame is availa ble to be read from the fifo. 1 = mb5 completed transmission/recepti on or frames available in the fifo 0 = no such occurrence buf4i ? buf0i ? buffer mb i interrupt or ?reserved? if the fifo is not enabled, these bits flag the in terrupts for mb0 to mb4. if th e fifo is enabled, these flags are not used and must be c onsidered as reserved locations. 1 = corresponding mb completed transmission/reception 0 = no such occurrence 24.3.4.11 rx individual mask registers (rximr0 ? rximr31) these registers are used as acceptan ce masks for id filtering in rx mbs and the fifo. if the fifo is not enabled, one mask register is provi ded for each available message buff er, providing id masking capability on a per message buffer basis. when the fifo is en abled (fen bit in mcr is set), the first 8 mask registers apply to the 8 elements of the fifo filter table (on a one-t o-one correspondence), while the rest of the registers apply to the regular mbs, starting from mb8. the individual rx mask regi sters are implemented in ram, so they are not affected by reset and must be explicitly initialized prior to any reception. furtherm ore, they can only be accessed by the cpu while the module is in freeze mode. out of freeze mode, write accesse s are blocked and read accesses will return ?all zeros?. furthermore, if the bcc bit in the mcr register is nega ted, any read or write operation to these registers results in access error. note the individual rx mask per message buff er feature may not be available in low cost mcus. please consult the specific mcu documentation to find out if this feature is s upported. if not supporte d, the rxgmask, rx14mask and rx15mask registers are available, regardless of the value of the bcc bit. figure 24-13. rx individual mask registers (rximr0 - rximr31) base + 0x0880?0x08ff 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mi31 mi30 mi29 mi28 mi27 mi26 mi25 mi24 mi23 mi22 mi21 mi20 mi19 mi18 mi17 mi16 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mi15 mi14 mi13 mi12 mi11 mi10 mi9 mi8 mi7 mi6 mi5 mi4 mi3 mi2 mi1 mi0
flexcan module freescale semiconductor 24-29 pxs20 microcontroller reference manual, rev. 1 mi31?mi0 ? mask bits for normal rx mbs, the mask bits affect the id filter programmed on the mb. for the rx fifo, the mask bits affect all bits programmed in the filter table (id, ide, rtr). 1 = the corresponding bit in the filter is checked against the one received 0 = the corresponding bit in the filter is ?don?t care? 24.4 functional description 24.4.1 overview the flexcan module is a can protocol engine with a very flexible mailbox system for transmitting and receiving can frames. the mailbox syst em is composed by a set of up to 64 message buffers (mb) that store configuration and control data, ti me stamp, message id and data (see section 24.3.2, message buffer structure ). the memory corresponding to the first 8 mbs can be configured to support a fifo reception scheme with a powerful id filteri ng mechanism, capable of checking in coming frames against a table of ids (up to 8 extended ids or 16 standard ids or 32 8-bi t id slices), each one wi th its own i ndividual mask register. simultaneous reception through fifo and mailbox is supported. for mailbox reception, a matching algorithm makes it possible to store received frames only in to mbs that have the same id programmed on its id field. a masking scheme makes it possibl e to match the id programmed on the mb with a range of ids on received can frames. for tr ansmission, an arbitratio n algorithm decides the prioritization of mbs to be transm itted based on the message id (optionally augmented by 3 local priority bits) or the mb ordering. before proceeding with the functional description, an important concept must be explained. a message buffer is said to be ?active? at a given time if it can participate in the matchi ng and arbitrat ion algorithms that are happening at that time. an rx mb with a ?0000? code is inactive (refer to table 24-4 ). similarly, a tx mb with a ?1000? or ?1001? c ode is also inac tive (refer to table 24-5 ). an mb not programmed with ?0000?, ?1000? or ?1001? will be temporarily deactivated (will not participate in the current arbitration or matching run) when the cpu writes to the c/s field of that mb (see section 24.4.6.2, message buffer deactivation ). 24.4.2 transmit process in order to transmit a can frame, the cpu must prepare a message buffer for transmission by executing the following procedure: ? if the mb is active (transmissi on pending), write an abort code (?1001?) to the code field of the control and status word to request an abortion of the transmission, then r ead back the code field and the iflag register to check if the transmission was aborted (see section 24.4.6.1, transmission abort mechanism ). if backwards compatibility is desired (aen in mcr negated), just write ?1000? to the code field to inactiv ate the mb but then the pending frame may be transmitted without notification (see section 24.4.6.2, message bu ffer deactivation ). ? write the id word. ? write the data bytes. ? write the length, control and c ode fields of the control and status word to activate the mb.
flexcan module 24-30 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 once the mb is activated in the fourth step, it will participate into the arbitrat ion process and eventually be transmitted according to its priority. at the end of the successful transmission, the value of the free running timer is written into the time stamp field, the code field in the control and status word is updated, a status flag is set in the interrupt flag regi ster and an interrupt is generated if allowed by the corresponding interrupt mask register bit. the new code fi eld after transmission de pends on the code that was used to activate the mb in step four (see table 24-4 and table 24-5 in section 24.3.2, message buffer structure ). when the abort feature is enable d (aen in mcr is asserted), afte r the interrupt flag is asserted for an mb configured as transmit buf fer, the mb is blocked, therefore the cpu is not able to update it until the interrupt flag be negated by cp u. it means that the cpu must clear the corresponding iflag before starting to prepare this mb for a new transmission or reception. 24.4.3 arbitration process the arbitration process is an algorithm executed by the mbm that scans th e whole mb memory looking for the highest priority message to be transmitted. all mbs program med as transmit buffers will be scanned to find the lowest id 1 or the lowest mb number or the hi ghest priority, depending on the lbuf and lprio_en bits on the control register. the arbitr ation process is triggered in the following events: ? during the crc field of the can frame ? during the error delimiter field of the can frame ? during intermission, if the winner mb defined in a previous arbitration was deactivated, or if there was no mb to transmit, but the cpu wrote to the c/s word of a ny mb after the previous arbitration finished ? when mbm is in idle or bus off state and the cpu writes to the c/s word of any mb ? upon leaving freeze mode when lbuf is asserted, the lprio_en bit has no effect and the lowest number buffer is transmitted first. when lbuf and lprio_en ar e both negated, the mb with the lowest id is transmitted fi rst but. if lbuf is negated and lprio_en is asserte d, the prio bits augment the id us ed during the arb itration process. with this extended id concept, arbi tration is done based on the full 32- bit id and the prio bits define which mb should be transmitted first, therefore mbs wi th prio = 000 have higher pr iority. if two or more mbs have the same priority, the regul ar id will determine th e priority of transmission. if two or more mbs have the same priority (3 extra bits) and the same regular id, the lowest mb will be transmitted first. once the highest priority mb is sel ected, it is transferred to a tem porary storage space called serial message buffer (smb), which has the same structure as a normal mb but is not user accessible. this operation is called ?move-out? and after it is done, wr ite access to the corresponding mb is blocked (if the aen bit in mcr is asserted). the write access is released in the following events: ? after the mb is transmitted ? flexcan enters in halt or bus off ? flexcan loses the bus arbitration or th ere is an error during the transmission 1. actually, if lbuf is negated, the arbitration considers not only the id, but also the rtr and ide bits placed inside the id at the same positions they are transmitted in the can frame.
flexcan module freescale semiconductor 24-31 pxs20 microcontroller reference manual, rev. 1 at the first opportunity window on the can bus, the me ssage on the smb is tran smitted according to the can protocol rules. flexc an transmits up to eight data bytes, even if the dlc (data length code) value is bigger. 24.4.4 receive process to be able to receive can frames into the mail box mbs, the cpu must prep are one or more message buffers for reception by executing the following steps: ? if the mb has a pending transmission, write an abort code (?1001?) to the code field of the control and status word to request an abortion of the transmission, then r ead back the code field and the iflag register to check if the transmission was aborted (see section 24.4.6.1, transmission abort mechanism ). if backwards compatibility is desired (aen in mcr negated), just write ?1000? to the code field to inactiv ate the mb, but then the pending frame may be transmitted without notification (see section 24.4.6.2, message bu ffer deactivation ). if the mb already programmed as a receiver, just write ?0000? to the code field of the control and status word to keep the mb inactive. ? write the id word ? write ?0100? to the code field of the c ontrol and status word to activate the mb once the mb is activated in the third step, it will be able to receive frames that match the programmed id. at the end of a successful reception, the mb is updated by the mbm as follows: ? the value of the free running timer is written into the time stamp field ? the received id, data (8 bytes at most) and length fields are stored ? the code field in the control and status word is updated (see table 24-4 and table 24-5 in section 24.3.2, message buffer structure ) ? a status flag is set in the interrupt flag regist er and an interrupt is generated if allowed by the corresponding interrupt mask register bit upon receiving the mb interrupt, the cpu should se rvice the received frame using the following procedure: ? read the control and status word (mandatory ? activates an internal lock for this buffer) ? read the id field (optional ? needed only if a mask was used) ? read the data field ? read the free running timer (optional ? releases the internal lock) upon reading the control and status word, if the busy bit is set in the code field, then the cpu should defer the access to the mb until th is bit is negated. reading the free running timer is not mandatory. if not executed the mb remains locke d, unless the cpu reads th e c/s word of another mb. note that only a single mb is locked at a time. th e only mandatory cpu read operation is the one on the control and status word to assure data coherency (see section 24.4.6, data coherence ). the cpu should synchronize to frame reception by the status flag bit for the specific mb in one of the iflag registers and not by the code field of that mb. polling the co de field does not work because once a frame was received and the cpu services the mb (by reading the c/s word followed by unlocking the mb), the code field will not return to empt y. it will remain full, as explained in table 24-4 . if the cpu
flexcan module 24-32 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 tries to workaround this behavior by writing to the c/s word to force an empty code after reading the mb, the mb is actually deactivated from any curre ntly ongoing matching process. as a result, a newly received frame matching the id of th at mb may be lost. in summary: never do polling by reading directly the c/s word of the mbs. instead, read the iflag registers. note that the received id field is al ways stored in the matching mb, thus the contents of the id field in an mb may change if the match was due to masking. note also that flexcan does r eceive frames transmitted by itself if there exists an rx matching mb, provi ded the srx_dis bit in the mcr is not asserted. if srx_dis is asserted, flexcan will not store frames transmitted by itself in any mb, even if it contains a matching mb, and no interrupt flag or interrupt si gnal will be generated due to the frame reception. to be able to receive can frames through the fifo, the cpu must enab le and configure the fifo during freeze mode (see section 24.4.7, rx fifo ). upon receiving the frames avai lable interrupt from fifo, the cpu should service the received fram e using the following procedure: ? read the control and status word (optional ? ne eded only if a mask wa s used for ide and rtr bits) ? read the id field (optional ? needed only if a mask was used) ? read the data field ? clear the frames available interr upt (mandatory ? release the buffe r and allow the cpu to read the next fifo entry) 24.4.5 matching process the matching process is an algorithm executed by th e mbm that scans the mb memory looking for rx mbs programmed with the same id as the one receiv ed from the can bus. if the fifo is enabled, the 8-entry id table from fifo is sca nned first and then, if a match is not found within the fifo table, the other mbs are scanned. in the event that the fifo is full, the matching algorithm will always look for a matching mb outside the fifo region. when the frame is received, it is te mporarily stored in a hi dden auxiliary mb called serial message buffer (smb). the matching process takes pl ace during the crc field of the receiv ed frame. if a matching id is found in the fifo table or in one of the regular mbs, the contents of the smb will be transferred to the fifo or to the matched mb during the 6th bit of the end-of-frame field of the can protocol. this operation is called ?move-in?. if a ny protocol error (crc, ack, etc.) is detected, than the move-in operation does not happen. for the regular mailbox mbs, an mb is said to be ?free to receive? a new frame if the following conditions are satisfied: ? the mb is not locked (see section 24.4.6.3, message buffer lock mechanism ) ? the code field is either empty or else it is full or overrun but the cpu has already serviced the mb (read the c/s word and then unlocked the mb) if the first mb with a matching id is not ?free to receive? the new frame, then the matching algorithm keeps looking for another free mb until it finds one. if it can not find one that is fr ee, then it will overwrite the last matching mb (unless it is locked) and set the code field to overrun (refer to table 24-4 and
flexcan module freescale semiconductor 24-33 pxs20 microcontroller reference manual, rev. 1 table 24-5 ). if the last matching mb is locked, then th e new message remains in the smb, waiting for the mb to be unlocked (see section 24.4.6.3, message buff er lock mechanism ). suppose, for example, that the fifo is disabled a nd there are two mbs with the same id, and flexcan starts receiving messages with that id. let us say that these mbs are the second and the fifth in the array. when the first message arrives, the matching algorithm will find the first match in mb number 2. the code of this mb is empty, so the message is stored there. when the second message arrives, the matching algorithm will find mb number 2 again, but it is not ?free to receive?, so it will keep looking and find mb number 5 and store the message there. if yet anothe r message with the same id arrives, the matching algorithm finds out that there are no matching mbs that are ?free to receiv e?, so it decides to overwrite the last matched mb, which is number 5. in doing so, it se ts the code field of th e mb to indicate overrun. the ability to match the same id in more than one mb can be exploited to implement a reception queue (in addition to the full featured fi fo) to allow more time for the cpu to service the mbs. by programming more than one mb with the same id, received me ssages will be queued into the mbs. the cpu can examine the time stamp field of the mbs to dete rmine the order in which the messages arrived. the matching algorithm described above can be changed to be the same one used in previous versions of the flexcan module. when the bcc bit in mcr is negated, the matchi ng algorithm stops at the first mb with a matching id that it founds, whether this mb is free or not. as a result, the message queueing feature does not work if the bcc bit is negated. matching to a range of ids is possible by using id acceptance masks. flexcan supports individual masking per mb. please refer to section 24.3.4.11, rx individual mask registers (rximr0?rximr31). during the matching algorithm, if a ma sk bit is asserted, th en the corresponding id bi t is compared. if the mask bit is negated, the corresponding id bit is ?d on?t care?. please note th at the individual mask registers are implemented in ram, so they are not initialized out of reset. also, they can only be programmed if the bcc bit is asserted and while the module is in freeze mode. flexcan also supports an alternate masking sche me with only three mask registers (rgxmask, rx14mask and rx15mask) for backwards compatibilit y. this alternate masking scheme is enabled when the bcc bit in the mcr register is negated. note the individual rx mask per message buff er feature may not be available in low cost mcus. please consult the specific mcu documentation to find out if this feature is s upported. if not supporte d, the rxgmask, rx14mask and rx15mask registers are available, regardless of the value of the bcc bit. 24.4.6 data coherence in order to maintain data cohere ncy and flexcan proper ope ration, the cpu must obe y the rules described in section 24.4.2, transmit process and section 24.4.4, receive process . any form of cpu accessing an mb structure within flexcan ot her than those specified may cause flexcan to behave in an unpredictable way.
flexcan module 24-34 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 24.4.6.1 transmission abort mechanism the abort mechanism provides a safe way to request the abortion of a pending transmission. a feedback mechanism is provided to inform th e cpu if the transmission was aborte d or if the frame could not be aborted and was transmitted instead. in order to maintain backwards compatibility, the abort mechanism must be explicitly enabled by as serting the aen bit in the mcr. in order to abort a transmission, the cpu must write a specific abort code (1001) to the code field of the control and status word. when the abort mechanism is enabled, the acti ve mbs configured as trasmission must be aborted first and then they may be updated. if the abort code is wr itten to an mb th at is currently being transmitted, or to an mb th at was already loaded into the sm b for transmission, the write operation is blocked and the mb is not deactivated, but the a bort request is captured a nd kept pending until one of the following conditions are satisfied: ? the module loses the bus arbitration ? there is an error during the transmission ? the module is put into freeze mode if none of conditions above are reache d, the mb is transmitted correctly, the interrupt flag is set in the iflag register and an interrupt to the cpu is generated (if enabled). the abort request is automatically cleared when the interrupt fl ag is set. in the other hand, if one of the above conditions is reached, the frame is not transmitted, therefore the abort code is written into the code field, the interrupt flag is set in the iflag and an interrupt is (opt ionally) generated to the cpu. if the cpu writes the abort code before the transmissi on begins internally, then the write operation is not blocked, therefore the mb is updated and no interrupt flag is set. in th is way the cpu just needs to read the abort code to make sure the active mb was deactivated. although th e aen bit is asserted and the cpu wrote the abort code, in this case the mb is deactiv ated and not aborted, because the transmission did not start yet. one mb is only aborted when the abort request is captured and kept pending until one of the previous conditions are satisfied. the abort procedure can be summarized as follows: ? cpu writes 1001 into the code field of the c/s word ? cpu reads the code field and compares it to the value that was written ? if the code field that was read is different from the value that was written, the cpu must read the corresponding iflag to check if th e frame was transmitte d or it is being cu rrently transmitted. if the corresponding iflag is set, the frame was tr ansmitted. if the corresponding iflag is reset, the cpu must wait for it to be se t, and then the cpu must read th e code field to check if the mb was aborted (code=1001) or it was transmitted (code=1000). 24.4.6.2 message buffer deactivation deactivation is mechanism pr ovided to maintain data coherence when the cpu writes to the control and status word of active mbs out of freeze mode. any cpu write access to the control and status word of an mb causes that mb to be excluded from the tran smit or receive processes during the current matching or arbitration round. the de activation is temporary, affecting only for the current match/arbitration round.
flexcan module freescale semiconductor 24-35 pxs20 microcontroller reference manual, rev. 1 the purpose of deactivation is data coherency. the match/arbitration process scans the mbs to decide which mb to transmit or receive. if the cpu updates the mb in the middle of a match or arbitration process, the data of that mb ma y no longer be coherent, therefore de activation of that mb is done. even with the coherence mechanism described above, writing to the control and status word of active mbs when not in freeze mode may produ ce undesirable results. examples are: ? matching and arbitration are one-p ass processes. if mbs are deactivated after they are scanned, no re-evaluation is done to determine a new match/ winner. if an rx mb with a matching id is deactivated during the matching proce ss after it was scanned, then this mb is marked as invalid to receive the frame, and flexcan wi ll keep looking for another matc hing mb within the ones it has not scanned yet. if it can not find one, then the message will be lost . suppose, for example, that two mbs have a matching id to a recei ved frame, and the user deactivat ed the first matching mb after flexcan has scanned the second. the received frame will be lost ev en if the second matching mb was ?free to receive?. ? if a tx mb containing th e lowest id is deactivated after fl excan has scanned it, then flexcan will look for another winner within the mbs that it has not scanned yet. ther efore, it may transmit an mb with id that may not be the lowest at the time because a lo wer id might be present in one of the mbs that it had already scanned before the deactivation. ? there is a point in time until which the deactivati on of a tx mb causes it not to be transmitted (end of move-out). after this point, it is transmitted but no interrupt is issued and the code field is not updated. in order to avoid this situati on, the abort procedures described in section 24.4.6.1, transmission abort mechanism should be used. 24.4.6.3 message buffer lock mechanism besides mb deactivation, flexcan ha s another data coherence mechanis m for the receive process. when the cpu reads the control and status word of an ?active not empty? rx mb, flexcan assumes that the cpu wants to read the whole mb in an atomic operation, and thus it sets an internal lock flag for that mb. the lock is released when the cpu reads the free running timer (global unlock operation), or when it reads the control and status word of another mb. th e mb locking is done to prevent a new frame to be written into the mb while the cpu is reading it. note the locking mechanism only applies to rx mbs which have a code different than inactive (?0000?) or empty 1 (?0100?). also, tx mbs can not be locked. suppose, for example, that the fifo is disabled and the second and the fifth mbs of the array are programmed with the same id, and flexcan has already received and stored messages into these two mbs. suppose now that the cpu decide s to read mb number 5 and at th e same time another message with the same id is arriving. when the cpu reads the cont rol and status word of mb number 5, this mb is locked. the new message arrives and the matching algorithm finds out that there are no ?free to receive? mbs, so it decides to override mb number 5. however, this mb is lock ed, so the new me ssage can not be written there. it will remain in the smb waiting fo r the mb to be unlocked, a nd only then will be written 1. in previous flexcan versions, reading the c/s word locked the mb even if it was empty. this behavior will be honored when the bcc bit is negated.
flexcan module 24-36 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 to the mb. if the mb is not unlocke d in time and yet anothe r new message with the same id arrives, then the new message overwrites th e one on the smb and there wi ll be no indication of lo st messages either in the code field of the mb or in the error and status register. while the message is being moved-in from the smb to the mb, the busy bit on the code field is asserted. if the cpu reads the control and status word and finds out that the busy bit is set, it should defer accessing the mb until the busy bit is negated. note if the busy bit is asserted or if the mb is empty, then reading the control and status word does not lock the mb. deactivation takes precedence over lock ing. if the cpu deactivates a locked rx mb, then its lock status is negated and the mb is marked as invalid fo r the current matching round. any pending message on the smb will not be transferred anymore to the mb. 24.4.7 rx fifo the receive-only fifo is enabled by a sserting the fen bit in the mcr. the reset value of this bit is zero to maintain software backwards comp atibility with previous versions of the module that did not have the fifo feature. when the fifo is enabled, the me mory region normally occ upied by the first 8 mbs (0x80-0xff) is now reserved for use of the fifo engine (see section 24.3.3, rx fifo structure ). management of read and write pointers is done inte rnally by the fifo engine. the cpu can read the received frames sequentially, in the order they we re received, by repeatedly accessing a message buffer structure at the beginning of the memory. the fifo can store up to six frames pending service by the cpu. an interrupt is sent to the cpu when new frames are available in the fifo. upon receiv ing the interrupt, the cpu must read the frame (accessing an mb in the 0x80 address) a nd then clear the interrupt. the act of clearing the interrupt triggers the fifo engine to replace the mb in 0x80 with the next frame in the queue, and then issue another interrupt to the cpu. if the fifo is full and more frames continue to be received, an overflow interrupt is issued to the cpu and subsequent frames are not accepted until the cpu creates space in the fifo by reading one or more fram es. a warning interrupt is also generated when five frames are accumulated in the fifo. a powerful filtering scheme is provided to accept onl y frames intended for the target application, thus reducing the interrupt servicing work load. the filter ing criteria is specifie d by programming a table of eight 32-bit registers that can be configured to one of th e following formats (see also section 24.3.3, rx fifo structure ): ? format a: 8 extended or standard ids (including ide and rtr) ? format b: 16 standard ids or 16 extended 14-bit id slices (i ncluding ide and rtr) ? format c: 32 standard or extended 8-bit id slices note a chosen format is applied to all 8 regi sters of the filter table. it is not possible to mix formats within the table.
flexcan module freescale semiconductor 24-37 pxs20 microcontroller reference manual, rev. 1 the eight elements of the filter ta ble are individually affected by the first eight individual mask registers (rximr0 - rximr7), allowing very powerful filtering criteria to be defined. the rest of the rximr, starting from rxim8, continue to affe ct the regular mbs, starting from mb8. if the bcc bit is negated (or if the rximr are not available for the particular mcu), then the fifo filt er table is affected by the legacy mask registers as follows: elem ent 6 is affected by rx14mask, el ement 7 is affected by rx15mask and the other elements (0 to 5) are affected by rxgmask. 24.4.7.1 precautions when using global mask and i ndividual mask registers mask filtering alignment is affected based on the se tting of the fen and bcc of mcr. the following table shows recommended actions de pending on fen and bcc settings. 24.4.8 can protocol related features 24.4.8.1 remote frames remote frame is a special kind of frame. the user can program an mb to be a request remote frame by writing the mb as transmit with th e rtr bit set to ?1?. after the remote request frame is transmitted successfully, the mb becomes a receive message buffer, with the same id as before. when a remote request frame is received by flexcan, its id is compared to the ids of the transmit message buffers with the code fi eld ?1010?. if there is a matching id, then this mb frame will be transmitted. note that if the matching mb has the rt r bit set, then flexcan will transmit a remote frame as a response. table 24-8. recommended fen and bcc settings case mcr[fen] rxfifo mcr[bcc] rxindividual mask notes case1 fen=0 bcc=0 rxgmask, rx14m ask and rx15mask can safely be used.this allows backwards compatibility to older devices (e.g. devices without the individual masks feature). in this case, individual masks are not used. case 2 fen=1 bcc=0 1st alternative: don't use rxgmask, rx14mask and rx15mask in this case, leave the masks in their reset state. case 3 fen=1 bcc=0 2nd alternative: do not configure any mb as rx (i.e. let all mbs as either tx or inactive). in this case, the masks rxgmask, rx14mask and rx15mask can be used to affect id tables without affecting the filtering process for rx mbs case 4 don?t care bcc=1 if mcr[bcc] = 1, then the rximrs are enabled an thus the masks rxgmask, rx14mask and rx15mask are not used.particularly, when mcr[fen] = 0, rxfifo is disabled; rxgmask, rx14mask and rx15mask don't affect filtering. individual masks used.
flexcan module 24-38 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 a received remote request frame is no t stored in a receive buffer. it is only used to trigger a transmission of a frame in response. the mask re gisters are not used in remote fram e matching, and all id bits (except rtr) of the incoming received frame should match. in the case that a remote request frame was r eceived and matched an mb, this message buffer immediately enters the internal arbi tration process, but is considered as normal tx mb, with no higher priority. the data length of this fr ame is independent of the dlc field in the remote frame that initiated its transmission. if the rx fifo is enabled (bit fen set in mcr), flexcan will not generate an automatic response for remote request frames that match the fifo filteri ng criteria. if the remote frame matches one of the target ids, it will be stor ed in the fifo and presented to the cpu. note that for filtering formats a and b, it is possible to select wh ether remote frames are ac cepted or not. for format c, remote frames are always accepted (if they match the id). 24.4.8.2 overload frames flexcan does transmit overload frames due to detection of following conditions on can bus: ? detection of a dominant bit in th e first/second bit of intermission ? detection of a dominant bit at the 7th bit (last) of end of frame field (rx frames) ? detection of a dominant bit at th e 8th bit (last) of error fram e delimiter or overload frame delimiter 24.4.8.3 time stamp the value of the free running timer is sampled at the beginning of th e identifier field on the can bus, and is stored at the end of ?move -in? in the time stamp field, provi ding network behavior with respect to time. note that the free running timer can be reset upon a specific frame recepti on, enabling network time synchronization. refer to tsyn description in section 24.3.4.2, control register (ctrl). 24.4.8.4 protocol timing figure 24-14 shows the structure of the clock generation ci rcuitry that feeds the can protocol interface (cpi) sub-module. the clock source bit (clk_src) in the ctrl register defines whether the internal clock is connected to the output of a crystal oscill ator (oscillator clock) or to the peripheral clock (generally from a fmpll). in orde r to guarantee reliable operation, the clock source should be selected while the module is in disable mode (bit md is set in the module configuration register).
flexcan module freescale semiconductor 24-39 pxs20 microcontroller reference manual, rev. 1 figure 24-14. can engine clocking scheme the crystal oscillator cloc k should be selected whenever a tight to lerance (up to 0.1%) is required in the can bus timing. the crystal oscillato r clock has better jitter perform ance than fmpll generated clocks. note this clock selection featur e may not be available in all mcus. a particular mcu may not have a fmpll, in which case it would have only the oscillator clock, or it may use only the fmpll clock feeding the flexcan module. in these cases, the clk_src bit in the ctrl register has no effect on the module operation. in order to guarantee reliable operat ion, the selected ca n protocol interface (cpi) clock should not be faster as the the peripheral clock. the flexcan module supports a variet y of means to setup bi t timing parameters th at are required by the can protocol. the control register has various fields used to control bit timing parameters: presdiv, propseg, pseg1, pseg2 and rjw. see section 24.3.4.2, control register (ctrl). the presdiv field controls a prescal er that generates the serial cloc k (sclock), whose period defines the ?time quantum? used to compose th e can waveform. a time quantum is the atomic unit of time handled by the can engine. a bit time is subdivided into three segments 1 (reference figure 24-15 and table 24-9 ): ? sync_seg: this segment has a fixed length of one time quantum. signal e dges are expected to happen within this section ? time segment 1: this segment includes the propa gation segment and the phase segment 1 of the can standard. it can be program med by setting the propseg and th e pseg1 fields of the ctrl register so that their sum (plus 2) is in the range of 4 to 16 time quanta 1. for further explanation of the underlying concepts please refer to iso/dis 11519 ? 1, section 10.3. reference also the bosch can 2.0a/b protocol specificatio n dated september 1991 for bit timing. peripheral clock (fmpll) oscillator clock (xtal) clk_src prescaler (1 .. 256) sclock cpi clock f tq f canclk prescaler v alue t ?? ------------------- --------------------- --------------- =
flexcan module 24-40 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? time segment 2: this segment represents the ph ase segment 2 of the can standard. it can be programmed by setting the pse g2 field of the ctrl register (plu s 1) to be 2 to 8 time quanta long figure 24-15. segments within the bit time table 24-10 gives an overview of the can compliant segmen t settings and the related parameter values. table 24-9. time segment syntax syntax description sync_seg system expects transitions to occur on the bus during this period. transmit point a node in transmit mode transfers a new value to the can bus at this point. sample point a node samples the bus at this point. if the three samples per bit option is selected, then this point marks the position of the third sample. table 24-10. can standard compliant bit time segment settings time segment 1 time segment 2 re-synchronization jump width 5 .. 10 2 1 .. 2 4 .. 11 3 1 .. 3 5 .. 12 4 1 .. 4 6 .. 13 5 1 .. 4 7 .. 14 6 1 .. 4 8 .. 15 7 1 .. 4 bit rate f tq number of time quanta tt t ?? ------------------- ------------------ ----------------- ------------------ ---------------- - = t sync_seg time segment 1 time segment 2 1 4 ... 16 2 ... 8 8 ... 25 time quanta = 1 bit time nrz signal sample point (single or triple sampling) (prop_seg + pseg1 + 2) (pseg2 + 1) transmit point
flexcan module freescale semiconductor 24-41 pxs20 microcontroller reference manual, rev. 1 note it is the user?s responsibility to ensure the bit time settings are in compliance with the can standard. for bit time calculations, use an ipt (information processing time) of 2, which is the value implemented in the flexcan module. 24.4.8.5 arbitration a nd matching timing during normal transmission or rece ption of frames, the arbitrati on, matching, move-in and move-out processes are executed during certain time windows inside the can frame, as shown in figure 24-16 . figure 24-16. arbitration, match and move time windows when doing matching and arbitration, flexcan needs to scan the whole message bu ffer memory during the available time slot. in order to have sufficient time to do that, the following requirements must be observed: ? a valid can bit timing must be programmed, as indicated in table 24-10 ? the peripheral clock frequency can not be smaller than the oscill ator clock frequency, i.e. the fmpll can not be programmed to di vide down the oscillator clock ? there must be a minimum ratio between the peri pheral clock frequency and the can bit rate, as specified in table 24-11 a direct consequence of the first re quirement is that the minimum numbe r of time quanta per can bit must be 8, so the oscillator cl ock frequency should be at least 8 times the can bit ra te. the minimum frequency ratio specified in table 24-11 can be achieved by choosing a high enough peripheral cloc k frequency when compared to the oscillator clock frequency, or by adjusting one or more of the bit timing parameters (presdiv, propseg, pseg1, pseg2). as an example, taking the case of 64 mbs, if the oscillator and 9 .. 16 8 1 .. 4 table 24-11. minimum ratio between peri pheral clock frequency and can bit rate number of message buffers minimum ratio 16 8 32 8 64 16 table 24-10. can standard compliant bit time segment settings (continued) time segment 1 time segment 2 re-synchronization jump width crc (15) eof (7) interm start move matching/arbitration window (24 bits) move (bit 6) window
flexcan module 24-42 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 peripheral clock frequencies are e qual and the can bit timing is progr ammed to have 8 time quanta per bit, then the prescaler factor (pre sdiv + 1) should be at least 2. for prescaler factor equal to one and can bit timing with 8 time quanta per bit, the ratio between peripheral and os cillator clock frequencies should be at least 2. 24.4.9 modes of operation details 24.4.9.1 freeze mode this mode is entered by asserting the halt bit in the mcr register or when the mcu is put into debug mode. in both cases it is also n ecessary that the frz bit is asserted in the mcr register and the module is not in any of the low power modes (disable, stop) . when freeze mode is re quested during transmission or reception, flexcan does the following: ? waits to be in either intermission, passive error, bus off or idle state ? waits for all internal activi ties like arbitration, matching, move-in and move-out to finish ? ignores the rx input pin and dr ives the tx pin as recessive ? stops the prescaler, thus halt ing all can prot ocol activities ? grants write access to the erro r counters register, which is read-only in other modes ? sets the not_rdy and frz_ack bits in mcr after requesting freeze mode, the us er must wait for the frz_ack bit to be asserted in mcr before executing any other action, otherwise flexcan may operate in an unpredic table way. in freeze mode, all memory mapped registers are accessible. exiting freeze mode is done in one of the following ways: ? cpu negates the frz bit in the mcr register ? the mcu is removed from debug mode and/or the halt bit is negated once out of freeze mode, flexcan tries to re-synchr onize to the can bus by waiting for 11 consecutive recessive bits. 24.4.9.2 module disable mode this low power mode is entered when the mdis bit in the mcr register is asserted. if the module is disabled during freeze mode, it shuts down the clocks to the cpi and mbm sub-modules, sets the lpm_ack bit and negates the frz_ack bit. if the m odule is disabled during tr ansmission or reception, flexcan does the following: ? waits to be in either idle or bus off state, or else waits for th e third bit of intermission and then checks it to be recessive ? waits for all internal activi ties like arbitration, matching, move-in and move-out to finish ? ignores its rx input pin and dr ives its tx pin as recessive ? shuts down the clocks to the cpi and mbm sub-modules ? sets the not_rdy and lpm_ack bits in mcr
flexcan module freescale semiconductor 24-43 pxs20 microcontroller reference manual, rev. 1 the bus interface unit continues to operate, enabling the cpu to access memory mapped registers, except the free running timer, the error counter register and the message buffers, which cannot be accessed when the module is in disable mode . exiting from this mode is done by negating the mdis bit, which will resume the clocks and negate the lpm_ack bit. 24.4.9.3 stop mode this is a system low power mode in which all mcu clocks are st opped for maximum power savings. if flexcan receives the global stop m ode request during freeze mode, it sets the lpm_ack bit, negates the frz_ack bit and then sends a stop acknowledge signal to the cpu, in order to shut down the clocks globally. if stop mode is requested during tran smission or reception, flexcan does the following: ? waits to be in either idle or bus off state, or el se waits for the third bit of intermission and checks it to be recessive ? waits for all internal activi ties like arbitration, matching, move-in and move-out to finish ? ignores its rx input pin and dr ives its tx pin as recessive ? sets the not_rdy and lpm_ack bits in mcr ? sends a stop acknowledge signal to the cpu, so that it can shut down the clocks globally exiting stop mode is done in one of the following ways: ? cpu resuming the clocks and removing the stop mode request ? cpu resuming the clocks and stop mode request as a result of the self wake mechanism in the self wake mechanism, if the slf_wak bit in mcr register was set at the time flexcan entered stop mode, then upon detectio n of a recessive to dominant transiti on on the can bus, flexcan sets the wak_int bit in the esr register and, if enabled by the wak_msk bit in mcr, generates a wake up interrupt to the cpu. upon receivi ng the interrupt, the cpu should resume the clocks and remove the stop mode request. flexcan will then wa it for 11 consecutive recessive bi ts to synchronize to the can bus. as a consequence, it will not re ceive the frame that woke it up. table 24-12 details the effect of slf_wak and wak_msk upon wake-up from stop mode. note that wake-up from stop mode only works when both bits are asserted. 24.4.10 interrupts the module can generate up to 70 inte rrupt sources (64 interrupts due to message buffers and 6 interrupts due to ored interrupts from mbs, bus off, error, tx warning, rx warning and wake up). the number of actual sources depends on the conf igured number of message buffers. table 24-12. wake-up from stop mode slf_wak wak_msk mcu clocks enabled wake-up interrupt generated 0 0 no no 0 1 no no 1 0 no no 11yesyes
flexcan module 24-44 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 each one of the message buffers can be an interrupt source, if its co rresponding imask bi t is set. there is no distinction between tx and rx interrupts for a particular buffer, under the assumption that the buffer is initialized for eith er transmission or reception. each of the buffers has assi gned a flag bit in the iflag registers. the bit is set when th e corresponding buffer completes a succ essful transmission/reception and is cleared when the cpu writes it to ?1? (unless another interrupt is gene rated at the same time). note it must be guaranteed that the cpu only clears the bit causing the current interrupt. for this reason, bit manipulati on instructions (bset) must not be used to clear interrupt flags. thes e instructions may cause accidental clearing of interrupt flags which are se t after entering the current interrupt service routine. if the rx fifo is enabled (bit fen on mcr set) , the interrupts corresponding to mbs 0 to 7 have a different behavior. bit 7 of the iflag1 becomes the ?fifo overflow? flag; bit 6 becomes the fifo warning flag, bit 5 becomes the ?frames availabl e in fifo flag? and bits 4-0 are unused. see section 24.3.4.10, interrupt flags 1 register (iflag1), for more information. a combined interrupt for all mbs is also generated by an or of all the interrupt sources from mbs. this interrupt gets generated when any of the mbs generate s an interrupt. in this case the cpu must read the iflag registers to determine wh ich mb caused the interrupt. the other 5 interrupt source s (bus off, error, tx warning, rx wa rning and wake up) generate interrupts like the mb ones, and can be read from the error and status register. the bus off, error, tx warning and rx warning interrupt mask bits are located in the c ontrol register, and the wake -up interrupt mask bit is located in the mcr. 24.4.11 bus interface the cpu access to flexcan registers ar e subject to the following rules: ? read and write access to supe rvisor registers in user mo de results in access error. ? read and write access to unimplement ed or reserved address space al so results in access error. any access to unimplemented mb or rx individual mask regist er locations results in access error. any access to the rx individual mask register space when the bcc bit in mcr is negated results in access error. ? if maxmb is programmed with a value smaller than the available number of mbs, then the unused memory space can be used as general pu rpose ram space. note that the rx individual mask registers can only be accessed in freeze mode , and this is still true for unused space within this memory. note also that re served words within ram cannot be used. as an example, suppose flexcan is configured with 64 mbs and maxmb is program med with zero. the maximum number of mbs in this case b ecomes one. the mb memory star ts at 0x0060, but the space from 0x0060 to 0x007f is reserved (for smb usage), and the space fr om 0x0080 to 0x008f is used by the one mb. this leaves us wi th the available space from 0x0090 to 0x047f. the available memory in the mask registers space would be from 0x0884 to 0x097f.
flexcan module freescale semiconductor 24-45 pxs20 microcontroller reference manual, rev. 1 note unused mb space must not be us ed as general purpose ram while flexcan is transmitting an d receiving can frames. 24.5 initialization/application information this section provide instructions for initializing the flexcan module. 24.5.1 flexcan initialization sequence the flexcan module may be reset in three ways: ? mcu level hard reset, which resets all memory mapped re gisters asynchronously ? mcu level soft reset, which rese ts some of the memory mapped re gisters synchronous ly (refer to table 24-2 to see what registers are affected by soft reset) ? soft_rst bit in mcr, which has the same effect as the mcu level soft reset soft reset is synchronous and has to follow an internal request/acknowledge procedure across clock domains. therefore, it may take some time to full y propagate its effects. the soft_rst bit remains asserted while soft reset is pending, so software can poll this bit to know when the reset has completed. also, soft reset can not be applied while clocks ar e shut down in any of the low power modes. the low power mode should be exited and the cloc ks resumed before applying soft reset. the clock source (clk_src bit) should be selected while the module is in disa ble mode. after the clock source is selected and the module is enabled (mdis bit negated), fl excan automatically goes to freeze mode. in freeze mode, flexcan is un-synchronized to the can bus, the halt and frz bits in mcr register are set, the internal state machines ar e disabled and the frz_ack and not_rdy bits in the mcr register are set. the tx pin is in recessive state a nd flexcan does not initi ate any transmission or reception of can frames. note that the message buffers and the rx in dividual mask registers are not affected by reset, so they ar e not automatically initialized. for any configuration change/initialization it is re quired that flexcan is put into freeze mode (see section 24.4.9.1, freeze mode ). the following is a generic initia lization sequence applicable to the flexcan module: ? initialize the module configuration register ? enable the individual filtering per mb and r eception queue features by setting the bcc bit ? enable the warning interrupts by setting the wrn_en bit ? if required, disable frame self re ception by setting the srx_dis bit ? enable the fifo by setting the fen bit ? enable the abort mechanism by setting the aen bit ? enable the local priority feature by setting the lprio_en bit ? initialize the control register ? determine the bit timing parame ters: propseg, pseg1, pseg2, rjw
flexcan module 24-46 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? determine the bit rate by programming the presdiv field ? determine the internal ar bitration mode (lbuf bit) ? initialize the message buffers ? the control and status word of al l message buffers mu st be initialized ? if fifo was enabled, the 8-entr y id table must be initialized ? other entries in each message buffer should be initia lized as required ? initialize the rx individual mask registers ? set required interrupt mask bits in the imask registers (for all mb interrupts), in ctrl register (for bus off and error interrupts) and in mcr register for wake-up interrupt ? negate the halt bit in mcr starting with the last event, flexcan attempts to synchronize to the can bus. 24.5.2 flexcan addressing and ram size configurations the ram configuration is as follows: ? 544 bytes for mb memory ? 128 bytes for individual mask registers in each configuration the user ca n program the maximum number of mbs that will take part in the matching and arbitration processes using the maxmb field in the mcr register. maxmb can be any number between 0?31.
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-1 pxs20 microcontroller reference manual, rev. 1 chapter 25 flexible motor control pulse width modulator module (flexpwm) 25.1 introduction 25.1.1 overview the pulse width modulator module (flexpwm) contai ns 4 pwm submodules each of which is set up to control a single half-bridge power st age. there are 4 fault channels. this pwm is capable of controlling most motor t ypes: ac induction motors (acim), permanent magnet ac motors (pmac), both brushless (bldc) and brush dc motors (bdc ), switched (srm) and variable reluctance motors (vrm), and stepper motors. this device contains two flexpwm m odules. the modules interact with the ctu as described in the ctu section of this document. 25.1.2 features ? 16 bits of resolution for center, edge aligned, and asymmetrical pwms ? pwm outputs can operate as complimen tary pairs or independent channels ? can accept signed numbers for pwm generation ? independent control of both edges of each pwm output ? synchronization to external hard ware or other pwm supported ? double buffered pwm registers ? integral reload rates from 1 to 16 ? half cycle reload capability ? multiple output trigger events can be generated per pwm cycle via hardware ? support for double swit ching pwm outputs ? fault inputs can be assigned to control multiple pwm outputs ? programmable filters for fault inputs ? independently programmable pwm output polarity ? independent top and botto m deadtime insertion ? each complementary pair can operate with its own pwm frequency and deadtime values ? individual software-control for each pwm output ? all outputs can be programmed to change simultaneously via a "force out" event ? pwmx pin can optionally output a th ird pwm signal from each submodule ? channels not used for pwm generation can be used for buffered output compare functions ? channels not used for pwm generation ca n be used for input capture functions
flexible motor control pulse width modulator module (flexpwm) 25-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? enhanced dual edge capture functionality ? the option to supply the source for each comp lementary pwm signal pair from any of the following: ? external digital pin ? internal timer channel ? external adc input, taking into account values set in adc high and low limit registers. 25.1.3 modes of operation care must be exercised when using this module in certain chip operating modes. some motors (such 3-phase ac motors) require regular software updates fo r proper operation. failur e to do so could result in destroying the motor or inverter. because of this , pwm outputs are placed in their inactive states in stop mode, and optionally under wait and debug mode s. pwm outputs will be reactivated (assuming they were active to begin with) when these modes are exited. table 25-1. modes when pwm operation is restricted mode description stop peripheral and cpu clocks are stopped. pwm outputs are driven inactive. wait cpu clocks are stopped while peripheral clocks continue to run. pwm outputs are driven inactive as a function of the waiten bit. debug cpu and peripheral clocks continue to run, but cpu maybe stalled for periods of time. pwm outputs are driven inactive as a function of the dbgen bit.
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-3 pxs20 microcontroller reference manual, rev. 1 25.1.4 block diagrams 25.1.4.1 module level figure 25-1. pwm block diagram pwma0 pwmb0 pwmx0 fault channel 0 ext_sync faults master reload output triggers aux clock sub-module 1 sub-module 2 fault0-3 pwma1 pwmb1 pwmx1 pwma2 pwmb2 pwmx2 ext_force interrupts master sync master force sub-module 0 sub-module 3 pwma3 pwmb3 pwmx3
flexible motor control pulse width modulator module (flexpwm) 25-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 25.1.4.2 pwm submodule figure 25-2. pwm subm odule block diagram 25.2 external signal descriptions the pwm module has external pi ns named pwma[n], pwmb[n], pwmx[n], fault[n], ext_sync, ext_force, exta[n], and extb[n]. the pwm m odule also has an on chip input called ext_clk and an on-chip output called out_trig[n]. the number of these signals can vary depending on pwm configuration for each chip. (see figure 13-2 .) 25.2.1 pwma[n] and pwmb[n ] - external pwm pair these pins are the output pins of the pwm channels. they can be independent pwm signals or a complementary pair. 25.2.2 pwmx[n] - auxiliary pwm signal these pins are the auxiliary output pins of the pwm channels. they can be independent pwm signals. when not needed as an output, they can be used as inputs to the input cap ture circuitry or they can be used to generate the ipol bit during deadtime correction. 25.2.3 fault[n] - fault inputs these are input pins for di sabling selected pwm outputs. 16 bit comparator 16 bit comparator 16 bit comparator 16 bit comparator d s r q init value initialize pwm on pwm off 16 bit comparator 16 bit comparator d s r q init value initialize pwm on pwm off compare 0 value compare 1 value compare 2 value compare 3 value compare 4 value compare 5 value comp. vs indep. dead time generator fault protection output override control pwma pwmb fault inputs from module bus output triggers interrupts 16 bit counter prescaler clock master sync (sub-module 0 only) master reload (sub-module 0 only) reload logic ldok mid-cycle reload modulo counter value preload counter preload mux pin mux pwmx master sync master reload register reloads pwm23 pwm45 mux select logic aux clock (sub-module 0 only) external sync register reload mux
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-5 pxs20 microcontroller reference manual, rev. 1 25.2.4 ext_sync - external synchronization signal this input signal allows a source ex ternal to the pwm to initialize the pwm counter . in this manner the pwm can be synchronized to external circuitry. 25.2.5 ext_force - external output force signal this input signal allows a source external to the pw m to force an update of the pwm outputs. in this manner the pwm can be synchronized to external circuitry. an exam ple would be to simultaneously switch all of the pwm outputs on a commutation boundary for trapezoidal control of a bldc motor. the boundary can be established via exte rnal logic or an on-chip timer. 25.2.6 exta[n] and extb[n] - al ternate pwm control signals these pins allow an alternate source to contro l the pwma and pwmb output s although typically, the exta input will be used for the generation of a co mplementary pair. typica l connections include adc results registers, tmr outputs, gpio inputs, and comparator outputs. th e sim chapter of the chip system spec will describe the possible connections and the bits to control any muxing. 25.2.7 out_trig0[n] and out_ trig1[n] - output triggers these outputs allow the pwm s ubmodules to control timing of the adc conversions. see 25.4.3.15, output trigger control register (tctrl) for a description of how to enable these outputs and how the compare registers match up to the output triggers. 25.2.8 ext_clk - external clock signal this on-chip input signal allows an on-chip source external to the pwm (typically a timer) to control the pwm clocking. in this manne r the pwm can be s ynchronized to the timer. th is signal must be generated synchronously to the pwm?s clock since it is not resynchronized in the pwm. 25.3 functional description 25.3.1 block diagram a block diagram of the pwm is shown in figure 25-1 . 25.3.2 pwm capabilities this section describes some capabilities of the pwm module. 25.3.2.1 center aligned pwms each submodule has its own timer th at is capable of generating pwm signals on two output pins. the edges of each of these signals are c ontrolled independently as shown in figure 25-3 .
flexible motor control pulse width modulator module (flexpwm) 25-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 25-3. center aligned example the submodule timers only coun t in the up direction and th en reset to the init valu e. instead of having a single value that determines pulse width, there are two values that must be specified: th e turn on edge and the turn off edge. this double acti on edge generation not only gives the user control over the pulse width, but over the relative alignment of the signal as well. as a result, ther e is no need to support separate pwm alignment modes since the pwm alignm ent mode is inherently a function of the turn on and turn off edge values. figure 25-3 also illustrates an additional enhancement to the pwm generation proce ss. when the counter resets, it is reloaded with a user specified value, which may or may not be zero. if the value chosen happens to be the 2?s complement of the modulus va lue, then the pwm generator operates in "signed" mode. this means that if each pwm?s turn on and turn off edge values are also the same number but only different in their sign, the "on" portion of the output si gnal will be centered around a count value of zero. therefore, only one pwm value needs to be calculated in software and then this value and its negative are provided to the submodule as the turn off and turn on e dges respectively. this technique will result in a pulse width that always consists of an odd number of timer counts. if all pwm signal edge calculations follow this same convention, then the signals will be center aligned with re spect to each other, which is the goal. of course, center alignment be tween the signals is not restricted to symmetry around the zero count value, as any other number would also work. howe ver, centering on zero provides the greatest range in signed mode and also simplifies the calculations. val1 ($0100) val3 val5 val0 ($0000) val4 val2 init ($ff00) pwma pwmb
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-7 pxs20 microcontroller reference manual, rev. 1 25.3.2.2 edge aligned pwms when the turn on edge for each pulse is specified to be the init value, then edge aligned operation results, as illustrated in figure 25-4 . therefore, only the turn off edge value needs to be periodically updated to change the pulse width. figure 25-4. edge aligned example (init=val2=val4) with edge aligned pwms, another example of the be nefits of signed mode ca n be seen. a common way to drive an h-bridge is to use a technique called "bipol ar" pwms where a 50% duty cycle results in zero volts on the load. duty cycles less than 50% result in negative load vol tages and duty cycles greater than 50% generate positive load voltages. if the module is set to signed mode operation (the init and val1 values are the same number with opposite signs), then there is a direct propor tionality between the pwm turn off edge value and the motor voltage, including the sign. so once again, signed mode of operation simplifies the software in terface to the pwm module si nce no offset calculations are required to translate the output variable control algorithm to the voltage on an h-bridge load. 25.3.2.3 phase shifted pwms in the previous sections, the benefits of signed m ode of operation were disc ussed in the context of simplifying the required software cal culations by eliminating the requirement to bi as up signed variables before applying them to the module. however, if num erical biases are applied to the turn on and turn off edges of different pwm signal, the signals will be phase shifted with re spect to each other, as illustrated in figure 25-5 . this results in certain advantages when applied to a power stage. for example, when operating a multi-phase inverter at a low modulation index, all of the pwm switching edges from the different phases occur at nearly the same time. this can be troublesome from a noise standpoint, especially val1 ($0100) val5 val0 ($0000) val3 init ($ff00) pwma pwmb
flexible motor control pulse width modulator module (flexpwm) 25-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 if adc readings of the i nverter must be scheduled near those times. phase shifting the pwm signals can open up timing windows between the switching edges to allow a signal to be sampled by the adc. however, phase shifting does not affect the duty cy cle so average load voltage is not affected. figure 25-5. phase shifted outputs example an additional benefit of phase shifted pwms can be seen in figure 25-6 . in this case, an h-bridge circuit is driven by 4 pwm signals to control the voltage wave form on the primary of a tr ansformer. both left and right side pwms ar e configured to always generate a square wave with 50% duty cycle. this works out nicely for the h-bridge sin ce no narrow pulse widths are gene rated reducing the high frequency switching requirements of the transistors. notice that the square wa ve on the right side of the h-bridge is phase shifted compared to the left side of the h-br idge. as a result, the transformer primary sees the bottom waveform across its terminals. the rms valu e of this waveform is directly controlled by the amount of phase shift of the square waves. regardless of the phase sh ift, no dc component appears in the load voltage as long as the duty cycle of each square wave remains at 50% maki ng this technique ideally suited for transformer loads. as a result, this topolo gy is frequently used in i ndustrial welders to adjust the amount of energy delivered to the weld arc. val1 ($0100) val5 val3 val0 ($0000) val4 val2 init ($ff00) pwma pwmb
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-9 pxs20 microcontroller reference manual, rev. 1 figure 25-6. phase shifted pwms applied to a transformer primary 25.3.2.4 double switching pwms double switching pwm output is supported to aid in single shunt current meas urement and three phase reconstruction. this met hod support two independent ri sing edges and two indepe ndent falling edges per pwm cycle. the val2 and val3 registers are used to generate the even channel (labelled as pwma in the figure) while val4 and val5 are used to genera te the odd channel. the two channels are combined using xor logic (see figure 25-17 ) as shown in figure 25-7 . the dblpwm signal can be run through the deadtime insertion logic. top left bottom left submodule 0 top right bottom right submodule 1 v+ left side right side transformer
flexible motor control pulse width modulator module (flexpwm) 25-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 25-7. double switching output example 25.3.2.5 adc triggering in cases where the timing of the adc triggering is cr itical, it must be scheduled as a hardware event instead of software activated. wi th this pwm module, multiple adc triggers can be generated in hardware per pwm cycle w ithout the requirement of another timer module. figure 25-8 shows how this is accomplished. when specifying complimentary mode of operation, only tw o edge comparators are required to generate the output pwm signals for a given submodule. this means that the other comparators are free to perform other functions. in this example, the software doesn?t have to quickly respond after the first conversion to set up other conve rsions that must occur in the same pwm cycle. val1 ($0100) val3 val5 val0 ($0000) val4 val2 init ($ff00) pwma pwmb dblpwm
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-11 pxs20 microcontroller reference manual, rev. 1 figure 25-8. multiple output trigger generation in hardware since each submodule ha s its own timer, it is possible for each s ubmodule to run at a di fferent frequency. one of the options possible with th is pwm module is to have one or more submodules running at a lower frequency, but still synchronized to the timer in submodule0. figure 25-9 shows how this feature can be used to schedule adc triggers over multiple pwm cycl es. a suggested use for this configuration would be to use the lower frequency submodule to contro l the sampling frequency of the software control algorithm where multiple adc tr iggers can now be scheduled ove r the entire sampling period. in figure 25-9 , all submodule comparators are shown be ing used for adc trigger generation. val1 ($0100) val3 val5 val4 val2 init ($ff00) pwm output triggers
flexible motor control pulse width modulator module (flexpwm) 25-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 25-9. multiple output triggers over several pwm cycles 25.3.2.6 enhanced capture capabilities (e-capture) when a pwm pin is not being used fo r pwm generation, it can be used to perform input ca ptures. recall that for pwm generation both edge s of the pwm signal are specified via separate co mpare register values. when programmed for input capture, both of these registers work on the same pin to capture multiple edges, toggling from one to the other in either a free running or one-s hot fashion. by simply programming the desired edge of each capture circuit, period and pulse width of an input signal can easily be measured without the requi rement to re-arm the circui t. in addition, each edge of the input signal can clock an 8 bit counter where the c ounter output is compared to a user specified value (edgcmp). when the counter output equals edgcmp, the value of the submodule timer is captu red and the counter is automatically reset. this feature allows the module to count a sp ecified number of edge events and then perform a capture and interrupt. figure 25-10 illustrates some of the functionality of the e-capture circuit. val5 val4 val3 val1 val0 output triggers val2 reload submodule0 counter (pwm generation) submodule1 counter
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-13 pxs20 microcontroller reference manual, rev. 1 figure 25-10. capture capabiliti es of the e-capture circuit when a submodule is being used fo r pwm generation, its timer counts up to the modulus value used to specify the pwm frequency and then is re-initialized. therefore, using this time r for input captures on one of the other pins (e.g, pw mx) has limited utility si nce it does not count thr ough all of the numbers and the timer reset represents a discontinuity in the 16 bit number range. however, when measuring a signal that is synchronous to the pwm frequency, the timer m odulus range is perfectly su ited for the application. as an example, consider figure 25-11 . in this application the output of a pwm power stage is connected to the pwmx pin that is configured for free running input captures. specifi cally, the cval0 capture circuitry is programmed for ri sing edges and the cval1 capt ure circuitry is set for fa lling edges. this will result in new load pulse width data being acquired every pwm cycle. to calculate the pu lse width, simply subtract the cval0 register value from the cval1 register value. this measurement is extremely beneficial when performing dead-tim e distortion correction on a half bri dge circuit drivi ng an inductive load. also, these values can be di rectly compared to the valx regi sters responsible for generating the pwm outputs to obtain a measuremen t of system propagation delays. set edge count value to 5 enable edge counter capture occurs after 5 edges capture occurs after 5 edges switch mux to input pin set to free run mode set cval1 to rising edge set cval0 to rising edge capture on cval0 capture on cval1 capture on cval0 capture on cval1 set to one-shot mode set capt0 to falling edge capture on cvla0 capture on cval1 re-arm capture circuit capture on cvla0 capture on cval1 set capt1 to falling edge set capt0 to rising edge
flexible motor control pulse width modulator module (flexpwm) 25-14 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 25-11. output pulse width measuremen t possible with the e-capture circuit 25.3.2.7 synchronous switch ing of multiple outputs before the pwm signals are routed to the output pins, they are processed by a hardware block that permits all submodule outputs to be switched synchronously. this feature ca n be extremely useful in commutated motor applications where the next co mmutation state can be laid in ah ead of time and then immediately switched to the outputs when the appropriate conditi on or time is reached. not only do all the changes occur synchronously on all submodule outputs, but th ey occur immediately after the trigger event occurs eliminating a ny interrupt latency. the synchronous output switching is accomplished via a signal cal led force_out. this signal originates from the local force bit within the s ubmodule, from submodule0, or from external to the pwm module and, in most cases, is supplied from an external timer channel configured for output compare. in a typical appl ication, software sets up the desired states of the output pins in preparation for the next force_out event. this selection lays dormant until the force_out signal transitions and then all outputs are switched simultaneously. th e signal switching is performed upstream from the deadtime generator so that any abr upt changes that might oc cur do not violate dead time on the power stage when in complementary mode. figure 25-12 shows a popular application that can benefit from this feature. on a brushless dc motor it is desirable on many cases to spin th e motor without need of hall-effect sensor feedback. instead, the back emf of the motor phases is monitore d and this information is used to schedule the next commutation event. the top waveforms of figure 25-12 are a simplistic representation of these back emf signals. to pwmx input i+ i- v+ v- actual load voltage pulse width is measured during deadtime, load inductance drives voltage with polarity that keeps inductive current flowing through diodes. pwma pwmb actual load voltage (for i+) actual load voltage (for i-)
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-15 pxs20 microcontroller reference manual, rev. 1 timer compare events (represented by the long vertical lines in the di agram) are scheduled based on the zero crossings of the back-emf waveforms. the pw m module is configured via software ahead of time with the next state of the pwm pins in anticipation of the compare ev ent. when it happens, the output compare of the timer drives the force_out signal which immediatel y changes the state of the pwm pins to the next commutation state with no software latency. figure 25-12. sensorless bldc commutation using the force out function 25.3.3 functional details this section describes the implementation of va rious sections of the pwm in greater detail. 25.3.3.1 pwm clocking figure 25-13 shows the logic used to generate the main c ounter clock. each subm odule can select between three clock signals: the ipbus clock, ext_clk, and aux_clk. the ext_clk is generated by an rotor electrical position (degrees) 0 60 120 180 240 300 360 phase r phase s phase t pwma0 pwma1 pwma2 pwmb0 pwmb1 pwmb2 zero crossings
flexible motor control pulse width modulator module (flexpwm) 25-16 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 on-chip resource such as a timer module and goes to all of the submodules. the aux_clk signal is broadcast from submodule0 and can be selected as the clock source by other subm odules so that the 8 bit prescaler and run bit from submodul e0 can control all of the submodul es. when aux_clk is selected as the source for the submodule cloc k, the run bit from s ubmodule0 is used instea d of the local run bit from this submodule. figure 25-13. clocking block diagram for each pwm submodule to permit lower pwm frequencies, the prescaler produces the pwm clock frequency by dividing the ipbus clock frequency by 1-128. the prescaler bits, prsc , in the control register (ctrl1), select the prescaler divisor. this prescaler is buffered and will not be used by the pwm generator until the ldok bit is set and a new pwm reload cycle begins or ldmod is set. 25.3.3.2 register reload logic the register reload logic is used to determine when th e outer set of regi sters for all double buffered register pairs will be transferred to the inne r set of registers. the register re load event can be scheduled to occur every "n" pwm cycles using the ldfq bits and the full bit. a half cycle reload option is also supported (half) where the reload can take place in the middle of a pwm cycle. the half cycle point is defined by the val0 register and does not have to be exactly in the middle of the pwm cycle. as illustrated in figure 25-14 the reload signal from submodule0 can be broadcast as the master reload signal allowing the reload logic from submodule0 to co ntrol the reload of registers in other submodules. figure 25-14. register reload logic 16 bit counter run 8 bit prescaler init value ipbus clock aux_clk input (from submod0) clk_sel aux_clk output (from submod0 only) init psrc submodule clock 0 1 2 3 ext_clk reserved 0 1 reload logic (counts pwm cycles) local reload ldok mod compare half compare master reload register reload master reload (from submod0 only) reload_sel reload opportunity (to on-chip trigger unit)
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-17 pxs20 microcontroller reference manual, rev. 1 25.3.3.3 counter synchronization referring to figure 25-15 , the 16 bit counter will c ount up until its output equals val1 which is used to specify the counter modulus value. the resulting comp are causes a rising edge to occur on the local sync signal which is one of four possible s ources used to cause the 16 bit counter to be initialized with init. if local sync is selected as the c ounter initialization signal, then va l1 within the submodule effectively controls the timer period (and thus the pwm fre quency generated by that submodule) and everything works on a local level. figure 25-15. submodule timer synchronization the master sync signal originates as the local sync from submodule0. if configured to do so, the timer period of any submodule can be locked to the period of the timer in s ubmodule0. the val1 register and associated comparator of the other submodules can then be freed up for other functions such as pwm generation, input captures, output compares, or output triggers. the ext_sync signal originates on chip or off chip depending on the system architecture. this signal may be selected as the source for count er initialization so that an extern al source can cont rol the period of all submodules. if the master reload signal is select ed as the source for counter initializa tion, then the period of the counter will be locked to the register reload frequency of submodule0. since the reload frequency is usually commensurate to the sampling freque ncy of the software control algor ithm, the submodule counter period will therefore equal the sampling peri od. as a result, this ti mer can be used to ge nerate output compares or output triggers over the entire sampling period which ma y consist of several pw m cycles. the master reload signal can only originate from submodule0. the counter can optionally initia lize upon the assertion of the force _out signal assuming that the force_en bit is set. as indicated by figure 25-15 , this constitutes a second init input into the counter which will cause the counter to initia lize regardless of which signal is selected as the counter init signal. 16 bit counter init init 16 bit comparator val1 mod compare processing logic master reload ext_sync master sync 0 1 2 3 init_sel local sync master sync (from submod0 only) submodule clock force_out force_en
flexible motor control pulse width modulator module (flexpwm) 25-18 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 the force_out signal is provided mainly for comm utated applications. when pwm signals are commutated on an inverter c ontrolling a brushless dc motor, it is necessary to restart the pwm cycle at the beginning of the commutation inte rval. this action effectively re synchronizes the pwm waveform to the commutation timing. otherwise, the average volta ge applied to a motor winding integrated over the entire commutation interval will be a function of th e timing between the asynch ronous commutation event with respect to the pwm cycle. th e effect is more criti cal at higher motor speeds where each commutation interval may consist of only a few pwm cycles. if th e counter is not initialized at the start of each commutation interval, the result will be an oscill ation caused by the beati ng between the pwm frequency and the commutation frequency. 25.3.3.4 pwm generation figure 25-16 illustrates how pwm generation is accomplishe d in each submodule. in each case, two comparators and associated valx registers are utilized for each pwm output signa l. one comparator and valx register is used to control the turn on edge while a second compar ator and valx register control the turn off edge. figure 25-16. pwm generation hardware 16 bit comparator 16 bit comparator 16 bit comparator 16 bit comparator d r q pwm23_init pwm on pwm off 16 bit comparator 16 bit comparator d s r q pwm45_init pwm on pwm off val0 val1 val2 val3 val4 val5 output triggers compare interrupts 16 bit counter r q pwmx_init pwm on pwm off d s s half comp mod comp (inverted pwm23 pwm45 pwmx force_out force_en force init to force out logic local sync)
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-19 pxs20 microcontroller reference manual, rev. 1 the generation of the local sync si gnal is performed exactly the same way as the other pwm signals in the submodule. while compar ator 0 causes a rising edge of the loca l sync signal, comp arator 1 generates a falling edge. comparator 1 is also hardwired to the reload logic to generate the half cycle reload indicator. if val1 is controlling the modulus of the counter and val0 is half of the val1 register minus the init value, then the half cycle reload pulse will occur exactly half way through the timer count period and the local sync will have a 50% duty cycle. on the other hand, if the val1 a nd val0 registers are not required for register reloading or c ounter initialization, they can be used to modulate the duty cycle of the local sync signal effectively turn ing it into an auxiliar y pwm signal (pwmx) a ssuming that the pwmx pin is not being used for another function such as input capture or deadtime distortion correction. including the local sync signal, e ach submodule is capable of genera ting 3 pwm signals where software has complete control over each edge of each of the signals. if the comparators and edge value registers are not required for pwm ge neration, they can also be used for other functions such as output compares, generati ng output triggers, or gene rating interrupts at timed intervals. the 16-bit comparators shown in figure 25-16 are "equal to or greater than" not just "equal to" comparators. in addition, if both the set and reset of the flip-flop are both asserted, then the flop output goes to 0. 25.3.3.5 output compare capabilities by using the valx registers in conjunction with th e submodule timer and 16 b it comparators, buffered output compare functionality can be achieved with no additional hardware required. specifically, the following output compare functions are possible: ? an output compare sets the output high ? an output compare sets the output low ? an output compare generates an interrupt ? an output compare generates an output trigger referring again to figure 25-16 , an output compare is initiated by programming a valx register for a timer compare which in turn causes the output of the d f lip-flop to either set or reset. for example, if an output compare is desired on the pwma signal that sets it high, va l2 would be programmed with the counter value where the output compare should take place. however, to prevent th e d flip-flop from being reset again after the compare has occurred, the val3 register must be programme d to a value outside of the modulus range of the counter. therefore, a compare that would result in rese tting the d flip-flop output would never occur. conversely, if an output compare is desired on the pwma signal that sets it low, the val3 register is pr ogrammed with the appropriate count value and the val2 re gister is programmed with a value outside the counter modulus range. regardless of whether a high compare or low compare is programmed, an interrupt or output trigger can be generated when the compare event occurs. 25.3.3.6 force out logic for each submodule software can select between seve n signal sources for the force_out signal: the local force bit, the master force signal from submodule0, the local re load signal, the master reload
flexible motor control pulse width modulator module (flexpwm) 25-20 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 signal from submodule0, the local sync signal, the master sync signal from submodule0, or the ext_force signal from on or off chip depending on th e chip architecture. the local signals are used when the user simply wants to ch ange the signals on the output pins of the submodule without regard for synchronization with other s ubmodules. however, if it is required that all signals on all submodule outputs change at the same time, the master signa ls or ext_force signa l should be selected. figure 25-17 illustrates the force logic. the sel23 and sel45 fields each choose from one of four signals that can be supplied to th e submodule outputs: the pwm signal, th e inverted pwm signal, a binary level specified by software via the out23 and out45 bits, or the exta or extb alternate external control signals. the selection can be determined ahead of time and, when a force_out event occurs, these values are presented to the signal selection m ux which immediately switches the requested signal to the output of the mux for fu rther processing downstream. figure 25-17. force out logic the local force signal of submodule0 can be broadcast as the master force signal to other submodules. this feature allows the local force bit of subm odule0 to synchronously update all of the submodule outputs at the same time. the ext_force signal originates from outside the pwm module from a source such as a timer or digital compar ators in the analog-to-digital converter. 25.3.3.7 independent or complementary channel operation writing a logic one to the indep bit of the cnfg re gister configures the pair of pwm outputs as two independent pwm channels. each pwm output is controlled by its own valx pair operating independently of the other output. 0 1 2 3 4 5 6 7 out45 extb pwm45 to deadtime logic dq sel45 force master force ext_force reserved force_sel 0 1 2 3 out23 exta pwm23 dq master force (from submod0 only) force_out pwm23 pwm45 from generation h/w from generation h/w sel23 dblpwm 3 2 0 1 local reload local sync master reload master sync
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-21 pxs20 microcontroller reference manual, rev. 1 writing a logic zero to the indep bit configures th e pwm output as a pair of complementary channels. the pwm pins are paired as shown in figure 25-18 in complementary channe l operation. which signal is connected to the output pin (pwm23 or pwm45) is determined by the ipol bit. figure 25-18. complementary channel pair the complementary channel operation is for driving t op and bottom transistors in a motor drive circuit, such as the one in figure 25-19 . figure 25-19. typical 3 phase ac motor drive complementary operation allows the use of the deadtime insertion feature. 25.3.3.8 deadtime insertion logic figure 25-20 shows the deadtime insertion logic of each submodule which is used to create non-overlapping complementary signals when not in independent mode. va l 3 va l 2 pwm23 pwm45 pwm23 generation va l 5 va l 4 pwm45 generation 0 1 ipol pwm a0 pwm a1 ac inputs to motor pwm a2 pwm b1 pwm b2 pwm b0
flexible motor control pulse width modulator module (flexpwm) 25-22 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 25-20. deadtime insertion and fine control logic while in the complementary mode, a pwm pair can be used to drive top/bottom tr ansistors, as shown in figure 25-20 . when the top pwm channel is active, the bot tom pwm channel is inactive, and vice versa. note to avoid short circuiting the dc bus and endangering the transistor, there must be no overlap of conducting intervals between top and bottom transistor. but the transistor?s characteristics may make its switching-off time longer than switching-on time. to avoid the conducting overlap of top and bottom transistors, deadtime needs to be inserted in the switching period (as illustrated in figure 25-21 ). the deadtime generators automatically insert software-select able activation delays into the pair of pwm outputs. the deadtime registers (dtcnt0 and dtcnt1) specify the number of ipbu s clock cycles to use for deadtime delay. every time the deadtime generator inputs change state, deadtime is inserted. deadtime forces both pwm outputs in the pair to the inactive state. when deadtime is inserted in comp lementary pwm signals connected to an inverter driving an inductive load, the pwm waveform on the invert er output will have a different dut y cycle than what appears on the output pins of the pwm module. this results in a di stortion in the voltage appl ied to the load. a method of correcting this, adding to or subtracting from the pwm va lue used, is discussed next. pwm23 from force out logic pwm23 rising edge detect down counter start dtcnt0 zero pwm45 detect edge falling counter down start dtcnt1 zero to output logic 0 1 ipol 1 0 indep 0 1 0 1 indep 0 1 indep 0 1 dblen pwm45 0 1 dblpwm
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-23 pxs20 microcontroller reference manual, rev. 1 figure 25-21. deadtime insertion 25.3.3.8.1 top/bottom correction in complementary mode, either the top or the bottom transistor controls the output voltage. however, deadtime has to be insert ed to avoid overlap of conducting interval between the top and bottom transistor. both transistors in complementary mode are off dur ing deadtime, allowing the output voltage to be determined by the current status of load and introduce distortion in the output voltage. see figure 25-22 . on ac induction motors running open-loop, the distorti on typically manifests itself as poor low-speed performance, such as torque ripple and rough operation. val1 ($0100) val3 val0 ($0000) val2 init ($ff00) pwma pwmb no deadtime pwma pwmb with deadtime dtcnt0 dtcnt1
flexible motor control pulse width modulator module (flexpwm) 25-24 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 25-22. deadtime distortion during deadtime, load inductance distorts output volta ge by keeping current flow ing through the diodes. this deadtime current flow creates a load voltage that varies with current directi on. with a positive current flow, the load voltage during deadtime is equal to the bottom supply, putting the top transistor in control. with a negative current flow, the lo ad voltage during deadtim e is equal to the top supply putting the bottom transistor in control. remembering that the original pwm pulse widths wh ere shortened by deadtime insertion, the averaged sinusoidal output will be le ss than the desired value. however, wh en deadtime is inserted, it creates a distortion in the motor current waveform. this distor tion is aggravated by dissimi lar turn-on and turn-off delays of each of the transistors. by giving the pwm module information on which transistor is controlling at a given time th is distortion can be corrected. for a typical circuit in complement ary channel operation, only one of the transistors will be effective in controlling the output voltage at any given time. th is depends on the direction of the motor current for that pair. see figure 25-22 . to correct distortion one of two different factors must be added to the desired pwm value, depending on whether the top or bottom transistor is controlling the output voltage. therefore, the software is responsible for calculat ing both compensated pwm valu es prior to placing them in the valx registers. either the val2/val3 or the val4/val5 register pair c ontrols the pulse width at any given time. for a given pwm pair, whether the val2/val3 or val4/val5 pair is active depends on either: ? the state of the current stat us pin, pwmx, for that driver ? the state of the odd/even correction bit, ipol, for that driver to correct deadtime distortion, soft ware can decrease or increase the value in the appropriate valx register. ? in edge-aligned operation, decreasi ng or increasing the pwm value by a correction value equal to the deadtime typically compen sates for deadtime distortion. desired deadtime pwm to top positive negative pwm to bottom positive current negative current load voltage transistor transistor load voltage load voltage current current v+
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-25 pxs20 microcontroller reference manual, rev. 1 ? in center-aligned operation, decreasing or increa sing the pwm value by a correction value equal to one-half the deadtime typically compensates for deadtime distortion. 25.3.3.8.2 manual correction to detect the current status, the voltage on each pwmx pin is sampled twice in a pwm period, at the end of each deadtime. the value is stored in the dtx bi ts in the ctrl1 register. the dtx bits are a timing marker especially indicating when to toggle between pwm value registers. software can then set the ipol bit to switch between val2/val3 and val4 /val5 register pairs according to dtx values. figure 25-23. current-status sense scheme for deadtime correction both d flip-flops latch low, dt0 = 0, dt1 = 0, during deadtime periods if current is large and flowing out of the complementary circuit. see figure 25-23 . both d flip-flops latch the high, dt0 = 1, dt1 = 1, during deadtime periods if curr ent is also large and flowing into the complementary circuit. however, under low-current, the output voltage of the complementary circuit during deadtime is somewhere between the high and low levels. th e current cannot free-wheel through the opposition anti-body diode, regardless of polarity, giving additional distor tion when the current crosses zero. sampled results will be dt0 = 0 and dt1 = 1. thus, the best time to change one pwm value register to another is just before the current zero crossing. pwma pwmb dq clk dq clk voltage sensor pwmx pwma pwmb dt0 dt1 positive current negative
flexible motor control pulse width modulator module (flexpwm) 25-26 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 25-24. output voltage waveforms 25.3.3.9 output logic figure 25-25 shows the output logic of each submodule including how each pwm output has individual fault disabling, polarity c ontrol, and output enable. this allows for maximum flexibility when interfacing to the external circuitry. the pwm23 and pwm45 signals which are output from the deadtime logic in figure 25-25 are positive true signals. in other words, a hi gh level on these signals should result in the corresponding transistor in the pwm inverter being turned on. the voltage level required at the pwm output pin to turn the transistor on or off is a function of the logic between the pin and th e transistor. therefore, it is imperative that the user program the pola and polb bits before enabling the output pins. a fault condition can result in the pwm output being tristated, forced to a logic 1, or forced to a logic 0 depending on the values programmed into the pwmxfs fields. deadtime pwm to top positive negative pwm to bottom load voltage with load voltage with transistor transistor high positive current low positive current current current load voltage with high negative current load voltage with low negative current tbtb t = deadtime interval before assertion of top pwm b = deadtime interval before assertion of bottom pwm v+
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-27 pxs20 microcontroller reference manual, rev. 1 figure 25-25. output logic section 25.3.3.10 e-capture commensurate with the idea of controlling both e dges of an output signal, the enhanced capture (e-capture) logic is designed to meas ure both edges of an input signal. as a result, when a submodule pin is configured for input capture, the cvalx registers asso ciated with that pin are used to record the edge values. figure 25-26 illustrates the block diagram of the e-capture circuit. upon en tering the pin input, the signal is split into two paths. one goes stra ight to a mux input where software can select to pa ss the signal directly to the capture logic for processing. the other path connects the signal to an 8 bit counter which counts both the rising and falling edges of the signal. the output of th is counter is compared to an 8 bit value that is specified by the user (edgcmpx) and when the two values are equal, the comp arator generates a pulse that resets the counter. this pulse is also supplied to the mux input where software can select it to be processed by the capture logic. this feature permits the e- capture circuit to count up to 256 edge events before initiating a capture event. this feature is us eful for dividing down high fr equency signals for capture processing so that capture interrupts don?t overwhelm the cpu. also, this feature can be used to simply generate an interrupt after "n " events have been counted. from deadtime logic 1 0 pwmafs[0] pwm23 disable pwma pola pwmafs[1] pwma output pwma_en 1 0 pwmbfs[0] pwm45 disable pwmb polb pwmbfs[1] pwmb output pwmb_en
flexible motor control pulse width modulator module (flexpwm) 25-28 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 25-26. enhanced capture (e-capture) logic based on the mode selection, the mux selects eith er the pin input or the compare output from the count/compare circuit to be processed by the capture logi c. the selected signal is routed to two separate capture circuits which work in tandem to capture sequent ial edges of the signal. the type of edge to be captured by each circuit is determ ined by the edgx1 and edgx0 bits w hose functionality is listed in figure 25-26 . also, controlling the operation of the captur e circuits is the arming logic which allows captures to be performed in a fr ee running (continuous) or one shot fashion. in free running mode, the capture sequences will be performed indefinitely. if both capt ure circuits are enab led, they will work together in a ping-pong style where a capture event fr om one circuit leads to th e arming of the other and vice versa. in one shot mode, only one capture sequence will be perfor med. if both capture circuits are enabled, capture circuit 0 is first armed and when a capture event occurs , capture circuit 1 is armed. once the second capture occurs, further captures are disabled until another capture sequence is initiated. both capture circuits are also capable of generating an interrupt to the cpu. 25.3.3.11 fault protection fault protection can control any combination of pwm ou tput pins. faults are ge nerated by a logic one on any of the faultx pins. this polarity can be ch anged via the flvl bits. each faultx pin can be mapped arbitrarily to any of the pwm outputs. when fault protection hardware disables pwm outputs, the pwm generator continues to run, only the output pins are forced to logic 0, logic 1, or tristated depending the values of the pwmxfs bits. capture circuit 1 arming logic submodule timer cf1 cie1 edg1 capture circuit 0 cf0 cie0 edg0 en1 capt1 en0 capt0 0 1 inp_sel edgcmp 8 bit counter int int pin input comparator edgcnt_en reset this logic is repeated for pwma, pwmb, and pwmx inputs. edgcnt 00 - disabled 01 - capture falling edges 10 - capture rising edges 11 - capture any edge edgx bits
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-29 pxs20 microcontroller reference manual, rev. 1 the fault decoder disables pwm pins selected by the fault logic and the disable mapping register (dismap). see figure 25-27 for an example of the fault disable l ogic. each bank of bits in dismap control the mapping for a single pwm pin. refer to table 25-2 . the fault protection is enabled even when the pwm m odule is not enabled; therefore, a fault will be latched in and must be cleared in order to prevent an interrupt when the pwm is enabled. figure 25-27. fault decoder for pwma 25.3.3.11.1 fault pin filter each fault pin has a programmable filter that can be bypassed. the sampling peri od of the filter can be adjusted with the filt_per field of the ffiltx regi ster. the number of consecutive samples that must agree before an input transition is recognized can be adjusted using the filt_cnt field of the same register. setting filt_per to all 0 disabl es the input filter for a given faultx pin. upon detecting a logic 0 on the filtered faultx pin (or a logic 1 if flvlx is set), the corresponding ffpinx and fault flag, fflagx, bits ar e set. the ffpinx bit remains set as long as the filtered faultx pin is zero. clear fflagx by writing a logic 1 to fflagx. table 25-2. fault mapping pwm pin controlling register bits pwma disa[3:0] pwmb disb[3:0] pwmx disx[3:0] disa0 disa1 disa2 disa3 disable fault0 fault1 fault2 fault3 pwma wait mode waiten debug mode dbgen stop mode
flexible motor control pulse width modulator module (flexpwm) 25-30 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 if the fiex, faultx pin interrupt enable bit is se t, the fflagx flag generate s a cpu interrupt request. the interrupt request latch remains set until: ? software clears the fflagx flag by writing a logic one to the bit ? software clears the fiex bi t by writing a logic zero to it ? a reset occurs even with the filter enabled, there is a combinational path from the faultx inputs to the pwm pins. this logic is also capable of holding a fault condition in the event of loss of clock to the pwm module. 25.3.3.11.2 automatic fault clearing setting an automatic clearing mode bit, fautox, conf igures faults from the faultx pin for automatic clearing. when fautox is set, disabled pw m pins are enabled when the faultx pin returns to logic one and a new pwm full or half cycle begins. see figure 25-28 . if ffullx is set, then the disabled pwm pins are enabled only at the start of a full cycle and not at th e half cycle. clearing the fflagx flag does not affect disabled pwm pins when fautox is set. figure 25-28. automatic fault clearing 25.3.3.11.3 manual fault clearing clearing the automatic clearing mode bit, fautox, c onfigures faults from the faultx pin for manual clearing: ? if the fault safety mode bits, fsa fex, are clear, then pwm pins di sabled by the faultx pins are enabled when: ? software clears the corresponding fflagx flag ? the pins are enabled when the ne xt pwm full or half cycle begins regardless of the logic level detected by the filter at the faultx pin. see figure 25-29 . if ffullx is set, then the disabled pwm pins are enabled only at the start of a full cycle and not at the half cycle. ? if the fault safety mode bits, fsafex, are set, then pwm pins disabled by the faultx pins are enabled when: ? software clears the corresponding fflagx flag ffpinx bit count outputs half cycle enabled disabled enabl disable enabled
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-31 pxs20 microcontroller reference manual, rev. 1 ? the filter detects a logic one on the faultx pin at the start of the next pwm full or half cycle boundary. see figure 25-30 . if ffullx is set, then the disabled pwm pins are enabled only at the start of a full cycle and not at the half cycle. figure 25-29. manual fault clearing (fsafe=0) figure 25-30. manual fault clearing (fsafe=1) note fault protection also applies during software output control when the sel23 and sel45 fields are set to sele ct out23 and out45 bits or exta and extb. fault clearing still occurs at half pwm cycle boundaries while the pwm generator is engaged, run e quals one. but the outx bits can control the pwm pins while the pwm generator is off, run equals zero. thus, fault clearing occurs at ipbus cycles while the pwm generator is off and at the start of pwm cycles when the generator is engaged. 25.3.3.11.4 fault testing the ftest bit is used to simulate a fa ult condition on each of the fault inputs. enabled ffpinx bit enabled disabled fflagx cleared count outputs enabled ffpinx bit enabled disabled fflagx cleared count outputs
flexible motor control pulse width modulator module (flexpwm) 25-32 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 25.3.4 pwm generator loading 25.3.4.1 load enable the ldok bit enables loading of the following pwm generator parameters: ? the prescaler divisor?from the prsc bits in the ctrl1 register ? the pwm period and pulse width?from the init and valx registers ldok allows software to finish calculating all of thes e pwm parameters so they can be synchronously updated. the psrc, init, and valx registers are loaded by software into a set of outer buffers. when ldok is set, these values are transferred to an i nner set of registers at th e beginning of the next pwm reload cycle to be used by the pwm generator. these values can be transfered to the inner set of registers immediately upon setting ldok if ldm od is set. set ldok by reading it when it is a logic zero and then writing a logic one to it. after loading, ldok is automatically cleared. 25.3.4.2 load frequency the ldfq bits in the ctrl1 regist er select an integral loading fr equency of one to 16 pwm reload opportunities. the ldfq bits take effect at every pwm reload oppor tunity, regardless the state of the ldok bit. the half and full bits in the ctrl1 register control reload timing. if full is set, a reload opportunity occurs at the e nd of every pwm cycle when the count equa ls val1. if half is set, a reload opportunity occurs at the ha lf cycle when the count equals val0. if both half and full are set, a reload opportunity occurs twice per pwm cycle when the count equals val1 and when it equals val0. figure 25-31. full cycle reload frequency change counter reload change reload frequency every two opportunities to every four opportunities to every opportunity
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-33 pxs20 microcontroller reference manual, rev. 1 figure 25-32. half cycle reload frequency change figure 25-33. full and half cycle reload frequency change 25.3.4.3 reload flag at every reload opportunity the pwm re load flag (rf) in the ctrl1 regist er is set. setting rf happens even if an actual reload is prevente d by the ldok bit. if the pwm reload interrupt enable bit, rie is set, the rf flag generates cpu interrupt requests allowing softwa re to calculate new pw m parameters in real time. when rie is not set, reloads still occur at the selected reload rate without genera ting cpu interrupt requests. figure 25-34. pwmf reload interrupt request counter reload change reload frequency every two opportunities to every four opportunities to every opportunity counter reload change reload frequency every two opportunities to every four opportunities to every opportunity to every two opportunities v dd cpu interrupt pwm reload request dq clk clr read rf as 1 then write 0 to rf reset rf rie
flexible motor control pulse width modulator module (flexpwm) 25-34 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 25.3.4.4 reload errors whenever one of the valx, fracx, or psrc registers is update d, the ruf flag is set to indicate that the data is not coherent. ruf will be cleared by a succe ssful reload which consists of the reload signal while ldok is set. if ruf is set and ldok is clear when the reload signal occurs, a re load error has taken place and the ref bit is set. if ruf is clear when a reload signal asserts, then the da ta is coherent and no error will be flagged. 25.3.4.5 initialization initialize all registers and set the ldok bit before setting the run bit. note even if ldok is not set, setting run also sets the rf flag. to prevent a cpu interrupt request, clear the rie bit before setting run. the pwm generator uses the last values loaded if run is cleared and then set while ldok equals zero. when the run bit is cleared: ? the rf flag and pending cpu interrupt requests are not cleared ? all fault circuitry remains active ? software/external output control remains active ? deadtime insertion continues duri ng software/external output control
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-35 pxs20 microcontroller reference manual, rev. 1 25.4 memory map and registers 25.4.1 module memory map table 25-3. pwm registers address reg name description pwm submodule registers (repeated for each submodule as sub goes from 0 to 3) mcpwm_base + ($50 * sub) + $00 cnt counter register mcpwm_base + ($50 * sub) + $02 init initial count register mcpwm_base + ($50 * sub) + $04 ctrl2 control 2 register mcpwm_base + ($50 * sub) + $06 ctrl1 control 1 register mcpwm_base + ($50 * sub) + $08 val0 value register 0 mcpwm_base + ($50 * sub) + $0a val1 value register 1 mcpwm_base + ($50 * sub) + $0c val2 value register 2 mcpwm_base + ($50 * sub) + $0e val3 value register 3 mcpwm_base + ($50 * sub) + $10 val4 value register 4 mcpwm_base + ($50 * sub) + $12 val5 value register 5 mcpwm_base + ($50 * sub) + $14 reserved mcpwm_base + ($50 * sub) + $16 reserved mcpwm_base + ($50 * sub) + $18 octrl output control register mcpwm_base + ($50 * sub) + $1a sts status register mcpwm_base + ($50 * sub) + $1c int en interrupt enable register mcpwm_base + ($50 * sub) + $1e dmaen dma enable register mcpwm_base + ($50 * sub) + $20 tctr l output trigger control register mcpwm_base + ($50 * sub) + $22 dism ap fault disable mapping register mcpwm_base + ($50 * sub) + $24 dt cnt0 deadtime coun t register 0 mcpwm_base + ($50 * sub) + $26 dt cnt1 deadtime coun t register 1 mcpwm_base + ($50 * sub) + $28 reserved mcpwm_base + ($50 * sub) + $2a reserved mcpwm_base + ($50 * sub) + $2c reserved mcpwm_base + ($50 * sub) + $2e reserved mcpwm_base + ($50 * sub) + $30 capt ctrlx capture cont rol register x mcpwm_base + ($50 * sub) + $32 capt compx capture compare register x mcpwm_base + ($50 * sub) + $34 cval0 capture value 0 register mcpwm_base + ($50 * sub) + $36 cval0c capture value 0 cycle register mcpwm_base + ($50 * sub) + $38 cval1 capture value 1 register mcpwm_base + ($50 * sub) + $3a cval1c capture value 1 cycle register
flexible motor control pulse width modulator module (flexpwm) 25-36 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 25.4.2 register descriptions the address of a register is the sum of a base address and an address offs et. the base addres s is defined at the core level and the address offset is defined at th e module level. there are a set of registers for each pwm submodule, for the configuration logic, and for each fault channel. 25.4.3 submodule registers these registers are repeated for each pwm submodule. the base address of submodule 0 is the same as the base address for the pwm module as a whole. th e base address of submodule 1 is $50. this is the base address of the pwm module plus an offset ba sed on the number of registers in a submodule. the base address of submodule 2 is e qual to the base address of subm odule 1 plus this same offset. mcpwm_base + ($50 * sub) + $3c reserved mcpwm_base + ($50 * sub) + $3e reserved mcpwm_base + ($50 * sub) + $40 reserved mcpwm_base + ($50 * sub) + $42 reserved mcpwm_base + ($50 * sub) + $44 reserved mcpwm_base + ($50 * sub) + $46 reserved mcpwm_base + ($50 * sub) + $48 reserved mcpwm_base + ($50 * sub) + $4a reserved configuration logic registers mcpwm_base + $140 outen output enable register mcpwm_base + $142 mask output mask register mcpwm_base + $144 swcout software controlled output register mcpwm_base + $146 dtsrcsel deadt ime source select register mcpwm_base + $148 mctrl m aster control register fault channel registers mcpwm_base + $14c fctrl fault control register mcpwm_base + $14e fsts f ault status register mcpwm_base + $150 ffilt f ault filter register table 25-3. pwm registers (continued) address reg name description
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-37 pxs20 microcontroller reference manual, rev. 1 25.4.3.1 counter register (cnt) figure 25-35. counter register (cnt) this read-only register displays th e state of the signed 16-bit submodule co unter. this regi ster is not byte accessible. 25.4.3.2 initial count register (init) figure 25-36. initial count register (init) the 16-bit signed value in this buffere d, read/write register defines the initial count value for the pwm in pwm clock periods. this is the value loaded into the submodule counter when local sync, master sync, or master reload is asserted (based on the value of init_sel) or when force is asserted and force init is enabled. for pwm operation, the buffered contents of this register are loaded into the counter at the start of every pwm cycle. this register is not byte accessible. note the init register is buffered. the value written does not take effect until the ldok bit is set and the next pwm load cycle begins or ldmod is set. this register cannot be written when ldok is set. read ing init reads the value in a buffer and not necessarily the va lue the pwm generator is currently using. 25.4.3.3 control 2 register (ctrl2) figure 25-37. control 2 register (ctrl2) pwm_sub_ base+$0 0 123456789101112131415 read cnt write reset 000000000000 0 000 pwm_sub_ base+$2 0 123456789101112131415 read init write reset 000000000000 0 000 pwm_sub _base+$4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 read dbg en wai ten in- dep pwm 23_ init pwm 45_ init pwm x_ init init_sel frc en 0 force_sel re- loa d _sel clk_sel write for ce reset 0000000000000000
flexible motor control pulse width modulator module (flexpwm) 25-38 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 dbgen - debug enable when set to one, the pwm will contin ue to run while the chip is in debug mode. if th e device enters debug mode and this bit is zero, then the pwm outputs will be disabled until de bug mode is exited. at that point the pwm pins will resume opera tion as programmed in the pwm registers. for certain types of motors (such as 3- phase ac), it is imperative that th is bit be left in its default state (in which the pwm is disabled in debug mode). failure to do so coul d result in damage to the motor or inverter. for other types of motors (example: dc motors), this bit might safely be set to one, enabling the pwm in debug mode. the key point is pwm parameter updates will not occur in debug mode. any motors requiring such updates should be disabled duri ng debug mode. if in doubt, leave this bit set to zero. waiten - wait enable when set to one, the pwm will continue to run whil e the chip is in wait mode. in this mode, the peripheral clock continues to run but the cpu cloc k does not. if the device enters wait mode and this bit is zero, then the pwm outputs will be disabled until wait mode is exited. at that point the pwm pins will resume operation as programmed in the pwm registers. for certain types of motors (such as 3- phase ac), it is imperative that th is bit be left in its default state (in which the pwm is disabled in wa it mode). failure to do so coul d result in damage to the motor or inverter. for other types of motors (example: dc motors), this bit might safely be set to one, enabling the pwm in wait mode. the key point is pwm parameter updates will not occur in this mode. any motors requiring such updates should be disabled during wait mode. if in doubt, leave this bit set to zero. indep - independent or comp lementary pair operation this bit determines if the pwma and pwmb channels will be independent pwms or a complementary pwm pair. 1 = pwma and pwmb outputs are independent pwms. 0 = pwma and pwmb form a complementary pwm pair. pwm23_init - pwm23 initial value this read/write bit determines the initial value fo r pwm23 and the value to which it is forced when force_init ( figure 25-16 ) is asserted. pwm45_init - pwm45 initial value this read/write bit determines the initial value fo r pwm45 and the value to which it is forced when force_init ( figure 25-16 ) is asserted. pwmx_init - pwmx initial value this read/write bit determines the initial value fo r pwmx and the value to which it is forced when force_init ( figure 25-16 ) is asserted. init_sel - initialization control select these read/write bits contro l the source of the init signal which goes to the counter. ? 00 = local sync (pwmx) causes initialization.
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-39 pxs20 microcontroller reference manual, rev. 1 ? 01 = master reload from submodule 0 causes init ialization. this setting should not be used in submodule 0 as it will force the init signal to logic 0. ? 10 = master sync from submodule 0 causes init ialization. this setting should not be used in submodule 0 as it will force the init signal to logic 0. ? 11 = ext_sync caus es initialization. frcen - force initialization enable this bit allows the force_out signa l to initialize the counter without regard to the signal selected by init_sel. this is a softwa re controlled initialization. 1 = initialization from a fo rce out event is enabled. 0 = initialization from a fo rce out event is disabled. force - force initialization if the force_sel bits are set to 000, writing a 1 to th is bit results in a force out event. this causes the following actions to be taken: ? the pwma and pwmb output pins will assume values based on the sel23 and sel45 bits. ? if the frcen bit is set, the c ounter value will be initialized with the init register value. force_sel - force source select this read/write bit determines the source of the force output signal for this submodule. ? 000 = the local force signal, force, from this submodule is us ed to force updates. ? 001 = the master force si gnal from submodule 0 is used to force updates. this setting should not be used in submodule 0 as it will hold the force output signal to logic 0. ? 010 = the local reload signal from th is submodule is used to force updates. ? 011 = the master reload signal fr om submodule0 is used to force updates. this setting should not be used in submodule0 as it will hold the force output signal to logic 0. ? 100 = the local sync signal from this submodule is used to force updates. ? 101 = the master sync signal from submodule0 is used to force up dates. this setting should not be used in submodule0 as it will hold the force output signal to logic 0. ? 110 = the external force signal, ext_force , from outside the pwm module causes updates. ?111 = reserved reload_sel - reload source select this read/write bit determines the source of the reload signal for this submodule. when this bit is set, the ldok bit in submodule 0 should be used since the local ldok bit will be ignored. 1 = the master reload signal (from submodule 0) is used to reload registers. this setting should not be used in submodule 0 as it will force the reload signal to logic 0. 0 = the local reload signal is used to reload registers. clk_sel - clock source select these read/write bits determine the source of the clock signal for this submodule. ? 00 = the ipbus clock is used as the cl ock for the local prescaler and counter. ? 01 = ext_clk is used as the clock for the local prescaler and counter.
flexible motor control pulse width modulator module (flexpwm) 25-40 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? 10 = submodule 0?s clock (aux_clk ) is used as the source cloc k for the local prescaler and counter. this setting should not be used in s ubmodule 0 as it will force the clock to logic 0. ?11 = reserved 25.4.3.4 control 1 register (ctrl1) figure 25-38. control 1 register (ctrl1) ldfq - load frequency these buffered read/write bits select the pwm load frequency according to table 25-4 . reset clears the ldfq bits, selecting loading every pwm oppor tunity. a pwm opportunity is determined by the half and full bits. note the ldfqx bits take effect when the current load cycle is complete regardless of the state of the ldok bit. reading the ldfqx bits reads the buffered values and not necessarily the values currently in effect. pwm_sub _base+$6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 read ldfq hal f full dt 0 prsc 0 ld- mod 0dbl en write reset 0000010000000000 table 25-4. pwm reload frequency ldfq pwm reload frequency 0000 every pwm opportunity 0001 every 2 pwm opportunities 0010 every 3 pwm opportunities 0011 every 4 pwm opportunities 0100 every 5 pwm opportunities 0101 every 6 pwm opportunities 0110 every 7 pwm opportunities 0111 every 8 pwm opportunities 1000 every 9 pwm opportunities 1001 every 10 pwm opportunities 1010 every 11 pwm opportunities 1011 every 12 pwm opportunities 1100 every 13 pwm opportunities 1101 every 14 pwm opportunities 1110 every 15 pwm opportunities 1111 every 16 pwm opportunities
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-41 pxs20 microcontroller reference manual, rev. 1 half - half cycle reload this read/write bit enables half-cycle reloads. a half cycle is defined by when the submodule counter matches the val0 register and does not ha ve to be half way through the pwm cycle. 1 = half-cycle reloads enabled. 0 = half-cycle reloads disabled. full - full cycle reload this read/write bit enables full-c ycle reloads. a full cycle is defined by when the submodule counter matches the val1 register. either the half or fu ll bit must be set in order to move the buffered data into the registers used by the pwm generators . if both the half and full bits are set, then reloads can occur twice per cycle. 1 = full-cycle reloads enabled. 0 = full-cycle reloads disabled. dt - deadtime these read only bits reflect the sampled values of the pwmx input at the end of each deadtime. sampling occurs at the end of deadtime 0 for dt[0] a nd the end of deadtime 1 fo r dt[1]. reset clears these bits. prsc - prescaler these buffered read/write bits se lect the divide ratio of the pwm clock frequency selected by clk_sel as illustrated in table 25-5 . note reading the prscx bits reads the buffered values and not necessarily the values currently in effect. the prscx bi ts take effect at the beginning of the next pwm cycle and only when the load okay bit, ldok, is set or ldmod is set. this field cannot be written when ldok is set. ldmod - load mode select this read/write bit selects the timing of load ing the buffered register s for this submodule. table 25-5. pwm prescaler prsc pwm clock frequency 000 f clk 001 f clk /2 010 f clk /4 011 f clk /8 100 f clk /16 101 f clk /32 110 f clk /64 111 f clk /128
flexible motor control pulse width modulator module (flexpwm) 25-42 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 1 = buffered registers of this submodule are loaded and take e ffect immediately upon ldok being set. 0 = buffered registers of this s ubmodule are loaded and take effect at the next pwm reload if ldok is set. dblen - double switching enable this read/write bit enables th e double switching pwm behavior. 1 = double switching enabled. 0 = double switching disabled. 25.4.3.5 value register 0 (val0) figure 25-39. value register 0 (val0) the 16-bit signed value in this buffered, read/write re gister defines the mid-cycle reload point for the pwm in pwm clock periods. this value also define s when the pwmx signal is set and the local sync signal is reset. this regi ster is not byte accessible. note the val0 register is buffered. the va lue written does not take effect until the ldok bit is set and the next pwm lo ad cycle begins or ldmod is set. val0 cannot be written wh en ldok is set. readi ng val0 reads the value in a buffer. it is not necessarily th e value the pwm generator is currently using. 25.4.3.6 value register 1 (val1) figure 25-40. value register 1 (val1) the 16-bit signed value written to this buffered, re ad/write register defines the modulo count value (maximum count) for the submodule count er. upon reaching this count value, the counter will reload itself with the contents of the init register and assert the local sync signal while reset ting pwmx. this register is not byte accessible. pwm_sub_ base+$8 0 123456789101112131415 read val0 write reset 000000000000 0 000 pwm_sub_ base+$a 0 123456789101112131415 read val1 write reset 000000000000 0 000
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-43 pxs20 microcontroller reference manual, rev. 1 note the val1 register is buffered. the va lue written does not take effect until the ldok bit is set and the next pwm lo ad cycle begins or ldmod is set. val1 cannot be written wh en ldok is set. readi ng val1 reads the value in a buffer and not necessarily the va lue the pwm generator is currently using. since the val1 register is used to defi ne the pwm period as well as turn off the pwmx output, a 100% duty cycle cannot be achieved on the pwmx output due to the inability to program val1 with a value grater than val1. 25.4.3.7 value register 2 (val2) figure 25-41. value register 2 (val2) the 16-bit signed value in this buffered, read/write register defines the count value to set pwm23 high ( figure 25-2 ). this register is not byte accessible. note the val2 register is buffered. the va lue written does not take effect until the ldok bit is set and the next pwm lo ad cycle begins or ldmod is set. val2 cannot be written wh en ldok is set. readi ng val2 reads the value in a buffer and not necessarily the va lue the pwm generator is currently using. 25.4.3.8 value register 3 (val3) figure 25-42. value register 3 (val3) the 16-bit signed value in this buffered, read/write register defines the count value to set pwm23 low ( figure 25-2 ). this register is not byte accessible. pwm_sub_ base+$c 0 123456789101112131415 read val2 write reset 000000000000 0 000 pwm_sub_ base+$e 0 123456789101112131415 read val3 write reset 000000000000 0 000
flexible motor control pulse width modulator module (flexpwm) 25-44 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 note the val3 register is buffered. the va lue written does not take effect until the ldok bit is set and the next pwm lo ad cycle begins or ldmod is set. val3 cannot be written wh en ldok is set. readi ng val3 reads the value in a buffer and not necessarily the va lue the pwm generator is currently using. 25.4.3.9 value register 4 (val4) figure 25-43. value register 4 (val4) the 16-bit signed value in this buffered, read/write register defines the count value to set pwm45 high ( figure 25-2 ). this register is not byte accessible. note the val4 register is buffered. the va lue written does not take effect until the ldok bit is set and the next pwm lo ad cycle begins or ldmod is set. val4 cannot be written wh en ldok is set. readi ng val4 reads the value in a buffer and not necessarily the va lue the pwm generator is currently using. 25.4.3.10 value register 5 (val5) figure 25-44. value register 5 (val5) the 16-bit signed value in this buffered, read/write register defines the count value to set pwm45 low ( figure 25-2 ). this register is not byte accessible. note the val5 register is buffered. the va lue written does not take effect until the ldok bit is set and the next pwm lo ad cycle begins or ldmod is set. val5 cannot be written wh en ldok is set. readi ng val5 reads the value in a buffer and not necessarily the va lue the pwm generator is currently using. pwm_sub_ base+$10 0 123456789101112131415 read val4 write reset 000000000000 0 000 pwm_sub_ base+$12 0 123456789101112131415 read val5 write reset 000000000000 0 000
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-45 pxs20 microcontroller reference manual, rev. 1 25.4.3.11 output control register (octrl) figure 25-45. output control register (octrl) pwma_in - pwma input this read only bit shows the logic value cu rrently being driven into the pwma input. pwmb_in - pwmb input this read only bit shows the logic value cu rrently being driven into the pwmb input. pwmx_in - pwmx input this read only bit shows the logic value cu rrently being driven into the pwmx input. pola - pwma output polarity this bit inverts the pwma output polarity. 1 = pwma output inverted. a low level on the pwma pin represents the "on" or "active" state. 0 = pwma output not inverted. a high level on th e pwma pin represents the "on" or "active" state. polb - pwmb output polarity this bit inverts the pwmb output polarity. 1 = pwmb output inverted. a low level on the pwmb pin represents the "on" or "active" state. 0 = pwmb output not inverted. a high level on the pw mb pin represents the " on" or "active" state. polx - pwmx output polarity this bit inverts the pwmx output polarity. 1 = pwmx output inverted. a low level on the pwmx pin represents the "on" or "active" state. 0 = pwmx output not inverted. a high level on th e pwmx pin represents the "on" or "active" state. pwmafs - pwma fault state these bits determine the fault state for the pwma output during fault conditions and stop mode. it may also define the output state during wait and debug modes depending on the settings of waiten and dbgen. ? 00 = output is forced to logic 0 state prio r to consideration of output polarity control. ? 01 = output is forced to logic 1 state prio r to consideration of output polarity control. ? 1x = output is tristated. pwm_sub _base+$1 8 0 123456789101112131415 read pwm a_in pwm b_in pwm x_in 00 pol a pol b pol x 00 pwmafs pwmbfs pwmxfs write reset uuu0000000000000
flexible motor control pulse width modulator module (flexpwm) 25-46 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 pwmbfs - pwmb fault state these bits determine the fault state for the pwmb output during fault conditions and stop mode. it may also define the output state during wait and debug modes depending on the settings of waiten and dbgen. ? 00 = output is forced to logic 0 state prio r to consideration of output polarity control. ? 01 = output is forced to logic 1 state prio r to consideration of output polarity control. ? 1x = output is tristated. pwmxfs - pwmx fault state these bits determine the fault state for the pwmx output during fault conditions and stop mode. it may also define the output state during wait and debug modes depending on the settings of waiten and dbgen. ? 00 = output is forced to logic 0 state prio r to consideration of output polarity control. ? 01 = output is forced to logic 1 state prio r to consideration of output polarity control. ? 1x = output is tristated. 25.4.3.12 status register (sts) figure 25-46. status register (sts) ruf - registers updated flag this read only flag is set when one of the init , valx, fracx, or prsc regi sters has been written resulting in non-coherent data in the set of double buffered registers. clear ruf by a proper reload sequence consisting of a reload signal while ldok = 1. reset clears ruf. 1 = at least one of the double buffered regist ers has been updated since the last reload. 0 = no register update has o ccurred since last reload. ref - reload error flag this read/write flag is set when a reload cy cle occurs while ldok is 0 and the double buffered registers are in a non-coherent state (ruf = 1). clear ref by writing a logic one to the ref bit. reset clears ref. 1 = reload signal occurred with non-coherent data and ldok = 0. 0 = no reload error occurred. rf - reload flag this read/write flag is set at the beginning of ev ery reload cycle regardless of the state of the ldok bit. clear rf by writing a logic one to the rf bit when valde is cl ear (non-dma mode). rf can also be cleared by the dma done si gnal when valde is set (dma mode). reset clears rf. pwm_sub _base+$1 a 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 read 0 ruf ref rf 0000 cfx 1 cfx 0 cmpf write reset 0000000000000000
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-47 pxs20 microcontroller reference manual, rev. 1 1 = new reload cycle since last rf clearing 0 = no new reload cycle since last rf clearing cfx1 - capture flag x1 this bit is set when the word count of the capt ure x1 fifo (cx1cnt) exceeds the value of the cfxwm field. this bit is cleared by writing a one to this bit pos ition if cx1de is clear (non-dma mode) or by the dma done signal if cx1de is set (dma mode). re set clears this bit. cfx0 - capture flag x0 this bit is set when the word count of the capt ure x0 fifo (cx0cnt) exceeds the value of the cfxwm field. this bit is cleared by writing a one to this bit pos ition if cx0de is clear (non-dma mode) or by the dma done signal if cx0de is set (dma mode). re set clears this bit. cmpf - compare flags these bits are set when the submodule counter value matches the va lue of one of the valx registers. clear these bits by writi ng a 1 to a bit position. 1 = a compare event has occurred for a particular valx value. 0 = no compare event has occurred for a particular valx value. 25.4.3.13 interrupt enable register (inten) figure 25-47. interrupt enable register (inten) reie - reload error interrupt enable this read/write bit enables the reload error flag (r ef) to generate cpu interrupt requests. reset clears rie. 1 = ref cpu interrupt requests enabled 0 = ref cpu interrupt requests disabled rie - reload interrupt enable this read/write bit enables the reload flag (rf) to generate cpu interrupt requests. reset clears rie. 1 = rf cpu interrupt requests enabled 0 = rf cpu interrupt requests disabled cx1ie - capture x 1 interrupt enable this bit allows the cfx1 flag to create an interrupt request to the cpu. do not set both this bit and the cx1de bit. 1 = interrupt request enabled for cfx1. 0 = interrupt request disabled for cfx1. pwm_sub _base+$1 c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 read 0 0 reie rie 0000cx1 ie cx0 ie cmpie write reset 0000000000000000
flexible motor control pulse width modulator module (flexpwm) 25-48 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 cx0ie - capture x 0 interrupt enable this bit allows the cfx0 flag to create an interrupt request to the cpu. do not set both this bit and the cx0de bit. 1 = interrupt request enabled for cfx0. 0 = interrupt request disabled for cfx0. cmpie - compare interrupt enables these bits enable the cmpf flags to cause a compare interrupt request to the cpu. 1 = the corresponding cmpf bit will cause an interrupt request. 0 = the corresponding cmpf bit will not cause an interrupt request. 25.4.3.14 dma enable register (dmaen) figure 25-48. dma enable register (dmaen) valde - value registers dma enable this read/write bit enables dma write requests fo r the valx and fracx registers when rf is set. reset clears valde. 1 = dma write requests for the va lx and fracx registers enabled 0 = dma write requests disabled fand - fifo watermark and control this read/write bit works in conjunction with the captde field when it is set to watermark mode (captde = 01). while the cxxde bits determine wh ich fifo watermarks the dma read request is sensitive to, this bit determines if the selected watermarks are and?ed to gether or or?ed together in order to create the request. 1 = selected fifo watermar ks are and?ed together. 0 = selected fifo waterm arks are or?ed together. captde - capture dma enable source select these read/write bits select the source of enabling the dma read reque sts for the capture fifos. reset clears these bits. ? 00 = read dma requests disabled. ? 01 = exceeding a fifo watermark sets the dma re ad request. this requires at least 1 of the cx1de or cx0de bits to also be set in order to determine whic h watermark(s) the dma request is sensitive to. ? 10 = a local sync (val1 matches counter) sets the read dma request. ? 11 = a local reload (rf being set) sets the read dma request. pwm_sub _base+$1 e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 read 0 0 0 0 0 0 val- de fan d captde 0000cx1 de cx0 de write reset 0000000000000000
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-49 pxs20 microcontroller reference manual, rev. 1 cx1de - capture x1 fifo dma enable this read/write bit enable s dma read requests for the capture x1 fi fo data when cfx1 is set. reset clears cx1de. do not set both this bit and the cx1ie bit. cx0de - capture x0 fifo dma enable this read/write bit enable s dma read requests for the capture x0 fi fo data when cfx0 is set. reset clears cx0de. do not set both this bit and the cx0ie bit. 25.4.3.15 output trigger control register (tctrl) figure 25-49. output trigger control register (tctrl) out_trig_en - output trigger enables these bits enable the generati on of out_trig0 and out_trig1 out puts based on the counter value matching the value in one or more of the val0-5 registers. val0, val2, and val4 are used to generate out_trig0 and val1, val3, and val5 are used to generate out_trig1. the out_trigx signals are only asserted as long as the counter value ma tches the valx value, therefore up to six triggers can be genera ted (three each on out_trig0 a nd out_trig1) per pwm cycle per submodule. 1 = out_trigx will set when the count er value matches the valx value. 0 = out_trigx will not set when the counter value matches the valx value. 25.4.3.16 fault disable mapping register (dismap) this register determines which pwm pins are disa bled by the fault protectio n inputs, illustrated in table 25-27 in section 25.3.3.11, fault protection . reset sets all of the bits in the fault disable mapping register. figure 25-50. fault disable mapping register (dismap) disx - pwmx fault disable mask each of the four bit of th is read/write field is one-t o-one associated with the four faultx inputs. the pwmx output will be turned off if there is a logic 1 on a faultx input and a 1 in the corresponding bit of the disx field. a reset sets all disx bits. pwm_sub_ base+$20 0 123456789101112131415 read 0000000000 out_trig_en write reset 000000000000 0 000 pwm_sub_ base+$22 0 123456789101112131415 read 1 1 1 1 disx disb disa write reset 1111111111111111
flexible motor control pulse width modulator module (flexpwm) 25-50 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 disb - pwmb fault disable mask each of the four bit of th is read/write field is one-t o-one associated with the four faultx inputs. the pwmb output will be turned off if there is a logic 1 on a faultx input and a 1 in the corresponding bit of the disb field. a reset sets all disb bits. disa - pwma fault disable mask each of the four bit of th is read/write field is one-t o-one associated with the four faultx inputs. the pwma output will be turned off if there is a logic 1 on a faultx input and a 1 in the corresponding bit of the disa field. a reset sets all disa bits. 25.4.3.17 deadtime count registers (dtcnt0, dtcnt1) deadtime operation is only applicab le to complementary channel operati on. the 12-bit values written to these registers are in terms of ipbu s clock cycles regardless of the se tting of prsc and/or clk_sel. reset sets the deadtime count regist ers to a default value of 0x0fff, selecting a deadtime of 4095 ipbus clock cycles. these registers are not byte accessible. figure 25-51. deadtime count register 0 (dtcnt0) figure 25-52. deadtime count register 1 (dtcnt1) the dtcnt0 field is used to control the deadtime dur ing 0 to 1 transitions of the pwma output (assuming normal polarity). the dtcnt1 field is used to control the deadtime during 0 to 1 transitions of the complementary pwmb output. 25.4.3.18 capture control x register (captctrlx) figure 25-53. capture control x register (captctrlx) pwm_sub_ base+$24 0 123456789101112131415 read 00000 dtcnt0 write reset 000001111111 1 111 pwm_sub_ base+$26 0 123456789101112131415 read 00000 dtcnt1 write reset 000001111111 1 111 pwm_sub _base+$3 0 0 123456789101112131415 read cx1cnt cx0cnt cfxwm edg cnt x_e n inp_ sel x edgx1 edgx0 one sho tx arm x write reset 0000000000000000
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-51 pxs20 microcontroller reference manual, rev. 1 cx1cnt - capture x1 fifo word count this field reflects the number of words in the capture x1 fifo. cx0cnt - capture x0 fifo word count this field reflects the number of words in the capture x0 fifo. cfxwm - capture x fifos water mark this field represents the water ma rk level for capture x fifos. th e capture flags, cfx1 and cfx0, won?t be set until the word count of the corresponding fifo is grea ter than this water mark level. edgcntx_en - edge counter x enable this bit enables the edge counter which counts ri sing and falling edges on the pwmx input signal. 1 = edge counter enabled. 0 = edge counter disabled and held in reset. inpselx - input select x this bit selects between the raw pwmx input si gnal and the output of th e edge counter/compare circuitry as the source for the input capture circuit. 1 = output of edge counter/c ompare selected as source. 0 = raw pwmx input signal selected as source. note when inpselx = 1, the internal edge counter is enabled and the rising and/or falling edges specified by the edgx0 and edgx1 fields are ignored. the software must still place a value other than 00 in either or both of the edgx0 and/or edgx1 fields in order to enable one or both of the capture registers. edgx1 - edge x 1 these bits control the input capture 1 circuitry by determining which input e dges cause a capture event. ? 00 = disabled. ? 01 = capture falling edges. ? 10 = capture rising edges. ? 11 = capture any edge. edgx0 - edge x 0 these bits control the input capture 0 circuitry by determining which input e dges cause a capture event. ? 00 = disabled. ? 01 = capture falling edges. ? 10 = capture rising edges. ? 11 = capture any edge. oneshotx - one shot mode aux this bit selects between free running and one shot mode for the i nput capture circuitry.
flexible motor control pulse width modulator module (flexpwm) 25-52 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 1 = one shot mode is selected. if both capture circuits are enabled, then capture circuit 0 is armed first after the armx bit is set. once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. after capture circuit 1 performs a capture , it is disarmed and the armx bit is cleared. no further captures will be performed until th e armx bit is set again. if only one of the capture circui ts is enabled, then a single ca pture will occur on the enabled capture circuit and the ar mx bit is then cleared. 0 = free running mode is selected if both capture circuits are enabled, then capture circuit 0 is armed first after the armx bit is set. once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. after capture circuit 1 performs a capture , it is disarmed and capture circuit 0 is re-armed. the process continues indefinitely. if only one of the capture circuits is enabled, th en captures continue indefinitely on the enabled capture circuit. armx - arm x setting this bit high starts the input capture process. this bit can be cleared at any ti me to disable input capture operation. this bit is self cleared when in one shot mode and the enabled capture circuit(s) has had a capture event(s). 1 = input capture operation as specified by the edgx bits is enabled. 0 = input capture operation is disabled. 25.4.3.19 capture compare x register (captcmpx) figure 25-54. capture compare x register (captcmpx) edgcntx - edge counter x this read only field contains the edge counte r value for the pwmx input capture circuitry. edgcmpx - edge compare x this read/write field is the co mpare value associated with the edge counter for the pwmx input capture circuitry. pwm_sub_ base+$32 0 123456789101112131415 read edgcntx edgcmpx write reset 0000000000000000
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-53 pxs20 microcontroller reference manual, rev. 1 25.4.3.20 capture value 0 register (cval0) figure 25-55. capture value 0 register (cval0) this read only register stores the value captured from the submodule counter. exactly when this capture occurs is defined by the edgx 0 bits. this is actually a 4 deep fifo and not a single register. this register is not byte accessible. 25.4.3.21 capture value 0 cycle register (cval0cyc) figure 25-56. capture value 0 cycle register (cval0cyc) this read only register stores the cycle number corresponding to th e value captured in cval0. the pwm cycle is reset to 0 and is incremented each time the counter is loaded with the init value. this is actually a 4 deep fifo and not a single register. 25.4.3.22 capture value 1 register (cval1) figure 25-57. capture value 1 register (cval1) this read only register stores the value captured from the submodule counter. exactly when this capture occurs is defined by the edgx 1 bits. this is actually a 4 deep fifo and not a single register. this register is not byte accessible. pwm_sub_ base+$34 0 123456789101112131415 read captval0 write reset 000000000000 0 000 pwm_sub_ base+$36 0 123456789101112131415 read 000000000000 0 cval0cyc write reset 000000000000 0 000 pwm_sub_ base+$38 0 123456789101112131415 read captval1 write reset 000000000000 0 000
flexible motor control pulse width modulator module (flexpwm) 25-54 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 25.4.3.23 capture value 1 cycle register (cval1cyc) figure 25-58. capture value 1 cycle register (cval1cyc) this read only register stores the cycle number corresponding to th e value captured in cval1. the pwm cycle is reset to 0 and is incremented each time the counter is loaded with the init value. this is actually a 4 deep fifo and not a single register. 25.4.4 configuration registers the base address of the configurati on registers is equal to the base a ddress of the mcpwm plus as offset of $140. 25.4.4.1 output enable register (outen) figure 25-59. output enable register (outen) pwma_en - pwma output enables these bits enable the pwma outputs of each subm odule. these bits shoul d be set to 0 (output disabled) when a pwma pin is being used for input capture. 1 = pwma output enabled. 0 = pwma output disabled. pwmb_en - pwmb output enables these bits enable the pwmb outputs of each subm odule. these bits shoul d be set to 0 (output disabled) when a pwmb pin is being used for input capture. 1 = pwmb output enabled. 0 = pwmb output disabled. pwmx_en - pwmx output enables these bits enable the pwmx outputs of each subm odule. these bits shoul d be set to 0 (output disabled) when a pwmx pin is being used for input capture or deadtime correction. 1 = pwmx output enabled. 0 = pwmx output disabled. pwm_sub_ base+$3a 0 123456789101112131415 read 000000000000 0 cval1cyc write reset 000000000000 0 000 pwm_base +$140 0 123456789101112131415 read 0 0 0 0 pwma_en pwmb_en pwmx_en write reset 0000000000000000
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-55 pxs20 microcontroller reference manual, rev. 1 25.4.4.2 mask register (mask) figure 25-60. mask register (mask) note the maskx bits are double buffered and do not take effect until a force_out event occurs within the appropriate submodule. refer to figure 25-17 to see how force_out is ge nerated. reading the mask bits reads the buffered value and not neces sarily the value currently in effect. maska - pwma masks these bits mask the pwma outputs of each subm odule forcing the output to logic 0 prior to consideration of the output polarity. 1 = pwma output masked. 0 = pwma output normal. maskb - pwmb masks these bits mask the pwmb outputs of each subm odule forcing the output to logic 0 prior to consideration of the output polarity. 1 = pwmb output masked. 0 = pwmb output normal. maskx - pwmx masks these bits mask the pwmx outputs of each subm odule forcing the output to logic 0 prior to consideration of the output polarity. 1 = pwmx output masked. 0 = pwmx output normal. 25.4.4.3 software controlled output register (swcout) figure 25-61. software controlled output register (swcout) pwm_base +$142 0 123456789101112131415 read 0 0 0 0 maska maskb maskx write reset 0000000000000000 pwm_base +$144 0 123456789101112131415 read 00000000 out 23_3 out 45_3 out 23_2 out 45_2 out 23_1 out 45_1 out 23_0 out 45_0 write reset 0000000000000000
flexible motor control pulse width modulator module (flexpwm) 25-56 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 note these bits are double buffered and do not take effect until a force_out event occurs within the appr opriate submodule. refer to figure 25-17 to see how force_out is generated. re ading these bits reads the buffered value and not necessarily the value currently in effect. out23_3 - software controlled output 23_3 this bit is only used when sel23 for submodule 3 is set to 0b10. it allows software control of which signal is supplied to the deadti me generator of that submodule. 1 = a logic 1 is supplied to the deadtime generator of submodule 3 instead of pwm23. 0 = a logic 0 is supplied to the deadtime generator of submodule 3 instead of pwm23. out45_3 - software controlled output 45_3 this bit is only used when sel45 for submodule 3 is set to 0b10. it allows software control of which signal is supplied to the deadti me generator of that submodule. 1 = a logic 1 is supplied to the deadtime generator of submodule 3 instead of pwm45. 0 = a logic 0 is supplied to the deadtime generator of submodule 3 instead of pwm45. out23_2 - software controlled output 23_2 this bit is only used when sel23 for submodule 2 is set to 0b10. it allows software control of which signal is supplied to the deadti me generator of that submodule. 1 = a logic 1 is supplied to the deadtime generator of submodule 2 instead of pwm23. 0 = a logic 0 is supplied to the deadtime generator of submodule 2 instead of pwm23. out45_2 - software controlled output 45_2 this bit is only used when sel45 for submodule 2 is set to 0b10. it allows software control of which signal is supplied to the deadti me generator of that submodule. 1 = a logic 1 is supplied to the deadtime generator of submodule 2 instead of pwm45. 0 = a logic 0 is supplied to the deadtime generator of submodule 2 instead of pwm45. out23_1 - software controlled output 23_1 this bit is only used when sel23 for submodule 1 is set to 0b10. it allows software control of which signal is supplied to the deadti me generator of that submodule. 1 = a logic 1 is supplied to the deadtime generator of submodule 1 instead of pwm23. 0 = a logic 0 is supplied to the deadtime generator of submodule 1 instead of pwm23. out45_1 - software controlled output 45_1 this bit is only used when sel45 for submodule 1 is set to 0b10. it allows software control of which signal is supplied to the deadti me generator of that submodule. 1 = a logic 1 is supplied to the deadtime generator of submodule 1 instead of pwm45. 0 = a logic 0 is supplied to the deadtime generator of submodule 1 instead of pwm45. out23_0 - software controlled output 23_0 this bit is only used when sel23 for submodule 0 is set to 0b10. it allows software control of which signal is supplied to the deadti me generator of that submodule.
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-57 pxs20 microcontroller reference manual, rev. 1 1 = a logic 1 is supplied to the deadtime generator of submodule 0 instead of pwm23. 0 = a logic 0 is supplied to the deadtime generator of submodule 0 instead of pwm23. out45_0 - software controlled output 45_0 this bit is only used when sel45 for submodule 0 is set to 0b10. it allows software control of which signal is supplied to the deadti me generator of that submodule. 1 = a logic 1 is supplied to the deadtime generator of submodule 0 instead of pwm45. 0 = a logic 0 is supplied to the deadtime generator of submodule 0 instead of pwm45. 25.4.4.4 deadtime s ource select register (dtsrcsel) figure 25-62. deadtime source select register (dtsrcsel) note the deadtime source select bits ar e double buffered and do not take effect until a force_out event oc curs within the appropr iate submodule. refer to figure 25-17 to see how force_out is ge nerated. reading these bits reads the buffered value and not necessa rily the value currently in effect. sel23_3 - pwm23_3 control select this field selects possible over-rides to the gene rated pwm23 signal in submodule 3 that will be passed to the deadtime logic upon the occurren ce of a "force out" even t in that submodule. ? 00 = generated pwm23_3 signal is used by the deadtime logic. ? 01 = inverted generated pwm23_3 signa l is used by the deadtime logic. ? 10 = out23_3 bit is used by the deadtime logic. ? 11 = exta[3] signal is used by the deadtime logic. sel45_3 - pwm45_3 control select this field selects possible over-rides to the gene rated pwm45 signal in submodule 3 that will be passed to the deadtime logic upon the occurren ce of a "force out" even t in that submodule. ? 00 = generated pwm45_3 signal is used by the deadtime logic. ? 01 = inverted generated pwm45_3 signa l is used by the deadtime logic. ? 10 = out45_3 bit is used by the deadtime logic. ? 11 = extb[3] signal is used by the deadtime logic. sel23_2 - pwm23_2 control select this field selects possible over-rides to the gene rated pwm23 signal in submodule 2 that will be passed to the deadtime logic upon the occurren ce of a "force out" even t in that submodule. ? 00 = generated pwm23_2 signal is used by the deadtime logic. pwm_base +$146 0 123456789101112131415 read sel23_3 sel45_3 sel23_2 sel45_2 sel23_1 sel45_1 sel23_0 sel45_0 write reset 0000000000000000
flexible motor control pulse width modulator module (flexpwm) 25-58 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? 01 = inverted generated pwm23_2 signa l is used by the deadtime logic. ? 10 = out23_2 bit is used by the deadtime logic. ? 11 = exta[2] signal is used by the deadtime logic. sel45_2 - pwm45_2 control select this field selects possible over-rides to the gene rated pwm45 signal in submodule 2 that will be passed to the deadtime logic upon the occurren ce of a "force out" even t in that submodule. ? 00 = generated pwm45_2 signal is used by the deadtime logic. ? 01 = inverted generated pwm45_2 signa l is used by the deadtime logic. ? 10 = out45_2 bit is used by the deadtime logic. ? 11 = extb[2] signal is used by the deadtime logic. sel23_1 - pwm23_1 control select this field selects possible over-rides to the gene rated pwm23 signal in submodule 1 that will be passed to the deadtime logic upon the occurren ce of a "force out" even t in that submodule. ? 00 = generated pwm23_1 signal is used by the deadtime logic. ? 01 = inverted generated pwm23_1 signa l is used by the deadtime logic. ? 10 = out23_1 bit is used by the deadtime logic. ? 11 = exta[1] signal is used by the deadtime logic. sel45_1 - pwm45_1 control select this field selects possible over-rides to the gene rated pwm45 signal in submodule 1 that will be passed to the deadtime logic upon the occurren ce of a "force out" even t in that submodule. ? 00 = generated pwm45_1 signal is used by the deadtime logic. ? 01 = inverted generated pwm45_1 signa l is used by the deadtime logic. ? 10 = out45_1 bit is used by the deadtime logic. ? 11 = extb[1] signal is used by the deadtime logic. sel23_0 - pwm23_0 control select this field selects possible over-rides to the gene rated pwm23 signal in submodule 0 that will be passed to the deadtime logic upon the occurren ce of a "force out" even t in that submodule. ? 00 = generated pwm23_0 signal is used by the deadtime logic. ? 01 = inverted generated pwm23_0 signa l is used by the deadtime logic. ? 10 = out23_0 bit is used by the deadtime logic. ? 11 = exta[0] signal is used by the deadtime logic. sel45_0 - pwm45_0 control select this field selects possible over-rides to the gene rated pwm45 signal in submodule 0 that will be passed to the deadtime logic upon the occurren ce of a "force out" even t in that submodule. ? 00 = generated pwm45_0 signal is used by the deadtime logic. ? 01 = inverted generated pwm45_0 signa l is used by the deadtime logic. ? 10 = out45_0 bit is used by the deadtime logic.
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-59 pxs20 microcontroller reference manual, rev. 1 ? 11 = extb[0] signal is used by the deadtime logic. 25.4.4.5 master control register (mctrl) figure 25-63. master co ntrol register (mctrl) ipol - current polarity this buffered read/write bit is used to select between pwm23 and pwm45 as the source for the generation of the complementar y pwm pair output. ipol is ignored in independent mode. 1 = pwm45 ( figure 25-2 ) is used to generate complementary pwm pair. 0 = pwm23 ( figure 25-2 ) is used to generate complementary pwm pair. note the ipol bit does not take effect until a force_ou t event takes place in the appropriate submodule. reading th e ipol bit reads the buffered value and not necessarily the value currently in effect. run - run this read/write bit enables the clocks to the pwm generator. wh en run equals zero, the submodule counter is reset. in submodules other than 0, the local run bit is ignored when clk_sel is 1 because this indicates that the aux_clk from submod0 is being used by this submodule. a reset clears run. 1 = pwm generator enabled. 0 = pwm generator disabled. note for proper initialization of the ldok and run bits, see section 25.3.4.5, initialization . cldok - clear load okay this write only bit is used to cl ear the ldok bit. write a 1 to th is location to clear the corresponding ldok. if a reload occurs with ld ok set at the same time that cldok is written, then the reload will not be performed and ldok will be cleared. this bit is self clearing and always reads as a 0. ldok - load okay this read/set bit loads the prsc bits of ctrl1 and the init, fracx, and val x registers into a set of buffers. the buffered prescaler divisor, subm odule counter modulus value, and pwm pulse width take effect at the next pwm reload if ldmod is clear or imme diately if ldmod is set. set ldok by reading it when it is logic zero and then writ ing a logic one to it. the valx, fracx, init, and prsc registers cannot be written while ldok is set. ldok is au tomatically cleared after the new pwm_base +$148 0 123456789101112131415 read ipol run 0000 ldok write cldok reset 0000000000000000
flexible motor control pulse width modulator module (flexpwm) 25-60 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 values are loaded, or can be manually cleared before a reload by writing a logic 1 to cldok. this bit cannot be written with a zero. ld ok can be set in dma mode when the dma indicates that it has completed the update of all prsc, init, valx, and fracx registers. reset clears ldok. 1 = load prescaler, modulus, and pwm values. 0 = do not load new values. note for proper initialization of the ldok and run bits, see section 25.3.4.5, initialization . 25.4.5 fault channel registers the base address of the fault logic is equal to the base address of the mcpwm plus an offset of $14c. 25.4.5.1 fault control register (fctrl) figure 25-64. fault control register (fctrl) flvl - fault level these read/write bits sel ect the active logic level of the indi vidual fault inputs. a reset clears flvl. 1 = a logic 1 on the fault input indicates a fault condition. 0 = a logic 0 on the fault input indicates a fault condition. fauto - automatic fault clearing these read/write bits select automatic or ma nual clearing of faults . a reset clears fauto. 1 = automatic fault clearing. pwm outputs disabled by this fault are enabled when the ffpinx bit is clear at the start of a half cycle or full cycle depending on the state of the ffull bits without regard to the state of fflagx bit. 0 = manual fault clearing. pwm outputs disabled by this fault are not enabled until the fflagx bit is clear at the start of a ha lf cycle or full cycle depending th e state of the ff ull bits. this is further controlled by the fsafe bits. fsafe - fault safety mode these read/write b its select the safety mode during manua l fault clearing. a reset clears fsafe. 1 = safe mode. pwm outputs disabled by this faul t are not enabled until th e fflagx bit is clear and the ffpinx bit is clear at the start of a half cycle or full cycle depending on the state of the ffull bits. pwm_base +$14c 0 123456789101112131415 read flvl fauto fsafe fie write reset 0000000000000000
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-61 pxs20 microcontroller reference manual, rev. 1 0 = normal mode. pwm outputs di sabled by this fault ar e not enabled until the fflagx bit is clear at the start of a half cycle or full cycle dependi ng on the state of the ff ull bits without regard to the state of the ffpinx bit. the pwm output s disabled by this fault input will not be re-enabled until the actual faultx input signal de-asserts since the fault input will combinationally disable the pwm outputs (as programmed in dismap). note the ffpinx bit may indicate a fault c ondition still exists even though the actual fault signal at the faultx pin is clear due to the fault filter latency. fie - fault interrupt enables this read/write bit enables cpu interrupt request s generated by the faultx pins. a reset clears fie. 1 = faultx cpu interrupt requests enabled. 0 = faultx cpu interrupt requests disabled. note the fault protection circuit is independ ent of the fiex bit and is always active. if a fault is detected, the pwm outputs are disabled according to the disable mapping register. 25.4.5.2 fault status register (fsts) figure 25-65. fault status register (fsts) ftest - fault test these read/write bit is used to simulate a fault condi tion. setting this bit will cause a simulated fault to be sent into all of the fault filters. the condi tion will propagate to the fault flag s and possibly the pwm outputs depending on the dismap settings. cl earing this bit removes the simulated fault condition. 1 = cause a simulated fault. 0 = no fault. ffpin - filtered fault pins these read-only bits reflect the current state of the filtered fa ultx pins converted to high polarity. a logic 1 indicates a fau lt condition exists on the fi ltered faultx pin. a rese t has no effect on ffpin. ffull - full cycle these read/write bits are used to control the ti ming for re-enabling the pw m outputs after a fault condition. these bits apply to both automati c and manual clearing of a fault condition. 1 = pwm outputs are re-enabled only at the start of a full cycle. 0 = pwm outputs are re-enabled at th e start of a full or half cycle. pwm_base +$14e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 read 0 0 0 ftest ffpin ffull fflag write reset 000 0 111100001111
flexible motor control pulse width modulator module (flexpwm) 25-62 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 fflag - fault flags these read-only flag is set within two cpu cycles after a transition to active on the faultx pin. clear fflagx by writing a logic one to it. a reset clears fflag. 1 = fault on the faultx pin. 0 = no fault on the faultx pin. 25.4.5.3 fault filter register (ffilt) figure 25-66. fault filter register (ffilt) the settings in this register are shar ed among each of the fault input filters. gstr - fault glitch stretch enable this bit is used to enable the faul t glitch stretching logic. this logi c ensures that narr ow fault glitches are stretched to be at least 2 ipbus clock cycles wi de. in some cases a narr ow fault input can cause problems due to the short pwm output shutdown/re-activation time. th e stretching logic ensures that a glitch on the fault input, when th e fault filter is disabled, will be registered in the fault flags. 1 = input fault signals will be stretc hed to at least 2 ipbus clock cycles. 0 = fault input glitch stretching is disabled. filt_cnt - fault filter count these bits represent the number of consecutive sa mples that must agree prior to the input filter accepting an input transition. a value of 0 represents 3 samples. a value of 7 represents 10 samples. the value of filt_cnt affects the input latency as described in section 25.4.5.3.1, input filter considerations . filt_per - fault filter period these bits represent the sampling peri od (in ipbus clock cycles) of the fa ult pin input filte r. each input is sampled multiple times at the rate specified by filt_per. if fi lt_per is 0x00 (default), then the input filter is bypassed. the value of filt_p er affects the input latency as described in section 25.4.5.3.1, input filter considerations . 25.4.5.3.1 input fi lter considerations the filt_per value should be set such that the sampli ng period is larger than the period of the expected noise. this way a noise spike will only corrupt one sample. the filt_cnt value should be chosen to reduce the probability of noisy sample s causing an incorrect transition to be recognized. the probability of an incorrect transition is define d as the probability of an incorrec t sample raised to the filt_cnt+3 power. pwm_base +$150 0 123456789101112131415 read gst r 0000 filt_cnt filt_per write reset 0000000000000000
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-63 pxs20 microcontroller reference manual, rev. 1 the values of filt_per and filt_cnt must also be traded off against the desire for minimal latency in recognizing input transitions. turn ing on the input filter (setting filt_per to a non-zero value) introduces a latency of ((fi lt_cnt+4) x filt_per x ipbus clock period) . note that even when the filter is enabled, there is a combin ational path to disable the pwm outputs. this is to ensure rapid response to fault conditions and also to ensure fault response if the pwm module loses its cloc k. the latency induced by the filter will be seen in the time to se t the fflag and ffpin bits of the fsts register. 25.5 interrupts each of the submodules within the flexpwm can genera te an interrupt from seve ral sources. the fault logic can also generate interrupts. the interrupt se rvice routine (isr) must ch eck the related interrupt enables and interrupt flags to determ ine the actual cause of the interrupt. table 25-6. interrupt summary core interrupt interrupt flag interrupt enable name description cof0 cmpf_0 cmpie_0 submodule 0 compare interrupt compare event has occurred caf0 cfx1_0, cfx0_0 cfx1ie_0, cfx0ie_0 submodule 0 input capture interrupt input capture event has occurred rf0 rf_0 rie_0 submodule 0 reload interrupt reload event has occurred cof1 cmpf_1 cmpie_1 submodule 1 compare interrupt compare event has occurred caf1 cfx1_1, cfx0_1 cfx1ie_1, cfx0ie_1 submodule 1 input capture interrupt input capture event has occurred rf1 rf_1 rie_1 submodule 1 reload interrupt reload event has occurred cof2 cmpf_2 cmpie_2 submodule 2 compare interrupt compare event has occurred caf2 cfx1_2, cfx0_2 cfx1ie_2, cfx0ie_2 submodule 2 input capture interrupt input capture event has occurred rf2 rf_2 rie_2 submodule 2 reload interrupt reload event has occurred cof3 cmpf_3 cmpie_3 submodule 3 compare interrupt compare event has occurred caf3 cfx1_3, cfx0_3 cfx1ie_3, cfx0ie_3 submodule 3 input capture interrupt input capture event has occurred rf3 rf_3 rie_3 submodule 3 reload interrupt reload event has occurred
flexible motor control pulse width modulator module (flexpwm) 25-64 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 25.6 dma each submodule can request a dma read access for it s capture fifos and a dma write request for its double buffered valx registers. ref ref_0 reie_0 submodule 0 reload error interrupt reload error has occurred ref_1 reie_1 submodule 1 reload error interrupt ref_2 reie_2 submodule 2 reload error interrupt ref_3 reie_3 submodule 3 reload error interrupt fflag fflag fie fault input interrupt fault condition has been detected table 25-7. dma summary dma request dma enable name description submodule 0 read request cx0de_0 capture fifo x0 read request cval0 contains a value to be read cx1de_0 capture fifo x! read request cval1 contains a value to be read captde_0 capture fifo read request source select selects source of read dma request submodule 0 write request valde_0 valx write request valx registers need to be updated submodule 1 read request cx0de_1 capture fifo x0 read request cval0 contains a value to be read cx1de_1 capture fifo x! read request cval1 contains a value to be read captde_1 capture fifo read request source select selects source of read dma request submodule 1 write request valde_1 valx write request valx registers need to be updated submodule 2 read request cx0de_2 capture fifo x0 read request cval0 contains a value to be read cx1de_2 capture fifo x! read request cval1 contains a value to be read captde_2 capture fifo read request source select selects source of read dma request table 25-6. interrupt summary (continued) core interrupt interrupt flag interrupt enable name description
flexible motor control pulse width modulator module (flexpwm) freescale semiconductor 25-65 pxs20 microcontroller reference manual, rev. 1 submodule 2 write request valde_2 valx write request valx registers need to be updated submodule 3 read request cx0de_3 capture fifo x0 read request cval0 contains a value to be read cx1de_3 capture fifo x! read request cval1 contains a value to be read captde_3 capture fifo read request source select selects source of read dma request submodule 3 write request valde_3 valx write request valx registers need to be updated table 25-7. dma summary (continued) dma request dma enable name description
flexible motor control pulse width modulator module (flexpwm) 25-66 freescale semiconductor pxs20 microcontroller reference manual, rev. 1
flexray communication controller freescale semiconductor 26-1 pxs20 microcontroller reference manual, rev. 1 chapter 26 flexray communication controller 26.1 introduction 26.1.1 reference the following documents are referenced. ? flexray communications system prot ocol specification, version 2.1 rev a 1 ? flexray communications system electrical physical layer specification, version 2.1 rev a 26.1.2 glossary this section provides a list of terms used in this chapter. 1. the flexray specifications have been developed for automoti ve applications.the flexray specifications have been neither developed nor tested for no n-automotive applications. table 26-1. list of terms term definition bcu buffer control unit. handles message buffer access. bmif bus master interface. provides master access to flexray memory area. cc flexray communication controller, module described in this chapter. cdc clock domain crosser chi controller host interface cycle length in ? t the actual length of a cycle in ? t for the ideal cc (+/- 0 ppm) ebi external bus interface flexray memory area memory area to store the physical message buffer payload data, frame header, frame and slot status, and synchronization frame related tables. system memory memory that cont ains the flexray memory area. system bus bus that connects the cc and system memory fss frame start sequence hif host interface. provides host access to the cc. host the flexray cc host cpu. lut look up table. stores message buffer header index value. mb message buffer mbidx message buffer index: the position of a header field entry within the header area. if the header area is accessed as an array, this is the same as the array index of the entry. mbnum message buffer number: position of message buffer configuration registers within the register map. for example, message buffer number 5 corresponds to the mbccs5 register. mcu microcontroller unit ? t microtick mt macrotick
flexray communication controller 26-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.1.3 color coding throughout this chapter types of items are highlight ed through the use of an italicized color font. flexray protocol parameters, constant s and variables are highlighted with blue italics . an example is the parameter gdactionpointoffset . flexray protocol states are highlighted in green italics . an example is the state poc:normal active . 26.1.4 overview the cc is a flexray communication controller that implements the flexray communications system protocol specification, version 2.1 rev a. the cc has three main components: ? controller host interface (chi) ? protocol engine (pe) ? clock domain crossing unit (cdc) a block diagram of the cc with its surrounding modules is given in figure 26-1 . mts media access test symbol nit network idle time pe protocol engine poc protocol operation control. ea ch state of the poc is denoted by poc:state rx reception seq sequencer engine tcu time control unit tx transmission sync frame null frame or message frame with sync frame indicator set to 1 startup frame null frame or message frame with both sync frame indicator and startup frame indicator set to 1 normal frame null frame or message frame with both sync frame indicator and startup frame indicator set to 0 null frame frame with null frame indicator set to 0 message frame frame with null frame indicator set to 1 table 26-1. list of terms (continued) term definition
flexray communication controller freescale semiconductor 26-3 pxs20 microcontroller reference manual, rev. 1 figure 26-1. flexray block diagram the protocol engine has two tran smitter units txa and txb and two receiver units rxa and rxb for sending and receiving frames thr ough the two flexray channels. the time control unit (tcu) is responsible for maintaini ng global clock synchronization to the fl exray network. the overall activity of the pe is controlled by the sequencer engine (seq). the cc host interface provides host a ccess to the module?s conf iguration, control, and status registers, as well as to the message buffer confi guration, control, and status register s. the message buffers themselves, which contain the frame header and payload data rece ived or to be transmitted, and the slot status information, are stored in the flexray memory area. the clock domain crossing unit implements signal crossing from th e chi clock domain to the pe clock domain and vice versa, to allow for asynchronous pe and chi clock domains. the cc stores the frame header and payload data of frames received or of frames to be transmitted in the flexray memory area. the applicat ion accesses the flexray memory area to retrieve and provide the frames to be processed by the cc. in addition to th e frame header and payload data, the cc stores the synchronization frame related tables in the fl exray memory area for application processing. the flexray memory area is located in the system memory of the mcu. the cc has access to the flexray memory area via its bus master in terface (bmif). the host provides the start address of the flexray memory area within the system memory by programming the system memory base address register (fr_symbadr) . all flexray memory area related offsets are stored in offset registers. the physical address pointer into the flexray me mory area of the mcu system memory is calculated using the offset values the flexray memory area base address. flexray interacts with the ctu as described in section 13.4.1, interaction with other peripherals. clock domain crossing pe txa rxa tcu config seq chi hif search lut bcu ca_rx cb_rx dbg0 ca_tx ca_tr_e cb_tx cb_tr_e dbg1 dbg2 dbg3 flexray peripheral bridge b system memory bmif system bus
flexray communication controller 26-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 note the cc does not provide a memory protection scheme for the flexraymemoryarea. 26.1.5 features the cc provides the following features: ? flexray communications system prot ocol specification, version 2.1 rev a compliant protocol implementation ? flexray communications system electrical physical layer specification, version 2.1 rev a compliant bus driver interface ? single channel support ? flexray port a can be configured to be conne cted either to physical flexray channel a or physical flexray channel b. ? flexray bus data rates of 10 mbit/s, 8 mbit/s, 5 mbit/s, and 2.5 mbit/s supported ? 64 configurable message buffers with ? individual frame id filtering ? individual channel id filtering ? individual cycle counter filtering ? message buffer header, status and payload da ta stored in dedicated flexray memory area ? allows for flexible and efficient message buffer implementation ? consistent data access ensured by means of buffer locking scheme ? application can lock multiple buffers at the same time ? size of message buffer payload data se ction configurable from 0 up to 254 bytes ? two independent message buffer segments with configurable size of payload data section ? each segment can contain message buffers assigned to the stat ic segment and message buffers assigned to the dynamic segment at the same time ? zero padding for transmit messa ge buffers in static segment ? applied when the frame payloa d length exceeds the size of th e message buffer data section ? transmit message buffers configurable with state/event semantics ? message buffers can be configured as ? receive message buffer ? single buffered transmit message buffer ? double buffered transmit message buffer (com bines two single buffered message buffer) ? individual message buffer r econfiguration supported ? means provided to safely disa ble individual message buffers ? disabled message buffers can be reconfigured ? two independent receive fifos ? one receive fifo per channel
flexray communication controller freescale semiconductor 26-5 pxs20 microcontroller reference manual, rev. 1 ? up to 255 entries for each fifo ? global frame id filtering, based on both value/mask filter s and range filters ? global channel id filtering ? global message id filtering for the dynamic segment ? 4 configurable slot error counters ? 4 dedicated slot status indicators ? used to observe slots without using receive message buffers ? measured value indicators for the clock synchronization ? internal synchronizatio n frame id and synchronization fr ame measurement tables can be copied into the flexray memory area ? fractional macroticks are supported for clock correction ? maskable interrupt sources provided via individual and combined interrupt lines ? 1 absolute timer ? 1 timer that can be configured to absolute or relative ? secded for protocol engine data ram ? sedded for chi lookup table ram 26.1.6 modes of operation this section describes the basic operational power modes of the cc. 26.1.6.1 disabled mode the cc enters the disabled mode during hard reset. th e cc indicates that it is in the disabled mode by negating the module enable bit men in the module configuration register (fr_mcr) . in the disabled mode no communicati on is performed on the flexray bus. all registers with the write access conditions any time and disabled mode can be accessed for writing as stated in section 26.5.2, register descriptions . the application configures the cc by accessing the configuration bits and fields in the module configuration register (fr_mcr) . 26.1.6.1.1 leave disabled mode the cc leaves the disabled mode and enters the no rmal mode, when the application writes 1 to the module enable bit men in the module configuration register (fr_mcr) note once the cc is enabled it can only be disabled via a device reset.
flexray communication controller 26-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.1.6.2 normal mode in this mode the cc is fully functional. the cc indica tes that it is in normal mode by asserting the module enable bit men in the module configuration register (fr_mcr) . 26.1.6.2.1 enter normal mode this mode is entered when the application requests the cc to leave the disabled mode . if the normal mode was entered by leaving the disabled mode, the a pplication has to perform th e protocol initialization described in 26.7.1.2, protocol initialization , to achieve full flexray functionality. depending on the values of the sc m, cha, and chb bits in the module configurat ion register (fr_mcr) , the corresponding flexray bus driver ports are enabled and driven. 26.2 external signal description this section lists and describes th e cc signals, connected to external pins. these signals are summarized in table 26-2 and described in detail in section 26.2.1, detailed signal descriptions . note the off chip signals ca_rx, ca_tx, and ca_tr_en are available on each package option. the availability of the other off chip signals depends on the package option. table 26-2. external signal properties name direction active reset function ca_rx input ? ? receive data channel a ca_tx output ? 1 transmit data channel a ca_tr_en output low 1 transmit enable channel a cb_rx input ? ? receive data channel b cb_tx output ? 1 transmit data channel b cb_tr_en output low 1 transmit enable channel b dbg0 output ? 0 debug strobe signal 0 dbg1 output ? 0 debug strobe signal 1 dbg2 output ? 0 debug strobe signal 2 dbg3 output ? 0 debug strobe signal 3
flexray communication controller freescale semiconductor 26-7 pxs20 microcontroller reference manual, rev. 1 26.2.1 detailed signal descriptions this section provides a detailed description of the cc signals, connected to external pins. 26.2.1.1 ca_rx ? recei ve data channel a the ca_rx signal carries the receive data for ch annel a from the corresponding flexray bus driver. 26.2.1.2 ca_tx ? transmit data channel a the ca_tx signal carries the transmit data for channel a to the corresponding flexray bus driver. 26.2.1.3 ca_tr_en ? transmit enable channel a the ca_tr_en signal indicates to the flexray bus driver th at the cc is attempting to transmit data on channel a. 26.2.1.4 cb_rx ? recei ve data channel b the cb_rx signal carries the receive data for ch annel b from the corresponding flexray bus driver. 26.2.1.5 cb_tx ? transmit data channel b the cb_tx signal carries the transmit data for channel b to the corresponding flexray bus driver 26.2.1.6 cb_tr_en ? transmit enable channel b the cb_tr_en signal indicates to the flexray bus driver th at the cc is attempting to transmit data on channel b. 26.2.1.7 dbg3, dbg2, dbg1 , dbg0 ? strobe signals these signals provide the selected debug strobe signals. for details on the debug strobe signal selection refer to section 26.6.16, strobe signal support . 26.3 controller host interface clocking the clock for the chi is derived fro m the system bus clock and has the same phase and frequency as the system bus clock. since the flexray protocol requires data delivery at fixed points in time, the memory read cycles from the flexra y memory area must be fi nished after a fixed amount of time. to ensure this, a minimum frequency f chi of the chi clock is required, which is given in equation 26-1 . eqn. 26-1 additional requirements for the mini mum frequency of the chi clock re sult from the number of message buffers. these requirements are provided in section 26.7.5, number of us able message buffers f chi 32 mhz ?
flexray communication controller 26-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.4 protocol engine clocking the clock for the protocol engine can be generated by two sources. the first source is the internal crystal oscillator and the second sour ce is an internal fmpll. the clock sour ce to be used is selected by the clock source select bit clksel in the module configuration register (fr_mcr) . if the protocol engine is clocked by the internal crystal oscillator , an 40 mhz crystal or cmos compatible clock must be connected to the osci llator pins. the crystal or clock mu st fulfill the requirements given by the flexray communications system prot ocol specification, version 2.1 rev a. 26.5 memory map and register description the cc occupies 768 bytes of address space starting atthe base address of the cc is defined by the memory map of the mcu. 26.5.1 memory map the complete memory map of the cc is shown in table 26-3 . the addresses presented here are the offsets relative to the cc base address whic h is defined by the mcu address map. table 26-3. flexray memory map offset register access module configuration and control 0x0000 module version register (fr_mvr) r 0x0002 module configuration register (fr_mcr) r/w 0x0004 system memory base address high register (fr_symbadhr) r/w 0x0006 system memory base address low register (fr_symbadlr) r/w 0x0008 strobe signal control register (fr_stbscr) r/w 0x000a reserved r 0x000c message buffer data size register (fr_mbdsr) r/w 0x000e message buffer segment size and utilization register (fr_mbssutr) r/w pe access registers 0x0010 pe dram access register (fr_pedrar) r/w 0x0012 pe dram data register (fr_pedrdr) r/w interrupt and error handling 0x0014 protocol operation control register (fr_pocr) r/w 0x0016 global interrupt flag and enable register (fr_gifer) r/w 0x0018 protocol interrupt flag register 0 (fr_pifr0) r/w 0x001a protocol interrupt flag register 1 (fr_pifr1) r/w 0x001c protocol interrupt enable register 0 (fr_pier0) r/w 0x001e protocol interrupt enable register 1 (fr_pier1) r/w 0x0020 chi error flag register (fr_chierfr) r/w 0x0022 message buffer interrupt ve ctor register (fr_mbivec) r 0x0024 channel a status error counter register (fr_casercr) r 0x0026 channel b status error counter register (fr_cbsercr) r
flexray communication controller freescale semiconductor 26-9 pxs20 microcontroller reference manual, rev. 1 protocol status 0x0028 protocol status register 0 (fr_psr0) r 0x002a protocol status register 1 (fr_psr1) r 0x002c protocol status register 2 (fr_psr2) r 0x002e protocol status register 3 (fr_psr3) r/w 0x0030 macrotick counter register (fr_mtctr) r 0x0032 cycle counter register (fr_cyctr) r 0x0034 slot counter channel a register (fr_sltctar) r 0x0036 slot counter channel b register (fr_sltctbr) r 0x0038 rate correction value register (fr_rtcorvr) r 0x003a offset correction value register (fr_ofcorvr) r 0x003c combined interrupt flag register (fr_cifr) r 0x003e system memory access time-o ut register (fr_symator) r/w sync frame counter and tables 0x0040 sync frame counter register (fr_sfcntr) r 0x0042 sync frame table offset register (fr_sftor) r/w 0x0044 sync frame table configuration, cont rol, status register (fr_sftccsr) r/w sync frame filter 0x0046 sync frame id rejection f ilter register (fr_sfidrfr) r/w 0x0048 sync frame id accept ance filter value re gister (fr_sfidafvr) r/w 0x004a sync frame id acceptance filter mask register (fr_sfidafmr) r/w network management vector 0x004c network management vector register 0 (fr_nmvr0) r 0x004e network management vector register 1 (fr_nmvr1) r 0x0050 network management vector register 2 (fr_nmvr2) r 0x0052 network management vector register 3 (fr_nmvr3) r 0x0054 network management vector register 4 (fr_nmvr4) r 0x0056 network management vector register 5 (fr_nmvr5) r 0x0058 network management vector length register (fr_nmvlr) r/w timer configuration 0x005a timer configuration and control register (fr_ticcr) r/w 0x005c timer 1 cycle set register (fr_ti1cysr) r/w 0x005e timer 1 macrotick offset register (fr_ti1mtor) r/w 0x0060 timer 2 configuration register 0 (fr_ti2cr0) r/w 0x0062 timer 2 configuration register 1 (fr_ti2cr1) r/w slot status configuration 0x0064 slot status selecti on register (fr_sssr) r/w 0x0066 slot status counter cond ition register (fr_ssccr) r/w slot status 0x0068 slot status register 0 (fr_ssr0) r table 26-3. flexray memory map (continued) offset register access
flexray communication controller 26-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 0x006a slot status register 1 (fr_ssr1) r 0x006c slot status register 2 (fr_ssr2) r 0x006e slot status register 3 (fr_ssr3) r 0x0070 slot status register 4 (fr_ssr4) r 0x0072 slot status register 5 (fr_ssr5) r 0x0074 slot status register 6 (fr_ssr6) r 0x0076 slot status register 7 (fr_ssr7) r 0x0078 slot status counter register 0 (fr_sscr0) r 0x007a slot status counter register 1 (fr_sscr1) r 0x007c slot status counter register 2 (fr_sscr2) r 0x007e slot status counter register 3 (fr_sscr3) r mts generation 0x0080 mts a configuration register (fr_mtsacfr) r/w 0x0082 mts b configuration register (mtsbcfr) r/w shadow buffer configuration 0x0084 receive shadow buffer index register (fr_rsbir) r/w receive fifo ? configuration 0x0086 receive fifo watermark and se lection register (fr_rfwmsr) r/w 0x0088 receive fifo start index register (fr_rfsir) r/w 0x008a receive fifo depth and size register (rfdsr) r/w receive fifo - control 0x008c receive fifo a read index register (fr_rfarir) r 0x008e receive fifo b read index register (fr_rfbrir) r receive fifo - filter 0x0090 receive fifo message id acceptance f ilter value register (fr_rfmidafvr) r/w 0x0092 receive fifo message id acceptance f ilter mask register (fr_rfmidafmr) r/w 0x0094 receive fifo frame id rejection fi lter value register (fr_rffidrfvr) r/w 0x0096 receive fifo frame id rejection filter mask register (fr_rffidrfmr) r/w 0x0098 receive fifo range filter conf iguration register (fr_rfrfcfr) r/w 0x009a receive fifo range filter c ontrol register (fr_rfrfctr) r/w dynamic segment status 0x009c last dynamic transmit slot channel a register (fr_ldtxslar) r 0x009e last dynamic transmit slot channel b register (fr_ldtxslbr) r protocol configuration 0x00a0 ... 0x00dc protocol configuration register 0 (fr_pcr0) ... protocol configuration register 30 (fr_pcr30) r/w ? r/w 0x00de ... 0x00e6 reserved r receive fifo ? configuration (cont.) table 26-3. flexray memory map (continued) offset register access
flexray communication controller freescale semiconductor 26-11 pxs20 microcontroller reference manual, rev. 1 26.5.2 register descriptions this section provides detailed descriptions of all re gisters in ascending address order, presented as 16-bit wide entities table 26-4 provides a key for the register figures and register tables. 0x00e8 receive fifo system memory base address high register (fr_rfsymbadhr) r/w 0x00ea receive fifo system memory base address low register (fr_rfsymbadlr) r/w 0x00ec receive fifo periodic timer register (fr_rfptr) r/w receive fifo - control (cont.) 0x00ee receive fifo fill level and pop count register (fr_rfflpcr) r/w ecc registers 0x00f0 ecc error interrupt flag and enable register (fr_eeifer) r/w 0x00f2 ecc error report and injection control register (fr_eericr) r/w 0x00f4 ecc error report address register (fr_eerar) r 0x00f6 ecc error report data register (fr_eerdr) r 0x00f8 ecc error report code register (fr_eercr) r 0x00fa ecc error injection address register (fr_eeiar) r/w 0x00fc ecc error injection data register (fr_eeidr) r/w 0x00fe ecc error injection code register (fr_eeicr) r/w message buffers configuration, control, status 0x0100 message buffer configuration, cont rol, status register 0 (fr_mbccsr0) r/w 0x0102 message buffer cycle counter filter register 0 (fr_mbccfr0) r/w 0x0104 message buffer frame id register 0 (fr_mbfidr0) r/w 0x0106 message buffer index register 0 (fr_mbidxr0) r/w ... ... ... 0x02f8 message buffer configuration, cont rol, status register 63 (fr_mbccsr63) r/w 0x02fa message buffer cycle counter filter register 63 (fr_mbccfr63) r/w 0x02fc message buffer frame id register 63 (fr_mbfidr63) r/w 0x02fe message buffer index register 63 (fr_mbidxr63) r/w table 26-4. register access conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writeable. r* reserved bit or field, will not be changed. applic ation must not write any value different from the reset value. fieldname identifies the field. its pres ence in the read or write row indicates that it can be read or written. register field types rwm a read/write bit that may be modified by a hardware in some fashion other than by a reset. table 26-3. flexray memory map (continued) offset register access
flexray communication controller 26-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.5.2.1 register reset all registers except the message buffer cycle counter filter registers (fr_mbccfrn) , message buffer frame id registers (fr_mbfidrn) , and message buffer index registers (fr_mbidxrn) are reset to their reset value on system reset. the registers me ntioned above are located in physical memory blocks and, thus, they are not affected by reset. for some re gister fields, additional reset conditions exist. these additional reset conditions are mentioned in the detaile d description of the register. the additional reset conditions are explained in table 26-5 . 26.5.2.2 registe r write access this section describes the write access restri ction terms that apply to all registers. 26.5.2.2.1 register wr ite access restriction for each register bit and register fi eld, the write access conditions are sp ecified in the detailed register description. a description of the wr ite access conditions is given in table 26-6 . if, for a specific register bit or field, none of the given write access conditions is fulfilled, any writ e attempt to this register bit or field is ignored without a ny notification. the values of the bits or fields are not changed. the condition term [a or b] indicates that the re gister or field can be written to if at least one of the conditions is fulfilled.the condition term [a and b] indicates that the register or field can be wr itten to if both conditions are fulfilled. w1c write one to clear. a flag bit that can be read, is cleared by writing a one, writing 0 has no effect. reset value 0 resets to zero. 1 resets to one. ? not defined after reset and not affected by reset. table 26-5. additional re gister reset conditions condition description protocol run command the register field is reset when the application writes to run command ?0101? to the poccmd field in the protocol operation control register (fr_pocr) . message buffer disable the register field is reset when the application has disabled the message buffer. this happens when the application writes 1 to the message buffer disable trigger bit fr_mbccsrn[edt] while the message buffer is enabled (fr_mbccsrn[eds] = 1) and the cc grants the disable to the application by clearing the fr_mbccsrn[eds] bit. table 26-6. register write access restrictions condition indication description any time ? no write access restriction. disabled mode fr_mcr[men] = 0 write access only when cc is in disabled mode. table 26-4. register access conventions convention description
flexray communication controller freescale semiconductor 26-13 pxs20 microcontroller reference manual, rev. 1 26.5.2.2.2 register write access requirements all registers can be accessed with 8-bit, 16-bit and 32- bit wide operations. for some of the registers, at least a 16-bit wide write access is required to ensure correct operation. this write access requirement is stated in the detailed register de scription for each register affected 26.5.2.2.3 internal register access the following memory mapped registers are us ed to access multiple internal registers. ? strobe signal control register (fr_stbscr) ? slot status selection register (fr_sssr) ? slot status counter condition register (fr_ssccr) ? receive shadow buffer index register (fr_rsbir) each of these memory mapped registers provides a se l field and a wmd bit. the sel field is used to select the internal register. the wmd bit controls th e write mode. if the wmd bit is set to 0 during the write access, all fields of the inte rnal register are updated. if the wmd bit set to 1, only the sel field is changed. all other fields of the inte rnal register remain unc hanged. this allows for r eading back the values of the selected internal regist er in a subsequent read access. 26.5.2.3 module version register (fr_mvr) this register provides the cc vers ion number. the module version numbe r is derived from the chi version number and the pe version number. normal mode fr_mcr[men] = 1 write access only when cc is in normal mode. poc:config fr_psr0[protstate] = poc:config write access only when protocol is in the poc:config state. mb_dis fr_mbccsr[eds] = 0 write access on ly when related message buffer is disabled. mb_lck fr_mbccsrn[lcks] = 1 write access only when related message buffer is locked. idl fr_eeiricr[bsy] = 0 write access only when ecc config uration is idle base + 0x0000 0123456789101112131415 r chiver pever w reset10100010 01101000 figure 26-2. module vers ion register (fr_mvr) table 26-6. register write access restrictions (continued) condition indication description
flexray communication controller 26-14 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.5.2.4 module configurat ion register (fr_mcr) this register defines the gl obal configuration of the cc. table 26-7. fr_mvr field descriptions field description chiver chi version number ? this field provides the ve rsion number of the cc host interface. pever pe version number ? this field provides the versio n number of the protocol engine. base + 0x0002 write: men, sbff, scm, chb, cha , ecce, fum, fam, clksel , bitrate: disabled mode sffe: disabled mode or poc:config 0123456789101112131415 r men sbff scm chb cha sffe ecce r* fum fam 0 clk sel bitrate 0 w reset0000000000000000 figure 26-3. module configuration register (fr_mcr) table 26-8. fr_mcr field descriptions field description men module enable ? this bit indicates whether or not the cc is in the disabled mode. the application requests the cc to leave the disabled mode by writing 1 to this bit before leaving the disabled mode, the application must configur e the scm, sbff, chb, cha, tmode, bitrate values. for details see section 26.1.6, modes of operation . 0 write: ignored, cc disable not possible read: cc disabled 1 write: enable cc read: cc enabled note: if the cc is enabled it can not be disabled. sbff system bus failure freeze ? this bit controls the behavior of the cc in case of a system bus failure. 0 continue normal operation 1 transition to freeze mode scm single channel device mode ? this control bit defines the channel device mode of the cc as described in section 26.6.10, channel device modes . 0 cc works in dual channel device mode 1 cc works in single channel device mode chb cha channel enable ? protocol related parameter: pchannels the semantic of these control bits depends on the channel device mode controlled by the scm bit and is given table 26-9 . sffe synchronization frame filter enable ? this bit controls the filtering for received synchronization frames. for details see section 26.6.15, sync frame filtering . 0 synchronization frame filtering disabled 1 synchronization frame filtering enabled
flexray communication controller freescale semiconductor 26-15 pxs20 microcontroller reference manual, rev. 1 ecce ecc functionality enable ? this bit controls the ecc memory error detection functionality. for details see section 26.6.24, memory content error detection . 0 ecc functionality (injection, detect ion, reporting, response) disabled 1 ecc functionality enabled fum fifo update mode ? this bit controls the fifo update behavior when the interrupt flags fr_gifer[fafaif] and fr_gifer[fafbif] are written by the application (see section 26.6.9.8, fifo update ) 0 fifoa/fifob is updated on writing 1 to fr_gifer[fafaif] /fr_gifer[fafbif] 1 fifoa/fifob) is not updated on writing 1 to fr_gif er[fafaif]/fr_gifer[fafbif] fam fifo address mode ? this bit controls the location of the system memo ry base address for the fifos. (see section 26.6.9.2, fi fo configuration ) 0 fifo base address located in system memory base addr ess register (fr_symbadr) 1 fifo base address located in receive fifo system memory base address register (fr_rfsymbadr) clksel protocol engine clock source select ? this bit is used to select the clock source for the protocol engine. 0 pe clock source is generated by on-chip crystal oscillator. 1 pe clock source is generated by on-chip fmpll. bitrate flexray bus bit rate ? this bit field defines the flexray bus bit rate. 000 10.0 mbit/sec 001 5.0 mbit/sec 010 2.5 mbit/sec 011 8.0 mbit/sec 100 reserved 101 reserved 110 reserved 111 reserved table 26-9. flexray channel selection scm chb cha description dual channel device modes 0 0 0 ports ca_rx, ca_tx, and ca_tr_en not driven by cc ports cb_rx, cb_tx, and ca_tr_en not driven by cc 0 1 ports ca_rx, ca_tx, and ca_tr_en driven by cc - connected to flexray channel a ports cb_rx, cb_tx, and ca_tr_en not driven by cc 1 0 ports ca_rx, ca_tx, and ca_tr_en not driven by cc ports cb_rx, cb_tx, and ca_tr_en driven by cc - connected to flexray channel b 1 1 ports ca_rx, ca_tx, and ca_tr_en driven by cc - connected to flexray channel a ports cb_rx, cb_tx, and ca_tr_en driven by cc - connected to flexray channel b single channel device mode 1 0 0 ports ca_rx, ca_tx, and ca_tr_en not driven by cc ports cb_rx, cb_tx, and ca_tr_en not driven by cc 0 1 ports ca_rx, ca_tx, and ca_tr_en driven by cc - connected to flexray channel a ports cb_rx, cb_tx, and ca_tr_en not driven by cc 1 0 ports ca_rx, ca_tx, and ca_tr_en driven by cc - connected to flexray channel b ports cb_rx, cb_tx, and ca_tr_en not driven by cc 11reserved table 26-8. fr_mcr field descriptions field description
flexray communication controller 26-16 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.5.2.5 system memory base address register (fr_symbadr) note the system memory base address must be set before the cc is enabled. the system memory base address regi sters define the base address of th e flexray memory area within the system memory. the base address is used by the bmif to calculat e the physical memory address for system memory accesses. 26.5.2.6 strobe signal control register (fr_stbscr) this register is used to assign the individual protocol timing related strobe signals given in table 26-12 to the external strobe ports. each strobe signal can be as signed to at most one strobe port. each write access base + 0x0004 write: disabled mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r smba[31:16] w rese t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 26-4. system memory base addr ess high register (fr_symbadhr) base + 0x0006 write: disabled mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r smba[15:4] 0 0 0 0 w rese t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 26-5. system memory base address low register (fr_symbadlr) table 26-10. fr_symbadr field descriptions field description smba system memory base address ? this is the value of the system memory base address for the individual message buffers and sync frame table. this is the value of the syst em memory base address for the receive fifo if the fifo address mode bit fr_mcr[fa m] is set to 1. it is defines as a byte address. base + 0x0008 16-bit write access required write: anytime 0123456789101112131415 r0 0 0 0 sel 000 enb 00 stbpsel wwmd rese t 0000000000000000 figure 26-6. strobe signal control register (fr_stbscr)
flexray communication controller freescale semiconductor 26-17 pxs20 microcontroller reference manual, rev. 1 to registers overwrites the previ ously written enb and stbpsel values for the signal indicated by sel. if more than one strobe signal is as signed to one strobe port, the curren t values of the strobe signals are combined with a binary or and presented at the strobe port. if no strobe signal is assigned to a strobe port, the strobe port carries logic 0. for more detailed and timing in formation refer to section 26.6.16, strobe signal support . note in single channel device mode, cha nnel b related strobe signals are undefined and should not be as signed to the strobe ports. .; table 26-11. fr_stbscr field descriptions field description wmd write mode ? this control bit defines the write mode of this register. 0 write to all fields in this register on write access. 1 write to sel field only on write access. sel strobe signal select ? this control field selects one of the strobe signals given in ta b l e 2 6 - 1 2 to be enabled or disabled and assigned to one of the four strobe ports given in table 26-12 . enb strobe signal enable ? the control bit is used to enable and to disable the strobe signal selected by stbssel. 0 strobe signal is disabled and not assigned to any strobe port. 1 strobe signal is enabled and assigned to the strobe port selected by stbpsel. stbpsel strobe port select ? this field selects the strobe port th at the strobe signal selected by the sel is assigned to. all strobe signals that are enabled and assigned to the same strobe port are combined with a binary or operation. 00 assign selected signal to dbg0 01 assign selected signal to dbg1 10 assign selected signal to dbg2 11 assign selected signal to dbg3 table 26-12. strobe signal mapping sel description channel type offset 1 referenc e dec hex 0 0x0 arm ? value +1 mt start 1 0x1 mt ? value +1 mt start 2 0x2 cycle start ? pulse 0 mt start 3 0x3 minislot start ? pulse 0 mt start 4 0x4 slot start a pulse 0 mt start 5 0x5 b 6 0x6 receive data after glit ch filtering a value +4 ca_rx 70x7 b cb_rx 8 0x8 channel idle indicator a level +5 ca_rx 90x9 b cb_rx 10 0xa syntax error detected a pulse +4 ca_rx 11 0xb b cb_rx 12 0xc content error detected a level +4 ca_rx 13 0xd b cb_rx
flexray communication controller 26-18 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.5.2.7 message buffer data size register (fr_mbdsr) this register defines the size of the message buffer data section for th e two message buffer segments in a number of two-byte entities. the cc provides two independent se gments for the individual messag e buffers. all individual message buffers within one segment have to have the same size for the message buffer data section. this size can be different for the two message buffer segments. 14 0xe receive fifo almost-full interrupt signals a value n.a. rx fifo a almost full interrupt 15 0xf b rx fifo b almost full interrupt notes: 1 given in pe clock cycles. base + 0x000c write: poc:config 0123456789101112131415 r0 mbseg2ds 0 mbseg1ds w rese t 0000000000000000 figure 26-7. message buffer data size register (fr_mbdsr) table 26-13. fr_mbdsr field descriptions field description mbseg2ds message buffer segment 2 data size ? the field defines the size of the message buffer data section in two-byte entities for message buffers within the second message buffer segment. mbseg1ds message buffer segment 1 data size ? the field defines the size of the message buffer data section in two-byte entities for message buffers within the first message buffer segment. table 26-12. strobe signal mapping (continued) sel description channel type offset 1 referenc e dec hex
flexray communication controller freescale semiconductor 26-19 pxs20 microcontroller reference manual, rev. 1 26.5.2.8 message buffer segment size and utilization regi ster (fr_mbssutr) this register is used to define the last individual message buffer that belongs to the first message buffer segment and the number of the last used individual message buffer. 26.5.2.9 pe dram access register (fr_pedrar) this register is used to trigger write and read operations on the pe data memory (pe dram). these operations are used for memory error in jection and memory error observation. base + 0x000e write: poc:config 0123456789101112131415 r0 0 last_mb_seg1 00 last_mb_util w rese t 0011111100111111 figure 26-8. message buffer segment size and utilization register (fr_mbssutr) table 26-14. fr_mbssutr field descriptions field description last_mb_seg1 last message buffer in segment 1 ? this field defines the message buffer number of the last individual message buffer that is assigned to the first message buffer segment. the individual message buffers in the first segment correspond to th e message buffer control registers fr_mbccsrn, fr_mbccfrn, fr_mbfidrn, fr_mbidxrn with n <= last_mb_seg1. the first message buffer segment contains last_mb_seg1+1 individual message buffers. note: the first message buffer segment contains at least one individual message buffer. the individual message buffers in the second message buffer segment correspond to the message buffer control registers fr _mbccsrn, fr_mbccfrn, fr_mbfidrn, fr_mbidxrn with l ast_mb_seg1 < n < 64. note: if last_mb_seg1 = 63 all individual message buffers belong to the first message buffer segment and the second message buffer segment is empty. last_mb_util last message buffer utilized ? this field defines the message buffer number of last utilized individual message buffer. the message buffer search engine examines all individual message buffer with a message buffer number n <= last_mb_util. note: if last_mb_util=last_mb_seg1 all individual message buffers belong to the first message buffer segment and the second message buffer segment is empty. base + 0x0010 16-bit write access required write: normal mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r inst addr dad w rese t 0000000000000000 figure 26-9. pe dram access register (fr_pedrar)
flexray communication controller 26-20 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 each write access to this register s initiates a read or write operati on on the pe dram. the access done status bit dad is cleared after the write access and is set if the pe dram access has been finished. in case of an pe dram write access, the data provided in pe dram data register (fr_pedrdr) are written into the pe dram, read back from the pe dram and are stored into the pe dram data register (fr_pedrdr) . in case of an pe dram read access, the requested da ta are read from pe dram and stored into the pe dram data register (fr_pedrdr) . for a detailed description refer to section 26.6.24, memory content error detection 26.5.2.10 pe dram data register (fr_pedrdr) this register provides the data to be written to or read from the pe dram by th e access initiated by write access to the pe dram access register (fr_pedrar) . table 26-15. fr_pedrar field descriptions field description inst pe dram access instruction ? this field defines the operati on to be executed on the pe dram. 0011 pe dram write: write fr_pedrdr[da ta] to pe dram address addr (16 bit) 0101 pe dram read: read data from pe dram address addr (16 bit) into fr_pedrdr[data] other reserved addr pe dram access address ? this field defines the address in the pe dram to be written to or read from. dad pe dram access done ? this status bit is cleared when the application has written to this register and is set when the pe dram access has finished. 0 pe dram access running 1 pe dram access done base + 0x0012 16-bit write access required write: normal mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r data w rese t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 26-10. pe dram data register (fr_pedrdr)
flexray communication controller freescale semiconductor 26-21 pxs20 microcontroller reference manual, rev. 1 26.5.2.11 protocol operation control register (fr_pocr) the application uses th is register to issue ? protocol control commands ? external clock correction commands protocol control commands are issu ed by writing to the po ccmd field. for more in formation on protocol control commands, see section 26.7.6, protocol control command execution . external clock correction commands are issued by wr iting to the eoc_ap and erc_ap fields. for more information on external clock correction, refer to section 26.6.11, external clock synchronization . base + 0x0014 write: normal mode 0123456789101112131415 r0 0 0 0 eoc_ap erc_ap bsy 0 0 0 poccmd wwme wmc rese t 0000000000000000 figure 26-11. protocol operation control register (fr_pocr)
flexray communication controller 26-22 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 table 26-16. fr_pocr field descriptions field description wme write mode external correction ? this bit controls the write mode of the eoc_ap and erc_ap fields. 0 write to eoc_ap and erc_ap fields on register write. 1 no write to eoc_ap and erc_ap fields on register write. eoc_ap external offset correction application ? this field is used to trigger the application of the external offset correctio n value defined in the protocol configuration register 29 (fr_pcr29) . 00 do not apply external offset correction value 01 reserved 10 subtract external o ffset correction value 11 add external offset correction value erc_ap external rate correction application ? this field is used to trigger application of the external rate correction value defined in the protocol configuration register 21 (fr_pcr21) 00 do not apply external rate correction value 01 reserved 10 subtract external rate correction value 11 add external rate correction value bsy wmc protocol control command write busy ? this status bit indicates the acceptance of the protocol control command issued by the application via the poccmd field. the cc sets this status bit when the application has issued a protocol co ntrol command via the poccmd field. the cc clears this status bit when protocol contro l command was accepted by the pe.when the application issues a protocol co ntrol command while th e bsy bit is asserted, the cc ignores this command, sets the protocol command ignored error flag pcmi_ef in the chi error flag register (fr_chierfr) , and will not change the value of the poccmd field. 0 command write idle, command accepted and ready to receive new protocol command. 1 command write busy, command not yet accepted, not ready to receive new protocol command. write mode command ? this bit controls the write mode of the poccmd field. 0 write to poccmd field on register write. 1 do not write to poccmd field on register write. poccmd protocol control command ? the application writes to this field to issue a protocol control command to the pe. the cc send s the protocol command to th e pe immediately. while the transfer is running, the bsy bit is set. 0000 allow_coldstart ? immediately activate capability of node to cold start cluster. 0001 all_slots ? delayed 1 transition to the all slots transmission mode. 0010 config ? immediately transition to the poc:config state. 0011 freeze ? immediately transition to the poc:halt state. 0100 ready, config_complete ? immediately transition to the poc:ready state. 0101 run ? immediately transition to the poc:startup start state. 0110 default_config ? immediately transition to the poc:default config state. 0111 halt ? delayed transition to the poc:halt state 1000 wakeup ? immediately initiate the wakeup procedure. 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved notes: 1 delayed means on completion of current communication cycle.
flexray communication controller freescale semiconductor 26-23 pxs20 microcontroller reference manual, rev. 1 26.5.2.12 global interrupt flag a nd enable register (fr_gifer) this register provides the means to control some of the interrupt request lines and provides the corresponding interrupt flags. the interrupt flags mif, prif, chif, rbif, and tbif are the outcome of a binary or of the related individual interrupt flags and interrupt enable s. the generation scheme for these flags is depicted in figure 26-160 . for more details on in terrupt generation, see section 26.6.20, interrupt support . these flags are cleared automati cally when all of the correspondi ng interrupt flags or interrupt enables in the related interrupt flag and en able registers are cleared by the application. base + 0x0016 write: normal mode 0123456789101112131415 r mif prif chif wup if fafb if fafa if rbif tbif mie prie chie wup ie fafb ie fafa ie rbie tbie w w1c w1c w1c reset0000000000000000 figure 26-12. global interrupt flag and enable register (fr_gifer) table 26-17. fr_gifer field descriptions field description mif module interrupt flag ? this flag is asserted if at least one of the other interrupt flags in this register and its related interrupt enable is asserted. 0 no interrupt flag is asserted or no interrupt enable is set 1 at least one of the other interrupt flags in this re gister is asserted and the related interrupt bit is asserted, too prif protocol interrupt flag ? this flag is set if at least one of the individual protocol interrupt flags in the protocol interrupt flag register 0 (fr_pifr0) and protocol interrupt flag register 1 (fr_pifr1) is asserted and the related interrupt enable flag is asserted. 0 all individual protocol interrupt flags are equa l to 0 or no interrupt enable bit is set. 1 at least one of the individual protocol interrupt flags and the related interrupt enable is equal to 1. chif chi interrupt flag ? this flag is set if at least one of the individual chi error flags in the chi error flag register (fr_chierfr) is asserted and the chi error interrupt enable fr_gifer[chie] is asserted. 0 all chi error flags are equal to 0 or the chi error interrupt is disabled 1 at least one chi error flag is asserted and chi error interrupt is enabled wupif wakeup interrupt flag ? this flag is set when the cc has received a wakeup symbol on the flexray bus. the application can determine on wh ich channel the wakeup symbol was received by reading the related wakeup flags wub and wua in the protocol status register 3 (fr_psr3). 0 no wakeup condition or interrupt disabled 1 wakeup symbol received on flexray bus and interrupt enabled
flexray communication controller 26-24 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 fafbif receive fifo channel b almost full interrupt flag ? this flag is set when one of the following events occurs a) the current number of fifo b entries is equal to or greater than the watermark defined by the wm field in the receive fifo watermark and selection register (fr_rfwmsr) , and the cc writes a received message into the fifo b, or b) the current number of fifo b entries is at least 1 and the periodic timer as defined by receive fifo periodic timer register (fr_rfptr) expires. 0 no such event 1 fifo b almost full event has occurred fafaif receive fifo channel a almost full interrupt flag ? this flag is set when one of the following events occurs a) the current number of fifo a entries is equal to or greater than the watermark defined by the wm field in the receive fifo watermark and selection register (fr_rfwmsr) , and the cc writes a received message into the fifo a, or b) the current number of fifo b entries is at least 1 and the periodic timer as defined by receive fifo periodic timer register (fr_rfptr) expires. 0 no such event 1 fifo a almost full event has occurred rbif receive message buffer interrupt flag ? this flag is set if for at least one of the individual receive message buffers (fr_mbccsr n[mtd] = 0) both the interrup t flag mbif and the interrupt enable bit mbie in the corresponding message buffer configuration, control, status registers (fr_mbccsrn) are asserted. the application can not clear this rbif flag directly. this flag is cleared by the cc when all of the interrupt flags mbif of the individual receive message buffers are cleared by the application or if the applic ation has cleared the interrupt enables bit mbie. 0 none of the individual receive message buffers has the mbif and mbie flag asserted. 1 at least one individual receive message buffer has the mbif and mbie flag asserted. tbif transmit message bu ffer interrupt flag ? this flag is set if for at least one of the individual single or double transmit message buffers (fr_mb ccsrn[mtd] = 1) both the interrupt flag mbif and the interrupt enable bit mbie in the corresponding message buffer configuration, control, status registers (fr_mbccsrn) are equal to 1. the applicatio n can not clear this tbif flag directly. this flag is cleared by the cc when either all of the individual interrupt flags mbif of the individual transmit message buffers are cleared by the application or the host has cleared the interrupt enables bit mbie. 0 none of the individual transmit message buffers has the mbif and mbie flag asserted. 1 at least one individual transmit message buffer has the mbif and mbie flag asserted. mie module interrupt enable ? this flag controls if the module interrupt line is asserted when the mif flag is set. 0 disable interrupt line 1 enable interrupt line prie protocol interrupt enable ? this flag controls if the protocol interrupt line is asserted when the prif flag is set. 0 disable interrupt line 1 enable interrupt line chie chi interrupt enable ? this flag controls if the chi inte rrupt line is asserted when the chif flag is set. 0 disable interrupt line 1 enable interrupt line table 26-17. fr_gifer field descriptions (continued) field description
flexray communication controller freescale semiconductor 26-25 pxs20 microcontroller reference manual, rev. 1 26.5.2.13 protocol interrupt flag register 0 (fr_pifr0) the register holds one set of the prot ocol-related individual interrupt flags. wupie wakeup interrupt enable ? this flag controls if the wakeup interrupt line is asserted when the wupif flag is set. 0 disable interrupt line 1 enable interrupt line fafbie receive fifo channel b almo st full interrupt enable ? this flag controls if the rx fifo b almost full interrupt line is asserted when the fafbif flag is set. 0 disable interrupt line 1 enable interrupt line fafaie receive fifo channel a almo st full interrupt enable ? this flag controls if the rx fifo a almost full interrupt line is asserted when the fafaif flag is set. 0 disable interrupt line 1 enable interrupt line rbie receive message buffer interrupt enable ? this flag controls if the receive message buffer interrupt line is asserted when the rbif flag is set. 0 disable interrupt line 1 enable interrupt line tbie transmit message buffer interrupt enable ? this flag controls if the transmit message buffer interrupt line is asserted when the tbif flag is set. 0 disable interrupt line 1 enable interrupt line base + 0x0018 write: normal mode 0123456789101112131415 rfatl _if intl _if ilcf _if csa _if mrc _if moc _if ccl _if mxs _if mtx _if lt x b _if lt x a _if tbvb _if tbva _if ti2 _if ti1 _if cys _if w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 26-13. protocol interrupt flag register 0 (fr_pifr0) table 26-17. fr_gifer field descriptions (continued) field description
flexray communication controller 26-26 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 table 26-18. fr_pifr0 field descriptions field description fatl_if fatal protocol error interrupt flag ? this flag is set when the protocol engine has detected a fatal protocol error. in this case, the protocol engine goes into the poc:halt state immediately. the fatal protocol errors are: 1) platesttx violation, as described in the mac process of the flexray protocol 2) transmission across slot boundary violation, as described in the fsp process of the flexray protocol 0 no such event. 1 fatal protocol error detected. intl_if internal protocol error interrupt flag ? this flag is set when the protocol engine has detected an internal protocol error. in this case, the protocol engine goes into the poc:halt state immediately. an internal protocol error occu rs when the protocol engine has not finished a calculation and a new calculation is requested. this can be caused by a hardware error. 0 no such event. 1 internal protocol error detected. ilcf_if illegal protocol configuration interrupt flag ? this flag is set when the protocol engine has detected an illegal protocol config uration parameter setting. in this case, the protocol engine goes into the poc:halt state immediately. the protocol engine checks the listen_timeout value programmed into the protocol configuration register 14 (fr_pcr14) and protocol configuration register 15 (fr_pcr15) when the config_complete command was sent by the application via the protocol oper ation control register (fr_pocr) . if the value of listen_timeout is equal to zero, the protocol configuration setting is considered as illegal. 0 no such event. 1 illegal protocol c onfiguration detected. csa_if cold start abort interrupt flag ? this flag is set when the configured number of allowed cold start attempts is reached and none of these attempts was successful. the number of allowed cold start attempts is configured by t he coldstart_attemp ts field in the protocol configuration register 3 (fr_pcr3) . 0 no such event. 1 cold start aborted and no more coldstart attempts allowed. mrc_if missing rate correction interrupt flag ? this flag is set when an insufficient number of measurements is available for rate corre ction at the end of the communication cycle. 0 no such event 1 insufficient number of measurements for rate correction detected moc_if missing offset corr ection interrupt flag ? this flag is set when an insufficient number of measurements is available for offset correction. th is is related to the missing_term event in the csp process for offset correction in the flexray protocol. 0 no such event. 1 insufficient number of measurements for offset correction detected. ccl_if clock correction limit reached interrupt flag ? this flag is set when the internal calculated offset or rate calculation values have reached or e xceeded its configured thresholds as given by the offset_coorection_out field in the protocol configuration register 9 (fr_pcr9) and the rate_correction_out field in the protocol configuration register 14 (fr_pcr14) . 0 no such event. 1 offset or rate correction limit reached.
flexray communication controller freescale semiconductor 26-27 pxs20 microcontroller reference manual, rev. 1 mxs_if max sync frames detected interrupt flag ? this flag is set when the number of synchronization frames detected in the current commun ication cycle exceeds the value of the node_sync_max field in the protocol configuration register 30 (fr_pcr30) . 0 no such event. 1 more than node_sync_max sync frames detected. note: only synchronization frames that have passed the synchronization frame acceptance and rejection filters are taken into account. mtx_if media access test symbol received interrupt flag ? this flag is set when the mts symbol was received on channel a or channel b. 0 no such event. 1 mts symbol received. ltxb_if platesttx violation on channel b interrupt flag ? this flag is set when the frame transmission on channel b in the dynamic segment exceeds the dy namic segment boundary. this is related to the platesttx violation, as described in the mac process of the flexray protocol. 0 no such event. 1 platesttx violation occurred on channel b. ltxa_if platesttx violation on channel a interrupt flag ? this flag is set when the frame transmission on channel a in the dynamic segment exceeds the dy namic segment boundary. this is related to the platesttx violation as described in the mac process of the flexray protocol. 0 no such event. 1 platesttx violation occurred on channel a. tbvb_if transmission across boundary on channel b interrupt flag ? this flag is set when the frame transmission on channel b crosses the slot boundary. this is related to the transmission across slot boundary violation as described in the fsp process of the flexray protocol. 0 no such event. 1 transmission across boundary violation occurred on channel b. tbva_if transmission across boundary on channel a interrupt flag ? this flag is set when the frame transmission on channel a crosses the slot boundary. this is related to the transmission across slot boundary violation as described in the fsp process of the flexray protocol. 0 no such event. 1 transmission across boundary violation occurred on channel a. ti2_if timer 2 expired interrupt flag ? this flag is set whenever timer 2 expires. 0 no such event. 1 timer 2 has reached its time limit. ti1_if timer 1 expired interrupt flag ? this flag is set whenever timer 1 expires. 0 no such event 1 timer 1 has reached its time limit cys_if cycle start interrupt flag ? this flag is set when a communication cycle starts. 0 no such event 1 communication cycle started. table 26-18. fr_pifr0 field descriptions (continued) field description
flexray communication controller 26-28 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.5.2.14 protocol interrupt flag register 1 (fr_pifr1) the register holds one set of the prot ocol-related individual interrupt flags. base + 0x001a write: normal mode 0123456789101112131415 remc _if ipc _if pecf _if psc _if ssi3 _if ssi2 _if ssi1 _if ssi0 _if 00 evt _if odt _if 0000 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 26-14. protocol interrupt flag register 1 (fr_pifr1) table 26-19. fr_pifr1 field descriptions field description emc_if error mode changed interrupt flag ? this flag is set when the value of the errmode bit field in the protocol status register 0 (fr_psr0) is changed by the cc. 0 no such event. 1 errmode field changed. ipc_if illegal protocol control command interrupt flag ? this flag is set when the pe tries to execute a protocol control command, which was issued via the poccmd field of the protocol operation control register (fr_pocr) , and detects that this protocol control command is not allowed in the current protocol state. in this case the command is not executed. for more details, see section 26.7.6, protocol control command execution . 0 no such event. 1 illegal protocol control command detected. pecf_if protocol engine communication failure interrupt flag ? this flag is set if the cc has detected a communication failure between the protocol engine and the cc host interface 0 no such event. 1 protocol engine communication failure detected. psc_if protocol state changed interrupt flag ? this flag is set when the protocol state in the protstate field in the protocol status register 0 (fr_psr0) has changed. 0 no such event. 1 protocol state changed. ssi3_if ssi2_if ssi1_if ssi0_if slot status counter incr emented inte rrupt flag ? each of these flag s is set when the slotstatuscnt field in the corresponding slot status c ounter registers (fr_sscr0?fr_sscr3) is incremented . 0 no such event. 1 the corresponding slot status counter has incremented. evt_if even cycle table written interrupt flag ? this flag is set if the cc has written the sync frame measurement / id tables into the flexray memory area for the even cycle. 0 no such event. 1 sync frame measurement table written odt_if odd cycle table written interrupt flag ? this flag is set if the cc has written the sync frame measurement / id tables into the flexray memory area for the odd cycle. 0 no such event. 1 sync frame measurement table written
flexray communication controller freescale semiconductor 26-29 pxs20 microcontroller reference manual, rev. 1 26.5.2.15 protocol interrupt enable register 0 (fr_pier0) this register defines whether or not the individual interrupt flags defined in the protocol interrupt flag register 0 (fr_pifr0) can generate a protocol interrupt request. base + 0x001c write: anytime 0123456789101112131415 r fatl _ie intl _ie ilcf _ie csa _ie mrc _ie moc _ie ccl _ie mxs _ie mtx _ie lt x b _ie lt x a _ie tbvb _ie tbva _ie ti2 _ie ti1 _ie cys _ie w reset0000000000000000 figure 26-15. protocol interrupt enable register 0 (fr_pier0) table 26-20. fr_pier0 field descriptions field description fatl_ie fatal protocol error interrupt enable ? this bit controls fatl_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled intl_ie internal protocol er ror interrupt enable ? this bit controls in tl_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled ilcf_ie illegal protocol configuration interrupt enable ? this bit controls ilcf_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled csa_ie cold start abort interrupt enable ? this bit controls csa_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled mrc_ie missing rate correction interrupt enable ? this bit controls mrc_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled moc_ie missing offset correct ion interrupt enable ? this bit controls moc_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled ccl_ie clock correction limit reached interrupt enable ? this bit controls ccl_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled mxs_ie max sync frames detected interrupt enable ? this bit controls mxs_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled
flexray communication controller 26-30 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.5.2.16 protocol interrupt enable register 1 (fr_pier1) this register defines whether or not th e individual interrupt flags defined in protocol interrupt flag register 1 (fr_pifr1) can generate a protocol interrupt request. mtx_ie media access test symbol received interrupt enable ? this bit controls mtx_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled lt x b _ i e platesttx violation on channel b interrupt enable ? this bit controls ltxb_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled lt x a _ i e platesttx violation on channel a interrupt enable ? this bit controls ltxa_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled tbvb_ie transmission across boundary on channel b interrupt enable ? this bit controls tbvb_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled tbva_ie transmission across boundary on channel a interrupt enable ? this bit controls tbva_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled ti2_ie timer 2 expired interrupt enable ? this bit controls ti1_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled ti1_ie timer 1 expired interrupt enable ? this bit controls ti1_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled cys_ie cycle start interrupt enable ? this bit controls cyc_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled base + 0x001e write: anytime 0123456789101112131415 r emc _ie ipc _ie pecf _ie psc _ie ssi3 _ie ssi2 _ie ssi1 _ie ssi0 _ie 00 evt _ie odt _ie 0000 w reset0000000000000000 figure 26-16. protocol interrupt enable register 1 (fr_pier1) table 26-20. fr_pier0 field descriptions field description
flexray communication controller freescale semiconductor 26-31 pxs20 microcontroller reference manual, rev. 1 26.5.2.17 chi error flag register (fr_chierfr) this register holds the chi related error flags. the interrupt generation for each of these error flags is controlled by the chi interrupt enable bit chie in the global interrupt flag and enable register (fr_gifer) . table 26-21. fr_pier1 field descriptions field description emc_ie error mode changed interrupt enable ? this bit controls emc_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled ipc_ie illegal protocol control command interrupt enable ? this bit controls ipc_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled pecf_ie protocol engine communication failure interrupt enable ? this bit controls pecf_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled psc_ie protocol state changed interrupt enable ? this bit controls psc_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled ssi3_ie ssi2_ie ssi1_ie ssi0_ie slot status counter incr emented interrupt enable ? this bit controls ssi[3:0]_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled evt_ie even cycle table written interrupt enable ? this bit controls evt_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled odt_ie odd cycle table written interrupt enable ? this bit controls odt_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled base + 0x0020 write: normal mode 0123456789101112131415 rfrlb _ef frla _ef pcmi _ef fovb _ef fova _ef mbs _ef mbu _ef lck _ef dbl _ef sbcf _ef 1 notes: 1 the flexray controller should be stopped via a freeze or ha lt command and subsequently rest arted when any of the error flags chierfr[sbcf_ef] or chierfr[ilsa_ef] is set. fid _ef dpl _ef spl _ef nml _ef nmf _ef ilsa _ef 1 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 26-17. chi error flag register (fr_chierfr)
flexray communication controller 26-32 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 table 26-22. fr_chierfr field descriptions field description frlb_ef frame lost channel b error flag ? this flag is set if a co mplete frame was received on channel b but could not be stored in the select ed individual message buffer because this message buffer is currently locked by the applicatio n. in this case, the frame and the related slot status information are lost. 0 no such event 1 frame lost on channel b detected frla_ef frame lost channel a error flag ? this flag is set if a co mplete frame was received on channel a but could not be stored in the select ed individual message buffer because this message buffer is currently locked by the applicatio n. in this case, the frame and the related slot status information are lost. 0 no such error 1 frame lost on channel a detected pcmi_ef protocol command ignored error flag ? this flag is set if the application has issued a poc command by writing to the poccmd field in the protocol operation control register (fr_pocr) while the bsy flag is equal to 1. in this case the command is ignored by the cc and is lost. 0 no such error 1 poc command ignored fovb_ef receive fifo overrun channel b error flag ? this flag is set when an overrun of the fifo for channel b occurred. this error occurs if a semantically valid frame was received on channel b and matches the all criteria to be appended to th e fifo for channel b but the fifo is full. in this case, the received frame and its related slot status information is lost. 0 no such error 1 fifo overrun on channel b has been detected fova_ef receive fifo overrun channel a error flag ? this flag is set when an overrun of the fifo for channel a occurred. this error occurs if a semantically valid frame was received on channel a and matches the all criteria to be appended to th e fifo for channel a but the fifo is full. in this case, the received frame and its related slot status information is lost. 0 no such error 1 fifo overrun on channel b has been detected msb_ef message buffer search error flag ? this flag is set if the message buffer search engine is still running while the next search cycle must be starte d due to the flexray prot ocol timing. in this case, not all message buffers are considered while searching. 0 no such event 1 search engine active while search start appears mbu_ef message buffer utilization error flag ? this flag is asserted if the application writes to a message buffer control field that is beyond t he number of utilized message buffers programmed in the message buffer segment size and ut ilization register (fr_mbssutr) . if the application writes to a fr_mbccsrn register with n > last_mb_util, the cc ignores the write attempt and asserts the message buff er utilization error flag mbu_ef in the chi error flag register (fr_chierfr) . 0 no such event 1 non-utilized message buffer enabled lck_ef lock error flag ? this flag is set if the application tries to lock a message buffer that is already locked by the cc due to internal operations. in that case, the cc does not grant the lock to the application. the application must issue the lock request again. 0 no such error 1 lock error detected
flexray communication controller freescale semiconductor 26-33 pxs20 microcontroller reference manual, rev. 1 dbl_ef double transmit message buffer lock error flag ? this flag is set if the application tries to lock the transmit side of a double transmit message buffer. in this case, the cc does not grant the lock to the transmit side of a double transmit message buffer. 0 no such event 1 double transmit buffer lock error occurred sbcf_ef system bus communication failure error flag ? this flag is set if a system bus access was not finished within the required amount of time (see section 26.6.19.2, system bus access timeout ). 0 no such event 1 system bus access not finished in time fid_ef frame id error flag ? this flag is set if the frame id st ored in the message buffer header area differs from the frame id stored in the message buffer control register. 0 no such error occurred 1 frame id error occurred dpl_ef dynamic payload length error flag ? this flag is set if the payload length written into the message buffer header field of a single or double transmit message buffer assigned to the dynamic segment is greater than the maximum payl oad length for the dynamic segment as it is configured in the corresponding prot ocol configuration register field max_payload_length_dynamic in the protocol configuration register 24 (fr_pcr24) . 0 no such error occurred 1 dynamic payload length error occurred spl_ef static payload length error flag ? this flag is set if the payload length written into the message buffer header field of a single or double transmit message buffer assigned to the static segment is different from the payload length for the static segment as it is configured in the corresponding protocol configuration regi ster field payload_length_static in the protocol configuration register 19 (fr_pcr19) . 0 no such error occurred 1 static payload length error occurred nml_ef network management length error flag ? this flag is set if the payload length written into the header structure of a receive message buffer assigned to the st atic segment is less than the configured length of the network manage ment vector as configured in the network management vector length register (fr_nmvlr) . in this case the received part of the network management vector will be used to update the network management vector. 0 no such error occurred 1 network management length error occurred nmf_ef network management frame error flag ? this flag is set if a received message in the static segment with a preamble indicator flag pp assert ed has its null frame indicator flag nf asserted as well. in this case, the global network management registers (see network management vector registers (fr_nmvr0?fr_nmvr5) ) are not updated. 0 no such error occurred 1 network management frame error occurred ilsa_ef illegal system bus address error flag ? this flag is set if the external system bus subsystem has detected an access to an illegal system bus address from the cc (see section 26.6.19.1, system bus illegal address access ). 0 no such event 1 illegal system bus address accessed table 26-22. fr_chierfr field descriptions (continued) field description
flexray communication controller 26-34 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.5.2.18 message buffer interrupt vector register (fr_mbivec) this register indicates the lowest numbered receive message buffer and the lo west numbered transmit message buffer that have their interr upt status flag mbif and interrupt enable mbie bits asserted. this means that message buffers with lower me ssage buffer numbers have higher priority. 26.5.2.19 channel a status error counter register (fr_casercr) this register provides the channel st atus error counter for channel a. th e protocol engine generates a slot status vector for each static slot, each dynamic slot, the symbol window, a nd the nit. the slot status vector contains the four protocol related error indicator bits vss!syntaxerror, vss!cont enterror, vss!bviolation , and vss!txconflict . the cc increments the status error counter by 1 if, for a sl ot or segment, at least one error indicator bit is set to 1. th e counter wraps around after it has r eached the maximum value. for more information on slot status monitoring, see section 26.6.18, slot status monitoring . base + 0x0022 0123456789101112131415 r 0 0 tbivec 0 0 rbivec w rese t 0000000000000000 figure 26-18. message buffer interrupt vector register (fr_mbivec) table 26-23. fr_mbivec field descriptions field description tbivec transmit buffer interrupt vector ? this field provides the number of the lowest numbered enabled transmit message buffer that has its interr upt status flag mbif and its interrupt enable bit mbie set. if there is no transmit message buffer wi th the interrupt status flag mbif and the interrupt enable mbie bits asserted, the value in this field is set to 0. rbivec receive buffer interrupt vector ? this field provides the message buffer number of the lowest numbered receive message buffer which has its inte rrupt flag mbif and its interrupt enable bit mbie asserted. if there is no receive message buff er with the interrupt st atus flag mbif and the interrupt enable mbie bits asserted, the value in this field is set to 0. base + 0x0024 a dditional reset: run command 0123456789101112131415 r status_err_cnt w rese t 0000000000000000 figure 26-19. channel a status error counter register (fr_casercr)
flexray communication controller freescale semiconductor 26-35 pxs20 microcontroller reference manual, rev. 1 26.5.2.20 channel b status error counter register (fr_cbsercr) this register provides the channel st atus error counter for channel b. th e protocol engine generates a slot status vector for each static slot, each dynamic slot, the symbol window, a nd the nit. the slot status vector contains the four protocol related error indicator bits vss!syntaxerror , vss!contenterror , vss!bviolation , and vss!txconflict . the cc increments the status error counter by 1 if, for a sl ot or segment, at least one error indicator bit is set to 1. th e counter wraps around after it has r eached the maximum value. for more information on slot status monitoring see section 26.6.18, slot status monitoring . 26.5.2.21 protocol status register 0 (fr_psr0) this register provides information about the current protocol status. table 26-24. fr_casercr field descriptions field description status_err_ cnt channel status error counter ? this field provides the current value channel status error counter. the counter value is updated within the fi rst macrotick of the following slot or segment. base + 0x0026 additional reset: run command 0123456789101112131415 r status_err_cnt w rese t 0000000000000000 figure 26-20. channel b status error counter register (fr_cbsercr) table 26-25. fr_cbsercr field descriptions field description status_err_ cnt channel status error counter ? this field provides the current channel status error count. the counter value is updated within the first ma crotick of the following slot or segment. base + 0x0028 0123456789101112131415 r errmode slotmode 0 protstate startupstate 0 wakeupstatus w rese t 0000000000000000 figure 26-21. protocol status register 0 (fr_psr0)
flexray communication controller 26-36 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 table 26-26. fr_psr0 field descriptions field description errmode error mode ? protocol related variable: vpoc!errormode . this field indicates the error mode of the protocol. 00 active 01 passive 10 comm_halt 11 reserved slotmode slot mode ? protocol related variable: vpoc!slotmode . this field indicates the slot mode of the protocol. 00 single 01 all_pending 10 all 11 reserved protstate protocol state ? protocol related variable: vpoc!state. this field indicates the state of the protocol. 000 poc:default config 001 poc:config 010 poc:wakeup 011 poc:ready 100 poc:normal passive 101 poc:normal active 110 poc:halt 111 poc:startup startup state startup state ? protocol related variable: vpoc!startupstate. this field indicates the current sub-state of the startup procedure. 0000 reserved 0001 reserved 0010 poc:coldstart collision resolution 0011 poc:coldstart listen 0100 poc:integration consistency check 0101 poc:integrationi listen 0110 reserved 0111 poc:initialize schedule 1000 reserved 1001 reserved 1010 poc:coldstart consistency check 1011 reserved 1100 reserved 1101 poc:integration coldstart check 1110 poc:coldstart gap 1111 poc:coldstart join wakeup status wakeup status ? protocol related variable: vpoc!wakeupstatus . this field provides the outcome of the execution of the wakeup mechanism. 000 undefined 001 received_header 010 received_wup 011 collision_header 100 collision_wup 101 collision_unknown 110 transmitted 111 reserved
flexray communication controller freescale semiconductor 26-37 pxs20 microcontroller reference manual, rev. 1 26.5.2.22 protocol status register 1 (fr_psr1) base + 0x002a additional re set: csaa, csp, cpn: run command write: normal mode 0123456789101112131415 r csaa csp 0 remcsat cpn hhr frz aptac ww1c reset0000000000000000 figure 26-22. protocol status register 1 (fr_psr1) table 26-27. fr_psr1 field descriptions field description csaa cold start attempt aborted flag ? protocol related event: ?set coldstart abort indicator in chi? this flag is set when the cc has aborted a cold start attempt. 0 no such event 1 cold start attempt aborted csp leading cold start path ? this status bit is set when the cc has reached the poc:normal active state via the leading cold start path. this in dicates that this node has started the network 0 no such event 1 poc:normal active reached from poc:startup state via leading cold start path remcsat remaining coldstart attempts ? protocol related variable: vremainingcoldstartattempts this field provides the number of remaining cold start attempts that the cc will execute. cpn leading cold start path noise ? protocol related variable: vpoc!coldstartnoise this status bit is set if the cc has reached the poc:normal active state via the leading cold start path under noise conditions. this indicates there was some activity on the flexray bus while the cc was starting up the cluster. 0 no such event 1 poc:normal active state was reached from poc:startup state via noisy lead ing cold start path hhr host halt request pending ? protocol related variable: vpoc!chihaltrequest this status bit is set when cc receives th e halt command from the application via the protocol operation control register (fr_pocr) . the cc clears this status bi t after a hard reset condition or when the protocol is in the poc:default config state. 0 no such event 1 halt command received frz freeze occurred ? protocol related variable: vpoc!freeze this status bit is set when the cc has reached the poc:halt state due to the host freeze command or due to an internal error condition requiri ng immediate halt. the cc clears this status bit after a hard reset condition or when the protocol is in the poc:default config state. 0 no such event 1 immediate halt due to freeze or internal error condition aptac allow passive to active counter ? protocol related variable: vpoc!vallowpassivetoactive this field provides the number of consecutiv e even/odd communication cycle pairs that have passed with valid rate and offset correction terms, but the protocol is still in the poc:normal passive state due to an application configured delay to enter poc:normal active state. this delay is defined by the allow_passive_to_active field in the protocol configuration register 12 (fr_pcr12) .
flexray communication controller 26-38 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.5.2.23 protocol status register 2 (fr_psr2) this register provides a snapshot of status inform ation about the network idle time nit, the symbol window and the clock synchronizati on. the nit related status bits nbvb, nseb, nbva, and nsea are updated by the cc after the end of the nit and before the end of the first slot of the next communication cycle. the symbol window related status bits stcb, sbvb, sseb, mtb, stca, sbva, sseb, and mta are updated by the cc after the end of the sy mbol window and before the end of the current communication cycle. if no symbol wi ndow is configured, the symbol wi ndow related status bits remain in their reset state. the clock synchronization related cl kcorrfailcnt is updated by the cc after the end of the static segment and before th e end of the current communication cycle. base + 0x002c additional reset: run command 0123456789101112131415 r nbvb nseb stcb sbvb sseb mtb nbva nsea stca sbva ssea mta clkcorrfailcnt w reset0000000000000000 figure 26-23. protocol status register 2 (fr_psr2) table 26-28. fr_psr2 field descriptions field description nbvb nit boundary violation on channel b ? protocol related variable: vss!bviolation for nit on channel b this status bit is set when there was some medi a activity on the flexray bus channel b at the end of the nit. 0 no such event 1 media activity at boundaries detected nseb nit syntax error on channel b ? protocol related variable: vss!syntaxerror for nit on channel b this status bit is set when a syntax error was detected during nit on channel b. 0 no such event 1 syntax error detected stcb symbol window transmit conflict on channel b ? protocol related variable: vss!txconflict for symbol window on channel b this status bit is set if there was a transmissi on conflict during the symbol window on channel b. 0 no such event 1 transmission conflict detected sbvb symbol window boundary violation on channel b ? protocol related variable: vss!bviolation for symbol window on channel b this status bit is set if there was some media ac tivity on the flexray bus channel b at the start or at the end of the symbol window. 0 no such event 1 media activity at boundaries detected sseb symbol window syntax error on channel b ? protocol related variable: vss!syntaxerror for symbol window on channel b this status bit is set when a syntax error was detected during the symbol window on channel b. 0 no such event 1 syntax error detected
flexray communication controller freescale semiconductor 26-39 pxs20 microcontroller reference manual, rev. 1 mtb media access test symbol mts received on channel b ? protocol related variable: vss!validmts for symbol window on channel b this status bit is set if the media access test symbol mts was received in the symbol window on channel b. 0 no such event 1 mts symbol received nbva nit boundary violation on channel a ? protocol related variable: vss!bviolation for nit on channel a this status bit is set when there was some medi a activity on the flexray bus channel a at the end of the nit. 0 no such event 1 media activity at boundaries detected nsea nit syntax error on channel a ? protocol related variable: vss!syntaxerror for nit on channel a this status bit is set when a syntax error was detected during nit on channel a. 0 no such event 1 syntax error detected stca symbol window transmit conflict on channel a ? protocol related variable: vss!txconflict for symbol window on channel a this status bit is set if there was a transmission conflicts during the symbol window on channel a. 0 no such event 1 transmission conflict detected sbva symbol window boundary violation on channel a ? protocol related variable: vss!bviolation for symbol window on channel a this status bit is set if there was some media ac tivity on the flexray bus channel a at the start or at the end of the symbol window. 0 no such event 1 media activity at boundaries detected ssea symbol window syntax error on channel a ? protocol related variable: vss!syntaxerror for symbol window on channel a this status bit is set when a syntax error was detected during the symbol window on channel a. 0 no such event 1 syntax error detected mta media access test symbol mts received on channel a ? protocol related variable: vss!validmts for symbol window on channel a this status bit is set if the media access test symbol mts was received in the symbol window on channel a. 1 mts symbol received 0 no such event clkcorr- failcnt clock correction failed counter ? protocol related variable: vclockcorrectionfailed this field provides the number of consecutiv e even/odd communication cycle pairs that have passed without clock synchronization having performed an offset or a rate correction due to lack of synchronization frames. it is not incremented when it has reach ed the configured value of either max_without_clock_correction_fatal or max_without _clock_correction_passive as defined in the protocol configuration register 8 (fr_pcr8) . the cc resets this counter on a hard reset condition, when the protocol enters the poc:normal active state, or when both the rate and offset correction terms have be en calculated successfully. table 26-28. fr_psr2 field descriptions (continued) field description
flexray communication controller 26-40 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.5.2.24 protocol status register 3 (fr_psr3) this register provides aggregated ch annel status information as an accrued status of channel activity for all communication slots, re gardless of whether they are assigne d for transmission or subscribed for reception. it provides accrued information for the symbol window, the nit, and the wakeup status. base + 0x002e additional reset: run command write: normal mode 0123456789101112131415 r 0 0 wub abvb aacb aceb aseb avfb 0 0 wua abva aaca acea asea avfa w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 26-24. protocol status register 3 (fr_psr3) table 26-29. fr_psr3 field descriptions field description wub wakeup symbol received on channel b ? this flag is set when a wakeup symbol was received on channel b. 0 no wakeup symbol received 1 wakeup symbol received abvb aggregated boundary violation on channel b ? this flag is set when a boundary violation has been detected on channel b. boundary violations are detected in the communication slots, the symbol window, and the nit. 0 no boundary violation detected 1 boundary violation detected aacb aggregated additional communication on channel b ? this flag is set when at least one valid frame was received on channel b in a slot that also contained an additional communication with either syntax error, content error, or boundary violations. 0 no additional communication detected 1 additional communication detected aceb aggregated content error on channel b ? this flag is set when a content error has been detected on channel b. content errors are dete cted in the communication slots, the symbol window, and the nit. 0 no content error detected 1 content error detected aseb aggregated syntax error on channel b ? this flag is set when a syntax error has been detected on channel b. syntax errors are detected in the communication slots, the symbol window and the nit. 0 no syntax error detected 1 syntax errors detected avfb aggregated valid frame on channel b ? this flag is set when a syn tactically correct valid frame has been received in any static or dynamic slot through channel b. 1 at least one syntactically valid frame received 0 no syntactically valid frames received wua wakeup symbol received on channel a ? this flag is set when a wakeup symbol was received on channel a. 0 no wakeup symbol received 1 wakeup symbol received
flexray communication controller freescale semiconductor 26-41 pxs20 microcontroller reference manual, rev. 1 26.5.2.25 macrotick counter register (fr_mtctr) this register provides the macrotick c ount of the current communication cycle. abva aggregated boundary violation on channel a ? this flag is set when a boundary violation has been detected on channel a. boundary violations are detected in the communication slots, the symbol window, and the nit. 0 no boundary violation detected 1 boundary violation detected aaca aggregated additional communication on channel a ? this flag is set when a valid frame was received in a slot on channel a that also c ontained an additional communication with either syntax error, content error, or boundary violations. 0 no additional communication detected 1 additional communication detected acea aggregated content error on channel a ? this flag is set when a content error has been detected on channel a. content errors are dete cted in the communication slots, the symbol window, and the nit. 0 no content error detected 1 content error detected asea aggregated syntax error on channel a ? this flag is set when a syntax error has been detected on channel a. syntax errors are detected in the communication slots, the symbol window, and the nit. 0 no syntax error detected 1 syntax errors detected avfa aggregated valid frame on channel a ? this flag is set when a syn tactically correct valid frame has been received in any static or dynamic slot through channel a. 0 no syntactically valid frames received 1 at least one syntactically valid frame received base + 0x0030 0123456789101112131415 r0 0 mtct w reset0000000000000000 figure 26-25. macrotick counter register (fr_mtctr) table 26-30. fr_mtctr field descriptions field description mtct macrotick counter ? protocol related variable: vmacrotick this field provides the macrotick co unt of the current communication cycle. table 26-29. fr_psr3 field descriptions (continued) field description
flexray communication controller 26-42 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.5.2.26 cycle counter register (fr_cyctr) this register provides the number of the current communication cycle. 26.5.2.27 slot counter channel a register (fr_sltctar) this register provides the number of the current slot in the curren t communication cycle for channel a. base + 0x0032 0123456789101112131415 r 0 0 0 0 0 0 0 0 0 0 cyccnt w rese t 0000000000000000 figure 26-26. cycle counter register (fr_cyctr) table 26-31. fr_cyctr field descriptions field description cyccnt cycle counter ? protocol related variable: vcyclecounter this field provides the number of the current communication cycle. if the counter reaches the maximum value of 63, the counter wraps and starts from zero again. base + 0x0034 0123456789101112131415 r00000 slotcnta w rese t 0000000000000000 figure 26-27. slot counter channel a register (fr_sltctar) table 26-32. fr_sltctar field descriptions field description slotcnta slot counter value for channel a ? protocol related variable: vslotcounter for channel a this field provides the number of the current slot in the current communication cycle.
flexray communication controller freescale semiconductor 26-43 pxs20 microcontroller reference manual, rev. 1 26.5.2.28 slot counter channel b register (fr_sltctbr) this register provides the number of the current slot in the curren t communication cycle for channel b. 26.5.2.29 rate correction value register (fr_rtcorvr) this register provides the sign extende d rate correction value in microticks as it was calculated by the clock synchronization algorithm. the cc updates this register durin g the nit of each odd numbered communication cycle. base + 0x0036 0123456789101112131415 r00000 slotcntb w rese t 0000000000000000 figure 26-28. slot counter channel b register (fr_sltctbr) table 26-33. fr_sltctbr field descriptions field description slotcnta slot counter value for channel b ? protocol related variable: vslotcounter for channel b this field provides the number of the cu rrent slot in the cu rrent communication cycle. base + 0x0038 additional reset: run command 0123456789101112131415 rratecorr w rese t 0000000000000000 figure 26-29. rate correction value register (fr_rtcorvr) table 26-34. fr_rtcorvr field descriptions field description ratecorr rate correction value ? protocol related variable: vratecorrection (before value limitation and external rate correction) this field provides the sign extended rate correction value in microticks as it was calculated by the clock synchronization algorithm. the value is represented in 2?s complement format. this value does not include the value limitation and the applic ation of the external rate correction. if the magnitude of the internally calculated rate correction value exceeds the limit given by rate_correction_out in the protocol configuration register 13 (fr_pcr13) , the clock correction reached limit interrupt flag ccl_if is set in the protocol interrupt flag register 0 (fr_pifr0) . note: if the cc was not able to calculate a new rate correction term due to a lack of synchronization frames, the ratecorr value is not updated.
flexray communication controller 26-44 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.5.2.30 offset correction value register (fr_ofcorvr) this register provides the sign extend ed offset correction value in micro ticks as it was calculated by the clock synchronization algorithm. the cc updates this register during the nit. 26.5.2.31 combined interrupt flag register (fr_cifr) this register provides five combined interrupt flag s and a copy of three individual interrupt flags. the combined interrupt flags are the result of a binary or of the values of other interrupt flags regardless of the state of the interrupt enable bits . the generation scheme for the combin ed interrupt flags is depicted in figure 26-162 . the individual interrupt flags wupif, fafb if, and fafaif are copies of corresponding flags in the global interrupt flag and en able register (fr_gifer) and are provided here to simplify the application interrupt flag check. to clear the indivi dual interrupt flags, the application must use the global interrupt flag and enab le register (fr_gifer) . base + 0x003a additional reset: run command 0123456789101112131415 r offsetcorr w rese t 0000000000000000 figure 26-30. offset correction value register (fr_ofcorvr) table 26-35. fr_ofcorvr field descriptions field description offset- corr offset correction value ? protocol related variable: voffsetco rrection (before value limitation and external offset correction) this field provides the sign extended offset correc tion value in microticks as it was calculated by the clock synchronization algorithm. the value is represented in 2?s complement format. this value does not include the value limitation and the applic ation of the external offset correction. if the magnitude of the internally calculated rate correction value exceeds the limit given by offset_correction_out field in the protocol configuration register 29 (fr_pcr29) , the clock correction reached limit interrupt flag ccl_if is set in the protocol interrupt flag register 0 (fr_pifr0) . note: if the cc was not able to calculate an new offset correction term due to a lack of synchronization frames, the of fsetcorr value is not updated. base + 0x003c 0123456789101112131415 r 00000000mifprifchif wup if fafb if fafa if rbif tbif w reset0000000000000000 figure 26-31. combined interrupt flag register (fr_cifr)
flexray communication controller freescale semiconductor 26-45 pxs20 microcontroller reference manual, rev. 1 note the meanings of the combined status bits mif, prif, chif, rbif, and tbif are different from those mentioned in the global interrupt flag and enable register (fr_gifer) . 26.5.2.32 system memory access time-out register (fr_symator) table 26-36. fr_cifr field descriptions field description mif module interrupt flag ? this flag is set if there is at least one interrupt source that has its interrupt flag asserted. 0 no interrupt source has its interrupt flag asserted 1 at least one interrupt source has its interrupt flag asserted prif protocol interrupt flag ? this flag is set if at least one of the individual protocol interrupt flags in the protocol interrupt flag register 0 (fr_pifr0) or protocol interrupt flag register 1 (fr_pifr1) is equal to 1. 0 all individual protocol interrupt flags are equal to 0 1 at least one of the individual protocol interrupt flags is equal to 1 chif chi interrupt flag ? this flag is set if at least one of the individual chi error flags in the chi error flag register (fr_chierfr) is equal to 1. 0 all chi error flags are equal to 0 1 at least one chi error flag is equal to 1 wupif wakeup interrupt flag ? provides the same value as fr_gifer[wupif] fafbif receive fifo channel b al most full interrupt flag ? provides the same value as fr_gifer[fafbif] fafaif receive fifo channel a al most full interrupt flag ? provides the same value as fr_gifer[fafaif] rbif receive message buffer interrupt flag ? this flag is set if for at least one of the individual receive message buffers (fr_mbccsrn[mtd] = 0) the interrupt flag mbif in the corresponding message buffer configuration, control, status registers (fr_mbccsrn) is equal to 1. 0 none of the individual receive message buffers has the mbif flag asserted. 1 at least one individual receive message buffers has the mbif flag asserted. tbif transmit message buffer interrupt flag ? this flag is set if for at least one of the individual single or double transmit message buffers (fr_mbccsrn[ mtd] = 1) the interrupt flag mbif in the corresponding message buffer configuration, cont rol, status registers (fr_mbccsrn) is equal to 1. 0 none of the individual transmit message buffers has the mbif flag asserted. 1 at least one individual transmit message buffers has the mbif flag asserted. base + 0x003e write: disabled mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 timeout w rese t 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 figure 26-32. system memory access time-out register (fr_symator)
flexray communication controller 26-46 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.5.2.33 sync frame counter register (fr_sfcntr) this register provides the number of synchronization fram es that are used for cl ock synchronization in the last even and in the last odd numbere d communication cycle. this register is updated after the start of the nit and before 10 mt afte r offset correction start. note if the application has locked the even synchronization table at the end of the static segment of an even communicati on cycle, the cc will not update the fields sfevb and sfeva. if the application has locked the odd sy nchronization table at the end of the static segment of an odd communicati on cycle, the cc will not update the values sfodb and sfoda. table 26-37. fr_symator field descriptions field description timeout system memory access time-out ? this value is related to the maximum amount of time to finish a system bus access in order to ensure correct fr ame transmission and reception. for a detailed description see section 26.6.19.2, syst em bus access timeout . base + 0x0040 additional reset: run command 0123456789101112131415 r sfevb sfeva sfodb sfoda w rese t 0000000000000000 figure 26-33. sync frame counter register (fr_sfcntr) table 26-38. fr_sfcntr field descriptions field description sfevb sync frames channel b, even cycle ? protocol related variable: size of ( vssyncidlistb for even cycle) this field provides the size of the internal list of frame ids of received synchronization frames used for clock synchronization. sfevb sync frames channel a, even cycle ? protocol related va riable: size of ( vssyncidlista for even cycle) this field provides the size of the internal list of frame ids of received synchronization frames used for clock synchronization. sfodb sync frames channel b, odd cycle ? protocol related variable: size of ( vssyncidlistb for odd cycle) this field provides the size of the internal list of frame ids of received synchronization frames used for clock synchronization. sfoda sync frames channel a, odd cycle ? protocol related variable: size of ( vssyncidlista for odd cycle) this field provides the size of the internal list of frame ids of received synchronization frames used for clock synchronization.
flexray communication controller freescale semiconductor 26-47 pxs20 microcontroller reference manual, rev. 1 26.5.2.34 sync frame table offset register (fr_sftor) this register defines the flexray memory area related offset for sync frame tables. for more details, see section 26.6.12, sync frame id and sync frame deviation tables . 26.5.2.35 sync frame table configur ation, control, status register (fr_sftccsr) this register provides configurati on, control, and status information related to the generation and access of the clock sync id tables a nd clock sync measurement tables. for a detailed description, see section 26.6.12, sync frame id and sync frame deviation tables . base + 0x0042 write: poc:config 0123456789101112131415 r sft_offset[15:1] 0 w rese t 0000000000000000 figure 26-34. sync frame table offset register (fr_sftor) table 26-39. fr_sftor field description field description sft_offset sync frame table offset ? the offset of the sync frame tables in the flexray memory area. this offset is required to be 16-bit al igned. thus stf_offset[0] is always 0. base + 0x0044 write: normal mode 0123456789101112131415 r 0 0 cycnum elks olk s eval oval 0 0 sdv en sid en w elkt olk t opt rese t 0000000000000000 figure 26-35. sync frame table configuration, control, status register (fr_sftccsr)
flexray communication controller 26-48 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 table 26-40. fr_sftccsr field descriptions field description elkt even cycle tables lock/unlock trigger ? this trigger bit is used to lock and unlock the even cycle tables. 0no effect 1 triggers lock/unlock of the even cycle tables. olkt odd cycle tables lock/unlock trigger ? this trigger bit is used to lock and unlock the odd cycle tables. 0no effect 1 triggers lock/unlock of the odd cycle tables. cycnum cycle number ? this field provides the number of the cycle in which the currently locked table was recorded. if none or both tables are locked, this value is related to the even cycle table. elks even cycle tables lock status ? this status bit indicates whether the application has locked the even cycle tables. 0 application has not locked the even cycle tables. 1 application has locked the even cycle tables. olks odd cycle tables lock status ? this status bit indicates whether the application has locked the odd cycle tables. 0 application has not locked the odd cycle tables. 1 application has locked the odd cycle tables. eval even cycle tables valid ? this status bit indicates whether the sync frame id and sync frame deviation tables for the even cycle are valid. the cc clears this status bit when it starts updating the tables, and sets this bit when it has finished the table update. 0 tables are not valid (update is ongoing) 1 tables are valid (consistent). oval odd cycle tables valid ? this status bit indicates whether the sync frame id and sync frame deviation tables for the odd cycle are valid. the cc clears this status bit w hen it starts updating the tables, and sets this bit when it has finished the table update. 0 tables are not valid (update is ongoing) 1 tables are valid (consistent). opt one pair trigger ? this trigger bit controls whether the cc writes continuously or only one pair of sync frame tables into the flexray memory area. if this trigger is set to 1 while sdven or siden is set to 1, the cc writes only one pair of the enabled sync frame tables corresponding to the next even-odd-cycle pair into the flexray memory area. in this case, the cc clears the sdven or siden bits immediately. if this trigger is set to 0 while sdven or siden is set to 1, the cc writes continuously the enabled sync frame tables into the flexray memory area. 0 write continuously pairs of enabled sync frame tables into flexray memory area. 1 write only one pair of enabled sync frame tables into flexray memory area. sdven sync frame deviation table enable ? this bit controls the generation of the sync frame deviation tables. the application must set this bit to request the cc to write the sync frame deviation tables into the flexray memory area. 0 do not write sync frame deviation tables 1 write sync frame deviation tables into flexray memory area note: if sdven is set to 1, then siden must also be set to 1. siden sync frame id table enable ? this bit controls the generation of the sync frame id tables. the application must set this bit to 1 to request t he cc to write the sync frame id tables into the flexray memory area. 0 do not write sync frame id tables 1 write sync frame id tables into flexray memory area
flexray communication controller freescale semiconductor 26-49 pxs20 microcontroller reference manual, rev. 1 26.5.2.36 sync frame id rejectio n filter register (fr_sfidrfr) this register defines the s ync frame rejection filter id. the application must upda te this register outside of the static segment. if the applica tion updates this register in the static segment, it can appear that the cc accepts the sync frame in the current cycle. 26.5.2.37 sync frame id acceptance f ilter value register (fr_sfidafvr) this register defines the sync frame acceptanc e filter value. for details on filtering, see section 26.6.15, sync frame filtering . base + 0x0046 16-bit write access required write: normal mode 0123456789101112131415 r000000 synfrid w rese t 0000000000000000 figure 26-36. sync frame id rejection filter register (fr_sfidrfr) table 26-41. fr_sfidrfr field descriptions field description synfrid sync frame rejection id ? this field defines the frame id of a frame that must not be used for clock synchronization. for details see section 26.6.15.2, sync frame rejection filtering . base + 0x0048 write: poc:config 0123456789101112131415 r000000 fval w rese t 0000000000000000 figure 26-37. sync frame id acceptance filter value register (fr_sfidafvr) table 26-42. fr_sfidafvr field descriptions field description fval filter value ? this field defines the value for the sync frame acceptance filtering.
flexray communication controller 26-50 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.5.2.38 sync frame id acceptance f ilter mask register (fr_sfidafmr) this register defines the sync frame acceptance filter mas k. for details on filtering see section 26.6.15.1, sync frame acceptance filtering . 26.5.2.39 network management vector registers (fr_nmvr0?fr_nmvr5) each of these six registers holds one part of the network management vector. the length of the network management vector is configured in the network management vector length register (fr_nmvlr) . if fr_nmvlr is programmed with a value that is less than 12 bytes, the remaining bytes of the network management vector registers (fr_nmvr0?fr_nmvr5) , which are not used for the network management vector accum ulating, will remain 0. the nmvr provides accrued information over all recei ved nmvs in the last communication cycle. all nmvs received in one cycle are ored into the nmvr. the nmvr is updated at the end of the communication cycle. base + 0x004a write: poc:config 0123456789101112131415 r000000 fmsk w rese t 0000000000000000 figure 26-38. sync frame id acceptance filter mask register (fr_sfidafmr) table 26-43. fr_sfidafm r field descriptions field description fmsk filter mask ? this field defines the mask for the sync frame acceptance filtering. base + 0x004c (fr_nmvr0) base + 0x004e (fr_nmvr1) base + 0x0050 (fr_nmvr2) base + 0x0052 (fr_nmvr3) base + 0x0054 (fr_nmvr4) base + 0x0056 (fr_nmvr5) 0123456789101112131415 r nmvp[15:8] nmvp[7:0] w rese t 0000000000000000 figure 26-39. network management vector registers (fr_nmvr0?fr_nmvr5)
flexray communication controller freescale semiconductor 26-51 pxs20 microcontroller reference manual, rev. 1 26.5.2.40 network management vector length register (fr_nmvlr) this register defines the length of th e network management vector in bytes. table 26-44. nmvr[0:5] field descriptions field description nmvp network management vector part ? the mapping between the network management vector registers (fr_nmvr0?fr_nmvr5) and the receive message buffer payload bytes in nmv[0:11] is depicted in table 26-45 . table 26-45. mapping of nmvrn to the received payload bytes nmvn nmvrn register nmvn received payload fr_nmvr0[nmvp[15:8]] nmv0 fr_nmvr0[nmvp[7:0]] nmv1 fr_nmvr1[nmvp[15:8]] nmv2 fr_nmvr1[nmvp[7:0]] nmv3 ... fr_nmvr5[nmvp[15:8]] nmv10 fr_nmvr5[nmvp[7:0]] nmv11 base + 0x0058 write: poc:config 0123456789101112131415 r000000000000 nmvl w rese t 0000000000000000 figure 26-40. network management vector length register (fr_nmvlr) table 26-46. fr_nmvlr field descriptions field description nmvl network management vector length ? protocol related variable: gnetworkmanagementvectorlength this field defines the length of the network management vector in bytes. legal values are between 0 and 12.
flexray communication controller 26-52 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.5.2.41 timer configuration a nd control register (fr_ticcr) this register is used to configure and control the two timers t1 and t2. for timer details, see section 26.6.17, timer support . the timer t1 is an absolute timer. the timer t2 can be configured as an absolute or relative timer. base + 0x005a write: t2_cfg: poc:config t2_rep, t1_rep, t1sp, t2sp, t1tr, t2tr: normal mode 0123456789101112131415 r0 0 t2_ cfg t2_ rep 000t2st000 t1_ rep 000t1st w t2sp t2tr t1sp t1tr reset0000000000000000 figure 26-41. timer configuration and control register (fr_ticcr) table 26-47. fr_ticcr field descriptions field description t2_cfg timer t2 configuration ? this bit configures the timebase mode of timer t2. 0 t2 is absolute timer. 1 t2 is relative timer. t2_rep timer t2 repetitive mode ? this bit configures the repetition mode of timer t2. 0 t2 is non repetitive 1 t2 is repetitive t2sp timer t2 stop ? this trigger bit is used to stop timer t2. 0 no effect 1 stop timer t2 t2tr timer t2 trigger ? this trigger bit is used to start timer t2. 0 no effect 1 start timer t2 t2st timer t2 state ? this status bit provides the current state of timer t2. 0 timer t2 is idle 1 timer t2 is running t1_rep timer t1 repetitive mode ? this bit configures the repetition mode of timer t1. 0 t1 is non repetitive 1 t1 is repetitive t1sp timer t1 stop ? this trigger bit is used to stop timer t1. 0 no effect 1 stop timer t1 t1tr timer t1 trigger ? this trigger bit is used to start timer t1. 0 no effect 1 start timer t1 t1st timer t1 state ? this status bit provides the current state of timer t1. 0 timer t1 is idle 1 timer t1 is running
flexray communication controller freescale semiconductor 26-53 pxs20 microcontroller reference manual, rev. 1 note both timers are deactivated immediatel y when the protocol enters a state different from poc:normal active or poc:normal passive . 26.5.2.42 timer 1 cycle set register (fr_ti1cysr) this register defines the cycle filter value and the cycle filter mask for timer t1. for a detailed description of timer t1, refer to section 26.6.17.1, absolute timer t1 . note if the application modifies the value in this register while the timer is running, the change becomes effective immediately and timer t1 will expire according to the changed value. 26.5.2.43 timer 1 macrotick offset register (fr_ti1mtor) this register holds the macrotick offs et value for timer t1. for a detailed description of timer t1, refer to section 26.6.17.1, absolute timer t1 . base + 0x005c write: anytime 0123456789101112131415 r0 0 t1_cyc_val 00 t1_cyc_msk w rese t 0000000000000000 figure 26-42. timer 1 cycle set register (fr_ti1cysr) table 26-48. fr_ti1cysr field descriptions field description t1_cyc_val timer t1 cycle filter value ? this field defines the cycl e filter value for timer t1. t1_cyc_msk timer t1 cycle filter mask ? this field defines the cycle filter mask for timer t1. base + 0x005e write: anytime 0123456789101112131415 r0 0 t1_mtoffset w rese t 0000000000000000 figure 26-43. timer 1 macrotick offset register (fr_ti1mtor)
flexray communication controller 26-54 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 note if the application modifies the value in this register while the timer is running, the change becomes effective immediately and timer t1 will expire according to the changed value. 26.5.2.44 timer 2 configuration register 0 (fr_ti2cr0) the content of this register depends on the value of the t2_cfg bit in the timer configuration and control register (fr_ticcr) . for a detailed description of timer t2, refer to section 26.6.17.2, absolute / relative timer t2 . note if timer t2 is configured as an absolute timer and the appl ication modifies the values in this register while th e timer is running, the change becomes effective immediately and timer t2 will expire according to the changed values. table 26-49. fr_ti1mtor field descriptions field description t1_mtoffset timer 1 macrotick offset ? this field defines the macrotick offset value for timer 1. base + 0x0060 write: anytime 0123456789101112131415 r r* t2_cyc_val r* t2_cyc_msk w r t2_mtcnt[31:16] w rese t 0000000000000000 figure 26-44. timer 2 configur ation register 0 (fr_ti2cr0) table 26-50. fr_ti2cr0 field descriptions field description fields for absolute timer t2 (fr_ticcr[t2_cfg] = 0) t2_cyc_val timer t2 cycle filter value ? this field defines the cycl e filter value for timer t2. t2_cyc_msk timer t2 cycle filter mask ? this field defines the cycle filter mask for timer t2. fields for relative time r t2 (fr_ticcr[t2_cfg = 1) t2_mtcnt[31:16] timer t2 macrotick high word ? this field defines the high word of the macrotick count for timer t2.
flexray communication controller freescale semiconductor 26-55 pxs20 microcontroller reference manual, rev. 1 if timer t2 is configured as a relative timer and the app lication changes the values in this register while the timer is running, the change becomes effective when the timer has expired according to the old values. 26.5.2.45 timer 2 configuration register 1 (fr_ti2cr1) the content of this register depends on the value of the t2_cfg bit in the timer configuration and control register (fr_ticcr) . for a detailed description of timer t2, refer to section 26.6.17.2, absolute / relative timer t2 . note if timer t2 is configured as an absolute timer and the appl ication modifies the values in this register while th e timer is running, the change becomes effective immediately and th e timer t2 will expire according to the changed values. if timer t2 is configured as a relative timer and the app lication changes the values in this register while the timer is running, the change becomes effective when the timer has expired according to the old values. base + 0x0062 write: anytime 0123456789101112131415 r r* t2_mtoffset w r t2_mtcnt[15:0] w rese t 0000000000000000 figure 26-45. timer 2 configur ation register 1 (fr_ti2cr1) table 26-51. fr_ti2cr1 field descriptions field description fields for absolute timer t2 (fr_ticcr[t2_cfg] = 0) t2_mtoffset timer t2 macrotick offset ? this field holds the macrotick offset value for timer t2. fields for relative timer t2 (fr_ticcr[t2_cfg] = 1) t2_mtcnt[15:0] timer t2 macrotick low word ? this field defines the low word of the macrotick value for timer t2.
flexray communication controller 26-56 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.5.2.46 slot status selection register (fr_sssr) this register is used to access the four internal non memory-mapped slot st atus selection registers fr_sssr0 to fr_sssr3. each intern al registers selects a slot, or symbol window/nit, whose status vector will be saved in the corresponding slot status registers (fr_ssr0?fr_ssr7) according to table 26-53 . for a detailed description of slot status monitoring, refer to section 26.6.18, slot status monitoring . base + 0x0064 16-bit write access required write: anytime 0123456789101112131415 r0 0 sel 0 slotnumber wwmd rese t 0000000000000000 figure 26-46. slot status se lection register (fr_sssr) table 26-52. fr_sssr field descriptions field description wmd write mode ? this control bit defines the write mode of this register. 0 write to all fields in this register on write access. 1 write to sel field only on write access. sel selector ? this field selects one of the four internal slot status selection registers for access. 00 select fr_sssr0. 01 select fr_sssr1. 10 select fr_sssr2. 11 select fr_sssr3. slotnumber slot number ? this field specifies the number of the slot whose status will be saved in the corresponding slot status registers. note: if this value is set to 0, the related slot stat us register provides th e status of the symbol window after the nit start, an d provides the status of the nit after the cycle start. table 26-53. mapping between fr_sssrn and fr_ssrn internal slot status selection register write the slot status of the sl ot selected by fr_sssrn for each even communication cycle odd communication cycle for channel b to for channel a to for channel b to for channel a to fr_sssr0 fr_ssr0[15:8] fr_ssr0[ 7:0] fr_ssr1[15:8] fr_ssr1[7:0] fr_sssr1 fr_ssr2[15:8] fr_ssr2[ 7:0] fr_ssr3[15:8] fr_ssr3[7:0] fr_sssr2 fr_ssr4[15:8] fr_ssr4[ 7:0] fr_ssr5[15:8] fr_ssr5[7:0] fr_sssr3 fr_ssr6[15:8] fr_ssr6[ 7:0] fr_ssr7[15:8] fr_ssr7[7:0]
flexray communication controller freescale semiconductor 26-57 pxs20 microcontroller reference manual, rev. 1 26.5.2.47 slot status counter condition register (fr_ssccr) this register is used to access and program the f our internal non-memory mapped slot status counter condition registers fr_ssccr0 to fr_ ssccr3. each of these four intern al slot status counter condition registers defines the mode and the conditions for incrementing the counter in the corresponding slot status counter registers (fr_sscr0?fr_sscr3) . the corresponden ce is given in table 26-55 . for a detailed description of slot stat us counters, refer to section 26.6.18.4, slot status counter registers . base + 0x0066 16-bit write access required write: anytime 0123456789101112131415 r0 0 sel 0 cntcfg mcy vfr syf nuf suf statusmask[3:0] wwmd rese t 0000000000000000 figure 26-47. slot status counter condition register (fr_ssccr) table 26-54. fr_ssccr field descriptions field description wmd write mode ? this control bit defines the write mode of this register. 0 write to all fields in this register on write access. 1 write to sel field only on write access. sel selector ? this field selects one of the four internal slot counter condition registers for access. 00 select fr_ssccr0. 01 select fr_ssccr1. 10 select fr_ssccr2. 11 select fr_ssccr3. cntcfg counter configuration ? these bit field controls the channel re lated incrementing of the slot status counter. 00 increment by 1 if condition is fulfilled on channel a. 01 increment by 1 if condition is fulfilled on channel b. 10 increment by 1 if condition is fulfilled on at least one channel. 11 increment by 2 if condition is fulfilled on both channels channel. increment by 1 if condition is fulfilled on only one channel. mcy multi cycle selection ? this bit defines whether the slot st atus counter accumulates over multiple communication cycles or provides information for the previ ous communication cycle only. 0 the slot status counter prov ides information for the previous communication cycle only. 1 the slot status counter accumulate s over multiple communication cycles. vfr valid frame restriction ? this bit is used to restrict th e counter to received valid frames. 0 the counter is not restricted to valid frames only. 1 the counter is restricted to valid frames only.
flexray communication controller 26-58 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.5.2.48 slot status registers (fr_ssr0?fr_ssr7) syf sync frame restriction ? this bit is used to restrict the counter to received frames with the sync frame indicator bit set to 1. 0 the counter is not restricted with re spect to the sync frame indicator bit. 1 the counter is restricted to frames with the sync frame indicator bit set to 1. nuf null frame restriction ? this bit is used to restrict the counter to received frames with the null frame indicator bit set to 0. 0 the counter is not restricted with respect to the null frame indicator bit. 1 the counter is restricted to frames wit h the null frame indicator bit set to 0. suf startup frame restriction ? this bit is used to restrict the counter to received frames with the startup frame indicator bit set to 1. 0 the counter is not restricted with respect to the startup frame indicator bit. 1 the counter is restricted to received frames with the startup frame indicator bit set to 1. status mask[3:0] slot status mask ? this bit field is used to enable the coun ter with respect to the four slot status error indica tor bits. statusmask[3] ? this bit enables the counting for slots with the syntax error indicator bit set to 1. statusmask[2] ? this bit enables the counting for slots wit h the content error indicator bit set to 1. statusmask[1] ? this bit enables the counting for slots with the boundary violation indicator bit set to 1. statusmask[0] ? this bit enables the counting for slots wi th the transmission conflict indicator bit set to 1. table 26-55. mapping between internal fr_ssccrn and fr_sscrn condition register condition defined for register fr_ssccr0 fr_sscr0 fr_ssccr1 fr_sscr1 fr_ssccr2 fr_sscr2 fr_ssccr3 fr_sscr3 base + 0x0068 (fr_ssr0) base + 0x006a (fr_ssr1) base + 0x006c (fr_ssr2) base + 0x006e (fr_ssr3) base + 0x0070 (fr_ssr4) base + 0x0072 (fr_ssr5) base + 0x0074 (fr_ssr6) base + 0x0076 (fr_ssr7) 0123456789101112131415 r vfb syb nfb sub seb ceb bvb tcb vfa sya nfa sua sea cea bva tca w reset0000000000000000 figure 26-48. slot status registers (fr_ssr0?fr_ssr7) table 26-54. fr_ssccr field descriptions field description
flexray communication controller freescale semiconductor 26-59 pxs20 microcontroller reference manual, rev. 1 each of these eight register s holds the status vector of the slot sp ecified in the corresponding internal slot status selection register, whic h can be programmed using the slot status selection register (fr_sssr) . each register is updated after the end of the corresponding slot as shown in figure 26-158 . the register bits are directly related to the protocol variables and described in more detail in section 26.6.18, slot status monitoring . note slot status information of the message buffers should not be used when any one of the the error flag s fr_chierfr[sbcf_ef] or fr_chierfr[ilsa_ef] is set. table 26-56. fr_ssr0?fr_ssr7 field descriptions field description vfb valid frame on channel b ? protocol related variable: vss!validframe channel b 0 vss!validframe = 0 1 vss!validframe = 1 syb sync frame indicator channel b ? protocol related variable: vrf!header!syfindicator channel b 0 vrf!header!syfindicator = 0 1 vrf!header!syfindicator = 1 nfb null frame indicator channel b ? protocol related variable: vrf!header!nfindicator channel b 0 vrf!header!nfindicator = 0 1 vrf!header!nfindicator = 1 sub startup frame indicator channel b ? protocol related variable: vrf!header!sufindicator channel b 0 vrf!header!sufindicator = 0 1 vrf!header!sufindicator = 1 seb syntax error on channel b ? protocol related variable: vss!syntaxerror channel b 0 vss!syntaxerror = 0 1 vss!syntaxerror = 1 ceb content error on channel b ? protocol related variable: vss!contenterror channel b 0 vss!contenterror = 0 1 vss!contenterror = 1 bvb boundary violation on channel b ? protocol related variable: vss!bviolation channel b 0 vss!bviolation = 0 1 vss!bviolation = 1 tcb transmission conflict on channel b ? protocol related variable: vss!txconflict channel b 0 vss!txconflict = 0 1 vss!txconflict = 1 vfa valid frame on channel a ? protocol related variable: vss!validframe channel a 0 vss!validframe = 0 1 vss!validframe = 1 sya sync frame indicator channel a ? protocol related variable: vrf!header!syfindicator channel a 0 vrf!header!syfindicator = 0 1 vrf!header!syfindicator = 1 nfa null frame indicator channel a ? protocol related variable: vrf!header!nfindicator channel a 0 vrf!header!nfindicator = 0 1 vrf!header!nfindicator = 1
flexray communication controller 26-60 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.5.2.49 slot status counter registers (fr_sscr0?fr_sscr3) each of these four registers provide s the slot status counter value for the previous communication cycle(s) and is updated at the cycle start. th e provided value depends on the contro l bits and fields in the related internal slot status counter c ondition register fr_ssccrn, which can be programmed by using the slot status counter conditi on register (fr_ssccr) . for more details, see section 26.6.18.4, slot status counter registers . note if the counter has reached its ma ximum value 0xffff and is in the multicycle mode, i.e. fr_ssccrn[mcy] = 1, the counter is not reset to 0x0000. the application can reset the counter by clearing the fr_ssccrn[mcy] bit and waiting for th e next cycle start, when the cc clears the counter. subseque ntly, the counter can be set into the multicycle mode again. sua startup frame indicator channel a ? protocol related variable: vrf!header!sufindicator channel a 0 vrf!header!sufindicator = 0 1 vrf!header!sufindicator = 1 sea syntax error on channel a ? protocol related variable: vss!syntaxerror channel a 0 vss!syntaxerror = 0 1 vss!syntaxerror = 1 cea content error on channel a ? protocol related variable: vss!contenterror channel a 0 vss!contenterror = 0 1 vss!contenterror = 1 bva boundary violation on channel a ? protocol related variable: vss!bviolation channel a 0 vss!bviolation = 0 1 vss!bviolation = 1 tca transmission conflict on channel a ? protocol related variable: vss!txconflict channel a 0 vss!txconflict = 0 1 vss!txconflict = 1 base + 0x0078 (fr_sscr0) base + 0x007a (fr_sscr1) base + 0x007c (fr_sscr2) base + 0x007e (fr_sscr3) additional reset: run command 0123456789101112131415 r slotstatuscnt w rese t 0000000000000000 figure 26-49. slot status counter registers (fr_sscr0?fr_sscr3) table 26-56. fr_ssr0?fr_ssr7 field descriptions (continued) field description
flexray communication controller freescale semiconductor 26-61 pxs20 microcontroller reference manual, rev. 1 26.5.2.50 mts a configuration register (fr_mtsacfr) this register controls the transmission of the me dia access test symbol mts on channel a. for more details, see section 26.6.13, mts generation . 26.5.2.51 mts b configurat ion register (mtsbcfr) this register controls the transmission of the me dia access test symbol mts on channel b. for more details, see section 26.6.13, mts generation . table 26-57. fr_sscr0?fr_sscr3 field descriptions field description slotstatuscnt slot status counter ? this field provides the current value of the slot status counter. base + 0x0080 write: mte: anytime cyccntmsk,cyccntval: poc:config 0123456789101112131415 r mte 0 cyccntmsk 00 cyccntval w rese t 0000000000000000 figure 26-50. mts a configuration register (fr_mtsacfr) table 26-58. fr_mtsacfr field descriptions field description mte media access test symbol transmission enable ? this control bit is used to enable and disable the transmission of the media access test symbol in the selected set of cycles. 0 mts transmission disabled 1 mts transmission enabled cyccntmsk cycle counter mask ? this field provides the filter mask for the mts cycle count filter. cyccntval cycle counter value ? th is field provides the filter valu e for the mts cycle count filter. base + 0x0082 write: mte: anytime cyccntmsk,cyccntval: poc:config 0123456789101112131415 r mte 0 cyccntmsk 00 cyccntval w rese t 0000000000000000 figure 26-51. mts b configur ation register (mtsbcfr)
flexray communication controller 26-62 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.5.2.52 receive shadow buffer index register (fr_rsbir) this register is used to provide and retrieve the indices of the message buffer header fields currently associated with the receive shadow buffers. for more details on the receive shadow buffer concept, refer to section 26.6.6.3.5, receive shadow buffers concept . table 26-59. mtsbcfr field descriptions field description mte media access test symbol transmission enable ? this control bit is used to enable and disable the transmission of the media access test symbol in the selected set of cycles. 0 mts transmission disabled 1 mts transmission enabled cyccntmsk cycle counter mask ? this field provides the filter mask for t he mts cycle count filter. cyccntval cycle counter value ? this field provides the filter value for t he mts cycle count filter. base + 0x0084 16-bit write access required write: wmd, sel: any time rsbidx: poc:config 0123456789101112131415 r0 0 sel 00000 rsbidx wwmd reset0000000000000000 figure 26-52. receive shadow buffer index register (fr_rsbir) table 26-60. fr_rsbir field descriptions field description wmd write mode ? this bit controls the write mode for this register. 0 update sel and rsbidx field on register write 1 update only sel field on register write sel selector ? this field is used to select the internal receive shadow buffer index register for access. 00 fr_rsbir_a1 ? receive shadow buffer index register for channel a, segment 1 01 fr_rsbir_a2 ? receive shadow buffer index register for channel a, segment 2 10 fr_rsbir_b1 ? receive shadow buffer index register for channel b, segment 1 11 fr_rsbir_b2 ? receive shadow buffer index register for channel b, segment 2 rsbidx receive shadow buffer index ? this field contains the current index of the message buffer header field of the receive shadow message buffer selected by the sel field. the cc uses this index to determine the physical location of the shadow buffer header field in the flexray memory area. the cc will update this field during receive operation.the application provides initial message buffer header index value in the configuration phase. cc: updates the message buffer head er index after successful reception. application: provides initial message buffer header index.
flexray communication controller freescale semiconductor 26-63 pxs20 microcontroller reference manual, rev. 1 26.5.2.53 receive fifo system me mory base address register (fr_rfsymbadr) these registers define the system me mory base address for the receive fi fo if the fifo address mode bit fr_mcr[fam] is set to 1. the system memory base a ddress is used by the bmif to calculate the physical memory address for system me mory accesses for the fifos. 26.5.2.54 receive fifo periodi c timer register (fr_rfptr) this register holds periodic timer duration for the periodic fifo timer. the periodic timer applies to both fifos (see section 26.6.9.3, fifo periodic timer ). base + 0x00e8 write: disabled mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r smba[31:16] w rese t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 26-53. receive fifo system memory ba se address high regi ster (fr_rfsymbadhr) base + 0x00ea write: disabled mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r smba[15:4] 0 0 0 0 w rese t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 26-54. receive fifo system memory base address low register (fr_rfsymbadlr) table 26-61. fr_rfsymbadr field descriptions field description smba system memory base address ? this is the value of the syst em memory base address for the receive fifo if the fifo address mode bit fr_mcr[fam] is set to 1. it is defines as a byte address. base + 0x00ec write: poc:config 0123456789101112131415 r0 0 ptd w rese t 0000000000000000 figure 26-55. receive fifo period ic timer register (fr_rfptr)
flexray communication controller 26-64 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.5.2.55 receive fifo wa termark and selection register (fr_rfwmsr) this register is used to ? select a receiver fifo for subsequent programming access through the receiver fifo configuration registers summarized in table 26-63 . ? to define the watermark for the selected fifo. table 26-62. fr_rfptr field descriptions field description ptd periodic timer duration ? this value defines the periodic timer duration in terms of macroticks. 0000 timer stays expired 3fff timer never expires other timer expires after specified number of macr oticks, expires and is re started at each cycle start base + 0x0086 write: wm a /wm b : poc:config, sel: anytime 0123456789101112131415 r wm a/ /wm b 0000000 sel w rese t 0000000000000000 figure 26-56. receive fifo watermark and selection register (fr_rfwmsr) table 26-63. sel controlled receiver fifo registers register receive fifo start index register (fr_rfsir) receive fifo depth and size register (rfdsr) receive fifo message id acceptance fi lter value register (fr_rfmidafvr) receive fifo message id acceptance filter mask register (fr_rfmidafmr) receive fifo frame id rejection f ilter value register (fr_rffidrfvr) receive fifo frame id rejection f ilter mask register (fr_rffidrfmr) receive fifo range filter conf iguration regist er (fr_rfrfcfr) receive fifo range filter control register (fr_rfrfctr) table 26-64. fr_rfwmsr field descriptions field description wm a wm b watermark ? this field defines the watermark value for the selected fifo. this value is used to control the generation of the almost full interrupt flags. sel select ? this control bit selects the receiver fifo for subsequent programming. 0 receiver fifo for channel a selected 1 receiver fifo for channel b selected
flexray communication controller freescale semiconductor 26-65 pxs20 microcontroller reference manual, rev. 1 26.5.2.56 receive fifo start index register (fr_rfsir) this register defines the message buffer header index of the firs t message buffer of the selected fifo. 26.5.2.57 receive fifo depth and size register (rfdsr) this register defines the st ructure of the selected fifo, i.e. the numbe r of entries and the size of each entry. base + 0x0088 write: poc:config 0123456789101112131415 r000000 sidx a /sidx b w rese t 0000000000000000 figure 26-57. receive fifo star t index register (fr_rfsir) table 26-65. fr_rfsir field descriptions field description sidx a sidx b start index ? this field defines the number of the mess age buffer header field of the first message buffer of the selected fifo. the cc uses the value of the sidx field to determine the physical location of the receiver fifo?s first message buffer header field. base + 0x008a write: poc:config 0123456789101112131415 r fifo_depth a /fifo_depth b 0 entry_size a /entry_size b w rese t 0000000000000000 figure 26-58. receive fifo dept h and size register (rfdsr) table 26-66. rfdsr field descriptions field description fifo_depth a fifo_depth b fifo depth ? this field defines the depth of the se lected fifo, i.e. the number of entries. entry_size a entry_size b entry size ? this field defines the size of the frame dat a sections for the selected fifo in 2 byte entities.
flexray communication controller 26-66 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.5.2.58 receive fifo a read index register (fr_rfarir) this register provides the message buffer header in dex of the next available fifo a entry that the application can read. note if the fifo is empty, the rdidx fiel d points to an physical message buffer with invalid content. 26.5.2.59 receive fifo b read index register (fr_rfbrir) this register provides the message buffer header in dex of the next available fifo b entry that the application can read. base + 0x008c 0123456789101112131415 r 0 0 0 0 0 0 rdidx w rese t 0000000000000000 figure 26-59. receive fifo a read index register (fr_rfarir) table 26-67. fr_rfarir field descriptions field description rdidx read index ? this field provides the message buffer header index of the next available fifo message buffer that the application can read. if the old style fifo mode is configured (fr_mcr[ fimd]=0), the cc updates this index by 1 entry, when the application writes to the fafaif flag in the global interrupt flag and enable register (fr_gifer) . if the new style fifo mode is configured (fr_ mcr[fimd]=1), the cc updat es this index by pca entries, when the application writes to the receive fifo fill level and pop count register (fr_rfflpcr) . base + 0x008e 0123456789101112131415 r 0 0 0 0 0 0 rdidx w rese t 0000000000000000 figure 26-60. receive fifo b r ead index register (fr_rfbrir)
flexray communication controller freescale semiconductor 26-67 pxs20 microcontroller reference manual, rev. 1 note if the fifo is empty, the rdidx fiel d points to an physical message buffer with invalid content. 26.5.2.60 receive fifo f ill level and pop count register (fr_rfflpcr) this register provides the current fi ll level of the two recei ver fifos and is used to pop a number of entries from the fifos. note if the pop count value pca/pcb is greater than the current fifo fill level flb/fla, than the fifo is empty afte r the update. no notification is given that not the required number of entries was removed. table 26-68. fr_rfbrir field descriptions field description rdidx read index ? this field provides the message buffer header index of the next available fifo message buffer that the application can read. base + 0x00ee 0123456789101112131415 rflb fla wpcb pca rese t 0000000000000000 figure 26-61. receive fifo fill level and pop count register (fr_rfflpcr) table 26-69. fr_rfflpcr field descriptions field description flb fill level fifo b ? this field provides the current number of entries in the fifo b. fla fill level fifo a ? this field provides the current number of entries in the fifo a. pcb pop count fifo b ? this field defines the number of entries to be removed from fifo b. pca pop count fifo a ? this field defines the number of entries to be removed from fifo a.
flexray communication controller 26-68 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.5.2.61 receive fifo m essage id acceptance filter value register (fr_rfmidafvr) this register defines the fi lter value for the message id acceptance filter of the selected fifo. for details on message id filtering see section 26.6.9.9, fifo filtering . 26.5.2.62 receive fifo m essage id acceptance filter mask register (fr_rfmidafmr) this register defines the filter mask for the message id acceptance filter of the selected fifo. for details on message id filtering see section 26.6.9.9, fifo filtering . base + 0x0090 write: poc:config 0123456789101112131415 r midafval a /midafval b w rese t 0000000000000000 figure 26-62. receive fifo message id acceptance filter value register (fr_rfmidafvr) table 26-70. fr_rfmidafvr field descriptions field description midafval a midafval b message id acceptance filter value ? filter value for the message id acceptance filter. base + 0x0092 write: poc:config 0123456789101112131415 r midafmsk a /midafmsk b w rese t 0000000000000000 figure 26-63. receive fifo message id acceptance filter mask register (fr_rfmidafmr) table 26-71. fr_rfmidafmr field descriptions field description midafmsk a midafmsk b message id acceptance filter mask ? filter mask for the mess age id acceptance filter.
flexray communication controller freescale semiconductor 26-69 pxs20 microcontroller reference manual, rev. 1 26.5.2.63 receive fifo frame id rejection filter value register (fr_rffidrfvr) this register defines the fi lter value for the frame id rejection filter of the se lected fifo. for details on frame id filtering see section 26.6.9.9, fifo filtering . 26.5.2.64 receive fifo frame id rejection filter mask register (fr_rffidrfmr) this register defines the filter mask for the frame id rejection filter of the selected fifo. for details on frame id filtering see section 26.6.9.9, fifo filtering . base + 0x0094 write: poc:config 0123456789101112131415 r00000 fidrfval a /fidrfval b w rese t 0000000000000000 figure 26-64. receive fifo frame id reject ion filter value register (fr_rffidrfvr) table 26-72. fr_rffidrfvr field descriptions field description fidrfval a fidrfval b frame id rejection filter value ? filter value for the frame id rejection filter. base + 0x0096 write: poc:config 0123456789101112131415 r00000 fidrfmsk a /fidrfmsk b w rese t 0000000000000000 figure 26-65. receive fifo frame id rejection filter mask register (fr_rffidrfmr) table 26-73. fr_rffidrfmr field descriptions field description fidrfmsk frame id rejection filter mask ? filter mask for the frame id rejection filter.
flexray communication controller 26-70 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.5.2.65 receive fifo range filter configuration register (fr_rfrfcfr) this register provides access to the four internal fram e id range filter boundary registers of the selected fifo. for details on frame id range filter see section 26.6.9.9, fifo filtering . 26.5.2.66 receive fifo range filter control regist er (fr_rfrfctr) this register is used to enable a nd disable each frame id range filter and to define whether it is running as acceptance or rejection filter. base + 0x0098 16-bit write access required write: wmd, ibd, sel: any time sid: poc:config 0123456789101112131415 r0 ibd sel 0 sid a /sid b wwmd rese t 0000000000000000 figure 26-66. receive fifo range filter configuration regi ster (fr_rfrfcfr) table 26-74. fr_rfrfcfr field descriptions field description wmd write mode ? this control bit defines the write mode of this register. 0 write to all fields in this register on write access. 1 write to sel and ibd field only on write access. ibd interval boundary ? this control bit selects the interval boundary to be programmed with the sid value. 0 program lower interval boundary 1 program upper interval boundary sel filter selector ? this control field selects the frame id range filter to be accessed. 00 select frame id range filter 0. 01 select frame id range filter 1. 10 select frame id range filter 2. 11 select frame id range filter 3. sid a sid b slot id ? defines the ibd-selected frame id boundary value for the sel-selected range filter. base + 0x009a write: anytime 0123456789101112131415 r0000 f3md f2md f1md f0md 0000 f3en f2en f1en f0en w reset0000000000000000 figure 26-67. receive fifo range filter control register (fr_rfrfctr)
flexray communication controller freescale semiconductor 26-71 pxs20 microcontroller reference manual, rev. 1 26.5.2.67 last dynamic transmit slot channel a register (fr_ldtxslar) this register provides the number of the last transmission slot in the dynamic segment for channel a. this register is updated after the end of the dynamic segment and before th e start of the next communication cycle. table 26-75. fr_rfrfctr field descriptions field description f3md range filter 3 mode ? this control bit defines the filter mode of the frame id range filter 3. 0 range filter 3 runs as acceptance filter 1 range filter 3 runs as rejection filter f2md range filter 2 mode ? this control bit defines the filter mode of the frame id range filter 2. 0 range filter 2 runs as acceptance filter 1 range filter 2 runs as rejection filter f1md range filter 1 mode ? this control bit defines the filter mode of the frame id range filter 1. 0 range filter 1 runs as acceptance filter 1 range filter 1 runs as rejection filter f0md range filter 0 mode ? this control bit defines the filter mode of the frame id range filter 0. 0 range filter 0 runs as acceptance filter 1 range filter 0 runs as rejection filter f3en range filter 3 enable ? this control bit is used to enable and disable the frame id range filter 3. 0 range filter 3 disabled 1 range filter 3 enabled f2en range filter 2 enable ? this control bit is used to enable and disable the frame id range filter 2. 0 range filter 2 disabled 1 range filter 2 enabled f1en range filter 1 enable ? this control bit is used to enable and disable the frame id range filter 1. 0 range filter 1 disabled 1 range filter 1 enabled f0en range filter 0 enable ? this control bit is used to enable and disable the frame id range filter 0. 0 range filter 0 disabled 1 range filter 0 enabled base + 0x009c 0123456789101112131415 r 0 0 0 0 0 lastdyntxslota w rese t 0000000000000000 figure 26-68. last dynamic transmit slot channel a register (fr_ldtxslar)
flexray communication controller 26-72 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.5.2.68 last dynamic transmit slot channel b register (fr_ldtxslbr) this register provides the number of the last transmission slot in the dy namic segment for channel b. this register is updated after the end of the dynamic segment and before th e start of the next communication cycle. 26.5.2.69 protocol configuration registers the following configurati on registers provide the necessary confi guration information to the protocol engine. the individual values in the registers are described in table 26-78 . for more details about the flexray related configuration parameters and the allowed parameter ranges, see flexray communications system protocol specification, version 2.1 rev a . table 26-76. fr_ldtxslar field descriptions field description lastdyntx slota last dynamic transmi ssion slot channel a ? protocol related variable: zlastdyntxslot channel a number of the last transmission slot in the dy namic segment for channel a. if no frame was transmitted during the dynamic segment on channel a, the value of this field is set to 0. base + 0x009e 0123456789101112131415 r 0 0 0 0 0 lastdyntxslotb w rese t 0000000000000000 figure 26-69. last dynamic transmit slot channel b register (fr_ldtxslbr) table 26-77. fr_ldtxslbr field descriptions field description lastdyntx slotb last dynamic transmi ssion slot channel b ? protocol related variable: zlastdyntxslot channel b number of the last transmission slot in the dynamic segment for channel b. if no frame was transmitted during the dynamic segment on channel b the value of this field is set to 0. table 26-78. protocol configuration register fields name description 1 min max unit fr_pc r coldstart_attempts gc oldstartattempts number 3 action_point_offset gdactionpointoffset - 1 mt 0 cas_rx_low_max gdcasrxlowmax - 1 gdbit 4 dynamic_slot_idle_phase gddynamicslotidlephase minislot 28 minislot_action_point_offset gdminislotactionpointoffset - 1 mt 3
flexray communication controller freescale semiconductor 26-73 pxs20 microcontroller reference manual, rev. 1 minislot_after_action_point gdminislot - gdminislotactionpointoffset - 1 mt 2 static_slot_length gdstaticslot mt 0 static_slot_after_action_point gdstaticslot - gdactionpointoffset - 1 mt 13 symbol_window_exists gdsymbolwindow !=0 0 1 bool 9 symbol_window_after_action_point gdsymbolwindow - gdactionpointoffset - 1 mt 6 tss_transmitter gdtsstransmitter gdbit 5 wakeup_symbol_rx_idle gdwakeupsymbolrxidle gdbit 5 wakeup_symbol_rx_low gdwakeupsymbolrxlow gdbit 3 wakeup_symbol_rx_window gdwakeupsymbolrxwindow gdbit 4 wakeup_symbol_tx_idle gdwakeupsymboltxidle gdbit 8 wakeup_symbol_tx_low gdwakeupsymboltxlow gdbit 5 noise_listen_timeout ( glistennoise * pdlistentimeout ) - 1 ? t 16/17 macro_initial_offset_a p macroinitialoffset[a] mt 6 macro_initial_offset_b p macroinitialoffset[b] mt 16 macro_per_cycle gmacropercycle mt 10 macro_after_first_static_slot gmacropercycle - gdstaticslot mt 1 macro_after_offset_correction gmacropercycle - goffsetcorrectionstart mt 28 max_without_clock_correction_fatal gmaxwithoutclockcorrectionfatal cyclepair s 8 max_without_clock_correction_pass ive gmaxwithoutclockcorrectionpassive cyclepair s 8 minislot_exists gnumberofminislots !=0 0 1 bool 9 minislots_max gnumberofminislots - 1 minislot 29 number_of_static_slots gnumberofstaticslots static slot 2 offset_correction_start goffsetcorrectionstart mt 11 payload_length_static gpayloadlengthstatic 2-bytes 19 max_payload_length_dynamic ppayloadlengthdynmax 2-bytes 24 first_minislot_action_point_offset max( gdactionpointoffset , gdminislotactionpointoffset ) - 1 mt 13 allow_halt_due_to_clock pallowhaltduetoclock bool 26 allow_passive_to_active pallowpassivetoactive cyclepair s 12 cluster_drift_damping pclusterdriftdamping ? t24 comp_accepted_startup_range_a pdacceptedstartuprange - pdelaycompensation[a] ? t22 comp_accepted_startup_range_b pdacceptedstartuprange - pdelaycompensation[b] ? t26 listen_timeout pdlistentimeout - 1 ? t 14/15 table 26-78. protocol configurati on register fields (continued) name description 1 min max unit fr_pc r
flexray communication controller 26-74 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 key_slot_id pkeyslotid number 18 key_slot_used_for_startup pkeyslotusedforstartup bool 11 key_slot_used_for_sync pkeyslotusedforsync bool 11 latest_tx gnumberofminislots - platesttx minislot 21 sync_node_max gsyncnodemax number 30 micro_initial_offset_a pmicroinitialoffset[a] ? t20 micro_initial_offset_b pmicroinitialoffset[b] ? t20 micro_per_cycle pmicropercycle ? t 22/23 micro_per_cycle_min pmicropercycle - pdmaxdrift ? t 24/25 micro_per_cycle_max pmicropercycle + pdmaxdrift ? t 26/27 micro_per_macro_nom_half round( pmicropermacronom / 2) ? t7 offset_correction_out po ffsetcorrectionout ? t9 rate_correction_out pratecorrectionout ? t14 single_slot_enabled psingleslotenabled bool 10 wakeup_channel pwakeupchannel see table 26-79 10 wakeup_pattern pwakeuppattern number 18 decoding_correction_a pdecodingcorrection + pdelaycompensation[a] + 2 ? t19 decoding_correction_b pdecodingcorrection + pdelaycompensation[b] + 2 ? t7 key_slot_header_crc header crc for key slot 0x00 0 0x7f f number 12 extern_offset_correction pexternoffsetcorrection ? t29 extern_rate_correction pexternratecorrection ? t21 notes: 1 see flexray communications system protoc ol specification, version 2.1 rev a for detailed protocol parameter definitions table 26-79. wakeup channel selection wakeup_channel wakeup channel 0a 1b table 26-78. protocol configurati on register fields (continued) name description 1 min max unit fr_pc r
flexray communication controller freescale semiconductor 26-75 pxs20 microcontroller reference manual, rev. 1 26.5.2.69.1 protocol configurat ion register 0 (fr_pcr0) 26.5.2.69.2 protocol configurat ion register 1 (fr_pcr1) 26.5.2.69.3 protocol configurat ion register 2 (fr_pcr2) 26.5.2.69.4 protocol configurat ion register 3 (fr_pcr3) base + 0x00a0 write: poc:config 0123456789101112131415 r action_point_offset st atic_slot_length w rese t 0000000000000000 figure 26-70. protocol configuration register 0 (fr_pcr0) base + 0x00a2 write: poc:config 0123456789101112131415 r0 0 macro_after_first_static_slot w rese t 0000000000000000 figure 26-71. protocol configuration register 1 (fr_pcr1) base + 0x00a4 write: poc:config 0123456789101112131415 r minislot_after_action_point number_of_static_slots w rese t 0000000000000000 figure 26-72. protocol configuration register 2 (fr_pcr2) base + 0x00a6 write: poc:config 0123456789101112131415 r wakeup_symbol_rx_low minislot_action_point_offset[4:0] coldstart_attempts w rese t 0000000000000000 figure 26-73. protocol configuration register 3 (fr_pcr3)
flexray communication controller 26-76 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.5.2.69.5 protocol configurat ion register 4 (fr_pcr4) 26.5.2.69.6 protocol configurat ion register 5 (fr_pcr5) 26.5.2.69.7 protocol configurat ion register 6 (fr_pcr6) 26.5.2.69.8 protocol configurat ion register 7 (fr_pcr7) base + 0x00a8 write: poc:config 0123456789101112131415 r cas_rx_low_max wakeup_symbol_rx_window w rese t 0000000000000000 figure 26-74. protocol configuration register 4 (fr_pcr4) base + 0x00aa write: poc:config 0123456789101112131415 r tss_transmitter wakeup_symbol_tx_low wakeup_symbol_rx_idle w rese t 0000000000000000 figure 26-75. protocol configuration register 5 (fr_pcr5) base + 0x00ac write: poc:config 0123456789101112131415 r0 symbol_window_after_action_point macro_initial_offset_a w rese t 0000000000000000 figure 26-76. protocol configuration register 6 (fr_pcr6) base + 0x00ae write: poc:config 0123456789101112131415 r decoding_correction_b micro_per_macro_nom_half w rese t 0000000000000000 figure 26-77. protocol configuration register 7 (fr_pcr7)
flexray communication controller freescale semiconductor 26-77 pxs20 microcontroller reference manual, rev. 1 26.5.2.69.9 protocol configurat ion register 8 (fr_pcr8) 26.5.2.69.10 protocol configurat ion register 9 (fr_pcr9) 26.5.2.69.11 protocol configurat ion register 10 (fr_pcr10) base + 0x00b0 write: poc:config 0123456789101112131415 r max_without_clock_ correction_fatal max_without_clock_ correction_passive wakeup_symbol_tx_idle w rese t 0000000000000000 figure 26-78. protocol configuration register 8 (fr_pcr8) base + 0x00b2 write: poc:config 0123456789101112131415 r mini slot_ exists sym bol_ win dow_ exists offset_correction_out w reset0000000000000000 figure 26-79. protocol configuration register 9 (fr_pcr9) base + 0x00b4 write: poc:config 0123456789101112131415 r single _slot _en abled wake up_ chan nel macro_per_cycle w reset0000000000000000 figure 26-80. protocol configur ation register 10 (fr_pcr10)
flexray communication controller 26-78 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.5.2.69.12 protocol configurat ion register 11 (fr_pcr11) 26.5.2.69.13 protocol configurat ion register 12 (fr_pcr12) 26.5.2.69.14 protocol configurat ion register 13 (fr_pcr13) 26.5.2.69.15 protocol configurat ion register 14 (fr_pcr14) base + 0x00b6 write: poc:config 0123456789101112131415 rkey_ slot_ used_ for_ start up key_ slot_ used_ for_ sync offset_correction_start w reset0000000000000000 figure 26-81. protocol configur ation register 11 (fr_pcr11) base + 0x00b8 write: poc:config 0123456789101112131415 r allow_passive_to_active key_slot_header_crc w reset0000000000000000 figure 26-82. protocol configur ation register 12 (fr_pcr12) base + 0x00ba write: poc:config 0123456789101112131415 r first_minislot_action_point_offset static_slot_after_action_point w reset0000000000000000 figure 26-83. protocol configur ation register 13 (fr_pcr13) base + 0x00bc write: poc:config 0123456789101112131415 r rate_correction_out listen_timeout[20:16] w reset0000000000000000 figure 26-84. protocol configur ation register 14 (fr_pcr14)
flexray communication controller freescale semiconductor 26-79 pxs20 microcontroller reference manual, rev. 1 26.5.2.69.16 protocol configurat ion register 15 (fr_pcr15) 26.5.2.69.17 protocol configurat ion register 16 (fr_pcr16) 26.5.2.69.18 protocol configurat ion register 17 (fr_pcr17) 26.5.2.69.19 protocol configurat ion register 18 (fr_pcr18) base + 0x00be write: poc:config 0123456789101112131415 r listen_timeout[15:0] w reset0000000000000000 figure 26-85. protocol configur ation register 15 (fr_pcr15) base + 0x00c0 write: poc:config 0123456789101112131415 r macro_initial_offset_b no ise_listen_tim eout[24:16] w reset0000000000000000 figure 26-86. protocol configur ation register 16 (fr_pcr16) base + 0x00c2 write: poc:config 0123456789101112131415 r noise_listen_timeout[15:0] w reset0000000000000000 figure 26-87. protocol configur ation register 17 (fr_pcr17) base + 0x00c4 write: poc:config 0123456789101112131415 r wakeup_pattern key_slot_id w reset0000000000000000 figure 26-88. protocol configur ation register 18 (fr_pcr18)
flexray communication controller 26-80 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.5.2.69.20 protocol configurat ion register 19 (fr_pcr19) 26.5.2.69.21 protocol configurat ion register 20 (fr_pcr20) 26.5.2.69.22 protocol configurat ion register 21 (fr_pcr21) 26.5.2.69.23 protocol configurat ion register 22 (fr_pcr22) base + 0x00c6 write: poc:config 0123456789101112131415 r decoding_correction_a payload_length_static w reset0000000000000000 figure 26-89. protocol configur ation register 19 (fr_pcr19) base + 0x00c8 write: poc:config 0123456789101112131415 r micro_initial_offset_b micro_initial_offset_a w reset0000000000000000 figure 26-90. protocol configur ation register 20 (fr_pcr20) base + 0x00ca write: poc:config 0123456789101112131415 r extern_rate_ correction latest_tx w reset0000000000000000 figure 26-91. protocol configur ation register 21 (fr_pcr21) base + 0x00cc write: poc:config 0123456789101112131415 r r* comp_accepted_startup_range_a micro_per_cycle[19:16 w reset0000000000000000 figure 26-92. protocol configur ation register 22 (fr_pcr22)
flexray communication controller freescale semiconductor 26-81 pxs20 microcontroller reference manual, rev. 1 26.5.2.69.24 protocol configurat ion register 23 (fr_pcr23) 26.5.2.69.25 protocol configurat ion register 24 (fr_pcr24) 26.5.2.69.26 protocol configurat ion register 25 (fr_pcr25) 26.5.2.69.27 protocol configurat ion register 26 (fr_pcr26) base + 0x00ce write: poc:config 0123456789101112131415 r micro_per_cycle[15:0] w reset0000000000000000 figure 26-93. protocol configur ation register 23 (fr_pcr23) base + 0x00d0 write: poc:config 0123456789101112131415 r cluster_drift_damping max_payload_length_dynamic micro_per_cycle_min [19:16] w reset0000000000000000 figure 26-94. protocol configur ation register 24 (fr_pcr24) base + 0x00d2 write: poc:config 0123456789101112131415 r micro_per_cycle_min[15:0] w reset0000000000000000 figure 26-95. protocol configur ation register 25 (fr_pcr25) base + 0x00d4 write: poc:config 0123456789101112131415 r allow _halt_ due _to_ clock comp_accepted_startup_range_b micro_per_cycle_max [19:16] w reset0000000000000000 figure 26-96. protocol configur ation register 26 (fr_pcr26)
flexray communication controller 26-82 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.5.2.69.28 protocol configurat ion register 27 (fr_pcr27) 26.5.2.69.29 protocol configurat ion register 28 (fr_pcr28) 26.5.2.69.30 protocol configurat ion register 29 (fr_pcr29) 26.5.2.69.31 protocol configurat ion register 30 (fr_pcr30) base + 0x00d6 write: poc:config 0123456789101112131415 r micro_per_cycle_max[15:0] w reset0000000000000000 figure 26-97. protocol configur ation register 27 (fr_pcr27) base + 0x00d8 write: poc:config 0123456789101112131415 r dynamic_slot _idle_phase macro_after_offset_correction w reset0000000000000000 figure 26-98. protocol configur ation register 28 (fr_pcr28) base + 0x00da write: poc:config 0123456789101112131415 r extern_offset_ correction minislots_max w reset0000000000000000 figure 26-99. protocol configur ation register 29 (fr_pcr29) base + 0x00dc write: poc:config 0123456789101112131415 r000000000000 sync_node_max w reset0000000000000000 figure 26-100. protocol configuration register 30 (fr_pcr30)
flexray communication controller freescale semiconductor 26-83 pxs20 microcontroller reference manual, rev. 1 26.5.2.70 ecc error interrupt flag and enable register (fr_eeifer) this register provides the means to control the ec c related interrupt request lines and provides the corresponding interrupt flag s. the interrupt flags are cleared by writing 1, which resets the corresponding report registers. for a detailed description see section 26.6.24.2, memory error reporting . base + 0x00f0 write: normal mode 0123456789101112131415 r lrne_of lrce_of drne_of drce_of lrne_if lrce_if drne_if drce_if 0 0 0 0 lrne_ie lrce_ie drne_ie drce_ie w w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 26-101. ecc error interrupt flag and enable register (fr_eeifer) table 26-80. fr_eeifer field descriptions field description error overflow flags lrne_of lram non-corrected error overflow flag ? this flag is set to 1 when at least one of the following events appears: a) memory errors are detected but not corrected on chi lram and interrupt flag lrne_if is already 1. b) memory errors are detected but not corrected on at least two banks of chi lram 0 no such event 1 non-corrected error overflow detected on chi lram lrce_of lram corrected error overflow flag ? this flag is set to 1 when at least one of the following events appears: a) memory errors are detected and corrected on chi lram and interrupt flag lrce_if is already 1. b) memory errors are detected and corrected on at least two banks of chi lram 0 no such event 1 corrected error overflow detected on chi lram note: error correction not implemented on chi lram, flag will never be asserted. drne_of dram non-corrected error overflow flag ? this flag is set to 1 when at least one of the following events appears: a) memory errors are detected but not corrected on pe dram and interrupt flag drne_if is already 1. b) memory errors are detected but not corrected on at least two banks of the pe dram 0 no such event 1 non-corrected error overflow detected on pe dram drce_of dram corrected error overflow flag ? this flag is set to 1 when at least one of the following events appears: a) memory errors are detected and corrected on pe dram and interrupt flag drce_if is already 1. b) memory errors are detected and corrected on at least two banks of pe dram 0 no such event 1 corrected error overflow detected on pe dram
flexray communication controller 26-84 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 error interrupt flags lrne_if lram non-corrected error interrupt flag ? this interrupt flag is set to 1 when a memory error is detected but not corrected on the chi lram. 0 no such event 1 non-corrected error detected on chi lram lrce_if lram corrected er ror interrupt flag ? this interrupt flag is se t to 1 when a memory error is detected and corrected on the chi lram. 0 no such event 1 corrected error detected on chi lram note: error correction not implemented on chi lram, flag will never be asserted. drne_if dram non-corrected error interrupt flag ? this interrupt flag is se t to 1 when a memory error is detected but not corrected on pe dram. 0 no such event 1 non-corrected error detected on pe dram drce_if dram corrected error interrupt flag ? this interrupt flag is set to 1 when a memory error is detected and corrected on pe dram. 0 no such event 1 corrected error detected on pe dram error interrupt enables lrne_ie lram non-corrected er ror interrupt enable ? this flag controls if the lram non-corrected error interrupt line is asserted when the lrne_if flag is set. 0 disable interrupt line 1 enable interrupt line lrce_ie lram corrected error interrupt enable ? this flag controls if the lram corrected error interrupt line is asserted when the lrce_if flag is set. 0 disable interrupt line 1 enable interrupt line drne_ie dram non-corrected error interrupt enable ? this flag controls if the dram non-corrected error interrupt line is asserted when the drne_if flag is set. 0 disable interrupt line 1 enable interrupt line drce_ie dram corrected error interrupt enable ? this flag controls if the dram corrected error interrupt line is asserted when the drce_if flag is set. 0 disable interrupt line 1 enable interrupt line table 26-80. fr_eeifer field descriptions (continued) field description
flexray communication controller freescale semiconductor 26-85 pxs20 microcontroller reference manual, rev. 1 26.5.2.71 ecc error report and injection control register (fr_eericr) this register configures the error injection and error reporti ng and provides the selector for the content of the report registers. base + 0x00f2 write: ers: anytime erm, eim, eie: idl 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r bsy 0 0 0 0 0 ers 0 0 0 erm 0 0 eim eie w rese t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 26-102. ecc error report and injection control register (fr_eericr) table 26-81. fr_eericr field descriptions field description bsy register update busy ? this field indicates the current state of the ecc configuration update and controls the register write access condition idl specified in ? section 26.5.2.2, register write access 0 ecc configuration is idle 1 ecc configuration is running ers error report select ? this field selects the content of the ecc error reporting registers. 00 show pe dram non-corrected error information 01 show pe dram corrected error information 10 show chi lram non-corrected error information 11 show chi lram corrected error information erm error report mode ? this bit configures the type of data written into the internal error report registers on the detection of a memory error. 0 store data and code as delivered by ecc decoding logic. 1 store data and code as read from the memory. eim error injection mode ? this bit configures the ecc error injection mode. 0 use fr_eeidr[data] and fr_eeicr[code] as xo r distortion pattern for error injection. 1 use fr_eeidr[data] and fr_eeicr[code] as write value for error injection. eie error injection enable ? this bit configures the ecc error injection on the memories. 0 error injection disabled 1 error injection enabled note: when the ecc functionality is required to be disabled (i.e.value of the fr_mcr[ecce] is 0), error injection enable bit fr_eericr[eie] should not be set to 1
flexray communication controller 26-86 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.5.2.72 ecc error report ad dress register (fr_eerar) this register provides the memory identifier, bank, and address for which the memory error is reported. 26.5.2.73 ecc error report data register (fr_eerdr) this register provides the data related information of the reported memory read access. the assignment of the bits depends on the selected me mory and memory bank as shown in table 26-84 . base + 0x00f4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r mid bank addr w rese t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 26-103. ecc error report address register (fr_eerar) table 26-82. fr_eerar field descriptions field description mid memory identifier ? this flag provides the memory instance for which the memory error is reported. 0 pe dram 1 chi lram bank memory bank ? this field provides the bank for which the memory error is reported. 000 reset value, updated to a valid value with the first ecc error. for mid=0: 000 bank0: pe dram [7:0] 001 bank1: pe dram [15:8] others - not used for mid=1: 000 bank0: fr_mbccfr(2n) 001 bank1: fr_mbfidr(2n) 010 bank2: fr_mbidxr(2n) 011 bank3: fr_mbccfr(2n+1) 100 bank4: fr_mbfidr(2n+1) 101 bank5: fr_mbidxr(2n+1) others - not used addr memory address ? this field provides the address of the failing memory location. base + 0x00f6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rdata w rese t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 26-104. ecc error report data register (fr_eerdr)
flexray communication controller freescale semiconductor 26-87 pxs20 microcontroller reference manual, rev. 1 26.5.2.74 ecc error report code register (fr_eercr) this register provides the ecc related inform ation of the reported memory read access. table 26-83. fr_eerdr field descriptions field description data data ? the content of this field depends on the report mode selected by fr_eericr[erm] erm=0: ecc data, shows data as generated by the ecc decoding logic. erm=1: memory data, shows data as read from the memory. table 26-84. valid bits in fr_eerdr[data] / fr_eeidr[data] field mem bank 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pe dram 0 pe dram[7:0] pe dram 1 pe dram[15:8] chi lram 0 fr_mbccfr(2n) chi lram 1 fr_mbfidr(2n) chi lram 2 fr_mbidxr(2n) chi lram 3 fr_mbccfr(2n+1) chi lram 4 fr_mbfidr(2n+1) chi lram 5 fr_mbidxr(2n+1) base + 0x00f8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 code w rese t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 26-105. ecc error report code register (fr_eercr) table 26-85. fr_eersr field descriptions field description code code ? the content of this field depends on the report mode selected by fr_eericr[erm] erm=0: syndrome. shows the ecc syndrome generated by the ecc decoding logic. the coding of the pe dram syndrome is shown in section 26.6.24.2.2, pe dram syndrome . the coding of the chi lram syndrome is shown in section 26.6.24.2.4, chi lram syndrome . erm=1: checkbits. shows the ecc checkbits read from the memory.
flexray communication controller 26-88 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.5.2.75 ecc error injection ad dress register (fr_eeiar) this register defines the memory module, bank, and address where the ecc error has to be injected. 26.5.2.76 ecc error injection data register (fr_eeidr) this register defines the data dist ortion pattern for the error injection write. the number of valid bits depends on the selected memory and memory bank as shown in table 26-84 . base + 0x00fa write: idl 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r mid bank addr w rese t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 26-106. ecc error injection address register (fr_eeiar) table 26-86. fr_eeiar field descriptions field description mid memory identifier ? this flag defines the memory instance for ecc error injection. 0 pe dram 1 chi lram bank memory bank ? this field defines the memory bank for ecc error injection. for mid=0: 000 bank0: pe dram [7:0] 001 bank1: pe dram [15:8] others reserved for mid=1: 000 bank0: fr_mbccfr(2n) 001 bank1: fr_mbfidr(2n) 010 bank2: fr_mbidxr(2n) 011 bank3: fr_mbccfr(2n+1) 100 bank4: fr_mbfidr(2n+1) 101 bank5: fr_mbidxr(2n+1) others reserved addr memory address ? this flag defines the memory address for ecc error injection. base + 0x00fc write: idl 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r data w rese t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 26-107. ecc error injection data register (fr_eeidr)
flexray communication controller freescale semiconductor 26-89 pxs20 microcontroller reference manual, rev. 1 26.5.2.77 ecc error injection code register (fr_eeicr) this register defines the ecc code distortion pattern for the error injection write. 26.5.2.78 message buffer configuration, control, status registers (fr_mbccsrn) the content of these registers comprises message buf fer configuration data, me ssage buffer control data, message buffer status information, and message buffer in terrupt flags. a detailed description of all flags can be found in section 26.6.6, individual message buffer func tional description . table 26-87. fr_eeidr field descriptions field description data data ? the content of this field depends on the error injection mode selected by fr_eericr[eim]. eim=0: this field defines the xor distortion pattern for the da ta written into the memory. eim=1: this field defines the data to be written into the memory. base + 0x00fe write: idl 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 code w rese t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 26-108. ecc error injection code register (fr_eeicr) table 26-88. fr_eeicr field descriptions field description code code ? the content of this field depends on the error injection mode selected by fr_eericr[eim]. eim=0: this field defines the xor distortion patte rn for the ecc checkbits written into the memory. eim=1: this field defines the ecc checkbits written into the memory. base + 0x0100 (fr_mbccsr0) base + 0x0108 (fr_mbccsr1) ... base + 0x02f8 (fr_mbccsr63) write: mcm, mbt, mtd: poc:config or mb_dis cmt: mb_lck or mb_dis edt, lckt, mbie, mbif: normal mode additional reset: cmt, dup, dval, mbif: message buffer disable 0123456789101112131415 r0 mcm mbt mtd cmt 0 0 mbie 0 0 0 dup dval eds lcks mbif w rwm edt lckt w1c reset0000000000000000 figure 26-109. message buffer configuration, control, st atus registers (fr_mbccsrn)
flexray communication controller 26-90 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 if the application writes 1 to the edt bit, no writ e access to the other regi ster bits is performed. if the application writes 0 to the edt bit and 1 to th e lckt bit, no write acce ss to the other bits is performed. table 26-89. fr_mbccsrn field descriptions field description message buffer configuration mcm message buffer commit mode ? this bit configures the commit mode of a double buffered message buffer. 0 streaming commit mode 1 immediate commit mode mbt message buffer type ? this bit configures the buffering type of a transmit message buffer. 0 single buffered message buffer 1 double buffered message buffer mtd message buffer transfer direction ? this bit configures the transfer direction of a message buffer. 0 receive message buffer 1 transmit message buffer message buffer control cmt commit for transmission ? this bit indicates if the transmit message buffer data are ready for transmission. 0 message buffer data not ready for transmission 1 message buffer data ready for transmission edt enable/disable trigger ? if the application writes 1 to this bit, a message buffer enable or disable is triggered, depending on the current value eds status bit is 0. 0no effect 1 message buffer enable or disable is triggered lckt lock/unlock trigger ? if the application writes 1 to this bit, a message buffer lock or unlock is triggered, depending on the current value of the lcks status bit. 0no effect 1 message buffer lock or unlock is triggered mbie message buffer interrupt enable ? this control bit defines whether the message buffer will generate an interrupt request when its mbif flag is set. 0 interrupt request generation disabled 1 interrupt request generation enabled
flexray communication controller freescale semiconductor 26-91 pxs20 microcontroller reference manual, rev. 1 26.5.2.79 message buffer cycle counter filter registers (fr_mbccfrn) this register contains message buffer configurat ion data for the transm ission mode, the channel assignment, and for the cycle counter filtering. for detailed information on cycle c ounter filtering, refer to section 26.6.7.1, message buffer cycle counter filtering . message buffer status dup data updated ? this status bit indicate s whether the frame header in the message buffer header field and the data in the message buffer data field were updated after a frame reception. 0 frame header and message buffer data field not updated 1 frame header and message buffer data field updated dval data valid ? for receive message buffers this status bit indicates whether the message buffer data field contains valid frame data. for transm it message buffers the status bit indicates if a message is transferred again due to the state transmission mode of the message buffer. 0 receive message buffer contains no valid frame data / message is transmitted for the first time 1 receive message buffer contains valid frame data / message will be transferred again eds enable/disable status ? this status bit indicates whether the message buffer is enabled or disabled. 0 message buffer is disabled. 1 message buffer is enabled. lcks lock status ? this status bit indicates the curr ent lock status of the message buffer. 0 message buffer is not locked by the application. 1 message buffer is locked by the application. mbif message buffer interrupt flag ? this flag is set when the slot status field of the message buffer was updated after frame transmission or reception, or when a transmit message buffer was just enabled by the application. 0 no such event 1 slot status field updated or trans mit message buffer just enabled base + 0x0102 (fr_mbccfr0) base + 0x010a (fr_mbccfr1) ... base + 0x02fa (fr_mbccfr63) 16-bit write access required write: poc:config or mb_dis 0123456789101112131415 r mtm cha chb ccfe ccfmsk ccfval w reset---------------- figure 26-110. message buffer cycle co unter filter regi sters (fr_mbccfrn) table 26-89. fr_mbccsrn field descriptions (continued) field description
flexray communication controller 26-92 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 . note if at least one message buffer assigned to a certain slot is assigned to both channels, then all message buffers assigne d to this slot have to be assigned to both channels. otherwis e, the message buffer configuration is illegal and the result of the message buf fer search is not defined. table 26-90. fr_mbccfrn field descriptions field description mtm message buffer transmission mode ? this control bit applies only to transmit message buffers and defines the transmission mode. 0 event transmission mode 1 state transmission mode cha chb channel assignment ? these control bits define the channel assignment and control the receive and transmit behavior of the message buffer according to table 26-91 . ccfe cycle counter filtering enable ? this control bit is used to enab le and disable the cycle counter filtering. 0 cycle counter filtering disabled 1 cycle counter filtering enabled ccfmsk cycle counter filterin g mask ? this field defines the filter mask for the cycle counter filtering. ccfval cycle counter filtering value ? this field defines the filter va lue for the cycle counter filtering. table 26-91. channel assignment description cha chb transmit message buffer receive message buffer static segment dynamic segment static segment dynamic segment 1 1 transmit on both channel a and channel b reserved (function not guaranteed) store first valid frame received on either channel a or channel b reserved (function not guaranteed) 0 1 transmit on channel b transmit on channel b store first valid frame received on channel b store first valid frame received on channel b 1 0 transmit on channel a transmit on channel a store first valid frame received on channel a store first valid frame received on channel a 0 0 no frame transmission no frame transmission no frame stored no frame stored
flexray communication controller freescale semiconductor 26-93 pxs20 microcontroller reference manual, rev. 1 26.5.2.80 message buffer fram e id registers (fr_mbfidrn) 26.5.2.81 message buffer i ndex registers (fr_mbidxrn) 26.6 functional description this section provides a detailed description of the functionality implemented in the cc. base + 0x0104 (fr_mbfidr0) base + 0x010c (fr_mbfidr1) ... base + 0x02fc (fr_mbfidr63) 16-bit write access required write: poc:config or mb_dis 0123456789101112131415 r00000 fid w reset00000 ----------- figure 26-111. message buffer frame id registers (fr_mbfidrn) table 26-92. fr_mbfidrn field descriptions field description fid frame id ? the semantic of this field depends on the message buffer transfer type. ? receive message buffer: this field is used as a filter value to determine if the message buffer is used for reception of a message received in a slot with the slot id equal to fid. ? transmit message buffer: this field is used to determine the slot in which the message in this message buffer should be transmitted. base + 0x0106 (fr_mbidxr0) base + 0x010e (fr_mbidxr1) ... base + 0x02fe (fr_mbidxr63) 16-bit write access required write: poc:config or mb_dis 0123456789101112131415 r000000000 mbidx w reset000000000 ------- figure 26-112. message buffer index registers (fr_mbidxrn) table 26-93. fr_mbidxrn field descriptions field description mbidx message buffer index ? this field provides the index of the message buffer header field of the physical message buffer that is currently associated with this message buffer. the application writes the index of th e initially associated message buffer hea der field into this register. the cc updates this register after fr ame reception or transmission.
flexray communication controller 26-94 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.6.1 message buffer concept the cc uses a data structure called message buffer to store frame data, confi guration, control, and status data. each message buffer consists of two parts, the message buffer control data and the physical message buffer. the message buffer control data are located in de dicated registers. the st ructure of the message buffer control data depends on the messa ge buffer type and is described in section 26.6.3, message buffer types . the physical message buffer is located in th e flexray memory area and is described in section 26.6.2, physical message buffer . 26.6.2 physical message buffer all flexray messages and related fram e and slot status information of r eceived frames and of frames to be transmitted to the flexray bus ar e stored in data structures called physical message buffers . the physical message buffers are located in the flexray memory area.the structure of a physical message buffer is depicted in figure 26-113 . a physical message buffer cons ists of two fields, the message buffer header field and the message buffer data field . the message buffer header field contains the frame header , the data field offset , and the slot status .the message buffer data field contains the frame data . the connection between the two fields is established by the data field offset . figure 26-113. physical message buffer structure 26.6.2.1 message buffer header field the message buffer header field is a contiguous region in the flexray memory area and oc cupies ten bytes. it contains the frame header, the data field offset , and the slot status. its structure is shown in figure 26-113 . the physical start address sadr_mbhf of the message buffer header field must be 16-bit aligned. 26.6.2.1.1 frame header the frame header occupies the first six bytes in the message buffer header field. it contains all flexray frame header related information according to the flexray communications system protocol specification, version 2.1 rev a . a detailed description of the usage and the content of the frame header is provided in section 26.6.5.2.1, frame h eader description . data field offset frame data message buffer header field message buffer data field slot status frame header sadr_mbdf sadr_mbhf flexray memory
flexray communication controller freescale semiconductor 26-95 pxs20 microcontroller reference manual, rev. 1 26.6.2.1.2 data field offset the data field offset follows the fra me header in the message buffer data field and occupies two bytes. it contains the offset of the corresponding message buffer data field with respect to the cc flexray memory area base address as provi ded by smba field in the system memory base address register (fr_symbadr) . the data field offset is used to determine the start address sadr_mbdf of the corresponding message buffer data field in the flexray memory area according to equation 26-2 . sadr_mbdf = [data field offset] + smba eqn. 26-2 26.6.2.1.3 slot status the slot status occupies the last two bytes of the me ssage buffer header field. it provides the slot and frame status related informat ion according to the flexray communications syst em protocol specification, version 2.1 rev a . a detailed description of the content and usage of the slot status is provided in section 26.6.5.2.3, slot status description . 26.6.2.2 message buffer data field the message buffer data fiel d is a contiguous area of 2- byte entities. this field c ontains the frame payload data, or a part of it, of the frame to be transmit ted to or received from th e flexray bus. the minimum length of this field depends on the specific message buf fer configuration and is specified in the message buffer descriptions given in section 26.6.3, message buffer types . 26.6.3 message buffer types the cc provides three different types of message buffers. ? individual message buffers ? receive shadow buffers ? receive fifo buffers for each message buffer type the st ructure of the physical message buffe r is identical. the message buffer types differ only in the structure and content of message buffer contro l data, which control the related physical message buffer. the message buffer control data are descri bed in the following sections. 26.6.3.1 individual message buffers the individual message buffers are used for all t ypes of frame transmission and for dedicated frame reception based on individual filter se ttings for each message buffer. the cc supports three types of individual message buffers, which are described in section 26.6.6, individual message buffer functional description . each individual message buffer consists of two parts, the phys ical message buffer, which is located in the flexray memory area, and the message buffer control data, which are located in dedicated registers. the structure of an individual message buffer is given in figure 26-114 . each individual message buffer has a message buffe r number n assigned, which determines the set of message buffer control registers a ssociated to this individual messa ge buffer. the individual message
flexray communication controller 26-96 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 buffer with message buffer number n is controlled by the regi sters fr_mbccsrn, fr_mbccfrn, fr_mbfidrn, and fr_mbidxrn. the connection between the message buffer control registers and the physical message buffer is established by the message buffe r index field mbidx in the message buffer index registers (fr_mbidxrn) . the start address sadr_mbhf of the rela ted message buffer header field in the flexray memory area is determined according to equation 26-3 . sadr_mbhf = (fr_mbidxrn[mbidx] * 10) + smba eqn. 26-3 figure 26-114. individual message buffer structure 26.6.3.1.1 individual m essage buffer segments the set of the individual message buffers can be sp lit up into two message buffer segments using the message buffer segment size and u tilization register (fr_mbssutr) . all individual message buffers with a message buffer number n <= fr_mbssutr[las t_mb_seg1] belong to th e first message buffer segment. all individual message buffe rs with a message buffer number n > fr_mbssutr[last_mb_seg1] belong to the second message buffer segment. the following rules apply to the length of the message buffer data field: ? all physical message buffers associated to indi vidual message buffers that belong to the same message buffer segment must have message buffer data fields of the same length ? the minimum length of the message buffer data fi eld for individual messag e buffers in the first message buffer segment is 2 * fr_mbdsr[mbseg1ds] bytes ? the minimum length of the messag e buffer data field fo r individual message buf fers assigned to the second segment is 2 * fr _mbdsr[mbseg2ds] bytes. 26.6.3.2 receive shadow buffers the receive shadow buffers are required for the fram e reception process for individual message buffers. the cc provides four receive shadow buffers, one r eceive shadow buffer per channel and per message buffer segment. fr_mbfidrn message buffer control registers fr_mbccsrn fr_mbccfrn fr_mbidxrn (min) fr_mbdsr[mbseg1ds] * 2 bytes / fr_mbdsr[mbseg2ds] * 2 bytes data field offset frame data message buffer header field message buffer data field slot status frame header sadr_mbdf sadr_mbhf flexray memory
flexray communication controller freescale semiconductor 26-97 pxs20 microcontroller reference manual, rev. 1 each receive shadow buffer consists of two parts, the physical message buffer located in the flexray memory area and the receive shadow buffer control registers located in dedicated register s. the structure of a receive shadow buffer is shown in figure 26-115 . the four internal shadow buffer control registers can be accessed by the receive shadow buffer i ndex register (fr_rsbir) . the connection between the receive sh adow buffer control register and the physical message buffer for the selected receive shadow buffer is established by th e receive shadow buffer i ndex field rsbidx in the receive shadow buffer index register (fr_rsbir) . the start address sadr_mbhf of the related message buffer header field in the flexray memory area is determined according to equation 26-4 . sadr_mbhf = (fr_rsbir[rsbidx] * 10) + smba eqn. 26-4 the length required for the message buffer data fiel d depends on the message buffer segment that the receive shadow buffer is assigned to. for the receiv e shadow buffers assigned to the first message buffer segment, the length must be the same as for the i ndividual message buffers assi gned to the first message buffer segment. for the receive sha dow buffers assigned to the second message buffe r segment, the length must be the same as for the indi vidual message buffers assigned to the second message buffer segment. the receive shadow buffer assignment is described in receive shadow buffer index register (fr_rsbir) . figure 26-115. receive shadow buffer structure 26.6.3.3 receive fifo the receive fifo implemen ts a frame reception syst em based on the fifo conc ept. the cc provides two independent receive fifos, one per channel. a receive fifo consists of a set of physical message buffers in the flexray memory area and a set of receive fifo control registers located in dedicated registers. the struct ure of a receive fifo is given in figure 26-116 . fr_rsbidx[3] fr_rsbidx[2] fr_rsbidx[1] fr_rsbidx[0] receive shadow buffer control registers (min) fr_mbdsr[mbseg1ds] * 2 bytes / fr_mbdsr[mbseg2ds] * 2 bytes data field offset frame data message buffer header field message buffer data field slot status frame header sadr_mbdf sadr_mbhf flexray memory
flexray communication controller 26-98 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 the connection between the receive fifo control registers and the se t of physical message buffers is established by the receive fifo start index register (fr_rfsir) , the receive fifo depth and size register (rfdsr) , and the receive fifo a read index register (fr_rfarir) / receive fifo b read index register (fr_rfbrir) . the system memory base address smba is define d by the system memory base address register selected by th e fifo address mode bit fr_mcr[fam]. the start byte address sadr_mbhf[1] of the first message buffer header field that belongs to the receive fifo in the flexray memory area is determined according to equation 26-5 . sadr_mbhf[1] = (10 * fr _rfsir[sidx]) + smba eqn. 26-5 the start byte address sadr_mbhf[n] of the last message buffer header field that belongs to the receive fifo in the flexray memory area is determined according to equation 26-6 . sadr_mbhf[n] = (10 * (fr_rfsir[si dx] + rfdsr[fifo_depth])) + smba eqn. 26-6 note all message buffer header fields assigned to a receive fifo must be a contiguous region. figure 26-116. receive fifo structure fr_rfbrir fr_rfdsr[b] fr_rfsir[b] fr_rfarir fr_rfdsr[a] fr_rfsir[a] frame header[1] slot status[1] data field offset[1] receive fifo control register message buffer header fields message buffer data fields frame header[n] slot status[n] data field offset[n] (min) rfdsr[entry_size] * 2 bytes rfdsr[fifo_depth] + frame header[i] slot status[i] data field offset[i] frame data[n] sadr_mbdf[n] frame data[i] sadr_mbdf[i] frame data[1] sadr_mbdf[1] rfdsr[fifo_depth] sadr_mbhf[n] sadr_mbhf[i] sadr_mbhf[1] flexray memory
flexray communication controller freescale semiconductor 26-99 pxs20 microcontroller reference manual, rev. 1 26.6.3.4 message buffer configuration and control data this section describes the configuration and control data for each message buffer type. 26.6.3.4.1 individual message buffer configuration data before an individual message buffer can be used for transmission or reception, it must be configured. there is a set of common configuratio n parameters that applies to all in dividual message buffers and a set of configuration parameters that applie s to each message buffer individually. common configuration data the set of common configurat ion data for indivi dual message buffers is located in the following registers. ? message buffer data si ze register (fr_mbdsr) the mbseg2ds and mbseg1ds fields define the mini mum length of the message buffer data field with respect to the message buffer segment. ? message buffer segment size and utilization register (fr_mbssutr) the last_mb_seg1 and last_mb_util fields define the segmentation of the individual message buffers and the number of individual message buffers that are used. for mo re details, see section 26.6.3.1.1, individual message buffer segments . specific configuration data the set of message buffer specific configuration data for individual me ssage buffers is located in the following registers. ? message buffer configuration, contro l, status registers (fr_mbccsrn) the mcm, mbt, mtd bits conf igure the message buffer type. ? message buffer cycle counter filter registers (fr_mbccfrn) the mtm, cha, chb bits configure the transm ission mode and the channel assignment. the ccfe, ccfmsk, and ccfval bits and fiel ds configure the cycle counter filter. ? message buffer frame id registers (fr_mbfidrn) for a transmit message buffer, the fid field is used to determine the slot in which the message in this message buffer will be transmitted. ? message buffer index registers (fr_mbidxrn) this mbidx field provides the index of the mess age buffer header field of the physical message buffer that is currently associat ed with this message buffer. 26.6.3.5 individual messag e buffer control data during normal operation, each individua l message buffer can be controlled by the control and trigger bits cmt, lckt, edt, and mbie in the message buffer configuration, control, status registers (fr_mbccsrn) .
flexray communication controller 26-100 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.6.3.6 receive shadow buffer configuration data before frame reception into the indi vidual message buffers can be perf ormed, the receive shadow buffers must be configured. the configur ation data are provided by the receive shadow buffer index register (fr_rsbir) . for each receive shadow buffer, the application provides th e message buffer header index. when the protocol is in the poc:normal active or poc:normal passive state, the receive shadow buffers are under full cc control. 26.6.3.7 receive fifo cont rol and configuration data this section describes the configuration a nd control data for the two receive fifos. 26.6.3.7.1 receive fifo configuration data the cc provides two functional indepe ndent receive fifos, one per ch annel. the fifos have a common subset of configuration data: ? receive fifo system memory base address register (fr_rfsymbadr) ? receive fifo periodic timer register (fr_rfptr) each fifo has its own set of configuration data. th e configuration data are located in the following registers: ? receive fifo watermark and se lection register (fr_rfwmsr) ? receive fifo start inde x register (fr_rfsir) ? receive fifo depth and size register (rfdsr) ? receive fifo message id acceptance filter value register (fr_rfmidafvr) ? receive fifo message id acceptance filter mask register (fr_rfmidafmr) ? receive fifo frame id rejection fi lter value register (fr_rffidrfvr) ? receive fifo frame id rejection fi lter mask register (fr_rffidrfmr) ? receive fifo range filter conf iguration register (fr_rfrfcfr) 26.6.3.7.2 receive fifo control data the application can access the fifos at any time using the control bi ts in the following registers: ? global interrupt flag and enable register (fr_gifer) ? receive fifo fill level and po p count register (fr_rfflpcr) 26.6.3.7.3 receive fifo status data the current status of the receive fifo is provided in the following register: ? global interrupt flag and enable register (fr_gifer) ? receive fifo a read inde x register (fr_rfarir) ? receive fifo b read index register (fr_rfbrir) ? receive fifo fill level and po p count register (fr_rfflpcr)
flexray communication controller freescale semiconductor 26-101 pxs20 microcontroller reference manual, rev. 1 26.6.4 flexray memory area layout the cc supports a wide range of possible layouts for the flexray memo ry area. two basic layout modes can be selected by the fifo address mode bit fr_mcr[fam]. 26.6.4.1 flexray memory area layout (fr_mcr[fam] = 0) figure 26-117 shows an example layout for the fifo address mode fr_mcr[ fam]=0. in this mode, the following set of rules applies to th e layout of the flex ray memory area: ? the flexray memory area is one contiguous region. ? the flexray memory area size is maximum 64 kbytes. ? the flexray memory area starts at a 16 byte boundary the flexray memory area c ontains three areas: the message buffer header area , the message buffer data area , and the sync frame table area . figure 26-117. example of flexray memory area layout (fr_mcr[fam] = 0) 26.6.4.2 flexray memory area layout (fr_mcr[fam] = 1) figure 26-118 shows an example layout for the fifo a ddress mode fr_mcr[fam] =1. the following set of rules applies to the layout of the flexray memory area: ? the flexray memory area cons ists of two contiguous regions. ? the size of each region is maximum 64 kbytes. message buffer header area flexray memory area message buffer data area sync frame table area data field offset frame header slot status data field offset frame header slot status message buffer header fields individual message buffers receive shadow buffers data field offset frame header slot status data field offset frame header slot status message buffer header fields receive fifo a data field offset frame header slot status data field offset frame header slot status message buffer header fields receive fifo b data field offset frame header slot status 10 bytes fr_symbadr[smba] system memory
flexray communication controller 26-102 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? each region start at a 16 byte boundary. figure 26-118. example of flexray memory area layout (fr_mcr[fam] = 1) 26.6.4.3 message buffer head er area (fr_mcr[fam] = 0) the message buffer header area contains all message buffer header fields of th e physical message buffers for all message buffer types. the following rules apply to the message buffer header fields for the three type of message buffers. 1. the start byte address sadr_mbhf of each message buffer header field for individual message buffers and receive shadow buffers must fulfill equation 26-7 . sadr_mbhf = (i * 10) + fr_symbadr[smba]; (0 <= i < 128) eqn. 26-7 2. the start byte address sadr_mbhf of each message buffer header field for the fifo must fulfill equation 26-8 . sadr_mbhf = (i * 10) + fr_sym badr[smba]; (0 <= i < 1024) eqn. 26-8 fifo header area fifo flexray memory data field offset frame header slot status data field offset frame header slot status message buffer header fields receive fifo a data field offset frame header slot status data field offset frame header slot status message buffer header fields receive fifo b fr_rfsymbadr[smba] system memory message buffer header area flexray memory message buffer data area sync frame table area data field offset frame header slot status data field offset frame header slot status message buffer header fields individual message buffers receive shadow buffers data field offset frame header slot status 10 bytes fr_symbadr[smba] fifo message buffer data area
flexray communication controller freescale semiconductor 26-103 pxs20 microcontroller reference manual, rev. 1 sadr_mbhf = (i * 10) + fr_sym badr[smba]; (0 <= i < 1024) eqn. 26-9 3. the message buffer header fields for each fifo have to be a contiguous area. 26.6.4.4 message buffer head er area (fr_mcr[fam] = 1) the message buffer header area contains all message buffer header fields of th e physical message buffers for the individual message buffers and receiver shadow buffers. the following rules apply to the message buffer header fields for the two type of message buffers. 1. the start address sadr_mbhf of each message buffer header field for individual message buffers and receive shadow buffers must fulfill equation 26-10 . sadr_mbhf = (i * 10) + fr_sym badr[smba]; (0 <= i < 128) eqn. 26-10 26.6.4.5 fifo message buffer h eader area (fr_mcr[fam] = 1) the fifo message buffer header area contains all me ssage buffer header fields of the physical message buffers for the fifo. the following rules appl y to the fifo message buffer header fields. 1. the start byte address sadr_mbhf of each message buffer header field for the fifo must fulfill equation 26-11 . sadr_mbhf = (i * 10) + fr_rfsymbadr[smba]; (0 <= i < 1024) eqn. 26-11 2. the message buffer header fields for each fifo have to be a contiguous area. 26.6.4.6 message buffer data area the message buffer data area contai ns all the message buffer data fiel ds of the physical message buffers. each message buffer data fiel d must start at a 16-bit boundary. 26.6.4.7 sync frame table area the sync frame table area is used to provide a copy of the internal s ync frame tables for application access. refer to section 26.6.12, sync frame id and sync frame deviation tables , for the description of the sync frame table area. 26.6.5 physical message buffer description this section provides a detailed de scription of the usage and the cont ent of the two parts of a physical message buffer, the message buffer header field and the message buffer data field. 26.6.5.1 message buffer prot ection and data consistency the physical message buffers are located in the fl exray memory area. the cc provides no means to protect the flexray memory area from uncontrolled or illegal host or other client wr ite access. to ensure data consistency of the phys ical message buffers, the a pplication must follow the write access scheme that is given in the description of each of the physical message buffer fields.
flexray communication controller 26-104 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.6.5.2 message buffer h eader field description this section provides a detailed desc ription of the usage and content of the message buffer header field. a description of the structure of the messa ge buffer header fields is given in section 26.6.2.1, message buffer header field . each message buffer header field consists of three sections: the frame header section, the data field offset, and the slot status section. for a detailed descri ption of the data field offset, see section 26.6.2.1.2, data field offset . 26.6.5.2.1 frame header description frame header content the semantic and content of the frame header section depends on the message buffer type. for individual receive message buffers and receive fifos, the frame header receives the frame header data of the first valid frame received on the assigned channels. for receive shadow buffers, the frame header receives the frame header data of the current frame received regardless of whether th e frame is valid or not. for transmit message buffers, the appl ication writes the frame header of the frame to be transmitted into this location. the frame header will be read out when the frame is transferred to the flexray bus. the structure of the frame header in the message buffer header field for receive message buffers and the receive fifo is given in figure 26-119 . a detailed description is given in table 26-95 . figure 26-119. frame header structure (receive message buffer and receive fifo) the structure of the frame header in the message buffer header field for transmit message buffers is given in figure 26-120 . a detailed description is given in table 26-96 . the checks that will be performed are described in frame header checks . figure 26-120. frame header structure (transmit message buffer) the structure of the frame header in the message buffer header fi eld for transmit message buffers assigned to key slot is given in figure 26-121 . 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x0 r ppi nuf syf suf fid 0x2 0 0 cyccnt 0 pldlen 0x400000 hdcrc 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x0 r ppi nuf syf suf fid 0x2 cyccnt pldlen 0x4 hdcrc = not used = checked = checked if static slot
flexray communication controller freescale semiconductor 26-105 pxs20 microcontroller reference manual, rev. 1 figure 26-121. frame header structure (transmit message buffer for key slot) frame header access the frame header is located in the flexray memory area. to ensure data consistency, the application must follow the write access scheme described below. for receive message buffers, receive shadow buffers, a nd receive fifos, the application must not write to the frame header field. for transmit message buffers, the application must follow the write access restrictions given in table 26-94 . this table shows the condition under which the application can write to the frame header entries without corrupting the flexray message transmission. frame header checks as shown in figure 26-120 and figure 26-121 not all fields in the messag e buffer frame header are used for transmission. some fields in the message buffer frame header are ignored, some are used for transmission, and some of them are checked for corr ect values. all checks that will be performed are described below. for message buffers assigned to the key slot, no checks will be performed. the value of the fid field must be equal to the value of the corresponding message buffer frame id registers (fr_mbfidrn) . if the cc detects a mismatch while tr ansmitting the frame header, it will set the frame id error flag fid_ef in the chi error flag register (fr_chierfr) . the value of the fid field will be ignored and replaced by the value provided in the message buffer frame id registers (fr_mbfidrn) . for transmit message buffers assigned to the static segment, the pldlen value must be equal to the value of the payload_length_static field in the protocol configuration register 19 (fr_pcr19) . if this is not fulfilled, the static payload le ngth error flag spl_ef in the chi error flag register (fr_chierfr) is set when the message buffer is under transmission. a syntacti cally and semantically co rrect frame is generated 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x0 r ppi nuf syf suf fid 0x2 cyccnt pldlen 0x4 hdcrc = not used table 26-94. frame header write access constraints (transmit message buffer) field single buffered double buffered static segment dynamic segment static segment dynamic segment commit side transmit side commit side transmit side fid poc:config or mb_dis ppi, pldlen, hdcrc poc:config or mb_dis or mb_lck mb_lck
flexray communication controller 26-106 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 with payload_length_static pa yload words and the payloa d length field in the tran smitted frame header set to payload_length_static. for transmit message buffers assigned to the dynamic segment, the pldlen value must be less than or equal to the value of the max_pa yload_length_dynamic field in the protocol configuration register 24 (fr_pcr24) . if this is not fulfilled, the dynamic pa yload length error flag dpl_ef in the chi error flag register (fr_chierfr) is set when the message buffer is under transmission. a syntactically and semantically correct dynamic frame is generated wi th pldlen payload words and the payload length field in the frame header set to pldlen. table 26-95. frame header field descriptions (receive message buffer and receive ffo) field description r reserved bit ? this is the value of the reserved bit of the received frame stored in the message buffer ppi payload preamble indicator ? this is the value of the payload preamble indicator of the received frame stored in the message buffer. nuf null frame indicator ? this is the value of the null frame indicator of the received frame stored in the message buffer. syf sync frame indicator ? this is the value of the sync frame indicator of the received frame stored in the message buffer. suf startup frame indicator ? this is the value of the startup frame indicator of the received frame stored in the message buffer. fid frame id ? this is the value of the frame id field of the received frame stored in the message buffer. cyccnt cycle count ? this is the number of the communicat ion cycle in which the frame stored in the message buffer was received. pldlen payload length ? this is the value of the payload length field of the received frame stored in the message buffer. hdcrc header crc ? this is the value of the header crc field of the received frame stored in the message buffer. table 26-96. frame header field descriptions (transmit message buffer) field description r reserved bit ? this bit is not used, the value of the reserved bit is generated internally according to flexray communications system protocol specification, version 2.1 rev a. ppi payload preamble indicator ? this bit provides the value of the payload preamble indicator for the frame transmitted from the message buffer. nuf null frame indicator ? this bit is not used, the value of the null frame indicator is generated internally according to flexray communications system protocol specification, version 2.1 rev a. syf sync frame indicator ? this bit is not used, the value of the sync frame indicator is generated internally according to flexray communications system protocol specification, version 2.1 rev a. suf startup frame indicator ? this bit is not used, the value of the startup frame indicator is generated internally according to flexray communications system protocol specification, version 2.1 rev a.
flexray communication controller freescale semiconductor 26-107 pxs20 microcontroller reference manual, rev. 1 26.6.5.2.2 data field offset description data field offset content for a detailed description of the data field offset, see section 26.6.2.1.2, data field offset . data field offset access the application shall program the da ta field offset when configuring the message buffers either in the poc:config state or when the message buffer is disabled. 26.6.5.2.3 slot status description the slot status is a read-only structure for the a pplication and a write-only structure for the cc. the meaning and content of the slot status in the messa ge buffer header field de pends on the message buffer type. receive message buffer and receiv e fifo slot st atus description this section describes the slot st atus structure for the individual re ceive message buffers and receive fifos. the content of the slot st atus structure for receive message buffers depends on the message buffer type and on the channel assignment for indivi dual receive message buffers as given by table 26-97 . the meaning of the bits in the slot status structure is explained in table 26-98 . fid frame id ? this field is checked as described in frame header checks . cyccnt cycle count ? this field is not used, the value of the transmitted cycle count field is taken from the internal communic ation cycle counter. pldlen payload length ? this field is checked and used as described in frame header checks . hdcrc header crc ? this field provides the value of the header crc field for the frame transmitted from the message buffer. table 26-97. receive message buffer slot status content receive message buffer type slot status content individual receive message buffer assigned to both channels fr_mbccfrn[cha]=1 and fr_mbccfrn[chb]=1 see figure 26-122 individual receive message buffer assigned to channel a fr_mbccfrn[cha]=1 and fr_mbccfrn[chb[=0 see figure 26-123 individual receive message buffer assigned to channel b fr_mbccfrn[cha]=0 and fr_mbccfrn[chb]=1 see figure 26-124 receive fifo channel a message buffer see figure 26-123 receive fifo channel b message buffer see figure 26-124 table 26-96. frame header field descriptions (transmit message buffer) field description
flexray communication controller 26-108 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 26-122. receive message buffer slot status structure (chab) figure 26-123. receive message buffer slot status structure (cha) figure 26-124. receive message buffer slot status structure (chb) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r vfb syb nfb sub seb ceb bvb ch vfa sya nfa sua sea cea bva 0 reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 vfa sya nfa sua sea cea bva 0 reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r vfb syb nfb sub seb ceb bvb 1 0 0 0 0 0 0 0 0 reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? table 26-98. receive message buffer slot status field descriptions field description common message buffer status bits vfb valid frame on channel b ? protocol related variable: vss!validframe channel b 0 vss!validframe = 0 1 vss!validframe = 1 syb sync frame indicator channel b ? protocol related variable: vrf!header!syfindicator channel b 0 vrf!header!syfindicator = 0 1 vrf!header!syfindicator = 1 nfb null frame indicator channel b ? protocol related variable: vrf!header!nfindicator channel b 0 vrf!header!nfindicator = 0 1 vrf!header!nfindicator = 1 sub startup frame indicator channel b ? protocol related variable: vrf!header!sufindicator channel b 0 vrf!header!sufindicator = 0 1 vrf!header!sufindicator = 1 seb syntax error on channel b ? protocol related variable: vss!syntaxerror channel b 0 vss!syntaxerror = 0 1 vss!syntaxerror = 1 ceb content error on channel b ? protocol related variable: vss!contenterror channel b 0 vss!contenterror = 0 1 vss!contenterror = 1 bvb boundary violation on channel b ? protocol related variable: vss!bviolation channel b 0 vss!bviolation = 0 1 vss!bviolation = 1 ch channel first valid received ? this status bit applies only to receive message buffers assigned to the static segment and to both channels. it i ndicates the channel that has received the first valid frame in the slot. this flag is set to 0 if no valid frame was received at all in the subscribed slot. 0 first valid frame received on channel a, or no valid frame received at all 0 first valid frame received on channel b
flexray communication controller freescale semiconductor 26-109 pxs20 microcontroller reference manual, rev. 1 transmit message buffer slot status description this section describes the slot status structure for transmit message buffers. on ly the tca and tcb status bits are directly related to the tran smission process. all other status bits in this structure are related to a receive process that may have occu rred. the content of the slot stat us structure for transmit message buffers depends on the channel assignment as given by table 26-99 . the meaning of the bits in the slot status structure is described in table 26-98 . figure 26-125. transmit message buffer slot status structure (chab) vfa valid frame on channel a ? protocol related variable: vss!validframe channel a 0 vss!validframe = 0 1 vss!validframe = 1 sya sync frame indicator channel a ? protocol related variable: vrf!header!syfindicator channel a 0 vrf!header!syfindicator = 0 1 vrf!header!syfindicator = 1 nfa null frame indicator channel a ? protocol related variable: vrf!header!nfindicator channel a 0 vrf!header!nfindicator = 0 1 vrf!header!nfindicator = 1 sua startup frame indicator channel a ? protocol related variable: vrf!header!sufindicator channel a 0 vrf!header!sufindicator = 0 1 vrf!header!sufindicator = 1 sea syntax error on channel a ? protocol related variable: vss!syntaxerror channel a 0 vss!syntaxerror = 0 1 vss!syntaxerror = 1 cea content error on channel a ? protocol related variable: vss!contenterror channel a 0 vss!contenterror = 0 1 vss!contenterror = 1 bva boundary violation on channel a ? protocol related variable: vss!bviolation channel a 0 vss!bviolation = 0 1 vss!bviolation = 1 table 26-99. transmit message buffer slot status content transmit message buffer type slot status content individual transmit message buffer assigned to both channels fr_mbccfrn[cha]=1 and fr_mbccfrn[chb]=1 see figure 26-125 individual transmit message buffer assigned to channel a fr_mbccfrn[cha]=1 and fr_mbccfrn[chb]=0 see figure 26-126 individual transmit message buffer assigned to channel b fr_mbccfrn[cha]=0 and fr_mbccfrn[chb]=1 see figure 26-127 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r vfb syb nfb sub seb ceb bvb tcb vfa sya nfa sua sea cea bva tca reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? table 26-98. receive message buffer slot status field descriptions (continued) field description
flexray communication controller 26-110 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 26-126. transmit message buffer slot status structure (cha) figure 26-127. transmit message buffer slot status structure (chb) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 vfa sya nfa sua sea cea bva tca reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r vfb syb nfb sub seb ceb bvb tcb 0 0 0 0 0 0 0 0 reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? table 26-100. transmit message buffer slot status structure field descriptions field description vfb valid frame on channel b ? protocol related variable: vss!validframe channel b 0 vss!validframe = 0 1 vss!validframe = 1 syb sync frame indicator channel b ? protocol related variable: vrf!header!syfindicator channel b 0 vrf!header!syfindicator = 0 1 vrf!header!syfindicator = 1 nfb null frame indicator channel b ? protocol related variable: vrf!header!nfindicator channel b 0 vrf!header!nfindicator = 0 1 vrf!header!nfindicator = 1 sub startup frame indicator channel b ? protocol related variable: vrf!header!sufindicator channel b 0 vrf!header!sufindicator = 0 1 vrf!header!sufindicator = 1 seb syntax error on channel b ? protocol related variable: vss!syntaxerror channel b 0 vss!syntaxerror = 0 1 vss!syntaxerror = 1 ceb content error on channel b ? protocol related variable: vss!contenterror channel b 0 vss!contenterror = 0 1 vss!contenterror = 1 bvb boundary violation on channel b ? protocol related variable: vss!bviolation channel b 0 vss!bviolation = 0 1 vss!bviolation = 1 tcb transmission conflict on channel b ? protocol related variable: vss!txconflict channel b 0 vss!txconflict = 0 1 vss!txconflict = 1 vfa valid frame on channel a ? protocol related variable: vss!validframe channel a 0 vss!validframe = 0 1 vss!validframe = 1 sya sync frame indicator channel a ? protocol related variable: vrf!header!syfindicator channel a 0 vrf!header!syfindicator = 0 1 vrf!header!syfindicator = 1 nfa null frame indicator channel a ? protocol related variable: vrf!header!nfindicator channel a 0 vrf!header!nfindicator = 0 1 vrf!header!nfindicator = 1
flexray communication controller freescale semiconductor 26-111 pxs20 microcontroller reference manual, rev. 1 26.6.5.3 message buffer data field description the message buffer data field is used to store the fram e payload data, or a part of it, of the frame to be transmitted to or received from the flexray bus. the minimum required length of this field depends on the message buffer type that the physical message buffer is assigned to and is given in table 26-101 . the structure of the message buffer data field is given in figure 26-128 . note the cc will not access any locations out side the message buffer data field boundaries given by table 26-101 . figure 26-128. message buffer data field structure sua startup frame indicator channel a ? protocol related variable: vrf!header!sufindicator channel a 0 vrf!header!sufindicator = 0 1 vrf!header!sufindicator = 1 sea syntax error on channel a ? protocol related variable: vss!syntaxerror channel a 0 vss!syntaxerror = 0 1 vss!syntaxerror = 1 cea content error on channel a ? protocol related variable: vss!contenterror channel a 0 vss!contenterror = 0 1 vss!contenterror = 1 bva boundary violation on channel a ? protocol related variable: vss!bviolation channel a 0 vss!bviolation = 0 1 vss!bviolation = 1 tca transmission conflict on channel a ? protocol related variable: vss!txconflict channel a 0 vss!txconflict = 0 1 vss!txconflict = 1 table 26-101. message buffer data field minimum length physical message buffer assigned to minimum length defined by individual message buffer in segment 1 fr_mbdsr[mbseg1ds] receive shadow buffer in segment 1 fr_mbdsr[mbseg1ds] individual message buffer in segment 2 fr_mbdsr[mbseg2ds] receive shadow buffer in segment 2 fr_mbdsr[mbseg2ds] receive fifo for channel a fr_rfdsr[entry_size] (fr_rfwmsr[sel] = 0) receive fifo for channel b fr_rfdsr[entry_size] (fr_rfwmsr[sel] = 1) 0123456789101112131415 0x0 data0 / mid0 / nmv0 data1 / mid1 / nmv1 0x2 data2 / nmv2 data3 / nmv3 ... ... ... 0xn- 2 data n-2 data n-1 table 26-100. transmit message buffer slot status structure field descriptions field description
flexray communication controller 26-112 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 the message buffer data field is located in the flex ray memory area; thus, the cc has no means to control application write access to the field. to ensure data consistency, the a pplication must follow a write and read access scheme. 26.6.5.3.1 message buffer data field read access for transmit message buffers, the cc will not modify the content of th e message buffer data field. thus the application can read back the data at a ny time without any impact on data consistency. for receive message buffers the application must lock the related re ceive message buffer and retrieve the message buffer header index from the message buffer index registers (fr_mbidxrn) . while the message buffer is locked, the cc will not update the message buffer data field. for receive fifos, the application can read the message buffer indicated by the receive fifo a read index register (fr_rfarir) or the receive fifo b read inde x register (fr_rfbrir) when the related fill levels in the receive fifo fill level and po p count register (fr_rfflpcr) indicate an non-empty fifo. 26.6.5.3.2 message buffer data field write access for receive message buffers, receive shadow buffers, a nd receive fifos, the application must not write to the message buffer data field. for transmit message buffers, the application must follow the write access restrictions given in table 26-102 . table 26-102. frame data write access constraints field single buffered double buffered commit side transmit side data, mid, nmv poc:config or mb_dis or mb_lck poc:config or mb_dis or mb_lck poc:config or mb_dis table 26-103. frame data field descriptions field description data 0, data 1, ... data n-1 message data ? provides the message data received or to be transmitted. for receive message buffer and receive fifos, this field provides the message data received for this message buffer. for transmit message buffers, the field provides the message data to be transmitted. mid 0, mid 1 message identifier ? if the payload preamble bit ppi is set in the message buffer frame header, the mid field holds the message id of a dynamic frame locate d in the message buffer. the receive fifo filter uses the received message id for message id filtering. nmv 0, nmv 1, ... nmv 11 network management vector ? if the payload preambl e bit ppi is set in the message buffer frame header, the network management vector field holds the network management vector of a static frame located in the message buffer. note: the mid and nmv bytes replace the corresponding data bytes.
flexray communication controller freescale semiconductor 26-113 pxs20 microcontroller reference manual, rev. 1 26.6.6 individual message bu ffer functional description the cc provides three basic types of individual message buffers: 1. single transmit message buffers 2. double transmit message buffers 3. receive message buffers before an individual message buffer can be used, it must be configured by the appl ication. after the initial configuration, the message buffer can be reconfigured later. the set of the configuration data for individual message buffers is given in section 26.6.3.4.1, individual message buffer configuration data . 26.6.6.1 individual messag e buffer configuration the individual message buffer configur ation consists of two steps. the fi rst step is the allocation of the required amount of memory for the flexray memory area. the second step is the programming of the message buffer configuration registers, which is described in this section. 26.6.6.1.1 common configuration data one part of the message buffer c onfiguration data is common to all individual message buffers and the receive shadow buffers. these data can onl y be set when the protocol is in the poc:config state. the application configures the num ber of utilized individual messag e buffers by writing the message buffer number of the last utilized message buffer into the last_mb_util field in the message buffer segment size and utilizati on register (fr_mbssutr) . the application configures the si ze of the two segments of individual message buffers by writing the message buffer number of the last me ssage buffer in the first segment into the last_mb_seg1 field in the message buffer segment size and utilization regist er (fr_mbssutr) the application configures the length of the message buffer data fields for both of the message buffer segments by writing to the mbseg2ds and mbseg1ds fields in the message buffer data size register (fr_mbdsr) . depending on the current receive functionality of th e cc, the application must configure the receive shadow buffers. for each se gment and for each channel with at least one indivi dual receive message buffer assigned, the application must configure th e related receive shadow buffer using the receive shadow buffer index register (fr_rsbir) . 26.6.6.1.2 specific configuration data the second part of the message buffer configur ation data is specific for each message buffer. these data can be cha nged only when either ? the protocol is in the poc:config state or ? the message buffer is disabl ed, i.e. fr_mbccsrn[eds] = 0 the individual message buffer type is defined by the mtd and mbt bits in the message buffer configuration, control, stat us registers (fr_mbccsrn) as given in table 26-104 .
flexray communication controller 26-114 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 the message buffer specific configuration data are 1. mcm, mbt, mtd bits in message buffer configuration, control, status registers (fr_mbccsrn) 2. all fields and bits in message buffer cycle counter filter registers (fr_mbccfrn) 3. all fields and bits in message buffer frame id registers (fr_mbfidrn) 4. all fields and bits in message buffer index registers (fr_mbidxrn) the meaning of the specific configurat ion data depends on the message buffe r type, as given in the detailed message buffer type descriptions section 26.6.6.2, single transmit message buffers , section 26.6.6.3, receive message buffers , and section 26.6.6.4, double transmit message buffer . 26.6.6.2 single transmit message buffers the section provides a detail ed description of the func tionality of single buffered transmit message buffers. a single transmit message buffer is used by the application to provide mess age data to the cc that will be transmitted over the flexray bus. th e cc uses the transmit message buffers to pr ovide information about the transmission process a nd status information about the slot in which message was transmitted. the individual message buffer with message buffer number n is configured to be a single transmit message buffer by the following settings: ? fr_mbccsrn[mbt] = 0 (single buffered message buffer) ? fr_mbccsrn[mtd] = 1 (t ransmit message buffer) 26.6.6.2.1 access regions to certain message buffer fields, both the application and the cc have access. to ensure data consistency, a message buffer locking scheme is implemented, which is used to control the acce ss to the data, control, and status bits of a message buffer. the access regions for single transm it message buffers are depicted in figure 26-129 . a description of the regions is given in table 26-105 . if an region is ac tive as indicated in table 26-106 , the access scheme given for that re gion applies to the message buffer. table 26-104. individual message buffer types fr_mbccsrn individual message buffer description mtd mbt 0 0 receive message buffer 01 reserved 1 0 single transmit message buffer 1 1 double transmit message buffer
flexray communication controller freescale semiconductor 26-115 pxs20 microcontroller reference manual, rev. 1 figure 26-129. single transmit message buffer access regions the trigger bits fr_mbccsrn[e dt] and fr_mbccsrn[lckt], and the interrupt enable bit fr_mbccsrn[mbie] are not under access control and can be accessed from the application at any time. the status bits fr_mbccsrn[eds] and fr_mbccsrn[lcks] are not under access contro l and can be accessed from the cc at any time. the interrupt flag fr_mbccsrn[mbif] is not unde r access control and can be accessed from the application and the cc at any time. cc clear access has higher priority. the cc restricts its access to the regions depending on the current state of the message buffer. the application must adhere to these re strictions in order to ensure data consistency. the transmit message buffer states are given in figure 26-130 . a description of the states is given in table 26-106 , which also provides the access scheme for the access regions. the status bits fr_mbccsrn[eds] and fr_mbcc srn[lcks] provide the application with the required message buffer status inform ation. the internal status informati on is not visible to the application. 26.6.6.2.2 message buffer states this section describes the transmit message buffer states and provides a state diagram. table 26-105. single transmit message buffer access regions description region access from region used for application module cfg read/write ? message buffer configuration msg read/write ? message data and slot status access nf ? read-only message header access for null frame transmission tx ? read/write message transmi ssion and slot status update cm ? read-only message buffer validation sr ? read-only message buffer search message buffer data field: data[0-n] message buffer header field: frame header fr_mbccsrn[cmt] message buffer header field: slot status message buffer header field: data field offset fr_mbccfrn[mtm/cha/chb/ccf*] fr_mbfidrn[fid] fr_mbidxrn[mbidx] fr_mbccsrn[mbt/mtd] tx nf cmt sr cfg msg
flexray communication controller 26-116 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 26-130. single transmit message buffer states table 26-106. single transmit message buffer state description state fr_mbccsrn access region description eds lcks appl. modul e idle 1 0 ? cm, sr idle - message buffer is idle. included in message buffer search. hdis 0 0 cfg ? dis abled - message buffer under configuration. excluded from message buffer search. hdislck 0 1 cfg ? dis abled and l ock ed - message buffer under configuration. excluded from message buffer search. hlck 1 1 msg sr l ock ed - applications access to data, control, and status. included in message buffer search. ccsa 1 0 ? ? s lot a ssigned - message buffer assi gned to next static slot. ready for null frame transmission. hlckccsa 1 1 msg ? l ock ed and s lot a ssigned - applications access to data, control, and status.message buffer assigned to next static slot ccnf 1 0 ? nf n ull f rame transmission header is used for null frame transmission. hlckccnf 1 1 msg nf l ock ed and n ull f rame transmission - applications access to data, control, and status. h eader is used for null frame transmission. ccma 1 0 ? cm m essage a vailable - message buffer is assigned to next slot and cycle counter filter matches. hlckccma 1 1 msg ? l ock ed and m essage a vailable - applications access to data, control, and status. message buffer is assigned to next slot and cycle counter filter matches. cctx 1 0 ? tx message t ransmission - message buffer data transmit. payload data from buffer transmitted hdis reset_state hd he idle sa dss su ccsu ccsa cctx tx hlck hlckccsa ccnf hl hu ccma hl hu hlckccnf hlckccma sss sts he hl sts hu hl dss ma sss hdislck hd hu hl hu sts ma sss sa dss sts dss
flexray communication controller freescale semiconductor 26-117 pxs20 microcontroller reference manual, rev. 1 26.6.6.2.3 message buffer transitions application transitions the application transitions can be triggered by the a pplication using the commands described in table 26-107 . the application issues the commands by writing to the message buffer configuration, control, status registers (fr_mbccsrn) . only one command can be issued with one write access. each command is executed immediately. if the command is ignored, it must be issued again. message buffer enable and disable the enable and disable commands issued by wri ting 1 to the trigger bit fr_mbccsrn[edt]. the transition that will be triggered by each of these command depends on th e current value of the status bit fr_mbccsrn[eds]. if the command triggers the disa ble transition hd and the message buffer is in one of the states ccsa, hlckccsa, ccma, hlckccma, ccnf, hlckccnf, or cctx, the disable transition has no effect (command is ignored) and the message buf fer state is not changed. no notification is given to the application.if the co mmunication controller is started as a non-coldstar t node and configured and enabled message buffers in the poc config state for slot 1, then the message buf fer can not be disabled in the integration_listen state by directly writing '1' to the edt bit. to facilitate this, a freeze command needs to be issued just before running the message buffer di sable for slot 1. th is should enable the message buffer disable during the listen states. message buffer lock and unlock the lock and unlock commands issued by writi ng 1 to the trigger bit fr_mbccsrn[lckt]. the transition that will be triggered by each of these commands depends on th e current value of the status bit fr_mbccsrn[lcks]. if the command triggers the lock transition hl and the message buffer is in the state cctx, the lock transition has no effect (command is ignored) and me ssage buffer state is not changed. in this case, the message buffer lock error flag lck_ef in the chi error flag register (fr_chierfr) is set. ccsu 1 0 ? tx s tatus u pdate - message buffer status update. update of status flags, the slot status field, and the header index. table 26-107. single transmit message buffer application transitions transition command condition description he fr_mbccsrn[edt]:= 1 fr_mbccsrn[eds] = 0 application triggers message buffer enable. hd fr_mbccsrn[eds] = 1 application triggers message buffer disable. hl fr_mbccsrn[lckt]:= 1 fr_mbccsrn[lcks] = 0 application triggers message buffer lock. hu fr_mbccsrn[lcks] = 1 application triggers message buffer unlock. table 26-106. single transmit message buffer state description (continued) state fr_mbccsrn access region description eds lcks appl. modul e
flexray communication controller 26-118 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 module transitions the module transitions that can be tr iggered by the cc are described in table 26-108 . each transition will be triggered for certain message buffers when the related condition is fulfilled. transition priorities the application can trigger only one transition at a time. there is no need to specify priorities among them. as shown in the first part of table 26-109 , the module transitions have a higher priority than the application transitions. for all st ates except the ccma state, both a lock/unlock transition hl/hd and a module transition can be executed at the same time. the result stat e is reached by first applying the application transition and subsequently the module transition to th e intermediately reached state. for example, if the message buffer is in the hlck state and the application unlocks the message buffer by the hu transition and the module triggers th e slot assigned transiti on sa, the intermediate state is idle and the resulting state is ccsa. the priorities among the module transiti ons is given in the second part of table 26-109 . table 26-108. single transmit message buffer module transitions transition condition description sa slot match and static slot s lot a ssigned - message buffer is assigned to next static slot. ma slot match and cyclecounter match m essage a vailable - message buffer is assigned to next slot and cycle counter filter matches. tx slot start and fr_mbccsrn[cmt] = 1 t ransmission slot start - slot start and commit bit cmt is set. in case of a dynamic slot, platesttx is not exceeded. su status updated s tatus u pdated - slot status field and message buffer status flags updated. interrupt flag set. sts static slot start st atic slot s tart - start of static slot. dss dynamic slot start or symbol window start or nit start d ynamic slot or s egment s tart. - start of dynamic slot or symbol window or nit. sss slot start or symbol window start or nit start s lot or s egment s tart - start of static slot or dynamic slot or symbol window or nit. table 26-109. single transmit message buffer transition priorities state priorities description module vs. application idle, hlck sa > hd ma > hd slot assigned > message buffer disable message available > me ssage buffer disable ccma tx > hl transmission start > message buffer lock module internal idle, hlck ma > sa message available > slot assigned ccma tx > sts tx > dss transmission slot start > static slot start transmission slot start > dynamic slot start
flexray communication controller freescale semiconductor 26-119 pxs20 microcontroller reference manual, rev. 1 26.6.6.2.4 transmit message setup to transmit a message over the flex ray bus, the application writes the message data into the message buffer data field and sets the commit bit cmt in the message buffer configuration, control, status registers (fr_mbccsrn) . the physical access to the message buf fer data field is described in section 26.6.3.1, individua l message buffers . as indicated by table 26-106 , the application shall write to the me ssage buffer data field and change the commit bit cmt only if the transmit message buffer is in one of the states hdis, hdislck, hlck, hlckccsa, hlckccma, or hlckccma. the application can change the state of a message buffer if it issues the appropriate commands shown in table 26-107 . the state change is indicated through the fr_mbccsrn[eds] and fr_mbcc srn[lcks] status bits. if the transmit message buffer ente rs one of the states hdis, hdislck, hlck, hlckccsa, hlckccma, or hlckccma the fr_mbccsrn[d val] flag is negated. 26.6.6.2.5 message transmission as a result of the message buffer search described in section 26.6.7, individual message buffer search , the cc triggers the message availabl e transition ma for up to two transm it message buffers. this changes the message buffer state from idle to ccma and the me ssage buffers can be used for message transmission in the next slot. the cc transmits a message from a me ssage buffer if both of the followi ng two conditions are fulfilled at the start of the transmission slot: 1. the message buffer is in th e message available state ccma 2. the message data are still va lid, i.e. fr_mbccsrn[cmt] = 1 in this case, the cc triggers the tx transition and changes the message buffer state to cctx. a transmit message buffer timing and state change diag ram for message transmission is given in figure 26-131 . in this example, the message buffer with message buffer number n is idle at the start of the search slot, matches the slot and cycle number of the next slot, and message buffer data are valid, i.e. fr_mbccsrn[cmt] = 1. figure 26-131. message transmission timing search[s+1] m t s ta r t ma slot s tx su ccma cctx slot s+1 idle m t s ta r t idle slot s+2 slot start slot start slot start m t s ta r t message transmit sss ccsu
flexray communication controller 26-120 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 26-132. message transmission from hlck state with unlock the amount of message data read from the flexray me mory area and transferred to the flexray bus is determined by the following three items 1. the message buffer segment that the message buffer is assigned to, as defined by the message buffer segment size and utiliz ation register (fr_mbssutr) . 2. the message buffer data field size, as defined by the related field of the message buffer data size register (fr_mbdsr) . 3. the value of the pldlen field in the me ssage buffer header field, as described in section 26.6.5.2.1, frame header description . if a message buffer is assigned to message buf fer segment 1, and pldlen > mbseg1ds, then 2 * mbseg1ds bytes will be read from the message buffer data field and zero padding is used for the remaining bytes for the flexray bus transfer. if pldlen <= mbseg1ds, the cc reads and transfers 2*pldlen bytes. the same holds for segment 2 and mbseg2ds. 26.6.6.2.6 null fr ame transmission a static slot with slot num ber s is assigned to the cc for channel a, if at least one transmit message buffer is configured with the fr_mbfidrn[fid] set to s and fr_mbccfrn[cha] set to 1. a null frame is transmitted in the static slot s on channel a, if this slot is assigned to the cc for channel a, and all transmit message buffers with fr_mbfidrn[fid] = s and fr_mbccfrn[cha] = 1 are either not committed, i.e fr_mbccsrn[cmt] = 0, or lock ed by the application, i.e. fr_m bccsrn[lcks] = 1, or the cycle counter filter is enabled and does not match. additionally, the application can clear the commit bit of a message buf fer that is in the ccma state, which is called uncommit or transmit abort . this message buffer will be used for null frame transmission. as a result of the message buffer search described in section 26.6.7, individual message buffer search , the cc triggers the slot assigned transition sa for up to two transmit message buffers if at least one of the conditions mentioned above is fulfi lled for these message buffers. the transition sa changes the message buffer states from either idle to ccsa or from hl ck to hlckccsa. in each cas e, these message buffers will be used for null frame transmi ssion in the next slot. a message buf fer timing and state change diagram for null frame transmission from idle state is given in figure 26-133 . search[s+1] mt st a rt m t s ta r t ma slot s tx sss hlckccma cctx slot s+1 hlck m t st a r t idle slot s+2 slot start slot start slot start hu ccma message transmit
flexray communication controller freescale semiconductor 26-121 pxs20 microcontroller reference manual, rev. 1 figure 26-133. null frame transmission from idle state a message buffer timing and state ch ange diagram for null frame transm ission from hlck state is given in figure 26-134 . figure 26-134. null frame transmission from hlck state if a transmit message buffer is in the ccsa or hlckcc sa state at the start of the transmission slot, a null frame is transmitted in any case, even if the me ssage buffer is unlocked or committed before the transmission slot starts. a tran smit message buffer timing and stat e change diagra m for null frame transmission for this case is given in figure 26-135 . figure 26-135. null frame transmission from hlck state with unlock since the null frame transmission will not use the messa ge buffer data, the appli cation can lock/unlock the message buffer during null frame tr ansmission. a transmit message buffer timing and state change diagram for null frame transmissi on for this case is given in figure 26-136 . search[s+1] m t s t ar t mt start sa slot s sts sss ccsa ccnf slot s+1 idle m t s ta r t idle slot s+2 slot start slot start slot start null frame transmit search[s+1] m t s ta r t m t s ta r t sa slot s sts sss hlckccsa hlckccnf slot s+1 hlck m t start hlck slot s+2 slot start slot start slot start null frame transmit search[s+1] mt star t m t s t art sa slot s sts sss hlckccsa ccnf slot s+1 hlck m t start idle slot s+2 slot start slot start slot start hu ccsa null frame transmit
flexray communication controller 26-122 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 26-136. null frame transmission from idle state with locking 26.6.6.2.7 message buffer status update after the end of each slot, the pe generates the sl ot status vector. depending on the this status, the transmitted frame type, and the amount of transmitted data, the message buffer status is updated. message buffer status update a fter complete message transmission the term complete message transmissi on refers to the fact that all payload data stored in the message buffer were send to flexray bus. in this case, the cc updates the slot status field of the message buffer and triggers the status updated transition su. with the su transition, the cc sets the message buffer interrupt flag fr_mbccsrn[mbif] to indi cate the successful message transmission. depending on the transmission mode flag fr_mbcc frn[mtm], the cc cha nges the commit flag fr_mbccsrn[cmt] and the valid flag fr_mbccs rn[dval]. if the fr_mbccfrn[mtm] flag is negated, the message buffer is in the event transmission mode. in this case, each committed message is transmitted only once. the commit flag fr_mbccsrn[ cmt] is cleared with the su transition. if the fr_mbccfrn[mtm] flag is asserted, the message buffer is in the state transmission mode . in this case, each committed message is transmitted as long as the application provides new da ta or locks the message buffers. the cc will not clear the fr_mbccsrn[cmt] flag at the end of tran smission and will set the valid flag fr_mbccsrn[dval] to indicate th at the message will be transmitted again. message buffer status update a fter incomplete message transmission the term incomplete message transmission refers to the fact that not all payload data that should be transmitted were send to flexray bus. this may be caused by the following regular conditions in the dynamic segment: 1. the transmission slot starts in a minisl ot with a minislot number greater than platesttx . 2. the transmission slot did not ex ist in the dynamic segment at all. additionally, an incomplete message transmission can be caused by internal communication errors. if those error occur, the protocol engine communicati on failure interrupt flag pecf_if is set in the protocol interrupt flag register 1 (fr_pifr1) . in any of these two cases, the status of the message buffer is not ch anged at all with th e su transition. the slot status field is not updated, the status and contro l flags are not changed, and th e interrupt flag is not set. search[s+1] m t s ta r t mt st a rt sa slot s sts sss slot s+1 idle mt start hlck slot s+2 slot start slot start slot start null frame transmit hl ccsa ccnf hlckccnf
flexray communication controller freescale semiconductor 26-123 pxs20 microcontroller reference manual, rev. 1 message buffer status update after null frame transmission after the transmission of a null fram e, the status of the message buffe r that was used for the null frame transmission is not changed at all. the slot status field is not updated, the status and control flags are not changed, and the interrupt flag is not set. 26.6.6.3 receive message buffers the section provides a detailed descri ption of the functionality of the receive message buffers. if receive message buffers are used it is re quired to configure the related receive shadow buffer as described in section 26.6.3.2, receive shadow buffers . a receive message buffer is used to receive a message from the flex ray bus based on individual filter criteria. the cc uses the receive message buffer to provide the following data to the application 1. message data received 2. information about the reception process 3. status information about the slot in which the message was received a individual message buffer with message buffer number n is configured as a receive message buffer by the following configuration settings ? fr_mbccsrn[mbt] = 0 (single buffered message buffer) ? fr_mbccsrn[mtd] = 0 (receive message buffer) to certain message buffer fields, both the application and the cc have access. to ensure data consistency, a message buffer locking scheme is im plemented that is used to control the access to the data, control, and status bits of a message buffer. the access regi ons for receive message buf fers are depicted in figure 26-137 . a description of the regions is given in table 26-110 . if an region is active as indicated in table 26-111 , the access scheme given for that region applies to the message buffer. figure 26-137. receive message buffer access regions message buffer data field: data[0-n] message buffer header field: frame header fr_mbccsrn[dval/dup] message buffer header field: slot status message buffer header field: data field offset fr_mbccfrn[cha/chb/ccf*] fr_mbfidrn[fid] fr_mbidxrn[mbidx] fr_mbccsrn[mtd] rx sr cfg msg
flexray communication controller 26-124 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 the trigger bits fr_mbccsrn[e dt] and fr_mbccsrn[lckt] and the interrupt enable bit fr_mbccsrn[mbie] are not under access control and can be accessed from the application at any time. the status bits fr_mbccsrn[eds] and fr_mbccsrn[lcks] are not under access contro l and can be accessed from the cc at any time. the interrupt flag fr_mbccsrn[mbif] is not unde r access control and can be accessed from the application and the cc at any time. cc set access has higher priority. the cc restricts its access to the regions depending on the current state of the message buffer. the application must adhere to these re strictions in order to ensure data consistency. th e receive message buffer states are given in figure 26-138 . a description of the message buffer states is given in table 26-106 , which also provides the access scheme for the access regions. the status bits fr_mbccsrn[eds] and fr_mbcc srn[lcks] provide the application with the required status information. the internal status information is not visible to the application. figure 26-138. receive message buffer states table 26-110. receive message buffer access region description region access from region used for application module cfg read/write ? message buffer configur ation, message data and status access msg read/write ? message data, header, and status access rx ? write-only message reception and status update sr ? read-only message buffer search data table 26-111. receive message buffer states and access state fr_mbccsrn access from description eds lcks appl. modul e idle 1 0 ? sr idle - message buffer is idle. included in message buffer search. hdis 0 0 cfg ? dis abled - message buffer under configuration. excluded from message buffer search. hdis reset_state hd he idle bs sns su ccsu ccbs ccrx hlck hlckccbs hlckccrx sss sls he hl hdislck hd hl hu bs sns hl hu hu hl hu sls sss
flexray communication controller freescale semiconductor 26-125 pxs20 microcontroller reference manual, rev. 1 26.6.6.3.1 message buffer transitions application transitions the application transitions that ca n be triggered by the application using the commands described in table 26-112 . the application issues the commands by writing to the message buffer configuration, control, status registers (fr_mbccsrn) . only one command can be issued with one write access. each command is executed immediately. if the command is ignored, it must be issued again. message buffer enable and disable the enable and disable commands issued by wri ting 1 to the trigger bit fr_mbccsrn[edt]. the transition that will be triggered by each of these command depends on th e current value of the status bit fr_mbccsrn[eds]. if the command triggers the disa ble transition hd and the message buffer is in one of the states ccbs, hlckccbs, or ccrx, the disabl e transition has no effect (command is ignored) and the message buffer state is not changed. no notificat ion is given to the appl ication.if the communication controller is started as a non-coldstart node and confi gured and enabled message buf fers in the poc config state for slot 1, then the message buffer can not be disabled in the in tegration_listen state by directly writing '1' to the edt bit. to facilitate this, a freeze command needs to be issued just before running the message buffer disable for slot 1. this should enable the message buffer disable during the listen states. message buffer lock and unlock the lock and unlock commands issued by writi ng 1 to the trigger bit fr_mbccsrn[lckt]. the transition that will be triggered by each of these commands depends on th e current value of the status bit fr_mbccsrn[lcks]. if the command triggers the lock transition hl while the message buffer is in the state ccrx, the lock transition has no effect (com mand is ignored) and message buffer state is not hdislck 0 1 cfg ? dis abled and l ock ed - message buffer under configuration. excluded from message buffer search. hlck 1 1 msg ? l ock ed - applications access to data, control, and status. included in message buffer search. ccbs 10?? b uffer s ubscribed - message buffer subscribed for reception. filter matches next (slot, cycle, channel) tuple. hlckccbs 1 1 msg ? l ock ed and b uffer s ubscribed - applications access to data, control, and status. message buffer subscribed for reception. ccrx 1 0 ? ? message r eceive - message data received into related shadow buffer. hlckccrx 1 1 msg ? l ock ed and message r eceive - applications access to data, control, and status. message da ta received into related shadow buffer. ccsu 1 0 ? rx s tatus u pdate - message buffer status update. update of status flags, the slot status field, and the header index. table 26-111. receive message buffer states and access (continued) state fr_mbccsrn access from description eds lcks appl. modul e
flexray communication controller 26-126 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 changed. in this case, the message buffer lock error flag lck_ef in the chi error flag register (fr_chierfr) is set. module transitions the module transitions that can be tr iggered by the cc are described in table 26-113 . each transition will be triggered for certain message buffers when the related condition is fulfilled. transition priorities the application can tr igger only one transition at a time. there is no need to sp ecify priorities among them. as shown in table 26-114 , the module transitions have a higher priority than th e application transitions. for all states except the ccrx stat e, a module transition and the appli cation lock/unlock transition hl/hu and can be executed at the same ti me. the result state is reached by first applying the module transition and subsequently the application tran sition to the intermediately reached state. for example, if the message buffer is in the buffer subscribed state ccbs and the module triggers the slot st art transition sls at the same time as the applicat ion locks the message buffer by the hl transition, the in termediate state is ccrx and the resulting state is locked buffer subscribed state hlckccrx. table 26-112. receive message buffer application transitions transition host command condition description he fr_mbccsrn[edt]:= 1 fr_mbccsrn[eds] = 0 application triggers message buffer enable. hd fr_mbccsrn[eds] = 1 application triggers message buffer disable. hl fr_mbccsrn[lckt]:= 1 fr_mbccsrn[lcks] = 0 a pplication triggers message buffer lock. hu fr_mbccsrn[lcks] = 1 application triggers message buffer unlock. table 26-113. receive message buffer module transitions transition condition description bs slot match and cyclecounter match b uffer s ubscribed - the message buffer f ilter matches next slot and cycle. sls slot start sl ot s tart - start of either static slot or dynamic slot. sns symbol window start or nit start s ymbol window or n it s tart - start of either symbol window or nit. sss slot start or symbol window start or nit start sl ot or s egment s tart - start of either static slot, dynamic slot, symbol window, or nit. su status updated s tatus u pdated - slot status field, messa ge buffer status flags, header index updated. interrupt flag set. table 26-114. receive message buffer transition priorities state priorities description module vs. application idle bs > hd buffer subscribed > message buffer disable hlck bs > hd buffer subscribed > message buffer disable
flexray communication controller freescale semiconductor 26-127 pxs20 microcontroller reference manual, rev. 1 26.6.6.3.2 message reception as a result of the message buffer search, the cc ch anges the state of up to two enabled receive message buffers from either idle state idle or locked state hlck to the either subscribed state ccbs or locked buffer subscribed state hlckccbs by triggering the buffer subscribed transition bs. if the receive message buffers for the next slot are assigned to both channels, then at most one receive message buffer is changed to a buffer subscribed state . if more than one matching message buffers assigned to a certain channe l, then only the message buffer with the lowest message buffer number is in one of the states mentioned above. with the start of the next static or dynamic slot the module trigger th e slot start transition sls. this changes the state of the subscribed receive messa ge buffers from either ccbs to ccrx or from hlckccbs to hlckccrx, respectively. during the reception slot, the recei ved frame data are written into the shadow buffers. for details on receive shadow buffers, see section 26.6.6.3.5, receive sha dow buffers concept . the data and status of the receive message buffers that are the ccrx or hlckccrx are not modified in the reception slot. 26.6.6.3.3 message buffer update with the start of the next static or dynamic slot or with th e start of the symbol wi ndow or nit, the module triggers the slot or segment start transition sss. this transition change s the state of the receiving receive message buffers from either ccrx to ccs u or from hlckccrx to hlck, respectively. if a message buffer was in the locked state hlckccr x, no update will be perfor med. the received data are lost. this is indica ted by setting the frame lost channel a/ b error flag frla_e f/frlb_ef in the chi error flag register (fr_chierfr) . if a message buffer was in th e ccrx state it is now in the ccsu state. after the evaluation of the slot status provided by the pe the message buffe r is updated. the message buffer upda te depends on the slot status bits and the segment the message buffer is assigned to. this is described in table 26-115 . ccrx sss > hl slot or segment start > message buffer lock table 26-115. receive message buffer update vss!validframe vrf!header!nfin dicator update description 1 1 valid non-null frame received. - message buffer data field updated. - frame header field updated. - slot status field updated. - dup:= 1 - dval:= 1 - mbif:= 1 table 26-114. receive message buffer transition priorities (continued) state priorities description
flexray communication controller 26-128 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 note if the number of the last slot in th e current communication cycle on a given channel is n , then all receive message buffers assigned to this channel with fr_mbfidrn[fid] > n will not be updated at all. when the receive message buffer update has finished the status updated transition su is triggered, which changes the buffer state from ccsu to idle. an exam ple receive message buffer timing and state change diagram for a normal fram e reception is given in figure 26-139 . figure 26-139. message reception timing the amount of message data written into the message buffer data field of the receive shadow buffer is determined by the following two items: 1. the message buffer segment that the messag e buffer is assigned to, as defined by the message buffer segment size and utiliz ation register (fr_mbssutr) . 2. the message buffer data field size, as defined by the related field of the message buffer data size register (fr_mbdsr) 3. the number of bytes received over the flexray bus if the message buffer is assigned to the message buf fer segment 1, and the number of received bytes is greater than 2*fr_mbdsr.mbseg1ds, the cc writ es only 2*fr_mbdsr.mbseg1ds bytes into the 1 0 valid null frame received. - message buffer data field not updated. - frame header field not updated. - slot status field updated. - dup:= 0 - dval not changed - mbif:= 1 0 x no valid frame received. - message buffer data field not updated. - frame header field not updated. - slot status field updated. - dup:= 0 - dval not changed. - mbif:= 1, if the slot was not an empty dynamic slot. note: an empty dynamic slot is indicated by the following frame and slot status bit values: vss!validframe = 0 and vss!syntaxerror = 0 and vss!contenterror = 0 and vss!bviolation = 0. table 26-115. receive message buffer update (continued) vss!validframe vrf!header!nfin dicator update description search[s+1] mt st ar t bs slot s sls su ccbs ccrx slot s+1 idle mt sta r t idle slot s+2 slot start slot start mt st ar t message receive to receive shadow buffer sss ccsu slot start
flexray communication controller freescale semiconductor 26-129 pxs20 microcontroller reference manual, rev. 1 message buffer data field of the receive shadow buf fer. if the number of received bytes is less than 2*fr_mbdsr.mbseg1ds, the cc writ es only the received number of byt es and will not change the trailing bytes in the message buffer da ta field of the receive shadow buffe r. the same holds for the message buffer segment 2 with fr_mbdsr.mbseg2ds. 26.6.6.3.4 received message access to access the message data received over the flexray bus, the application reads the message data stored in the message buffer data field of the corresponding receive message buffer. the access to the message buffer data field is described in section 26.6.3.1, individual message buffers . the application can read the message buffer data field if the receive me ssage buffer is one of the states hdis, hdislck, or hlck. if th e message buffer is in one of these states, the cc w ill not change the content of the message buffer. 26.6.6.3.5 receive shadow buffers concept the receive shadow buffer concept applies only to individua l receive message buffers. the intention of this concept is to ensure that only syntactically and se mantically valid received non-null frames are presented to the application in a receive message buffer. the basic structure of a receive shadow buffer is described in section 26.6.3.2, receive shadow buffers . the receive shadow buffers temporar ily store the received frame header and message data. after the slot boundary the slot status information is generated. if the slot status info rmation indicates the reception of the valid non-null frame (see table 26-115 ), the cc writes the slot status into the slot status field of the receive shadow buffer and exchanges the content of the message buffer index registers (fr_mbidxrn) with the content of the corresponding internal shadow buffer index register. in all other cases, the cc writes the slot status into the identified receiv e message buffer, depending on the slot status and the flexray segment the message buffer is assigned to. the shadow buffer concept, with its index exchange, results in the fact that the flexray memory area located message buffer associated to an individua l receive message buffer changes after successful reception of a valid frame. this mean s that the message buffer area in the flexray memory area accessed by the application for reading the re ceived message is different from th e initial setting of the message buffer. therefore, the application must not rely on the index inform ation written initially into the message buffer index registers (fr_mbidxrn) . instead, the index of the messag e buffer header field must be fetched from the message buffer index registers (fr_mbidxrn) . 26.6.6.4 double transmit message buffer the section provides a detailed description of the functionality of the double transmit message buffers. double transmit message buffers are used by the applic ation to provide the cc with the message data to be transmitted over the flexray bus. the cc uses th is message buffer to pr ovide information to the application about the transmission pr ocess, and status information about the slot in which message data was transmitted.
flexray communication controller 26-130 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 in contrast to the single transmit message buffers, the application can provide new transmis sion data while the transmission of the previously provided message data is running. this scheme is called double buffering and can be considered as a fifo of depth 2. double transmit message buffers are implemented by combining two indi vidual message buff ers that form the two sides of an double transmit me ssage buffer. one side is called the commit side and will be accessed by the application to provi de the message data. the other side is called the transmit side and is used by the cc to transmit the message data to the flexray bus . the two sides are located in adjacent individual message buffers. the message buffer th at implements the commit side ha s an even message buffer number 2n. the transmit side message buffer follows the com mit side message buffer and has the message buffer number 2n+1. the basic structure and data flow of a double transmit message buffer is given in figure 26-140 . figure 26-140. double transmit buffer structure and data flow note both the commit and the transmit side must be configured with identical values except for the message buffer index registers (fr_mbidxrn) . 26.6.6.4.1 access regions to certain message buffer fields, both the application and the cc have access. to ensure data consistency, a message buffer locking scheme is implemented, which controls the excl usive access to the data, control, and status bits of the message buffer. the access scheme for double transmit message buffers is depicted in figure 26-141 . the given regions represent fields that can be accessed from both th e application and the cc and, thus, require access restrictions. a description of the regions is given in table 26-116 . commit side transmit side application flexray bus mb# 2n mb# 2n+1 internal message transfer message data message data message data
flexray communication controller freescale semiconductor 26-131 pxs20 microcontroller reference manual, rev. 1 figure 26-141. double transmit message buffer access regions layout the trigger bits fr_mbccsrn[e dt] and fr_mbccsrn[lckt], and the interrupt enable bit fr_mbccsrn[mbie] are not under access control and can be accessed from the application at any time. the status bits fr_mbccsrn[eds] and fr_mbccsrn[lcks] are not under access contro l and can be accessed from the cc at any time. the interrupt flag fr_mbccsrn[mbif] is not unde r access control and can be accessed from the application and the cc at any time. cc set access has higher priority. the cc restricts its access to the re gions, depending on the current stat e of the corresponding part of the double transmit message buffer. the appl ication must adhere to these restri ctions in order to ensure data consistency. the states for the commit side of a d ouble transmit message buffer are given in figure 26-142 . a description of the states is given in table 26-118 . the states for the transmit side of a double transmit table 26-116. double transmit message buffer access regions description access description region type application module commit side cfg read/write ? message buffer configuration msg read/write ? message buffer data and control access itx ? read/write internal message transfer. ss ? write-only slot status update transmit side cfg read/write ? message buffer configuration sr ? read-only message buffer search tx ? read-only internal message transfer, message transmission ss ? write-only slot status update message buffer data field: data[0-n] message buffer header field: frame header fr_mbccsr(2n)[cmt] message buffer header field: slot status message buffer header field: data field offset fr_mbccfr(2n)[mtm/cha/chb/ccf*] fr_mbfidr(2n)[fid] fr_mbidxr(2n)[mbidx] fr_mbccsr(2n)[mbt/mtd] message buffer data field: data[0-n] message buffer header field: frame header fr_mbccsr(2n+1)[cmt] message buffer header field: slot status message buffer header field: data field offset fr_mbccfr(2n+1)[mtm/cha/chb/ccf*] fr_mbfidr(2n+1)[fid] fr_mbidxr(2n+1)]mbidx] fr_mbccsr(2n+1)[mbt/mtd] commit side transmit side cfg msg cfg itx ss ss sr tx
flexray communication controller 26-132 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 message buffer are given in figure 26-143 . a description of the states is given in table 26-118 . the description tables also provide th e access scheme for the access regions. the status bits fr_mbccsrn[eds] and fr_mbcc srn[lcks] provide the application with the required message buffer status inform ation. the internal status informati on is not visible to the application. 26.6.6.4.2 message buffer states this section describes the transmit message buffer states and provides a state diagram. figure 26-142. double transmit message buffer state diagram (commit side) a description of the states of the commit side of a double transmit mess age buffer is given in table 26-117 . table 26-117. double transmit message buffer state description (commit side) state fr_mbccsr( 2n) access region description eds lcks appl. module common states hdis 0 0 cfg ? dis abled - message buffer under configuration. commit side can not be used for internal message transfer. ccitx 1 0 ? itx i nternal message t ransfer - message buffer data transferred from commit side to transmit side. commit side specific states idle 1 0 ? itx, ss idle - message buffer commit side is idle. commit side can be used for internal message transfer. hdislck 0 1 cfg ss dis abled and l ock ed - message buffer under configuration. commit side can not be used for internal message transfer. hlck 1 1 msg ss l ock ed - applications access to data, control, and status. commit side can not be used for internal message transfer. hdis reset_state hd he idle is ie ccitx hlck he hl hu hdislck hu hd hl
flexray communication controller freescale semiconductor 26-133 pxs20 microcontroller reference manual, rev. 1 figure 26-143. double transmit message buffer state diagram (transmit side) a description of the states of the transmit side of a double transmit messag e buffer is given in table 26-118 . table 26-118. double transmit message buffer state description (transmit side) state fr_mbccsr n access region description eds lcks appl. module common states hdis 0 0 cfg ? dis abled - message buffer under configuration. excluded from message buffer search. ccitx 1 0 ? tx i nternal m essage t ransfer - message buffer data transferred from commit side to transmit side. transmit side specific states idle 1 0 ? sr idle - message buffer transmit side is idle. transmit side is included in message buffer search. ccsa 1 0 ? ? s lot a ssigned - message buffer assi gned to next static slot. ready for null frame transmission. ccsaccitx 1 0 ? tx s lot a ssigned and i nternal m essage t ransfer - message buffer assigned to next static slot and message buffer data transferred from commit side to transmit side. ccnf 1 0 ? tx n ull f rame transmission header is used for null frame transmission. ccnfccitx 1 0 ? tx n ull f rame transmission and i nternal m essage t ransfer - header is used for null frame transmission and message buffer data transferred from co mmit side to transmit side. ccma 1 0 ? ? m essage a vailable - message buffer is assigned to next slot and cycle counter filter matches. ccmaccitx 1 0 ? ? m essage a vailable and i nternal m essage t ransfer - message buffer is assigned to next slot and cycle counter filter matches and message buffer data transf erred from commit side to transmit side. hdis reset_state hd he idle sa dss su ccsu ccsa cctx tx ccitx ccsaccitx ccnf is ie ccma is ie ccnfccitx ccmaccitx sss sts is ie sts ie is dss ma sss
flexray communication controller 26-134 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.6.6.4.3 message buffer transitions application transitions the application transitions that ca n be triggered by the application using the commands described in table 26-119 . the application issues the commands by writing to the message buffer configuration, control, status registers (fr_mbccsrn) . only one command can be issued with one write access. each command is executed immediately. if the command is ignored, it must be issued again. message buffer enable and disable the enable and disable commands can be issued on the transmit side onl y. any enable or disable command issued on the commit side will be ignored without not ification. the tr ansitions that will be triggered depends on the value of the eds bit. the enable and disable commands will affe ct both the commit side and the transmit side at the same time. if the a pplication triggers the disa ble transition hd while the transmit side is in one of the states ccsa, ccsaccitx, cc nf, ccnfccitx, ccma, ccmaccitx, cctx, or ccsu, the disable transition ha s no effect (command is ignored) an d the message buffer state is not changed. no notification is given to the application. message buffer lock and unlock the lock and unlock commands can be issued on th e commit side only. any lock or unlock command issued on the transmit side will be ignored and th e double transmit buffer lock error flag dbl_ef in the chi error flag register (fr_chierfr) will be set. the transitions that will be trigge red depends on the current value of the lcks bit. th e lock and unlock commands will onl y affect the commit side. if the application triggers the lock transi tion hl while the commit side is in the state ccitx, the message buffer state will not be changed and the message buffer lock error flag lck_ef in the chi error flag register (fr_chierfr) will be set. cctx 1 0 ? tx message t ransmission - message buffer data transmit. payload data from buffer transmitted ccsu 1 0 ? ss s tatus u pdate - message buffer status update. update of status flags, the slot status field, and the header index. note: the slot status field of the commit side is updated too, even if the application has locked the commit side. table 26-119. double transmit message buffer host transitions transition host command condition description he fr_mbccsr(2n+1)[edt]: =1 fr_mbccsr(2n+1)[eds] = 0 application triggers message buffer enable. hd fr_mbccsr(2n+1)[eds] = 1 application triggers message buffer disable. table 26-118. double transmit message buffer state description (transmit side) (continued) state fr_mbccsr n access region description eds lcks appl. module
flexray communication controller freescale semiconductor 26-135 pxs20 microcontroller reference manual, rev. 1 module transitions the module transitions that can be tr iggered by the cc are described in table 26-120 . the transitions c1 and c2 apply to both sides of the me ssage buffer and are applied at the same time. all other cc transitions apply to the transmit side only. transition priorities the application can trigger only one transition at a time. there is no need to specify priorities among them. as shown in the first part of table 26-121 , the module transitions have a higher priority than the application transitions. the priorities among the cc transitions and the related states are given in the second part of table 26-121 . these priorities apply only to the transmit side. the internal message transmit start transition is has tho lowest priority. hl fr_mbccsr(2n)[lckt]:= 1 fr_mbccsr(2n)[lcks] = 0 application triggers message buffer lock. hu fr_mbccsr(2n)[lcks] = 1 application triggers message buffer unlock. table 26-120. double transmit message buffer module transitions transition condition description common transitions is see section 26.6.6.4.5, internal message tr a n s fe r i nternal message transfer s tart - start transfer of message data from commit side to transmit side. ie i nternal message transfer e nd - stop transfer of message data from commit side to transmit side. note: the internal message transfer is stopped before the slot or segment start. transmit side specific transitions sa slot match and static slot s lot a ssigned - message buffer is assigned to next static slot. ma slot match and cyclecounter match m essage a vailable - message buffer is assigned to next slot and cycle counter filter matches. tx slot start and fr_mbccsr(2n+1)[c mt]=1 t ransmission slot start - slot start and commit bit cmt is set. in case of a dynamic slot, platesttx is not exceeded. su status updated s tatus u pdated - slot status field a nd message buffer status flags updated. interrupt flag set. sts static slot start st atic slot s tart - start of static slot. dss dynamic slot start or symbol window start or nit start d ynamic slot or s egment s tart. - start of dynamic slot or symbol window or nit. sss slot start or symbol window start or nit start s lot or s egment s tart - start of static slot or dynamic slot or symbol window or nit. table 26-119. double transmit message buffer host transitions (continued) transition host command condition description
flexray communication controller 26-136 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.6.6.4.4 message preparation the application provides the message data through the commit side. the transmission itself is executed from the transmit side. the transfer of the message data from the commit side to th e transmit side is done by the internal message transfer , which is described in section 26.6.6.4.5, internal message transfer to transmit a message over the flex ray bus, the application writes the message data into the message buffer data field of the commit side and sets the commit bit cmt in the message buffer configuration, control, status registers (fr_mbccsrn) . the physical access to the me ssage buffer data field is described in section 26.6.3.1, individual message buffers . as indicated by table 26-117 , the application shall write to the me ssage buffer data field and change the commit bit cmt only if the transmit message buffer is in one of the st ates hdis, hdislck, or hlck. the application can change the state of a message buffe r if it issues the appropriate commands shown in table 26-119 . the state change is indicated through the fr_mbccsrn[eds] and fr_mbccsrn[lcks] status bits. 26.6.6.4.5 internal message transfer the internal message transfer transf ers the message data from the commit side to the transmit side. the internal message transfer is implemented as the swapping of the content of the message buffer index registers (fr_mbidxrn) of the commit side and the transmit side. after the swa pping, the commit side cmt bit is cleared, the commit side interrupt flag mbif is set, the transmit side cmt bit is set, and the transmit side dval bit is cleared. the conditions and the point in time when the internal message transfer is started are controlled by the message buffer commit mode bit mcm in the message buffer configuration, control, status registers (fr_mbccsrn) . the mcm bit configures the message buffer for either the streaming commit mode or the immediate commit mode. a deta iled description is given in streaming commit mode and immediate commit mode . the internal message transfer is triggered wi th the transition is. both sides of the message buffer enter one of the ccitx states. the internal me ssage transfer is finished with the transition ie. streaming commit mode the intention of the streaming commit mode is to ensure that each committed message is transmitted at least once . the cc will not start the inte rnal message transfer for a messa ge buffer as long as the message data on the transmit side is not transmitted at least once. table 26-121. double transmit message buffer transition priorities state priority description module vs. application idle is > hd is > hl internal message transfer start > message buffer disable internal message transfer start > message buffer lock module internal idle ma > sa message available > slot assigned ccma tx > sts tx > dss transmission slot start > static slot start transmission slot start > dynamic slot start
flexray communication controller freescale semiconductor 26-137 pxs20 microcontroller reference manual, rev. 1 the streaming commit mode is conf igured by clearing the message buffer commit mode bit mcm in the message buffer configuration, contro l, status registers (fr_mbccsrn) . in this mode, the internal message tr ansfer from the commit side to the transmit side is started for a double transmit message buffer when all of the following conditions are fulfilled 1. the commit side is in the idle state 2. the commit site message data ar e valid, i.e. fr_mbccsr(2n)[cmt] = 1 3. the transmit side is in one of the states idle, ccsa, or ccma 4. the transmit side contains either no valid message data, i.e. fr_mbccsr(2n+1)[cmt] = 0 or the message data were tran smitted at least once, i. e. fr_mbccsr(2n+1)[dval] = 1 an example of a streami ng commit mode state cha nge diagram is given in figure 26-144 . in this example, both the commit and the transmit si de do not contain valid message data and the application provides two messages. the message buffer does not match the next slot. figure 26-144. internal message transfer in streaming commit mode immediate commit mode the intention of the immediate co mmit mode is to transmit the latest data provided by the application. this implies that it is not guaranteed that each pr ovided message will be tr ansmitted at least once. the immediate commit mode is configured by setti ng the message buffer commit mode bit mcm in the message buffer configuration, contro l, status registers (fr_mbccsrn) . in this mode, the internal message transfer from the commit side to the transmit side is started for one double transmit message buffer when all of the following conditions are fulfilled 1. the commit side is in the idle state 2. the commit site message data ar e valid, i.e. fr_mbccsr(2n)[cmt] = 1 3. the transmit side is in one of the states idle, ccsa, or ccma it is not checked whether the transm it side contains no valid message data or valid message data were transmitted at least once. if message data are va lid and not transmitted, th ey may be overwritten. an example of a streami ng commit mode state cha nge diagram is given in figure 26-145 . in this example, both the commit and the tran smit side do not contain valid message data, and the applic ation provides two messages and the first message is gets overwritte n. the message buffer does not match the next slot. idle commit tr a n s m i t idle hl hlck side side slot s slot s+1 slot s+2 search[s+1] slot start slot start slot start hu ccitx idle is ccitx ie idle hl hlck hu idle idle no internal message transfer, until message transmitted
flexray communication controller 26-138 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 26-145. internal message transfer in immediate commit mode 26.6.6.4.6 message transmission for double transmit message buffers, the message buffer search checks only the transmit side part. the internal scheduling ensures, that the internal message transfer is stopped on the me ssage buffer search start. thus, the transmit side of message buffer, that is not in its transmis sion or status update slot, is always in the idle state. the message transmit behavior and transmission state changes of the transmit side of a double transmit message buffer are the same as for si ngle buffered transmit buffers, except that the transm it side of double buffers cannot be locked by the application, i.e. the hu and hl transition do not ex ist. therefore, refer to section 26.6.6.2.5, message transmission. 26.6.6.4.7 message buffer status update the message buffer status u pdate behavior of the tran smit side of a double transm it message buffer is the same as for single transmit message buffers which is described in section 26.6.6.2.7, message buffer status update. additionally, the slot status field of the commit side is update after the update of the sl ot status field of the transmit side, even if the commit side is locked by th e application. this is implem ented to provide the slot status of the most r ecent transmission slot. 26.6.7 individual message buffer search this section provides a detailed descripti on of the message buffer search algorithm. the message buffer search determines for each enabled channel if a slot s in a communication cycle c is assigned for frame or null frame tran smission or if it is subscribed for frame reception on that channel. the message buffer search is a se quential algorithm which is invoked at the following protocol related events: 1. nit start 2. slot start in the static segment 3. minislot start in the dynamic segment idle commit transmit idle hl hlck side side slot s slot s+1 slot s+2 search[s+1] slot start slot start slot start hu ccitx idle is ccitx ie idle hl hlck hu idle ccitx idle is ccitx ie idle idle internal message transfer overwrites non-transmitted message
flexray communication controller freescale semiconductor 26-139 pxs20 microcontroller reference manual, rev. 1 the message buffer search within the nit searches fo r message buffers assigned or subscribed to slot 1. the message buffer search within slot n searches for message buffers a ssigned or subscribed to slot n+1 . in general, the message buffer search for the next slot n considers only message buffers which are 1. enabled, i.e. fr_mbccsrn[eds] = 1, and 2. matches the next slot n , i.e. fr_mbfidrn[fid] = n , and 3. are the transmit side buffer in ca se of a double transmit message buffer. on top of that, for the static se gment only those message buffers are considered, that match the condition of at least one row of table 26-122 . for the dynamic segment only those message buffers are considered, that match the condition of at least one row of table 26-123 . these message buffers are called matching message buffers. for each enabled channel the message buffer search may identify multiple matching message buffers. among all matching message buffers the message buffers with hi ghest priority according to table 26-122 for the static segment and according to table 26-123 for the dynamic segment are selected. table 26-122. message buffer search priority (static segment) priority mtd lcks cmt ccfm 1 notes: 1 cycle counter filter match, see section 26.6.7.1, message buff er cycle counter filtering. description transitio n (highest) 0 1 0 1 1 transmit buffer, ma tches cycle count, not locked and committed ma 1 1 - 0 1 transmit buffer, matches cycle count, not committed sa 1 1 ? 1 transmit buffer, matches cycle count, locked sa 2 1 - ? ? transmit buffer sa 3 0 0 n/a 1 receive buffer, matches cycle count, not locked sb (lowest) 4 0 1 n/a 1 receive buffer, matches cycle count, locked sb table 26-123. message buffer search priority (dynamic segment) priority mtd lcks cmt ccfm 1 notes: 1 cycle counter filter match, see section 26.6.7.1, message buff er cycle counter filtering. description transition (highest) 0 1 0 1 1 transmit buffer, matches cycle count, not locked and committed ma 10 0 n/a 1receive buffer, matches cycle count, not locked sb (lowest) 2 0 1 n/a 1 receive buffer, matches cycle count, locked sb
flexray communication controller 26-140 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 if there are multiple message buffer with highest pr iority, the message buffer with the lowest message buffer number is selected. all messa ge buffer which have the highest pr iority must have a consistent channel assignment as specified in section 26.6.7.2, message buffer ch annel assignment consistency . depending on the message buffer ch annel assignment the same messa ge buffer can be found for both channel a and channel b. in this case, this message buffer is used as described in section 26.6.3.1, individual message buffers . 26.6.7.1 message buffer cycle counter filtering the message buffer cycle counter filter is a valu e-mask filter defined by the ccfe, ccfmsk, and ccfval fields in the message buffer cycle counter filter registers (fr_mbccfrn) . this filter determines a set of communication cycles in which th e message buffer is consid ered for message reception or message transmission. if the cycle c ounter filter is disabled, i.e. ccfe = 0, this set of cycles consists of all communication cycles. if the cycle counter filter of a message buffer does not match a certain communication cycle number, this message buffer is not considered for message transmi ssion or reception in that communication cycle. in case of a transmit message buffer as signed to a slot in the static segment, though, this buffer is added to the matching message buffers to i ndicate the slot assignment and to trigger the null frame transmission. the cycle counter filter of a me ssage buffer matches the communicat ion cycle with the number cyccnt if at least one of the followi ng conditions evaluates to true: eqn. 26-12 eqn. 26-13 26.6.7.2 message buffer channel assignment consistency the message buffer channel assignment given by the cha and chb bits in the message buffer cycle counter filter regi sters (fr_mbccfrn) defines the channels on whic h the message buffer will receive or transmit. the message buffer with number n transmits or receives on channel a if fr_mbccfrn[cha] = 1 and transmits or rece ives on channel b if fr_mbccfrn[chb] = 1. to ensure correct message buffer operation, all messag e buffers assigned to the same slot and with the same priority must have a consistent channel assignment. that means they must be either assigned to one channel only, or must be assigned to both channels. the behavior of the message buffer search is not defined, if both types of ch annel assignments occur for one slot a nd priority. an inconsistent channel assignment for message buffer 0 and message buffer 1 is depicted in figure 26-146 . figure 26-146. inconsistent channel assignment mbccfrn ccfe ?? 0 = cyccnt & mbccfrn ccfmsk ?? mbccfrn ccfval ?? & mbccfrn ccfmsk ?? = mb0 fr_mbccfr0[cha] = 1, fr_mbccfr0[chb] = 0 mb1 dual channel assignment single channel assignment fr_mbfidr0[fid] = 10 fr_mbfidr1[fid] = 10 fr_mbccfr1[cha] = 1, fr_mbccfr1[chb] = 1
flexray communication controller freescale semiconductor 26-141 pxs20 microcontroller reference manual, rev. 1 26.6.7.3 node related slot multiplexing the term node related slot multiplexing applies to the dynamic segment only and refers to the functionality if there are transmit as well as receive message buffers are configured for the same slot. according to table 26-123 the transmit buffer is only found if the cycle counter filter matches, and the buffer is not locked and committed. in all other cases, the receive buffer will be found. t hus, if the block has no data to transmit in a dynamic slot, it is able to receive frames on that slot. 26.6.7.4 message buffer search error if the message buffer search is running while the ne xt message buffer search start event appears, the message buffer search is stopped and the message bu ffer search error flag msb_ef is set in the chi error flag register (fr_chierfr) . this appears only if th e chi frequency is too low to search through all message buffers within the nit or a minislot. the message buffer result is not defined in this case. for more details see section 26.7.5, number of usable message buffers. 26.6.8 individual message buffer reconfiguration the initial configuration of each i ndividual message buffer can be changed even when the protocol is not in the poc:config state. this is referred to as individual message buffer reconfiguration . the configuration bits and fiel ds that can be changed ar e given in the section on specific configuration data . the common configuration data given in the section on specific configuration data can not be reconfigured when the protocol is out of the poc:config state. 26.6.8.1 reconfiguration schemes depending on the target and destinatio n basic state of the message buffer th at is to be reconfigured, there are three reconfiguration schemes. 26.6.8.1.1 basic type not changed (rc1) a reconfiguration will not change the basic type of the individual message buffer, if both the message buffer transfer direction bit fr_mbccsrn[mtd] an d the message buffer type bit fr_mbccsrn[mbt] are not changed. this type of rec onfiguration is denoted by rc1 in figure 26-147 . single transmit and receive message buffers can be rc1 -reconfigured when in the hdis or hdislck state. double transmit message buffers can be rc1-reconfigured if both the tr ansmit side and the commit side are in the hdis state. 26.6.8.1.2 buffer type not changed (rc2) a reconfiguration will not change the buffer type of the individual me ssage buffer if the message buffer buffer type bit fr_mbccsrn[mbt] is not changed. this type of reco nfiguration is denoted by rc2 in figure 26-147 . it applies only to single transmit and recei ve message buffers. singl e transmit and receive message buffers can be rc2-reconfigured when in the hdis or hdislck state.
flexray communication controller 26-142 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.6.8.1.3 buffer type changed (rc3) a reconfiguration will change the buffer type of th e individual message buffer if the message buffer type bit fr_mbccsrn[mbt] is changed. this type of reconfiguration is denoted by rc3 in figure 26-147 . the rc3 reconfiguration splits one double buffer into two single buffers or combines two single buffer into one double buffer. in the later case, the two si ngle message buffers must have consecutive message buffer numbers and the smaller one must be even. message buffers can be rc3 reconfigured if they are in the hdis state. figure 26-147. message buffer reconfiguration scheme 26.6.9 receive fifos this section provides the functional de scription of the two receive fifos. 26.6.9.1 overview the two receive fifos implement the queue d message buffer concept defined by the flexray communications system protocol specification, version 2.1 rev a. one fifo is assigned to channel a, the other fifo is assigned to channel b. both fi fos work completely inde pendent from each other. the message buffer structure of each fifo is described in section 26.6.3.3, receive fifo. the area in the flexray memory area for each of the two fifos is characterized by: ? the fifo system memory base address ? the index of the first fifo entry given by receive fifo start inde x register (fr_rfsir) ? the number of fifo entries and the le ngth of each fifo entry as given by receive fifo depth and size register (rfdsr) 26.6.9.2 fifo configuration the fifos can be configured for two different locations of the system memory ba se address via the fifo address mode bit fam in the module configuration register (fr_mcr) . single rx single tx double tx (commit side) double tx (transmit side) rc1 rc1 rc1 rc2 rc3 rc3
flexray communication controller freescale semiconductor 26-143 pxs20 microcontroller reference manual, rev. 1 26.6.9.2.1 single system memory base address mode this mode is configured, when the fifo address mode flag fr_mcr[fam ] is set to 0. in this mode, the location of the system memory base address for the fifo buffers is system memory base address register (fr_symbadr) . 26.6.9.2.2 dual system memory base address mode this mode is configured, when the fifo address mode flag fr_mcr[fam ] is set to 1. in this mode, the location of the system memory base address for the fifo buffers is receive fifo system memory base address register (fr_rfsymbadr) . the fifo control and confi guration data are given in section 26.6.3.7, receive fifo control and configuration data. the configuration of the fifo s consists of two steps. the first step is the allocation of the required am ount of memory for the fl exray memory area. this includes the allocation of the message buffer header area and the allocation of the message buffer data fields. for more details see section 26.6.4, flexray memory area layout. the second step is the programming of the confi guration data register while the pe is in poc:config. the following steps configur e the layout of the fifo. ? configure the fifo update and address modes in module configuration register (fr_mcr) ? configure the fifo system memory base address ? configure the receive fifo start inde x register (fr_rfsir) with the first message buffer header index that belongs to the fifo ? configure the receive fifo depth and size register (rfdsr) with fifo entry size ? configure the receive fifo depth and size register (rfdsr) with fifo depth ? configure the fifo filters 26.6.9.3 fifo periodic timer the fifo periodic timer is used to generate an fifo almost-full interrupt at certain point in time, if the almost-full watermark is not reached, but the fifo is not empty. this can be used to prevent frames from get stuck in the fi fo for a long time. the fifo periodic timer is configured via the receive fifo periodic timer register (fr_rfptr) . if the periodic timer duration fr_rfptr[p td] is configured to 0x0000, the periodic timer is continuously expired. if the periodic t imer duration fr_rfptr[ptd] is configur ed to 0x3fff, the periodic timer never expires. if the periodic timer is configured to a value ptd, greater than 0x0000 and smaller 0x3fff, the periodic timer expires and is restar ted at the start of every communi cation cycle, and expires and is restarted after ptd macroticks have been elapsed. 26.6.9.4 fifo reception the fifo reception is a cc internal operation.
flexray communication controller 26-144 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 a message frame reception is dire cted into the fifo, if no indivi dual message buffer is assigned for transmission or subscribed for reception for the curren t slot. in this case the fifo filter path shown in figure 26-148 is activated. if the fifo filter path indicates that the received fr ame has to be appended to the fifo and the fifo is not full, the cc writes the received frame header into the message buffer header field indicated by the cc internal fifo write inde x. the frame payload data are written into the corresponding message buffer data field. if the status of the received frame indicates a valid non-null frame, the slot status information is written into the message buffer header field and the cc internal fifo write index is updated by 1 and the fifo fill level fla (flb) in the receive fifo fill level and po p count register (fr_rfflpcr) is incremented.if the status of the rece ived frame indicates an invalid or null frame, the frame is not appended to the fifo. 26.6.9.5 fifo almost-full interrupt generation if the fifo fill level fla (flb) is updated after a frame reception and exceeds the fifo watermark level wm, i.e. fla>wm a (flb>wm b ), then the fifo almost-full interrupt flag fr_gifer[fafaif] (fr_gifer[fafbif]) is asserted.if the periodic timer expires, and fifoa (fifob) is not empty, i.e. fla>0 (flb>0), then the fifo almost-full interrupt flag fr_gifer[fafaif] (fr_gifer[fafbif]) is asserted. 26.6.9.6 fifo overflow error generation if the fifoa (fifob) is full, i.e. fla=fifo_depth a (flb=fifo_depth b ) and the conditions for a fifo reception as described in section 26.6.9.4, fifo reception , are fulfilled, then the fifo overflow error flag fr_chierfr[fova_ef] (fr_chierfr[fovb_ef]) is asserted. 26.6.9.7 fifo message access the fifoa (fifob) contains valid messages if the fi fo fill level fla (flb) is greater than 0. the receive fifo a read index register (fr_rfarir) ( receive fifo b read index register (fr_rfbrir) ) pointing to a message buffer with valid conten t and the oldest frames stored in the fifo. if the fifo fill level fla (flb ) is 0, than the fifoa (fifob) c ontains no valid me ssages and the receive fifo a read index register (fr_rfarir) ( receive fifo b read index register (fr_rfbrir) ) pointing to a message buffer with invalid content. in th is case the application must not read data from the fifo. to access the oldest message in the fifoa (fifob), the application first reads the read index rdidx out of the receive fifo a read index register (fr_rfarir) ( receive fifo b read index register (fr_rfbrir) ). this read index points to the message buffer header field of the oldest message buffer that contains valid received message data. the applicat ion can access the message data as described in section 26.6.3.3, receive fifo. when the application has read th e message buffer data and status information, it can update the fifo as described in section 26.6.9.8, fifo update .
flexray communication controller freescale semiconductor 26-145 pxs20 microcontroller reference manual, rev. 1 26.6.9.8 fifo update the application updates the fifoa (fifob) by writing a pop count value pc different from 0 to the pca (pcb) field in the receive fifo fill level and po p count register (fr_rfflpcr) . as a result of the this opera tion, the cc removes the oldest pc entries from fifoa (fifob). if the specified pop count value pc is greater than the current fill level fl provided in fla (fab) field, then only fl entries are removed from the fifoa (fifob), the remaining fl-pc requested pop operations are discarded without any notificati on. in this case fifoa (fifob) is empty after the update operation. the read index in the receive fifo a read index register (fr_rfarir) ( receive fifo b read index register (fr_rfbrir) ) is incremented by the number of removed it ems. if the read index reaches the top of the fifo, it wraps around to th e fifo start index defined in receive fifo start index register (fr_rfsir) automatically. 26.6.9.8.1 fifo interrupt flag update th fifo interrupt flag update m ode is configured, when the fifo update mode flag fr_mcr[fum] is set to 0. in this mode fifoa (fifob) will be updated by 1 entry, when the interrupt flag fr_gifer[fafaif] (fr_gife r[fafbif]) is written with 1 by the application. if the fifo is empty, the update reque st is ignored without any notification. the read index in the receive fifo a read index register (fr_rfarir) ( receive fifo b read index register (fr_rfbrir) ) is incremented by 1, if the fifo was not empty. if the read index reaches the top of the fifo, it wraps around to the fifo start index automatically. 26.6.9.9 fifo filtering the fifo filtering is activated after all enabled i ndividual receive message buffers have been searched without success for a message buffer to receive the current frame. the cc provides three sets of fifo filters. the fifo filters are applied to va lid non-null frames only. the fifo will not receive invalid or nul l-frames. for each fifo filter, the pass criteria is specified in the related section given below. only frames that have passed all filters will be appended to the fifo. the fifo filter path is depicted in figure 26-148 .
flexray communication controller 26-146 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 26-148. received frame fifo filter path valid frame received ( vrf ) individual null frame frame id value- frame id append to fifo ( vrf ) frame id no frame received fifo full set fifo overflow interrupt flag message buffer found ? no passed passed passed yes (vrf!header!nfindicator=0 ) ? mask rejection filter ? range rejection filter ? range acceptance filter ? in dynamic segment ? ? store into message buffer ( vrf ) yes no else ignore frame yes else else message id ( vrf!header!ppindicator=1 ) ? message id yes passed acceptance filter ? no yes no else
flexray communication controller freescale semiconductor 26-147 pxs20 microcontroller reference manual, rev. 1 a received frame passes the fifo filtering if it has passed all three type of filter. 26.6.9.9.1 rx fifo frame id value-mask rejection filter the frame id value-mask rejection filter is a value-mask filter and is defined by the fields in the receive fifo frame id rejection filter value register (fr_rffidrfvr) and the receive fifo frame id rejection filter mask register (fr_rffidrfmr) . each received frame with a frame id fid that does not match the value-mask filter value pa sses the filter, i.e. is not rejected. consequently, a received valid frame with the frame id fid passes the rx fifo frame id value-mask rejection filter if equation 26-14 is fulfilled. eqn. 26-14 the rx fifo frame id value-mask re jection filter can be c onfigured to pass all frames by the following settings. ? fr_rffidrfvr[fidrfval]:= 0x000 a nd fr_rffidrfmr[fidrfmsk]:= 0x7ff using the settings above, only the frame with frame id 0 will be rejecte d, which is an invalid frame. all other frames will pass. the rx fifo frame id value-mask rejection filter can be configured to reject all frames by the following settings. ? fr_rffidrfmr[fidrfmsk]:= 0x000 using the settings above, equation 26-14 can never be fulfilled (0!= 0) a nd thus all frames are rejected; no frame will pass. this is the reset value for the rx fifo. 26.6.9.9.2 rx fifo frame id range rejection filter each of the four rx fifo frame id range filters can be configured as a rejection filter. the filters are configured by the receive fifo range filter conf iguration register (fr_rfrfcfr) and controlled by the receive fifo range filter c ontrol register (fr_rfrfctr) . the rx fifo frame id range filters apply to all received valid frames. a received frame with the frame id fid passes the rx fifo frame id range rejection filters if ei ther no rejection filter is enabled, or, fo r all of the enabled rx fifo frame id range rejection filters, i.e. fr_rfrfc tr[fimd] = 1 and fr_rfrfctr[fien] = 1, equation 26-15 is fulfilled. eqn. 26-15 consequently, all frames with a frame id that fulfills equation 26-16 for at least one of the enabled rejection filters will be re jected and thus not pass. eqn. 26-16 26.6.9.9.3 rx fifo frame id range acceptance filter each of the four rx fifo frame id range filter s can be configured as an ac ceptance filter. the filters are configured by the receive fifo range filter conf iguration register (fr_rfrfcfr) and controlled by the receive fifo range filter c ontrol register (fr_rfrfctr) . the rx fifo frame id range filters fid & fr_ rffidrfmr fidrfmsk ?? fr_ rffidrfvr fidrfval ?? & fr_ rffidrfmr fidrfmsk ?? ? fid fr_ rfrfcfr sel sid ibd 0 = ?? ?? or fr_ rfrfcfr sel sid ibd 1 = ?? fid ? ?? rfrfcfr sel sid ibd 0 = ?? fid fr_ rfrfcfr sel sid ibd 1 = ?? ??
flexray communication controller 26-148 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 apply to all received valid frames. a received frame with the frame id fid passes the rx fifo frame id range acceptance filters if either no acceptance filter is enabled, or, for at least one of the enabled rx fifo frame id range acceptan ce filters, i.e. fr_rfrfctr[fimd] = 0 and fr_rfrfctr[fien] = 1, equation 26-17 is fulfilled. eqn. 26-17 26.6.9.9.4 rx fifo messa ge id acceptance filter the rx fifo message id acceptance filter is a value-mask filter and is defined by the receive fifo message id acceptance filter value register (fr_rfmidafvr) and the receive fifo message id acceptance filter mask register (fr_rfmidafmr) . this filter applies only to valid frames received in the dynamic segment with the payload preamble indicator bit ppi set to 1. all other frames will pass this filter. a received valid frame in the dynamic segment with th e payload preamble indicator bit ppi set to 1 and with the message id mid (the first two bytes of the payload) will pass the rx fifo message id acceptance filter if equation 26-18 is fulfilled. eqn. 26-18 the rx fifo message id acceptance filter can be configured to accep t all frames by setting ? fr_rfmidafmr[midafmsk]:= 0x000 using the settings above, equation 26-18 is always fulfilled and all frames will pass. 26.6.10 channel device modes this section describes the two flexray channe l device modes that are supported by the cc. 26.6.10.1 dual channel device mode in the dual channel device mode, both flexray ports are connected to physical flexray bus lines. the flexray port consis ting of ca_rx, ca _tx, and ca_tr_en is connected to the physical bus channel a and the flexray port consisting of cb_rx, cb_tx, and cb_tr_en is connected to the physical bus channel b. the dual channel system is shown in figure 26-149 . fr_ rfrfcfr sel sid ibd 0 = ?? fid fr_ rfrfcfr sel sid ibd 1 = ?? ?? mid & fr_ rfmidafmr midafmsk ?? fr_ rfmidafmr midafval ?? & fr_ rfmidafmr midafmsk ?? =
flexray communication controller freescale semiconductor 26-149 pxs20 microcontroller reference manual, rev. 1 figure 26-149. dual channel device mode 26.6.10.2 single channel device mode the single channel device mode suppor ts devices that have only one flex ray port available. this flexray port consists of the signals ca_rx, ca_tx, and ca_tr_en and can be connected to either the physical bus channel a (shown in figure 26-150 ) or the physical bus channel b (shown in figure 26-151 ). if the device is configured as a single channel de vice by setting fr_mcr.scd to 1, only the internal channel a and the flexray port a is used. depending on the setting of fr_mcr.cha and fr_mcr.chb, the internal channel a behaves either as a flexray chan nel a or flexray channel b. the bit fr_mcr.cha must be set, if the flexray port a is connected to a flexray channel a. the bit fr_mcr.chb must be set if the fl exray port a is connected to a fl exray channel b. the two flexray channels differ only in the initial value for the frame crc ccrcinit . for a single channel device, the application can access and configure only the registers related to internal channel a. chi pe cfg(a) reg(a) ccrcinit[a] ccrcinit[b] cfg(b) reg(b) channel 0 channel 1 flexray channel a flexray bus driver channel a ca_rx ca_tx ca_tr_en flexray channel b flexray bus driver channel b cb_rx cb_tx cb_tr_en flexray
flexray communication controller 26-150 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 26-150. single channel device mode (channel a) figure 26-151. single channel device mode (channel b) 26.6.11 external clock synchronization the application of the external rate and offset correct ion is triggered when the application writes to the eoc_ap and erc_ap fields in the protocol operation cont rol register (fr_pocr) . the pe applies the external correction values in the next even-odd cycle pair as shown in figure 26-152 and figure 26-153 . chi pe cfg(a) reg(a) ccrcinit[a] ccrcinit[b] cfg(b) reg(b) channel a channel b flexray channel a flexray bus driver channel a ca_rx ca_tx ca_tr_en cb_rx cb_tx cb_tr_en flexray chi pe cfg(a) reg(a) ccrcinit[b] cfg(b) reg(b) channel a channel b flexray channel b init value for frame crc is ccrcinit[b] ccrcinit[a] flexray bus driver channel a ca_rx ca_tx ca_tr_en cb_rx cb_tx cb_tr_en flexray
flexray communication controller freescale semiconductor 26-151 pxs20 microcontroller reference manual, rev. 1 note the values provided in the eoc_ap and erc_ap fields are the values that were written from the appl ication most recently. if these value were already applied, they will not be applied in the current cycle pair again. if the offset correction applied in the nit of cycle 2n +1 shall be affect by the external offset correction, the eoc_ap field must be written to after the start of cycle 2n and before the end of the static segment of cycle 2n+1. if this field is written to after the end of the st atic segment of cycle 2n+ 1, it is not guaranteed that the external correction value is applied in cycl e 2n+1. if the value is not applied in cycle 2n+1, then the value will be applied in the cycle 2n+3. refer to figure 26-152 for timing details. figure 26-152. external offset correction write and application timing if the rate correction for the cycle pair [2n+2, 2n+3] shall be affect by the external offset correction, the erc_ap field must be written to after the start of cy cle 2n and before the end of the static segment start of cycle 2n+1. if this field is written to after the end of the static segment of cycle 2n+1, it is not guaranteed that the external correction value is applied in cycle pair [2n+2, 2n+3]. if the valu e is not applied for cycle pair [2n+2, 2n+3], then the va lue will be applied for cycl e pair [2n+4, 2n+5]. refer to figure 26-153 for details. figure 26-153. external rate correction write and application timing 26.6.12 sync frame id and sync frame deviation tables the flexray protocol requires the pr ovision of a snapshot of the synchr onization frame id tables for the even and odd communication cycle for both channels. the cc provides the means to write a copy of these internal tables into the flexray memory area and en sures application access to consistent tables by means of table locking. once the application has locked the table successf ully, the cc will not overwrite these tables and the application can read a consistent snapshot. note only synchronization frames that have passed the synchronization frame filters are considered for clock synchr onization and appear in the sync frame tables. static segment nit static segment nit eoc_ap write window eoc_ap application cycle 2n cycle 2n+1 static segment nit erc_ap write window erc_ap application cycle 2n static segment nit cycle 2n+1 static segment nit cycle 2n+2 static segment nit cycle 2n+3
flexray communication controller 26-152 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.6.12.1 sync frame id table content the sync frame id table is a snapshot of the protocol related variables vssyncidlista and vssyncidlistb for each even and odd communication cycle. this table provides a list of the frame ids of the synchronization frames received on the corresponding channel and cycle that are used for the clock synchronization. 26.6.12.2 sync frame deviation table content the sync frame deviation table is a snapshot of th e protocol related variable zsdev(id)(oe)(ch)!value. each sync frame deviation table entry provides the deviation value for the s ync frame, with the frame id presented in the corresponding en try in the sync frame id table. figure 26-154. sync table memory layout 26.6.12.3 sync frame id and sync frame deviation table setup the cc writes a copy of the intern al synchronization frame id and deviation tables into the flexray memory area if requested by the application. the a pplication must provide th e appropriate amount of flexray memory area for the tables. the me mory layout of the tables is given in figure 26-154 . each table occupies 120 16-bit entries. fr_sftor fr_sftor + 180 sync frame id cha 1 sync frame id cha 2 sync frame id cha 3 sync frame id cha 4 sync frame id cha 5 sync frame id cha 6 sync frame id cha 7 sync frame id cha 8 sync frame id cha 9 sync frame id cha 10 sync frame id cha 11 sync frame id cha 12 sync frame id cha 13 sync frame id cha 14 sync frame id cha 15 sync deviation cha 1 sync deviation cha 2 sync deviation cha 3 sync deviation cha 4 sync deviation cha 5 sync deviation cha 6 sync deviation cha 7 sync deviation cha 8 sync deviation cha 9 sync deviation cha 10 sync deviation cha 11 sync deviation cha 12 sync deviation cha 13 sync deviation cha 14 sync deviation cha 15 fr_sftor + 60 fr_sftor +120 sync frame id cha 1 sync frame id cha 2 sync frame id cha 3 sync frame id cha 4 sync frame id cha 5 sync frame id cha 6 sync frame id cha 7 sync frame id cha 8 sync frame id cha 9 sync frame id cha 10 sync frame id cha 11 sync frame id cha 12 sync frame id cha 13 sync frame id cha 14 sync frame id cha 15 sync deviation cha 1 sync deviation cha 2 sync deviation cha 3 sync deviation cha 4 sync deviation cha 5 sync deviation cha 6 sync deviation cha 7 sync deviation cha 8 sync deviation cha 9 sync deviation cha 10 sync deviation cha 11 sync deviation cha 12 sync deviation cha 13 sync deviation cha 14 sync deviation cha 15 offset + $00 offset + $02 offset + $04 offset + $06 offset + $08 offset + $0a offset + $0c offset + $0e offset + $10 offset + $12 offset + $14 offset + $16 offset + $18 offset + $1a offset + $1c sync frame id chb 1 sync frame id chb 2 sync frame id chb 3 sync frame id chb 4 sync frame id chb 5 sync frame id chb 6 sync frame id chb 7 sync frame id chb 8 sync frame id chb 9 sync frame id chb 10 sync frame id chb 11 sync frame id chb 12 sync frame id chb 13 sync frame id chb 14 sync frame id chb 15 sync deviation chb 1 sync deviation chb 2 sync deviation chb 3 sync deviation chb 4 sync deviation chb 5 sync deviation chb 6 sync deviation chb 7 sync deviation chb 8 sync deviation chb 9 sync deviation chb 10 sync deviation chb 11 sync deviation chb 12 sync deviation chb 13 sync deviation chb 14 sync deviation chb 15 sync frame id chb 1 sync frame id chb 2 sync frame id chb 3 sync frame id chb 4 sync frame id chb 5 sync frame id chb 6 sync frame id chb 7 sync frame id chb 8 sync frame id chb 9 sync frame id chb 10 sync frame id chb 11 sync frame id chb 12 sync frame id chb 13 sync frame id chb 14 sync frame id chb 15 sync deviation chb 1 sync deviation chb 2 sync deviation chb 3 sync deviation chb 4 sync deviation chb 5 sync deviation chb 6 sync deviation chb 7 sync deviation chb 8 sync deviation chb 9 sync deviation chb 10 sync deviation chb 11 sync deviation chb 12 sync deviation chb 13 sync deviation chb 14 sync deviation chb 15 offset + $1e offset + $20 offset + $22 offset + $24 offset + $26 offset + $28 offset + $2a offset + $2c offset + $2e offset + $30 offset + $32 offset + $34 offset + $36 offset + $38 offset + $3a fr_sfcntr sfeva sfevb fr_sfcntr sfoda sfodb even odd even odd
flexray communication controller freescale semiconductor 26-153 pxs20 microcontroller reference manual, rev. 1 while the protocol is in poc:config state, the application must program the offsets for the tables into the sync frame table offset register (fr_sftor) . 26.6.12.4 sync frame id and sync frame deviation table generation the application controls the genera tion process of the sync frame id and sync frame deviation tables into the flexray memory area using the sync frame table configurati on, control, status register (fr_sftccsr) . a summary of the copy modes is given in table 26-124 . the sync frame table generation pro cess is described in the following for the even cycle. the same sequence applies to the odd cycle. if the application has enabled the sync frame tabl e generation by setting fr_ sftccsr[siden] to 1, the cc starts the update of the even cycle related tables af ter the start of the nit of the next even cycle. the cc checks if the application has lock ed the tables by reading the fr_sft ccsr[elks] lock status bit. if this bit is set, the cc will not update the table in this cycle. if this bit is cleare d, the cc locks this table and starts the table update. to indicate that these tables are currently updated and may contain inconsistent data, the cc clears the even table valid status bit fr_sftccsr[eval]. once all table entries related to the even cycle have been transferred into the flexra y memory area, the cc sets the even table valid bit fr_sftccsr[eval] and the even cycle table written interrupt flag evt_if in the protocol interrupt flag register 1 (fr_pifr1) . if the interrupt enable fl ag evt_ie is set, an inte rrupt request is generated. to read the generated tables, the application must lock the tables to prevent the cc from updating these tables. the locking is initiated by writing a 1 to the even table lock trigger fr_sftccsr[elkt]. when the even table is not currently update d by the cc, the lock is granted a nd the even table lock status bit fr_sftccsr[elks] is set. this indicates that the a pplication has successfully locked the even sync tables and the corresponding status in formation fields sfra, sfrb in the sync frame counter register table 26-124. sync frame table generation modes fr_sftccsr description opt sdven siden 0 0 0 no sync frame table copy 0 0 1 sync frame id tables will be copied continuously 0 1 0 reserved 0 1 1 sync frame id tables and sync frame deviation tables will be copied continuously 1 0 0 no sync frame table copy 1 0 1 sync frame id tables for next even-odd-cycle pair will be copied 1 1 0 reserved 1 1 1 sync frame id tables and sync frame deviation tables for next even-odd-cycle pair will be copied
flexray communication controller 26-154 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 (fr_sfcntr) . the value in the fr_sftccsr[cycnum] fiel d provides the number of the cycle that this table is related to. the number of available table entries per channe l is provided in the fr_sfcntr[sfeva] and fr_sfcntr[sfevb] fields. the applicat ion can now start to read the sync table data from the locations given in figure 26-154 . after reading all the data from the locked tables, th e application must unlock the table by writing to the even table lock trigger fr_sftccs r[elkt] again. the even table lock status bit fr _sftccsr[elks] is reset immediately. if the sync frame table generation is disabl ed, the table valid bits fr_sftccsr[eval] and fr_sftccsr[eval] are reset when the counter values in the sync frame counter register (fr_sfcntr) are updated. this is done because the tables stored in the flexray memory area are no longer related to the values in the sync frame counter re gister (fr_sfcntr) . figure 26-155. sync frame table trigger and generation timing 26.6.12.5 sync frame table access the sync frame tables wi ll be transferred into the flexray me mory area during the table write windows shown in figure 26-155 . during the table write, the application ca n not lock the table that is currently written. if the application locks the table outsid e of the table write window, the lock is granted immediately. 26.6.12.5.1 sync frame tabl e locking and unlocking the application locks the even/odd s ync frame table by writing 1 to th e lock trigger bit elkt/olkt in the sync frame table configuration, cont rol, status register (fr_sftccsr) . if the affected table is not currently written to the flexray memory area, the lock is granted immediately, and the lock status bit elks/olks is set. if the affected table is currently written to the flexray memory area, the lock is not granted. in this case, the applicat ion must issue the lock request again until the lock is granted. the application unlocks the even/odd sync frame tabl e by writing 1 to the lock trigger bit elkt/olkt. the lock status bit elks/olks is cleared immediately. 26.6.13 mts generation the cc provides a flexible means to request the transm ission of the media acce ss test symbol mts in the symbol window on channel a or channel b. the application can configure the se t of communication cycles in which the mts will be transmitted over the flexray bus by programming the cycc ntmsk and cyccntval fields in the mts a configuration regi ster (fr_mtsacfr) and mts b configuration register (mtsbcfr) . fr_sftccsr.[opt,siden,sdven] write window even table write static segment nit static segment nit static segment nit cycle 2n-1 cycle 2n cycle 2n+1 odd table write
flexray communication controller freescale semiconductor 26-155 pxs20 microcontroller reference manual, rev. 1 the application enables or disables the generation of the mts on either channel by setting or clearing the mte control bit in the mts a configuration register (fr_mtsacfr) or mts b configuration register (mtsbcfr) . if an mts is to be transmitted in a certai n communication cycle, the application must set the mte control bit during the static segm ent of the preceding communication cycle. the mts is transmitted over channel a in th e communication cycle with number cyccnt, if equation 26-20 , equation 26-21 , and equation 26-21 are fulfilled. eqn. 26-19 eqn. 26-20 eqn. 26-21 the mts is transmitted over channel b in th e communication cycle with number cyccnt, if equation 26-19 , equation 26-22 , and equation 26-23 are fulfilled. eqn. 26-22 eqn. 26-23 26.6.14 key slot transmission 26.6.14.1 key slot assignment a key slot is assigned to the cc if the key_slot_id field in the protocol configur ation register 18 (fr_pcr18) is configured with a value greater than 0 and less or equal to number_of_static_slots in protocol configuration register 2 (fr_pcr2) , otherwise no key slot is assigned. 26.6.14.2 key slot transmission in poc:startup if a key slot is assigne d and the cc is in the poc:startup state, startup null frames will be transmitted as specified by flexray communications system protoc ol specification, version 2.1 rev a . 26.6.14.3 key slot transmission in poc:normal active if a key slot is assi gned and the cc is in poc:normal active , a frame of the type as shown in table 26-125 is transmitted. if a tr ansmit message buffer is configured for the key slot and a valid me ssage is available, a message frame is transmitted (see section 26.6.6.2.5, message transmission ). if no transmit message buffer is configured for the key slot or no valid mess age is available, a null fr ame is transmitted (see section 26.6.6.2.6, null frame transmission ). fr_ psr 0 protstate ?? poc:normal active = fr_ mtsacrf mte ?? 1 = cyccnt & fr_ mtsacfr cyccntmsk ?? fr_ mtsacfr cyccntval ?? & fr_ mtsacfr cyccntmsk ?? = fr_ mtsbcrf mte ?? 1 = cyccnt & fr_ mtsbcfr cyccntmsk ?? fr_ mtsbcfr cyccntval ?? & fr_ mtsbcfr cyccntmsk ?? =
flexray communication controller 26-156 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.6.15 sync frame filtering each received synchronization frame must pass the sync frame acceptance filt er and the sync frame rejection filter before it is considered for clock synchronization. if the synchr onization frame filtering is globally disabled, i.e. the sffe control bit in the module configuration register (fr_mcr) is cleared, all received synchronization fram es are considered for clock synchronization. if a received synchronization frame did not pa ss at least one of the two filters, this frame is pr ocessed as a normal frame and is not considered for clock synchronization. 26.6.15.1 sync frame acceptance filtering the synchronization frame accep tance filter is implemente d as a value-mask filter. the value is configured in the sync frame id acceptance filt er value register (fr_sfidafvr) and the mask is configured in the sync frame id acceptance filter mask register (fr_sfidafmr) . a received synchronization frame with the frame id fid passes the sync frame acceptance filter, if equation 26-24 or equation 26-25 evaluates to true. eqn. 26-24 eqn. 26-25 note sync frames are transmitted in the static segment only. thus fid <= 1023. 26.6.15.2 sync frame rejection filtering the synchronization frame rejection filter is a comparator. the compare value is defined by the sync frame id rejection filter register (fr_sfidrfr) . a received synchronization frame with the frame id fid passes the sync frame rejection filter if equation 26-26 or equation 26-27 evaluates to true. eqn. 26-26 eqn. 26-27 note sync frames are transmitted in the static segment only. thus fid <= 1023. table 26-125. key slot frame type fr_pcr11[key_slot_used_for_syn c] fr_pcr11[key_slot_used_for_star tup] key slot frame type 0 0 normal frame 0 1 normal frame 1 notes: 1 the frame transmitted has an semantically incorrect header and will be detected as an in valid frame at the receiver. 1 0 sync frame 1 1 startup frame fr_ mcr sffe ?? 0 = fid & fr_ sfidafmr fmsk ?? fr_ sfidafvr fval ?? & fr_ sfidafmr fmsk ?? = fr_ mcr sffe ?? 0 = fid fr_ sfidrfr synfrid ?? ?
flexray communication controller freescale semiconductor 26-157 pxs20 microcontroller reference manual, rev. 1 26.6.16 strobe signal support the cc provides a number of strobe signals for observi ng internal protocol timi ng related signals in the protocol engine. the signals are listed and described in table 26-12 . 26.6.16.1 strobe signal assignment each of the strobe signals listed in table 26-12 can be assigned to one of th e four strobe ports using the strobe signal control register (fr_stbscr) . to assign multiple strobe signals, the application must write multiple times to the strobe signal control register (fr_stbscr) with appropriate settings. to read out the current settings for a strobe signal with number n, the application must execute the following sequence. 1. write to fr_stbscr with wmd = 1 a nd sel = n. (updates sel field only) 2. read stbcsr. the sel field provides n and the enb and stbpse l fields provides the settings for signal n. 26.6.16.2 strobe signal timing this section provides detail ed timing information of the strobe signals with respect to th e protocol engine clock. the strobe signals display internal pe signals. due to the internal archit ecture of the pe, some signals are generated several pe clock cycles before the actual action is performe d on the flexray bus. these signals are listed in table 26-12 with a negative clock offset. an example waveform is given in figure 26-156 . figure 26-156. strobe signal timing (type = pulse, clk_offset = -2) other signals refer to events that occurred on the fl exray bus some cycles befo re the strobe signal is changed. these signals are listed in table 26-12 with a positive clock offset . an example waveform is given in figure 26-157 . pe clock strobe signal flexray bus event -2
flexray communication controller 26-158 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 26-157. strobe signal timing (type = pulse, clk_offset = +4) 26.6.17 timer support the cc provides two timers, which run on the flexray time base. e ach timer generates a maskable interrupt when it reaches a configur ed point in time. timer t1 is an absolute timer. timer t2 can be configured to be an absolute or a relative timer . both timers can be configured to be repetitive. in the non-repetitive mode, timer stops if it expires. in repetitive mode, timer is restarted when it expires. both timers are active only when the protocol is in poc:normal active or poc:normal passive state. if the protocol is not in one of these modes, the timers are stopped. the application must restart the timers when the protocol has reached the poc:normal active or poc:normal passive state. 26.6.17.1 absolute timer t1 the absolute timer t1 has the protoc ol cycle count and the macrotick c ount as the time base. the timer 1 interrupt flag ti1_if in the protocol interrupt flag register 0 (fr_pifr0) is set at the macrotick start event, if equation and equation 26-29 are fulfilled eqn. 26-28 eqn. 26-29 if the timer 1 interrupt enable bit ti1_ie in the protocol interrupt enable register 0 (fr_pier0) is asserted, an interrupt request is generated. the status bit t1st is set when the timer is tri ggered, and is cleared when the timer expires and is non-repetitive. if the timer expires but is repetitive, the t1st bit is not cleared and the t imer is restarted immediately. the t1st is cleared when the timer is stopped. 26.6.17.2 absolute / relative timer t2 the timer t2 can be configured to be an absolute or relative timer by setting the t2_cfg control bit in the timer configuration and c ontrol register (fr_ticcr) . the status bit t2st is set when the timer is triggered, and is cleared when the timer expires and is non-repetitive. if the timer expires but is repetitive, the t2st bit is not cleared and the timer is restarted immediately. the t2st is cleared when the timer is stopped. pe clock strobe signal flexray bus event +4 cyctr ctccnt ?? & fr_ ti 1 cysr t 1_ cyc _ msk ?? fr_ ti 1 cysr t 1_ cyc _ val ?? & fr_ ti 1 cysr t 1_ cyc _ msk ?? = fr_ mtctr mtct ?? fr_ ti 1 mtor t 1_ mtoffset ?? =
flexray communication controller freescale semiconductor 26-159 pxs20 microcontroller reference manual, rev. 1 26.6.17.2.1 absolute timer t2 if timer t2 is configured as an absolute timer, it has the same functionality ti mer t1 but the configuration from timer 2 configuration re gister 0 (fr_ti2cr0) and timer 2 configuration re gister 1 (fr_ti2cr1) is used. on expiration of timer t 2, the interrupt flag ti2_if in the protocol interrupt flag register 0 (fr_pifr0) is set. if the timer 1 interrupt enable bit ti1_ie in the protocol interrupt enable register 0 (fr_pier0) is asserted, an interrupt request is generated. 26.6.17.2.2 relative timer t2 if the timer t2 is configured as a relati ve timer, the interrupt flag ti2_if in the protocol interrupt flag register 0 (fr_pifr0) is set, when the programmed amount of macroticks mt[31:0], defined by timer 2 configuration regi ster 0 (fr_ti2cr0) and timer 2 configuration register 1 (fr_ti2cr1) , has expired since the trigger or restar t of timer 2. the relative timer is implemented as a down counter and expires when it has reached 0. at th e macrotick start event, the value of mt[31:0] is checked and then decremented. thus, if the timer is started with mt[ 31:0] == 0, it expires at the next macrotick start. 26.6.18 slot status monitoring the cc provides several means for slot status monitoring. all slot status monitors use the same slot status vector provided by the pe. th e pe provides a slot status vector for each static slot, for each dynamic slot, for the symbol window, and for the nit, on a per channe l base. the content of the slot status vector is described in table 26-126 . the pe provides the slot st atus vector within the first macrotick after the end of the related slot/window/nit, as shown in figure 26-158 . figure 26-158. slot status vector update note the slot status for the nit of cycle n is provided after the start of cycle n+1. cycle start slot start slot start symbol window start mt status(nit) mt status(slot 1) status(slot k) mt status(slot n) mt nit start status(sym.win) mt cycle start status(nit) communication cycle static segment dynamic segment symbol window nit slot 1 mt
flexray communication controller 26-160 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.6.18.1 channel status error counter registers the two channel status er ror counter registers, channel a status error count er register (fr_casercr) and channel b status error count er register (fr_cbsercr) , incremented by one, if at least one of four slot status error bits, vss!syntaxerror , vss!contenterror , vss!bviolation , or vss!txconflict is set to 1. the status vectors for all slots in the static and dynamic segment, in the symbol window, and in the nit are taken into account. the counters wrap roun d after they have reached the maximum value. table 26-126. slot status content status content static / dynamic slot slot related status vss!validframe - valid frame received vss!syntaxerror - syntax error occurred while receiving vss!contenterror - content error occurred while receiving vss!bviolation - boundary violation while receiving for slots in which the module transmits: vss!txconflict - reception ongoing while transmission starts for slots in which the module does not transmit: vss!txconflict - reception ongoing while transmission starts first valid - channel that has received the first valid frame received frame related status extracted from a) header of valid frame, if vss!validframe = 1 b) last received header, if vss!validframe = 0 c) set to 0, if nothing was received vrf!header!nfindicator - null frame indicator (0 for null frame) vrf!header!sufindicator - startup frame indicator vrf!header!syfindicator - sync frame indicator symbol window window related status vss!validframe - always 0 vss!contenterror - content error occurred while receiving vss!syntaxerror - syntax error occurred while receiving vss!bviolation - boundary violation while receiving vss!txconflict - reception ongoing while transmission starts received symbol related status vss!validmts - valid media test access symbol received received frame related status see static/dynamic slot nit nit related status vss!validframe - always 0 vss!contenterror - content error occurred while receiving vss!syntaxerror - syntax error occurred while receiving vss!bviolation - boundary violation while receiving vss!txconflict - always 0 received frame related status see static/dynamic slot
flexray communication controller freescale semiconductor 26-161 pxs20 microcontroller reference manual, rev. 1 26.6.18.2 protocol status registers the protocol status register 2 (fr_psr2) provides slot status informatio n about the network idle time nit and the symbol window. the protocol status re gister 3 (fr_psr3) provides aggregat ed slot status information. 26.6.18.3 slot status registers the eight slot status registers, slot status registers (fr_ssr0?fr_ssr7) , can be used to observe the status of static slots, dynamic slots, the symbol window, or the nit without individual message buffers. these registers provide all slot stat us related and received frame / symb ol related status information, as given in table 26-126 , except of the first valid indicator for non-transmission slots. 26.6.18.4 slot status counter registers the cc provides four slot stat us error counter registers, slot status counter registers (fr_sscr0?fr_sscr3) . each of these slot status counter re gisters is updated with the value of an internal slot status counter at th e start of a communication cycle. the internal slot status counter is incremented if its increment condition, defined by the slot status counter condition register (fr_ssccr) , matches the status vector provided by the pe. all static slots, the symbol window, and the nit status are taken into account. dynamic slots are excluded . the internal slot st atus counting and update timing is shown in figure 26-159 . figure 26-159. slot status counting and fr_sscrn update the pe provides the status of the nit in the first slot of the next cycle. due to these facts, the fr_sscrn register reflects, in cycle n, the stat us of the nit of cycle n-2, and the status of all static slots and the symbol window of cycle n-1. cycle start slot start slot start symbol window start mt status(nit) mt status(slot 1) status(slot k) mt status(slot n) mt nit start status(sym.win) mt cycle start status(nit) communication cycle static segment dynamic segment symbol window nit slot 1 mt incr. fr_sscrn_int on error incr. fr_sscrn_int on error fr_sscrn:= fr_sscrn_in fr_sscrn_int not updated r_sscrn:= fr_sscrn_int
flexray communication controller 26-162 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 the increment condition for each slot status counter c onsists of two parts, the frame related condition part and the slot related conditi on part. the internal slot status counter fr_sscrn_int is incremented if at least one of the conditions is fulfilled: 1. frame related condition: ? (fr_ssccrn[vfr] | fr_ssccrn[syf] | fr_ ssccrn[nuf] | fr_ssccrn[suf]) // count on frame condition = 1; and ? ((~fr_ssccrn[vfr] | vss!validframe ) & // valid frame restriction (~fr_ssccrn[syf] | vrf!header!syfindicator ) & // sync frame indicator restriction (~fr_ssccrn[nuf] | ~ vrf!header!nfindicator ) & // null frame indicator restriction (~fr_ssccrn[suf] | vrf!header!sufindicator )) // startup frame indicator restriction = 1; note the indicator bits syf, nuf, and su f are valid only when a valid frame was received. thus it is required to set the vfr always, whenever count on frame condition is used. 2. slot related condition: ? ((fr_ssccrn[statusmask[3]] & vss!contenterror ) | // increment on content error (fr_ssccrn[statusmask[2]] & vss!syntaxerror ) | // increment on syntax error (fr_ssccrn[statusmask[1]] & vss!bviolation ) | // increment on boundary violation (fr_ssccrn[statusmask[0]] & vss!txconflict )) // increment on transmission conflict = 1; if the slot status counter is in single cycle mode, i.e. fr_ssccrn[mc y] = 0, the internal slot status counter fr_sscrn_int is reset at each cycle start. if the slot status coun ter is in the multicycle mode, i.e. fr_ssccrn[mcy] = 1, the counter is not reset and incremented, until the maximum value is reached. 26.6.18.5 message buffer slot status field each individual message buffer and each fifo message buffer provides a slot status field, which provides the information shown in table 26-126 for the static/dynamic slot. the update conditions for the slot status field depend on the message buffer type. refer to the message buffer update sections in section 26.6.6, individual message buffer functional description . 26.6.19 system bus access this section provides a description of th e system bus accesses performed by the cc. all flexray memory area data located in the system memory are accessed via the system bus. there are two types of failures that can occu r during the system bus access, the system bus illegal address access and the system bus access timeout.
flexray communication controller freescale semiconductor 26-163 pxs20 microcontroller reference manual, rev. 1 the behavior of the cc after the occurrence of a syst em bus failure is defined by the sbff bit in the module configuration register (fr_mcr) . 26.6.19.1 system bus illegal address access if the system bus detects an cc access to an illegal a ddress, the cc receives a not ification from the system bus about this event and sets the ilsa_ef flag in the chi error flag register (fr_chierfr) . 26.6.19.2 system bus access timeout the cc starts a timer when it has send an access request to the system bus. this timer expires after 2 * fr_symator[timeout] + 2 system bus clock cycles. if the access is not finished within this amount of time, the sbcf_ef flag in the chi error flag register (fr_chierfr) is set. note the value of the timeout field should be set to greater than 1. for the value 1 and 0, a system bus access timeout error will occur in any case. 26.6.19.3 continue after system bus failure if the sbff bit in the module configuration register (fr_mcr) is 0, the cc will continue its operation after the occurrence of the system bus access failure but will not gene rate any system bus accesses until the start of the next communication cycle. if a frame is under transmission when the system bus failure occurs, a co rrect frame is generated with the remaining header and frame data are replaced by all ze ros. depending on the point in time this can affect the ppi bit, the header crc, the pa yload length in case of an dynamic slot, and the payload data. starting from the next slot in the current cycle, no frames wi ll be transmitted and recei ved, except for the key slot, where a sync or startup null-frame is tr ansmitted, if the ke y slot is assigned. if a frame is received when the sy stem bus failure occurs, the recepti on is aborted and the related receive message buffer is not updated. normal operation is resumed after th e start of next communication cycle. 26.6.19.4 freeze after system bus failure if the sbff bit in the module configuration register (fr_mcr) is set to 1, the cc wi ll go into the freeze mode immediately after the occurrence of one of the system bus access failures. 26.6.20 interrupt support the cc provides 108 individual in terrupt sources and five combined interrupt sources.
flexray communication controller 26-164 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.6.20.1 individual interrupt sources 26.6.20.1.1 message buffer interrupts the cc provides 64 message buffer interrupt sources. each individual message buffer provi des an interrupt flag fr_mbccsrn [mbif] and an interrupt enable bit fr_mbccsrn[mbie]. the cc sets th e interrupt flag when the slot status of the message buffer was updated. if the interrupt enable bit is asse rted, an interrupt request is generated. 26.6.20.1.2 fifo interrupts the cc provides 2 fifo interrupt sources. each of the 2 fifo provides a receive fifo almost full interrupt flag. the cc sets the receive fifo almost full interrupt flags (fr_gifer[ fafbif], fr_gifer[fafaif]) in the global interrupt flag and enable register (fr_gifer) if the corresponding receiv e fifo fill level exceed s the defined watermark. 26.6.20.1.3 wakeup interrupt the cc provides one interrupt s ource related to the wakeup. the cc sets the wakeup interrupt fl ag fr_gifer[wupif] when it ha s received a wakeup symbol on the flexray bus. the cc generates an interrupt request if the interrupt enable bit fr_gifer[wupie] is asserted. 26.6.20.1.4 protocol interrupts the cc provides 25 interrupt s ources for protocol related events. for details, see protocol interrupt flag register 0 (fr_pifr0) and protocol interrupt flag register 1 (fr_pifr1) . each interrupt source has its own interrupt enable bit. 26.6.20.1.5 chi interrupts the cc provides 16 interrupt sources for ch i related error events. for details, see chi error flag register (fr_chierfr) . there is one common interrupt enable bit fr_gifer[chie] for all chi error interrupt sources. 26.6.20.2 combined interrupt sources each combined interrupt source generates an interrupt request only when at least one of the interrupt sources that is combined ge nerates an interrupt request. 26.6.20.2.1 receive message buffer interrupt the receive message buffer interrupt request is gene rated when at least one of the individual receive message buffers generates an interr upt request mbxirq [n] and the interrupt enable bit fr_gifer[rbie] is set.
flexray communication controller freescale semiconductor 26-165 pxs20 microcontroller reference manual, rev. 1 26.6.20.2.2 transmit message buffer interrupt the transmit message buffer interrupt request is generated when at leas t one of the individual transmit message buffers generates an interr upt request mbxirq[n] and the inte rrupt enable bit fr_gifer[tbie] is asserted. 26.6.20.2.3 protocol interrupt the protocol interrupt request is generated when at le ast one of the individual protocol interrupt sources generates an interrupt request and the inte rrupt enable bit fr_gifer[prie] is set. 26.6.20.2.4 chi interrupt the chi interrupt request is generated when at leas t one of the individual chi error interrupt sources generates an interrupt request and the inte rrupt enable bit fr_gifer[chie] is set. 26.6.20.2.5 module interrupt the module interrupt request is genera ted if at least one of the combin ed interrupt sources generates an interrupt request and the interrupt enable bit fr_gifer[mie] is set.
flexray communication controller 26-166 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 26-160. scheme of fr_gifer interrupt signal generation interrupt sources interrupt signals fr_mbccsrn[mbif] n fr_chierfr[15:0] 16 fr_pifr0[15:0] 16 fr_pifr1[9:0] 10 receive message buffer interrupt chi interrupt fr_gifer[fafaif] rx fifo a almost full interrupt fr_gifer[wupif] wakeup interrupt fr_gifer[rbie] fr_mbccsrn[mtd] rxbuf txbuf fr_gifer[prie] fr_gifer[wupie] fr_mbccsrn[mbie] & fr_pier0[15:0] fr_pier1[9:0] or & & & fr_gifer[chie] & & n & or transmit message buffer interrupt fr_gifer[tbie] & n or or & & fr_gifer[fafaie] fr_gifer[fafbif] rx fifo b almost full interrupt & fr_gifer[fafbie] & fr_gifer[rbif] fr_gifer[tbif] fr_gifer[prif] fr_gifer[chif] protocol interrupt fr_gifer n pe or & module interrupt fr_gifer[mif] fr_gifer[mie] rx fifo a rx fifo b protocol interrupt chi interrupt wakeup interrupt rx fifo a almost full interrupt rx fifo b almost full interrupt receive message buffer interrupt transmit message buffer interrupt
flexray communication controller freescale semiconductor 26-167 pxs20 microcontroller reference manual, rev. 1 figure 26-161. scheme of fr_eeifer interrupt signal generation fr_eeifer[lrne_if] lram non-corrected error interrupt & lram ecc interrupt sources interrupt signals fr_eeifer fr_eeifer[lrne_ie] fr_eeifer[lrce_if] & fr_eeifer[lrce_ie] fr_eeifer[drne_if] & fr_eeifer[drne_ie] fr_eeifer[drce_if] & fr_eeifer[drce_ie] dram ecc lram corrected error interrupt dram non-corrected error interrupt dram corrected error interrupt
flexray communication controller 26-168 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 26-162. scheme of fr_cifr flags generation 26.6.21 lower bit rate support the cc supports a number of lower bit rates on the flexray bus channels. the lower bit rates are implemented by modifying the duration of the microtick pdmicrotick , the number of samples per microtick psamplespermicrotick , the number of samples per bit csamplesperbit , and the strobe offset cstrobeoffset. the application configures the flexray channel bit rate by setting the bitrate field in the module configuration register (fr_mcr) . the protocol values are set intern ally. the available bit rates, the related bitrate field configurati on settings and related protocol parameter values are shown in table 26-127 . interrupt sources fr_mbccsrn[mbif] n fr_chierfr[15:0] 16 fr_pifr0[15:0] 16 fr_pifr1[9:0] 10 fr_cifr[fafaif] fr_cifr[wupif] fr_mbccsrn[mtd] rxbuf txbuf or & n & or n or or fr_cifr[fafbif] fr_cifr[rbif] fr_cifr[tbif] fr_cifr[prif] fr_cifr[chif] fr_cifr n pe or fr_cifr[mif] rx fifo a rx fifo b
flexray communication controller freescale semiconductor 26-169 pxs20 microcontroller reference manual, rev. 1 note the bit rate of 8 mbit/ s is not defined by the flexray communications system protocol specifi cation, version 2.1 rev a. 26.6.22 pe data memory (pe dram) the pe data memory (pe dram) is 128 word, 16-bit wi de memory with byte acce ss, which contains the program data of the pe in ternal cpu. the pe dram is divided into two banks, 8-bit each. the memory data [7:0] are assigned to bank0, the memo ry data [15:8] are assigned to bank1. the flexray module provides means to access the pe dram from the application. the pe dram application access is initiated and controlled via pe dram access register (fr_pedrar) and pe dram data register (fr_pedrdr) . this functionality is used to check the memory error detection. 26.6.22.1 pe dram read access a read access from the pe dram can be initiated in any protocol state. the following sequence describes a read access from the pe dram address 0x70. 1. fr_pedrar:= 0x00e0; // inst=0x0; addr=070 2. wait until fr_pedrar[dad] == 1; // wait for end of pe dram access 3. val = fr_pedrdr[data]; // get read pe dram data table 26-127. flexray channel bit rate control flexray channel bit rate [mbit/s] fr_mcr.bitr ate pdmicrotick [ns] gdsampleclockperiod [ns] psamplespermicrotick csamplesperbit cstrobeoffset 10.0 000 25.0 12.5 2 8 5 8.0 011 25.0 12.5 2 10 6 5.0 001 25.0 25.0 1 8 5 2.5 010 50.0 50.0 1 8 5 table 26-128. pe dram layout addr bank1 bank0 0x00 byte1 byte0 0x01 byte3 byte2 ... 0x7f byte255 byte254
flexray communication controller 26-170 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 the read access is handled by the pe internal cpu wi th the lowest execution pr iority. this may cause an response delay with a maximum of 1000 pe clock cycle (25us). 26.6.22.2 pe dram write access a write access into the pe dr am can be initiated in any protocol state. the following sequence describes a write access to the pe dram address 0x70. 1. fr_pedrar:= 0x30e0; // inst=0x3; addr=0x70 2. wait until fr_pedrar[dad] == 1; // wait for end of pe dram access 3. val = fr_pedrdr[data]; // get read back pe dram data the write access is handled by the pe internal cpu wi th the lowest execution priority. this may causes an response delay with a maximu m of 1000 pe clock cycle (25us). if the conditions given in section 26.6.22.3, pe dram wr ite access limitations , are fulfilled, the data provided in pe dram data register (fr_pedrdr) are written into the pe dr am, read back in the next clock cycle and stored into the pe dram data register (fr_pedrdr) . otherwise, data are not written into the pe dram and 0x0000 is stored into the pe dram data register (fr_pedrdr) . 26.6.22.3 pe dram writ e access limitations the pe dram is used by the protocol engine if the module is not in poc:default config state. the only address not used by the protocol e ngine is 0x70. to prevent the corrupt ion of protocol engine data the following pe dram write access limitat ions apply for a pplication writes. 1. when the module is in poc:default config state, all pe dram addresses are writable. 2. when the module is not in poc:default config state, only pe dram address 0x70 is writable. 26.6.23 chi lookup-table memory (chi lram) the chi lookup-table memory (chi lram) is an ch i internal memory which contains the message buffer configuration data. the configuration data fo r two message buffers are contained in one memory row. the chi lram is divided into 6 memory banks. the chi lram is accessed by the application vi a regular register read and write accesses. table 26-129. chi lram layout adr bank5 bank4 bank3 bank2 bank1 bank0 0x00 fr_mbidxr1 fr_mbfidr1 fr_mbccfr1 fr_mbidxr0 fr_mbfidr0 fr_mbccfr0 0x01 fr_mbidxr3 fr_mbfidr3 fr_mbccfr3 fr_mbidxr2 fr_mbfidr2 fr_mbccfr2 ... 0x0f fr_mbidxr63 fr_mbfidr63 mbccf63 fr_mbidxr62 mbfid62 fr_mbccfr62
flexray communication controller freescale semiconductor 26-171 pxs20 microcontroller reference manual, rev. 1 26.6.24 memory content error detection the flexray module provides integrated memory cont ent error detection for both the chi lram and pe dram, and memory content error correction for the pe dram. the memory error detection for the chi lram uses an standard hamming code with a hamming distance of 3 and detects all single-bit and double-bit errors (sedded). the memory error dete ction and correction for the pe dram uses an enhanced hamming code with a hamming distance of 4 and detects and corrects all single-bit errors and detects all double-bit errors (secded). this section describes the reporting of the occurrence of memory content errors, the reactio n of the module on the occurrence, and how the appli cation can inject memory errors in order to trigger the report and response behavior. 26.6.24.1 memory error types a memory error is the distortion of one or more bits read out of the memory. the read ing of the values of all zeros and all ones is considered as an special case. the flexray module detects and indicates the memory errors as shown in table 26-130 . the entries on the top have higher priority. each memory read access reads out all banks of the addressed row, and runs error detection on all banks, even in the case that the applicat ion has triggered a read from only one bank. this ma y lead to the reporting of an memory error if at least one bank contains a memo ry error, even if an error free bank has been read. 26.6.24.2 memory error reporting the memory error reporting is enabled only if the ecc functionality enable bit ecce in the module configuration register (fr_mcr) is set. table 26-130. detected memory error types memory priority memo ry data indication chi lram 0 (highest) all zero?s no error - valid data pe dram non-corrected error chi lram all one?s non-corrected error pe dram chi lram 1 (lowest) one bit flipped non-corrected error pe dram corrected error chi lram two bits flipped non-corrected error pe dram chi lram three or more bits flipped one out of {no error, non-corrected error}, defined by coding given in section 26.6.24.2. 3, chi lram checkbits , and section 26.6.24.2.3, chi lram checkbits . pe dram one out of {no error, corrected error, non-corrected error}, defined by coding given in section 26.6.24.2.1, pe dram checkbits , and section 26.6.24.2.2, pe dram syndrome .
flexray communication controller 26-172 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 for each of the two memories exists two sets of intern al registers to store the detection of one corrected and one non-corrected memory error. if a memory error is detected, the module checks whether the related error interrupt flag in the ecc error interrupt flag and enab le register (fr_eeifer) is set. ? if the error interrupt flag is set, the related in ternal error reporting regist er is not updated and the related error overflow flag is set to 1 to indicate a loss of error condition. ? if the error interrupt flag is not set, the internal reporting register is updated and the error interrupt flag is set to 1. if two or more memory errors of the same type are det ected, the error for the bank with the lower bank number will be reported, a nd the error overflow flag will be set to 1. if a memory error is detected for at least two banks of one memory, the related error overflow flag is set to 1 to indicate a loss of error condition. 26.6.24.2.1 pe dram checkbits the coding of the checkbits reported in ecc error report code register (fr_eercr) for pe dram memory errors is shown in table 26-132 . this table shows the implemen ted enhanced hamming code. if the error injection was applied to distort the checkbits, then the distorted checkbits are reported. 26.6.24.2.2 pe dram syndrome the coding of the syndrome reported in ecc error report code register (fr_eercr) for pe dram memory errors is shown in table 26-132 . table 26-131. pe dram checkbits coding code code data 3 2 1 0 7 6 5 4 3 2 1 0 4 1 notes: 1 the checkbit code[4] is set to 1 if and only if there is a even number of 1?s in columns with x. x x x x x x x x x x x x 3 2 2 the checkbits code[3]... code[0 ] are set to 1 if and only if there is a odd number of 1?s in all columns with x. this coding of the checkbit ensures that ne ither 0x000 nor 0xfff are valid code words and written into the memory. - - - - x x x x - - - - 2 - - - - x - - - x x x - 1 - - - - - x x - x x - x 0 - - - - - x - x x - x x
flexray communication controller freescale semiconductor 26-173 pxs20 microcontroller reference manual, rev. 1 26.6.24.2.3 chi lram checkbits the coding of the checkbits reported in ecc error report code register (fr_eercr) for chi lram memory errors is shown in table 26-133 . this table shows the implemen ted hamming code. if the error injection was applied to distort the checkbits , then the distorted checkbits are reported. ??? table 26-132. fr_eercr[code] pe dram syndrome coding fr_eercr[code] description [4] [3:0] 0x1 0x0 no error (never appears in error report registers) 0x0 0x0 if data == 0: non corrected error (dedicated handling of all zero code word) if data!= 0: corrected error (parity bit 4) 0x0 0x1 corrected error (parity bit 0) 0x0 0x2 corrected error (parity bit 1) 0x0 0x3 corrected error (data bit 0) 0x0 0x4 corrected error (parity bit 2) 0x0 0x5 corrected error (data bit 1) 0x0 0x6 corrected error (data bit 2) 0x0 0x7 corrected error (data bit 3) 0x0 0x8 corrected error (parity bit 3) 0x0 0x9 corrected error (data bit 4) 0x0 0xa corrected error (data bit 5) 0x0 0xb corrected error (data bit 6) 0x0 0xc corrected error (data bit 7) 0x0 0xd-0xf non-corrected error 0x1 0x1-0xf non-corrected error table 26-133. chi lram checkbits coding code 1 notes: 1 the checkbit code[n] is set to 1 if and only if th ere is a odd number of 1?s in all columns with x. data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4 x x x x x - - - - - - - - - - - 3 - - - - - x x x x x x x - - - - 2 x x - - - x x x x - - - x x x - 1 - - x x - x x - - x x - x x - x 0 x - x - x x - x - x - x x - x x
flexray communication controller 26-174 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.6.24.2.4 chi lram syndrome the coding of the syndrome reported in ecc error report code register (fr_eercr) for chi lram memory errors is shown in table 26-134 . 26.6.24.3 memory error response the memory error response is enabled only when the ecc functionality enable bit ecce in the module configuration register (fr_mcr) is set. in case of the detection of a corrected memory error, the flexray m odule continues its normal operation using the corrected data word. th is section describes the behavior of the flexray module after the detection of a non-corrected memory error. 26.6.24.3.1 chi lram memory error response after module read the flexray module reads the message buffer confi guration buffer data located in the chi lram for each each message buffer one time in each slot and in the nit. if a non-corrected memory error is detected duri ng this module read access, the flexray module will consider the affected message buffer as disabled fo r the current search and will exclude this buffer from the search. the configuration of the af fected message buffe r is not changed. if the affected message buffer is a tx message buffer, no frame will be transmitte d from this message buffer in the next slot. if the affected message buffer is a rx message buffer, no frame will be received to this message buffer in the next slot. 26.6.24.3.2 chi lram memory erro r response after application read the application can read the content of the ch i lram via reading the fr_mbccfrn, fr_mbfidrn, and fr_mbidxrn registers. if a non-corrected memory error is det ected during this ki nd of read access, the module indicates the detected memory error, de livers the non-corrected data read and continues its normal operation. 26.6.24.3.3 pe dram error response after module read if the module detects an non-corrected memory error during read of program data which is contained in pe dram, this is considered as an fatal protocol error and the module enters the protocol freeze state immediately. table 26-134. fr_eercr[code] chi lram syndrome coding fr_eercr[co de] description 0x00 no error (never appears in error report registers) 0x01-0x1f non corrected error
flexray communication controller freescale semiconductor 26-175 pxs20 microcontroller reference manual, rev. 1 26.6.24.3.4 pe dram error res ponse after appli cation read in poc:default config state if the module detects an non-corrected memory error during an application tri ggered read from any pe dram address and the protocol is in the poc:default config state, this is consider ed as an fatal protocol error and the module enters the protocol freeze st ate. this behavior allows for checking the freeze functionality in case of the detection of non-corrected errors. 26.6.24.3.5 pe dram er ror response after appl ication read out of poc:default config if the module detects an non-corrected memory error during an application tri ggered read from any pe dram address, and the pr otocol is not in the poc:default config state, this error is not considered as an fatal error and the protocol state is not changed. this prevents any interference of the running protocol by pe dram error injection reads. 26.6.25 memory error injection the error injection functionality is us ed by the application to inject data errors into the memories to trigger and check the memory erro r detection functionality. the error injection is enabled only if the ecc functionality enable bit ecce in the module configuration register (fr_mcr) and the error injection enab le control bit eie in the ecc error report and injection control register (fr_eericr) are set. the error injection mode is configured by the eim configuration bit in the ecc error report and injection control register (fr_eericr) .when the error injection is enabled, each write access to the configured memory location will be distorted. the injector has the same behavior for flexray m odule memory writes and appl ication memory writes. 26.6.25.1 chi lram error injection the following sequence describes an error injection sequence for the chi lram. this sequence includes the setup of the error injector foll owed by an application tr iggered write access to provoke an distortion of the memory content. when the flexray module is in poc:default config , there are no limitations and impacts of error injection for the a pplication. for error injection out of poc:default config see section 26.7.2, chi lram error inject ion out of poc:default config . injector setup: 1. fr_mcr[ecce]:= 1; - enable ecc functionality 2. fr_eerice[eie]:=i_mode; - configure error injection mode 3. fr_eeiar[mid]:= 1; - select chi lram for error injection 4. fr_eeiar[bank]:= i_bank; - define the bank for error injection; i_bank = {0,1,2,3,4,5}
flexray communication controller 26-176 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 5. fr_eeiar[addr]:= i_addr; - define the address for error injection; 0<= i_addr <= 0x0f 6. fr_eeidr[data]:= d_dist; - define the data distortion pattern 7. fr_eeicr[code]:= c_dist; - define the checkbit distortion pattern 8. fr_eerice[eie]:=1; - enable error injection application write access: 1. if (i_bank==0) -> fr_mbccfr(2*i_addr):= data; if (i_bank==1) -> fr_m bfidr(2*i_addr):= data; if (i_bank==2) -> fr_m bidxr(2*i_addr):= data; if (i_bank==3) -> fr_mbcc fr(2*i_addr+1):= data; if (i_bank==4) -> fr_m bfidr(2*i_addr+1):= data; if (i_bank==5) -> fr_mbi dxr(2*i_addr+1):= data; - write data to the defined inj ection bank and in jection address 26.6.25.2 pe dram error injection the following sequence describes an error injection sequence for the pe dram. this sequence includes the setup of error injector followed by an application triggered write ac cess to provoke an distortion of the memory content. when the flexray module is in poc:default config , there are no limitations and impacts of error injection for the application. for er ror injection out of poc:default config see section 26.7.3, pe dram error injection out of poc:default config . injector setup: 1. fr_mcr[ecce]:= 1; - enable ecc functionality 2. fr_eerice[eie]:=i_mode; - configure error injection mode 3. fr_eeiar[mid]:= 0; - select pe dram for error injection 4. fr_eeiar[bank]:= i_bank; - define the bank for error injection; i_bank = {0,1} 5. fr_eeiar[addr]:= i_addr; - define the address for erro r injection; 0<= i_addr <= 0x7f 6. fr_eeidr[data]:= d_dist; - define the data distortion pattern 7. fr_eeicr[code]:= c_dist; - define the checkbit distortion pattern 8. fr_eerice[eie]:=1; - enable error injection
flexray communication controller freescale semiconductor 26-177 pxs20 microcontroller reference manual, rev. 1 application write access (i_addr=0x70): 1. fr_pedrar:= 0x30e0; // inst=0x3; addr=0x70 2. wait until fr_pedrar[dad] == 1; // wait for end of pe dram access 3. val = fr_pedrdr[data]; // get read back pe dram data note: the write access to the pe dram triggers an read from pe dram in the next cycle, which triggers the detection of the distorted data. 26.7 application information 26.7.1 initialization sequence this section describes the required steps to initialize the cc. the fi rst subsection describes the steps required after a system rese t, the second section describes the step s required after pre ceding shutdown of the cc. 26.7.1.1 module initialization this section describes the module related initialization steps after a system reset. 1. configure cc. a) configure the control bits in the module configuratio n register (fr_mcr) b) configure the system memory base address in system memory base address register (fr_symbadr) 2. enable the cc. a) write 1 to the module enable bit men in the module configuration register (fr_mcr) the cc now enters the normal mode. the applicati on can commence with the protocol initialization described in section 26.7.1.2, protocol initialization . 26.7.1.2 protocol initialization this section describes the protocol related initialization steps. 1. configure the protocol engine. a) issue config command via protocol operation control register (fr_pocr) b) wait for poc:config in protocol status register 0 (fr_psr0) c) configure the fr_pcr0,..., fr_pcr30 regist ers to set all protocol parameters 2. configure the message buffers and fifos. a) set the number of message buffers used a nd the message buffer segmentation in the message buffer segment size and utili zation register (fr_mbssutr) b) define the message buffer data size in the message buffer data size register (fr_mbdsr) c) configure each message buffer by sett ing the configuration values in the message buffer configuration, control, st atus registers (fr_mbccsrn) , message buffer cycle counter
flexray communication controller 26-178 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 filter registers (fr_mbccfrn) , message buffer frame id registers (fr_mbfidrn) , message buffer index registers (fr_mbidxrn) d) configure the fifos e) issue config_complete command via protocol operation control register (fr_pocr) f) wait for poc:ready in protocol status re gister 0 (fr_psr0) after this sequence, the cc is conf igured as a flexray node and is ready to integrate into the flexray cluster. 26.7.1.3 chi lram initialization the module will start reading chi lram data if it has entered the start up state, thus, all ecc bits have to set correctly. to fulfill this requi rement, the application must write in itial values into all message buffer configuration registers fr_mbccfrn, fr_mbfidrn, and fr_mbi dxrn during the protocol config state, even if the message buffers are not used. 26.7.1.4 pe dram initialization the pe dram initialization is performed by the module in the poc:default config state. this initialization runs for 4.8 ? s, and will delay the state transition from poc:default config into poc:config . 26.7.2 chi lram error injection out of poc:default config when the flexray module is out of the poc:default config state, it reads the configuration data of all utilized message buffe rs in every slot. if the m odule reads the chi lr am address that wa s used for error injection, an memory error is detected and the messa ge buffer is not used for transmission or reception. this section describes how to inject errors on the chi lram without disturbi ng the running application. ? set injection address to fr_eei dr[addr] = 0x0f- only the last tw o message buffers are affected by error injection ? utilize less than 63 message buffe rs; fr_mbssutr[last_mb_util]<=62 - the last two message buffers are not used and configuration data are not read by the module 26.7.3 pe dram error injection out of poc:default config when the flexray module is out of the poc:default config state, only the pe dram address 0x70 is writable by the application. this locat ion is not used by the flexray module. 26.7.4 shut down sequence this section describes a secure s hut down sequence to stop the cc gra cefully. the main targets of this sequence are ? finish all ongoing reception and transmission ? do not corrupt flexray bus and do not disturb ongoing flexray bus communication
flexray communication controller freescale semiconductor 26-179 pxs20 microcontroller reference manual, rev. 1 for a graceful shutdown the applicati on shall perform the following tasks: 1. disable all enabled message buffers. a) repeatedly write 1 to fr_mbccsrn[ edt] until fr_mbccsrn[eds] == 0. 2. stop protocol engine. a) issue halt command via protocol operation cont rol register (fr_pocr) b) wait for poc:halt in protocol status register 0 (fr_psr0) 26.7.5 number of usable message buffers this section describes the relationshi p between the number of message buffers that can be utilized and the required minimum chi clock frequenc y. additional constraints for the minimum chi clock frequency are given in section 26.3, controller ho st interface clocking . the cc uses a sequential search algorithm to de termine the individual me ssage buffer assigned or subscribed to the next slot. this search must be finished within one flexray slot. the shortest flexray slot is an empty dynamic slot. an empty dyna mic slot is a minisl ot and consists of gdminislot macroticks with a nominal duration of gdmacrotick . the minimum duration of a corrected macrotick is gdmacrotick min = 39 ? t. this results in a minimum slot length of eqn. 26-30 the search engine is located in the chi and runs on the chi clock. it evaluates one individual message buffer per chi clock cycle. for inte rnal status update and double buffer commit operations, and as a result of the clock domain crossing jitter, an additional amount of 10 chi cloc k cycles is required to ensure correct operation. for a given number of message buffers and for a given chi clock frequency f chi , this results in a search duration of eqn. 26-31 the message buffer search must be finish ed within one slot which requires that equation 26-32 must be fulfilled eqn. 26-32 this results in the formula given in equation 26-33 which determines the required minimum chi frequency for a given number of me ssage buffers that are utilized. eqn. 26-33 the minimum chi frequency for a selected set of relevant protocol parameters is given in table 26-135 . table 26-135. minimum f chi [mhz] examples (64 message buffers) pdmicrotick [ns] gdminislot 234567 25.0 37.94 25.30 18.98 15.18 12.65 10.84 50.0 18.98 12.65 9. 45 7.59 6.33 5.43 ? slotmin 39 pdmicrotick gdminislot ?? = ? search 1 f chi ------- # messagebuffers 10 + ?? ? = ? search ? slotmin ? f chi # messagebuffers 10 + 39 pdmicrotick gdminislot ?? --------------------------------------------------------------------- - ?
flexray communication controller 26-180 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 26.7.6 protocol control command execution this section considers the issues of the protocol control command execution. the application issues any of the protocol co ntrol commands listed in the poccmd field of table 26-16 by writing the command to the poccmd field of the protocol operation cont rol register (fr_pocr) . as a result the cc sets the bsy bit while the command is transferred to the pe. when the pe has accepted the command, the bsy flag is cleared. all commands are accepted by the pe. the pe maintains a protocol comma nd vector. for each command that wa s accepted by the pe, the pe sets the corresponding command bit in the protocol comm and vector. if a command is issued while the corresponding command bit is set, the command is not queued and is lost. if the command execution block of the pe is idle, it selects the next accepted protocol command with the highest priority from the current protocol command vector according to the protocol control command priorities given in table 26-136 . if the current protocol state does not allow the execution of this protocol command (see poc state changes in flexray communications system pr otocol specification, version 2.1 rev a ) the cc asserts the illegal protocol command interrupt flag ipc_if in the protocol interrupt flag register 1 (fr_pifr1) . the protocol command is not executed in this case. some protocol commands may be inte rrupted by other commands or the de tection of a fatal protocol error as indicated by table 26-136 . if the application issues the free ze or ready command, or if the pe detects a fatal protocol error, some commands already stored in the co mmand vector will be removed from this vector. table 26-136. protocol control command priorities protocol command priority interrupted by cleared and terminated by freeze (highest) 1 none ready 2 config_complete 3 all_slots 4 freeze, ready, config_complet, fatal protocol error freeze, ready, config_complete, fatal protocol error allow_coldstart 5 run 6 freeze, fatal protocol error wakeup 7 freeze, fatal protocol error default_config 8 freeze, fatal protocol error config 9 halt (lowest) 10 freeze, ready, config_complete, fatal protocol error
flexray communication controller freescale semiconductor 26-181 pxs20 microcontroller reference manual, rev. 1 26.7.7 message buffer search on si mple message buffer configuration this sections describes the messag e buffer search behavior for a simp lified message buffer configuration. the fifo behavior is not c onsidered in this section. 26.7.7.1 simple message buffer configuration a simple message buffer conf iguration is a configurati on that has at most one tr ansmit message buffer and at most one receive messag e buffer assigned to a slot s . the simple configuration used in this section utilizes two message buff ers, one single buffered transmit message buffer and one receive message buffer. the transmit message buffer has the message buffer number t and has following configuration the availability of data in the transmit buffer is indicated by the commit bi t fr_mbccsrt[cmt] and the lock bit fr_mbccsrt[lcks]. the receive message buffer has the message buffer number r and has following configuration table 26-137. transmit buffer configuration register field value description fr_mbccsr t mcm - used only for double buffers mbt 0 single transmit buffer mtd 1 transmit buffer fr_mbccfr t mtm 0 event transition mode cha 1 assigned to channel a chb 0 not assigned to channel b ccfe 1 cycle counter filter enabled ccfmsk 000011 cycle set = {4n} = {0,4,8,12,...} ccfval 000000 fr_mbfidr t fid s assigned to slot s table 26-138. receive buffer configuration register field value description fr_mbccsr r mcm - n/a mbt - n/a mtd 0 receive buffer
flexray communication controller 26-182 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 furthermore the assumption is that both message buffers are enabled (fr_mbccsr t [eds] = 1 and fr_mbccsr r [eds] = 1) note the cycle set {4n+2} = {2,6,10,...} is assigned to the receive buffer only. the cycle set {4n} = {0,4,8,12,...} is assigned to both buffers. 26.7.7.2 behavior in static segment in this case, both message buffers are assigned to a slot s in the static segment. the configuration of a transm it buffer for a static slot s assigns this slot to the node as a transmit slot. the flexray protocol requires: ? when a slot occurs, if the slot is assigned to a node on a channel that node must transmit either a normal frame or a null frame on that channel. specifically, a null fram e will be sent if there is no data ready, or if there is no match on a transmit filt er (cycle counter f iltering, for example). regardless of the availability of data and the cycle counter fi lter, the node will transm it a frame in the static slot s. in any case, the result of the message buffe r search will be the tr ansmit message buffer t. the receive message buffer r will not be found, no reception is possible. 26.7.7.3 behavior in dynamic segment in this case, both message buf fers are assigned to a slot s in the dynamic segment. the flexray protocol requires: ? when a slot occurs, if a slot is assigned to a node on a channel that node onl y transmits a frame on that channel if there is data ready and there is a match on relevant transmit filters (no null frames are sent). the transmission of a frame in the dynamic segment is determined by the av ailability of data and the match of the cycle counter filter of the transmit message buffer. fr_mbccfr r mtm - n/a cha 1 assigned to channel a chb 0 not assigned to channel b ccfe 1 cycle counter filter enabled ccfmsk 000001 cycle set = {2n} = {0,2,4,6,...} ccfval 000000 fr_mbfidr r fid s subscribed slot table 26-138. receive buffer configuration (continued) register field value description
flexray communication controller freescale semiconductor 26-183 pxs20 microcontroller reference manual, rev. 1 26.7.7.3.1 transmit data not available if transmit data are not available , i.e. the transmit buffer is not committed fr_mbccsr t [cmt]=0 and/or locked fr_mbccsr t [lcks]=1, a) for the cycles in the set {4n}, which is assigned to both buffers, the receiv e buffer will be found and the node can receive data, and b) for the cycles in the set {4n+2}, which is assigne d to the receive buffer only, the receive buffer will be found and the node can receive data. the receive cycles are shown in figure 26-163 figure 26-163. transmit data not available 26.7.7.3.2 transmit data available if transmit data are available, i.e. the transmit buffe r is committed fr_mbccsr t [cmt]=1 and not locked fr_mbccsr t [lcks]=0, a) for the cycles in the set {4n}, which is assigned to both buffers, the transm it buffer will be found and the node transmits data. b) for the cycles in the set {4n+2}, which is assigne d to the receive buffer only, the receive buffer will be found and the node can receive data. the receive and transmit cycles are shown in figure 26-163 figure 26-164. transmit data not available 0 rx 1 2 rx 3 4 rx 5 6 rx 7 59 60 rx 61 62 rx 8 rx 63 0 tx 1 2 rx 3 4 tx 5 6 rx 7 59 60 tx 61 62 rx 8 tx 63
flexray communication controller 26-184 freescale semiconductor pxs20 microcontroller reference manual, rev. 1
frequency-modulated phase-locked loop (fmpll) freescale semiconductor 27-1 pxs20 microcontroller reference manual, rev. 1 chapter 27 frequency-modulated phase-locked loop (fmpll) 27.1 introduction this section describes the features and functions of the two independent fmpll mo dules implemented in pxs20. 27.2 overview the fmplls allow the user to generate high speed system clocks from a common 4?40 mhz input clock. further, the fmplls support progr ammable frequency modulation of the system clock. the fmpll multiplication factor and the output clock divider ratio are software-configurable. pxs20 has two fmplls: one for the system clock using frequency modul ation (fm) and one that can be used for motor control peripherals. the fmpll?s block di agram is shown in figure 27-1 . figure 27-1. fmpll block diagram 27.3 features the fmpll has the following major features: ? input clock frequency from 4?40 mhz ? voltage controlled oscillato r (vco) range from 256?512 mhz (see section 27.7, requirements ) ? reduced frequency divider (rfd ) for reduced frequency operation without forcing the fmpll to relock ? frequency modulated phase-locked loop (fmpll) ? modulation enabled/disabled through software ? triangle wave modulation ? programmable modulation depth ? 0.25% to 4% deviation fr om center spread frequency ? ?0.5% to ?8% deviation fr om down spread frequency ? programmable modulation frequency dependent on reference frequency ? self-clocked mode (scm) operation phase/frequency detector vco idf ndiv loop frequency divider clkin odf phi charge pump loop filter
frequency-modulated phase-locked loop (fmpll) 27-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? four operating modes ? normal mode ? progressive clock swit ching (only on fmpll_0 for the system clock) ? normal mode with spread sp ectrum clock generation (sscg) ? powerdown mode 27.4 memory map the fmplls are mapped through the mc_cgm register slot. table 27-1 shows the memory map locations. addresses are given as offsets of the module base address. 27.5 register descriptions the fmpll operation is controlled by two registers. these registers can only be written in supervisor mode. 27.5.1 control register (cr) table 27-1. fmpll memory map address register access base: 0xc3fe_00a0 (fmpll_0) 0xc3fe_00c0 (fmpll_1) 0x0000 control register - cr r/w 0x0004 modulation register special offset 0x0000 access: user read, supervisor read/write 0123456789101112131415 r 0 0 idf odf 0 ndiv w reset 0000010101000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000 en_pll _sw 0 00i_lock s_lock pll_fail _mask pll_fail _flag 1 w w1c w1c reset 0000000000000001 figure 27-2. control register (cr)
frequency-modulated phase-locked loop (fmpll) freescale semiconductor 27-3 pxs20 microcontroller reference manual, rev. 1 table 27-2. cr field descriptions field description 2-5 idf the value of this field sets the fmpll input division factor as described in ta b l e 2 7 - 3 . the reset value is set during integration. 6-7 odf the value of this field sets the fmpll output division factor as described in table 27-4 . the reset value is set during integration. 9-15 ndiv the value of this field sets the fmpll loop division factor as described in table 27-5 . the reset value is set during integration. 23 en_pll_sw this bit is used to enable progressive clock switching. 0 progressive clock switching disabled 1 progressive clock switching enabled 24-25 reserved 27 i_lock this bit is set by hardware whenever there is a lo ck/unlock event.it is cleared by software, writing 1. 28 s_lock this bit is an indication of wh ether the fmpll has acquired lock. 0 fmpll unlocked 1 fmpll locked 29 pll_fail_mask this bit is used to mask the pll_fail output. 0 pll_fail not masked 1 pll_fail masked 30 pll_fail_flag this bit is asynchronously set by hardware whenever a loss of lock event occurs while fmpll is switched on. it is cleared by software, writing 1. table 27-3. input divide ratios idf[3:0] input division factor (idf) 0000 divide by 1 0001 divide by 2 0010 divide by 3 0011 divide by 4 0100 divide by 5 0101 divide by 6 0110 divide by 7 0111 divide by 8 1000 divide by 9 1001 divide by 10 1010 divide by 11 1011 divide by 12
frequency-modulated phase-locked loop (fmpll) 27-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 1100 divide by 13 1101 divide by 14 1110 divide by 15 1111 clock inhibit table 27-4. output divide ratios odf[1:0] output division factor (odf) 00 divide by 2 01 divide by 4 10 divide by 8 11 divide by 16 table 27-5. loop divide ratios ndiv[6:0] loop divide factor (ldf) 0000000-0011111 na 0100000 divide by 32 0100001 divide by 33 0100010 divide by 34 ... ... 1011111 divide by 95 1100000 divide by 96 1100001-1111111 na table 27-3. input divide ratios (continued) idf[3:0] input division factor (idf)
frequency-modulated phase-locked loop (fmpll) freescale semiconductor 27-5 pxs20 microcontroller reference manual, rev. 1 27.5.2 modulation register (mr) offset 0x0004 access: user read, supervisor read/write 01234567 8 9101112131415 rstr b_b ypa ss 0 spr d_s el mod_period w reset00000000 0 00 0 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ssc g_e n inc_step w reset00000000 0 00 0 0000 figure 27-3. modulation register (mr) table 27-6. mr field descriptions field description 0 strb_bypa ss strobe bypass the strb_bypass signal is used to bypass the strb signal used inside fmpll to latch the correct values for control bits (inc_step, mod_period and sprd_sel). 0 = strb is used to latch fmpll modulation control bits 1 = strb is bypassed. in this case control bits need to be static. the control bits must be changed only when fmpll is in power down mode. 2 sprd_sel spread type selection the sprd_sel control the spread type in frequency modulation mode. 0 = center spread 1 = down spread 3-15 mod_perio d modulation period the mod_period field is the binary equivalent of the value modperiod derived from following formula: where: fref: represents the output frequency of the feedback divider fmod : represents the modulation frequency modperiod f ref 4 f mod ? ------------------- =
frequency-modulated phase-locked loop (fmpll) 27-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 27.6 functional description 27.6.1 normal mode in normal mode the fmpll inputs are driven by the cr. this means that, when the fmpll is in lock state, the fmpll output clock (phi) is derived by the reference clock (xosc) through this relation: where the value of idf , ldf and odf are set in cr and can be derived from table 27-3 , table 27-4 , and table 27-5 . see also section 27.7, requirements . 27.6.2 progressive clock switching progressive clock swit ching is expected to be used on system clock. when changing the system clock to run on a pll frequency, the pll lock s at a divided frequency, then gr adually decreases the division until it is divided by 1. (see illustration below.) the effect is to gradually increase current consumption instead of a single large increase. figure 27-4. illustration of progressive clock switching the gradual transition is further illustrated in table 27-7 . 16 sscg_en frequency modulation enable the sscg_en enables the frequency modulation. 0 = frequency modulation disabled 1= frequency modulation enabled 17-31 inc_step increment step the inc_step field is the binary equivalent of the value incstep derived from following formula: where: md : represents the peak modulation depth in percentage (center spread -- pk-pk=+/-md, downspread -- pk-pk=-2*md) mdf : represents the nominal value of loop di vider (ndiv in fmpll control register) table 27-6. mr field descriptions (continued) field description incstep round 2 15 1 ? ?? md ? mdf ? 100 5 ? modperiod ? -------------------------------------------------------------- ?? ?? = phi xosc ldf ? idf odf ? ---------------------- - = pll lock frequency division factor of 8, then 4, then 2, then 1 pll output clock
frequency-modulated phase-locked loop (fmpll) freescale semiconductor 27-7 pxs20 microcontroller reference manual, rev. 1 progressive clock switching is enabled using the cr[en_pll_sw] field. 27.6.3 normal mode with frequency modulation the fmpll default mode is wit hout frequency modulation enabled. when frequency modulation is enabled, however, two parameters must be set to ge nerate the desired level of modulation: the period, and the step. the modulation waveform is always a triangle wave and its sh ape is not programmable. fm modulation is activa ted using these steps: 1. configure the fm modulation char acteristics: mod_period, inc_step. 2. enable the fm modulation by programming the sscg_ en bit of mr register to 1. fm modulated mode can be enabled only when fmpll is in lock state. to latch these values inside the fmpll, two wa ys are used depending on the value of strb_bypass register bit in mr. if strb_bypass is low, the modulation parameters are latched in the fmpll only when the strb signal goes high. the strb signal is automatically generated in the fmpll when the modulation is enabled (sscg_en goes high) if the fmpll is lock ed (s_lock=1) or when the modulation has been enabled (sscg_en=1) and fmpll enters in lock state (s_lock goes high). if strb_bypass is high, the strb signal is bypassed. in this case, control bits (m od_period[12:0], inc_step[14:0], spread_c ontrol) must be changed only when the fmpll is in power down mode. the modulation depth in % is table 27-7. progressive clock switching for 120 mhz fmpll operation fmpll lock frequency division factor fmpll output clock frequency number of fmpll output clock cycles during division number of fmpll lock frequency cycles during division 120 mhz 8 15 mhz 15 120 120 mhz 4 30 mhz 30 120 120 mhz 2 60 mhz 60 120 120 mhz 1 120 mhz onward ? modulationdepth 100 5 ? incstep modperiod ? ? 2 15 1 ? ?? mdf ? ---------------------------------------------------------------------------------------------- ?? ?? =
frequency-modulated phase-locked loop (fmpll) 27-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 note you must ensure that the product of inctep and modperio d is less than (2 15 -1) and modperiod is less than or equal to 2 12 . figure 27-5. frequency modulation 27.6.4 powerdown mode the fmpll can be switched off when not require d to achieve lower consumption by programming the me_x_mc registers in the mc_me module. 27.7 requirements the fmpll vco frequency f vco , defined in equation 27-1 , must be in the range 256?512 mhz. eqn. 27-1 care is required when programming the multiplication and division fact ors to respect this requirement. as a result, the maximum system frequency cannot be reached with all supported (4 mhz to 40 mhz) xosc clock frequencies. before se lecting the xosc clock frequency, you must verify which system clock frequencies will be supported by the available settings for ndiv, idf, odf, and other parameters. 27.8 recommendations to avoid any unpredictable behavior of the fmpll clock, it is recommended to respect the following guidelines: ? you must change the multiplication, division fa ctors only when the fmpll output clock is not selected as the source for an active clock on the chip. mo d_period, inc_step, spread_sel bits should be modified before activating the fm modulated mode. then strobe has to be generated time frequency f0 f0 center spread down spread md md 2 md t mod 2t mod f vco clkin idf ------------------ ndiv ? =
frequency-modulated phase-locked loop (fmpll) freescale semiconductor 27-9 pxs20 microcontroller reference manual, rev. 1 to enable the new settings. if strb_byp is set to 1 then mod_period, inc_step and spread_sel can be modified only wh en fmpll is in power down mode. ? use progressive clock swit ching for the system clock.
frequency-modulated phase-locked loop (fmpll) 27-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1
interrupt controller (intc) freescale semiconductor 28-1 pxs20 microcontroller reference manual, rev. 1 chapter 28 interrupt controller (intc) 28.1 introduction 28.1.1 module overview the interrupt controller (intc) provi des priority-based preemptive sche duling of interrupt requests. this scheduling scheme is suitable for statically scheduled hard real-t ime systems. the intc supports 256 interrupt requests. it is targeted to work with a power architecture processo r and automotive powertrain applications where the isrs nest to multiple levels, but it also can be used with other processors and applications. for high priority interrupt requests in these target app lications, the time from the assertion of the interrupt request from the peripheral to when th e processor is performing useful work to service the interrupt request needs to be minimized. the intc supports this goal by providing a unique ve ctor for each interrupt request source. it also provi des 16 priorities so that lower priority isrs do not delay the execution of higher priority isrs. since each individual a pplication will have different priori ties for each source of interrupt request, the priority of each inte rrupt request is configurable. when multiple tasks share a resour ce, coherent accesses to that resource need to be supported. the intc supports the priority ceiling protoc ol for coherent accesses. by providi ng a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource can not preempt each other. multiple processors can assert interru pt requests to each other through soft ware settable interrupt requests. these same software settable interr upt requests also can be used to break the work involved in servicing an interrupt request into a high pr iority portion and a low priority portion. the high priority portion is initiated by a peripheral inte rrupt request, but then the isr can assert a software settable interrupt request to finish the servicing in a lower pr iority isr. therefore th ese software settable in terrupt requests can be used instead of the peripheral isr scheduling a task through the rtos. 28.1.2 block diagram figure 28-1 shows a block diagram of the interrupt controller (intc).
interrupt controller (intc) 28-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 28-1. intc block diagram 28.1.3 features ? supports 248 peripheral interrupt and 8 software-configurable interrupt request sources ? 9-bit vector ? unique vector for each interrupt request source. ? hardware connection to processor or read from register. ? each interrupt source can be progr ammed to one of 16 priorities. ? preemption ? preemptive prioritized inte rrupt requests to processor. ? isr at a higher priority preempts isrs or tasks at lower priorities. ? automatic pushing or popping of preemp ted priority to or from a lifo. ? ability to modify the isr or task priority. modi fying the priority can be used to implement the priority ceiling protocol fo r accessing shared resources. ? low latency - three clocks from re ceipt of interrupt reque st from peripheral to interrupt request to processor. peripheral bus hardware vector enable software set/clear interrupt registers flag bits peripheral interrupt requests module configuration register highest priority 4 priority comparator slave interface for reads & writes 1 push/update/acknowledge 1 1 1 update interrupt vector 1 interrupt request to processor memory mapped registers non-memory mapped logic end of interrupt register request selector priority arbitrator highest priority interrupt requests n 1 n 1 vector encoder interrupt vector 9 processor 0 interrupt acknowledge register interrupt vector 9 n 1 8 n 1 x 4-bits new priority 4 current priority 4 processor 0 current priority register processor 0 priority lifo pop 1 lowest vector interrupt request 1 vector table entry size pushed priority 4 popped priority 4 interrupt acknowledge 1 the total number of in terrupt sources is 256. priority select registers
interrupt controller (intc) freescale semiconductor 28-3 pxs20 microcontroller reference manual, rev. 1 28.2 modes of operation 28.2.1 normal mode in normal mode, the intc has two handshaking modes with the processor: software vector mode and hardware vector mode. 28.2.1.1 software vector mode in software vector mode, so ftware, that is the interrupt exception handler, must read a register in the intc to obtain the vector associated with the interrupt request to the proc essor. the intc will use software vector mode for a given processor when its asso ciated intc_bcr[hven_prc0] bit is cleared. the hardware vector enable si gnal to the processor is dr iven as negated when its associated hven_prc0 bit is negated. the vector is read from the intc _iackr_prc0 register. read ing the intc_iackr_prc0 negates the interrupt request to the as sociated processor. even if a highe r priority interrupt request arrived while waiting for this interrupt acknowl edge, the interrupt request to the pr ocessor will negate for at least one clock. the reading also pushes th e pri value in the intc_cpr regist er onto the associated lifo and updates pri in the associated intc _cpr_prc0 with the new priority. furthermore, the interrupt vector to the processor is driven as all ?0?s. the interrupt acknowledge signal from the associated processor is ignored. 28.2.1.2 hardware vector mode in hardware vector mode, the hardwa re is the interrupt vector signal from the intc in conjunction with a processor with the capability to use that vector. in ha rdware vector mode, this hardware causes the first instruction to be executed in handling the interrupt re quest to the processor to be specific to that vector. therefore the interrupt exception handler is specific to a peripheral or software se ttable interrupt request rather than being common to all of them. the intc will use hardware vector mode for a given processor when its associated hven_prc0 bit in the intc_bcr is asserted. the ha rdware vector enable signal to the associated processor is driven as asserted. when the interrupt request to the associated processor asserts, the interrupt vector signal is updated. the va lue of that interrupt vector is the unique vector associated with the preempting periphe ral or software settable interrupt request. the vect or value matches the value of the intvec_prc0 field in the intc_iackr_prc0. the processor negates the interrupt request to the pr ocessor driven by the intc by asserting the interrupt acknowledge signal for one cloc k. even if a higher priority interrupt request arrived while waiting for this interrupt acknowledge, the interrupt request to the processor will negate for at least one clock. the assertion of the interrupt acknowledge signal for a given processor pushes the associated pri value in the associated intc_cpr_prc0 regist er onto the associated lifo and updates the associated pri in the associated intc_cpr_prc0 register with the new priority. this pushing of the pri value onto the associated lifo and updati ng pri in the associated intc_cpr_prc0 does not occur when the associated interrupt acknowledge signal asserts a nd the intc_sscir register is writ ten at a time such that the pri value in the associated intc_cpr_prc0 register woul d need to be pushed and th e previously last pushed pri value would need to be popped simultaneously. in this case, pri in the associated intc_cpr_prc0 is updated with the new priority, and the as sociated lifo is neither pushed or popped.
interrupt controller (intc) 28-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 28.2.2 debug mode the intc operation in debug mode is iden tical to its operation in normal mode. 28.2.3 stop mode the intc supports the stop mode mechanism. the intc can have it s clock input disabl ed at any time by the clock driver on the soc. while its clocks ar e disabled, the intc regi sters are not accessible. some soc applications require that any peripheral interrupt request source be able to awaken a portion or all of the soc from stop mode. since the intc requires clocking in orde r for a peripheral interrupt request to generate an interrupt request to the processor, it does not support that requireme nt if it is not clocked. 28.2.4 factory test mode all intc registers are accessi ble in factory test mode. 28.3 external signal description the intc has no external mcu signals. 28.4 memory map/register definition 28.4.1 memory map table 28-1 is the intc memory map. table 28-1. intc memory map offset from intc_base register access 1 reset value 2 location 0x0000 intc block configuration re gister (intc_bcr) r/w 0x0000_0000 on page 28-6 0x0004 reserved 0x0008 intc current priority register for processor 0 (intc_cpr_prc0) r/w 0x0000_000f on page 28-7 0x000c reserved 0x0010 intc interrupt acknowledge register for processor 0 (intc_iackr_prc0) r/w 0x0000_0000 on page 28-8 0x0014 reserved 0x0018 intc end of interrupt register for processor 0 (intc_eoir_prc0) r 0x0000_0000 on page 28-9 0x001c reserved 0x0020 intc software set/clear interrupt register 0 - 3 (intc_sscir0_3) r/w 0x0000_0000 on page 28-9
interrupt controller (intc) freescale semiconductor 28-5 pxs20 microcontroller reference manual, rev. 1 28.4.2 register information with exception of the intc_sscirn and intc_psrn, all registers are 32 bits in width. any combination of accessing the four bytes of a register with a si ngle access is supported, provi ded that the access does not cross a register boundary. these supported accesses incl ude types and sizes of 8 bits, aligned 16 bits, misaligned 16 bits to the middl e 2 bytes, and aligned 32 bits. although intc_sscirn and intc_psrn are 8 bits wide, they can be accessed with a single 16-bit or 32-bit access, provided th at the access does not cross a 32-bit boundary. in software vector mode, the side effects of a read of intc_iackr_prc 0 are the same regardless of the size of the read. in either software or hardware vector mode, the size of a write to intc_sscir n or intc_eoir_prc0 does not affect on the operation of the write. 0x0024 intc software set/clear interrupt register 4 - 7 (intc_sscir4_7) r/w 0x0000_0000 on page 28-9 0x0028?0x003c reserved 0x0040?0x013c intc priority select register 0 - 3 (intc_psr0_3) - intc priority select register 252 - 255 (intc_psr252_255) 3 r/w 0x0000_0000 on page 28-11 0x0140?0x3fff reserved notes: 1 in this column, r/w = read/write, r = read-only, and w = write-only. 2 in this column, the symbol ?u? indicates one or more bits in a byte are undefined at reset. see the associated description for more information. 3 the pri fields are 'reserved' for peripheral interrup t requests whose vectors are labeled as not used in table 28-4 . table 28-1. intc memory map (continued) offset from intc_base register access 1 reset value 2 location
interrupt controller (intc) 28-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 28.4.3 intc block configur ation register (intc_bcr) figure 28-2. intc block configuration register (intc_bcr) the block configuration register is us ed to configure options of the intc. vtes_prc0 ? vector table entry size the vtes_prc0 bit controls the number of ?0?s to the right of intc_iackr_prc0[intvec_prc0] in. if the cont ents of intc_iackr_prc0 are used as an address of an entry in a vector table, then the num ber of rightmost ?0?s will determine the size of each vector table entry. see section 28.6.3, code compression?s impact on vector table, for a use of the vtes_prc0 bit. 1 = 8 bytes 0 = 4 bytes hven_prc0 ? hardware vector enable the hven bit controls whether the intc is in hardware vector mode or software vector mode. refer to section 28.2.1, normal mode, for the details of the handshaking with the processor in each mode. 1 = hardware vector mode 0 = software vector mode intc_base 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 vte s_p rc0 0 0 0 0 hve n_p rc0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved
interrupt controller (intc) freescale semiconductor 28-7 pxs20 microcontroller reference manual, rev. 1 28.4.4 intc current priority regist er for processor 0 (intc_cpr_prc0) figure 28-3. intc current priority register for processor 0 (intc_cpr_prc0) the current priority register masks any peripheral or softwa re settable interrupt re quest at the same or lower priority of the current value of the pri fi eld in intc_cpr_prc0 from generating an interrupt request to processor 0. when intc_iackr_prc0 is re ad in software vector mode, or the interrupt acknowledge signal from the processor is asserted in hardware vector mode, the value of pri is pushed onto the lifo, and pri is updated with the prio rity of the preempting interrupt request. when intc_eoir_prc0 is written, the lifo is popped in to the intc_cpr_prc0?s pri field. an exception case in hardware vector mode to this behavior is described in section 28.2.1.2, hardwa re vector mode. the masking priority can be raised or lowered by wr iting to the pri field, supporting the pcp. refer to section 28.6.6, priority ceiling protocol . note depending on an soc implementation?s pipelining capabilities and bus architecture, a store to modify the pri field which closely precedes or follows an access to a shared resource can result in a non-coherent access to that resource. refer to section 28.6.6.2, ensuring coherency, for example code to ensure coherency. pri[0:3] ? priority. pri is the priority of the currently executing isr according to the field values defined in table 28-2 . intc_base+0x8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 pri w reset: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 = unimplemented or reserved table 28-2. pri values pri meaning 1111 priority 15 - highest priority 1110 priority 14 1101 priority 13 1100 priority 12 1011 priority 11 1010 priority 10 1001 priority 9 1000 priority 8
interrupt controller (intc) 28-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 28.4.5 intc interrupt acknowle dge register for processor 0 (intc_iackr_prc0) figure 28-4. intc inte rrupt acknowledge register fo r processor 0 (intc_iackr_prc0) the interrupt acknowledge register for processor 0 provides a value wh ich can be used to load the address of an isr from a vector table. the vector table can be composed of addresses of the isrs specific to their respective interrupt vectors. also, in software vector mode, the intc_iackr_prc0 has side effects from read s. therefore, it must not be read speculatively while in this mode. the side effects are the same regardless of the size of the read. reading the intc_iackr_prc0 does not have side effects in hardware vector mode. vtba_prc0[0:20] ? vector table base address for processor 0. vtba_prc0 can be the base address of a vector table of addresses of isrs for processor 0. the vtba_prc0 only uses the leftmost 20 bits when the vtes_prc0 bit in intc_bcr is asserted. intvec_prc0[0:8] ? interrupt vector for processor 0. 0111 priority 7 0110 priority 6 0101 priority 5 0100 priority 4 0011 priority 3 0010 priority 2 0001 priority 1 0000 priority 0 - lowest priority intc_base+0x10 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r vtba_prc0 (most significant 16 bits) w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 1 notes: 1 when the intc_bcr[vtes_prc0] bit is set, intvec_prc0 is sh ifted to the left one bit. bit 29 is read as a ?0?. vtba_prc0 is narrowed to 20 bits in width. 21 22 23 24 25 26 27 28 29 1 30 31 r vtba_prc0 (least significant 5 bits) intvec_prc0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 28-2. pri values (continued) pri meaning
interrupt controller (intc) freescale semiconductor 28-9 pxs20 microcontroller reference manual, rev. 1 intvec_prc0 is the vector of the peripheral or software settable interrupt request that caused the interrupt request to the processor. when the in terrupt request to the processor asserts, the intvec_prc0 is updated, whether the intc is in software or hardware vector mode. 28.4.6 intc end of interrupt regist er for processor 0 (intc_eoir_prc0) figure 28-5. intc end of interrupt register for processor 0 (intc_eoir_prc0) writing to the end of interrupt register signals the e nd of the servicing of the interrupt request. when the intc_eoir_prc0 is written, the priority last pus hed on the lifo is popped into intc_cpr_prc0. an exception case in hardware vector mode to this be havior is described in section 28.2.1.2, hardware vector mode. the values and size of data writ ten to the intc_eoir_prc0 are ignor ed. those values and sizes written to this register neither update the intc_eoir_prc0 contents or affect whether the lifo pops. for possible future compatibility, write four bytes of all ?0?s to the intc_eoir_prc0. 28.4.7 intc software set/clear inte rrupt registers (intc_sscir0_3 - intc_sscir4_7) figure 28-6. intc software set/clear interrupt register 0 - 3 (intc_sscir0_3) intc_base+0x18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w see text reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w see text reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 intc_base+0x20 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 clr0 0 0 0 0 0 0 0 clr1 w set0 set1 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 clr2 0 0 0 0 0 0 0 clr3 w set2 set3 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved
interrupt controller (intc) 28-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 28-7. intc software set/clear interrupt register 4 - 7 (intc_sscir4_7) the software set/clear interrupt registers support the setting or clearing of soft ware settable interrupt request. these registers cont ain eight independent sets of bits to set and clea r a corresponding flag bit by software. with the exception of being set by software, this flag bit behaves the same as a flag bit set within a peripheral. this flag bit generates an interrupt reque st within the intc just like a peripheral interrupt request. writing a ?1? to set x will leave set x unchanged at ?0? but will set clr x . writing a ?0? to set x will have no effect. clr x is the flag bit. writing a ?1? to clr x will clear it. writing a ?0? to clr x will have no effect. if a ?1? is written to a pair set x and clr x bits at the same time, clr x will be asserted, regardless of whether clr x was asserted before the write. set0 - set7 ? set flag bits writing a ?1? will se t the corresponding clr x bit. writing a ?0? will have no effect. each set x always will be read as a ?0?. clr0 - clr7 ? clear flag bits clr x is the flag bit. writing a ?1? to clr x will clear it provide d that a ?1? is not written simultaneously to its corresponding set x bit. writing a ?0? to clr x will have no effect. 1 = interrupt request pending within intc. 0 = interrupt request not pending within intc. intc_base+0x24 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 clr4 0 0 0 0 0 0 0 clr5 w set4 set5 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 clr6 0 0 0 0 0 0 0 clr7 w set6 set7 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved
interrupt controller (intc) freescale semiconductor 28-11 pxs20 microcontroller reference manual, rev. 1 28.4.8 intc priority select regist ers (intc_psr0_3 - intc_psr252_255) figure 28-8. intc priority select register 0 - 3 (intc_psr0_3) figure 28-9. intc priority select register 252 - 255 (intc_psr252_255) the priority select regist ers support the selection of an individual priority for each source of interrupt request. the unique vector of each peripheral or software settable in terrupt request determines which intc_psr x _ x is assigned to that interrupt request. the software settable interrupts requests 0 - 7 are assigned vectors 0 - 7, and thei r priorities are configured in intc_psr0_3 and intc_psr4_7, respectively. the peripheral inte rrupt requests are assigned vect ors 8?255, and their priorities are configured in intc_psr8_11 th rough intc_psr252_255, respectively. note the prix field of an intc_psrx_x must not be modified while its corresponding peripheral or software sett able interrupt request is asserted. pri0[0:3] - pri255[0:3] ? priority select. pri x selects the priority for the interrupt requests. refer to the field values in table 28-2 . intc_base+0x40 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pri0 0 0 0 0 pri1 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 pri2 0 0 0 0 pri3 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved intc_base+0x13c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pri252 0 0 0 0 pri253 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 pri254 0 0 0 0 pri255 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved
interrupt controller (intc) 28-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 28.5 functional description the functional description involves the areas of interrupt request s ources, priority management, and handshaking with the processor. in addition, spaces in the memory map have been reserved for other possible implementations of the intc. 28.5.1 interrupt request sources the intc has two types of interrupt requests, peripheral and software settable. these interrupt requests can assert on any clock cycle. the intc has no spurious vect or support. therefore, if an asserted pe ripheral or software settable interrupt request, whose prix va lue in the intc_psr n is higher than the pri valu e in intc_cpr_prc0, negates before the interrupt request to the processor for that peripheral or software settable interrupt request is acknowledged, the interrupt request to the processor still can assert or will remain asserted for that peripheral or software setta ble interrupt request. in th is case, the interrupt vector will correspond to that peripheral or software settable in terrupt request. also, the pri valu e in the intc_cpr_prc0 will be updated with the corresponding prix value in intc_psrx_x. furthermore, clearing the peripheral interrupt request?s en able bit in the peripheral or, alternatively, setting its mask bit has the same consequences as clearing its flag bit. setting its enable bit or clearing its mask bit while its flag bit is asserted ha s the same effect on the intc as an interrupt event setting the flag bit. 28.5.1.1 peripheral interrupt requests an interrupt event in a peripheral?s ha rdware sets a flag bit which resides in that pe ripheral. the interrupt request from the peripheral is driven by that flag bit. the time from when the peripheral starts to drive its peripheral interrupt request to the intc to the time that the intc starts to drive the interrupt request to the processor is three cycles. interrupt requests from devices extern al to the intc are classified as peripheral interrupt requests in this document. an anticipated way that the intc will support an external in terrupt request is by having a flag bit in a peripheral which records an external interrupt request. this flag bit then drives a peripheral interrupt request. it is the responsibility of the in terrupt handler to clear th is flag bit before the intc_eoir_prc0 can be written. 28.5.1.2 software settable interrupt requests an interrupt request is triggered by software by writing a ?1? to a set x bit in the intc_sscir n registers. this write sets the corresponding clr x bit, which is a flag bit, resu lting in the interrupt request. the interrupt request is cleared by writing a ?1? to the clr x bit. the time from the write to the set x bit to the time that th e intc starts to drive th e interrupt request to the processor is four clocks.
interrupt controller (intc) freescale semiconductor 28-13 pxs20 microcontroller reference manual, rev. 1 28.5.1.3 unique vector for each interrupt request source each peripheral and software sett able interrupt request is assigne d a hardwired unique 9-bit vector. software settable interrupts 0 - 7 are assigned vectors 0 - 7 respectively. th e peripheral inte rrupt requests are assigned vectors 8 to as high as needed to cover all of th e peripheral inte rrupt requests. 28.5.2 priority management the asserted interrupt reque sts are compared to each other based on their pri x values set in intc_psr n . the result of that comparison also is compared to pri in the associated intc_cpr_prc0 register. the results of those comparisons are used to manage the priority of the isr being executed by the associated processor. the associated lifo also assists in managing that priority. 28.5.2.1 current prio rity and preemption the priority arbitrator, selector, encode r, and comparator subblocks shown in figure 28-1 are used to compare the priority of the asserted interrupt requests to the current priority. if th e priority of any asserted peripheral or software setta ble interrupt request is higher than the current priority for a given processor, then the interrupt request to the pr ocessor is asserted. also, a unique vector for the preempting peripheral or software settable interrupt reque st is generated for the associated intc_iackr_prc0 register, and if in hardware vector mode, for the inte rrupt vector provided to the processor. 28.5.2.1.1 priority ar bitrator subblock the priority arbitrator subblock for e ach processor compares all the prioriti es of all of the asserted interrupt requests assigned to that processor, both peripheral and software settable. the output of the priority arbitrator subblock is the highest of those priorities assigned to a gi ven processor. also, any interrupt requests which have this highest priority are output as asserted interrupt requests to the associated request selector subblock. 28.5.2.1.2 request selector subblock if only one interrupt request from the associated priority arbitrator subbloc k is asserted, then it is passed as asserted to the associ ated vector encoder subbloc k. if multiple interrupt re quests from the associated priority arbitrator s ubblock are asserted, then only the one with th e lowest vector is passed as asserted to the associated vector encoder subblock. the lower vect or is chosen regardless of the time order of the assertions of the peripheral or so ftware settable in terrupt requests. 28.5.2.1.3 vector encoder subblock the vector encoder subblock generate s the unique 9-bit vector for the as serted interrupt request from the request selector subblock fo r the associated processor. 28.5.2.1.4 priority co mparator subblock the priority comparator subblock co mpares the highest priority output from the associated priority arbitrator subblock with pri in the associated intc_cpr_prc0. if the priority comparator subblock detects that this highest priority is higher than the cu rrent priority, then it asserts the interrupt request to
interrupt controller (intc) 28-14 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 the associated processor. this interrupt request to th e processor asserts whether this highest priority is raised above the value of pri in the associated intc_cpr_prc0, or the pri value in the associated intc_cpr_prc0 is lowered below this highest priori ty. this highest priority then becomes the new priority which will be written to pri in the associ ated intc_cpr_prc0 when th e interrupt request to the processor is acknowledged. in terrupt requests whose pri x in intc_psr x _ x are zero will not cause a preemption because their pri x will not be higher than pri in the associated intc_cpr_prc0. 28.5.2.2 lifo the lifo stores the preempted pr i values from the associated in tc_cpr_prc0. therefore, because these priorities are stacked within the intc, if in terrupts need to be enabled during the isr, at the beginning of the interrupt exception handler the pri value in the associated intc_cpr_prc0 does not need to be loaded from the associated intc_cpr_p rc0 and stored onto the c ontext stack. likewise at the end of the interrupt exception handler, the priority does not need to be loaded from the context stack and stored into the associated intc_cpr_prc0. the pri value in the associated intc_cpr_prc0 is pushed onto the lifo when the associated intc_iackr_prc0 is read in soft ware vector mode or the inte rrupt acknowledge signal from the associated processor is asse rted in hardware vector mode. the priori ty is popped into pri in the associated intc_cpr_prc0 whenever the associated intc_e oir_prc0 is written. an exception case in hardware vector mode to this behavior is described in section 28.2.1.2, hardware vector mode . although the intc supports 16 prior ities, an isr executing with pri in the intc_cpr_prc0 equal to 15 will not be preempted. th erefore, the lifo supports the stacking of 15 priori ties. however, the lifo is only 14 entries deep. an entry for a priority of 0 is not needed because of how pushing onto a full lifo and popping an empty lifo are treate d. if the lifo is pushed 15 or mo re times than it is popped, the priorities first pushed are ove rwritten. a priority of 0 would be an overwritten priority. however, the lifo will pop ?0?s if it is popped more times than it is pushed. therefore, although a priority of 0 was overwritten, it is regenerated with the popping of an empty lifo. the lifo is not memory-mapped. 28.5.3 handshaking with processor 28.5.3.1 software vector mode handshaking 28.5.3.1.1 acknowledging interrupt request to processor a timing diagram of the interrupt request and acknow ledge handshaking in software vector mode, along with the handshaking near th e end of the interrupt exce ption handler, is shown in figure 28-10 . the intc examines the peripheral and software settable interrupt requests. when it finds an asserted peripheral or software settable interrupt re quest with a higher priority than pri in the associated section 28.4.4, intc current priority register for processor 0 (intc_cpr_prc0) , it asserts the interrupt request to the associated processor. the intvec field in the associated section 28.4.5, intc interrupt acknowledge register for processor 0 (intc_iackr_prc0) is updated with the preempti ng interrupt request?s vector when the interrupt request to the pr ocessor is asserted. the intvec fiel d retains that valu e until the next
interrupt controller (intc) freescale semiconductor 28-15 pxs20 microcontroller reference manual, rev. 1 time the interrupt request to the processor is asse rted. the rest of the handshaking is described in section 28.2.1.1, software vector mode . 28.5.3.1.2 end of inte rrupt exception handler before the interrupt exception handling completes, section 28.4.6, intc end of interrupt register for processor 0 (intc_eoir_prc0) , must be written. when it is writte n, the associated lifo is popped so that the preempted priority is rest ored into pri of the associated intc_cpr_prc0. before it is written, the peripheral or software settable flag bit must be cleared so that the peripheral or software settable interrupt request is negated. note a store to clear the peripheral or soft ware settable interrupt flag bit which closely precedes the store to the in tc_eoir_prc0 can result in that peripheral or software settable interru pt request being serviced again. to prevent this, execute a power arch itecture isync, msync, or mbar instruction before the store to the intc_eoir_prc0 as shown in section 28.6.2.1, software vector mode . when returning from the preemption, the intc does not search for the periphe ral or software settable interrupt request whose isr was pr eempted. depending on how much the isr progressed, that interrupt request may no longer even be asserted. when pri in the associated intc_cpr _prc0 is lowered to the priority of the preempted isr, the interrupt request for the preempt ed isr or any other asserted peripheral or software settable interrupt request at or below th at priority will not cause a preemption. instead, after the restoration of the preempted contex t, the processor will return to the instruction address that it was to next execute before it was preempted. this next instru ction is part of the preempted isr or the interrupt exception handler?s prolog or epilog.
interrupt controller (intc) 28-16 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 28-10. software vector mode handshaking timing diagram 28.5.3.2 hardware vector mode handshaking a timing diagram of the in terrupt request and acknow ledge handshaking in hard ware vector mode, along with the handshaking near the end of the interrupt exception handler, is shown in figure 28-11 . as in software vector mode, the intc ex amines the peripheral and software settable interrupt requests, and when it finds an asserted one with a higher priority than pri in the associated intc_cpr_prc0, it asserts the interrupt request to the associated proc essor. the intvec field in the associated intc_iackr_prc0 is updated with th e preempting peripheral or software settable interrupt request?s vector when the interrupt request to the processor is asserted. th e intvec field retains that value until the next time the interrupt request to the associated processor is asserted. in addition, the value of the interrupt vector to the associated processor matches the value of th e intvec field in the associated intc_iackr_prc0. the rest of th e handshaking is described in section 28.2.1.2, hardware vector mode . the handshaking near the end of the interrupt excepti on handler, that is the writing to the associated intc_eoir_prc0, is the same as in software vector mode. refer to section 28.5.3.1.2, end of interrupt exception handler . 0 1 0 clock interrupt request to processor hardware vector enable interrupt vector interrupt acknowledge read intc_iackr_prc x write intc_eoir_prc x intvec in intc_iackr_prc x pri in intc_cpr_prc x peripheral interrupt request 100 0 108 0
interrupt controller (intc) freescale semiconductor 28-17 pxs20 microcontroller reference manual, rev. 1 figure 28-11. hardware vector mode handshaking timing diagram 28.6 initialization/application information 28.6.1 initialization flow after exiting reset, all of the pri x and prc_sel x fields in section 28.4.8, intc priority select registers (intc_psr0_3 - intc_psr252_255) , will be zero, and pri in both section 28.4.4, intc current priority register for pr ocessor 0 (intc_cpr_prc0) , will be 15. these reset valu es will prevent the intc from asserting the interrupt request to the processors. fu rthermore, the indigo-li ne section of the ipi specification states that the periphera ls must have a bit to enable or mask peripheral interrupt request signals. an initialization sequence fo r allowing the peri pheral and software settab le interrupt requests to cause an interrupt request to the processor is: interrupt_request_initialization: configure vtes_prc0 and hven_prc0 in intc_bcr configure vtba_prc0 in intc_iackr_prc0 raise the pri x fields to the desired processor in intc_psr x _ x set the enable bits or clear the mask bits for the peripheral interrupt requests lower pri in intc_cpr_prc0 to zero enable processor recognition of interrupts 28.6.2 interrupt exception handler these example interrupt exception handlers use power architecture assembly code. 0 108 0 1 0 clock interrupt request to processor hardware vector enable interrupt vector interrupt acknowledge read intc_iackr_prc x write intc_eoir_prc x intvec in intc_iackr_prc x pri in intc_cpr_prc x peripheral interrupt request 100 0 108
interrupt controller (intc) 28-18 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 28.6.2.1 software vector mode interrupt_exception_handler: code to save srr0 and srr1 lis r3,hi(intc_iackr_prc0) # form intc_iackr_prc0 address ori r3,r3,lo(intc_iackr_prc0) lwz r3,0x0(r3) # load intc_iackr_prc0, which clears request to processor lwz r3,0x0(r3) # load address of isr from vector table code to enable processor recognition of interrupts and save context required by eabi mtlr r3 # move intc_iackr_prc0 contents into link register blrl # branch to isr; link register updated with epilog # address epilog: lis r3,hi(intc_eoir_prc0) # form intc_eoir_prc0 address ori r3,r3,lo(intc_eoir_prc0) li r4,0x0 # form 0 to write to intc_eoir_prc0 stw r4,0x0(r3) # store to intc_eoir_prc0, informing intc to lower priority code to restore context required by eabi and disable processor recognition of interrupts code to restore srr0 and srr1 rfi vector_table_base_address: address of isr for interrupt with vector 0 address of isr for interrupt with vector 1 . . . address of isr for interrupt with vector 510 address of isr for interrupt with vector 511 isr x : code to service the interrupt event code to clear flag bit which drives interrupt request to intc blr # return to epilog 28.6.2.2 hardware vector mode this interrupt exception handler is useful with processor and system bus implementations which support a hardware vector. this example assumes that each interrupt_exception_handler x only has space for four instructions, and therefore a branch to interrupt_exception_handler_continued x is needed. interrupt_exception_handler x : b interrupt_exception_handler_continued x # 4 instructions available, branch to continue interrupt_exception_handler_continued x : code to save srr0 and srr1 code to enable processor recognition of interrupts and save context required by eabi
interrupt controller (intc) freescale semiconductor 28-19 pxs20 microcontroller reference manual, rev. 1 bl isr x # branch to isr for interrupt with vector x epilog: lis r3,hi(intc_eoir_prc0) # form intc_eoir_prc0 address ori r3,r3,lo(intc_eoir_prc0) li r4,0x0 # form 0 to write to intc_eoir_prc0 stw r4,0x0(r3) # store to intc_eoir_prc0, informing intc to lower priority code to restore context required by eabi and disable processor recognition of interrupts code to restore srr0 and srr1 rfi isr x : code to service the interrupt event code to clear flag bit which drives interrupt request to intc blr # branch to epilog 28.6.3 code compression?s impact on vector table the entries in the vector table in th e interrupt exception handler example in section 28.6.2.1, software vector mode , are addresses of isrs. a vector table also can be written whose entries are branches to isrs. the instruction flow branches to the entry in the v ector table corresponding to th e vector of the peripheral or software settable interrupt request, and then th e instruction flow branches to the corresponding isr. while a vector table of addr esses of isrs is not affe cted by code compression, a vector table of branches to isrs can be affected. code co mpression techniques can produce for some cases instructions that are wider than 32 bits but less than 64 bi ts. if the vector table is compress ed and some instructions are wider than 32 bits, the vtes_prc0 bit in section 28.4.3, intc block config uration register (intc_bcr) , can be set. each entry in the ve ctor table then can occupy 64 bits. 28.6.4 isr, rtos, and task hierarchy the rtos and all of the ta sks under its control typical ly execute with pri in section 28.4.4, intc current priority register for processor 0 (intc_cpr_prc0) , having a value of 0. the rtos will execute the tasks according to whatever priority scheme that it may have, but that priority scheme is independent and has a lower priority of execution than the priority sc heme of the intc. in other words, the isrs execute above intc_cpr_prc0 priority 0 and outside the control of the rtos, the rtos executes at intc_cpr_prc0 priority 0, and while the tasks execut e at different priorities under the control of the rtos, they also execute at intc_cpr_prc0 priority 0. if a task shares a resource with an isr and the pcp is being used to mana ge that shared resource, then the task?s priority can be elevated in the intc_cpr _prc0 while the shared resource is being accessed. an isr whose pri x in section 28.4.8, intc priority se lect registers (intc_psr0_3 - intc_psr252_255) , has a value of 0 will not caus e an interrupt request to the selected processor, even if its peripheral or software settable interrupt request is asserted. fo r a peripheral inte rrupt request, not
interrupt controller (intc) 28-20 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 setting its enable bit or disabling th e mask bit will cause it to remain negated, which consequently also will not cause an interrupt request to the processor. since the isrs are outsid e the control of the rtos, this isr will not run unless called by another isr or the in terrupt exception handler, perhaps after executing another isr. 28.6.5 order of execution an isr with a higher priority can pr eempt an isr with a lower priority , regardless of the unique vectors associated with each of their peri pheral or software settable interrupt requests. however, if multiple peripheral or software sett able interrupt requests are asserted, more than one has the hi ghest priority, and that priority is high enough to ca use preemption, the intc selects the one with the lowest unique vector regardless of the order in time that they asserte d. however, the ability to meet deadlines with this scheduling scheme is no less than if the isrs execute in the time order that their peripheral or software settable interrupt requests asserted. the example in table 28-3 shows the order of execution of both isrs with differen t priorities and the same priority.
interrupt controller (intc) freescale semiconductor 28-21 pxs20 microcontroller reference manual, rev. 1 28.6.6 priority ceiling protocol 28.6.6.1 elevating priority the pri field in section 28.4.4, intc current priority regi ster for processor 0 (intc_cpr_prc0) , is elevated in the osek pcp to the ceil ing of all of the priorities of th e isrs that share a resource. this protocol therefore allows coherent accesse s of the isrs to that shared resource. table 28-3. order of isr execution example code executing at end of step step # step description rtos isr108 1 isr208 isr308 isr408 interrupt exception handler pri in intc_cpr at end of step 1 rtos at priority 0 is executing. x0 2 peripheral interrupt request 100 at priority 1 asserts. interrupt taken. x1 3 peripheral interrupt request 400 at priority 4 is asserts. interrupt taken. x4 4 peripheral interrupt request 300 at priority 3 is asserts. x4 5 peripheral interrupt request 200 at priority 3 is asserts. x4 6 isr408 completes. interrupt exception handler writes to intc_eoir_prc0. x1 7 interrupt taken. isr208 starts to execute, even though peripheral interrupt request 300 asserted first. x3 8 isr208 completes. interrupt exception handler writes to intc_eoir_prc0. x1 9 interrupt taken. isr308 starts to execute. x3 10 isr308 completes. interrupt exception handler writes to intc_eoir_prc0. x1 11 isr108 completes. interrupt exception handler writes to intc_eoir_prc0. x0 12 rtos continues execution. x 0 notes: 1 isr108 executes for peripheral interrupt request 100 because the first eight isrs are for software settable interrupt requests.
interrupt controller (intc) 28-22 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 for example, isr1 has a priority of 1, isr2 has a priority of 2, and isr3 has a priority of 3. they all share the same resource. before isr1 or isr2 can access that resource, they must raise the pri value in intc_cpr_prc x to 3, the ceiling of all of th e isr priorities. after they release the resource, they must lower the pri value in intc_cpr_prc x to prevent further priority inversion. if they do not raise their priority, then isr2 can preempt isr1, and isr3 can preempt isr1 or isr2, possi bly corrupting the shared resource. another possible failure mechanism is deadlock if the higher priority isr needs the lower priority isr to release the resource before it can continue, but the lo wer priority isr can not release the resource until the higher priority isr completes a nd execution returns to the lower priority isr. using the pcp instead of disabling processor recognition of all interrupt s reduces the priority inversion time when accessing a shared resource. for example, while isr3 can not preempt isr1 while it is accessing the shared resource, all of the isrs w ith a priority higher than 3 can preempt isr1. 28.6.6.2 ensuring coherency a scenario can exist on some soc implementations th at can cause non-coherent accesses to the shared resource. as an example, isr1 and isr2 both share a resource. isr1 has a lower priority than isr2. isr1 is executing, and it writes to the intc_cpr_prc0. th e instruction following this store is a store to a value in a shared coherent data block. either just befo re or at the same time as the first store, the intc asserts the interrupt request to the processor because the peripheral interr upt request for isr2 has asserted. as the processor is responding to the interrupt request from the intc, and as it is aborting transactions and flushing its pipeline, it is possible in some soc implementations that both of these stores will be executed. isr2 thereby thinks that it can access the data block coherently, but the data block has been corrupted. osek uses the getresource and rele aseresource system services to mana ge access to a shared resource. to prevent this corruption of a coherent data bl ock, modifications to pri in intc_cpr_prc0 can be made by those system servi ces with the code sequence: disable processor recognition of interrupts pri modification enable processor recognition of interrupts 28.6.7 selecting priorities accordin g to request rates and deadlines the selection of the priorities for th e isrs can be made using rate m onotonic scheduling or a superset of it, deadline monotonic scheduling. in rms, the isrs which have higher request rates have higher priorities. in dms, if the deadline is before the next time the isr is requested, then the isr is assigned a priority according to the time from th e request for the isr to the deadline , not from the time of the request for the isr to the next request for it. for example, isr1 executes every 100 ? s, isr2 executes every 200 ? s, and isr3 executes every 300 ? s. isr1 has a higher priority than isr2 which has a hi gher priority than isr3. however, if isr3 has a deadline of 150 ? s, then it has a higher priority than isr2. the intc has 16 priorities, which could be much less than the number of isrs. in this case, the isrs should be grouped with other isrs that have similar deadlines. for exampl e, a priority could be allocated for every time the request rate doubles. isrs with re quest rates around 1 ms woul d share a priority, isrs with request rates around 500 ? s would share a priority, isrs with request rates around 250 ? s would share
interrupt controller (intc) freescale semiconductor 28-23 pxs20 microcontroller reference manual, rev. 1 a priority, etc. with this approac h, a range of isr request rates of 2 16 could be covered, regardless of the number of isrs. reducing the number of priorities does cause some prio rity inversion which reduces the processor?s ability to meet its deadlines. ho wever, reducing the number of priorities can reduce the size and latency through the interrupt controller. it also allows easier mana gement of isrs with similar deadlines that share a resource. they can be placed at the same priority wi thout any further priority inversion, and they do not need to use the pcp to access the shared resource. 28.6.8 software settab le interrupt requests the software settable interrupt reque sts can be used in two ways. they can be used to schedule a lower priority portion of an isr and for processors to interr upt other processors in a multiple processor system. 28.6.8.1 scheduling a lower priority portion of an isr a portion of an isr needs to be executed at the pri x value in section 28.4.8, intc priority select registers (intc_psr0_3 - intc_psr252_255) ,, which becomes the pri value in either section 28.4.4, intc current priority register for processor 0 (intc_cpr_prc0) , with the interrupt acknowledge. the isr, however, can have a portion of it which does not need to be executed at this higher priority. therefore, executing this later portion which does not need to be executed at this higher priority can block the execution of isrs which do not have a higher priority than the earlier portion of the isr but do have a higher priority than what the later portion of the isr needs. this priority inversion reduces the processor?s ability to meet its deadlines. one option is for the isr to complete the earlier higher priority portion, but then schedule through the rtos a task to execute the later lower priority por tion. however, some rtoss can require a large amount of time for an isr to schedule a task. therefore, a second option is fo r the isr, after co mpleting the higher priority portion, to set a set x bit in section 28.4.7, intc software se t/clear interrupt registers (intc_sscir0_3 - intc_sscir4_7) . writing a ?1? to set x causes a software sett able interrupt request. this software settable interrupt request , which usually will have a lower pri x value in the intc_psr x _ x , therefore will not cause priority inversion. 28.6.8.2 scheduling an is r on another processor since the set x bits in the intc_sscir x _ x are memory mapped, processo rs in multiple processor systems can schedule isrs on the othe r processors. one applic ation is that one proc essor simply wants to command another processor to perfor m a piece of work, and the initiati ng processor does not need to use the results of that work. if the in itiating processor is concerned that processor executing the software settable isr has not completed the work before asking it to again execute that isr, it can check if the corresponding clr x bit in intc_sscir x _ x is asserted before again writing a ?1? to the set x bit. another application is the sharing of a block of data. for example, a first processor has completed accessing a block of data and wants a second processo r to then access it. furt hermore, after the second processor has completed accessing th e block of data, the first proce ssor again wants to access it. the accesses to the block of data must be done coherently. the pro cedure is that the first processor writes a ?1? to a set x bit on the second processor. the second processor, afte r accessing the block of data, clears the
interrupt controller (intc) 28-24 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 corresponding clr x bit and then writes ?1? to a set x bit on the first processor, informing it that it now can access the block of data. 28.6.9 lowering priori ty within an isr in soc implementations without the soft ware settable interrupt requests in section 28.4.7, intc software set/clear interrupt registers (intc_sscir0_3 - intc_sscir4_7) , the only other way besides scheduling a task through an rtos to not have priority inversion with an isr whose work spans multiple priorities as described in section 28.6.8.1, scheduling a lower pr iority portion of an isr , is to lower the current priority. however, the intc has a lifo whose depth is determ ined by the number of priorities. note lowering the pri value in either section 28.4.4, intc current priority register for processor 0 (intc_cpr_prc0) , within an isr to below the isr?s corresponding pri value in section 28.4.8, intc priority select registers (intc_p sr0_3 - intc_psr252_255) , allows more preemptions than the depth of the lifo can support. therefore, the intc does no t support lowering the current priority with in an isr as a way to avoid priority inversion. 28.6.10 negating an interrupt request outside of its isr 28.6.10.1 negating an interrupt requ est as a side effect of an isr some peripherals have flag bits wh ich can be cleared as a side effect of servicing a pe ripheral interrupt request. for example, reading a sp ecific register can clear the fl ag bits, and consequently their corresponding interrupt requests too. this clearing as a side effect of servic ing a peripheral interrupt request can cause the negation of other peripheral inte rrupt requests besi des the peripheral interrupt request whose isr presently is executing. this negating of a peripheral interrupt request outside of its isr can be a desired effect. 28.6.10.2 negating multiple in terrupt requests in one isr an isr can clear other flag bits besides its own flag bit. one reason that an isr clears multiple flag bits is because it serviced those other fl ag bits, and therefore the isrs for th ese other flag bits do not need to be executed. 28.6.10.3 proper setting of interrupt request priority whether an interrupt request negates outside of its own isr due to the si de effect of an isr execution or the intentional clearing a flag bit, th e priorities of the peripheral or soft ware settable interrupt requests for these other flag bits must be selected properly. their pri x values in section 28.4.8, intc priority select registers (intc_psr0_3 - intc_psr252_255) , must be selected to be at or lower than the priority of the isr that cleared their flag bits. otherwise, those flag bits still can cause the interrupt request to the processor to assert. furthermore, th e clearing of these other flag bits also has the same timing relationship
interrupt controller (intc) freescale semiconductor 28-25 pxs20 microcontroller reference manual, rev. 1 to the writing to section 28.4.7, intc software set/clear interrupt registers (intc_sscir0_3 - intc_sscir4_7) , as the clearing of the flag bit that cause d the present isr to be executed. refer to section 28.5.3.1.2, end of inte rrupt exception handler . a flag bit whose enable bit or mask bit is negating its peripheral interrupt reque st can be cleared at any time, regardless of the peripheral interrupt request?s pri x value in intc_psr x _ x . 28.6.11 examining lifo contents in normal mode, the user does not need to know the contents of the lifo. he may not even know how deeply the lifo is nested. however, if he should want to read the contents, such as in debug mode, they are not memory mapped. the contents still can be r ead by popping the lifo and reading the pri field in either section 28.4.4, intc current priority regi ster for processor 0 (intc_cpr_prc0) . the code sequence is: pop_lifo: store to intc_eoir_prc0 load intc_cpr_prc0, examine pri, and store onto stack if pri is not zero or value when interrupts were enabled, branch to pop_lifo when the examination is complete, the lifo can be restored using this code sequence: push_lifo: load stacked pri value and store to intc_cpr_prc x load intc_iackr_prc0 if stacked pri values are not depleted, branch to push_lifo 28.7 interrupt sources table 28-4 defines the interrupt sources for interrupt controll er intc_0 and intc_1. interrupts generated by on-platform peripherals are rout ed to their own interrupt contro ller only. interr upts generated by off-plaform peripherals are routed to both interrupt controllers. in decoupled parallel mode the interrupt load can be distributed to both cores by assigning different interrupt levels (interrupt level 0 to effectively disable an irq) to the same source at each interrupt controller. table 28-4. interrupt sources for intc_0 and intc_1 irq # offset size (bytes) source signal source module for intc_0 source module for intc_1 section b (on-platform peripherals) 0 0x0000 16 software setable flag 0 intc_0 (software) intc_1 (software) 1 0x0010 16 software setable flag 1 intc_0 (software) intc_1 (software) 2 0x0020 16 software setable flag 2 intc_0 (software) intc_1 (software) 3 0x0030 16 software setable flag 3 intc_0 (software) intc_1 (software) 4 0x0040 16 software setable flag 4 intc_0 (software) intc_1 (software) 5 0x0050 16 software setable flag 5 intc_0 (software) intc_1 (software) 6 0x0060 16 software setable flag 6 intc_0 (software) intc_1 (software)
interrupt controller (intc) 28-26 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 7 0x0070 16 software setable flag 7 intc_0 (software) intc_1 (software) 8 0x0080 16 not used 9 0x0090 16 platform flash bank 0 abort | platform flash bank 0 stall | platform flash bank 1 abort | platform flash bank 1 stall | platform flash bank 2 abort | platform flash bank 2 stall | platform flash bank 3 abort | platform flash bank 3 stall ecsm_0 ecsm_1 1 10 0x00a0 16 combined error dma_0 dma_1 11 0x00b0 16 channel 0 dma_0 dma_1 12 0x00c0 16 channel 1 dma_0 dma_1 13 0x00d0 16 channel 2 dma_0 dma_1 14 0x00e0 16 channel 3 dma_0 dma_1 15 0x00f0 16 channel 4 dma_0 dma_1 16 0x0100 16 channel 5 dma_0 dma_1 17 0x0110 16 channel 6 dma_0 dma_1 18 0x0120 16 channel 7 dma_0 dma_1 19 0x0130 16 channel 8 dma_0 dma_1 20 0x0140 16 channel 9 dma_0 dma_1 21 0x0150 16 channel 10 dma_0 dma_1 22 0x0160 16 channel 11 dma_0 dma_1 23 0x0170 16 channel 12 dma_0 dma_1 24 0x0180 16 channel 13 dma_0 dma_1 25 0x0190 16 channel 14 dma_0 dma_1 26 0x01a0 16 channel 15 dma_0 dma_1 27 0x01b0 16 reserved 28 0x01c0 16 swt timeout 2 swt_0 swt_0 29 0x01d0 16 swt timeout 2 swt_1 swt_1 30 0x01e0 16 match on channel 0 stm_0 stm_1 31 0x01f0 16 match on channel 1 stm_0 stm_1 32 0x0200 16 match on channel 2 stm_0 stm_1 33 0x0210 16 match on channel 3 stm_0 stm_1 34 0x0220 16 not used table 28-4. interrupt sources for intc_0 and intc_1 (continued) irq # offset size (bytes) source signal source module for intc_0 source module for intc_1
interrupt controller (intc) freescale semiconductor 28-27 pxs20 microcontroller reference manual, rev. 1 35 0x0230 16 ecc_platformflash_ noncorrectable error| ecc_dbd_platformram_ noncorrectable error ecsm_0 ecsm_1 1 36 0x0240 16 ecc_platformflash_1bit_correction| ecc_platformram_1bit_correction ecsm_0 ecsm_1 1 37 0x0250 16 not used not allocated not allocated section c (off-platform peripherals) 38 0x0260 16 not used 39 0x0270 16 not used 40 0x0280 16 not used 41 0x0290 16 siu external irq_0 siul 42 0x02a0 16 siu external irq_1 siul 43 0x02b0 16 siu external irq_2 siul 44 0x02c0 16 siu external irq_3 siul 45 0x02d0 16 not used 46 0x02e0 16 not used 47 0x02f0 16 not used 48 0x0300 16 not used 49 0x0310 16 not used 50 0x0320 16 not used 51 0x0330 16 safe mode interrupt mc_me mc_me 52 0x0340 16 mode transition interrupt mc_me mc_me 53 0x0350 16 invalid mode interrupt mc_me mc_me 54 0x0360 16 invalid mode config mc_me mc_me 55 0x0370 16 not used 56 0x0380 16 'functional' reset alternate event interrupt mc_rgm mc_rgm 57 0x0390 16 xosc counter expired xosc xosc 58 0x03a0 16 not used 59 0x03b0 16 pitimer channel 0 pit pit 60 0x03c0 16 pitimer channel 1 pit pit 61 0x03d0 16 pitimer channel 2 pit pit 62 0x03e0 16 adc_eoc adc_0 adc_0 63 0x03f0 16 adc_er adc_0 adc_0 64 0x0400 16 adc_wd adc_0 adc_0 table 28-4. interrupt sources for intc_0 and intc_1 (continued) irq # offset size (bytes) source signal source module for intc_0 source module for intc_1
interrupt controller (intc) 28-28 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 65 0x0410 16 flexcan_esr[err_int] flexcan_0 flexcan_0 66 0x0420 16 flexcan_esr_boff | flexcan_transmit_warning | flexcan_receive_warning flexcan_0 flexcan_0 67 0x0430 16 reserved reserved reserved 68 0x0440 16 flexcan_buf_00_03 flexcan_0 flexcan_0 69 0x0450 16 flexcan_buf_04_07 flexcan_0 flexcan_0 70 0x0460 16 flexcan_buf_08_11 flexcan_0 flexcan_0 71 0x0470 16 flexcan_buf_12_15 flexcan_0 flexcan_0 72 0x0480 16 flexcan_buf_16_31 flexcan_0 flexcan_0 73 0x0490 16 not used 74 0x04a0 16 dspi_sr[tfuf] | dspi_sr[rfof] dspi_0 dspi_0 75 0x04b0 16 dspi_sr[eoqf] dspi_0 dspi_0 76 0x04c0 16 dspi_sr[tfff] dspi_0 dspi_0 77 0x04d0 16 dspi_sr[tcf] dspi_0 dspi_0 78 0x04e0 16 dspi_sr[rfdf] dspi_0 dspi_0 79 0x04f0 16 linflex_rxi linflex_0 linflex_0 80 0x0500 16 linflex_txi linflex_0 linflex_0 81 0x0510 16 linflex_err linflex_0 linflex_0 82 0x0520 16 adc_eoc adc_1 adc_1 83 0x0530 16 adc_er adc_1 adc_1 84 0x0540 16 adc_wd adc_1 adc_1 85 0x0550 16 flexcan_esr[err_int] flexcan_1 flexcan_1 86 0x0560 16 flexcan_esr_boff | flexcan_transmit_warning | flexcan_receive_warning flexcan_1 flexcan_1 87 0x0570 16 reserved 88 0x0580 16 flexcan_buf_00_03 flexcan_1 flexcan_1 89 0x0590 16 flexcan_buf_04_07 flexcan_1 flexcan_1 90 0x05a0 16 flexcan_buf_08_11 flexcan_1 flexcan_1 91 0x05b0 16 flexcan_buf_12_15 flexcan_1 flexcan_1 92 0x05c0 16 flexcan_buf_16_31 flexcan_1 flexcan_1 93 0x05d0 16 not used 94 0x05e0 16 dspi_sr[tfuf] | dspi_sr[rfof] dspi_1 dspi_1 table 28-4. interrupt sources for intc_0 and intc_1 (continued) irq # offset size (bytes) source signal source module for intc_0 source module for intc_1
interrupt controller (intc) freescale semiconductor 28-29 pxs20 microcontroller reference manual, rev. 1 95 0x05f0 16 dspi_sr[eoqf] dspi_1 dspi_1 96 0x0600 16 dspi_sr[tfff] dspi_1 dspi_1 97 0x0610 16 dspi_sr[tcf] dspi_1 dspi_1 98 0x0620 16 dspi_sr[rfdf] dspi_1 dspi_1 99 0x0630 16 linflex_rxi linflex_1 linflex_1 100 0x0640 16 linflex_txi linflex_1 linflex_1 101 0x0650 16 linflex_err linflex_1 linflex_1 102 0x0660 16 not used 103 0x0670 16 not used 104 0x0680 16 not used 105 0x0690 16 not used 106 0x06a0 16 not used 107 0x06b0 16 not used 108 0x06c0 16 not used 109 0x06d0 16 not used 110 0x06e0 16 not used 111 0x06f0 16 not used 112 0x0700 16 not used 113 0x0710 16 not used 114 0x0720 16 dspi_sr[tfuf] | dspi_sr[rfof] dspi_2 dspi_2 115 0x0730 16 dspi_sr[eoqf] dspi_2 dspi_2 116 0x0740 16 dspi_sr[ tfff] dspi_2 dspi_2 117 0x0750 16 dspi_sr[tcf] dspi_2 dspi_2 118 0x0760 16 dspi_sr[rfdf] dspi_2 dspi_2 119 0x0770 16 not used 120 0x0780 16 not used 121 0x0790 16 not used 122 0x07a0 16 not used 123 0x07b0 16 not used 124 0x07c0 16 not used 125 0x07d0 16 not used 126 0x07e0 16 not used 127 0x07f0 16 pitimer channel 3 pit pit table 28-4. interrupt sources for intc_0 and intc_1 (continued) irq # offset size (bytes) source signal source module for intc_0 source module for intc_1
interrupt controller (intc) 28-30 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 128 0x0800 16 not used 129 0x0810 16 not used 130 0x0820 16 not used 131 0x0830 16 lrneif | drneif flexray flexray 132 0x0840 16 lrceif | drceif flexray flexray 133 0x0850 16 fafaif flexray flexray 134 0x0860 16 fafvif flexray flexray 135 0x0870 16 wupif flexray flexray 136 0x0880 16 prif flexray flexray 137 0x0890 16 chif flexray flexray 138 0x08a0 16 tbif flexray flexray 139 0x08b0 16 rbif flexray flexray 140 0x08c0 16 mif flexray flexray 141 0x08d0 16 reserved 142 0x08e0 16 reserved 143 0x08f0 16 reserved 144 0x0900 16 reserved 145 0x0910 16 reserved 146 0x0920 16 reserved 147 0x0930 16 reserved 148 0x0940 16 reserved 149 0x0950 16 reserved 150 0x0960 16 reserved 151 0x0970 16 reserved 152 0x0980 16 reserved 153 0x0990 16 reserved 154 0x09a0 16 reserved 155 0x09b0 16 reserved 156 0x09c0 16 reserved section d (off-platform peripherals) 157 0x09d0 16 tc0ir etimer_0 etimer_0 158 0x09e0 16 tc1ir etimer_0 etimer_0 159 0x09f0 16 tc2ir etimer_0 etimer_0 160 0x0a00 16 tc3ir etimer_0 etimer_0 table 28-4. interrupt sources for intc_0 and intc_1 (continued) irq # offset size (bytes) source signal source module for intc_0 source module for intc_1
interrupt controller (intc) freescale semiconductor 28-31 pxs20 microcontroller reference manual, rev. 1 161 0x0a10 16 tc4ir etimer_0 etimer_0 162 0x0a20 16 tc5ir etimer_0 etimer_0 163 0x0a30 16 not used 164 0x0a40 16 not used 165 0x0a50 16 wtif etimer_0 etimer_0 166 0x0a60 16 not used 167 0x0a70 16 rcf etimer_0 etimer_0 168 0x0a80 16 tc0ir etimer_1 etimer_1 169 0x0a90 16 tc1ir etimer_1 etimer_1 170 0x0aa0 16 tc2ir etimer_1 etimer_1 171 0x0ab0 16 tc3ir etimer_1 etimer_1 172 0x0ac0 16 tc4ir etimer_1 etimer_1 173 0x0ad0 16 tc5ir etimer_1 etimer_1 174 0x0ae0 16 not used 175 0x0af0 16 not used 176 0x0b00 16 not used 177 0x0b10 16 not used 178 0x0b20 16 rcf etimer_1 etimer_1 179 0x0b30 16 rf0 flexpwm_0 180 0x0b40 16 cof0 flexpwm_0 181 0x0b50 16 caf0 flexpwm_0 182 0x0b60 16 rf1 flexpwm_0 183 0x0b70 16 cof1 flexpwm_0 184 0x0b80 16 caf1 flexpwm_0 185 0x0b90 16 rf2 flexpwm_0 186 0x0ba0 16 cof2 flexpwm_0 187 0x0bb0 16 caf2 flexpwm_0 188 0x0bc0 16 rf3 flexpwm_0 189 0x0bd0 16 cof3 flexpwm_0 190 0x0be0 16 caf3 flexpwm_0 191 0x0bf0 16 fflag flexpwm_0 192 0x0c00 16 ref flexpwm_0 193 0x0c10 16 mrs_i ctu_0 194 0x0c20 16 t0_i ctu_0 table 28-4. interrupt sources for intc_0 and intc_1 (continued) irq # offset size (bytes) source signal source module for intc_0 source module for intc_1
interrupt controller (intc) 28-32 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 195 0x0c30 16 t1_i ctu_0 196 0x0c40 16 t2_i ctu_0 197 0x0c50 16 t3_i ctu_0 198 0x0c60 16 t4_i ctu_0 199 0x0c70 16 t5_i ctu_0 200 0x0c80 16 t6_i ctu_0 201 0x0c90 16 t7_i ctu_0 202 0x0ca0 16 fifo0_i ctu_0 203 0x0cb0 16 fifo1_i ctu_0 204 0x0cc0 16 fifo2_i ctu_0 205 0x0cd0 16 fifo3_i ctu_0 206 0x0ce0 16 adc_i ctu_0 207 0x0cf0 16 err_i ctu_0 208 0x0d00 16 not used 209 0x0d10 16 not used 210 0x0d20 16 not used 211 0x0d30 16 not used 212 0x0d40 16 not used 213 0x0d50 16 not used 214 0x0d60 16 not used 215 0x0d70 16 not used 216 0x0d80 16 not used 217 0x0d90 16 not used 218 0x0da0 16 not used 219 0x0db0 16 not used 220 0x0dc0 16 not used 221 0x0dd0 16 not used 222 0x0de0 16 tc0ir etimer_2 223 0x0df0 16 tc1ir etimer_2 224 0x0e00 16 tc2ir etimer_2 225 0x0e10 16 tc3ir etimer_2 226 0x0e20 16 tc4ir etimer_2 227 0x0e30 16 tc5ir etimer_2 228 0x0e40 16 not used table 28-4. interrupt sources for intc_0 and intc_1 (continued) irq # offset size (bytes) source signal source module for intc_0 source module for intc_1
interrupt controller (intc) freescale semiconductor 28-33 pxs20 microcontroller reference manual, rev. 1 229 0x0e50 16 not used 230 0x0e60 16 not used 231 0x0e70 16 not used 232 0x0e80 16 rcf etimer_2 233 0x0e90 16 rf0 flexpwm_1 234 0x0ea0 16 cof0 flexpwm_1 235 0x0eb0 16 caf0 flexpwm_1 236 0x0ec0 16 rf1 flexpwm_1 237 0x0ed0 16 cof1 flexpwm_1 238 0x0ee0 16 caf1 flexpwm_1 239 0x0ef0 16 rf2 flexpwm_1 240 0x0f00 16 cof2 flexpwm_1 241 0x0f10 16 caf2 flexpwm_1 242 0x0f20 16 rf3 flexpwm_1 243 0x0f30 16 cof3 flexpwm_1 244 0x0f40 16 caf3 flexpwm_1 245 0x0f50 16 fflag flexpwm_1 246 0x0f60 16 ref flexpwm_1 247 0x0f70 16 core_0 failed lock attempt 3 sema4_0 - core_1 failed lock attempt 3 - sema4_0 248 0x0f80 16 core_0 failed lock attempt 3 sema4_1 - core_1 failed lock attempt 3 - sema4_1 249 0x0f90 16 not used 250 0x0fa0 16 alarm interrupt (alrm) fccu 251 0x0fb0 16 configuration time-out (cfg_to) fccu 252 0x0fc0 16 self check rcc0 failure fccu 253 0x0fd0 16 self check rcc1 failure fccu 254 0x0fe0 16 voltage monitor fault or high/low voltage detector error pmu 255 0x0ff0 16 swg error (serr) swg notes: 1 as the pflashc_1 is not operational in dp mode, the ecsm_1 instantiation does not receive any flash memory ecc status or rww information and t herefore can not signal any rww, ecc sbc or non-correctable ecc interrupt to the intc_1. theref ore core_1 will not receive any status notification on flash rww events and ecc errors in dp mode. 2 the interrupt from swt 0 goes to both intcs as ir q 28. the interrupt from swt 1 goes to both intcs as irq 29. table 28-4. interrupt sources for intc_0 and intc_1 (continued) irq # offset size (bytes) source signal source module for intc_0 source module for intc_1
interrupt controller (intc) 28-34 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 3 the sema4 unit is only available in dp mode.
jtag controller (jtagc) freescale semiconductor 29-1 pxs20 microcontroller reference manual, rev. 1 chapter 29 jtag controller (jtagc) 29.1 introduction figure 29-1 is a block diagram of the jt ag controller (jtagc) block. figure 29-1. jtag stl (i eee 1149.1) block diagram 29.1.1 overview the jtagc block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. testi ng is performed via a bounda ry scan technique, as defined in the ieee 1149.1-2001 standard. all data input to and output from the jtagc block is communicated in serial format. 29.1.2 features the jtagc block is compliant wi th the ieee 1149.1-2001 standard, and supports the following features: ? ieee 1149.1-2001 test access port (tap) interface ? 4 pins (tdi, tms, tck, and tdo) tck tms tdi test access port (tap) tdo 32-bit device identification register boundary scan register . . controller 1-bit bypass register . 5-bit tap instruction decoder 5-bit tap instruction register . . . jcomp 5-bit tap instruction decoder .
jtag controller (jtagc) 29-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? a jcomp input that provides reset cont rol and the ability to share the tap. ? a 5-bit instruction register that supports seve ral ieee 1149.1-2001 defined instructions as well as several public and private device-s pecific instructions. refer to table 29-3 for a list of supported instructions. ? sharing of the tap with other tap contro llers via access_aux_tap_x instructions. ? a test_ctrl register (for cut2/3 only) ? test data registers: a bypass register, a boundary scan register, and a device identif ication register. ? a tap controller state machine that controls the operation of the data registers, instruction register and associated circuitry. 29.1.3 modes of operation the jtagc block uses jcomp and a power-on reset i ndication as its primary re set signals. several ieee 1149.1-2001 defined test modes are supported, as well as a bypass mode. 29.1.3.1 reset the jtagc block is placed in reset when either powe r-on reset is asserted, jcomp is negated, or the tms input is held high for enough consecutive rising edge s of tck to sequence the tap controller state machine into the test-logic-reset state. holdi ng tms high for 5 consecutive rising edges of tck guarantees entry into the test-logic-reset state regardle ss of the current tap cont roller state. asserting power-on reset or setting jcomp to a value other th an the value required to enable the jtagc block results in asynchronous entry into the reset state. while in reset, the following actions occur: ? the tap controller is forced into the test-logic- reset state, thereby disa bling the test logic and allowing normal operation of the on-chip system logic to continue unhindered ? the instruction register is load ed with the idcode instruction 29.1.3.2 ieee 1149.1-20 01 defined test modes the jtagc block supports several ieee 1149.1-2001 defi ned test modes. a test mode is selected by loading the appropriate instruction in to the instruction register while the jtagc is enabled. supported test instructions include extest, sample and sample/ preload. each instruction defines the set of data register(s) that may operate and interact with the on-chip system logic while the instruction is current. only one test data register path is enabled to shift data betwee n tdi and tdo for each instruction. the boundary scan register is enabled for seri al access between tdi and tdo when the extest, sample or sample/preload instructions are active . the functionality of each test mode is explained in more detail in section 29.4.4, jtagc block instructions . 29.1.3.3 bypass mode when no test operation is required, th e bypass instruction can be loaded to place the jtagc block into bypass mode. while in bypass mode , the single-bit bypass shift regi ster is used to provide a minimum-length serial path to shift data between tdi and tdo.
jtag controller (jtagc) freescale semiconductor 29-3 pxs20 microcontroller reference manual, rev. 1 29.2 external signal description 29.2.1 overview the jtagc consists of 5 signals that connect to off chip development tools and allow access to test support functions. the jtagc signals are outlined in table 29-1 . 29.2.2 detailed signal descriptions this section describes each of the signals listed in table 29-1 in more detail. 29.2.2.1 tck - test clock input test clock input (tck) is an input pin used to synchronize the test logic and control register access through the tap. 29.2.2.2 tdi - test data input test data input (tdi) is an input pin that receives seri al test instructions and data. tdi is sampled on the rising edge of tck. 29.2.2.3 tdo - test data output test data output (tdo) is an output pin that transmits serial output for test instructions and data. tdo is three-stateable and is actively driven only in the shift- ir and shift-dr states of the tap controller state machine, which is described in section 29.4.3, tap controller state machine . the tdo output of this block is clocked on the falling edge of tck and sampled by the develo pment tool on the rising edge of tck. 29.2.2.4 tms - test mode select test mode select (tms) is an input pin used to sequence the ieee 1149.1-2001 test control state machine. tms is sampled on the rising edge of tck. table 29-1. jtag signal properties name i/o function reset state pull 1 notes: 1 the pull is not implemented in this block. pullu p/pulldown devices are implemented in the pads. tck input test clock - down tdi input test data in - up tdo output test data out high z 2 2 tdo output buffer enable is negated when the jtag c is not in the shift-ir or shift-dr states. a weak pull may be implemented at the tdo pad for use when jtagc is inactive. - tms input test mode select - up jcomp input jtag compliancy - down
jtag controller (jtagc) 29-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 29.2.2.5 jcomp - jtag compliancy the jcomp signal provides ieee 1149.1-2001 compatibility and provides the ability to share the tap. the jtagc tap controller is enabled when jcomp is set to the jtagc enable encoding , otherwise the jtagc tap controller remains in reset. 29.3 register definition this section provides a detailed description of the jtagc block registers accessible through the tap interface, including data registers a nd the instruction register. individua l bit-level descriptions and reset states of each register are included. these regist ers are not memory-mappe d and can only be accessed through the tap. 29.3.1 register descriptions the jtagc block registers are described in this section. 29.3.1.1 instruction register the jtagc block uses a 5-bit inst ruction register as shown in table 29-2 . the instruction register allows instructions to be loaded into the block to select the test to be performed or the test data register to be accessed or both. instructions are shifted in through tdi while the tap controller is in the shift-ir state, and latched on the falling edge of tck in the update -ir state. the latched inst ruction value can only be changed in the update-ir and test-logic-reset ta p controller states. synchronous entry into the test-logic-reset state results in the idcode instru ction being loaded on the falling edge of tck. asynchronous entry into the test-l ogic-reset state results in as ynchronous loading of the idcode instruction. during the capture-ir tap controller state, the instruction sh ift register is loaded with the value 0b10101, making this value the register?s read value when the ta p controller is sequenced into the shift-ir state. figure 29-2. 5-bit instruction register 29.3.1.2 bypass register the bypass register is a single-bit shif t register path selected for serial data transfer be tween tdi and tdo when the bypass or reserve instruc tions are active. after entry into th e capture-dr stat e, the single-bit shift register is set to a logic 0. therefore, the first bit shifted out after selecting the bypass register is always a logic 0. 29.3.1.3 device identification register the device identification register, shown in figure 29-3 , allows the revision number, part number, manufacturer, and design center responsible for the de sign of the part to be determined through the tap. 4 3 2 1 0 r 1 0 1 0 1 w instruction code reset: 0 0 0 0 1
jtag controller (jtagc) freescale semiconductor 29-5 pxs20 microcontroller reference manual, rev. 1 the device identification register is selected for serial data tran sfer between tdi and tdo when the idcode instruction is active. entry into the capture- dr state while the device identification register is selected loads the idcode into the shift register to be shifted out on tdo in the shift-dr state. no action occurs in the update-dr state. th e part revision number (p rn) and part identifica tion number (pin) fields are system plugs, and the manufacturer identity c ode (mic) is a constant value assigned to the manufacturer by the jedec. the shift register lsb is fo rced to logic 1 on the ri sing edge of tck following entry into the capture-dr state. therefore, the first bit to be shifted out after selecting the idcode register is always a logic 1. the remaining 31 bits are forced to the value of the de vice identification register on the rising edge of tck following entry into the capture-dr state. figure 29-3. device identification register prn ? part revision number bits [31:28] contain the re vision number of the part. cut1: 0x0 cut2: 0x0 cut3: 0x1 dc ? design center bits [27:22] indicate the design center. the default value is 0x2b. pin ? part identification number bits [21:12] contain the pa rt number of the device. cut1: 0x2a2 cut2: 0x2a3 cut3: 0x2a3 mic ? manufacturer identity code bits [11:1] contain the reduced joint electron de vice engineering council (jedec) id. the default value is 0x00e. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r part revision number design center part identification number w reset: prn dc pin 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r part identification number manufacturer identity code 1 w reset: pin (contd.) 0 0 0 0 0 0 0 1 1 1 0 1 = reserved
jtag controller (jtagc) 29-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 bit [0] ? idcode register id bit [0] identifies this register as the device identification re gister and not the bypass register 29.3.1.4 test_ctrl register (cut2/3 only) the test_ctrl register (supported on cut2/3 only) is a k-bit shift register path from tdi to tdo selected when the enable_test_ctrl instruction is active. the size (k) of the test_ctrl register is defined by the test_ctrl_size pa rameter. the test_ctrl register tr ansfers its value to a parallel hold register on the rising e dge of tck when the tap controller stat e machine is in the update-dr state. 29.3.1.5 censor_ctrl register the censor_ctrl register is a 65 -bit shift register path from tdi to tdo selected when the enable_censor_ctrl instruction is active. the default reset valu e of the censor_ctrl register is 65?b0 . the censor_ctrl register transfers its value to a parallel hold register on the rising edge of 01234567891011121314 r pstat_sel tdo_sel rdy_sel rdy_enable 1 1 notes: 1 this bit is reserved. the defined value will be used for future compatibility. 0 1 1 1 1 1 1 1 0 1 1 1 0 1 0 1 0 1 0 1 w reset 000010111010000 figure 4. test_ctrl register (cut2/3 only) table 29-2. test_ctrl field descriptions field description pstat_sel processor status select selects whether the core_0 or the core_1 processor status outputs will appear on the nexus mdo pins when processor status mode is enabled in the npc port configuration register. 0 core_0 pstat outputs selected. 1 core_1 pstst outputs selected. tdo_sel tdo select selects whether the core_0 or core_1 tdo output will be observable. 0 core_0 tdo output selected. 1 core_1 tdo output selected. rdy_sel rdy select selects whether the nexus aux interface rdy pad output buffer is fed by core_0 or by core_1 rdy_b signal 0 core_0 provides rdy signal 1 core_1 provides rdy signal rdy_enable rdy enable enables rdy functionality for corresponding gpio pin. setting this bit overrides siul output muxing configuration for the corresponding pad. 0 disables rdy functionality (output mux for the pad is controlled by siul) 1 enables rdy functionality (output mux for the pad is controlled by jtagc)
jtag controller (jtagc) freescale semiconductor 29-7 pxs20 microcontroller reference manual, rev. 1 tck when the tap controller state machin e is in the update-dr state. once the enable_censor_ctrl instruction is executed, the register value will remain valid until a jtag reset occurs. figure 29-5. censor_ctrl register censor_ctrl - censorship control the censor_ctrl bits are used to co ntrol chiptop censorship functions. 29.3.1.6 boundary scan register the boundary scan register is connected betw een tdi and tdo when the extest, sample or sample/preload instructions are active. it is used to capture input pin da ta, force fixed values on output pins, and select a logic value and direction fo r bidirectional pins. each bit of the boundary scan register represents a sepa rate boundary scan register cell, as described in the ieee 1149.1-2001 standard and discussed in section 29.4.5, boundary scan. the size of the boundary scan register and bi t ordering is device-dependent and can be f ound in the device bsdl file. 29.4 functional description 29.4.1 jtagc reset configuration while in reset, the tap controller is forced into th e test-logic-reset state, thus disabling the test logic and allowing normal operation of the on-chip system logic. in addition, the instruction register is loaded with the idcode instruction. 29.4.2 ieee 1149.1-2001 (j tag) test access port the jtagc block uses the ieee 1149.1-2001 tap for acce ssing registers. this port can be shared with other tap controllers on the mcu. ow nership of the port is determined by the valu e of the jcomp signal and the currently loaded instructi on. for more detail on tap sharing via jtagc instructions refer to section 29.4.4.6, access_aux_tap_x instructions . data is shifted between tdi and tdo though the selected register starting wi th the least significant bit, as illustrated in figure 29-6 . this applies for the instruction regist er, test data registers, and the bypass register. * 1 notes: 1 the size of censor_ctrl is 65 bits . ... 2 1 0 r censor_ctrl w reset: * 2 2 the reset value of censor_ctrl is 65?b0 . * * * *
jtag controller (jtagc) 29-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 29-6. shifting data through a register 29.4.3 tap controller state machine the tap controller is a synchronous state machine that interprets the sequence of logical values on the tms pin. figure 29-7 shows the machine?s states. the value show n next to each state is the value of the tms signal sampled on the rising edge of the tck signal. as figure 29-7 shows, holding tms at logic 1 while clocking tck through a su fficient number of rising edges also causes the state machine to enter the test-logic-reset state. selected register msb lsb tdi tdo
jtag controller (jtagc) freescale semiconductor 29-9 pxs20 microcontroller reference manual, rev. 1 figure 29-7. ieee 1149.1-2001 tap c ontroller finite state machine test logic reset run-test/idle select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pau s e - i r exit2-dr exit2-ir update-dr update-ir 1 0 1 1 1 00 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 note: the value shown adjacent to each state transition in this figure represents the value of tms at the time of a rising edge of tck.
jtag controller (jtagc) 29-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 29.4.3.1 enabling the tap controller the jtagc tap controller is enabled by setting jcomp to a logic 1 value. 29.4.3.2 selecting an ie ee 1149.1-2001 register access to the jtagc data registers is achieved by loading the instructi on register with any of the jtagc block instructions while the jtagc is enabled. instru ctions are shifted in via the select-ir-scan path and loaded in the update-ir state. at this point, all data register access is performed via the select-dr-scan path. the select-dr-scan path is used to read or write the register data by shifting in the data (lsb first) during the shift-dr state. when reading a register, the regi ster value is loaded into the ieee 1149.1-2001 shifter during the capture-dr state. when writing a regi ster, the value is loaded from the ieee 1149.1-2001 shifter to the register during the u pdate-dr state. when reading a regist er, there is no requirement to shift out the entire register c ontents. shifting may be terminated once the required number of bits have been acquired. 29.4.4 jtagc block instructions the jtagc block implements the ieee 1 149.1-2001 defined instructions listed in table 29-3 . this section gives an overv iew of each instruction; re fer to the ieee 1149.1-2001 standard for more details. all undefined opcodes are reserved. table 29-3. jtag instructions instruction code[4:0] instruction summary idcode 00001 selects device identification register for shift sample/preload 00010 selects boundary scan register for shifting, sampling, and preloading without disturbing functional operation sample 00011 selects boundary scan register for shifting and sampling without disturbing functional operation extest 00100 selects boundary scan register while applying preloaded values to output pins and asserting functional reset access_aux_tap_x 10000-11110 grants one of the auxiliary tap controllers ownership of the tap as shown in the cells below. the number of auxiliary tap controllers sharing the port is share_cnt factory debug reserved 00101, 00110, 01010, 00111 intended for factory debug only access_aux_tap_npc 10000 enables access to the npc tap controller access_aux_tap_core_0 10001 enables a ccess to core_0 tap controller only access_aux_tap_nxss_lsm 10110 enables access to the nxss modules in lsm (cut2/3 only) access_aux_tap_nxss_0 10111 enables access to the nxss_0 module (cut2/3 only) access_aux_tap_nxss_1 11000 enables access to the nxss_1 module (cut2/3 only) access_aux_tap_core_1 11001 enables a ccess to core_1 tap controller only access_aux_tap_lsm 11010 enables access to co re tap controllers in ls mode. both cores receive tdi input data.
jtag controller (jtagc) freescale semiconductor 29-11 pxs20 microcontroller reference manual, rev. 1 29.4.4.1 idcode instruction idcode selects the 32-bit device identification regist er as the shift path between tdi and tdo. this instruction allows interrogation of the mcu to determ ine its version number and other part identification data. idcode is the instruction placed into the in struction register when the jtagc block is reset. 29.4.4.2 sample/preload instruction the sample/preload instru ction has two functions: ? first, the sample portion of the instruction obtains a sample of the system data and control signals present at the mcu input pi ns and just before the boundary s can register cells at the output pins. this sampling occurs on the rising edge of tck in th e capture-dr state when the sample/preload instruction is active. the samp led data is viewed by shifting it through the boundary scan register to the tdo ou tput during the shift- dr state. both the data capture and the shift operation are transparent to system operation. ? secondly, the preload portion of the instructi on initializes the boundary scan register cells before selecting the extest instruction to perf orm boundary scan tests. this is achieved by shifting in initialization data to the boundary scan register during the shift-dr state. the initialization data is transferre d to the parallel outputs of the boundary scan register cells on the falling edge of tck in the update -dr state. the data is applied to the external output pins by the extest instruction. system operation is not affected. 29.4.4.3 sample instruction the sample instruction obtains a samp le of the system data and contro l signals present at the mcu input pins and just before the boundary scan register cells at the output pins . this sampling occurs on the rising edge of tck in the capture-dr stat e when the sample instruction is act ive. the sampled data is viewed by shifting it through th e boundary scan register to the tdo output during the shift-dr state. there is no defined action in the update-dr state. both the data capture and the shift operation are transparent to system operation. 29.4.4.4 extest ? extern al test instruction extest selects the boundary scan regi ster as the shift path between td i and tdo. it allows testing of off-chip circuitry and board-level interconnections by driving preloa ded data contained in the boundary scan register onto the syst em output pins. typically, th e preloaded data is loaded into the boundary scan access_aux_tap_multi 11100 enables access to and serializes the core_0 and core_1 taps bypass 11111 selects bypass register for data operations reserved 1 all other opcodes decoded to select bypass register notes: 1 the manufacturer reserves the right to change the de coding of reserved instruction codes in the future table 29-3. jtag instructions (continued) instruction code[4:0] instruction summary
jtag controller (jtagc) 29-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 register using the sample/preload instruction before the selecti on of extest. extest asserts the internal system reset for the mcu to force a predictable internal st ate while performing external boundary scan operations. 29.4.4.5 enable_censor_ctrl instruction the enable_censor_ctrl instruction selects the censor_ctrl register for connection as the shift path between tdi and tdo. 29.4.4.6 access_aux_tap_x instructions the jtagc is configurable to allow up to fifteen other tap controllers on the device to share the port with it. this is done by providing access _aux_tap_x instructions for each of these tap controllers. when this instruction is loaded, control of the jtag pins are transferred to th e selected tap controller. any data input via tdi and tms is passed to the selected ta p controller, and any tdo output from the selected tap controller is sent back to the jtagc to be out put on the pins. the jtagc regains control of the jtag port during the update-dr state if the pause-dr stat e was entered. auxiliary ta p controllers are held in run-test/idle while they are inactive. instructions not used to access an auxiliary tap controller on a device are treated like the bypass instruction. 29.4.4.7 bypass instruction bypass selects the bypass register, creating a single-bit shift regist er path between tdi and tdo. bypass enhances test efficiency by reducing the overall shift path when no test operation of the mcu is required. this allows more rapid move ment of test data to and from other components on a board that are required to perform test functions. while the bypass instruction is active the system logic operates normally. 29.4.5 boundary scan the boundary scan technique allows signals at component boundaries to be controlled and observed through the shift-register stage asso ciated with each pad. each stage is part of a larger boundary scan register cell, and cells for each pad are interconnected serially to form a shift-register chain around the border of the design. the boundary scan register consists of this shift -register chain, and is connected between tdi and tdo when the extest, sample, or sample/preload instructions are loaded. the shift-register chain contains a serial input and serial output, as well as clock and control signals. 29.5 initialization/application information the test logic is a static logic de sign, and tck can be stopped in either a high or low state without loss of data. however, the system clock is not synchroni zed to tck internally. a ny mixed operation using both the test logic and the system functional logic requires extern al synchronization. to initialize the jtagc block and enable access to registers, the following sequence is required: 1. set the jcomp signal to the jtagc enable value, thereby enabling the jtagc tap controller 2. load the appropriate instruction for the test or action to be performed
jtag controller (jtagc) freescale semiconductor 29-13 pxs20 microcontroller reference manual, rev. 1
jtag controller (jtagc) 29-14 freescale semiconductor pxs20 microcontroller reference manual, rev. 1
memory protection unit (mpu) freescale semiconductor 30-1 pxs20 microcontroller reference manual, rev. 1 chapter 30 memory protection unit (mpu) 30.1 introduction the memory protection unit (mpu) provides hard ware access control for all memory references generated in a device. using region descriptors whic h define memory spaces and their associated access rights, the mpu concurrently monitors all system bus transactions and evalua tes the appropriateness of each transfer. memory references that have sufficie nt access control rights are allowed to complete, while references that are not mapped to any region descriptor or have insuff icient rights are terminated with a protection error response. the mpu implements a set of program-visible region descriptors whic h are used to moni tor all system bus addresses. the result is a hardware structure with a two-dimensional connecti on matrix, where the region descriptors represent one dimension and the individual system bus addresses and attr ibutes are the second dimension. 30.2 block diagram a simplified block diagram of the mpu module is shown in figure 30-1 . the hardware?s two-dimensional connection matrix is clearly visible with the basi c access evaluation ?macro? shown as the replicated submodule block. the ahb 1 bus slave ports (s{0,1,2,3}_h*) are shown on th e left side of the diagram, the region descriptor registers in the middle and the ips bus interface (ips_*) on the right side. the evaluation macro contains the tw o magnitude comparators connected to the start and end address registers from each region descriptor ( rgd n ) as well as the combinational logic bl ocks to determine the region hit and the access protection error. for information on th e details of the access evaluation macro, see section 30.7.1, access evaluation macro . 1.arm?s advanced hi gh-performance bus
memory protection unit (mpu) 30-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 30-1. mpu block diagram ips_wdata ips_addr decode mux ips bus 31 0 control rgd0 rgd1 rgd(n-1) hit_b start end error ips_rdata 31 0 hit_b start end error error_detail (edrn) error_address (earn) > > ahb_error_ap > > bus slave ports address phase signals s{1,2,3}_h* s0_h* r,w,x r,w,x
memory protection unit (mpu) freescale semiconductor 30-3 pxs20 microcontroller reference manual, rev. 1 30.3 features the mpu implements a two-dimensional hardware arra y of memory region descriptors and the crossbar slave ahb ports to continuously monitor the legality of every memory refere nce generated by each bus master in the system. the feature set includes: ? support for 16 memory region descriptors ? specification of start and end addresses provide gran ularity for region sizes from 32 bytes to 4gb ? 4 bus masters that support the traditional {read, write, execute} permissions w ith independent definitions for supervisor and user mode accesses. ? automatic hardware maintenance of the region de scriptor valid bit rem oves issues associated with maintaining a coherent image of the descriptor ? alternate memory view of the access control wo rd for each descriptor provides an efficient mechanism to dynamically alter only the access rights of a descriptor ? for overlapping region descript ors, priority is given to permission granting over access denying as this approach provides more flexibility to sy stem software. see section 30.7.2, putting it all together and ahb error terminations , for details and section 30.9, application information , for an example. ? support for 3 ahb slave port connections ? mpu hardware continuously monitors every ahb slave port access us ing the pre-programmed memory region descriptors ? an access protection error is det ected if a memory reference doe s not hit in any memory region or the reference is flagged as illegal in all memory regions where it does hit. in the event of an access error, the ahb reference is terminated wi th an error response and the mpu inhibits the bus cycle being sent to the targeted slave devi ce. this results in a machine check exception. ? 64-bit error registers, one for each ahb slave port, capture the last faulting address, attributes and ?detail? information ? global mpu enable/disable control bit provides a mechanism to easily load region descriptors during system startup or allow complete a ccess rights during debug wi th the module disabled on this device, the two instantiations of the mpu are referred to as mp u_0 (attached to the slave side of xbar_0) and mpu_1 (attached to the slave side of xbar_1). both instantiations are identical and do not differ in ls mode or dp mode. the mpu port allocation is shown in table 30-1 . table 30-1. mpu port allocation axbs slave port mpu_0 mpu_1 flash memory port 0 port 0 sram port 1 port 1 peripheral bridge port 2 port 2
memory protection unit (mpu) 30-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 30.4 modes of operation the mpu module does not support any special modes of operation. as a memory-mapped device located on the platform?s high-speed system bus, it responds based strictly on the memory addresses of the connected system buses. the ips bus is used to access the mpu?s programming model and the memory protection functions are evaluated on a reference-by-reference basis us ing the addresses from the ahb system bus port(s). power dissipation is minimized when the mp u?s global enable/disable bit is cleared (mpu_cesr[vld] = 0). 30.5 external signal description the mpu module does not include any external interface. 30.6 memory map and register definition the mpu module provides an ips programming model ma pped to an spp-standard on-platform 16 kb space. the programming model is partitioned into three groups: ? control/status registers ? the data structure contai ning the region descriptors ? the alternate view of the regi on descriptor access control values the programming model can onl y be referenced using 32- bit (word) accesses. atte mpted references using different access sizes, to undefined (r eserved) addresses, or with a non- supported access type (for example, a write to a read-only regi ster or a read of a write-only regist er) generate an ips error termination. the mpu programming model map is shown in table 30-2 . table 30-2. mpu memory map offset address register name register description size (bits) location 0x0000 mpu_cesr mpu control/error status register 32 on page 30-6 0x0004? 0x000f reserved 0x0010 mpu_ear0 mpu error address register, slave port 0 32 on page 30-6 0x0014 mpu_edr0 mpu error detail register, slave port 0 32 on page 30-7 0x0018 mpu_ear1 mpu error address register, slave port 1 32 on page 30-6 0x001c mpu_edr1 mpu error detail register, slave port 1 32 on page 30-7 0x0020 mpu_ear2 mpu error address register, slave port 2 32 on page 30-6 0x0024 mpu_edr2 mpu error detail register, slave port 2 32 on page 30-7 0x0028? 0x03ff reserved 0x0400 mpu_rgd0 mpu region descriptor 0 128 on page 30-8
memory protection unit (mpu) freescale semiconductor 30-5 pxs20 microcontroller reference manual, rev. 1 0x0410 mpu_rgd1 mpu region descriptor 1 128 on page 30-8 0x0420 mpu_rgd2 mpu region descriptor 2 128 on page 30-8 0x0430 mpu_rgd3 mpu region descriptor 3 128 on page 30-8 0x0440 mpu_rgd4 mpu region descriptor 4 128 on page 30-8 0x0450 mpu_rgd5 mpu region descriptor 5 128 on page 30-8 0x0460 mpu_rgd6 mpu region descriptor 6 128 on page 30-8 0x0470 mpu_rgd7 mpu region descriptor 7 128 on page 30-8 0x0480 mpu_rgd8 mpu region descriptor 8 128 on page 30-8 0x0490 mpu_rgd9 mpu region descriptor 9 128 on page 30-8 0x04a0 mpu_rgd10 mpu region descriptor 10 128 on page 30-8 0x04b0 mpu_rgd11 mpu region descriptor 11 128 on page 30-8 0x04c0 mpu_rgd12 mpu region descriptor 12 128 on page 30-8 0x04d0 mpu_rgd13 mpu region descriptor 13 128 on page 30-8 0x04e0 mpu_rgd14 mpu region descriptor 14 128 on page 30-8 0x04f0 mpu_rgd15 mpu region descriptor 15 128 on page 30-8 0x0500- 0x07ff reserved 0x0800 mpu_rgdaac0 mpu rgd alternate access control 0 32 on page 30-13 0x0804 mpu_rgdaac1 mpu rgd alternate access control 1 32 on page 30-13 0x0808 mpu_rgdaac2 mpu rgd alternate access control 2 32 on page 30-13 0x080c mpu_rgdaac3 mpu rgd alternate access control 3 32 on page 30-13 0x0810 mpu_rgdaac4 mpu rgd alternate access control 4 32 on page 30-13 0x0814 mpu_rgdaac5 mpu rgd alternate access control 5 32 on page 30-13 0x0818 mpu_rgdaac6 mpu rgd alternate access control 6 32 on page 30-13 0x081c mpu_rgdaac7 mpu rgd alternate access control 7 32 on page 30-13 0x0820 mpu_rgdaac8 mpu rgd alternate access control 8 32 on page 30-13 0x0824 mpu_rgdaac9 mpu rgd alternate access control 9 32 on page 30-13 0x0828 mpu_rgdaac10 mpu rgd alternate access control 10 32 on page 30-13 0x082c mpu_rgdaac11 mpu rgd alternate access control 11 32 on page 30-13 0x0830 mpu_rgdaac12 mpu rgd alternate access control 12 32 on page 30-13 0x0834 mpu_rgdaac13 mpu rgd alternate access control 13 32 on page 30-13 0x0838 mpu_rgdaac14 mpu rgd alternate access control 14 32 on page 30-13 0x083c mpu_rgdaac15 mpu rgd alternate access control 15 32 on page 30-13 0x0840- 0x3fff reserved table 30-2. mpu memory map (continued) offset address register name register description size (bits) location
memory protection unit (mpu) 30-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 30.6.1 mpu control/error st atus register (mpu_cesr) the mpu_cesr provides one byte of error status plus three bytes of configur ation information. a global mpu enable/disable bit is also included in this register. figure 30-2. mpu control/error status register (mpu_cesr) 30.6.2 mpu error address register, slave port n (mpu_earn) when the mpu detects an access error on slave port n, th e 32-bit reference address is captured in this read-only register and the corresponding bit in the mpu_cesr[sperr] field set. additional information about the faulting access is captured in the corresponding mpu_ edrn register at the same time. this register and the corresponding mpu_ed rn register contain the most r ecent access error; there are no hardware interlocks with the mpu_ cesr[sperr] field as the error re gisters are always loaded upon the occurrence of each pr otection violation. offset mpu_base + 0x000 access: read/partial write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r sperr000001000 hrl nsp nrgd 00 00 0 0 0 vld ww1c reset00000000100000000011001000000000 table 30-3. mpu_cesr field descriptions field description sperr slave port n error, where the slave port number matches the bit number. each bit in this field represents a flag maintained by the mpu for signaling the presence of a captured error contained in the mpu_earn and mpu_edrn regist ers. the individual bit is set when the hardware detects an error and records the faulting address and attributes. it is cleared when the corresponding bit is written as a logical one. if another error is captured at the exact same cycle as a write of a logical one, this flag remains set. a ?find first one? instruction (o r equivalent) can be used to detect the presence of a captured error. 0 the corresponding mpu_earn/mpu_edrn r egisters do not contain a captured error. 1 the corresponding mpu_earn/mpu_edrn registers do contain a captured error. hrl hardware revision level. this 4-bit read-only field specifies the mpu?s hardware and definition revision level. it can be read by software to determine the functional definition of the module. nsp number of slave ports. this 4-bit read-only field specifies the number of slave ports connected to the mpu. for this device, nsp = 3. nrgd number of region descriptors. this 4-bit read-only field specifies the number of region descriptors implemented in the mpu. the defined encodings include: 0b00 8 region descriptors 0b01 12 region descriptors 0b10 16 region descriptors (correct value for this device) vld valid. this bit provides a global enable/disable for the mpu. 0 the mpu is disabled. 1 the mpu is enabled. while the mpu is disabled, all accesses from all bus masters are allowed.
memory protection unit (mpu) freescale semiconductor 30-7 pxs20 microcontroller reference manual, rev. 1 figure 30-3. mpu error address register, slave port n (mpu_earn) 30.6.3 mpu error detail register, slave port n (mpu_edrn) when the mpu detects an access error on slave port n, 32 bits of error deta il are captured in this read-only register and the corresponding bit in the mpu_cesr [sperr] field set. information on the faulting address is captured in the correspondi ng mpu_earn register at the same time. note this register and the corresponding mpu_earn register contain the most r ecent access error; there are no hardware interlocks with the mpu_cesr[sperr] field as the error regist ers are always loaded upon the occurrence of each protection violation. figure 30-4. mpu error detail register, slave port n (mpu_edrn) offset mpu_base + 0x010 (mpu_ear0) mpu_base + 0x018 (mpu_ear1) mpu_base + 0x020 (mpu_ear2) access: read read read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eaddr w reset00000000000000000000000000000000 table 30-4. mpu_earn field descriptions field description 0?31 eaddr error address. this read-only field is the refe rence address from slave port n that generated the access error. offset mpu_base + 0x014 (mpu_edr0) mpu_base + 0x01c (mpu_edr1) mpu_base + 0x024 (mpu_edr2) access: read read read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eacd epid emn eattr erw w reset00000000000000000000000000000000
memory protection unit (mpu) 30-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 30.6.4 mpu region descriptor n (mpu_rgdn) each 128-bit (four 32-bit word) region descriptor specifi es a given memory space and the access attributes associated with that space. the desc riptor definition is the very esse nce of the operation of the memory protection unit. the region descriptors ar e organized sequentially in the mpu?s pr ogramming model and each of the four 32-bit words are detailed in the subsequent sections. 30.6.4.1 mpu region descriptor n, word 0 (mpu_rgdn.word0) the first word of the mpu region descriptor define s the 0-modulo-32 byte start address of the memory region. writes to this word clear th e region descriptor?s valid bit (see section 30.6.4.4, mpu region descriptor n, word 3 (mpu_rgdn.word3), for more information). table 30-5. mpu_edrn field descriptions field description 0?15 eacd error access control detail. this 16-bit read-only field implements one bit per region descriptor and is an indication of the region descriptor hit where the error occurred. the mpu performs a reference-by-reference evaluation to determine the presence/absence of an access error. when an error is detected, the hit-qualified access c ontrol vector is captured in this field. if the mpu_edrn register contains a captured erro r and the eacd field is all zeroes, this signals an access that did not hit in any region descriptor. all non-zero eacd values signal references that hit in a region descriptor(s), but failed due to a protection error as defined by the specific set bits. if only a single eacd bit is set, then the protection error was caused by a single non-overlapping region descriptor. if two or more eacd bits are set, then the protection error was caused in an overlapping set of region descriptors. 16?23 epid error process identification. this 8-bit read-only field records the process identifier of the faulting reference. the process identifier is typically driven only by processor cores; fo r other bus masters, this field is cleared. 24?27 emn error master number. this 4-bit read-only field records the logical master number of the faulting reference. this field is used to determine the bus master that generated the access error. 28?30 eattr error attributes. this 3-bit read-only field records at tribute information about the faulting reference. the supported encodings are defined as: 0b00 user mode, instruction access 0b01 user mode, data access 0b10 supervisor mode, instruction access 0b11 supervisor mode, data access all other encodings are reserved. for non-core bu s masters, the access attribute information is typically wired to supervisor, data (0b011). 31 erw error read/write. this 1-bit read-only field signals the access type (read, write) of the faulting reference. 0read 1write
memory protection unit (mpu) freescale semiconductor 30-9 pxs20 microcontroller reference manual, rev. 1 figure 30-5. mpu region descriptor, word 0 register (mpu_rgdn.word0) 30.6.4.2 mpu region descriptor n, word 1 (mpu_rgdn.word1) the second word of the mpu region descriptor defines the 31-modulo-32 byte end address of the memory region. writes to this word clear th e region descriptor?s valid bit (see section 30.6.4.4, mpu region descriptor n, word 3 (mpu_rgdn.word3), for more information). figure 30-6. mpu region descriptor, word 1 register (mpu_rgdn.word1) 30.6.4.3 mpu region descriptor n, word 2 (mpu_rgdn.word2) the third word of the mpu region de scriptor defines the access contro l rights of the memory region. bus masters 0-3 have a 6-bit field defining separate privil ege rights for user and supervisor mode accesses as well as the optional inclus ion of a process identificat ion field within the defini tion. for these fields, the bus master number refers to the logical master number as specified in section 15.1.4, logical master ids. offset mpu_base + 0x400 + (16*n) + 0x0 (mpu_rgdn.word0) access: r/w 012345678910111213141516171819202122232425262728293031 r srtaddr 0 0 0 00 w reset00000000000000000000000000 000000 table 30-6. mpu_rgdn.word0 field descriptions field description 0?26 srtaddr start address. this field defines the most significant bits of the 0-modulo-32 byte start address of the memory region. offset mpu_base + 0x400 + (16*n) + 0x4 (mpu_rgdn.word1) access: r/w 012345678910111213141516171819202122232425262728293031 r endaddr 1 1 1 11 w reset (n=0) 11111111111111111111111111 111111 reset (n>0) 00000000000000000000000000 011111 table 30-7. mpu_rgdn.word1 field descriptions field description 0?26 endaddr end address. this field defines t he most significant bits of the 31 -modulo-32 byte end address of the memory region. there are no hardware checks to veri fy that endaddr >= srtaddr; it is software?s responsibility to properly load these region descriptor fields.
memory protection unit (mpu) 30-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 (nexus controllers have ids 8 and 9, but only the last 3 bits of the id are used for this purposes, so they share privileges with cores 0 and 1.) for the processor privilege rights, there are three flags associated with this functi on: {read, write, execute}. in this context, these flags follow the traditional definition: ? read ( r ) permission refers to the ability to access th e referenced memory address using an operand (data) fetch. ?write ( w ) permission refers to the ability to update the referenced memory address using a store (data) instruction. ? execute ( x ) permission refers to the ability to read the referenced memory address using an instruction fetch. writes to this word clear the region descriptor?s valid bit (see section 30.6.4.4, mpu region descriptor n, word 3 (mpu_rgdn.word3), for more information). since it is al so expected that sy stem software may adjust only the access controls with in a region descriptor (mpu_rgdn.wo rd2) as different tasks execute, an alternate programming view of th is 32-bit entity is provided. if only the access controls are being updated, this operation should be pe rformed by writing to mpu_rgdaacn (alternate access control n) as stores to these locations do not affect the descri ptor?s valid bit. figure 30-7. mpu region descriptor, word 2 register (mpu_rgdn.word2) offset mpu_base + 0x400 + (16*n) + 0x8 (mpu_rgdn.word2) access: r/w 012345678 9101112131 4 15 16 17 18 19 2 0 21 22 23 24 25 2 6 27 28 29 30 31 r00000000m 3 p e m3s m m3um r w x m 2 p e m2s m m2um r w x m 1 p e m1s m m1um r w x m 0 p e m0s m m0um r w x w reset (n=0) 000000000 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 reset (n>0) 000000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
memory protection unit (mpu) freescale semiconductor 30-11 pxs20 microcontroller reference manual, rev. 1 table 30-8. mpu_rgdn.word2 field descriptions field description m3pe bus master 3 process identifier enable. if set, this flag specifies that the process identifier and mask (defined in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. m3sm bus master 3 supervisor mode access control. this 2-bit field defines the access controls for bus master 3 when operating in supervisor mode. the m3sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m3um for user mode m3um bus master 3 user mode access control. this 3-bit field defines the access controls for bus master 3 when operating in user mode. the m3um field consis ts of three independent bits, enabling read, write and execute permissions: {r,w,x} . if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated wi th an access error (if not allowed by any other descriptor) and the access not performed. m2pe bus master 2 process identifier enable. if set, this flag specifies that the process identifier and mask (defined in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. m2sm bus master 2 supervisor mode access control. this 2-bit field defines the access controls for bus master 2 when operating in supervisor mode. the m2sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m2um for user mode m2um bus master 2 user mode access control. this 3-bit field defines the access controls for bus master 2 when operating in user mode. the m2um field consis ts of three independent bits, enabling read, write and execute permissions: {r,w,x} . if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated wi th an access error (if not allowed by any other descriptor) and the access not performed. m1pe bus master 1 process identifier enable. if set, this flag specifies that the process identifier and mask (defined in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. m1sm bus master 1 supervisor mode access control. this 2-bit field defines the access controls for bus master 1 when operating in supervisor mode. the m1sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m1um for user mode
memory protection unit (mpu) 30-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 30.6.4.4 mpu region descriptor n, word 3 (mpu_rgdn.word3) the fourth word of the mpu region descriptor contains the optional process identi fier and mask, plus the region descriptor?s valid bit. since the region descriptor is a 4-word entity, there are potential coherency issues as this structure is being updated since multiple writes are required to update the entire descriptor. ac cordingly, the mpu hardware assists in the operation of the descri ptor valid bit to preven t incoherent region desc riptors from generating spurious access errors. in pa rticular, it is expected th at a complete update of a re gion descriptor is typically done with sequential writes to mpu_rgdn.word0, then mpu_rgdn.word1,... and finally mpu_rgdn.word3. the mpu hardware automatically clears the valid bit on any writes to words {0,1,2} of the descriptor. writes to this word set/clear the valid bit in a normal manner. since it is also expected that system software may ad just only the access controls within a region descriptor (mpu_rgdn.word2) as different ta sks execute, an alternate progr amming view of mpu_rgdn.word2 is provided. if only the access controls are being upda ted, this operation should be performed by writing to mpu_rgdaacn (alternate access control n) as stores to these locations do not affect the descriptor?s valid bit. m1um bus master 1 user mode access control. this 3-bit field defines the access controls for bus master 1 when operating in user mode. the m1um field consis ts of three independent bits, enabling read, write and execute permissions: {r,w,x} . if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated wi th an access error (if not allowed by any other descriptor) and the access not performed. m0pe bus master 0 process identifier enable. if set, this flag specifies that the process identifier and mask (defined in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. m0sm bus master 0 supervisor mode access control. this 2-bit field defines the access controls for bus master 0 when operating in supervisor mode. the m0sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m0um for user mode m0um bus master 0 user mode access control. this 3-bit field defines the access controls for bus master 0 when operating in user mode. the m0um field consis ts of three independent bits, enabling read, write and execute permissions: {r,w,x} . if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated wi th an access error (if not allowed by any other descriptor) and the access not performed. table 30-8. mpu_rgdn.word2 field descriptions (continued) field description
memory protection unit (mpu) freescale semiconductor 30-13 pxs20 microcontroller reference manual, rev. 1 figure 30-8. mpu region descriptor, word 3 register (mpu_rgdn.word3) 30.6.5 mpu region descriptor alternate access control n (mpu_rgdaacn) as noted in section 30.6.4.3, mpu region descriptor n, word 2 (mpu_rgdn.word2) , it is expected that since system software may adjust only the access controls within a region descriptor (mpu_rgdn.word2) as diff erent tasks execute, an alternate programming view of this 32-bit entity is desired . if only the access controls ar e being updated, this operation shoul d be performed by writing to mpu_rgdaacn (alternate access control n) as stores to these locations do not affect the descriptor?s valid bit. the memory address therefore provides an alternate location for updating mpu_rgdn.word2. offset mpu_base + 0x400 + (16*n) + 0xc (mpu_rgdn.word3) access: r/w 012345678910111213141516171819202122232425262728293031 r pid pidmask 00 00000000 00 0 0 0v l d w reset00000000000000000000000000 000000 table 30-9. mpu_rgdn.word3 field descriptions field description 0?7 pid process identifier. this 8-bit field specifies that t he optional process identifier is to be included in the determination of whether the current access hits in the region descriptor. this field is combined with the pidmask and included in the region hit determination if mp u_rgdn.word2[mxpe] is set. 8?15 pidmask process identifier mask. this 8-bit field provides a masking capability so that multiple process identifiers can be included as part of the region hit det ermination. if a bit in the pidmask is set, then the corresponding bit of the pid is ignored in the comparison. this field is combined with the pid and included in the region hit determination if mpu_rg dn.word2[mxpe] is set. for more information on the handling of the pid and pidmask, see section 30.7.1.1, access evaluation ? hit determination . 31 vld valid. this bit signals the region descriptor is valid . any write to mpu_rgdn.word{0,1,2} clears this bit, while a write to mpu_rgdn.word3 sets or clear s this bit depending on bit 31 of the write operand. 0 region descriptor is invalid 1 region descriptor is valid
memory protection unit (mpu) 30-14 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 30-9. mpu rgd alternate access control n (mpu_rgdaacn) since the mpu_rgdaacn register is simply anot her memory mapping for mpu_rgdn.word2, the field definitions shown in table 30-10 are identical to those presented in table 30-8 . offset mpu_base + 0x800 + (4*n ) (mpu_rgdaacn) access: r/w 012345678 9101112131 4 15 16 17 18 19 2 0 21 22 23 24 25 2 6 27 28 29 30 31 r00000000m 3 p e m3s m m3um r w x m 2 p e m2s m m2um r w x m 1 p e m1s m m1um r w x m 0 p e m0s m m0um r w x w reset (n=0) 000000000 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 reset (n>0) 000000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 30-10. mpu_rgdaacn field descriptions field description m3pe bus master 3 process identifier enable. if set, this flag specifies that the process identifier and mask (defined in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. m3sm bus master 3 supervisor mode access control. this 2-bit field defines the access controls for bus master 3 when operating in supervisor mode. the m3sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m3um for user mode m3um bus master 3 user mode access control. this 3-bit field defines the access controls for bus master 3 when operating in user mode. the m3um field consis ts of three independent bits, enabling read, write and execute permissions: {r,w,x} . if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated wi th an access error (if not allowed by any other descriptor) and the access not performed. m2pe bus master 2 process identifier enable. if set, this flag specifies that the process identifier and mask (defined in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. m2sm bus master 2 supervisor mode access control. this 2-bit field defines the access controls for bus master 2 when operating in supervisor mode. the m2sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m2um for user mode m2um bus master 2 user mode access control. this 3-bit field defines the access controls for bus master 2 when operating in user mode. the m2um field consis ts of three independent bits, enabling read, write and execute permissions: {r,w,x} . if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated wi th an access error (if not allowed by any other descriptor) and the access not performed.
memory protection unit (mpu) freescale semiconductor 30-15 pxs20 microcontroller reference manual, rev. 1 30.7 functional description in this section, the functional operati on of the mpu is detailed. in partic ular, subsequent sections discuss the operation of the access evaluation macro as well as the handling of error-terminated ahb bus cycles. 30.7.1 access evaluation macro as previously discussed, the basic operation of th e mpu is performed in the access evaluation macro, a hardware structure replicated in the two- dimensional connection matrix. as shown in figure 30-10 , the access evaluation macro inputs the ah b system bus address phase signals (ahb_ap) and the contents of a region descriptor (rgdn) and performs tw o major functions: region hit determination ( hit_b ) and detection of an access protection violation ( error ). m1pe bus master 1 process identifier enable. if set, this flag specifies that the process identifier and mask (defined in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. m1sm bus master 1 supervisor mode access control. this 2-bit field defines the access controls for bus master 1 when operating in supervisor mode. the m1sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m1um for user mode m1um bus master 1 user mode access control. this 3-bit field defines the access controls for bus master 1 when operating in user mode. the m1um field consis ts of three independent bits, enabling read, write and execute permissions: {r,w,x} . if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated wi th an access error (if not allowed by any other descriptor) and the access not performed. m0pe bus master 0 process identifier enable. if set, this flag specifies that the process identifier and mask (defined in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. m0sm bus master 0 supervisor mode access control. this 2-bit field defines the access controls for bus master 0 when operating in supervisor mode. the m0sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m0um for user mode m0um bus master 0 user mode access control. this 3-bit field defines the access controls for bus master 0 when operating in user mode. the m0um field consis ts of three independent bits, enabling read, write and execute permissions: {r,w,x} . if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated wi th an access error (if not allowed by any other descriptor) and the access not performed. table 30-10. mpu_rgdaacn field descriptions (continued) field description
memory protection unit (mpu) 30-16 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 30-10. mpu access evaluation macro figure 30-10 is not intended to be a schematic of th e actual access evaluation macro, but rather a generalized block diagram showing the majo r functions included in this logic block. 30.7.1.1 access evaluation ? hit determination to determine if the current ahb re ference hits in the given region, two magnitude comparators are used in conjunction with the region?s start and end addre sses. the boolean equation fo r this portion of the hit determination is defined as: region_hit =((haddr[0:26]>= rgdn.srtaddr[0:26]) & (haddr[0:26] <= rgdn.endaddr[0:26])) & rgdn.vld eqn. 30-1 where haddr[*] is the current ahb reference address, rgdn.srtaddr[*] and rgdn.endaddr[*] are the start and end addresses, and rgdn.vld is the valid bit, all from region descriptor n. recall there are no hardware checks to verify that rgdn.endaddr > rgdn.srtaddr , and it is software?s responsibility to properly load appropriate values into these fields of the region descriptor. in addition to the algebraic compar ison of the ahb reference address ve rsus the region descriptor?s start and end addresses, the optional proc ess identifier is examined agains t the region descriptor?s pid and pidmask fields. using the hmaster[*] number to select the appropria te mxpe field from the region descriptor, a process identifier hit term is formed as: pid_hit =~rgdn.mxpe | ((current_pid[0:7] | rgdn.pidmask[0:7])= = (rgdn.pid[0:7] | rgdn.pidmask[0:7])) eqn. 30-2 hit_b start end error > > rgdn ahb_ap hit & error hit_b | error >= <= r,w,x
memory protection unit (mpu) freescale semiconductor 30-17 pxs20 microcontroller reference manual, rev. 1 where the current_pid[*] is the selected process identifier from the current bus master, and rgdn.pid[*] and rgdn.pidmask[*] are the appropriate process iden tifier fields from the region descriptor n. for ahb bus masters that do not output a process identifi er, the mpu forces the pid_hit term to be asserted. as shown in figure 30-10 , the access evaluation macro actually forms the logical complement ( hit_b ) of the combined region_hit and pid_hit boolean equations. 30.7.1.2 access evaluation ? priv ilege violation determination while the access evaluation macro is making the region hit determinat ion, the logic is also evaluating if the current access is allowed by the permissions defined in the region de scriptor. using the ahb hmaster[*] and hprot[1] (supervisor/user mode) signals, a set of effective permissions ( eff_rgd[r,w,x] ) is generated from the appropriate fields in the region descriptor. the protection violation logic then evaluates the access against the effective permissi ons using the speci fication shown in table 30-11 . the resulting boolean equation for the processor protection violations is: cpu_protection_violation = ~hwrite & ~hprot[0] & ~eff_rgdn[x]// ifetch & no x | ~hwrite & hprot[0] & ~eff_rgdn[r]// data_read & no r | hwrite& ~eff_rgdn[w] // data_write& no w eqn. 30-3 the resulting boolean equation for the non- processor protection violations is: protection_violation = ~hwrite & ~eff_rgdn[r]// data_read & no r | hwrite& ~eff_rgdn[w] // data_write& no w eqn. 30-4 table 30-11. protection violation definition description inputs output hwrite hprot[0] eff_rgd[r] eff_rgd[w] eff_rgd[x] protection violation? inst fetch read 0 0 ? ? 0 yes, no x permission inst fetch read 0 0 ? ? 1 no, access is allowed data read 0 1 0 ? ? yes, no r permission data read 0 1 1 ? ? no, access is allowed data write 1 ? ? 0 ? yes, no w permission data write 1 ? ? 1 ? no, access is allowed
memory protection unit (mpu) 30-18 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 as shown in figure 30-10 , the output of the protecti on violation logic is the error signal, that is, error = protection_violation . the access evaluation macro then uses the hit_b and error signals to form two outputs. the combined (hit_b | error) signal is used to signal the current access is not allowed and (~hit_b & error) is used as the input to mpu_edrn (error detail register) in the event of an error. the critical timing arc through the access evaluati on macro involves the dela y from the arrival of haddr[*] through the two magnitude comparators and through the hit_b generation as shown in figure 30-11 . figure 30-11. access evaluati on macro critical timing path 30.7.2 putting it all together and ahb error terminations for each ahb slave port being monitored, the mpu performs a reduction-and of all the individual (hit_b | error) terms from each access evaluation macro. this expression then terminates the bus cycle with an error and reports a protection error for three conditions: 1. if the access does not hit in any region descriptor, a pr otection error is reported. 2. if the access hits in a single region descriptor and that region si gnals a protection violation, then a protection error is reported. 3. if the access hits in multip le (overlapping) regions and all regions signal protec tion violations, then a protection error is reported. the third condition reflects th at priority is given to permission granting over access denying for overlapping regions as this approach provides more flexibility to syst em software in region descriptor assignments. for an example of the use of overlapping region descriptors, see section 30.9, application information . the handling of the ahb bus cycle with a protection er ror requires two distinct actions. first, recall the protection error logic reside s within the ahb address phase pipeline stage. in the event of a protection error, the reference must be inhibited from enteri ng the ahb data phase for th e targeted slave device. stated differently, the reference?s address phase must be aborted as viewed by the targeted slave device. hit_b start end error > > rgdn ahb_ap
memory protection unit (mpu) freescale semiconductor 30-19 pxs20 microcontroller reference manual, rev. 1 this is accomplished by dynamically revising the htrans[*] signal sent to the slave device. the htrans[*] attribute signals an idle or valid reference (as a non-sequential or sequent ial access), and this signal is ?intercepted? by the mpu. if the access is allowed, then the mpu simply passes the original htrans[*] value to the slave device. ho wever if a protection error is detected, then the mpu forces htrans[*] sent to the slave to the idle encoding. this effectively cancel s the transaction before it is seen by the slave device. while forcing htrans[*] = idle effectively prevents the bus cycl e from being transmitted to the slave device, the ahb transa ction has already been ?co mmitted? in other portions of the platform, namely in the initiating bus master and the crossbar switch. to properly termin ate the bus cycle for these modules, it is necessary to post the st andard 2-cycle ahb error resp onse. for this response, the hresp[*] signal is forced to the error encoding for 2 cycles, the first with hready negated and the second with hready asserted. to perform these terminat ion functions, the mpu ?intercepts? the hready and hresp[*] signals from the slave devices , performs the required logic f unctions to for ce the response on the bus cycle with a protection error, and then out puts the adjusted values to the crossbar switch. 30.8 initialization information the reset state of mpu_cesr[vld] disables the enti re module. recall while th e mpu is disabled, all accesses from all bus masters are allowed. this stat e also minimizes the power dissipation of the mpu. the power dissipation of each access evaluation macro is minimized when the associated region descriptor is marked as invalid or when mpu_cesr[vld] = 0. typically the appropriate number of region desc riptors (mpu_rgdn) are load ed at system startup, including the setting of the mpu_rgdn.word3[vld] bits, before mpu_cesr[vld] is set, enabling the module. this approach allows all the loaded region de scriptors to be enabled si multaneously. recall if a memory reference does not hit in any region descriptor, the attempted acc ess is terminated with an error. 30.9 application information in an operational system, interfacing with the mpu can generally be classi fied into the following activities: 1. creation of a new memory region requires load ing the appropriate region descriptor into an available register location. when a new descriptor is loaded into a rgdn, it would typically be performed using four 32-bit wo rd writes. as discussed in section 30.6.4.4, mpu region descriptor n, word 3 (mpu_rgdn.word3) , the hardware assists in the maintenance of the valid bit, so if this approach is foll owed, there are no coherency issues associated with the multi-cycle descriptor writes. deletion/remova l of an existing memory region is performed simply by clearing mpu_rgdn.word3[vld]. 2. if only the access rights for an existing region de scriptor need to change , a 32-bit write to the alternate version of the access control word (mpu_rgdaacn) would t ypically be performed. recall writes to the region descriptor using this alternate access control location do not affect the valid bit, so there are, by de finition, no coherency issues invol ved with the update. the access rights associated with the memory region switch in stantaneously to the new value as the ips write completes.
memory protection unit (mpu) 30-20 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 3. if the region?s start and end addresses are to be changed, this would typically be performed by writing a minimum of three words of the re gion descriptor: mpu_rgdn.word{0,1,3}, where the writes to word0 and word1 redefine the start and end addresses respectively and the write to word3 re-enables the region descri ptor valid bit. in many situati ons, all four words of the region descriptor would be rewritten. 4. typically, references to the mpu?s programming m odel would be restricted to supervisor mode accesses from a specific processor(s) , so a region descriptor would be specifically allocated for this purpose with attempted accesses from other masters or while in user mode terminated with an error. 5. when the mpu detects an access error, the curren t ahb bus cycle is terminated with an error response and information on the faulting reference captured in the mpu_earn and mpu_edrn registers. the error-terminated ahb bus cycle typical ly initiates some type of error response in the originating bus master. for example, a proce ssor core may respond with a bus error exception, while a data movement bus master may respond with an error interr upt. in any event, the processor can retrieve the captured error address and detail information simply be reading the mpu_e{a,d}rn registers. information on which er ror registers contain ca ptured fault data is signaled by mpu_cesr[sperr]. 6. finally, consider the use of overlapping region descriptors. appl ication of overla pping regions can often reduce the number of descriptors required fo r a given set of access cont rols. it is important to note that, in the overlapping memory space, the protection rights of the corresponding region descriptors are logically summed together (the boolean or operator) . in the following example of a dual-core system, there are four bus masters: the two processors (cp0, cp1) and two dma engines (dma1, a traditional da ta movement engine transf erring data between ram and peripherals and dma2, a second engine tr ansferring data to/from the ram only). consider the region desc riptor assignments in table 30-12 . in this example, there are 8 descriptors used to span 9 regions in the three main spaces of the system memory map (flash, ram and ips peripheral space). each region indi cates the specific permissions fo r each of the four bus masters and this definition provides an appropriate set of shared, private and executable memory spaces. of particular interest are the two overlappi ng spaces: region descriptors 2 & 3 and 3 & 4. the space defined by rgd2 with no overlap is a private data and st ack area that provides read/write access to cp0 only. the overlapping sp ace between rgd2 and rgd3 defines a shared data space for passing data from cp 0 to cp1 and the access controls are defined by the logical or of the two region descriptors. thus, cp0 has ( rw- | r-- ) = ( rw- ) permissions, while cp1 has ( --- | r-- ) = ( r-- ) permission in this space. both dma engines are excluded from this shared processor data region. the overlapping spaces be tween rgd3 and rgd4 de fines another shared data space, this one for passing data from cp 1 to cp0. for this overlapping space, cp0 has ( r-- | --- ) = ( r-- ) permission, while cp1 has ( rw- | r-- ) = ( rw- ) permission. the non-overlapped space of rgd4 defines a pr ivate data and stac k area for cp1 only. the space defined by rgd5 is a shared data region, accessible by all four bus masters. finally, the slave peripheral space ma pped onto the ips bus is partitioned into two regions: one containing the mpu?s programming model accessible only to th e two processor cores and the remaining peripheral region accessible to both proce ssors and the traditional dma1 master.
memory protection unit (mpu) freescale semiconductor 30-21 pxs20 microcontroller reference manual, rev. 1 this simple example is intended to show one possible appl ication of the capabi lities of the memory protection unit in a typical system. table 30-12. overlapping region descriptor example region description rgdn cp0 cp1 dma1 dma2 system space cp0 code 0 rwx r-- -- -- flash memory cp1 code 1 r-- rwx -- -- cp0 data and stack 2 rw- --- -- -- sram cp0 ? cp1 shared data 3 r-- r-- -- -- cp1 ? cp0 shared data cp1 data and stack 4 --- rw- -- -- shared dma data 5 rw- rw- rw rw mpu 6 rw- rw- -- -- ips peripherals 7 rw- rw- rw --
memory protection unit (mpu) 30-22 freescale semiconductor pxs20 microcontroller reference manual, rev. 1
lin controller (linflexd) freescale semiconductor 31-1 pxs20 microcontroller reference manual, rev. 1 chapter 31 lin controller (linflexd) 31.1 introduction the linflexd (local interconnect network flexible with dma support) controller inte rfaces the lin network and supports the lin prot ocol versions 1.3, 2.0, 2.1 and j2602 in both master and slave modes. linflexd includes a lin mode that provides additional features (compa red to standard uart) to ease lin implementation, improve system robustness, minimize cpu load and allow slave node resynchronization. figure 31-1 shows the linflexd block diagram. figure 31-1. linflexd block diagram 31.2 main features the linflexd controller can operate in several modes, each of which has a distinct set of features. these distinct features are descri bed in the following sections. in addition, the linflexd c ontroller has several featur es common to all modes: ? fractional baud rate generator lin protocol handler register model / application interface buffer interface lin status baud rate filter config. message slave lin control config control status message handler master message handler id filters (1) 1 filter activation optional
lin controller (linflexd) 31-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? 3 operating modes for power saving and configuration registers lock ? initialization ?normal ?sleep ? 2 test modes ? loop back ?self test ? maskable interrupts 31.2.1 lin mode features ? supports lin protocol versions 1.3, 2.0, 2.1 and j2602 ? master mode with aut onomous message handling ? classic and enhanced checksum calculation and check ? single 8-byte buffer for transmission/reception ? extended frame mode for in -application programming purposes ? wake-up event on dominant bit detection ? true lin field state machine ? advanced lin error detection ? header, response and frame timeout ? slave mode ? autonomous header handling ? autonomous transmit/receive data handling ? lin automatic resynchronization, allowing operation with internal rc oscillator as clock source ? identifier filters for autonomous message handling in slave mode 31.2.2 uart mode features ? full-duplex communication ? selectable frame size: ? 8-bit frame ? 9-bit frame ? 16-bit frame ? 17-bit frame ? selectable parity: ? even ?odd ?0 ?1
lin controller (linflexd) freescale semiconductor 31-3 pxs20 microcontroller reference manual, rev. 1 ? 4-byte buffer for reception, 4-byte buffer for transmission ? 12-bit counter for timeout management 31.3 the lin protocol the lin (local interconnect networ k) is a serial communication prot ocol. the topology of a lin network is shown in figure 31-2 . a lin network consists of: ? one master task ? several slave tasks ? the lin bus a master node contains the master ta sk as well as a slave task, all ot her nodes contain a slave task only. the master node decides when and which frame shal l be transferred on the bus. the slave task provides the data to be transported by the frame. figure 31-2. lin network topology 31.3.1 dominant and recessive logic levels the lin bus defines two l ogic levels, ?dominant? a nd ?recessive?, as follows: ? dominant: logical low level (0) ? recessive: logical high level (1) 31.3.2 lin frames a frame consists of a header provided by the master task and a response provided by the slave task, as shown in figure 31-3 . lin master node lin slave node 1 lin slave node n lin lin lin rx tx lin transceiver linflexd controller mcu lin bus application
lin controller (linflexd) 31-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 31-3. lin frame structure 31.3.3 lin header the header consists of: ? a break field (described in section 31.3.3.1, break field ) ? a sync pattern (described in section 31.3.3.2, sync pattern ) ? an identifier (described in section 31.3.4.2, identifier ) the slave task associated with th e identifier provides the response. 31.3.3.1 break field the break field, shown in figure 31-4 , is used to signal the beginning of a new frame. it is always generated by the master and consists of: ? at least 13 dominant bits including the start bit ? at least one recessive bit that functions as break delimiter figure 31-4. break field 31.3.3.2 sync pattern the sync pattern is a byte consisting of altern ating dominant and recessi ve bits as shown in figure 31-5 . it forms a data value of 0x55. header response header response master task slave task 1 slave task 2 frame slot frame header response space response start bit break delimiter
lin controller (linflexd) freescale semiconductor 31-5 pxs20 microcontroller reference manual, rev. 1 figure 31-5. sync pattern 31.3.4 response the response consists of: ? a data field (described in section 31.3.4.1, data field ) ? a checksum (described in section 31.3.4.3, checksum ) the slave task interested in the data associated with the identifier re ceives the response and verifies the checksum. 31.3.4.1 data field the structure of the data field tran smitted on the lin bus is shown in figure 31-6 . the lsb of the data is sent first and the msb last. the star t bit is encoded as a dominant bit and the stop bit is encoded as a recessive bit. figure 31-6. structure of the data field 31.3.4.2 identifier the identifier, shown in figure 31-7 , consists of two sub-fields: ? the identifier value (in bits 0?5) ? the identifier parity (in bits 6?7) the parity bits p0 and p1 are defined as follows: ? p0 = id0 xor id1 xor id2 xor id4 ? p1 = not(id1 xor id3 xor id4 xor id5) figure 31-7. identifier 31.3.4.3 checksum the checksum contains the inve rted 8-bit sum (with carry) ove r one of two possible groups: start bit stop bit start bit lsb msb stop bit byte field start bit id0 p1 stop bit id1 id2 id3 id4 id5 p0
lin controller (linflexd) 31-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? the classic checksum sums all data bytes, and is used for communication with lin 1.3 slaves. ? the enhanced checksum sums all data bytes and th e identifier, and is used for communication with lin 2.0 (or later) slaves. 31.4 linflexd and software intervention the increasing number of communicat ion peripherals embedde d on microcontrollers (for example, can, lin, spi) requires more and more cpu resources for the communicat ion management. even a 32-bit microcontroller is overloade d if its peripherals do no t provide high level featur es to autonomously handle the communication. even though the lin prot ocol with a maximum baud rate of 20 kbit/s is relatively slow, it still generates a non-negligible load on the cpu if the lin is impl emented on a standard uart, as is usually the case. to minimize the cpu load in master mode, li nflexd handles the lin messages autonomously. in master mode, once the so ftware has triggered the header transm ission, linflexd doe s not request any software (that is, applicat ion) intervention until the next header transmission request in transmission mode or until the checksum r eception in reception mode. to minimize the cpu load in slave mode, linf lexd requires software intervention only to: ? trigger transmission or reception or data discard depending on the identifier ? write data into the buffer (tra nsmission mode) or read data fr om the buffer (reception mode) after checksum reception if filter mode is activated for sl ave mode, linflexd require s software intervention only to write data into the buffer (transmission mode) or read data from the buffer (reception mode) the software uses the control, stat us and configuration registers to: ? configure lin parameters (for example, baud rate or mode) ? request transmissions ? handle receptions ? manage interrupts ? configure lin error and timeout detection ? process diagnostic information the message buffer stores transm itted or received lin frames. 31.5 summary of operating modes the linflexd controller has three operating modes: ? normal ? initialization ?sleep after a hardware reset, the linf lexd controller is in sleep m ode to reduce power consumption.
lin controller (linflexd) freescale semiconductor 31-7 pxs20 microcontroller reference manual, rev. 1 the transitions between th ese modes are shown in figure 31-8 . the software instructs linflexd to enter initialization mode or sleep mode by setting lincr1[init] or lincr1 [sleep], respectively. figure 31-8. linflexd controller operating modes in addition to these controller-level operating mode s, the linflexd controller also supports several protocol-level modes: ? lin mode: ? master mode ? slave mode ? slave mode with identifier filtering ? slave mode with automatic resynchronization ? uart mode ? test modes: ? loop back mode ?self test mode these modes are discussed in de tail in subsequent sections. 31.6 controller-level operating modes 31.6.1 initialization mode the software initialization can be done while the hardware is in initiali zation mode. to enter or exit this mode, the software sets or cl ears lincr1[init], respectively. in initialization mode, all message transfers to and from the lin bus are stopped and the lin bus output (lintx) is recessive. entering initialization mode does not cha nge any of the configuration registers. to initialize the linflexd controller, the software must: sleep initialization normal s l e e p s l e e p * i n i t reset s l e e p l i n r x d o m i n a n t s l e e p * i n i t sl eep * i n i t
lin controller (linflexd) 31-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? select the desired mode (master, slave or uart) ? set up the baud rate register ? if lin slave mode with filter activation is selected, initialize the identifier list 31.6.2 normal mode after initialization is complete, the software must clear lincr1[init] to put the linflexd controller into normal mode. 31.6.3 sleep (low-power) mode to reduce power consumption, linfle xd has a low-power mode called sleep mode. in this mode, the linflexd clock is st opped. consequently, the linfle xd will not update the stat us bits, but software can still access the li nflexd registers. to enter this mode, the software must set lincr1[sleep]. linflexd can be awakened (exit sleep mode) in one of two ways: ? the software clears lincr1[sleep] ? automatic wake-up is enabled (lincr1[awum] is set) and linflexd de tects lin bus activity (that is, if a wakeup pulse of 150 ? s is detected on the lin bus) on lin bus activity detection, hardware automati cally performs the wake-up sequence by clearing lincr1[sleep] if lincr1[a wum] is set. to exit from sleep m ode if lincr1[awum] is cleared, the software must clear lincr1[sleep ] when a wake-up event occurs. 31.7 lin modes 31.7.1 master mode in master mode, the software uses the me ssage buffer to handle the lin messages. master mode is selected when lincr1[mme] is set. 31.7.1.1 lin header transmission according to the lin protocol, a ny communication on the lin bus is triggered by the master sending a header. the header is transmitted by the master task while the data is transmitted by the slave task of a node. to transmit a header with linflexd the application must set up the id entifier, the data field length and configure the message (direction and checksum type) in the bidr regist er before requesting the header transmission by set ting lincr2[htrq].
lin controller (linflexd) freescale semiconductor 31-9 pxs20 microcontroller reference manual, rev. 1 31.7.1.2 data transmission (tr ansceiver as publisher) when the master node is publisher of the data corresponding to the identif ier sent in the header, then the slave task of the master ha s to send the data in the re sponse part of the lin frame . therefore, the software must provide the data to linflexd before requesting the header transmi ssion. the software stores the data in the message buffer bdr. according to the data field length linflexd tran smits the data and the checksum. the software uses the bi dr[ccs] bit to configure the checksu m type (classic or enhanced) for each message. the direction of the message buffer is controlled by th e bidr[dir] bit. when the software sets this bit the response is sent by linflexd (publ isher). clearing this bit configures the message buffer as subscriber. 31.7.1.3 data reception (transceiver as subscriber) to receive data from a slave node, the master sends a header with the corres ponding identifier. linflexd stores the data received from the slave in the messag e buffer and stores the message status in the linsr. 31.7.1.4 error dete ction and handling linflexd is able to detect and handle lin communicat ion errors. a code stored in the lin error status register (linesr) signals the errors to the software. table 31-1 lists the errors detected in ma ster mode and the linflexd contro ller?s response to these errors. 31.7.2 slave mode in slave mode the software uses the me ssage buffer to handle the lin messages. slave mode is selected when the lincr1[mme] is cleared. table 31-1. errors in master mode error description linflexd response to error bit error during transmission, the value read back from the bus differs from the transmitted value ? stops the transmission of the frame after the corrupted bit ? generates an interrupt if linier[beie] is set ? returns to idle state framing error a dominant state has been sampled on the stop bit of the currently received character (sync field, identifier, or data field) if encountered during reception: ? discards the current frame ? generates an interrupt if linier[feie] is set ? returns immediately to idle state checksum error the computed checksum does not match the received checksum if encountered during reception: ? discards the current frame ? generates an interrupt if linier[ceie] is set ? returns to idle state response and frame timeout refer to section 31.12.1, 8-bit timeout counter, for more details
lin controller (linflexd) 31-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 31.7.2.1 data transmission (tr ansceiver as publisher) when linflexd receives the identifier, an rx interrupt is generated. the software must: ? read the received id in the bidr register ? fill the bdr registers ? specify the data field lengt h using the bidr[dfl] field ? trigger the data transmi ssion by setting lincr2[dtrq] one or several identifier filters can be configur ed for transmission by sett ing the dir bits in the corresponding ifcr registers and ac tivated by setting one or severa l bits in the ifer register. when at least one identifier filter is configured in transmission and ac tivated, and if the received id matches the filter, a specific tx interrupt is generated. typically, the software has to copy the data from ram locations to th e bdrl and bdrm registers. to copy the data to the right location, the software has to identify the data by means of the identifier. to avoid this and to ease the access to the ram locations, the linflexd controller provide s a filter match index. this index value is the number of the fi lter which matched the received identifier. the software can use the index in th e ifmi register to dir ectly access the pointer wh ich points to the right data array in the ram area and copy this data to the bdrl and bdrm registers (see figure 31-10 ). using a filter avoids the software having to configure the direction, the data field length and the checksum type in the bdir register. the so ftware fills the bdrl and bdrm registers and triggers the data transmission by set ting lincr2[dtrq]. if linflexd cannot provide enough tx identifier filters to handle all identifiers the software has to transmit data for, then a filter can be configured in mask mode (refer to section 31.7.3, slave mode with identifier filtering ) in order to manage several identifiers with one filter only. 31.7.2.2 data reception (transceiver as subscriber) when linflexd receives the identifier, an rx interrupt is generated. the software must: ? read the received id in the bidr register ? specify the data field length using the bidr[dfl] field before the reception of the stop bit of the first byte of data field when the checksum reception is comp leted, an rx interrupt is generated to allow the software to read the received data in the bdr registers. one or several identifier filters can be configured for reception by cl earing the dir bit in the corresponding ifcr registers and activated by clearing one or several b its in the ifer register. when at least one identifier filter is configured in reception and activated, and if the received id matches the filter, an rx interrupt is genera ted after the checksum reception only. typically, the software has to copy the data from the bdrl and bdrm registers to ram locations. to copy the data to the right location, the software has to identify the data by means of the identifier. to avoid
lin controller (linflexd) freescale semiconductor 31-11 pxs20 microcontroller reference manual, rev. 1 this and to ease the access to the ram locations, the linflexd controller provide s a filter match index. this index value is the number of the fi lter which matched the received identifier. the software can use the index in th e ifmi register to dir ectly access the pointer wh ich points to the right data array in the ram area and c opy this data from the bdrl and bdrm registers to the ram (see figure 31-10 ). using a filter avoids the so ftware reading the id value in the bidr register, and configuring the direction, the data field length and the checks um type in the bidr register. if linflexd cannot provide enough rx identifier filters to handle all identifiers the software has to receive the data for, then a filter can be configured in mask mode (refer to section 31.7.3, slav e mode with identifier filtering ) in order to manage several identifiers with one filter only. 31.7.2.3 data discard when linflexd receives the identifier, an rx interr upt is generated. if the re ceived identifier does not concern the node, the software must set lincr2[ddrq]. linfle xd returns to idle state. 31.7.2.4 error dete ction and handling table 31-2 lists the errors detected in sl ave mode and the linflexd contro ller?s response to these errors. table 31-2. errors in slave mode error description linflexd response to error bit error during transmission, the value read back from the bus differs from the transmitted value ? stops the transmission of the frame after the corrupted bit ? generates an interrupt if linier[beie] is set ? returns to idle state framing error a dominant state has been sampled on the stop bit of the currently received character (sync field, identifier, or data field) if encountered during reception: ? discards the current frame ? generates an interrupt if linier[feie] is set ? returns immediately to idle state checksum error the computed checksum does not match the received checksum if encountered during reception: ? discards the received frame ? generates an interrupt if linier[ceie] is set ? returns to idle state header error an error occurred during header reception (break delimiter error, inconsistent sync field, header timeout) if encountered during header reception, a break field error, an inconsistent sync field, or a timeout: ? discards the header ? generates an interrupt if linier[heie] is set ? returns to idle state
lin controller (linflexd) 31-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 31.7.2.5 valid header a received header is considered as valid when it has been received corr ectly according to the lin protocol. if a valid break field and break delim iter come before the end of the cu rrent header, or at any time during a data field, the current header or data is discarded and the state m achine synchronizes on this new break. 31.7.2.6 valid message a received or transmitted message is considered as valid when the data has been received or transmitted without error according to the lin protocol. 31.7.2.7 overrun after the message buffer is full, th e next valid message reception causes an overrun and a message is lost. the linflexd controller sets linsr[bof] to si gnal the overrun condition. which message is lost depends on the configuration of the rx message buffer: ? if the buffer lock function is di sabled (lincr1[rblm] cleared), th e last message stored in the buffer is overwritten by the new incoming message. in this case, the latest message is always available to the software. ? if the buffer lock function is enabled (lincr1[rblm] set), the most recent message is discarded and the previous message is available in the buffer. 31.7.3 slave mode with identifier filtering in the lin protocol, the identifier of a message is not associated with the address of a node but related to the content of the message. consequently a transmit ter broadcasts its message to all receivers. when a slave node receives a header, it decides - depending on th e identifier value - whethe r the software needs to receive or send a res ponse. if the message does not target the node , it must be discar ded without software intervention. to fulfill this requirement, the linflexd controller provides configurable filt ers in order to request software intervention only if needed. this hardware filtering saves cpu resour ces which would otherwise be needed by software for filtering. the filtering is accomplished through the use of ifcr registers. these registers have the names ifcr0 through ifcr7. this section also uses the nomenclature ifcr 2n and ifcr 2n+1 ; in this nomenclature, n is an integer, and the corresponding ifcr register is calculated using the formula in the subscript. 31.7.3.1 filter submodes usually each of the 16 ifcrs is used to filter one dedicated identifier, but this means that the linflexd controller could filter a maximum of 16 id entifiers. in order to be able to handle more identifiers, the filters can be configured to operate as masks. table 31-3 describes the two avai lable filter submodes.
lin controller (linflexd) freescale semiconductor 31-13 pxs20 microcontroller reference manual, rev. 1 the bit mapping and register organization in these two submodes is shown in figure 31-9 . figure 31-9. filter configuration - register organization 31.7.3.2 identifier filter submode configuration the identifier filters are configured in the ifcr register s. to configure an identifier filter the filter must first be deactivated by clearing th e corresponding bit in the ifer[fact] field. the submode (identifier list or mask) for the corresponding if cr register is confi gured by the ifmr[ifm] field. for each filter, the ifcr register is used to configure: ? the id or mask ? the direction (tx or rx) ? the data field length ? the checksum type if no filter is active, an rx interrupt is generated on any received identifier event. table 31-3. filter submodes submode description identifier list both filter registers are used as identifier registers. all bits of the incoming identifier must match the bits specified in the filter register. this is the default submode for the linflexd controller. mask the identifier registers are associ ated with mask registers specifying which bits of the identifier are handl ed as ?must match? or as ?don?t care?. ifcr x identifier id bit mapping identifier filter re gister organization ccs dir identifier filter configuration ifcr 2n identifier identifier ifcr 2n+1 ifm = 0 identifier filter submode ifcr 2n identifier mask ifcr 2n+1 ifm = 1 identifier list submode mask submode dfl
lin controller (linflexd) 31-14 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 if at least one active filter is conf igured as tx, all received identifiers matching this filter generate a tx interrupt. if at least one active filter is conf igured as rx, all received identifiers matching this filter generate an rx interrupt. if no active filter is configured as rx, all received identi fiers not matching tx filter(s) generate an rx interrupt. further details are provided in table 31-4 and figure 31-10 . figure 31-10. identifier match index 31.7.4 slave mode with automatic resynchronization automatic resynchronization must be enabled in slave mode if f ipg_clock_lin tolerance is greater than 1.5%. this feature compensates a f ipg_clock_lin deviation up to 14%, as spec ified in the lin standard. table 31-4. filter to interrupt vector correlation number of active filters number of active filters configured as tx number of active filters configured as rx interrupt vector 0 0 0 - rx interrupt on all ids a (a > 0) a 0 - tx interrupt on ids matching the filters, - rx interrupt on all other ids if bf bit is set, no rx interrupt if bf bit is reset n (n = a + b) a (a > 0) b (b > 0) - tx interrupt on ids matching the tx filters, - rx interrupt on ids matching the rx filters, - all other ids discarded (no interrupt) b (b > 0) 0 b - rx interrupt on ids matching the filters, - tx interrupt on all other ids if bf bit is set, no tx interrupt if bf bit is reset ifmi message0 message1 message2 data pointers table ram @ +
lin controller (linflexd) freescale semiconductor 31-15 pxs20 microcontroller reference manual, rev. 1 this mode is similar to sl ave mode as described in section 31.7.2, slave mode, with the addition of automatic resynchroni zation enabled by the lincr1[lase] bit. in this mode linflexd adjusts the fractional baud rate generator af ter each synch field reception. 31.7.4.1 automatic resynchronization method when automatic resynchronization is enabled, after each lin break, the time dura tion between five falling edges on rdi is sampled on f ipg_clock_lin as shown in figure 31-11 . then the lfdiv value (and its associated linibrr and linfbrr re gisters) are automatically updated at the end of the fifth falling edge. during lin sync field meas urement, the linflexd state machine is stopped and no data is transferred to the data register. figure 31-11. lin sync field measurement lfdiv is an unsigned fixed point number. the mantissa is coded on 20 bi ts in the linibrr register and the fraction is coded on 4 bits in the linfbrr register. if lincr1[lase] is set, lfdiv is automatical ly updated at the end of each lin sync field. three registers are used internally to manage the auto-update of the linflexd divider (lfdiv): ? lfdiv_nom (nominal value written by soft ware at linibrr a nd linfbrr addresses) ? lfdiv_meas (results of the field synch measurement) ? lfdiv (used to genera te the local baud rate) on transition to idle, break or break delimiter state due to any error or on rece ption of a complete frame, hardware reloads lfdiv with lfdiv_nom. 31.7.4.2 deviation error on the sync field the deviation error is checke d by comparing the current baud rate (relative to the slave oscillator) with the received lin sync field (relative to the master os cillator). two checks are performed in parallel. the first check is based on a measurement between the fi rst falling edge and the last falling edge of the sync field: lin break break bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit lin sync field lfdiv(n) lfdiv(n+1) t br = baud rate period t br delim. t ipg_clock_in = clock period t br =16.lfdiv.t ipg_clock_in measurement = 8.t br lfdiv = tbr/(16.t ipg_clock_lin )
lin controller (linflexd) 31-16 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? if d1 > 14.84%, lhe is set. ? if d1 < 14.06%, lhe is not set. ? if 14.06% < d1 < 14.84%, lhe can be either set or reset depending on th e dephasing between the signal on linflexd_rx pin the f ipg_clock_lin clock. the second check is based on a meas urement of time between each fa lling edge of the sync field: ? if d2 > 18.75%, lhe is set. ? if d2 < 15.62%, lhe is not set. ? if 15.62% < d2 < 18.75%, lhe can be either set or reset depending on th e dephasing between the signal on linflexd_rx pin the f ipg_clock_lin clock. note that the linflexd does not need to check if th e next edge occurs slower than expected. this is covered by the check for deviation error on the full synch byte. 31.8 test modes the linflexd controller includes two test modes, loop back mode and self test mode. they can be selected by the lbkm and sftm bits in the lincr1 register. these bits must be configured while linflexd is in initialization mode. after one of the two test modes has been se lected, linflexd must be started in normal mode. 31.8.1 loop back mode linflexd can be put in loop back mode by setting lincr1[lbkm]. in loop back mode, the linflexd treats its own transmitted messages as r eceived messages. this is illustrated in figure 31-12 . figure 31-12. linflexd in loop back mode this mode is provided for self-test functions. to be independe nt of external events , the lin core ignores the linrx signal. in this mode, the linflexd performs an internal fee dback from its tx output to its rx input. the actual value of the linr x input pin is disregarded by the linflexd. the transmitted messages can be monitored on the lintx pin. 31.8.2 self test mode linflexd can be put in self te st mode by setting linc r1[lbkm] and lincr1[s ftm]. this mode can be used for a ?hot self test?, me aning the linflexd can be tested as in loop back mode but without lintx linrx linflexd tx rx
lin controller (linflexd) freescale semiconductor 31-17 pxs20 microcontroller reference manual, rev. 1 affecting a running lin syst em connected to the lintx and linrx pins. in this mode, the linrx pin is disconnected from the li nflexd and the lintx pin is held recessive. th is is illustrated in figure 31-13 . figure 31-13. linflexd in self test mode 31.9 uart mode the main features of uart mode are presented in section 31.2.2, uart mode features . 31.9.1 data frame structure 31.9.1.1 8-bit data frame the 8-bit uart data frame is shown in figure 31-14 . the 8th bit can be a data or a parity bit. parity (even, odd, 0, or 1) can be selected by the uartcr[pc] field. an even parity is set if the modulo-2 sum of the 7 data bits is 1. an odd parity is cleared in this case. figure 31-14. uart mode 8-bit data frame 31.9.1.2 9-bit data frame the 9-bit uart data frame is shown in figure 31-15 . the 9th bit is a parity bit. parity (even, odd, 0, or 1) can be selected by the by the uartcr[ pc] field. an even parity is set if the modulo-2 su m of the 8 data bits is 1. an odd parity is cleared in this case. parity 0 forces a zero logical valu e. parity 1 forces a high logical value. linflexd lintx linrx tx rx =1 start bit d0 d7 stop bit byte field - data bit - parity bit d1 d2 d3 d4 d5 d6
lin controller (linflexd) 31-18 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 31-15. uart mode 9-bit data frame 31.9.1.3 16-bit data frame the 16-bit uart data frame is shown in figure 31-16 . the 16th bit can be a data or a parity bit. parity (even, odd, 0, or 1) can be selected by the uartcr[pc] field. pa rity 0 forces a zero logical value. parity 1 forces a high logical value. figure 31-16. uart mode 16-bit data frame 31.9.1.4 17-bit data frame the 17-bit uart data frame is shown in figure 31-17 . the 17th bit is the parity bit. parity (even, odd, 0, or 1) can be selected by the uartcr [pc] field. parity 0 forces a zero l ogical value. parity 1 forces a high logical value. figure 31-17. uart mode 17-bit data frame 31.9.2 buffer the 8-byte buffer is divided into two parts ? one fo r receiver and one for tran smitter ? as shown in table 31-5 . start bit d0 d7 stop bit byte field - parity bit d1 d2 d3 d4 d5 d6 d8 start bit d0 d15 stop bit byte field - data bit - parity bit d1 d2 ... ... d13 d14 start bit d0 d16 stop bit byte field - parity bit d1 d2 ... d13 d14 d15
lin controller (linflexd) freescale semiconductor 31-19 pxs20 microcontroller reference manual, rev. 1 for 16-bit frames, the lower 8 bits will be written in bdr0 and the upper 8 bits will be written in bdr1. 31.9.3 uart transmitter in order to start transmission in uart mode, th e uartcr[uart] and uartcr [txen] bits must be set. transmission starts when bdr0 (least significa nt data byte) is programmed. the number of bytes transmitted is equal to the value confi gured by the uartcr[tdfltfc] field (see table 31-17 ). the transmit buffer size is as follows: ? 4 bytes when uartcr[wl1] = 0 ? 2 half-words when uartcr[wl1] = 1 therefore, the maximum transmission that can be triggered is 4 bytes (2 half-words). after the programmed number of bytes has be en transmitted, the uartsr[dtftff] flag is set. if the uartcr[txen] field is cleared dur ing a transmission, the current tr ansmission is completed, but no further transmission can be invoked. the buffer can be configured in fifo mode (mandatory when dma tx is enabled) by setting uartcr[tfbm]. the access to the bdrl register is shown in table 31-6 . table 31-5. uart buffer structure bdr uart mode 0tx0 1tx1 2tx2 3tx3 4rx0 5rx1 6rx2 7rx3 table 31-6. bdrl access in uart mode access mode 1 word length 2 ips operation result write byte0 fifo byte ok write byte1-2-3 fifo byte ips transfer error write half-word0-1 fifo byte ips transfer error write word fifo byte ips transfer error write byte0-1-2-3 fifo half-word ips transfer error write half-word0 fifo half-word ok write half-word1 fifo half-word ips transfer error write word fifo half-word ips transfer error read byte0-1-2-3 fifo byte/ half-word ips transfer error
lin controller (linflexd) 31-20 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 31.9.4 uart receiver reception of a data byte is star ted as soon as the software comple tes the following tasks in order: 1. exits initialization mode 2. sets the uartcr[rxen] field 3. detects the start bit there is a dedicated data buffer for recei ved data bytes. its size is as follows: ? 4 bytes when uartcr[wl1] = 0 ? 2 half-words when uartcr[wl1] = 1 after the programmed number (rdfl bits) of bytes has been receive d, the uartsr[drfrfe] field is set. if the uartcr[rxen] field is cleared during a reception, the current recep tion is completed, but no further reception can be invoked unt il uartcr[rxen] is set again. the buffer can be configured in fifo mode (r equired when dma rx is enabled) by setting uartcr[rfbm]. the access to the bdrm register is shown in table 31-7 . read half-word0-1 fifo byte/half-word ips transfer error read word fifo byte/half-word ips transfer error write byte0-1-2-3 buffer byte/half-word ok write half-word0-1 buffer byte/half-word ok write word buffer byte/half-word ok read byte0-1-2-3 buffer byte/half-word ok read half-word0-1 buffer byte/half-word ok read word buffer byte/half-word ok notes: 1 as specified by uartcr[tfbm] 2 as specified by the wl1 and wl0 bi ts of the uartcr register. in uart fifo mode (uartcr[tfbm] = 1),any read operation causes an ips transfer error. table 31-7. bdrm access in uart mode access mode 1 word length 2 ips operation result read byte4 fifo byte ok read byte5-6-7 fifo byte ips transfer error read half-word2-3 fifo byte ips transfer error read word fifo byte ips transfer error read byte4-5-6-7 fifo half-word ips transfer error table 31-6. bdrl access in uart mode (continued) access mode 1 word length 2 ips operation result
lin controller (linflexd) freescale semiconductor 31-21 pxs20 microcontroller reference manual, rev. 1 table 31-8 lists some common scenarios, controller re sponses, and suggestions when the linflexd controller is acting as a uart receiver. read half-word2 fifo half-word ok read half-word3 fifo half-word ips transfer error read word fifo half-word ips transfer error write byte4-5-6-7 fifo byte/ half-word ips transfer error write half-word2-3 fifo byte/half-word ips transfer error write word fifo byte/half-word ips transfer error read byte4-5-6-7 buffer byte/half-word ok read half-word2-3 buffer byte/half-word ok read word buffer byte/half-word ok write byte4-5-6-7 buffer byte/ half-word ips transfer error write half-word2-3 buffer byte/half-word ips transfer error write word buffer byte/half-word ips transfer error notes: 1 as specified by uartcr[rfbm] 2 as specified by the wl1 and w l0 bits of the uartcr register table 31-8. uart receiver scenarios scenario responses and suggestions the software does not know (in advance) how many bytes will be received. do not program uartcr[rdflrfc] in advance. when this field is zero (as it is af ter reset), reception occurs on a byte-by-byte basis. therefore, the state machine will move to idle state after each byte is received. uartcr[rdflrfc] is programmed for a certain number of bytes received, but the actual number of bytes received is smaller. the reception will hang. in this case, the software must monitor the uartsr[to] field, and move to idle state by setting lincr1[sleep]. table 31-7. bdrm access in uart mode (continued) access mode 1 word length 2 ips operation result
lin controller (linflexd) 31-22 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 31.10 memory map and register description table 31-9 shows the linflexd memory/register map. see the device memory map for the base address. a stop request arrives before the reception is completed. the request is acknowledged only after the programmed number of data bytes are received. in other words, the stop request is not serviced immediately. in this case, the software must monitor the uartsr[to] field and move the state machine to idle state as appropriate. the stop request will be serviced only after this is complete. a parity error occurs during the reception of a byte. the corresponding uartsr[pe n ] field is set. no interrupt is generated. a framing error occurs during the reception of a byte. ? uartsr[fe] is set. ? if linier[feie] = 1, an interrupt is generated. this interrupt is helpful in identifying which byte has the framing error, since there is only one register bit for framing errors. a new byte has been received, but the last received frame has not been read from the bu ffer (uartsr[rmb] has not yet been cleared by the software) ? an overrun error will occur (uartsr[bof] will be set). ? one message will be lost (depending on the setting of lincr[rblm]). ? an interrupt is generated if linier[boie] is set. table 31-9. linflexd memory map address offset register description location 0x00 lin control register 1 (lincr1) on page 31-23 0x04 lin interrupt enable register (linier) on page 31-26 0x08 lin status register (linsr) on page 31-28 0x0c lin error status register (linesr) on page 31-31 0x10 uart mode control register (uartcr) on page 31-32 0x14 uart mode status register (uartsr) on page 31-35 0x18 lin timeout control status register (lintcsr) on page 31-37 0x1c lin output compar e register (linocr) on page 31-38 0x20 lin timeout control register (lintocr) on page 31-39 0x24 lin fractional baud rate register (linfbrr) on page 31-40 0x28 lin integer baud rate register (linibrr) on page 31-40 0x2c lin checksum field register (lincfr) on page 31-41 0x30 lin control register 2 (lincr2) on page 31-42 0x34 buffer identifier register (bidr) on page 31-43 0x38 buffer data register least significant (bdrl) on page 31-44 0x3c buffer data register most significant (bdrm) on page 31-45 0x40 identifier filter enable register (ifer) on page 31-46 table 31-8. uart receiver scenarios (continued) scenario responses and suggestions
lin controller (linflexd) freescale semiconductor 31-23 pxs20 microcontroller reference manual, rev. 1 31.10.1 lin control register 1 (lincr1) 0x44 identifier filter match index (ifmi) on page 31-47 0x48 identifier filter mode register (ifmr) on page 31-48 0x4c?0x88 identifier filt er control register s 0?15 (ifcr0?ifcr15) on page 31-48 0x8c global control register (gcr) on page 31-49 0x90 uart preset timeout register (uartpto) on page 31-51 0x94 uart current timeout register (uartcto) on page 31-51 0x98 dma tx enable register (dmatxe) on page 31-52 0x9c dma rx enable register (dmarxe) on page 31-53 offset:0x00 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ccd 1 cfd 1 lase 1 awum 1 mbl 1 bf 1 sft m 1 lbkm 1 mme 1 sbdt 1 rblm 1 sleep init w reset000000001000/1 2 0010 1 these fields are writable only in initialization mode (lincr1[init] = 1). 2 resets to 0 in slave mode and to 1 in master mode figure 31-18. lin control register 1 (lincr1) table 31-10. lincr1 field descriptions field description ccd checksum calculation disable this bit is used to disable the checksum calculation (see ta b l e 3 1 - 1 1 ). 0: checksum calculation is done by hardware. when th is bit is reset the lincfr register is read-only. 1: checksum calculation is disabled. when this bit is set the lincfr register is read/write. user can program this register to send a software calculated crc (provided cfd is reset). note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. table 31-9. linflexd memory map (continued) address offset register description location
lin controller (linflexd) 31-24 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 cfd checksum field disable this bit is used to disable the checksum field transmission (see table 31-11 ). 0: checksum field is sent after the required number of data bytes is sent. 1: no checksum field is sent. note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. lase lin slave automatic resynchronization enable 0: automatic resynch ronization disable 1: automatic resynchronization enable note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. awum automatic wake-up mode this bit controls the behavior of the linflexd hardware during sleep mode. 0: the sleep mode is exited on software reques t by clearing the sleep bit of the lincr register. 1: the sleep mode is exited automatically by ha rdware on rx dominant state detection. the sleep bit of the lincr register is cleared by hardware whenever wuf bit in linsr is set. note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. mbl lin master break length these bits indicate the break length in master mode (see table 31-12 ). note: these bits can be written in initialization mode only. they are read-only in normal or sleep mode. bf bypass filter 0: no interrupt if id does not match any filter 1: an rx interrupt is generated on id not matching any filter notes: ? if no filter is activate d, this bit is reserved. ? this bit can be written in initialization mode only. it is read-only in normal or sleep mode. sftm self test mode this bit controls the self test mode . for more details please refer to section 31.8.2, self test mode . 0: self test mode disable 1: self test mode enable note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. lbkm loop back mode this bit controls the loop back mode. for more details please refer to section 31.8.1, loop back mode . 0: loop back mode disable 1: loop back mode enable note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode mme master mode enable 0: slave mode enable 1: master mode enable note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. sbdt slave mode break detection threshold 0: 11-bit break 1: 10-bit break note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. table 31-10. lincr1 field descriptions (continued) field description
lin controller (linflexd) freescale semiconductor 31-25 pxs20 microcontroller reference manual, rev. 1 rblm receive buffer locked mode 0: receive buffer not locked on overrun. once the slave receive buffer is full the next incoming message overwrites the previous one. 1: receive buffer locked against overrun. once the receive buffer is full the next incoming message is discarded. note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. sleep sleep mode request this bit is set by software to request linflexd to enter sleep mode. this bit is cleared by software to exit sleep mode or by hardware if the awum bit in lincr1 and the wuf bit in linsr are set (see table 31-13 ). init initialization request the software sets this bit to switch hardware into in itialization mode. if the sl eep bit is reset, linflexd enters normal mode when clearing the init bit (see ta b l e 3 1 - 1 3 ). table 31-11. checksum bits configuration cfd ccd lincfr checksum sent 1 1 read/write none 1 0 read-only none 0 1 read/write programmed in lincfr by bits cf[0:7] 0 0 read-only hardware calculated table 31-12. lin master break length selection mbl length 0000 10-bit 0001 11-bit 0010 12-bit 0011 13-bit 0100 14-bit 0101 15-bit 0110 16-bit 0111 17-bit 1000 18-bit 1001 19-bit 1010 20-bit 1011 21-bit 1100 22-bit 1101 23-bit 1110 36-bit table 31-10. lincr1 field descriptions (continued) field description
lin controller (linflexd) 31-26 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 31.10.2 lin interrupt en able register (linier) 1111 50-bit table 31-13. operating mode selection sleep init operating mode 1 0 sleep (reset value) x 1 initialization 00normal offset: 0x04 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r szie ocie beie ceie heie 0 0 feie boie lsie wuie dbfie dbeietoie drie dtie hrie w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 31-19. lin interrupt enable register (linier) table 31-14. linier field descriptions field description szie stuck at zero interrupt enable 0: no interrupt when szf bit in linesr or uartsr is set 1: interrupt generated when szf bit in linesr or uartsr is set ocie output compare interrupt enable 0: no interrupt when ocf bit in linesr or uartsr is set 1: interrupt generated when ocf bit in linesr or uartsr is set beie bit error interrupt enable 0: no interrupt when bef bit in linesr is set 1: interrupt generated when bef bit in linesr is set ceie checksum error interrupt enable 0: no interrupt on checksum error 1: interrupt generated when checksum error flag (cef) is set in linesr table 31-12. lin master break length selection (continued) mbl length
lin controller (linflexd) freescale semiconductor 31-27 pxs20 microcontroller reference manual, rev. 1 heie header error interrupt enable 0: no interrupt on break delimiter error, synch field error, id field error 1: interrupt generated on break delimiter error, synch field error, id field error feie framing error interrupt enable 0: no interrupt on framing error 1: interrupt generated on framing error boie buffer overrun interrupt enable 0: no interrupt on buffer overrun 1: interrupt generated on buffer overrun lsie lin state interrupt enable 0: no interrupt on lin state change 1: interrupt generated on lin state change this interrupt can be used for debugging purposes. it has no status flag but is reset when writing ?1111? into the lin state bits in the linsr register. wuie wake-up interrupt enable 0: no interrupt when wuf bit in linsr or uartsr is set 1: interrupt generated when wuf bit in linsr or uartsr is set dbfie data buffer full interrupt enable 0: no interrupt when buffer data register is full 1: interrupt generated when data buffer register is full dbeietoie data buffer empty interrupt enable / timeout interrupt enable 0: no interrupt when buffer data register is empty 1: interrupt generated when data buffer register is empty note: an interrupt is generated if this bit is set and one of the following is true: linflexd is in lin mode and linsr[dbef] is set linflexd is in uart mode and uartsr[to] is set drie data reception complete interrupt enable 0: no interrupt when data reception is completed 1: interrupt generated when data received flag (drf) in linsr or uartsr is set dtie data transmitted interrupt enable 0: no interrupt when data transmission is completed 1: interrupt generated when data transmitted flag (dtf) is set in linsr or uartsr register hrie header received interrupt enable 0: no interrupt when a valid lin header has been received 1: interrupt generated when a valid lin header has been received, that is, hrf bit in linsr register is set table 31-14. linier field descriptions (continued) field description
lin controller (linflexd) 31-28 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 31.10.3 lin status register (linsr) offset: 0x08 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r lins 00rmb0 rbsy rps wuf dbff dbef drf dtf hrf ww1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000001000000 figure 31-20. lin status register (linsr)
lin controller (linflexd) freescale semiconductor 31-29 pxs20 microcontroller reference manual, rev. 1 table 31-15. linsr field descriptions field description lins lin state lin mode states description 0000: sleep mode linflexd is in sleep mode to save power consumption. 0001: initialization mode linflexd is in initialization mode. 0010: idle this state is entered on several events: ? sleep bit and init in lincr1 register have been cleared by software, ? a falling edge has been received on rx pin and awum bit is set, ? the previous frame reception or transmission has been completed or aborted. 0011: break in slave mode, a falling edge followed by a dominant state has been detected. receiving break. note: in slave mode, in case of error new lin state can be either idle or break depending on last bit state. if last bit is dominant new lin state is break, otherwise idle. in master mode, break transmission ongoing. 0100: break delimiter in slave mode, a valid break has been detected. refer to lincr1 register for break length configuration (10-bit or 11-bit). waiting for a rising edge. in master mode, break transmission has been completed. break delimiter transmission is ongoing. 0101: synch field in slave mode, a valid break delimiter has been detected (recessive state for at least one bit time). receiving synch field. in master mode, synch field transmission is ongoing. 0110: identifier field in slave mode, a valid synch field has been received. receiving id field. in master mode, identifier transmission is ongoing. 0111: header reception/transmission completed in slave mode, a valid header has been received and i dentifier field is available in the bidr register. in master mode, header transmission is completed. 1000: data reception/transmission response reception/transmission is ongoing. 1001: checksum data reception/transmission completed. checksum reception/transmission ongoing. in uart mode, only the following stat es are flagged by the lin state bits: ?init ? sleep ?idle ? data transmission/reception rmb release message buffer 0: buffer is free 1: buffer ready to be read by software. this bit must be cleared by software after reading data received in the buffer. this bit is cleared by hardware in initialization mode. rbsy receiver busy flag 0: receiver is idle 1: reception ongoing note: in slave mode, after header reception, if dir bi t in bidr is reset and reception starts then this bit is set. in this case, user cannot set dtrq bit in lincr2. rps lin receive pin state this bit reflects the current status of linrx pin for diagnostic purposes.
lin controller (linflexd) 31-30 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 wuf wake-up flag this bit is set by hardware and indicates to the software that linflexd has detected a falling edge on the linrx pin when ? slave is in sleep mode, ? master is in sleep mode or idle state. this bit must be cleared by software. it is reset by hardware in initialization mode. an interrupt is generated if wuie bit in linier is set. dbff data buffer full flag this bit is set by hardware and indicates the buffer is full. it is set only when receiving extended frames (dfl > 7). this bit must be cleared by software. it is reset by hardware in initialization mode. dbef data buffer empty flag this bit is set by hardware and indicates the buffer is empty. it is set only when transmitting extended frames (dfl > 7). this bit must be cleared by software, once buffer has been filled again, in order to start transmission. this bit is reset by hardwa re in initialization mode. drf data reception completed flag this bit is set by hardware and indica tes the data reception is completed. this bit must be cleared by software. it is reset by hardware in initialization mode. note: this flag is not set in case of bit error or framing error. dtf data transmission completed flag this bit is set by hardware and indicates the data transmission is completed. this bit must be cleared by software. it is reset by hardware in initialization mode. note: this flag is not set in case of bit error if iobe bit is reset. hrf header reception flag this bit is set by hardware and indicates a valid header reception is completed. this bit must be cleared by software. this bit is reset by hardware in initialization mode and at end of completed or aborted frame. note: if filters are enabled, this bit is set only when identifier software filtering is required, that is to say: ? all filters are inactive and bf bit in lincr1 is set ? no match in any filter and bf bit in lincr1 is set ? tx filter match table 31-15. linsr field descriptions (continued) field description
lin controller (linflexd) freescale semiconductor 31-31 pxs20 microcontroller reference manual, rev. 1 31.10.4 lin error status register (linesr) offset: 0x0c access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r szf ocf bef cef sfef bdef idpef fef bof 0 0 0 000nf w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 31-21. lin error status register (linesr) table 31-16. linesr field descriptions field description szf stuck at zero flag this bit is set by hardware when the bus is dominant for more than a 100-bit time. it is cleared by software. ocf output compare flag 0: no output compare event occurred 1: the content of the counter has matched the conten t of oc1[0:7] or oc2[0:7] in linocr. if this bit is set and iot bit in lintcsr is set, linflexd moves to idle state. if ltom bit in lintcsr register is set then ocf is reset by hardware in initialization mode. if ltom bit is reset, then ocf maintains it s status whatever the mode is. bef bit error flag this bit is set by hardware and indicates to the soft ware that linflexd has detected a bit error. this error can occur during response field transmission (slave and master modes) or during header transmission (in master mode). this bit is cleared by software. cef checksum error flag this bit is set by hardware and indicates that th e received checksum does not match the hardware calculated checksum. this bit is cleared by software. note: this bit is never set if ccd or cfd bit in lincr1 register is set. sfef synch field error flag this bit is set by hardware and indicates that a sy nch field error occurred (inconsistent synch field). bdef break delimiter error flag this bit is set by hardware and indicates that the received break delimiter is too short (less than one bit time). idpef identifier parity error flag this bit is set by hardware and indicates that a identifier parity error occurred. note: header interrupt is triggered when sfef or bd ef or idpef bit is set and heie bit in linier is set.
lin controller (linflexd) 31-32 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 31.10.5 uart mode cont rol register (uartcr) fef framing error flag this bit is set by hardware and indicates to the so ftware that linflexd has detected a framing error (invalid stop bit). this error can occur during rec eption of any data in the response field (master or slave mode) or during reception of synch field or identifier field in slave mode. bof buffer overrun flag this bit is set by hardware when a new data byte is received and the buffer full flag is not cleared. if rblm in lincr1 is set then the new byte received is discarded. if rblm is reset then the new byte overwrites the buffer. it can be cleared by software. nf noise flag this bit is set by hardware when noise is detected on a received character. this bit is cleared by software. offset: 0x10 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tdfltfc 1 rdflrfc 1 rfbm tfbm 2 wl[1] 2 pc1 2 rxen txen pc0 2 pce 2 wl[0] 2 uart 2 w reset0000000000000000 1 these fields are read/write in uart bu ffer mode and read-only in other modes. 2 these fields are writable only in initialization mode (l incr1[init] = 1). figure 31-22. uart mode control register (uartcr) table 31-16. linesr field descriptions (continued) field description
lin controller (linflexd) freescale semiconductor 31-33 pxs20 microcontroller reference manual, rev. 1 table 31-17. uartcr field descriptions field description tdfltfc transmitter data fiel d length / tx fifo counter this field has one of two functions depending on the mode of operation as follows: ? when linflexd is in uart buffer mode (tfbm = 0), tdfltfc defines the number of bytes to be transmitted. the field is read/write in this co nfiguration. the first bit is reserved and not implemented. the permissible values are as follows (with x representing the unimplemented first bit): 0bx00: 1 byte 0bx01: 2 bytes 0bx10: 3 bytes 0bx11: 4 bytes when the uart data length is configured as ha lf-word (wl = 0b10 or 0b11), the only valid values for tdfltfc are 0b001 and 0b011. ? when linflexd is in uart fifo mode (tfb m = 1), tdfltfc contains the number of entries (bytes) of the tx fifo. the field is read-only in this configuration. the permissible values are as follows: 0b000: empty 0b001: 1 byte 0b010: 2 bytes 0b011: 3 bytes 0b100: 4 bytes all other values are reserved. this field is meaningful and can be programmed only when the uart bit is set. rdflrfc receiver data field length / rx fifo counter this field has one of two functions depending on the mode of operation as follows: ? when linflexd is in uart buffer mode (rfbm = 0), rdflrfc defines the number of bytes to be received. the field is read/write in this configur ation. the first bit is reserved and not implemented. the permissible values are as follows (with x representing the unimplemented first bit): 0bx00: 1 byte 0bx01: 2 bytes 0bx10: 3 bytes 0bx11: 4 bytes when the uart data length is configured as ha lf-word (wl = 0b10 or 0b11), the only valid values for rdflrfc are 0b001 and 0b011. ? when linflexd is in uart fifo mode (rfb m = 1), rdflrfc contains the number of entries (bytes) of the rx fifo. the field is read-only in this configuration. the permissible values are as follows: 0b000: empty 0b001: 1 byte 0b010: 2 bytes 0b011: 3 bytes 0b100: 4 bytes all other values are reserved. this field is meaningful and can be programmed only when the uart bit is set. rfbm rx fifo/buffer mode 0 rx buffer mode enabled 1 rx fifo mode enabled (mandatory in dma rx mode) this field can be programmed in initialization mode only when the uart bit is set.
lin controller (linflexd) 31-34 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 tfbm tx fifo/buffer mode 0 tx buffer mode enabled 1 tx fifo mode enabled (mandatory in dma tx mode) this field can be programmed in initialization mode only when the uart bit is set. rxen receiver enable 0: receiver disabled 1: receiver enabled this field can be programmed only when the uart bit is set. txen transmitter enable 0: transmitter disabled 1: transmitter enabled this field can be programmed only when the uart bit is set. note: transmission starts when this bit is set and when writing data0 in the bdrl register. pc parity control 00 parity sent is even 01 parity sent is odd 10 a logical 0 is always transmitted/checked as parity bit 11 a logical 1 is always transmitted/checked as parity bit this field can be programmed in initialization mode only when the uart bit is set. pce parity control enable 0: parity transmit/check disabled 1: parity transmit/check enabled this field can be programmed in initialization mode only when the uart bit is set. wl word length in uart mode 00 7 bits data + parity 01 8 bits data when pce = 0 or 8 bits data + parity when pce = 1 10 15 bits data + parity 11 16 bits data when pce = 0 or 16 bits data + parity when pce = 1 this field can be programmed in initialization mode only when the uart bit is set. uart uart mode enable 0: lin mode 1: uart mode this field can be programmed in initialization mode only. table 31-17. uartcr field descriptions (continued) field description
lin controller (linflexd) freescale semiconductor 31-35 pxs20 microcontroller reference manual, rev. 1 31.10.6 uart mode status register (uartsr) offset: 0x14 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r szf ocf pe3 pe2 pe1 pe0 rmb fef bof rps wuf 0 to drfrfe dtftff nf w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 31-23. uart mode status register (uartsr) table 31-18. uartsr field descriptions field description szf stuck at zero flag this bit is set by hardware when the bus is dominant for more than a 100-bit time. it is cleared by software. ocf ocf output compare flag 0: no output compare event occurred 1: the content of the counter has matched the content of oc1[0:7] or oc2[0:7] in linocr. an interrupt is generated if the ocie bit in linier register is set. pe3 parity error flag rx3 this bit indicates if there is a parity error in the corresponding received byte (rx3). no interrupt is generated if this error occurs. 0: no parity error 1: parity error pe2 parity error flag rx2 this bit indicates if there is a parity error in the corresponding received byte (rx2). no interrupt is generated if this error occurs. 0: no parity error 1: parity error pe1 parity error flag rx1 this bit indicates if there is a parity error in the corresponding received byte (rx1). no interrupt is generated if this error occurs. 0: no parity error 1: parity error pe0 parity error flag rx0 this bit indicates if there is a parity error in the corresponding received byte (rx0). no interrupt is generated if this error occurs. 0: no parity error 1: parity error
lin controller (linflexd) 31-36 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 rmb release message buffer 0: buffer is free 1: buffer ready to be read by software. this bit must be cleared by software after reading data received in the buffer. this bit is cleared by hardware in initialization mode. fef framing error flag this bit is set by hardware and indicates to the so ftware that linflexd has detected a framing error (invalid stop bit). bof fifo/buffer overrun flag this bit is set by hardware when a new data byte is received and the rmb bit is not cleared in uart buffer mode. in uart fifo mode, this bit is set wh en there is a new byte and the rx fifo is full. in uart fifo mode, once rx fifo is full, the new received message is discarded regardless of the value of lincr1[rblm]. if lincr1[rblm] = 1, the new by te received is discarded. if lincr1[rblm] = 0, the new byte overwrites buffer. this field can be cleared by writing a 1 to it. an interrupt is generated if linier[boie] is set. rps lin receive pin state this bit reflects the current status of linrx pin for diagnostic purposes. wuf wake-up flag this bit is set by hardware and indicates to the software that linflexd has detected a falling edge on the linrx pin in sleep mode. this bit must be cleared by software. it is reset by hardware in initialization mode. an interrupt i generated if wuie bit in linier is set. to timeout the linflexd controller sets this field when a ua rt timeout occurs ? that is, when the value of uartcto becomes equal to the preset value of the timeout (uartpto register setting). this field should be cleared by software. the gcr[sr] field should be used to reset the receiver fsm to idle state in case of uart timeout for uart recepti on depending on the application both in buffer and fifo mode. an interrupt is generated when linier[dbeietoie] is set on the error interrupt line in uart mode. drfrfe data reception completed flag / rx fifo empty flag the linflexd controller sets this field as follows: ? in uart buffer mode (rfbm = 0), it indicates that the num ber of bytes programmed in rdfl has been received. this field should be cleared by soft ware. an interrupt is gene rated if linier[drie] is set. this field is set in case of framing error, parity error, or overrun. this field reflects the same value as in linesr when in initialization mode and uart bit is set. ? in uart fifo mode (rfbm = 1), it indicates that t he rx fifo is empty. this field is a read-only field used internally by the dma rx interface. dtftff data transmission completed flag / tx fifo full flag the linflexd controller sets this field as follows: ? in uart buffer mode (tfbm = 0), it indicates th at the data transmission is completed. this field should be cleared by software. an interrupt is generat ed if linier[dtie] is set. this field reflects the same value as in linesr when in initialization mode and uart bit is set. ? in uart fifo mode (tfbm = 1), it indicates that the tx fifo is full. this field is a read-only field used internally by the dma tx interface. nf noise flag this bit is set by hardware when noise is detected on a received character. this bit is cleared by software. table 31-18. uartsr field descriptions (continued) field description
lin controller (linflexd) freescale semiconductor 31-37 pxs20 microcontroller reference manual, rev. 1 31.10.7 lin timeout control status register (lintcsr) offset: 0x18 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 0 lto m 1 iot 1 toce 1 cnt w w1c w1c w1c reset0000001000000000 1 these fields are writable only in initialization mode (l incr1[init] = 1). figure 31-24. lin timeout control status register (lintcsr) table 31-19. lintcsr field descriptions name description ltom lin timeout mode 0: lin timeout mode (header, res ponse and frame timeout detection) 1: output compare mode this bit can be set/cleared in initialization mode only. iot idle on timeout 0: lin state machine not reset to idle on timeout event 1: lin state machine reset to idle on timeout event this bit can be set/cleared in initialization mode only. toce timeout counter enable 0: timeout counter disable. ocf bit in linesr or uartsr is not set on an output compare event. 1: timeout counter enable. ocf bit is se t if an output compare event occurs. toce bit is configurable by software in initialization mode. if lin state is not init and if timer is in lin timeout mode, then hardware takes control of toce bit. cnt counter value these bits indicate the lin timeout counter value.
lin controller (linflexd) 31-38 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 31.10.8 lin output comp are register (linocr) offset: 0x1c access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 roc2 1 oc1 1 ww1c 1 w1c 1 reset1111111111111111 1 if lintcsr[ltom] = 1, these fields are read-only. figure 31-25. lin output compare register (linocr) table 31-20. linocr field descriptions field description oc2 output compare 2 value these bits contain the value to be co mpared to the value of lintcsr[cnt]. oc1 output compare 1 value these bits contain the value to be co mpared to the value of lintcsr[cnt].
lin controller (linflexd) freescale semiconductor 31-39 pxs20 microcontroller reference manual, rev. 1 31.10.9 lin timeout cont rol register (lintocr) offset: 0x20 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 rto 0 hto 3 w reset00001110000/1 1 0/1 2 1100 1 resets to 1 in slave mode and to 0 in master mode 2 resets to 0 in slave mode and to 1 in master mode 3 hto field can only be written in slave mode, lincr1[mme] = 0. figure 31-26. lin timeout control register (lintocr) table 31-21. lintocr field descriptions field description rto response timeout value this register contains the response timeout duration (in bit time) for 1 byte. the reset value is 0xe = 14, corresponding to t response_maximum =1.4xt response_nominal hto header timeout value this register contains the header timeout duration (in bit time). this value does not include the first 11 dominant bits of the break. the reset value depends on which mode linflexd is in. hto can be written only for slave mode.
lin controller (linflexd) 31-40 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 31.10.10 lin fractional baud rate register (linfbrr) 31.10.11 lin integer baud rate register (linibrr) offset: 0x24 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 0000 0000 div_f 1 w reset0000000000000000 1 this field is writable only in in itialization mode, lincr1[init] = 1. figure 31-27. lin timeout control register (lintocr) table 31-22. linfbrr field descriptions field description div_f fraction bits of lfdiv the 4 fraction bits define the value of the fraction of the linflexd divider (lfdiv). fraction (lfdiv) = decimal value of div_f / 16. this register can be written in initialization mode only, lincr1[init] = 1. offset: 0x28 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 0000 0000 div_m 1 w reset00000000000000000000000000000000 1 this field is writable only in initialization mode (lincr1[init] = 1). figure 31-28. lin integer ba ud rate register (linibrr)
lin controller (linflexd) freescale semiconductor 31-41 pxs20 microcontroller reference manual, rev. 1 31.10.12 lin checksum field register (lincfr) table 31-23. linibrr field descriptions field description div_m lfdiv mantissa these bits define the linflexd divider (lfdiv) mantissa value (see table 31-24 ). this register can be written in initialization mode only. table 31-24. integer baud rate selection div_m mantissa 0x0 lin clock disabled 0x1 1 ... ... 0xffffe 1048574 0xfffff 1048575 offset: 0x2c access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 0000 cf w reset0000000000000000 figure 31-29. lin checksum field register (lincfr) table 31-25. lincfr field descriptions field description cf checksum bits when lincr1[ccd] is cleared, these bits are re ad-only. when lincr1[ccd] is set, these bits are read/write. see table 31-11 .
lin controller (linflexd) 31-42 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 31.10.13 lin control register 2 (lincr2) offset: 0x30 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 iobe 1 iope 1 wurq ddrq dtrq abrq htrq 0 0 0 0 0 0 0 0 w w1c w1c w1c w1c w1c reset 0 1 0/1 2 0000000000000 1 these fields are writable only in initialization mode (lincr1[init] = 1. 2 resets to 1 in slave mode and to 0 in master mode figure 31-30. lin control register 2 (lincr2) table 31-26. lincr2 field descriptions field description iobe idle on bit error 0: bit error does not reset lin state machine 1: bit error reset lin state machine this bit can be set/cleared in initialization mode only (lincr1[init]) = 1. iope idle on identifier parity error 0: identifier parity error doe s not reset lin state machine. 1: identifier parity error reset lin state machine. this bit can be set/cleared in initialization mode only (lincr1[init]) = 1. wurq wake-up generation request setting this bit generates a wake-up pulse. it is reset by hardware when the wake-up character has been transmitted. the character sent is copied from data0 in bdrl buffer. note that this bit cannot be set in sleep mode. software has to exit sleep mode before requesting a wake-up. bit error is not checked when transmitting the wake-up request. ddrq data discard request set by software to stop data re ception if the frame does not concern the node. this bit is reset by hardware once linflexd has moved to idle state. in slave mode, this bit can be set only when hrf bit in linsr is set and identifier did not match any filter. dtrq data transmission request set by software in slave mode to request the trans mission of the lin data field stored in the buffer data register. this bit can be set only when hrf bit in linsr is set. cleared by hardware when the request has been completed or aborted or on an error condition. in master mode, this bit is set by hardware when dir bit in bidr is set and header transmission is completed.
lin controller (linflexd) freescale semiconductor 31-43 pxs20 microcontroller reference manual, rev. 1 31.10.14 buffer identifier register (bidr) this register contains the fields that identify a transaction and provi de other information related to it. all the fields in this regi ster must be updated when an id filter (enabled) in sl ave mode (tx or rx) matches the id received. abrq abort request set by software to abort the current transmission. cleared by hardware when the transmission has been aborted. linflexd aborts the transmission at the end of the current bit. this bit can also abort a wake-up request. it can also be used in uart mode. htrq header transmission request set by software to request t he transmission of the lin header. cleared by hardware when the request has been completed or aborted. this bit has no effect in uart mode. offset: 0x34 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dfl dir ccs 00 id ww1cw1c reset0000000000000000 figure 31-31. buffer identifier register (bidr) table 31-27. bidr field descriptions field description dfl data field length these bits define the number of data bytes in the response part of the frame. dfl = number of data bytes - 1. normally, lin uses only dfl[0:2] to manage frames wit h a maximum of 8 bytes of data. identifier filters are compatible with dfl[ 0:2] and dfl[0:5] . dfl[ 3:5] are provided to manage extended frames. dir direction this bit controls the direction of the data field. 0: linflexd receives the data and copy them in the bdr registers. 1: linflexd transmits the data from the bdr registers. table 31-26. lincr2 field descriptions (continued) field description
lin controller (linflexd) 31-44 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 31.10.15 buffer data regist er least significant (bdrl) ccs classic checksum this bit controls the type of checksum applied on the current message. 0: enhanced checksum covering identifier and data fields. this is compatib le with lin specification 2.0 and higher. 1: classic checksum covering data fi elds only. this is compatible wi th lin specification 1.3 and below. id identifier identifier part of the identifier field without the identifier parity. offset: 0x38 access: user read/write 0123456789101112131415 r data3 data2 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r data1 data0 w reset0000000000000000 figure 31-32. buffer data register least significant (bdrl) table 31-28. bdrl field descriptions field description data3 data byte 3 data byte 3 of the data field data2 data byte 2 data byte 2 of the data field data1 data byte 1 data byte 1 of the data field data0 data byte 0 data byte 0 of the data field table 31-27. bidr field descriptions (continued) field description
lin controller (linflexd) freescale semiconductor 31-45 pxs20 microcontroller reference manual, rev. 1 31.10.16 buffer data regist er most significant (bdrm) offset: 0x3c access: user read/write 0123456789101112131415 r data7 data6 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r data5 data4 w reset0000000000000000 figure 31-33. buffer data regi ster most significant (bdrm) table 31-29. bdrm field descriptions field description data7 data byte 7 data byte 7 of the data field data6 data byte 6 data byte 6 of the data field data5 data byte 5 data byte 5 of the data field data4 data byte 4 data byte 4 of the data field
lin controller (linflexd) 31-46 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 31.10.17 identifier filter enable register (ifer) offset: 0x40 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 0000 fact 1 w reset0000000000000000 1 this field is writable only in initialization mode (lincr1[init] = 1). figure 31-34. identifier filter enable register (ifer) table 31-30. ifer field descriptions field description fact filter activation (see table 31-31 ) the software sets the bit fact[x] to activa te the filters x in identifier list mode. in identifier mask mode bits fact(2n + 1) have no effect on the corresponding filters as they act as masks for the identifiers 2n. 0 filters 2n and 2n + 1 are deactivated. 1 filters 2n and 2n + 1 are activated. table 31-31. ifer[fact] configuration bit value result fact[0] 0 filters 0 and 1 are deactivated. 1 filters 0 and 1 are activated. fact[1] 0 filters 2 and 3 are deactivated. 1 filters 2 and 3 are activated. fact[2] 0 filters 4 and 5 are deactivated. 1 filters 4 and 5 are activated. fact[3] 0 filters 6 and 7 are deactivated. 1 filters 6 and 7 are activated. fact[4] 0 filters 8 and 9 are deactivated. 1 filters 8 and 9 are activated. fact[5] 0 filters 10 and 11 are deactivated. 1 filters 10 and 11 are activated.
lin controller (linflexd) freescale semiconductor 31-47 pxs20 microcontroller reference manual, rev. 1 31.10.18 identifier filter match index (ifmi) fact[6] 0 filters 12 and 13 are deactivated. 1 filters 12 and 13 are activated. fact[7] 0 filters 14 and 15 are deactivated. 1 filters 14 and 15 are activated. offset: 0x44 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000 0000 00000 ifmi w reset0000000000000000 figure 31-35. identifier filter match index (ifmi) table 31-32. ifmi field descriptions field description ifmi filter match index this register contains the index corresponding to t he received id. it can be used to directly write or read the data in ram (refer to section 31.7.2, slave mode, for more details). when no filter matches, ifmi = 0. w hen filter n is matching, ifmi = n + 1. table 31-31. ifer[fact] configuration (continued) bit value result
lin controller (linflexd) 31-48 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 31.10.19 identifier filter mode register (ifmr) 31.10.20 identifier filter control registers (ifcr0?ifcr15) the function of these registers is different depending on which mode the linflexd controller is in, as described in table 31-34 . offset:0x48 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000 0000 00000 ifm 1 w reset0000000000000000 1 this field is writable only in initialization mode(lincr1[init] = 1). figure 31-36. identifier filter mode register (ifmr) table 31-33. ifmr field descriptions field description ifm filter mode 0 filters 2 n and 2 n + 1 are in identifier list mode. 1 filters 2 n and 2 n + 1 are in mask mode (filter 2 n + 1 is the mask for the filter 2 n ). table 31-34. ifcr functionality based on mode mode ifcr functionality identifier list each ifcr register acts as a filter. identifier mask if a = (number of filters) / 2, and n = 0 to (a - 1), then ifcr[2n] acts as a filter and if cr[2n+1] acts as the mask for ifcr[2n].
lin controller (linflexd) freescale semiconductor 31-49 pxs20 microcontroller reference manual, rev. 1 31.10.21 global control register (gcr) this register can be programmed only in initialization mode. the configuration specified in this register applies in both lin and uart modes. offsets: 0x4c?0x88 (16 regist ers) access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dfl 1 dir 1 ccs 1 00 id 1 w reset0000000000000000 1 these fields are writable only in initialization mode (lincr1[init] = 1). figure 31-37. identifier filter control registers (ifcr0?ifcr15) table 31-35. ifcr field descriptions field description dfl data field length this field defines the number of data bytes in the response part of the frame. dir direction this bit controls the direction of the data field. 0: linflexd receives the data and copy them in the bdrl and bdrm registers. 1: linflexd transmits the data fr om the bdrl and bdrm registers. ccs classic checksum this bit controls the type of checksum applied on the current message. 0: enhanced checksum covering identifier and data fields. this is compatib le with lin specification 2.0 and higher. 1: classic checksum covering data fi elds only. this is compatible wi th lin specification 1.3 and below. id identifier identifier part of the identifier field without the identifier parity.
lin controller (linflexd) 31-50 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 offset: 0x8c access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000 0000 000 tdfbm 1 rdfbm 1 tdlis 1 rdlis 1 stop 1 0 w sr 1 reset0000000000000000 1 this field is writable only in initialization mode (lincr1[init] = 1). figure 31-38. global control register (gcr) table 31-36. gcr field descriptions field description tdfbm transmit data first bit msb this field controls the first bit of transmitted data (payload only) as msb/lsb in both uart and lin modes. 0 the first bit of transmitted data is lsb ? that is, the first bit transmitted is mapped on the lsb bit (bdr(0), bdr(8), bdr(16), bdr(24)). 1 the first bit of transmitted data is msb ? that is , the first bit transmitted is mapped on the msb bit (bdr(7), bdr(15), bdr(23), bdr(31)). rdfbm received data first bit msb this field controls the first bit of received data (payload only) as msb/lsb in both uart and lin modes. 0 the first bit of received data is lsb ? that is, t he first bit received is mapped on the lsb bit (bdr(0), bdr(8), bdr(16), bdr(24)). 1 the first bit of received data is msb ? that is, the first bit received is mapped on the msb bit (bdr(7), bdr(15), bdr(23), bdr(31)). tdlis transmit data level inversion selection this field controls the data inversion of transmitted data (payload only) in both uart and lin modes. 0 transmitted data is not inverted. 1 transmitted data is inverted. rdlis received data level inversion selection this field controls the data inversion of received data (payload only) in both uart and lin modes. 0 received data is not inverted. 1 received data is inverted. stop stop bit configuration this field controls the number of stop bits in tr ansmitted data in both uart and lin modes. the stop bit is configured for all the fields (delimiter, sync, id, checksum, and payload). 0 one stop bit 1 two stop bits
lin controller (linflexd) freescale semiconductor 31-51 pxs20 microcontroller reference manual, rev. 1 31.10.22 uart preset timeout register (uartpto) this register contains the preset timeout value in uart mode, and is used to monitor the idle state of the reception line. the timeout detection uses this register and the uartcto register described in section 31.10.23, uart current timeout register (uartcto) . 31.10.23 uart current timeout register (uartcto) this register contains the current timeout value in uart mode, and is used in conjunction with the uartpto register (see section 31.10.22, uart preset t imeout register (uartpto) ) to monitor the idle state of the reception line. uart ti meout works in both cpu and dma modes. the timeout counter: ? starts at zero and counts upward ? is clocked with the baud rate clock presca led by a hard-wired sc aling factor of 16 ? is automatically enabled when uartcr[rxen] = 1 sr soft reset if the software writes a ?1? to this field, the linflexd controller execut es a soft reset in which the fsms, fifo pointers, counters, timers, status registers, and error registers are reset but the configuration registers are unaffected. this field always reads ?0?. offset: 0x90 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000 0 pto w reset0000111111111111 figure 31-39. uart preset timeout register (uartpto) table 31-37. uartpto field descriptions field description pto preset value of the timeout counter do not set pto = 0 (otherwise, uartsr[to] would immediately be set). table 31-36. gcr field descriptions (continued) field description
lin controller (linflexd) 31-52 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 31.10.24 dma tx enable register (dmatxe) this register enables the dma tx interface. offset: 0x94 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000 0cto w reset0000000000000000 figure 31-40. uart current timeout register (uartcto) table 31-38. uartcto field descriptions field description cto current value of the timeout counter this field is reset whenever one of the following occurs: ? a new value is written to the uartpto register ? the value of this field matches the value of uartpto[pto] ? a hard or soft reset occurs ? new incoming data is received when cto matches the value of uartpto[pto], uartsr[to] is set. offset: 0x98 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dte 15 dte 14 dte 13 dte 12 dte 11 dte 10 dte 9 dte 8 dte 7 dte 6 dte 5 dte 4 dte 3 dte 2 dte 1 dte0 w reset0000000000000000 figure 31-41. dma tx enable register (dmatxe)
lin controller (linflexd) freescale semiconductor 31-53 pxs20 microcontroller reference manual, rev. 1 31.10.25 dma rx enable register (dmarxe) this register enables the dma rx interface. 31.11 dma interface the linflexd dma interface offers a parametric and programmable solu tion with the following features: ? lin master node, tx mode: single dma channel ? lin master node, rx mode: single dma channel ? lin slave node, tx mode: 1 to n dma cha nnels where n = max num ber of id filters ? lin slave node, rx mode: 1 to n dma cha nnels where n = max number of id filters ? uart node, tx mode: single dma channel ? uart node, rx mode: single dma channel + timeout table 31-39. dmatxe field descriptions field description dte n dma tx channel n enable 0 dma tx channel n disabled 1 dma tx channel n enabled note: when dmatxe = 0x0, the dma tx interface fsm is forced (soft reset) into the idle state. offset: 0x9c access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dre 15 dre 14 dre 13 dre 12 dre 11 dre 10 dre 9 dte 8 dre 7 dre 6 dre 5 dre 4 dre 3 dre 2 dre 1 dre0 w reset0000000000000000 figure 31-42. dma rx enable register (dmarxe) table 31-40. dmarxe field descriptions field description dre n dma rx channel n enable 0 dma rx channel n disabled 1 dma rx channel n enabled note: when dmarxe = 0x0, the dma rx interface fsm is forced (soft reset) into the idle state.
lin controller (linflexd) 31-54 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 the linflexd controller interacts with an enhanced direct memory access (e dma) controller; see the description of that controller fo r details on its operati on and the transfer cont rol descriptors (tcds) referenced in this section. 31.11.1 master node, tx mode on a master node in tx mode, the dma interface re quires a single tx channel. each tcd controls a single frame, except for the extended frames (multiple tcds). the memory map associated with the tcd chain (ram area and linflexd registers) is shown in figure 31-43 . figure 31-43. tcd chain memory map (master node, tx mode) the tcd chain of the dma tx channel on a master node supports: ? master to slave: transmission of the entire frame (header + data) ? slave to master: transmission of the header. the data reception is controlled by the rx channel on the master node. ? slave to slave: tran smission of the header. the register settings for the lincr2 and bidr re gisters for each class of lin frame are shown in table 31-41 . lincr2 (4 bytes) bidr (4 bytes) bdrl + bdrm dma transfer (4/8 bytes) lincr2 (4 bytes) bidr (4 bytes) lincr2 (4 bytes) bidr (4 bytes) bdrl + bdrm (8 bytes) bdrl + bdrm (4/8 bytes) ram area tcd (n+2) tcd (n+3) linked chain lincr2 (4 bytes) bidr (4 bytes) bdrl + bdrm (4/8 bytes) lincr2 (4 bytes) bidr (4 bytes) lincr2 (4 bytes) bidr (4 bytes) bdrl + bdrm (8 bytes) bdrl + bdrm (4/8 bytes) linflex2 registers frame (n+1) slave ? > master or slave ? > slave extended frame (n+2) master ? > slave extended frame (n+3) master ? > slave frame (n) master ? > slave 1 dma tx channel (tcd si ngle and/or linked chain) tcd (n+1) tcd (n)
lin controller (linflexd) freescale semiconductor 31-55 pxs20 microcontroller reference manual, rev. 1 the concept fsm to control the dma tx interface is shown in figure 31-44 . the dma tx fsm will move to idle state immediately at next clock edge if dmatxe[0] = 0. table 31-41. register settings (master node, tx mode) lin frame lincr2 bidr master to slave ddrq=1 dtrq=0 htrq=0 dfl = payload size id = address ccs = checksum dir = 1 (tx) slave to master ddrq=0 dtrq=0 htrq=0 dfl = payload size id = address ccs = checksum dir = 0 (rx) slave to slave ddrq=1 dtrq=0 htrq=0 dfl = payload size id = address ccs = checksum dir = 0 (rx)
lin controller (linflexd) 31-56 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 31-44. fsm to control the dma tx interface (master node) the tcd settings (word transfer) are shown in table 31-42 . all other tcd fields are equal to 0. tcd settings based on half-word or byte transfers are allowed. enables dma tx channel request (dmaerqh, dmaerql) !dtf & !drf & (lin idle | dbef) & dma_ten & !token_dma_rx ? true dma tx transfer (req/ack minor/major loop) from ram area to linflex registers dma tx transfer is completed ? true dbef ? false set htrq to transmit the lin frame (header + [data]) !dir & !ddrq ? false (tx mode) true (rx mode) clear dbef to transmit the lin frame (data for extended frame) true false false false false dtf ? dbef ? set token_dma_rx to enable the dma rx interface clear dtf true (end of frame) true (extended frame, size > 8 bytes)
lin controller (linflexd) freescale semiconductor 31-57 pxs20 microcontroller reference manual, rev. 1 31.11.2 master node, rx mode on a master node in rx mode, the dma interface re quires a single rx channel. each tcd controls a single frame, except for the extended frames (multipl e tcds). the memory map associated to the tcd chain (ram area and linflexd registers) is shown in figure 31-45 . figure 31-45. tcd chain memory map (master node, rx mode) the tcd chain of the dma rx cha nnel on a master node supports slave- to-master reception of the data field. table 31-42. tcd settings (master node, tx mode) tcd field value description citer[14:0] 1 single iteration for the ?major? loop biter[14:0] 1 single iteration for the ?major? loop nbytes[31:0] [4 + 4] + 0/4/8 = n d ata buffer is stuffed with dumm y bytes if the length is not word aligned. lincr2 + bidr + bdrl + bdrm saddr[31:0] ram address soff[15:0] 4 word increment ssize[2:0] 2 word transfer slast[31:0] ?n daddr[31:0] lincr2 address doff[15:0] 4 word increment dsize[2:0] 2 word transfer dlast_sga[31:0] ?n no scatter/gather processing int_maj 0/1 interrupt disabled/enabled d_req 1 only on the last tcd of the chain. start 0 no software request bidr (4 bytes) bdrl + bdrm (4/8 bytes) dma transfer ram area tcd (n+2) linked chain bidr (4 bytes) bdrl + bdrm (8 bytes) bdrl + bdrm (4/8 bytes) linflex2 registers extended frame (n+1) frame (n) slave ? > master 1 dma rx channel (tcd single and/or linked chain) tcd (n+1) tcd (n) extended frame (n+2) bidr (4 bytes) bdrl + bdrm (4/8 bytes) bidr (4 bytes) bdrl + bdrm (8 bytes) bdrl + bdrm (4/8 bytes)
lin controller (linflexd) 31-58 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 the bidr register is optionally copi ed into the ram area. this bidr fi eld (part of fifo data) contains the id of each message to allow the cpu to figure out which id was received by the linflexd dma if only the ?one dma channel? setup is used. the concept fsm to control the dma rx interface is shown in figure 31-46 . the dma rx fsm will move to idle state immediately at next clock edge if dmarxe[0]=0. figure 31-46. fsm to control the dma rx interface (master node) the tcd settings (word transfer) are shown in table 31-43 . all other tcd fields are equal to 0. tcd settings based on half-word or byte transfer are allowed. enables dma rx channel request (dmaerqh, dmaerql) (drf | (dbff & rmb)) & token_dma_rx & dma_ren ? true dma rx transfer (req/ack minor/major loop) from linflex registers to ram area dma rx transfer done ? true false false false false drf ? dbff & rmb ? clear token_dma_rx true true (extended frame, clear drf clear dbff, rmb (for extended frame) size > 8 bytes)
lin controller (linflexd) freescale semiconductor 31-59 pxs20 microcontroller reference manual, rev. 1 31.11.3 slave node, tx mode on a slave node in tx mode, the dma interface requires a dma tx channel for each id filter programmed in tx mode. in case a si ngle dma tx channel is available, a single id field filter must be programmed in tx mode. each tcd controls a single frame, except for the extended frames (multiple tcds). the memory map associated to the tcd chai n (ram area and linflexd registers) is shown in figure 31-47 . figure 31-47. tcd chain memory map (slave node, tx mode) the tcd chain of the dma tx channel on a slave node supports: table 31-43. tcd settings (master node, rx mode) tcd field value description citer[14:0] 1 single iteration for the ?major? loop biter[14:0] 1 single iteration for the ?major? loop nbytes[31:0] [4] + 4/8 = n data buffer is stuffed with dummy bytes if the length is not word aligned. bidr + bdrl + bdrm saddr[31:0] bidr address soff[15:0] 4 word increment ssize[2:0] 2 word transfer slast[31:0] ?n daddr[31:0] ram address doff[15:0] 4 word increment dsize[2:0] 2 word transfer dlast_sga[31:0] ?n no scatter/gather processing int_maj 0/1 interrupt disabled/enabled d_req 1 only on the last tcd of the chain. start 0 no software request dma transfer ram area tcd (n+2) linked chain linflex2 registers extended frame (n+1) frame (n) slave ? > master 1 dma tx channel/filter (tcd single and/or linked chain) tcd (n+1) tcd (n) extended frame (n+2) bdrl + bdrm (4/8 bytes) bdrl + bdrm (8 bytes) bdrl + bdrm (4/8 bytes) slave ? > slave bdrl + bdrm (4/8 bytes) bdrl + bdrm (8 bytes) bdrl + bdrm (4/8 bytes)
lin controller (linflexd) 31-60 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? slave to master: transmission of the data field ? slave to slave: transm ission of the data field the register settings of the lincr2, ifer , ifmr, and ifcr registers are shown in table 31-44 . the concept fsm to control the dma tx interface is shown in figure 31-48 . dma tx fsm will move to idle state if dmatxe[ x ] = 0, where x =ifmi?1. table 31-44. register settings (slave node, tx mode) lin frame lincr2 ifer ifmr ifcr slave to master or slave to slave ddrq = 0 dtrq = 0 htrq = 0 to enable an id filter (tx mode) for each dma tx channel - identifier list mode - identifier mask mode dfl = payload size id = address ccs = checksum dir = 1(tx)
lin controller (linflexd) freescale semiconductor 31-61 pxs20 microcontroller reference manual, rev. 1 figure 31-48. fsm to control the dma tx interface (slave node) the tcd settings (word transfer) are shown in table 31-45 . all other tcd fields are equal to 0. tcd settings based on half-word or byte transfer are allowed. enables dma tx channel/filter request (dmaerqh, dmaerql) !dtf & !drf & (dbef | hrf) & (ifmi != 0) & dma_ten ? true dma tx transfer (req/ack) from ram area to linflex registers (channel/filter mapping) dma tx transfer done ? true dbef ? false set dtrq to transmit the lin frame (data) clear dbef to transmit the lin frame (data for extended frame) true false false false false dtf ? dbef ? clear dtf true true (extended frame, size > 8 bytes)
lin controller (linflexd) 31-62 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 31.11.4 slave node, rx mode on a slave node in rx mode, th e dma interface requires a dma rx channel for each id filter programmed in rx mode. in case a single dma rx channe l is available, a single id field filter must be programmed in rx mode. each tcd controls a single frame, except for the extended frames (multiple tcds). the memory map associated to the tcd chai n (ram area and linflexd registers) is shown in figure 31-49 . figure 31-49. tcd chain memory map (slave node, rx mode) the tcd chain of the dma rx channel on a slave node supports: table 31-45. tcd settings (slave node, tx mode) tcd field value description citer[14:0] 1 single iteration for the ?major? loop biter[14:0] 1 single iteration for the ?major? loop nbytes[31:0] 4/8 = n data buffer is stuffed with dummy bytes if the length is not word aligned. bdrl + bdrm saddr[31:0] ram address soff[15:0] 4 word increment ssize[2:0] 2 word transfer slast[31:0] ?n daddr[31:0] bdrl address doff[15:0] 4 word increment dsize[2:0] 2 word transfer dlast_sga[31:0] ?n no scatter/gather processing int_maj 0/1 interrupt disabled/enabled d_req 1 only on the last tcd of the chain. start 0 no software request bidr (4 bytes) bdrl + bdrm (4/8 bytes) dma transfer ram area tcd (n+2) linked chain bidr (4 bytes) bdrl + bdrm (8 bytes) bdrl + bdrm (4/8 bytes) linflex2 registers extended frame (n+1) frame (n) master ? > slave 1 dma rx channel/filter (tcd single and/or linked chain) tcd (n+1) tcd (n) extended frame (n+2) bidr (4 bytes) bdrl + bdrm (4/8 bytes) bidr (4 bytes) bdrl + bdrm (8 bytes) bdrl + bdrm (4/8 bytes) slave ? > slave
lin controller (linflexd) freescale semiconductor 31-63 pxs20 microcontroller reference manual, rev. 1 ? master to slave: recep tion of the data field. ? slave to slave: recep tion of the data field. the register setting of the lincr2, ifer , ifmr, and ifcr registers are given in table 31-46 . the concept fsm to control the dma rx interface is shown in figure 31-50 . dma rx fsm will move to idle state if dmarxe[ x ]=0 where x =ifmi-1. figure 31-50. fsm to control the dma rx interface (slave node) table 31-46. register settings (slave node, rx mode) lin frame lincr2 ifer ifmr ifcr master to slave or slave to slave ddrq = 0 dtrq = 0 htrq = 0 to enable an id filter (rx mode) for each dma rx channel - identifier list mode - identifier mask mode dfl = payload size id = address ccs = checksum dir = 0 (rx) enables dma rx channel/filter request (dmaerqh, dmaerql) !dtf & (drf | (dbff & rmb)) & (ifmi != 0) & dma_ren ? true dma rx transfer (req/ack) from linflex registers to ram area (channel/filter mapping) dma rx transfer done ? true false false false false drf ? dbff & rmb ? true true (extended frame, clear drf clear dbff, rmb (for extended frame) size > 8 bytes)
lin controller (linflexd) 31-64 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 the tcd settings (word transfer) are shown in table 31-47 . all other tcd fields = 0. tcd settings based on half-word or byte transfer are allowed. 31.11.5 uart node, tx mode in uart tx mode, the dma inte rface requires a dma tx channel. a single tcd can control the transmission of an entire tx buffer. the memory map associated with the tcd chain (ram area and linflexd registers) is shown in figure 31-51 . figure 31-51. tcd chain memory map (uart node, tx mode) table 31-47. tcd settings (slave node, rx mode) tcd field value description citer[14:0] 1 single iteration for the ?major? loop biter[14:0] 1 single iteration for the ?major? loop nbytes[31:0] [4] + 4/8 = n data buffer is stuffed with dummy bytes if the length is not word aligned. bidr + bdrl + bdrm saddr[31:0] bdrl address soff[15:0] 4 word increment ssize[2:0] 2 word transfer slast[31:0] ?n daddr[31:0] ram address doff[15:0] 4 word increment dsize[2:0] 2 word transfer dlast_sga[31:0] ?n no sc atter/gather processing int_maj 0/1 interrupt disabled/enabled d_req 1 only on the last tcd of the chain. start 0 no software request bdrl (m half-words) bdrl (2 half-words fifo mode) bdrl (m half-words) bdrl (2 half-words fifo mode) bdrl (m bytes) bdrl (m bytes) dma transfer (8/16-bits data format) ram area linflex2 registers 1 dma tx channel (tcd single and/or linked chain) tcd (n+1) tcd (n) buffer (n+1) bdrl (4 bytes fifo mode) bdrl (4 bytes fifo mode) buffer (n)
lin controller (linflexd) freescale semiconductor 31-65 pxs20 microcontroller reference manual, rev. 1 the uart tx buffer must be configur ed in fifo mode in order to: ? allow the transfer of large data buffer by a single tcd ? adsorb the latency, following a dma request (due to the dma arbitration), to move data from the ram to the fifo ? use low priority dma channels ? support the uart baud rate (2 mb/s) without underrun events the tx fifo size is: ? 4 bytes in 8-bit data format ? 2 half-words in 16-bit data format a dma request is triggered by fifo not full (tx) status signals. the concept fsm to control the dma tx interface is shown in figure 31-52 . dma tx fsm will move to idle state if dmatxe[0] = 0.
lin controller (linflexd) 31-66 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 31-52. fsm to control the dma tx interface (uart node) the tcd settings (typica l case) are shown in table 31-48 . all other tcd fields = 0. the minor loop transfers a single byte/half-word as soon a free entry is available in the tx fifo. table 31-48. tcd settings (uart node, tx mode) tcd field value description 8-bit data 16-bit data citer[14:0] m multiple iterations for the ?major? loop biter[14:0] m multiple iterations for the ?major? loop nbytes[31:0] 1 2 minor loop transfer = 1 or 2 bytes saddr[31:0] ram address !tff & dma_ten ? true false false !tff ? uart tx buffer (fifo mode) set txen enables dma tx channel request (dmaerqh, dmaerql) dma tx transfer (req/ack) from ram area to uart tx fifo dma tx (major loop) done ? true false dma tx (minor loop) done ? true false true
lin controller (linflexd) freescale semiconductor 31-67 pxs20 microcontroller reference manual, rev. 1 31.11.6 uart node, rx mode in uart rx mode, the dma inte rface requires a dma rx channel. a single tcd can control the reception of an entire rx buffer. the memory map associated with the tcd chain (ram area and linflexd registers) is shown in figure 31-53 . figure 31-53. tcd chain memory map (uart node, rx mode) the uart rx buffer must be configur ed in fifo mode in order to: ? allow the transfer of large data buffer by a single tcd ? adsorb the latency, following a dma request (due to the dma arbitration), to move data from the fifo to the ram ? use low priority dma channels soff[15:0] 1 2 byte/half-word increment ssize[2:0] 0 1 byte/half-word transfer slast[31:0] -m -m * 2 daddr[31:0] bdrl address daddr = bdrl + 0x3 for byte transfer daddr = bdrl + 0x2 for half-word transfer doff[15:0] 0 no increment (fifo) dsize[2:0] 0 1 byte/half-word transfer dlast_sga[31:0] 0 no scatter/gather processing int_maj 0/1 interrupt disabled/enabled d_req 1 only on the last tcd of the chain. start 0 no software request table 31-48. tcd settings (uart node, tx mode) (continued) tcd field value description 8-bit data 16-bit data buffer (n+1) buffer (n) dma transfer (8/16-bits data format) ram area linflex2 registers 1 dma rx channel (tcd single and/or linked chain) bdrm (4 bytes fifo mode) bdrm (2 half-words fifo mode) bdrm (4 bytes fifo mode) bdrm (2 half-words fifo mode) tcd (n+1) tcd (n) bdrm (m bytes) bdrm (m half-words) bdrm (m bytes) bdrm (m half-words)
lin controller (linflexd) 31-68 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? support high uart baud rate (at l east 2 mb/s) without overrun events the rx fifo size is: ? 4 bytes in 8-bit data format ? 2 half-words in 16-bit data format this is sufficient because just one byte allows a reaction time of about 3.8 ? s (at 2 mbit/s), corresponding to about 450 clock cycles at 120 mhz, before the tran smission is affected. a dm a request is triggered by fifo not empty (rx) status signals. the concept fsm to control the dma rx interface is shown in figure 31-54 . dma rx fsm will move to idle state if dmarxe[0] = 0.
lin controller (linflexd) freescale semiconductor 31-69 pxs20 microcontroller reference manual, rev. 1 figure 31-54. fsm to control the dma rx interface (uart node) the tcd settings (typica l case) are shown in table 31-49 . all other tcd fields = 0. the minor loop transfers a single byte/half-w ord as soon an entry is av ailable in the rx fifo. a new software reset bit is !rfe & dma_ren ? true false !rfe ? uart rx buffer (fifo mode) timeout config enables dma rx channel request (dmaerqh, dmaerql) dma rx transfer (req/ack) from uart rx fifo to ram area dma rx (major loop) done ? true false dma rx (minor loop) done ? true false true set rxen timeout restart false false timeout ? true set timeout flag
lin controller (linflexd) 31-70 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 required that allows the linflexd fsms to be reset in case this timeout state is reached or in any other case. timeout counter can be re-written by so ftware at any time to extend timeout period. 31.11.7 use cases and limitations ? in lin slave mode, the dma capability can be used only if the id filtering mode is activated. the number of id filters enabled must be equal to the number of dma channels enabled. the correspondence between channel # an d id filter is based on ifmi (i dentifier filter match index). ? in lin master mode both the dma channels (t x and rx) must be en abled in case the dma capability is required. ? in uart mode the dma capability can be used only if the uart tx/rx buffers are configured as fifos. ? dma and cpu operating modes are mutually exclusive for the data/frame transfer on a uart or lin node. once a dma transfer is finished the cpu can handle subsequent accesses. ? error management must be alwa ys executed via cpu enabling the related error interrupt sources. the dma capability does not provi de support for the error manage ment. error management means checking status bits, handling irqs a nd potentially canceling dma transfers. ? the dma programming model must be coherent wi th the tcd setting defined in this document. table 31-49. tcd settings (uart node, rx mode) tcd field value description 8 bits data 16 bits data citer[14:0] m multiple iterations for the ?major? loop biter[14:0] m multiple iterations for the ?major? loop nbytes[31:0] 1 2 minor loop transfer = 1 or 2 bytes saddr[31:0] bdrm address saddr = bdrm + 0x3 for byte transfer saddr = bdrm + 0x2 for half-word transfer soff[15:0] 0 no increment (fifo) ssize[2:0] 0 1 byte/half-word transfer slast[31:0] 0 daddr[31:0] ram address doff[15:0] 1 2 byte/half-word increment dsize[2:0] 0 1 byte/half-word transfer dlast_sga[31:0] -m -m * 2 no scatter/gather processing int_maj 0/1 interrupt disabled/enabled d_req 1 only on the last tcd of the chain. start 0 no software request
lin controller (linflexd) freescale semiconductor 31-71 pxs20 microcontroller reference manual, rev. 1 31.12 functional description 31.12.1 8-bit timeout counter 31.12.1.1 lin timeout mode the timeout counter can be used to monitor lin frames timing as well as problems on the lin bus such as: ? bus stuck at dominant state ? header timeout ? no bus activity ? slave not responding e rror (in master mode) ? wake-up timeout the header timeout and response ti meout values can be tuned in the lintocr register. the lintocr reset value corresponds to t header_max , t response_max and t frame_max defined in the lin standard. if the lintcsr[ltom] = 1, oc1 and oc2 output co mpare values in the linocr register are automatically updated. 1 oc1 is used to check t header and t response and oc2 is used to check t frame (refer to figure 31-55 ). when linflexd moves from break state to br eak delimiter state (refer to linsr register): ? oc1 is updated with the value of oc header (oc header =cnt+hto), ? oc2 is updated with the value of oc frame (oc frame =cnt+hto+rtox9 (frame timeout value for an 8-byte frame)), ? the toce bit is set. on the start bit of the firs t data byte of the response (and if no error occurred dur ing the header reception), oc1 is updated with the value of oc response (oc response = cnt + rto x 9 (response timeout value for an 8-byte frame)). when bidr[dfl] is updated (and if no error occurred during the head er reception), oc1 and oc2 are automatically updated to check t response and t frame according to rto (tolerance) and dfl. on the checksum reception or in case of error in th e header or data field, the toce bit is cleared. this configuration is used to detect header timeout and response timeout. 1. the linocr register is read-only.
lin controller (linflexd) 31-72 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 31-55. header and response timeout 31.12.1.2 output compare mode the timeout counter can also be used as an output compare function. in this case, the ltom bit must be reset and output compare values can be updated in lintocr register by software. 31.12.2 interrupts table 31-50. linflexd interrupt control interrupt event event flag bit enable control bit interrupt vector header received interrupt hrf hrie rxi 1 notes: 1 in slave mode, if at least one filter is configured as tx and enabled, header received interrupt vector is rxi or txi depending on the value of identifier received. data transmitted interrupt dtf dtie txi data received interrupt drf drie rxi data buffer empty interrupt dbef dbeie txi data buffer full interrupt dbff dbfie rxi wake-up interrupt wupf wupie rxi lin state interrupt 2 2 for debug and validation purposes. lsf lsie rxi buffer overrun interrupt bof boie err framing error interrupt fef feie err header error interrupt hef heie err checksum error interrupt cef ceie err bit error interrupt bef beie err output compare interrupt ocf ocie err stuck at zero interrupt szf szie err oc frame oc header oc response header response break frame oc1 oc2 response space
lin controller (linflexd) freescale semiconductor 31-73 pxs20 microcontroller reference manual, rev. 1 figure 31-56. interrupt diagram 31.12.3 fractional baud rate generation the baud rates for the receiver and transmitter are both set to the sa me value as programmed in the mantissa (linibrr) and fr action (linfbrr) registers . lfdiv is an unsigned fixed point number. the 20-bit ma ntissa is coded in the linibrr register and the fraction is coded in the linfbrr register. the following examples show how to derive lf div from linibrr and li nfbrr register values: lsie states wuie wuf dbff drf hrie tx dtie dtf hrie hrf rx dbfie drie boie bof feie fef cef beie bef ceie hrf heie sfef,sdef,idpef ocie ocf szie szf error dbeie dbef toie to tx/rx baud = f ipg_clock_lin (16 * lfdiv)
lin controller (linflexd) 31-74 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 example 31-1. if linibrr = 27d and linfbrr = 12d, then mantissa (lfdiv) = 27d fraction (lfdiv) = 12/16 = 0.75d therefore lfdiv = 27.75d example 31-2. to program lfdiv = 25.62d, linfbrr = 16 * 0.62 = 9.92, nearest real number 10d = ah linibrr = mantissa(25.620d) = 25d = 19h note the baud counters are updated with the new value of the baud registers after a write to linibrr. hence the baud register value must not be changed during a transact ion. the linfbrr (contai ning the fraction bits) must be programmed before linibrr. note lfdiv must be greater than or equal to 1.5d, for example, linibrr = 1 and linfbrr = 8. therefore, the maximum possible baudrate is fperiph_set_1_clk / 24. 31.13 programming considerations this section describes the various configurat ions in which the linflexd can be used. table 31-51. error calculation for programmed baud rates baud rate f ipg_clock_lin = mhz f ipg_clock_lin = 16 mhz actual value programmed in the baud rate register % error = (calculated - desired) baud rate / desired baud rate actual value programmed in the baud rate register % error = (calculated - desired) baud rate / desired baud rate linibrr linfbrr linibrr linfbrr 10417 10416.7 383 16 -0.003 10416.7 95 16 -0.003
lin controller (linflexd) freescale semiconductor 31-75 pxs20 microcontroller reference manual, rev. 1 31.13.1 master node figure 31-57. programming consideration: master node, transmitter figure 31-58. programming consideration: master node, receiver figure 31-59. programming consideration: master node, transmitter, bit error figure 31-60. programming consideration: master node, receiver, checksum error header data tx checksum tx configure id dfl, data buffer set htrq txi interrupt dtf set dir = 1 header data rx checksum rx configure id, dfl set htrq rxi interrupt drf set dir = 0 and ddrq = 0 header data tx configure id dfl, data buffer set htrq dir = 1 bef set erri interrupt iobe = 1 header data tx checksum tx configure id dfl, data buffer set htrq tx interrupt dtf set dir = 1 bef set err interrupt iobe = 0 header data rx checksum rx configure id, dfl set htrq err interrupt cef set dir = 0 and ddrq = 0
lin controller (linflexd) 31-76 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 31.13.2 slave node figure 31-61. programming consideration: slave node, transmitter, no filters figure 31-62. programming consideration: slave node, receiver, no filters figure 31-63. programming consideration: slave node, transmitter, no filters, bit error figure 31-64. programming consideration: slave node, receiver, no filters, checksum error header data tx checksum tx tx interrupt dtf set hrf set rx interrupt set dtrq configure ccs, dir, dfl, data buffers header data rx checksum rx rx interrupt drf set configure ccs, dir, dfl hrf set rx interrupt ddrq = 0 header ddrq = 1 hrf set rx interrupt header data tx err interrupt bef set hrf set rx interrupt set dtrq configure dir, dfl, data buffers iobe = 1 header data rx checksum rx err interrupt cef set ddrq = 0 configure dir, dfl hrf set rx interrupt
lin controller (linflexd) freescale semiconductor 31-77 pxs20 microcontroller reference manual, rev. 1 figure 31-65. programming consideration: slave node, at le ast one tx filter, bf is reset, id matches filter figure 31-66. programming consideration: slave node, at least one rx filter, bf is reset, id matches filter figure 31-67. programming consideration: slave node, rx only, tx only, rx and tx filters, id not matching filter, bf is reset figure 31-68. programming consideration: slave node, tx filter, bf is set header data tx checksum tx tx interrupt dtf set set dtrq write data buffers hrf set tx interrupt (id matched) note: this configuration can be used in case the slave never receives data (for example, as with a sensor). header data rx checksum rx rxi interrupt drf set ifmi = id matched+1 header id not matching any filter header data tx checksum tx tx interrupt dtf set set dtrq write data buffers hrf set tx interrupt (id has matched) header data rx checksum rx rx interrupt drf set ddrq = 0 configure ccs, dir, dfl hrf set rx interrupt (id not matched) note: this configuration is used when: a) all tx ids are managed by filters b) the number of other filters is not enough to manage all reception ids
lin controller (linflexd) 31-78 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 31-69. programming consideration: slave node, rx filter, bf is set header data rx checksum rx rx interrupt drf set ifmi = id matched header data rx checksum rx rx interrupt drf set hrf set rx interrupt (id not matched) configure ccs, dir, dfl (id is rx) ddrq = 0 header data tx checksum tx tx interrupt dtf set hrf set rx interrupt set dtrq configure ccs, dir, dfl, data buffers (id is tx)
lin controller (linflexd) freescale semiconductor 31-79 pxs20 microcontroller reference manual, rev. 1 figure 31-70. programming consideration: slave node, tx filter, rx filter, bf is set 31.13.3 extended frames figure 31-71. programming consideration: extended frames header data tx checksum tx tx interrupt dtf set set dtrq write data buffers hrf set tx interrupt (ifmi = id matched+1) header data rx checksum rx rxi interrupt drf set ifmi = id matched+1 header data rx/tx checksum rx/tx rx/tx interrupt drf/dtf set ddrq = 0 configure ccs, dir, dfl hrf set rx interrupt (id not matched) note: this configuration is used when: a) the number of filters is not enough b) filters are used for most fre quently-used ids to reduce cpu usage header 8 bytes tx 8 bytes tx checksum tx tx interrupt dtf set configure dir, dfl, hrf set rx interrupt (id not matched) dbef set refill buffer reset dbef ccs dtrq =1 header 8 bytes rx 8 bytes rx checksum rx rx interrupt drf set configure dir, dfl, hrf set rx interrupt (id not matched) rmb, dbff read buffer reset rmb set ddrq = 0 ccs
lin controller (linflexd) 31-80 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 31.13.4 timeout figure 31-72. programming consideration: response timeout figure 31-73. programming consideration: frame timeout figure 31-74. programming consideration: header timeout 31.13.5 uart mode figure 31-75. programming consideration: uart mode header rx/tx data rx oc1 t response_max ocf is set err interrupt header rx/tx data rx/tx oc2 t frame_max ocf is set err interrupt header rx oc1 t header_max ocf is set err interrupt break data rx/tx dtf/drf is set tx/rx interrupt set txen/rxen write buffer for tx
mode entry module (mc_me) freescale semiconductor 32-1 pxs20 microcontroller reference manual, rev. 1 chapter 32 mode entry module (mc_me) 32.1 introduction 32.1.1 overview the mc_me controls the soc mode and mode transition sequences in all f unctional states. it also contains configuration, control and status re gisters accessible for the application. figure 32-1 depicts the mc_me block diagram.
mode entry module (mc_me) 32-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 registers platform interface core mc_me figure 32-1. mc_me block diagram mc_rgm xosc pll0 pll1 ircosc mc_cgm peripherals flash vreg device mode state machine wkpu
mode entry module (mc_me) freescale semiconductor 32-3 pxs20 microcontroller reference manual, rev. 1 32.1.2 features the mc_me includes the following features: ? control of the available modes by the me_me register ? definition of various device m ode configurations by the me_< mode >_mc registers ? control of the actual devi ce mode by the me_mctl register ? capture of the current m ode and various res ource status within the cont ents of the me_gs register ? optional generation of various mode transition interrupts ? status bits for each cause of invalid mode transitions ? peripheral clock gating control base d on the me_run_pc0?7, me_lp_pc0?7, and me_pctl0?143 registers ? capture of current peripher al clock gated/enabled status 32.1.3 modes of operation the mc_me is based on several device modes corres ponding to different usage models of the device. each mode is configurable and ca n define a policy for energy and pr ocessing power management to fit particular system requirements. an application can easily switch fr om one mode to another depending on the current needs of the system. the operating modes controlled by the mc_me are divided into system and user modes. the system modes are modes such as reset, drun, safe, and test. these modes aim to ease the configurat ion and monitoring of the system. the user modes ar e modes such as run0?3, halt0, and stop0 which can be configured to meet the application requirements in terms of energy management and available proc essing power. the modes drun, safe, test, and run0?3 are the device software running modes. table 32-1 describes the mc_me modes. table 32-1. mc_me mode descriptions name description entry exit reset this is a chip-wide virtual mode during which the application is not ac tive. the system rema ins in this mode until all resources are available for the embedded software to take control of the device. it manages hardware initialization of chip configuration, voltage regulators, clock sources, and flash modules. system reset assertion from mc_rgm system reset deassertion from mc_rgm drun this is the entry mode for the embedded software. it provides full accessibility to the system and enables the configuration of the system at startup. it provides the unique gate to enter user modes. bam when present is executed in drun mode. system reset deassertion from mc_rgm, software request from safe, test and run0?3 system reset assertion, run0?3, test via software, safe via software or hardware failure. safe this is a chip-wide service mode which may be entered on the detection of a recoverable error. it forces the system into a pre-defined safe configuration from which the system may try to recover. hardware failure, software request from drun, test, and run0?3 system reset assertion, drun via software
mode entry module (mc_me) 32-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 32.2 external signal description the mc_me has no connectio ns to any external pins . 32.3 memory map and register definition the mc_me contains registers for: ? mode selection and status reporting ? mode configuration ? mode transition interrupts status and mask control ? scalable number of peripheral sub-m ode selection and status reporting test this is a chip-wide service mode which is intended to provide a control environment for device software testing. software request from drun system reset assertion, drun via software run0 ? 3 these are software running modes where most processing activity is done. these various run modes allow to enable different clock & power config urations of the system with respect to each other. software request from drun or other run0?3, interrupt event from halt0, interrupt or wakeup event from stop0 system reset assertion, safe via software or hardware failure, other run0?3 modes, halt0, stop0 via software halt0 this is a reduced-activity low-power mode during which the clock to the core is disabled. it can be configured to switch off analog peripherals like clock sources, flash, main regulator, etc. for efficient power management at the cost of higher wakeup latency. software request from run0?3 system reset assertion, safe on hardware failure, run0?3 on interrupt event stop0 this is an advanced low-power mode during which the clock to the core is disabled. it may be configured to switch off most of the peripherals including clock sources for efficient power management at the cost of higher wakeup latency. software request from run0?3 system reset assertion, safe on hardware failure, run0?3 on interrupt event or wakeup event table 32-1. mc_me mode descriptions (continued) name description entry exit
mode entry module (mc_me) freescale semiconductor 32-5 pxs20 microcontroller reference manual, rev. 1 32.3.1 memory map table 32-2. mc_me register description address name description size access location user supervisor test 0xc3fd _c000 me_gs global status word read read read on page 32-13 0xc3fd _c004 me_mctl mode control word read read/write read/write on page 32-15 0xc3fd _c008 me_me mode enable word read read/write read/write on page 32-16 0xc3fd _c00c me_is interrupt status word read read/write read/write on page 32-17 0xc3fd _c010 me_im interrupt mask word read read/write read/write on page 32-19 0xc3fd _c014 me_imts invalid mode transition status word read read/write read/write on page 32-20 0xc3fd _c018 me_dmts debug mode transition status word read read read on page 32-21 0xc3fd _c020 me_reset_mc reset mode configuration word read read read on page 32-24 0xc3fd _c024 me_test_mc test mode configuration word read read/write read/write on page 32-24 0xc3fd _c028 me_safe_mc safe mode configuration word read read/write read/write on page 32-25 0xc3fd _c02c me_drun_mc drun mode configuration word read read/write read/write on page 32-25 0xc3fd _c030 me_run0_mc run0 mode configuration word read read/write read/write on page 32-26 0xc3fd _c034 me_run1_mc run1 mode configuration word read read/write read/write on page 32-26 0xc3fd _c038 me_run2_mc run2 mode configuration word read read/write read/write on page 32-26 0xc3fd _c03c me_run3_mc run3 mode configuration word read read/write read/write on page 32-26 0xc3fd _c040 me_halt0_mc halt0 mode configuration word read read/write read/write on page 32-26 0xc3fd _c048 me_stop0_mc stop0 mode configuration word read read/write read/write on page 32-27 0xc3fd _c060 me_ps0 peripheral status 0 word read read read on page 32-28 0xc3fd _c064 me_ps1 peripheral status 1 word read read read on page 32-29
mode entry module (mc_me) 32-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 0xc3fd _c068 me_ps2 peripheral status 2 word read read read on page 32-29 0xc3fd _c080 me_run_pc0 run peripheral configuration 0 word read read/write read/write on page 32-30 0xc3fd _c084 me_run_pc1 run peripheral configuration 1 word read read/write read/write on page 32-30 ? 0xc3fd _c09c me_run_pc7 run peripheral configuration 7 word read read/write read/write on page 32-30 0xc3fd _c0a0 me_lp_pc0 low-power peripheral configuration 0 word read read/write read/write on page 32-31 0xc3fd _c0a4 me_lp_pc1 low-power peripheral configuration 1 word read read/write read/write on page 32-31 ? 0xc3fd _c0bc me_lp_pc7 low-power peripheral configuration 7 word read read/write read/write on page 32-31 0xc3fd _c0c4 me_pctl4 dspi0 control byte read read/write read/write on page 32-31 0xc3fd _c0c5 me_pctl5 dspi1 control byte read read/write read/write on page 32-31 0xc3fd _c0c6 me_pctl6 dspi2 control byte read read/write read/write on page 32-31 0xc3fd _c0d0 me_pctl16 flexcan0 control byte read read/write read/write on page 32-31 0xc3fd _c0d1 me_pctl17 flexcan1 control byte read read/write read/write on page 32-31 0xc3fd _c0d8 me_pctl24 flexray control byte read read/write read/write on page 32-31 0xc3fd _c0e0 me_pctl32 adc0 control byte read read/write read/write on page 32-31 0xc3fd _c0e1 me_pctl33 adc1 control byte read read/write read/write on page 32-31 0xc3fd _c0e3 me_pctl35 ctu control byte read read/write read/write on page 32-31 0xc3fd _c0e6 me_pctl38 etimer0 control byte read read/write read/write on page 32-31 0xc3fd _c0e7 me_pctl39 etimer1 control byte read read/write read/write on page 32-31 table 32-2. mc_me register description (continued) address name description size access location user supervisor test
mode entry module (mc_me) freescale semiconductor 32-7 pxs20 microcontroller reference manual, rev. 1 note any access to unused registers as we ll as write accesses to read-only registers will: ? not change register content ? cause a transfer error 0xc3fd _c0e8 me_pctl40 etimer2 control byte read read/write read/write on page 32-31 0xc3fd _c0e9 me_pctl41 flexpwm0 control byte read read/write read/write on page 32-31 0xc3fd _c0ea me_pctl42 flexpwm1 control byte read read/write read/write on page 32-31 0xc3fd _c0f0 me_pctl48 lin_flex0 control byte read read/write read/write on page 32-31 0xc3fd _c0f1 me_pctl49 lin_flex1 control byte read read/write read/write on page 32-31 0xc3fd _c0fa me_pctl58 crc control byte read read/write read/write on page 32-31 0xc3fd _c0fe me_pctl62 swg control byte read read/write read/write on page 32-31 0xc3fd _c11c me_pctl92 pit control byt e read read/write read/write on page 32-31 table 32-3. mc_me memory map address name 012327 567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0xc3fd _c000 me_gs r s_current_mode s_mtrans 100 s_pdo 00 s_mvr reserved s_fla w r0 0 0 0 0000 s_pll1 s_pll0 s_xosc s_ircosc s_sysclk w table 32-2. mc_me register description (continued) address name description size access location user supervisor test
mode entry module (mc_me) 32-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 0xc3fd _c004 me_mctl r ta r g e t _ m o d e 0000000 00000 w r1 0 1 0 0101000 01111 w key 0xc3fd _c008 me_me r0 0 0 0 0000000 00000 w r 0 (cut1) reset_dest (cut2/3) 0000 stop0 0 halt0 run3 run2 run1 run0 drun safe test reset (cut1) reset_func (cut2/3) w 0xc3fd _c00c me_is (cut1)r0 0 0 0 0000000 00000 w r0 0 0 0 0000000 0 i_iconf i_imode i_safe i_mtc w w1c w1c w1c w1c me_is (cut2/3) r0 0 0 0 0000000 00000 w r0 0 0 0 0000000 i_iconf_cu i_iconf i_imode i_safe i_mtc w w1c w1c w1c w1c w1c 0xc3fd _c010 me_im r0 0 0 0 0000000 00000 w r0 0 0 0 0000000 0 m_iconf m_imode m_safe m_mtc w table 32-3. mc_me memory map (continued) address name 012327 567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
mode entry module (mc_me) freescale semiconductor 32-9 pxs20 microcontroller reference manual, rev. 1 0xc3fd _c014 me_imts r0 0 0 0 0000000 00000 w r0 0 0 0 0000000 s_mti s_mri s_dma s_nma s_sea w w1c w1c w1c w1c w1c 0xc3fd _c018 me_dmts rprevious_mode 0000 mph_busy 00 pmc_prog core_dbg 00 smr w r0 vreg_csrc_sc csrc_csrc_sc ircosc_sc scsrc_sc sysclk_sw reserved flash_sc cdp_prph_0_143 00 cdp_prph_64_95 cdp_prph_32_63 cdp_prph_0_31 w 0xc3fd _c01c reserved 0xc3fd _c020 me_reset_ mc r0 0 0 0 0000 pdo 00 mvron reserved flaon w r0 0 0 0 0000 pll1on pll0on xoscon ircoscon sysclk w 0xc3fd _c024 me_test_m c r0 0 0 0 0000 pdo 00 mvron reserved flaon w r0 0 0 0 0000 pll1on pll0on xoscon ircoscon sysclk w table 32-3. mc_me memory map (continued) address name 012327 567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
mode entry module (mc_me) 32-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 0xc3fd _c028 me_safe_m c r0 0 0 0 0000 pdo 00 mvron reserved flaon w r0 0 0 0 0000 pll1on pll0on xoscon ircoscon sysclk w 0xc3fd _c02c me_drun_m c r0 0 0 0 0000 pdo 00 mvron reserved flaon w r0 0 0 0 0000 pll1on pll0on xoscon ircoscon sysclk w 0xc3fd _c030 ? 0xc3fd _c03c me_run0?3 _mc r0 0 0 0 0000 pdo 00 mvron reserved flaon w r0 0 0 0 0000 pll1on pll0on xoscon ircoscon sysclk w 0xc3fd _c040 me_halt0_ mc r0 0 0 0 0000 pdo 00 mvron reserved flaon w r0 0 0 0 0000 pll1on pll0on xoscon ircoscon sysclk w 0xc3fd _c044 reserved table 32-3. mc_me memory map (continued) address name 012327 567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
mode entry module (mc_me) freescale semiconductor 32-11 pxs20 microcontroller reference manual, rev. 1 0xc3fd _c048 me_stop0_ mc r0 0 0 0 0000 pdo 00 mvron reserved flaon w r0 0 0 0 0000 pll1on pll0on xoscon ircoscon sysclk w 0xc3fd _c04c ? 0xc3fd _c05c reserved 0xc3fd _c060 me_ps0 r0 0 0 0 000 s_flexray 000 0 0 0 s_flexcan1 s_flexcan0 w r0 0 0 0 00000 s_dspi2 s_dspi1 s_dspi0 0000 w 0xc3fd _c064 me_ps1 r0 s_swg 000 s_crc 00000 0 0 0 s_lin_flex1 s_lin_flex0 w r0 0 0 0 0 s_flexpwm1 s_flexpwm0 s_etimer2 s_etimer1 s_etimer0 00 s_ctu 0 s_adc1 s_adc0 w 0xc3fd _c068 me_ps2 r0 0 0 s_pit 0000000 00000 w r0 0 0 0 0000000 00000 w table 32-3. mc_me memory map (continued) address name 012327 567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
mode entry module (mc_me) 32-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 32.3.2 register description unless otherwise noted, all registers may be accessed as 32-bit word s, 16-bit half-words, or 8-bit bytes. the bytes are ordered accor ding to big endian. for example, the me_run_pc0 register may be accessed as a word at address 0xc3fd_c080, as a half-word at address 0xc3f d_c082, or as a byte at address 0xc3fd_c083. 0xc3fd _c06c reserved 0xc3fd _c070 reserved 0xc3fd _c074 ? 0xc3fd _c07c reserved 0xc3fd _c080 ? 0xc3fd _c09c me_run_pc 0?7 r0 0 0 0 0000000 00000 w r0 0 0 0 0000 run3 run2 run1 run0 drun safe test reset w 0xc3fd _c0a0 ? 0xc3fd _c0bc me_lp_pc0 ?7 r0 0 0 0 0000000 00000 w r0 0 0 0 0 stop0 0 halt0 00000000 w 0xc3fd _c0c0 ? 0xc3fd _c14c me_pctl0? 143 1 r0 dbg_f lp_cfg run_cfg 0 dbg_f lp_cfg run_cfg w r0 dbg_f lp_cfg run_cfg 0 dbg_f lp_cfg run_cfg w 0xc3fd _c150 ? 0xc3fd _fffc reserved notes: 1 there is space in the register map for 144 peripherals. please see table 32-2 for the me_pctln locations actually occupied. the unoccupied locations contain a read-only byte value of 0x00. table 32-3. mc_me memory map (continued) address name 012327 567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
mode entry module (mc_me) freescale semiconductor 32-13 pxs20 microcontroller reference manual, rev. 1 32.3.2.1 global status register (me_gs) this register contains global mode status. address 0xc3fd_c000 access: user read, supervisor read, test read 0123456789101112131415 r s_current_mode s_mtrans 100 s_pdo 00 s_mvr reserved s_fla w reset0000110000011111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r s_pll1 s_pll0 s_xosc s_ircosc s_sysclk w reset0000000000010000 figure 32-2. global status register (me_gs) table 32-4. global status register (me_gs) field descriptions field description s_curren t_mode current device mode status 0000 reset 0001 test 0010 safe 0011 drun 0100 run0 0101 run1 0110 run2 0111 run3 1000 halt0 1001 reserved 1010 stop0 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved s_mtrans mode transition status 0 mode transition process is not active 1 mode transition is ongoing s_pdo output power-down status ? this bit specifies output power-down status of i/os. this bit is asserted whenever outputs of pads are forced to high impedance state or the pads power sequence driver is switched off. 0 no automatic safe gating of i/os used and pads power sequence driver is enabled 1 in safe/test modes, outputs of pads are forc ed to high impedance state and the pads power sequence driver is disabled. the inputs are level unchanged. in stop0 mode, only the pad power sequence driver is disabled, but the st ate of the output remains functional.
mode entry module (mc_me) 32-14 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 s_mvr main voltage regulator status 0 main voltage regulator is not ready 1 main voltage regulator is ready for use s_fla flash availability status 00 flash is not available 01 flash is in power-down mode 10 flash is in low-power mode 11 flash is in normal mode and available for use s_ssclk1 secondary system clock source 1 status 0 secondary system clock source 1 is not stable 1 secondary system clock source 1 is providing a stable clock s_pll1 secondary fmpll status 0 secondary fmpll is not stable 1 secondary fmpll is providing a stable clock s_pll0 system fmpll status 0 system fmpll is not stable 1 system fmpll is providing a stable clock s_xosc 4-40 mhz crystal oscillator status 0 4-40 mhz crystal oscillator is not stable 1 4-40 mhz crystal oscillator is providing a stable clock s_ircosc 16 mhz internal rc oscillator status 0 16 mhz internal rc oscillator is not stable 1 16 mhz internal rc oscillator is providing a stable clock s_sysclk system clock switch status ? these bits specify the system clock currently used by the system. 0000 16 mhz int. rc osc. 0001 reserved 0010 4?40 mhz crystal osc. 0011 reserved 0100 system fmpll 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 system clock is disabled table 32-4. global status register (m e_gs) field descriptions (continued) field description
mode entry module (mc_me) freescale semiconductor 32-15 pxs20 microcontroller reference manual, rev. 1 32.3.2.2 mode control register (me_mctl) this register is used to trigger software-controlle d mode changes. depending on the modes as enabled by me_me register bits, configurati ons corresponding to unavailable mo des are reserved and access to me_< mode >_mc registers must respect this for successful mode requests. note byte and half-word write accesses are not allowed fo r this register as a predefined key is required to change its value. address 0xc3fd_c004 access: user read, super visor read/write, test read/write 0123456789101112131415 r ta r g e t _ m o d e 000000000000 w reset0011000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r1010010100001111 w key reset1010010100001111 figure 32-3. mode control register (me_mctl) table 32-5. mode control register (me_mctl) field descriptions field description ta r g e t _ m ode t arget device mode ? these bits provide the target device mode to be entered by software programming. the mechanism to ente r into any mode by software requires the write operation twice: first time with key, and second time with inverted key. these bits are automatically updated by hardware while entering safe on hardware request. also, while exiting from the halt0 and stop0 modes on hardware exit events, these are updated with the appropriate run0?3 mode value. 0000 reset 0001 test 0010 safe 0011 drun 0100 run0 0101 run1 0110 run2 0111 run3 1000 halt0 1001 reserved 1010 stop0 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 cut1: reserved cut2/3: reset (triggers a ?destructive? reset event) key control key ? these bits enable write access to this re gister. any write access to the register with a value different from the keys is ignored. read access will always return inverted key. key:0101101011110000 (0x5af0) inverted key:1010010100001111 (0xa50f)
mode entry module (mc_me) 32-16 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 32.3.2.3 mode enable register (me_me) this register allows a way to di sable the device modes which are not required for a given device. reset (for cut1), reset_dest & reset_func (for cu t2/3), safe, drun, and run0 modes are always enabled. address 0xc3fd_c008 access: user read, super visor read/write, test read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000 stop0 0 halt0 run3 run2 run1 run0 drun safe test reset (cut1) w reset0000000000011101 figure 32-4. mode enable register (me_me) for cut1 address 0xc3fd_c008 access: user read, super visor read/write, test read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r reset_dest 0000 stop0 0 halt0 run3 run2 run1 run0 drun safe test reset_func (cut2/3) w reset1000000000011101 figure 32-5. mode enable register (me_me) for cut2/3 table 32-6. mode enable register (me_me) field descriptions field description reset_dest (cut2/3 only) ?destructive? reset mode enable 1 ?destructive? reset mode is enabled stop0 stop0 mode enable 0 stop0 mode is disabled 1 stop0 mode is enabled
mode entry module (mc_me) freescale semiconductor 32-17 pxs20 microcontroller reference manual, rev. 1 32.3.2.4 interrupt status register (me_is) halt0 halt0 mode enable 0 halt0 mode is disabled 1 halt0 mode is enabled run3 run3 mode enable 0 run3 mode is disabled 1 run3 mode is enabled run2 run2 mode enable 0 run2 mode is disabled 1 run2 mode is enabled run1 run1 mode enable 0 run1 mode is disabled 1 run1 mode is enabled run0 run0 mode enable 0 run0 mode is disabled 1 run0 mode is enabled drun drun mode enable 0 drun mode is disabled 1 drun mode is enabled safe safe mode enable 0 safe mode is disabled 1 safe mode is enabled test test mode enable 0 test mode is disabled 1 test mode is enabled reset (cut1) reset mode enable 0 reset mode is disabled 1 reset mode is enabled reset_func (cut2/3) ?functional? reset mode enable 1 ?functional? reset mode is enabled address 0xc3fd_c00c access: user read, super visor read/write, test read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000000000 i_iconf i_imode i_safe i_mtc w w1c w1c w1c w1c reset0000000000000000 figure 32-6. interrupt status register (me_is) for cut1 table 32-6. mode enable register (me_me) field descriptions (continued) field description
mode entry module (mc_me) 32-18 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 this register provides the current interrupt status. address 0xc3fd_c00c access: user read, super visor read/write, test read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000000 i_iconf_cu i_iconf i_imode i_safe i_mtc w w1c w1c w1c w1c w1c reset0000000000000000 figure 32-7. interrupt status register (me_is) for cut2/3 table 32-7. interrupt status register (me_is) field descriptions field description i_iconf_cu (cut2/3 only) invalid mode configuration interrupt (clock usage) ? this bit is set during a mode transition if a clock which is required to be on by an enabled peripher al is configured to be turned off. it is cleared by writing a ?1? to this bit. 0 no invalid mode configuration (clock usage) interrupt occurred 1 invalid mode configuration (clock usage) interrupt is pending i_iconf invalid mode configuration interrupt ? this bit is set whenever a write operation to me_< mode >_mc registers with invalid mode configuration is attempted. it is cleared by writing a ?1? to this bit. 0 no invalid mode configuration interrupt occurred 1 invalid mode configuration interrupt is pending i_imode invalid mode interrupt ? this bit is set whenever an invalid mode transition is requested. it is cleared by writing a ?1? to this bit. 0 no invalid mode interrupt occurred 1 invalid mode interrupt is pending i_safe safe mode interrupt ? this bit is set whenever the device enters safe mode on hardware requests generated in the system. it is cleared by writing a ?1? to this bit. 0 no safe mode interrupt occurred 1 safe mode interrupt is pending i_mtc mode transition complete interrupt ? this bit is set whenever the mode transition process completes (s_mtrans transits from 1 to 0). it is cleared by writing a ?1? to this bit. this mode transition interrupt bit will not be set while entering low-power modes halt0, or stop0. 0 no mode transition complete interrupt occurred 1 mode transition complete interrupt is pending
mode entry module (mc_me) freescale semiconductor 32-19 pxs20 microcontroller reference manual, rev. 1 32.3.2.5 interrupt mask register (me_im) this register controls whether an event generates an interrupt or not. address 0xc3fd_c010 access: user read, super visor read/write, test read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000000 m_iconf m_imode m_safe m_mtc w reset0000000000000000 figure 32-8. interrupt mask register (me_im) for cut1 address 0xc3fd_c010 access: user read, super visor read/write, test read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000000 m_iconf_cu m_iconf m_imode m_safe m_mtc w reset0000000000000000 figure 32-9. interrupt mask register (me_im) for cut2/3 table 32-8. interrupt mask register (me_im) field descriptions field description m_conf_cu (cut2/3 only) invalid mode configuration (clock usage) interrupt mask 0 invalid mode interrupt is masked 1 invalid mode interrupt is enabled m_iconf invalid mode configuration interrupt mask 0 invalid mode interrupt is masked 1 invalid mode interrupt is enabled m_imode invalid mode interrupt mask 0 invalid mode interrupt is masked 1 invalid mode interrupt is enabled
mode entry module (mc_me) 32-20 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 32.3.2.6 invalid mode transiti on status register (me_imts) this register provides the stat us bits for the possible causes of an invalid mode interrupt. m_safe safe mode interrupt mask 0 safe mode interrupt is masked 1 safe mode interrupt is enabled m_mtc mode transition comp lete interrupt mask 0 mode transition comple te interrupt is masked 1 mode transition complete interrupt is enabled address 0xc3fd_c014 access: user read, super visor read/write, test read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000000 s_mti s_mri s_dma s_nma s_sea w w1c w1c w1c w1c w1c reset0000000000000000 figure 32-10. invalid mode transition status register (me_imts) table 32-9. invalid mode transition status register (me_imts) field descriptions field description s_mti mode transition illegal status ? this bit is set whenever a new mode is requested while some other mode transition process is active (s_mtrans is ?1?). please refer to section 32.4.5, mode transition interrupts for the exceptions to this behavior. it is cleared by writing a ?1? to this bit. 0 mode transition requested is not illegal 1 mode transition requested is illegal s_mri mode request illegal status ? this bit is set whenever the target mode requested is not a valid mode with respect to current mode. it is cleared by writing a ?1? to this bit. 0 target mode requested is not ille gal with respect to current mode 1 target mode requested is illegal with respect to current mode s_dma disabled mode access status ? this bit is set whenever the target mode requested is one of those disabled modes determined by me_me register. it is cleared by writing a ?1? to this bit. 0 target mode requested is not a disabled mode 1 target mode requested is a disabled mode table 32-8. interrupt mask register (me_im) field descriptions (continued) field description
mode entry module (mc_me) freescale semiconductor 32-21 pxs20 microcontroller reference manual, rev. 1 32.3.2.7 debug mode transition status register (me_dmts) this register provides the status of different factors which influence mode transitions. it is used to give an indication of why a mode tran sition indicated by me_gs.s_mtra ns may be taking longer than expected. note the me_dmts register does not indi cate whether a mode transition is ongoing. therefore, some me_dmts bits may still be asserted after the mode transition has completed. s_nma non-existing mode access status ? this bit is set whenever the target mode requested is one of those non existing modes determined by me_me regist er. it is cleared by writing a ?1? to this bit. 0 target mode request ed is an existing mode 1 target mode requested is a non-existing mode s_sea safe event active status ? this bit is set whenever the device is in safe mode, safe event bit is pending and a new mode request ed other than reset/safe modes. it is cleared by writing a ?1? to this bit. 0 no new mode requested other than reset/safe while safe event is pending 1 new mode requested other than reset/safe while safe event is pending address 0xc3fd_c018 access: user read, super visor read/write, test read/write 0123456789101112131415 r previous_mode 0 0 0 0 mph_busy 00 pmc_prog core_dbg 00 smr w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 vreg_csrc_sc csrc_csrc_sc ircosc_sc scsrc_sc sysclk_sw reserved flash_sc cdp_prph_0_143 00 cdp_prph_64_95 cdp_prph_32_63 cdp_prph_0_31 w reset0000000000000000 figure 32-11. debug mode transition status register (me_dmts) table 32-9. invalid mode transition status regi ster (me_imts) field descriptions (continued) field description
mode entry module (mc_me) 32-22 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 table 32-10. debug mode transition status register (me_dmts) field descriptions field description previous_ mode previous device mode ? these bits show the mode in which the device was prior to the latest change to the current mode. 0000 reset 0001 test 0010 safe 0011 drun 0100 run0 0101 run1 0110 run2 0111 run3 1000 halt0 1001 reserved 1010 stop0 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved mph_busy mc_me/mc_pcu handshake busy indicator ? this bit is set if the mc_me has requested a mode change from the mc_pcu and the mc_pcu has not yet responded. it is cleared when the mc_pcu has responded. 0 handshake is not busy 1 handshake is busy pmc_prog mc_pcu mode change in progress indicator ? this bit is set if the mc_pcu is in the process of powering up or down power domains. it is cleared when all power-up/down processes have completed. 0 power-up/down transition is not in progress 1 power-up/down transition is in progress core_dbg processor is in debug mode indicator ? this bit is set while the processor is in debug mode. 0 the processor is not in debug mode 1 the processor is in debug mode smr safe mode request from mc_rgm is active indica tor ? this bit is set if a hardware safe mode request has been triggered. it is cleared when the hardware safe mode request has been cleared. 0 a safe mode request is not active 1 a safe mode request is active vreg_csr c_sc main vreg dependent clock source state change during mode transition indicator ? this bit is set when a clock source which depends on the main voltage regulator to be powered-up is requested to change its power up/down state. it is cleared when the clock source has co mpleted its state change. 0 no state change is taking place 1 a state change is taking place csrc_csr c_sc (other) clock source dependent clock source state change during mode transition indicator ? this bit is set when a clock source which depends on ano ther clock source to be powered-up is requested to change its power up/down state. it is cleared when the clock source has completed its state change. 0 no state change is taking place 1 a state change is taking place ircosc_sc ircosc state change during mode transition indicator ? this bit is set when the 16 mhz internal rc oscillator is requested to change its power up/dow n state. it is cleared when the 16 mhz internal rc oscillator has completed its state change. 0 no state change is taking place 1 a state change is taking place
mode entry module (mc_me) freescale semiconductor 32-23 pxs20 microcontroller reference manual, rev. 1 scsrc_sc secondary clock sources state change during mode transition indicator ? this bit is set when a secondary clock source is requested to change its power up/down state. it is cleared when all secondary system clock sources have completed thei r state changes. (a ?secondary clock source? is a clock source other than ircosc.) 0 no state change is taking place 1 a state change is taking place sysclk_s w system clock switching pending status ? 0 no system clock source switching is pending 1 a system clock source switching is pending flash_sc flash state change during mode transition indi cator ? this bit is set when the flash is requested to change its power up/down state. it is cleared when the dflash has completed its state change. 0 no state change is taking place 1 a state change is taking place cdp_prph _0_143 clock disable process pending status for peripherals 0?143 1 ? this bit is set when any peripheral has been requested to have its clock disabled. it is cleared when all the peripherals which have been requested to have their clocks disabled have entered the state in which their clocks may be disabled. 0 no peripheral clock disabling is pending 1 clock disabling is pending for at least one peripheral cdp_prph _64_95 clock disable process pending status for peripherals 64?95 1 ? this bit is set when any peripheral appearing in me_ps2 has been requested to have it s clock disabled. it is cleared when all these peripherals which have been requested to have their clocks disabled have entered the state in which their clocks may be disabled. 0 no peripheral clock disabling is pending 1 clock disabling is pending for at least one peripheral cdp_prph _32_63 clock disable process pending status for peripherals 32?63 1 ? this bit is set when any peripheral appearing in me_ps1 has been requested to have it s clock disabled. it is cleared when all these peripherals which have been requested to have their clocks disabled have entered the state in which their clocks may be disabled. 0 no peripheral clock disabling is pending 1 clock disabling is pending for at least one peripheral cdp_prph _0_31 clock disable process pending status for peripherals 0?31 1 ? this bit is set when any peripheral appearing in me_ps0 has been requested to have it s clock disabled. it is cleared when all these peripherals which have been requested to have their clocks disabled have entered the state in which their clocks may be disabled. 0 no peripheral clock disabling is pending 1 clock disabling is pending for at least one peripheral notes: 1 for cut2/3: peripheral n corresponds to the me_pctl n register. please see ta b l e 3 2 - 2 for the me_pctl n locations actually occupied, which in turn indicates wh ich peripherals are reported in th e me_dmts registe r. table 32-10. debug mode transition status regi ster (me_dmts) field descriptions (continued) field description
mode entry module (mc_me) 32-24 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 32.3.2.8 reset mode configuration register (me_reset_mc) this register configures system behavi or during reset mode. please refer to table 32-11 for details. 32.3.2.9 test mode configuration register (me_test_mc) this register configures system beha vior during test mode. please refer to table 32-11 for details. note byte write accesses are not allowed to this register. address 0xc3fd_c020 access: user read, super visor read/write, test read/write 0123456789101112131415 r 00000000pdo00 mvron reserved flaon w reset0000000000011111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pll1on pll0on xoscon ircoscon sysclk w reset0000000000010000 figure 32-12. reset m ode configuration register (me_reset_mc) address 0xc3fd_c024 access: user read, super visor read/write, test read/write 0123456789101112131415 r 00000000 pdo 00 mvron reserved flaon w reset0000000000011111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000 pll1on pll0on xoscon ircoscon sysclk w reset0000000000010000 figure 32-13. test mode configuration register (me_test_mc)
mode entry module (mc_me) freescale semiconductor 32-25 pxs20 microcontroller reference manual, rev. 1 32.3.2.10 safe mode configuration register (me_safe_mc) this register configures system behavi or during safe mode. please refer to table 32-11 for details. note byte write accesses are not allowed to this register. 32.3.2.11 drun mode configuration register (me_drun_mc) this register configures system beha vior during drun mode. please refer to table 32-11 for details. note byte write accesses are not allowed to this register. address 0xc3fd_c028 access: user read, super visor read/write, test read/write 0123456789101112131415 r 00000000 pdo 00 mvron reserved flaon w reset0000000010011111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pll1on pll0on xoscon ircoscon sysclk w reset0000000000010000 figure 32-14. safe mode confi guration register (me_safe_mc) address 0xc3fd_c02c access: user read, super visor read/write, test read/write 0123456789101112131415 r 00000000pdo00 mvron reserved flaon w reset0000000000011111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000 pll1on pll0on xoscon ircoscon sysclk w reset0000000000010000 figure 32-15. drun mode configuration register (me_drun_mc)
mode entry module (mc_me) 32-26 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 32.3.2.12 run0?3 mode configuration registers (me_run0 ? 3_mc) this register configures system behavior during run 0?3 modes. please refer to table 32-11 for details. note byte write accesses are not allowed to this register. 32.3.2.13 halt0 mode configuration register (me_halt0_mc) this register configures system beha vior during halt0 mode. please refer to table 32-11 for details. note byte write accesses are not allowed to this register. address 0xc3fd_c030 - 0xc3fd_c03c access: user read, supervisor read/write, test read/write 0123456789101112131415 r 00000000pdo00 mvron reserved flaon w reset0000000000011111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000 pll1on pll0on xoscon ircoscon sysclk w reset0000000000010000 figure 32-16. run0?3 mode confi guration registers (me_run0?3_mc) address 0xc3fd_c040 access: user read, super visor read/write, test read/write 0123456789101112131415 r 00000000pdo00 mvron reserved flaon w reset0000000000011010 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000 pll1on pll0on xoscon ircoscon sysclk w reset0000000000010000 figure 32-17. halt0 mode confi guration register (me_halt0_mc)
mode entry module (mc_me) freescale semiconductor 32-27 pxs20 microcontroller reference manual, rev. 1 32.3.2.14 stop0 mode configuration re gister (me_stop0_mc) this register configures system behavi or during stop0 mode. please refer to table 32-11 for details. note byte write accesses are not allowed to this register. address 0xc3fd_c048 access: user read, super visor read/write, test read/write 0123456789101112131415 r 00000000 pdo 00 mvron reserved flaon w reset0000000000010101 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000 pll1on pll0on xoscon ircoscon sysclk w reset0000000000010000 figure 32-18. stop0 mode configuration register (me_stop0_mc) table 32-11. mode configuration registers (me_< mode >_mc) field descriptions field description pdo i/o output power-down control ? this bit controls the output power-down of i/os. 0 no automatic safe gating of i/os used and pads power sequence driver is enabled 1 in safe/test modes, outputs of pads are fo rced to high impedance state and pads power sequence driver is disabled. the inputs are leve l unchanged. in stop0 mode, only the pad power sequence driver is disabled, but the st ate of the output remains functional. mvron main voltage regulator control ? this bit specifies whether main voltage regulator is switched off or not while entering this mode. 1 main voltage regulator is switched on flaon flash power-down control ? this bit specifies the operating mode of the code flash after entering this mode. 00 reserved 01 flash is in power-down mode 10 flash is in low-power mode 11 flash is in normal mode pll1on secondary fmpll control 0 secondary fmpll is switched off 1 secondary fmpll is switched on pll0on system fmpll control 0 system fmpll is switched off 1 system fmpll is switched on xoscon 4-40 mhz crystal oscillator control 0 4-40 mhz crystal oscillator is switched off 1 4-40 mhz crystal oscillator is switched on
mode entry module (mc_me) 32-28 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 32.3.2.15 peripheral status register 0 (me_ps0) this register provides the status of the peripherals. please refer to table 32-12 for details. ircoscon 16 mhz internal rc oscillator control 0 16 mhz internal rc oscillator is switched off 1 16 mhz internal rc oscillator is switched on sysclk system clock switch control ? these bits specify the system clock to be used by the system. 0000 16 mhz int. rc osc. 0001 reserved 0010 4?40 mhz crystal osc. 0011 reserved 0100 system fmpll 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 system clock is disabled in test mode, reserved in all other modes address 0xc3fd_c060 access: user read, supervisor read, test read 0123456789101112131415 r s_flexray s_flexcan1 s_flexcan0 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r s_dspi2 s_dspi1 s_dspi0 w reset0000000000000000 figure 32-19. peripheral status register 0 (me_ps0) table 32-11. mode configuration registers (me_< mode >_mc) field descriptions (continued) field description
mode entry module (mc_me) freescale semiconductor 32-29 pxs20 microcontroller reference manual, rev. 1 32.3.2.16 peripheral status register 1 (me_ps1) this register provides the status of the peripherals. please refer to table 32-12 for details. 32.3.2.17 peripheral status register 2 (me_ps2) this register provides the status of the peripherals. please refer to table 32-12 for details. address 0xc3fd_c064 access: user read, supervisor read, test read 0123456789101112131415 r s_swg s_crc s_lin_flex1 s_lin_flex0 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r s_flexpwm1 s_flexpwm0 s_etimer2 s_etimer1 s_etimer0 s_ctu s_adc1 s_adc0 w reset0000000000000000 figure 32-20. peripheral status register 1 (me_ps1) address 0xc3fd_c068 access: user read, supervisor read, test read 0123456789101112131415 r s_pit w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r w reset0000000000000000 figure 32-21. peripheral status register 2 (me_ps2)
mode entry module (mc_me) 32-30 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 32.3.2.18 run peripheral configuration registers (me_run_pc0 ? 7) these registers configure eight different t ypes of peripheral behavior during run modes. table 32-12. peripheral status registers 0?4 (me_ps0?4) field descriptions field description s_ peripheral status ? these bits specify the cu rrent status of the periph erals in the system. if no peripheral is mapped on a particular position (i.e. the corresponding mods bit is ?0?), the corresponding bit is always read as ?0?. 0 peripheral is frozen 1 peripheral is active address 0xc3fd_c080 - 0xc3fd_c09c access: user read, supervisor read/wr ite, test read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000 run3 run2 run1 run0 drun safe test reset w reset0000000000000000 figure 32-22. run peripheral config uration registers (me_run_pc0?7) table 32-13. run peripheral configuration re gisters (me_run_pc0?7) field descriptions field description run3 peripheral control during run3 0 peripheral is frozen with clock gated 1 peripheral is active run2 peripheral control during run2 0 peripheral is frozen with clock gated 1 peripheral is active run1 peripheral control during run1 0 peripheral is frozen with clock gated 1 peripheral is active run0 peripheral control during run0 0 peripheral is frozen with clock gated 1 peripheral is active drun peripheral control during drun 0 peripheral is frozen with clock gated 1 peripheral is active safe peripheral control during safe 0 peripheral is frozen with clock gated 1 peripheral is active
mode entry module (mc_me) freescale semiconductor 32-31 pxs20 microcontroller reference manual, rev. 1 32.3.2.19 low-power peripheral conf iguration registers (me_lp_pc0 ? 7) these registers configure eight different types of periphera l behavior during non-run modes. 32.3.2.20 peripheral control registers (me_pctl0 ? 143) these registers select the conf igurations during run and non-run modes for each peripheral. test peripheral control during test 0 peripheral is frozen with clock gated 1 peripheral is active reset peripheral control during reset 0 peripheral is frozen with clock gated 1 peripheral is active address 0xc3fd_c0a0 - 0xc3fd_c0bc access: user read, supervisor read/wr ite, test read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000 stop0 0 halt0 00000000 w reset0000000000000000 figure 32-23. low-power peripheral configuration registers (me_lp_pc0?7) table 32-14. low-power peripheral configuratio n registers (me_lp_pc0?7) field descriptions field description stop0 peripheral control during stop0 0 peripheral is frozen with clock gated 1 peripheral is active halt0 peripheral control during halt0 0 peripheral is frozen with clock gated 1 peripheral is active address 0xc3fd_c0c0 - 0xc3fd_c14f access: user read, supervisor read/wr ite, test read/write 01234567 r 0 dbg_f lp_cfg run_cfg w reset00000000 figure 32-24. peripheral control registers (me_pctl0?143) table 32-13. run peripheral configuration register s (me_run_pc0?7) field descriptions (continued) field description
mode entry module (mc_me) 32-32 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 note after modifying any of the me_run_pc0?7, me_lp_pc0?7, and me_pctl n registers, software must request a mode change and wait for the mode change to be completed before entering debug mode in order to have consistent behavior between the peri pheral clock control process and the clock status reporting in the me_ps n registers. 32.4 functional description 32.4.1 mode transition request the transition from one mode to another mode is normally handled by software by accessing the mode control register me_mctl. but the in case of special events, the mode transition can be automatically managed by hardware. in order to switch from one mode to another, the application should access the me_mctl register twice by writing ? the first time with the value of the key (0x5af0) into the key bit field and the required target mode into the target_mode bit field, ? and the second time with the inverted value of the key (0xa50f) into the key bit field and the required target mode into the target_mode bit field. table 32-15. peripheral control registers (me_pctl0?143) field descriptions field description dbg_f peripheral control in debug mode ? this bit controls the state of the peripheral in debug mode 0 peripheral state depends on run_cfg/lp_cfg bits and the device mode 1 peripheral is frozen if not already frozen in device modes. note: this feature is useful to freeze the peripheral state while entering debug. for example, this may be used to prevent a reference timer from running while making a debug accesses. lp_cfg peripheral configuration select for non-run modes ? these bits associate a configuration as defined in t he me_lp_pc0?7 reg isters to the peripheral. 000 selects me_lp_pc0 configuration 001 selects me_lp_pc1 configuration 010 selects me_lp_pc2 configuration 011 selects me_lp_pc3 configuration 100 selects me_lp_pc4 configuration 101 selects me_lp_pc5 configuration 110 selects me_lp_pc6 configuration 111 selects me_lp_pc7 configuration run_cfg peripheral configuration select for run modes ? these bits associate a configuration as defined in the me_run_pc0 ? 7 registers to the peripheral. 000 selects me_run_pc0 configuration 001 selects me_run_pc1 configuration 010 selects me_run_pc2 configuration 011 selects me_run_pc3 configuration 100 selects me_run_pc4 configuration 101 selects me_run_pc5 configuration 110 selects me_run_pc6 configuration 111 selects me_run_pc7 configuration
mode entry module (mc_me) freescale semiconductor 32-33 pxs20 microcontroller reference manual, rev. 1 once a valid mode transition request is detected, the ta rget mode configuration in formation is loaded from the corresponding me_< mode >_mc register. the mode transition re quest may require a number of cycles depending on the programmed configuration, and so ftware should check the s_current_mode bit field and the s_mtrans bit of the global status regist er to verify when the mode has been correctly entered and the transition pr ocess has completed. for a description of valid mode requests, please refer to section 32.4.5, mode transition interrupts . any modification of the mode configur ation register of the currently sel ected mode will not be taken into account immediately but on th e next request to enter this mode. th is means that transition requests such as run0?3 ? run0?3, drun ? drun, safe ? sa fe, and test ? test are considered valid mode transition requests. as soon as the mode request is accepted as valid, the s_mtrans bit is set till the status in the register matches the c onfiguration programmed in the respective me_< mode >_mc register. note it is recommended that software poll the s_mtrans bit in the register after requesting a transition to halt0 or stop0 modes. safe drun test reset run0 run1 halt0 stop0 system modes user modes software request non-recoverable failure run2 run3 recoverable hardware failure figure 32-25. mc_me mode diagram
mode entry module (mc_me) 32-34 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 32.4.2 mode details 32.4.2.1 reset mode the device enters this m ode on the following events: ? from safe, drun, run0?3, or test mode wh en the target_mode bit field of the me_mctl register is written with: ? cut1: ?0000? ? cut2/3: either ?0000? for a ?functional? reset or ?1111? for a ?destructive? reset ? from any mode due to a system reset by the mc _rgm because of some non-recoverable hardware failure in the system (see the mc_rgm chapter for details) transition to this mode is instantaneous, and the syst em remains in this mode until the reset sequence is finished. the mode configuration information for th is mode is provided by the me_reset_mc register. this mode has a pre-defined configur ation, and the 16 mhz int. rc osc. is selected as the system clock. 32.4.2.2 drun mode the device enters this m ode on the following events: ? automatically from reset mode after completion of the reset sequence ? from run0?3, safe, or test mode when th e target_mode bit field of the me_mctl register is written with ?0011? as soon as any of the above events has occurred, a drun mode transi tion request is generated. the mode configuration information for this mode is provid ed by the me_drun_mc register. in this mode, the flash, all clock sources, and the system clock configuration can be contro lled by software as required. after system reset, the software execution starts with the default configurati on selecting the 16 mhz int. rc osc. as the system clock. this mode is intended to be used by software ? to initialize all registers as per the system needs note software must ensure that the code executes from ram before changing to this mode if the flash is configured to be in the low-power or power-down state in this mode. 32.4.2.3 safe mode the device enters this m ode on the following events: ? from drun, run0?3, or test mode when th e target_mode bit field of the me_mctl register is written with ?0010? ? from any mode except reset due to a safe mode request ge nerated by the mc_rgm because of some potentially rec overable hardware failure in the sy stem (see the mc_rgm chapter for details)
mode entry module (mc_me) freescale semiconductor 32-35 pxs20 microcontroller reference manual, rev. 1 note for cut2/3: if a hardware safe mode request occurs during reset, depending on the timing of the safe mode request, safe mode may be entered immediately after the normal completion of the reset sequence or several system clock cycles after drun entry. the safe mode request does not have any influence on the ex ecution of the reset sequence itself. as soon as any of the above events has occurred, a safe m ode transition request is generated. the mode configuration information for this mode is provid ed by the me_safe_mc register. this mode has a pre-defined configuration, and the 16 mhz int. rc osc. is selected as the system clock. if the safe mode is requested by software while some other mode transitio n process is ongoing, the new target mode becomes the safe mode regardless of other pending requests or new requests during the mode transition. no new mode request made during a tr ansition to the safe mode will cause an invalid mode interrupt. note if software requests to change to th e safe mode and then requests to change back to the parent mode before the mode tr ansition is completed, the device?s final mode after mode tr ansition will be the safe mode. as long as a safe event is active, the system rema ins in the safe mode, and any software mode request during this time is ignored and lost. this mode is intended to be used by software ? to assess the severity of the cause of failure and then to either ? re-initialize the device via the drun mode, or ? completely reset the devi ce via the reset mode. if the outputs of the system i/os n eed to be forced to a high impeda nce state upon entering this mode, the pdo bit of the me_safe_mc register should be set. the input levels remain unchanged. 32.4.2.4 test mode the device enters this m ode on the following events: ? from the drun mode when the target_mode bi t field of the me_mctl register is written with ?0001? as soon as any of the above events has occurred, a test mode transition request is generated. the mode configuration information for this mode is provided by the me_test_mc register. except for the main voltage regulator, all resource s of the system are configurable in th is mode. the system clock to the whole system can be stopped by programming th e sysclk bit field to ?1111?, a nd in this case, the only way to exit this mode is via a device reset. this mode is intended to be used by software ? to execute software test routines
mode entry module (mc_me) 32-36 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 note software must ensure that the code executes from ram before changing to this mode if the flash is configured to be in the low-power or power-down state in this mode. 32.4.2.5 run0?3 modes the device enters one of thes e modes on the following events: ? from the drun, safe, or another run0?3 mode when th e target_mode bit field of the me_mctl register is written with ?0100?0111? ? from the halt0 mode due to an interrupt event ? from the stop0 mode due to an interrupt or wakeup event as soon as any of the above events has occurred, a run0?3 mode transition request is generated. the mode configuration information fo r these modes is provided by the me_run0?3_mc registers. in these modes, the flash, all clock sources, and the system cl ock configuration can be c ontrolled by software as required. these modes are intended to be used by software ? to execute application routines note software must ensure that the code executes from ram before changing to this mode if the flash is configured to be in the low-power or power-down state in this mode. 32.4.2.6 halt0 mode the device enters this m ode on the following events: ? from one of the run0?3 modes when the targ et_mode bit field of the me_mctl register is written with ?1000?. as soon as any of the above events has occurred, a halt0 mode transi tion request is generated. the mode configuration information for this mode is provid ed by me_halt0_mc register. this mode is quite configurable, and the me_halt0_mc register should be programmed according to the system needs. the flash can be put in low-power or power-down mode as ne eded. if there is a halt0 mode request while an interrupt request is active, the transition to halt0 is a borted with the resultant mode being the current mode, safe (on safe mode request) , or drun (on reset), and an invalid mode interrupt is not generated. this mode is intended as a first-level low-power mode with ? the core clock frozen ? only a few peripherals running and to be used by software ? to wait until it is require d to do something and then to react qui ckly (i.e. within a few system clock cycles of an interrupt event)
mode entry module (mc_me) freescale semiconductor 32-37 pxs20 microcontroller reference manual, rev. 1 32.4.2.7 stop0 mode the device enters this m ode on the following events: ? from one of the run0?3 modes when the targ et_mode bit field of the me_mctl register is written with ?1010?. as soon as any of the above events has occurred, a stop0 mode transi tion request is generated. the mode configuration information for this mode is provided by the me_stop0_mc register. this mode is fully configurable, and the me_stop0_mc register should be programmed according to the system needs. the following clock sources are switched off in this mode: ? the system fmpll ? the secondary fmpll the flash can be put in pow er-down mode as needed. if there is a stop0 mode request while any interrupt or wakeup event is active, the transition to stop0 is aborted with the resultant mode being the current mode, safe (on safe mode request) , or drun (on reset), and an invalid mode interrupt is not generated. this can be used as an advanced low-power mode wi th the core clock frozen and almost all peripherals stopped. this mode is intended as an advanced low-power mode with ? the core clock frozen ? almost all peripherals stopped and to be used by software ? to wait until it is required to do something with no need to react quickly (e.g. allow for system clock source to be re-started) this mode can be used to stop all clock sources an d thus preserve the device status. when exiting the stop0 mode, the 16 mhz internal rc os cillator clock is select ed as the system clock until the target clock is available. note for cut2/3: it is good practice for software to ensure that the s_mtrans bit in the register has been cleared on stop0 mode exit to ensure that the previous run0?3 mode c onfiguratoin has been fully restored before executing critical code. 32.4.3 mode transition process the process of mode transition follows the follow ing steps in a pre-defined manner depending on the current device mode and the requested target mode. in many cases of m ode transition, not all steps need to be executed based on the mode c ontrol information, and some steps ma y not be applicable according to the mode definition itself.
mode entry module (mc_me) 32-38 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 32.4.3.1 target mode request the target mode is requested by accessing the me_m ctl register with the required keys. this mode transition request by software must be a valid request satisfying a set of pre-defined rules to initiate the process. if the request fails to satisfy these rules, it is ignored, and the ta rget_mode bit field is not updated. an optional interrupt can be generated for invali d mode requests. refer to section 32.4.5, mode transition interrupts for details. in the case of mode transitions occurring because of ha rdware events such as a reset, a safe mode request, or interrupt requests and wakeup ev ents to exit from low-power modes, the target_mode bit field of the me_mctl register is automatically updated with the appropriate target mode. the mode change process start is indicated by the se tting of the mode transition status bit s_mtrans of the register. a reset mode requested via the me_mctl register is passed to the mc_rgm, which generates a global system reset and initiates th e reset sequence. the reset mode re quest has the highest priority, and the mc_me is kept in the reset mode during the entire reset sequence. the safe mode request has the next hi ghest priority after reset. it can be generated either by software via the me_mctl register from all software r unning modes including drun, run0?3, and test or by the mc_rgm after the detection of system hardware failures, which may occur in any mode. 32.4.3.2 target mode configuration loading on completion of the target mode request step, the target mode configuration from the me_< target mode >_mc register is loaded to start the res ources (voltage sources, clock sources, flash, pads, etc.) co ntrol process. an overview of resource control possibili ties for each mode is shown in . a ? ? ? indicates that a given resource is configurable for a given mode. table 32-16. mc_me resource control overview resourc e mode reset test safe drun run0?3 halt0 stop0 ircosc ? ?? on on on on on on on xosc ? ???? off off offoffoffoffoff pll0 ? ??? off off offoffoffoff off pll1 ? ???? off off offoffoffoffoff flash ? ???? normal normal normal normal normal low-power power- down
mode entry module (mc_me) freescale semiconductor 32-39 pxs20 microcontroller reference manual, rev. 1 32.4.3.3 peripheral clocks disable on completion of the target mode request step, the mc_me requests each peripheral to enter its stop mode when: ? the peripheral is configured to be disabled via the target mode, the peripheral configuration registers me_run_pc0?7 and me_lp_pc0?7, and the peripheral control registers me_pctl0?143 caution for cut1: the mc_me does not automati cally request peripherals to enter their stop modes if the power domains in which they are residing are to be turned off due to a mode change. theref ore, it is software?s responsibility to ensure that those peripherals that are to be powered down are configured in the mc_me to be frozen. note for cut2/3: the mc_me automatically requests peripherals to enter their stop modes if the power domai ns in which they are residing are to be turned off due to a mode change. however, it is good practice for software to ensure that those peripherals that are to be powered down are configured in the mc_me to be frozen. each peripheral acknowledges its stop mode request after clos ing its internal activity. the mc_me then disables the corresponding clock(s) to this peripheral. in the case of a safe mode transition request, the mc_me does not wait for the peripherals to acknowledge the stop requests. the safe mode cloc k gating configuration is applied immediately regardless of the status of the peripherals? stop acknowledges. please refer to section 32.4.6, peripheral clock gating for more details. each peripheral that may block or disrupt a communication bus to which it is connected ensures that these outputs are forced to a safe or recessive st ate when the device enters the safe mode. mvreg ?? on on on on on on on pdo ?? ? off off on off off off off table 32-16. mc_me resource control overview (continued) resourc e mode reset test safe drun run0?3 halt0 stop0
mode entry module (mc_me) 32-40 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 32.4.3.4 processor low-power mode entry if, on completion of the peripheral clocks disable step, the mode transition is to the halt0 mode, the mc_me requests the processor to ente r its halted state. the processor acknowledges its halt state request after completing all outst anding bus transactions. if, on completion of the peripheral clocks disable step, the mode transition is to the stop0 mode, the mc_me requests the processor to en ter its stopped state. the processo r acknowledges its st op state request after completing all outst anding bus transactions. 32.4.3.5 processor and syst em memory clock disable if, on completion of the processor low-power mode entry step, the mode transition is to the halt0 or stop0 mode and the processor is in its appropriate halted or stopped state, the mc_me disables the processor and system memory clocks to achieve further power saving. the clocks to the processor and system memory are unaffected while transi tioning between software running modes such as drun, run0?3, and safe. caution clocks to the whole device including th e processor and system memory can be disabled in test mode. 32.4.3.6 clock sources switch-on on completion of the processor low-power mode entry step, the mc_me switch es on all clock sources based on the < clock source >on bits of the me_< current mode >_mc and me_< target mode >_mc registers. the following clock sour ces are switched on at this step: ? the 16 mhz internal rc oscillator ? the 4-40 mhz crystal oscillator ? the system fmpll ? the secondary fmpll the clock sources that are required by the target mode are switched on. the duration required for the output clocks to be stable depends on the type of source, a nd all further steps of mode transition depending on one or more of these clocks waits for the stable st atus of the respective clocks . the availability status of these clocks is updated in the s_< clock source > bits of register. the clock sources which need to be switched off are unaffecte d during this process in order to not disturb the system clock which might require one of these cl ocks before switching to a different target clock. 32.4.3.7 flash module switch-on on completion of the step, if the flash needs to be switched to normal mode from its low-power or power-down mode based on the flaon bit field of the me_< current mode >_mc and me_< target mode >_mc registers, the mc_me requests the flas h to exit from its low-power/power-down mode. when the flash is available fo r access, the s_fla bit field of th e register is updated to ?11? by hardware.
mode entry module (mc_me) freescale semiconductor 32-41 pxs20 microcontroller reference manual, rev. 1 caution it is illegal to switch the flash from low-power mode to power-down mode and from power-down mode to low- power mode. the mc_me, however, does not prevent this nor does it flag it. 32.4.3.8 pad outputs-on on completion of the step, if the pdo bit of the me_< target mode >_mc register is cleared, then ? all pad outputs are enabled to return to their previous state ? the i/o pads power sequence driver is switched on 32.4.3.9 peripheral clocks enable based on the current and target de vice modes, the peripheral c onfiguration registers me_run_pc0?7, me_lp_pc0?7, and the peripheral co ntrol registers me_pctl0?143, th e mc_me enables the clocks for selected modules as required. this step is executed only after the process is completed. 32.4.3.10 processor and memory clock enable if the mode transition is from a ny of the low-power modes halt0 or stop0 to run0?3, the clocks to the processor and system memory are enabled. the pro cess of enabling these cloc ks is executed only after the flash module switch-on process is completed. 32.4.3.11 processor low-power mode exit if the mode transition is from any of the low-power modes halt0 orstop0 to run0?3, the mc_me requests the processor to exit from its halted or stopped state. this step is executed only after the processor and memory clock enable process is completed. 32.4.3.12 system clock switching based on the sysclk bit field of the me_< current mode >_mc and me_< target mode >_mc registers, if the target and current system cl ock configurations differ, the follow ing method is implemented for clock switching. ? the target clock configuration for the 16 mhz int. rc osc. takes effect only after the s_ircosc bit of the register is set by hardware (i.e. the 16 mhz internal rc os cillator has stabilized). ? for cut2/3: the target clock conf iguration for the 4-40 mhz crystal os c. takes effect only after the s_xosc bit of the register is set by hardware (i.e., the 4-40 mhz crystal oscillator has stabilized). ? the target clock configuration fo r the system fmpll takes effect onl y after the s_pll0 bit of the register is set by hardware (i.e. the system fmpll has stabilized). ? if the clock is to be disabled, the sysclk bit field should be programmed with ?1111?. this is possible only in thetest mode.
mode entry module (mc_me) 32-42 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 the current system clock configuration can be obs erved by reading the s_sysclk bit field of the register, which is updated afte r every system clock switch ing. until the target clock is available, the system uses the previous clock configuration. system clock switchi ng starts only after ? the clock sources switch-on process has completed if the target system clock source is one of the following: ? the 16 mhz internal rc oscillator ? the system fmpll ? the peripheral clocks disable process has completed in order not to change the system clock frequency before peripherals cl ose their internal activities an overview of system clock source selection possibilities for each mode is shown in table 32-17 . a ? ? ? indicates that a given clock source is selectable for a given mode. 32.4.3.13 pad switch-off if the pdo bit of the me_< target mode >_mc register is ?1? then ? the outputs of the pads are forced to the high impedance state if the target mode is safe or test this step is executed only after the peripheral clocks disable process has completed. 32.4.3.14 clock sources (with no dependencies) switch-off based on the device mode and the < clock source >on bits of the me_< mode >_mc registers, if a given clock source is to be switched off and no other cl ock source needs it to be on, the mc_me requests the table 32-17. mc_me system clock selection overview system clock source mode reset test safe drun run0?3 halt0 stop0 16 mhz int. rc osc. ? (default) ? (default) ? (default) ? (default) ? (default) ? (default) ? (default) for cut2/3: 4-40 mhz crystal osc ? ???? system fmpll ? ??? system clock is disabled ? ? notes: 1 disabling the system clock during test mode will require a reset in order to exit test mode
mode entry module (mc_me) freescale semiconductor 32-43 pxs20 microcontroller reference manual, rev. 1 clock source to power down and update s its availability status bit s_< clock source > of the register to ?0?. the following clock sources switched off at this step: ? the system fmpll ? the secondary fmpll this step is executed only after the system clock switching process has completed. 32.4.3.15 clock sources (with dependencies) switch-off based on the device mode and the < clock source >on bits of the me_< mode >_mc registers, if a given clock source is to be switched off and all clock sour ces which need this clock s ource to be on have been switched off, the mc_me requests th e clock source to power down and updates its availability status bit s_< clock source > of the register to ?0?. the following clock sources switched off at this step: ? the 16 mhz internal rc oscillator ? the 4-40 mhz crystal oscillator this step is executed only after ? the system clock switching process has completed in order not to lose the current system clock during mode transition ? the clock sources (with no de pendencies) switch-off process has completed in order to, for example, prevent unwanted lock transitions 32.4.3.16 flash switch-off based on the flaon bit field of the me_< current mode >_mc and me_< target mode >_mc registers, if the flash is to be put in its low-power or power- down mode, the mc_me requests the flash to enter the corresponding power mode and waits for the flash to acknowledge. the exact power mode status of the flash is updated in the s_fla bit field of the register. this step is executed only when the processor and system memory clock disable process has completed. 32.4.3.17 current mode update the current mode status bit field s_ current_mode of the register is updated with the target mode bit field target_mode of the me_mctl register when: ? all the updated status bits in the regist er match the configuration specified in the me_< target mode >_mc register ? power sequences are done ? clock disable/enable process is finished ? processor low-power mode (halt/stop) entry and exit processes are finished note for cut2/3: safe mode entry does not wait for the cloc k disable/enable process to finish. it only waits for the me_gs.s_rc bit to be set. this is to ensure that the safe mode is entered as quickly as possible.
mode entry module (mc_me) 32-44 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 software can monitor the mode tran sition status by reading the s_mtrans bit of th e register. the mode transition latency can differ from one mode to anothe r depending on the resources? availability before the new mode request and the ta rget mode?s requirements. if a mode transition is taking longer to complete th an is expected, the me_dmts register can indicate which process is still in progress.
mode entry module (mc_me) freescale semiconductor 32-45 pxs20 microcontroller reference manual, rev. 1 end target mode request write me_mctl register safe mode request interrupt/wakeup event peripheral clocks disable clock sources switch-on system clock switching flash switch-on pad processor low-power processor & pad peripheral clocks enable flash switch-off s_mtrans = ?1? analog on digital control analog off current mode update start s_mtrans = ?0? outputs on outputs off entry processor low-power exit clock disable memory processor & clock enable memory figure 32-26. mc_me transition diagram clock sources without dependencies switch-off clock sources with dependencies switch-off
mode entry module (mc_me) 32-46 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 32.4.4 protection of mode configuration registers while programming the mode c onfiguration registers me_< mode >_mc, the following rules must be respected. otherwise, the write opera tion is ignored and an invalid mode configuration interrupt may be generated. ? if the 16 mhz int. rc osc. is selected as the system clock, ircosc must be on. ? for cut1: ? if pll0on is 1, xoscon must also be 1. ? if pll1on is 1, xoscon must also be 1. ? for cut2/3: ? if the 4-40 mhz crystal osc. clock is sel ected as the system clock, xosc must be on. ? if the system pll clock is selected as the system clock, pll0 must be on. ? if pll0 is on, xosc must also be on. ? if pll1 is on, xosc must also be on. note software must ensure that clock source s with dependencies other than those mentioned above are swithced on as needed. there is no automatic protection mechanism to check this in the mc_me. ? configuration ?00? for the fl aon bit field is reserved. ? system clock configurations marked as ?reserved? may not be selected. ? configuration ?1111? for the sysc lk bit field is allowed only fo r thetest mode, and only in this case may all system clock sources be turned off. caution if the system clock is stopped duri ng test mode, the device can exit only via a system reset. 32.4.5 mode transition interrupts the mc_me provides interrupts for incorrectly c onfiguring a mode, requesting an invalid mode transition, indicating a safe mode tr ansition not due to a software re quest, and indicating when a mode transition has completed. 32.4.5.1 invalid mode configuration interrupt whenever a write operation is attempted to the me_< mode >_mc registers violating the protection rules mentioned in the section 32.4.4, protection of mode configuration registers , the interrupt pending bit i_iconf of the me_is register is set and an interrupt request is generated if the mask bit m_iconf of me_im register is ?1?. for cut2/3: in addition, during a m ode transition, if a cloc k source has been c onfigured in the me_< target mode >_mc register to be off and a pe ripheral requiring this cl ock source to be on ha s been enabled via the me_run_pc0?7/me_lp_pc0?7 and me_pctl n registers, the interrupt pending bit i_iconf_cu
mode entry module (mc_me) freescale semiconductor 32-47 pxs20 microcontroller reference manual, rev. 1 of the me_is register is set and an iterrupt request is generated if the mask bit m_iconf_cu of the me_im register is ?1?. 32.4.5.2 invalid mode transition interrupt the mode transition request is consider ed invalid under the following conditions: ? if the system is in the safe mode and the sa fe mode request from mc_r gm is active, and if the target mode requested is other than reset or safe, then this new mode request is considered to be invalid, and the s_sea bit of the me_imts register is set. ? if the target_mode bit field of the me_mctl re gister is written with a value different from the specified mode values (i.e. a non-existing mode), an invalid m ode transition event is generated. when such a non existing mode is requested, the s_ nma bit of the me_imts re gister is set. this condition is detected regardless of whether the proper key mechan ism is followed while writing the me_mctl register. ? if some of the device modes ar e disabled as programmed in th e me_me register, their respective configurations are considered reserved, and a ny access to the me_mctl register with those values results in an invalid mode transition reques t. when such a disabled mode is requested, the s_dma bit of the me_imts register is set. this condition is detected re gardless of whether the proper key mechanism is followed while writing the me_mctl register. ? if the target mode is not a valid mode with resp ect to the current mode, the mode request illegal status bit s_mri of the me_imts register is set. this conditi on is detected only when the proper key mechanism is followed whil e writing the me_mctl register. otherwise, the write operation is ignored. ? if further new mode requests occu r while a mode transition is in progress (the s_mtrans bit of the register is ?1?), the mode transition illegal status bit s_mti of the me_imts register is set. this condition is detected only when the proper key mechanism is follow ed while writing the me_mctl register. otherwise, the write operation is ignored. note as the causes of invalid mode transiti ons may overlap at the same time, the priority implemented for invalid m ode transition status bits of the me_imts register in the order from hi ghest to lowest is s_sea, s_nma, s_dma, s_mri, and s_mti. as an exception, the mode transition request is not considered as invalid under the following conditions: ? a new request is allowed to enter the reset or safe mode irrespective of the mode transition status. ? as the exit of halt0 and stop 0 modes depends on the interrupts of the syst em which can occur at any instant, these requests to retu rn to run0?3 modes are always valid. ? in order to avoid any unwanted lockup of the devi ce modes, software can abort a mode transition by requesting the parent mode if , for example, the mode transi tion has not completed after a software determined ?reasonable? amount of time for whatever r eason. the parent mode is the device mode before a valid mode request was made.
mode entry module (mc_me) 32-48 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? self-transition requests (e.g. run0 ? run0) are not considered as invalid even when the mode transition process is active (i.e . s_mtrans is ?1?). during the lo w-power mode exit process, if the system is not able to enter the respective ru n0?3 mode properly (i.e. all status bits of the register match with confi guration bits in the me_< mode >_mc register), then software can only request the safe or reset mode. it is not possible to request any ot her mode or to go back to the low-power mode again. whenever an invalid mode request is detected, the interrupt pending bit i_imode of the me_is register is set, and an interrupt request is generated if the mask bit m_imode of the me_im register is ?1?. 32.4.5.3 safe mode transition interrupt whenever the system enters the safe mode as a re sult of a safe mode reque st from the mc_rgm due to a hardware failure, the interrupt pending bit i_safe of the me_is register is set, and an interrupt is generated if the mask bit m_safe of me_im register is ?1?. the safe mode interrupt pending bit can be cleared only when the safe mode request is deasserted by the mc_rgm (see the mc_rgm chapte r for details on how to clear a safe mode request). if the system is already in safe mode, any ne w safe mode request by the mc_rgm also sets the interrupt pending bit i_safe. however, the safe mode interrupt pending bit is not set when the safe mode is entered by a software request (i.e. programming of register). 32.4.5.4 mode transition complete interrupt whenever the system fully completes a mode transition (i.e. the s_mtrans bit of register transits from ?1? to ?0?), the interrupt pending bit i_mtc of the me _is register is set, and an interrupt request is generated if the mask bit m_mtc of the me_im register is ?1?. the in terrupt bit i_mtc is not set when entering low-power modes halt0 and stop0 in order to avoid the same event requesting the immediate exit of these low-power modes. 32.4.6 peripheral clock gating during all device modes, each peri pheral can be associated with a particular clock gating policy determined by two groups of peri pheral configuration registers. the run peripheral configuration registers me_run_pc0?7 are chosen only during the software running modes drun, test, safe, and ru n0?3. all configurati ons are programmable by software according to the needs of the application. each configuration register contains a mode bit which determines whether or not a peripheral clock is to be gated. run configuratio n selection for each peripheral is done by the run_cfg bit field of the me_pctl0?143 registers. the low-power peripheral configur ation registers me_lp_ pc0?7 are chosen only during the low-power modes halt0 and stop0. all configurations are progr ammable by software according to the needs of the application. each configuration register contai ns a mode bit which determines whether or not a peripheral clock is to be gated. lo w-power configuration selection fo r each peripheral is done by the lp_cfg bit field of the me_pctl0?143 registers.
mode entry module (mc_me) freescale semiconductor 32-49 pxs20 microcontroller reference manual, rev. 1 any modifications to the me _run_pc0?7, me_lp_pc0?7, and me_pctl0?143 registers do not affect the clock gating beha vior until a new mode tran sition request is generated. whenever the processor enters a de bug session during any mode, the foll owing occurs for each peripheral: ? the clock is gated if the dbg_f bit of the associated me_pctl0?1 43 register is set. otherwise, the peripheral clock gating stat us depends on the run_cfg a nd lp_cfg bits. any further modifications of the me_run_pc0?7, me_lp_pc0?7, and me_pctl0?143 registers during a debug session will take affect immediately without requiring any new mode request. 32.4.7 application example figure 32-27 shows an example application flow for requesting a mode cha nge and then waiting until the mode transition has completed.
mode entry module (mc_me) 32-50 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 32-27. mc_me application example flow diagram start of mode change config for target mode okay? write me__mc , me_run_pc0?7 , me_lp_pc0?7 , and me_pctl0?143 registers n y write me_mctl with target mode and key write me_mctl with target mode and inverted key start timer s_mtrans cleared? y timer expired? n y n write me_mctl with current or safe mode and key write me_mctl with current or safe mode and inverted key stop timer mode change done
mode entry module (mc_me) freescale semiconductor 32-51 pxs20 microcontroller reference manual, rev. 1
mode entry module (mc_me) 32-52 freescale semiconductor pxs20 microcontroller reference manual, rev. 1
nexus crossbar slave port data trace module (nxss) [cut2/3 only] freescale semiconductor 33-1 pxs20 microcontroller reference manual, rev. 1 chapter 33 nexus crossbar slave port data trace module (nxss) [cut2/3 only] 33.1 introduction the nxss modules on cut2/3 of this device provide the data trace and watc hpoint messaging features defined in the class 3 i eee-isto 5001-2003 standard. the pxs20 cut2/3 provides two nxss modules: ? nxss_0 can be programmed to trace data accesses to the system sram0. ? nxss_1 can be programmed to trace data accesses to the system sram1. all output messages and register acc esses are compliant with the prot ocol defined in the ieee-isto 5001-2003 standard. note the auxiliary port and its signals, such as mcko, mseo [1:0], mdo[11:0] and others, are referenced. the devi ce npc module arbitr ates the access of the single auxiliary port. the functions of the nxss_0 and nxss_1 modules are described without the interaction of the npc, as if nexus has a dedicated auxiliary port, to simplify the description. 33.2 block diagram figure 33-1 shows a block diagram of the nxss. in nexus full port mode there are 12 mdos and in nexus reduced port mode there are 4 mdos.
nexus crossbar slave port data trace module (nxss) [cut2/3 only] 33-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 33-1. nxss block diagram 33.3 features features include the following: ? data trace via data write messaging (dwm) and data read messaging (drm ). this provides the capability for the development tool to trace re ads and/or writes to system sram0 and system sram1. ? watchpoint messaging via the auxiliary pins ? watchpoint trigger enable of data trace messaging (dtm) ? registers for data trace, watchpoin t generation, and watchpoint trigger ? all features controllable and configurable via the jtag port 33.4 external signal description 33.4.1 rules for output messages the nxss module observes the same ru les for output messages as the npc. 33.4.2 auxiliary port arbitration the nxss_0 and nxss_1 modules arbitr ate for the shared nexus port. th is arbitration is handled by the npc and is based on prioritized re quests from the nxss_0, nxss_1, and the other nexus clients sharing the port. breakpoint/ watchpoint control message queues npc control and i/o logic memory control general control and status registers arbitration data snoop mdo[11:0] mseo [0] mseo [1] mcko evto evti tdi tdo tms tclk trst ieee 1149.1 ahb bus (jtag) tap controller (jcomp)
nexus crossbar slave port data trace module (nxss) [cut2/3 only] freescale semiconductor 33-3 pxs20 microcontroller reference manual, rev. 1 33.5 nxss programmer model this section describes the programmer model. ne xus registers are accessed using the jtag port in compliance with ieee 1149.1. 33.5.1 development control registers (dc1 and dc2) the development control re gisters (dc1 and dc2) control the basic development features of the nxss_0 and nxss_1 modules. table 33-1. register s available in the nxss programmer model register 1 notes: 1 all registers have read/write access. nexus access opcode read address write address location development control 1 (dc1_ n ) 0x2 0x04 0x05 on page 33-3 development control 2 (dc2_ n ) 0x3 0x06 0x07 on page 33-3 watchpoint trigger (wt_ n ) 0xb 0x16 0x17 on page 33-5 data trace control (dtc_ n ) 0xd 0x1a 0x1b on page 33-5 data trace start address 1 (dtsa1_ n ) 0xe 0x1c 0x1d on page 33-7 data trace start address 2 (dtsa2_ n ) 0xf 0x1e 0x1f on page 33-7 data trace end address 1 (dtea1_ n ) 0x12 0x24 0x25 on page 33-7 data trace end address 2 (dtea2_ n ) 0x13 0x26 0x27 on page 33-7 breakpoint/watchpoint co ntrol register 1 (bwc1_ n ) 0x16 0x2c 0x2d on page 33-8 breakpoint/watchpoint co ntrol register 2 (bwc2_ n ) 0x17 0x2e 0x2f on page 33-9 breakpoint/watchpoint ad dress register 1 (bwa1_ n ) 0x1e 0x3c 0x3d on page 33-10 breakpoint/watchpoint ad dress register 2 (bwa2_ n ) 0x1f 0x3e 0x3f on page 33-10 access: r/w 0123456789101112131415 r opc 0 0 eoc 00 wen 00000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 00000000 0 0 eic tm w reset0000000000000000 figure 33-2. development control register 1 (dc1)
nexus crossbar slave port data trace module (nxss) [cut2/3 only] 33-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 table 33-2. dc1 field descriptions field description opc 1 notes: 1 the output port mode control bit (opc) is shown for clarity. this function is controlled globally by the npc port control register (pcr). output port mode control. 0 reduced port mode configuration 1 full port mode configuration eoc evto control. 00 evto upon occurrence of watchpoint (internal or external) 01 evto upon entry into system-level debug mode 1x reserved wen watchpoint trace enable. 0 watchpoint messaging disabled 1 watchpoint messaging enabled. eic evti control. 00 evti for synchronization (data trace) 01 reserved 10 evti disabled for this module 11 reserved tm trace mode. 000 no trace 1xx reserved x1x data trace enabled xx1 reserved access: r/w 0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728293031 r ewc 0000000000 00000000 0 0 0 0 0 0 w reset00000000000000000000000000000000 figure 33-3. development control register 2 (dc2) table 33-3. dc2 field description field description ewc 1 evto watchpoint configuration 00000000 = no watchpoints trigger evto 1xxxxxxx = reserved x1xxxxxx = reserved xx1xxxxx = reserved xxx1xxxx = reserved xxxx1xxx = internal watc hpoint #1 triggers evto xxxxx1xx = internal watchpoint #2 triggers evto xxxxxx1x = reserved xxxxxxx1 = reserved
nexus crossbar slave port data trace module (nxss) [cut2/3 only] freescale semiconductor 33-5 pxs20 microcontroller reference manual, rev. 1 33.5.2 watchpoint trigger register (wt) the watchpoint trigger register (wt) allows the watchpoints defined internally to the nxss_0 and nxss_1 modules to trigger actions. these watchpoints can control data trace enable and disable. the wt bits can be used to produce an address re lated window for triggering trace messages. note the wt bits only enable data trace if the tm bits within the development control register (dc) have not alre ady been set to enable data trace. 33.5.3 data trace control register (dtc) the data trace control register (dtc ) controls whether dtm messages are restricted to reads, writes or both for a user programmable address range. there are two data trace channels controlled by the dtc for the nxss_0 and nxss_1 modules. notes: 1 the eoc bits in dc1 must be programmed to trigger evto on watchpoint occurrence for the ewc bits to have any effect. access: r/w 0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728293031 r000000 dts dte 000000 00000000 0 0 0 0 0 0 w reset00000000000000000000000000000000 figure 33-4. watchpoint trigger register (wt) table 33-4. wt field descriptions field description dts data trace start control. 000 trigger disabled 001?100 reserved 101 use internal watchpoint #1 (bwa1 register) 110 use internal watchpoint #2 (bwa2 register) 111 reserved dte data trace end control 000 trigger disabled 001?100 reserved 101 use internal watchpoint #1 (bwa1 register) 110 use internal watchpoint #2 (bwa2 register) 111 reserved
nexus crossbar slave port data trace module (nxss) [cut2/3 only] 33-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 access: r/w 0123456789101112131415161718192021222324 25262728293031 r rwt 1 rwt 2 00000000 amid nsid 0000 rc 1 rc 2 0 0 0 0 0 0 w reset000000000000000000000000 0 0 000000 figure 33-5. data trace control register (dtc) table 33-5. dtc field descriptions bit description rwt1 read/write trace 1 00 no trace messages generated x1 enable data read trace 1x enable data write trace rwt2 read/write trace 2 00 no trace messages generated x1 enable data read trace 1x enable data write trace amid ahb master id select this field selects which crossbar master will have its accesses to the sram traced. only one master can have its accesses to the sram traced at a time. lock-step mode decoding 0000 core_0 / core_1 0001 reserved 0010 edma_0 / edma_1 0011 flexray 0100?1111 reserved decoupled parallel mode decoding 0000 core_0 0001 core_1 0010 edma_0 0011 flexray 0100 reserved 0101 reserved 0110 dma 1 0111 reserved 1000?1111 reserved
nexus crossbar slave port data trace module (nxss) [cut2/3 only] freescale semiconductor 33-7 pxs20 microcontroller reference manual, rev. 1 33.5.4 data trace start address re gisters 1 and 2 (dtsa1 and dtsa2) the data trace start address regist ers 1 and 2 (dtsa1 and dtsa2) defi ne the start addresses for each trace channel. 33.5.5 data trace end address regi sters 1 and 2 (d tea1 and dtea2) the data trace end address registers 1 and 2 (dtea1 and dtea2) define the end addresses for each trace channel. nsid nexus source id this field defines the nexus source id that w ill be used in the nexus trace messages. this should be set by tools to: lock-step mode decoding 0000?1001 reserved 1010 nxss_0 / nxss_1 1011?1111 reserved decoupled parallel mode decoding 0000-1001 reserved 1010 nxss_0 1011 nxss_1 1100?1111 reserved rc1 range control 1 0 condition trace on address within range (endpoints inclusive) 1 condition trace on address outside of range (endpoints exclusive) rc2 range control 2 0 condition trace on address within range (endpoints inclusive) 1 condition trace on address outside of range (endpoints exclusive) access: r/w 012345678910111213141516171819202122232425262728293031 r data trace start address w reset00000000000000000000000000000000 figure 33-6. data trace start address registers (dtsa1, dtsa2) access: r/w 012345678910111213141516171819202122232425262728293031 r data trace end address w reset00000000000000000000000000000000 figure 33-7. data trace start address registers (dtea1, dtea2) table 33-5. dtc field descriptions (continued) bit description
nexus crossbar slave port data trace module (nxss) [cut2/3 only] 33-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 table 33-6 illustrates the range that is selected for data trace for various cases of dtsa being less than, greater than, or equal to dtea. note dtsa must be less than or equal to dtea to guarantee correct data write/read traces. when the range cont rol bit is 0 (inter nal range), accesses to dtsa and dtea addresses are trac ed. when the range control bit is 1 (external range), accesses to dtsa and dtea are not traced. 33.5.6 breakpoint / watchpoint control register 1 (bwc1) the breakpoint / watchpoint control re gister 1 (bwc1) contro ls attributes for ge neration of nxss_0 and nxss_1 watchpoint number 1. table 33-6. data trace address range options programmed values range control bit value range selected dtsa ? dtea 0 dtsa ? ? dtea dtsa ? dtea 1 ? dtsa dtea ? dtsa > dtea ? invalid range, no trace access: r/w 0123456789101112131415 16 171819202122232425262728293031 r bwe 1 brw 1 bwr 1 bwt 1 w reset0000000000000000 0 000000000000000 figure 33-8. break / watchpoint control register 1 (bwc1) table 33-7. bwc1 field descriptions field description bwe1 breakpoint/watchpoint #1 enable 00 internal nexus watchpoint #1 disabled 01?10 reserved 11 internal nexus watchpoint #1 enabled brw1 breakpoint/watchpoint #1 read/write select 00 watchpoint #1 hit on read accesses 01 watchpoint #1 hit on write accesses 10 watchpoint #1 on read or write accesses 11 reserved
nexus crossbar slave port data trace module (nxss) [cut2/3 only] freescale semiconductor 33-9 pxs20 microcontroller reference manual, rev. 1 33.5.7 breakpoint / watchpoint control register 2 (bwc2) the breakpoint / watchpoint control re gister 2 (bwc2) contro ls attributes for ge neration of nxss_0 and nxss_1 watchpoint number 2. bwr1 breakpoint/watchpoin t #1 register compare 00 no register compare (same as bwc1[31:30] = 2?b00) 01 reserved 10 compare with bwa1 value 11 reserved bwt1 breakpoint/watchpoint #1 type 0 reserved 1 watchpoint #1 on data accesses access: r/w 0123456789101112131415 16 171819202122232425262728293031 r bwe 2 brw 2 bwr 2 bwt 2 w reset0000000000000000 0 000000000000000 figure 33-9. break / watchpoint control register 2 (bwc2) table 33-8. bwc2 field descriptions field description bwe2 breakpoint/watchpoint #2 enable 00 internal nexus watchpoint #2 disabled 01?10 reserved 11 internal nexus watchpoint #2 enabled brw2 breakpoint/watchpoint #2 read/write select 00 watchpoint #2 hit on read accesses 01 watchpoint #2 hit on write accesses 10 watchpoint #2 on read or write accesses 11 reserved bwr2 breakpoint/watchpoint #2 register compare 00 no register compare (same as bwc1[31:30] = 2?b00) 01 reserved 10 compare with bwa2 value 11 reserved bwt2 breakpoint/watchpoint #2 type 0 reserved 1 watchpoint #2 on data accesses table 33-7. bwc1 field descriptions (continued) field description
nexus crossbar slave port data trace module (nxss) [cut2/3 only] 33-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 33.5.8 breakpoint/watchpoint addr ess registers 1 and 2 (bwa1 and bwa2) the breakpoint/watchpoint address registers are compared with bus addresses to generate internal watchpoints. 33.5.9 unimplemented registers unimplemented registers are those with client select and index value comb inations other than those listed in table 33-1 . for unimplemented registers, the nxss_0 a nd nxss_1 modules drives tdo to zero during the ?shift-dr? state. it also transmits an er ror message with the i nvalid access opcode encoding. 33.6 functional description 33.6.1 tcodes su pported by nxss_0 and nxss_1 the nxss_0 and nxss_1 pins allow for flexible tr ansfer operations via publ ic messages. a tcode defines the transfer format, the numbe r and/or size of the packets to be transferred, and the purpose of each packet. the ieee-isto 5001-2003 de fines a set of public messages. the nxss _0 and nxss_1 modules support the public tcodes as shown in table 33-9 . access: r/w 012345678910111213141516171819202122232425262728293031 r breakpoint / watchpoint address w reset00000000000000000000000000000000 figure 33-10. breakpoint / watchpoint address registers (bwa1, bwa2) table 33-9. public tcodes supported message name packet size bits packet name packet type packet description min. max. data trace - date write message 6 6 tcode fixed tcode number = 5 4 4 src fixed source processor identifier (multiple nexus configuration) 3 3 dsz fixed data size (refer to table 33-11 ) 1 32 u-addr variable unique portion of the data write value 1 64 data variable data write value data trace - data read message 6 6 tcode fixed tcode number = 6 4 4 src fixed source processor identifier (multiple nexus configuration) 3 3 dsz fixed data size (refer to table 33-11 ) 1 32 u-addr variable unique portion of the data read value 1 64 data variable data read value
nexus crossbar slave port data trace module (nxss) [cut2/3 only] freescale semiconductor 33-11 pxs20 microcontroller reference manual, rev. 1 error message 6 6 tcode fixed tcode number = 8 4 4 src fixed source processor identifier (multiple nexus configuration) 5 5 ecode fixed error code (refer to table 33-10 ) data trace - data write message w/ sync 6 6 tcode fixed tcode number = 13 (0xd) 4 4 src fixed source processor identifier (multiple nexus configuration) 3 3 dsz fixed data size (refer to table 33-11 ) 1 32 f-addr variable full access address (leading zero (0) truncated) 1 64 data variable data write value data trace - data read message w/ sync 6 6 tcode fixed tcode number = 14 (0xe) 4 4 src fixed source processor identifier (multiple nexus configuration) 3 3 dsz fixed data size (refer to table 33-11 ) 1 32 f-addr variable full access address (leading zero (0) truncated) 1 64 data variable data read valued watchpoint message 6 6 tcode fixed tcode number = 15 (0xf) 4 4 src fixed source processor identifier (multiple nexus configuration) 4 4 wphit fixed number indicating watchpoint sources table 33-10. error code (ecode) encoding (tcode = 8) error code (ecode) description 00000 reserved 00001 reserved 00010 data trace overrun 00011 reserved 00100 reserved 00101 invalid access opcode (nexus register unimplemented) 00110 watchpoint overrun 00111 reserved 01000 data trace and watchpoint overrun 01001?11111 reserved table 33-9. public tcodes supported (continued) message name packet size bits packet name packet type packet description min. max.
nexus crossbar slave port data trace module (nxss) [cut2/3 only] 33-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 33.6.2 data trace this section deals with the data trace mechan ism supported by the nxss_0 and nxss_1 modules. data trace is implemented via data write mess aging (dwm) and data read messaging (drm). 33.6.3 data trace messaging (dtm) nxss_0 and nxss_1 data trace mess aging is accomplished by snoopi ng the nxss_0 and nxss_1 data bus, and storing the information for qualifying acce sses (based on enabled features and matching ahb master id and target addr esses). the nxss module traces all data access that meet the selected range and attributes. 33.6.4 dtm message formats the nxss module supports five types of dtm messa ges ? data write, data read, data write synchronization, data read synchronization, and error messages. 33.6.4.1 data write and data read messages the data write and data read messag es contain the data write/read valu e and the address of the write/read access, relative to the pr evious data trace message. data write message and data read message information is messaged out in the following format: figure 33-11. data write/read message format 33.6.4.2 dtm overflow error messages an error message occurs when a ne w message cannot be queued due to the message queue being full. the fifo discards incoming messages until it has comple tely emptied the queue. after it is emptied, an error table 33-11. data trace size (dsz) encodings (tcode = 5, 6, 13, 14) dtm size encoding transfer size 000 byte 001 halfword (two bytes) 010 word (four bytes) 011 doubleword (eight bytes) 100?111 reserved data msb lsb 2 3 4 u-addr dsz src 5 4 bits 1 tcode (000101 or 000110) 3 bits 1?32 bits 1?64 bits 6 bits max length = 109 bits; min length = 15 bits
nexus crossbar slave port data trace module (nxss) [cut2/3 only] freescale semiconductor 33-13 pxs20 microcontroller reference manual, rev. 1 message is queued. the error encodi ng indicates which type s of messages attempted to be queued while the fifo was being emptied. if only a data trace message attempts to enter the queue while it is being em ptied, the error message incorporates the data trace only error encoding (00010). if a watchpoint also attemp ts to be queued while the fifo is being emptied, then the error message incorporates error encoding (01000). error information is messaged out in the following format: figure 33-12. error message format 33.6.4.3 data trace synchronization messages a data trace write/read w/ sync. message is messaged via the auxiliar y port (provided data trace is enabled) for the following conditions (refer to table 33-12 ): ? initial data trace message upon ex it from system reset or whenev er data trace is enabled is a synchronization message. ? upon returning from debug mode, the first data trace message is a s ynchronization message. ? after occurrence of queue ove rrun (can be caused by any trace message), the first data trace message is a sync hronization message. ? after the periodic data trace counter has expired indicating 255 without-sync data trace messages have occurred since the last with-sync message occurred. ? upon assertion of the event in (evti ) pin, the first data trace message is a synchronization message if the eic bits of the dc register have enabled this feature. ? upon data trace write/read after the previous dtm message was lost due to an attempted access to a secure memory location. ? upon data trace write/read after th e previous dtm message was lost due to a collision entering the fifo between the dtm message and any of the fo llowing: error message, or watchpoint message. data trace synchronization messages provide the full address (without leading zeros) and ensure that development tools fully synchronize with data tr ace regularly. synchroniza tion messages provide a reference address for subsequent dtms, in which onl y the unique portion of the data trace address is transmitted. the format for data trace writ e/read w/ sync. messa ges is as follows: ecode (00010 / 01000) msb lsb 1 2 src tcode (001000) 3 6 bits 4 bits 5 bits fixed length = 15 bits
nexus crossbar slave port data trace module (nxss) [cut2/3 only] 33-14 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 33-13. data write/read w/ sync message format exception conditions that re sult in data trace synchr onization are summarized in table 33-12 . 33.6.5 dtm operation 33.6.5.1 enabling data trace messaging data trace messaging can be enabled in one of two ways. ? setting the dc1[tm] field to enable data trace table 33-12. data trace exception summary exception condition exception handling system reset negation at the negation of jtag reset (jcomp), queue pointers, counters, state machines, and registers within the nxss _0 and nxss_1 module are reset. if data trace is enabled, the first data trac e message is a data write/read w/ sync. message. data trace enabled the first data trace message (after data trace has been enabled) is a synchronization message. exit from debug upon exit from debug mode the ne xt data trace message is converted to a data write/read w/ sync. message. queue overrun an error message occurs when a new message cannot be queued due to the message queue being full. the fifo disca rds messages until it has completely emptied the queue. after it is emptied, an error message is queued. the error encoding indicates the types of messages that attempted to be queued while the fifo was being emptied. the next dtm message in the queue is a data write/read w/ sync. message. periodic data trace synchronization a forced synchronization occurs periodically after 255 data trace messages have been queued. a data write/re ad w/ sync. message is queued. the periodic data trace message counter then resets. event in if the nexus module is enabled, an evti assertion initiates a data trace write/read w/ sync. message upon the ne xt data write/read (if data trace is enabled and the eic bits of the dc register have enabled this feature). attempted access to secure memory any attempted read or write to secure memory locations temporarily disable data trace & cause the corresponding dtm to be lost. a subsequent read/write queues a data trace read/write with sync. message. collision priority all messages have the following priority: error ? wpm ? dtm. a dtm message which attempts to enter the queue at the same time as an error message, or watchpoint message is lo st. a subsequent read/write queues a data trace read/write with sync. message. data msb lsb 2 3 4 f-addr dsz src 5 4 bits 1 tcode (001101 or 001110) 3 bits 1?32 bits 1?64 bits 6 bits max length = 109 bits; min length = 15 bits
nexus crossbar slave port data trace module (nxss) [cut2/3 only] freescale semiconductor 33-15 pxs20 microcontroller reference manual, rev. 1 ? using the wt[dts] field to enab le data trace on watchpoint hits 33.6.5.2 dtm queueing nxss_0 and nxss_1 implement a progr ammable depth queue for queuing all messages. messages that enter the queue are transmitted via the auxiliary pins in the order in which they are queued. note if multiple trace messages must be que ued at the same time, watchpoint messages have the highest priority (wpm ? dtm). 33.6.5.3 relative addressing the relative address feature is co mpliant with ieee-isto nexus 5001-2003 and is designed to reduce the number of bits transmitted for a ddresses of data trace messages. 33.6.5.4 data trace windowing data write/read messages are enabled via the rwt1(2) field in the data trace control register (dtc) for each dtm channel. data trace windowing is achieve d via the address range defined by the dtea and dtsa registers and by the rc1(2) field in the dtc. all read/write accesses by the selected ahb master id (see dtc register for more detail s) that fall inside or outside these address ra nges, as programmed, are candidates to be traced. 33.7 watchpoint support the nxss_0 and nxss_1 module provides watchpoint me ssaging via the auxiliary pins, as defined by ieee-isto 5001-2003. watchpoint messages can be ge nerated using the nxss_0 and nxss _1 defined internal watchpoints. 33.7.1 watchpoint messaging enabling watchpoint messaging is accomplished by setting the watchpoint messaging enable bit, dc1[wen]. using the bwc1 and bwc2 registers, tw o independently controll ed internal watchpoints can be initialized. when the selected ahb master id address matches on bwa1 or bwa2, a watchpoint message is transmitted. the nexus module provides watchpoi nt messaging using the tcode. when either of the two possible watchpoint sources asserts, a message is sent to the queue to be messaged out. this message indicates the watchpoint number.
nexus crossbar slave port data trace module (nxss) [cut2/3 only] 33-16 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 33-14. watchpoint message format 33.7.2 watchpoint error message an error message occurs when a ne w message cannot be queued due to the message queue being full. the fifo discards messages until it has completely emptied the queue. after it is emptied, an error message is queued. the error encoding indicates wh ich types of messages attempted to be queued while the fifo was being emptied. if only a watchpoint message attempts to enter the queue while it is being emptied, th e error message incorporates the watchpoint only error encoding (00110). if a da ta trace message also attempts to enter the queue while it is being emptied, the error message incorporates error encoding (01000). error information is messaged out in the following format (refer to figure 33-15 ). figure 33-15. error message format table 33-13. watchpoint source desc ription (wphit field descriptor) watchpoint source (4 bits) watchpoint description xxx1 reserved xx1x reserved x1xx internal watchpoint #1 (bwa1 match) 1xxx internal watchpoint #2 (bwa2 match) wphit (xxxx) msb lsb 1 2 src tcode (001111) 3 6 bits 4 bits 4 bits fixed length = 14 bits ecode (00110 / 01000) msb lsb 1 2 src tcode (001000) 3 6 bits 4 bits 5 bits fixed length = 15 bits
nexus port controller (npc) freescale semiconductor 34-1 pxs20 microcontroller reference manual, rev. 1 chapter 34 nexus port controller (npc) 34.1 information specific to this device this section presents device-specifi c parameterization, customization, and feature availability information not specifically referenced in the remainder of this chapter. 34.1.1 parameter values the parameter values for th is device are shown in table 34-1 . 34.1.2 unavailable features mcko clock gating is not supported on cut1 of this device. (it is supported on cut2/3.) this device does not support an mcko division factor of 3. theref ore, the setting pcr[mcko_div] = 2 (see table 34-6 ) is not availabl e on this device. nexus ddr mode works only for mcko division f actors of 2, 4, and 8. therefore, the setting pcr[mcko_div] = 0 (see table 34-6 ) will not support nexus ddr mode on this device. 34.2 introduction figure 34-1 is a block diagram of the nexus port controller (npc) block. table 34-1. device parameter values parameter value number of mdo pins available in reduced-port mode 4 number of mdo pins available in full-port mode 12 part identification number 0x2a2 manufacturer identity code (mic) 0x00e design center code (dc) 0x2b
nexus port controller (npc) 34-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 34-1. nexus port controller block diagram 34.2.1 overview on a system-on-a-chip devi ce, there are often multiple blocks that require development support. each of these blocks implements a development interfa ce based on the ieee-isto 5001-2003 standard. the blocks share input and output ports that interface with the development tool. the npc controls the usage of the input and output port in a manne r that allows all the individual deve lopment interface blocks to share the port, and appear to the devel opment tool to be a single block. 34.2.2 features the npc block performs the following functions: ? controls arbitration for ownership of the nexus auxiliary output port ? nexus device identification register and messaging ? generates mcko enable and fr equency division control signals ? controls sharing of evto ? generates an mcko clock gating control signal to enable gating of mcko when the auxiliary output port is idle ? control of the device-wide debug mode ? generates asynchronous reset signal for nexus bloc ks based on jcomp input, censorship status, and power-on reset status ? system clock locked status indicati on via mdo[0] following power-on reset ? provides nexus support for censorship mode port arbiter message transmitter mdo/mseo generation jtag tdi tdo tck tms debug mode control register tdo generation reset control jcomp evto control control interface pstat mdo mux mdo mseo_b miscellaneous logic
nexus port controller (npc) freescale semiconductor 34-3 pxs20 microcontroller reference manual, rev. 1 ?rdy pin support to increase the tran sfer rate of the ieee 1149.1 port for large data read requests (supported on cut2/3 only) 34.2.3 modes of operation the npc block uses the jcomp input, the censorship status , and an inte rnal power-on rese t indication as its primary reset signals. u pon exit of reset, the mode of operation is determined by the port configuration register (pcr) settings. 34.2.3.1 reset the npc block is asynchronously placed in reset when either power-on reset is asserted, jcomp is not set for nexus access, the device enters censored mode , or the tap controller state machine is in the test-logic-reset state. holding tms high for 5 consecutive rising edges of tck guarantees entry into the test-logic-reset state regardless of the current ta p controller state. following negation of power-on reset, the npc remains in reset until the system cl ock achieves lock. the np c is unaffected by other sources of reset. while in rese t, the following actions occur: ? the tap controller is forced into the test-logic-reset state ? the auxiliary output port pins are negated ? the tdi, tms, and tck tap inputs are ignored (when in power-on reset, censored mode or jcomp not set for npc operation only) ? registers default back to their reset values 34.2.3.2 disabled-port mode in disabled-port mode, auxiliary output pin port enable signals are negated, thereby disabling message transmission. any debug feat ure that generates messages can not be used. the primary features available are class 1 features and read/write ac cess to the registers. class 1 featur es include the ability to trigger a breakpoint event indication through evto . 34.2.3.3 full-port mode full-port mode (fpm) is entered by asserting the mcko_en and fpm bits in the pcr. all trace features are enabled or can be enabled by wr iting the configuration registers via the tap. the number of mdo pins available is device-specific. 34.2.3.4 reduced-port mode reduced-port mode (rpm) is entered by asserting th e mcko_en bit and deasserting the fpm bit in the pcr. all trace features are enabled or can be enabled by writing the c onfiguration registers via the tap. the number of mdo pins available is device-specific. 34.2.3.5 censored mode when the device is in censored mode, reading the cont ents of internal flash externally is not allowed. to prevent nexus modules from violating censorship, the npc is held in reset when in censored mode,
nexus port controller (npc) 34-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 asynchronously holding all other nexus modules in rese t as well. this prevents nexus read/write to memory mapped resources and the tr ansmission of nexus trace messages. 34.2.3.6 nexus double data rate mode nexus double data rate (ddr) mode is enabled by a sserting the ddr_en bit in the pcr. in double data rate mode, message data is updated as fo llows, effectively doubl ing message throughput: ? for cut1: on each edge (bot h rising and falling) of mcko ? for cut2/3: between the edges ( both rising and falling) of mcko 34.3 external signal description 34.3.1 overview the npc pin interface provides for the transmission of messages from nexus blocks to the external development tools and for access to nexus client registers. the npc pin de finition is outlined in table 34-2 . 34.3.2 detailed signal descriptions this section describes each of the signals listed in table 34-2 in more detail. the jtag test clock (tck) input from the pin is not a direct input to the npc. the npc requires two separate input clocks for tck clocked logic, one for posedge (risi ng edge tck) logic and one for negedg e (falling edge tck) logic. both clocks are derived from the pin tck, and generated external to the npc. table 34-2. npc signal properties name port function reset state pull 1 notes: 1 the pull is not implemented in this block. pull up/pulldown devices are implemented in the pads. evto auxiliary event out pin 0b1 ? jcomp jtag jtag compliancy and tap sharing control ? down mdo auxiliary message data out pins 0 2 2 following a power-on reset, mdo[0] remains asserted until power-on reset is exited and the system clock achieves lock. ? mseo auxiliary message start/end out pins 0b11 ? tck 3 3 tck frequency must be lower than system clock frequency during low power and normal operation modes for communication jtag test clock input ? down tdi jtag test data input ? up tdo jtag test data output high z 4 4 tdo output buffer enable is negated when the npc is not in the shift-ir or shift-dr states. a weak pull may be implemented on tdo at the soc level. ? tms jtag test mode select input ? up rdy jtag data ready for transfer to/from nrrs ? ?
nexus port controller (npc) freescale semiconductor 34-5 pxs20 microcontroller reference manual, rev. 1 34.3.2.1 evto - event out event out (evto ) is an output pin that is asserted upon breakpoint occurrence to provide breakpoint status indication. the evto output of the npc is ge nerated based on the values of the individual evto signals from all nexus blocks that implement the signal. 34.3.2.2 jcomp - jtag compliancy the jcomp signal provides th e ability to share the tap. the npc ta p controller is en abled when jcomp is set to the npc enable encoding, otherwis e the npc tap controller remains in reset. 34.3.2.3 mdo - me ssage data out message data out (mdo) are output pins used for uploading otm, btm, dtm, and other messages to the development tool. the development tool should sa mple mdo on the rising e dge of mcko. the width of the mdo bus used is determ ined by reset configuration. 34.3.2.4 mseo_b - mess age start/end out message start/end out (mseo ) is an output pin that indicates when a message on the mdo pins has started, when a variable length packet has ended, or when the message has e nded. the development tool should sample mseo on the rising edge of mcko. 34.3.2.5 tck - test clock input test clock input (tck) pin is used to synchronize the test logic and control register access through the jtag port. the jtag clock (tck) typically operates at a freque ncy well below the system clock frequency, as specified in the electrical data sheets. in some ca ses, however, such as low power mode (if the device supports low power modes), the syst em clock frequency may be lowe red significantly from the normal operating range. if the system clock frequency is reduced below the fre quency of tck it will no longer be possible to communicate with the nexus port controller port conf iguration register (npc_pcr). therefore, if the tool needs to update the np c_pcr low power debug enable (npc[pcr[lp_dbg]) or low power synchronization bits (npc[pcr[lp1_syn] and npc[pcr[ lp2_syn]), the clock frequency must be lowered. ensure that the frequency of tck does not exceed the system clock frequency during normal operation and during low power operation. note tck clock frequency needs to be sm aller than sysclk/2 for correct operation of npc/nexus/nxss subsystem 34.3.2.6 tdi - test data input test data input (tdi) pin receives se rial test instruction and data. td i is sampled on the rising edge of tck.
nexus port controller (npc) 34-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 34.3.2.7 tdo - nexus test data output test data output (tdo) pin transmit s serial output for instructions an d data. tdo is three-stateable and is actively driven in the shift-ir and shift-dr c ontroller states. tdo is updated on the falling edge of tck and sampled by the development tool on the rising edge of tck. 34.3.2.8 tms - test mode select test mode select input (tms) pin is used to sequence the ieee 1149.1-2001 tap controller state machine. tms is sampled on the rising edge of tck. 34.3.2.9 rdy ? data ready for transfer (on cut2/3 only) the rdy pin, supported on cut2/3 only, exis ts to increase the transfer rate of the ieee 1149.1 port. it is used to signal when data are ready to be transferred to and from nrrs. this may elim inate the need to poll nrrs for status information for synchronization purpos es. this capability become s especially important when performing read/write access transfers to different speed target memories. the rdy pin asserts (asynchronous ly) a logic low whenever the read/w rite access transfer has completed without error and then deasserts when the ieee 1149.1 state machine has reached the capture_dr state. the rdy pin is controlled by the test_ctrl register in the jtagc module (see section 29.3.1.4, test_ctrl register (cut2/3 only) ). 34.4 register definition this section provides a detailed description of the npc registers accessible to the end user. individual bit-level descriptions and reset st ates of the registers are included. table 34-3 shows the npc registers by index values. the registers are not memory-mapped and can only be accessed via the tap. the npc block does not implemen t the client select control register because the value does not matter when accessing the registers. note that the bypass and instruction registers have no index values. these registers are not accessed in the sa me manner as nexus client registers. refer to the individual register descri ptions for more detail. 34.4.1 register descriptions this section consists of npc register descriptions. table 34-3. npc registers index register 0 device id register (did) 127 port configuration register (pcr)
nexus port controller (npc) freescale semiconductor 34-7 pxs20 microcontroller reference manual, rev. 1 34.4.1.1 bypass register the bypass register is a single-bit shif t register path selected for serial data transfer be tween tdi and tdo when the bypass instruction or any unimplemented instructions are active. after entry into the capture-dr state, the single-bit shift register is set to a logic 0. theref ore, the first bit shifted out after selecting the bypass regist er is always a logic 0. 34.4.1.2 instruction register the npc block uses a 4-bit inst ruction register as shown in table 34-2 . the instruction register is accessed via the select_ir_scan path of the tap controller stat e machine, and allows instructions to be loaded into the block to enable the npc for register acces s (nexus_enable) or select the bypass register as the shift path from tdi to tdo (byp ass or unimplemented instructions). instructions are shifted in through tdi while the tap c ontroller is in the shift-ir state, and latched on the falling edge of tck in the update -ir state. the latched instruction value can only be changed in the update-ir and test-logic-reset tap controller states. synchronous entr y into the test-logic-reset state results in synchronous loading of the bypass instru ction. asynchronous entry in to the test-logic-reset state results in asynchronous loadin g of the bypass instruction. during the capture-ir tap controller state, the instruction register is loaded with the va lue of the previously executed instruction, making this value the register?s read value when the tap c ontroller is sequenced in to the shift-ir state. figure 34-2. 4-bit instruction register 34.4.1.3 nexus device id register (did) the device identification register, shown in figure 34-3 , allows the part revisi on number, design center, part identification number, and manufacturer identity code of the part to be determined through the auxiliary output port. figure 34-3. nexus device id register 0 1 2 3 r previous instruction opcode w instruction opcode reset: bypass instruction opcode (0xf) register index: 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r part revision number design center part identification number w reset: prn dc pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r part identification number manufacturer identity code 1 w reset: pin (cont?d.) 0 0 0 0 0 0 0 1 1 1 0 1 = reserved
nexus port controller (npc) 34-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 34.4.1.4 port configuration register (pcr) figure 34-4. port configuration register (pcr) the pcr, shown in figure 34-4 , is used to select the npc mode of operation, enable mcko and select the mcko frequency, and enable or disable mcko gating. this register should be c onfigured as soon as the npc is enabled. the pcr register may be re written by the debug tool s ubsequent to the enabling of the npc for low power debug support. in this case, the de bug tool may set and clear the lp _dbg and lpn_syn bits, but must preserve the original state of th e remaining bits in the register. note the mode or clock division must not be modified after mcko has been enabled. changing the mode or clock division while mcko is enabled can produce unpredictable results. table 34-4. did field descriptions bit name description 31:28 prn part revision number these bits contain the revision number of the part 27:22 dc design center these bits indicate the device design center 21:12 pin part identification number these bits contain the part number of the device 11:1 mic manufacturer identity code these bits contain the reduced joint electron device engineering council (jedec) id for freescale semiconductor, 0xe. 0 bit [0] idcode register id bit [0] identifies this register as the device i dentification register and not the bypass register register index: 127 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r fpm mck o_gt mck o_en mcko_div evt_ en ddr_ en 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r lp_d bg 0 0 0 0 0 lp2_ syn lp1_ syn 0 0 0 0 0 0 0 psta t_en w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = reserved
nexus port controller (npc) freescale semiconductor 34-9 pxs20 microcontroller reference manual, rev. 1 table 34-5. pcr field descriptions name description fpm full port mode the value of the fpm bit determi nes if the auxiliary output port uses the full mdo port or a reduced mdo port to transmit messages. 1 = all mdo pins are used to transmit messages 0 = a subset of mdo pins are used to transmit messages mcko_gt mcko clock gating control this bit is used to enable or disable mcko clo ck gating. if clock gating is enabled, the mcko clock is gated when the npc is in enabled mode bu t not actively transmitting messages on the auxiliary output port. when clock gating is disabled , mcko is allowed to run even if no auxiliary output port messages are being transmitted. 1 = mcko gating is enabled 0 = mcko gating is disabled mcko_en mcko enable this bit enables the mcko clock to run. when enabled, the frequency of mcko is determined by the mcko_div field. 1 = mcko clock is enabled 0 = mcko clock is driven to zero mcko_div mcko division factor the value of this signal determines the frequ ency of mcko relative to the system clock frequency when mcko_en is asserted. table 34-6 shows the meaning of mcko_div values. in this table, sys_clk represents the system clock frequency. evt_en evto /evti enable this bit enables the evto /evti port functions. 1 = evto /evti port enabled 0 = evto /evti port disabled ddr_en double data rate mode enable this bit enables nexus double data rate (ddr) mode. in ddr mode, message data is updated on both rising and falling edges of mcko, effectively doubling message throughput. 1 = ddr mode enabled 0 = ddr mode disabled lp_dbg_en low power debug enable this bit enables debug functionality on exit from low power modes on supported devices. 1 = low power debug enabled 0 = low power debug disabled lpn_syn low power mode n synchronization these bits are used to synchronize the entry into low power modes between the device and debug tool. supported devices set these bits before a pending entry into low power mode. after reading the bit as set, the debug tool then clears the bit to acknowledge to the device that it may enter the low power mode. 1 = low power mode entry pending 0 = low power mode entry acknowledged pstat_en processor status mode enable 1 this bit enables processor status (pstat) mode. in pstat mode, all auxiliary output port mdo pins are used to transmit processor status information, and nexus messaging is unavailable. 1 = pstat mode enabled 0 = pstat mode disabled
nexus port controller (npc) 34-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 34.5 functional description 34.5.1 npc reset configuration the npc is placed in disabled mode upon exit of rese t. if message transmission via the auxiliary port is desired, a write to the pcr is then required to enable the npc and select the mode of operation. asserting mcko_en places the npc in enable d mode and enables mcko. the fre quency of mcko is selected by writing the mcko_div field. asserti ng or negating the fpm bit selects full-port or reduced-port mode, respectively. table 34-7 describes the npc rese t configuration options. 34.5.2 auxiliary output port the auxiliary output port is shared by each of the nexus modules on the devi ce. the npc communicates with each of the nexus modules and arbitrates for access to the port. notes: 1 pstat mode is intended for factory processor debug only. the pstat_en bit should be written to disable pstat mode if nexus messaging is desired. no nexus messages are transmitted under any circumstances when pstat mode is enabled. table 34-6. mcko_div values mcko_div[2:0] mcko frequency 0 sys_clk 1 notes: 1 the sys_clk setting for mcko freque ncy should only be used if this setting does not violate the maximum operating frequency of the auxiliary port pins. 1 sys_clk/2 2 sys_clk/3 3 sys_clk/4 4 reserved 5 reserved 6 reserved 7 sys_clk/8 table 34-7. npc reset configuration options jcomp equal to npc_jcomp_plug? mcko_en bit of the port configuration register fpm bit of the port configuration register configuration no x x reset yes 0 x disabled yes 1 1 full-port mode yes 1 0 reduced-port mode
nexus port controller (npc) freescale semiconductor 34-11 pxs20 microcontroller reference manual, rev. 1 34.5.2.1 output message protocol the protocol for transmitting me ssages via the auxiliary port is accomplished with the mseo functions. the mseo pins are used to signal the end of variable-l ength packets and the end of messages. they are not required to indicate the end of fixed-length packets. mdo and mseo are sampled on the rising edge of mcko. figure 34-5 illustrates the state diagram for mseo transfers. all transitions not included in the figure are reserved, and must not be used. figure 34-5. mseo transfers ( for 2-bit mseo ) 34.5.2.2 output messages in addition to sending out messages ge nerated in other nexus blocks, th e npc can also output the device id message contained in th e device id register and the port repl acement output messag e on the mdo pins. the device id message can also be sent out serially through tdo. idle start message normal transfer end packet end message mseo = 11 m s e o = 0 1 m s eo = 0 0 mseo = 00 mseo = 00 mseo = 00 mseo = 00 mseo = 11 m s eo = 1 1 mseo = 01 mseo = 01 mseo = 11 m s e o = 1 1 mseo = 01 mseo = 01 mseo = 10 m se o = 1 0
nexus port controller (npc) 34-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 table 34-8 describes the device id and port replacement output messages th at the npc can transmit on the auxiliary port. the tcode is the first packet transmitted. figure 34-6 shows the various message format s that the pin interface formatte r has to encounter. note that for variable-length fields, the transmitted size of th e field is determined from the range of the least significant bit to the most significant non-zero-valued bit (i.e. most significant zero-valued bits are not transmitted). the double edges in figure 34-6 indicate the starts and ends of me ssages. fields without shaded areas between them are grouped into super-fields and can be transmitted together without end-of-packet indications between them. 34.5.2.3 rules of message ? a variable-sized field with in a message must end on a port boundary. (p ort boundaries depend on the number of mdo pins active with the current reset configuration.) ? a variable-sized field may start within a por t boundary only when follow ing a fixed-length field. ? super-fields must end on a port boundary. ? when a variable-length field is sized such that it does not end on a port boundary, it is necessary to extend and zero fill the remain ing bits after the highest order bit so that it can end on a port boundary. ? multiple fixed-length p ackets may start and/or end on a single clock. ? when any packet follows a variable-lengt h packet, it must start on a port boundary. ? the field containing the tcode number is always transferred out first, followed by subsequent fields of information. ? within a field, the lowe st significant bits are shifted out first. figure 34-7 shows the transmission sequence of a message that is made up of a tcode followed by two fields. table 34-8. npc output messages message name min. packet size (bits) max packet size (bits) packet type packet name packet description device id message 6 6 fixed tcode value = 1 32 32 fixed id did register contents message tcode field #1 field #2 field #3 field #4 field #5 min. size 1 (bits) max size 2 (bits) device id message 1 fixed = 32 na na na na 38 38 notes: 1. minimum information size. the actual number of bits transmitted depends on the number of mdo pins 2. maximum information size. the actual number of bits transmitted depends on the number of mdo pins figure 34-6. message field sizes
nexus port controller (npc) freescale semiconductor 34-13 pxs20 microcontroller reference manual, rev. 1 figure 34-7. transmission sequence of messages 34.5.3 ieee 1149.1-2001 (jtag) tap the npc block uses the ieee 1149.1-2001 tap for accessi ng registers. each of the individual nexus blocks on the device implements a tap controller for accessing its regi sters as well. tap signals include tck, tdi, tms, and tdo. there may also be othe r blocks on the mcu that use the tap and implement a tap controller. the value of the jcomp input c ontrols ownership of the port between nexus and non-nexus blocks sharing the tap. refer to the ieee 1149.1-2001 specification for further de tail on electrical and pi n protocol compliance requirements. the npc implements a nexus controller state machine that transitions based on the state of the ieee 1149.1-2001 state machine shown in figure 34-9 . the nexus controller stat e machine is defined by the ieee-isto 5001-2003 standard. it is shown in figure 34-10 . the instructions implemented by the npc tap controller are listed in table 34-9 . the value of the nexus-enable instruction is 0b0000. each unimple mented instruction acts like the bypass instruction. the size of the npc in struction register is 4-bits. data is shifted between tdi and tdo starting with the least signi ficant bit as illustrated in figure 34-8 . this applies for the instruction register and all nexus tool-mapped registers. figure 34-8. shifting data into register table 34-9. implemented instructions instruction name private/p ublic opcode description nexus-enable public 0x0 activate nexus c ontroller state machine to read and write npc registers. bypass private 0xf npc bypass instructi on. also the va lue loaded into the npc ir upon exit of reset. tcode (6 bits) field #1 field #2 12 3 msb lsb msb lsb msb lsb selected register msb lsb tdi tdo
nexus port controller (npc) 34-14 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 34.5.3.1 enabling the npc tap controller assertion of the power-on re set signal, entry into censo red mode, or setting jcom p to a value other than the npc enable encoding resets the npc tap controll er. when not in power-on reset or censored mode, the npc tap controller is enabled by driving jc omp with the npc enable value and exiting the test-logic-reset state. loading the nexus-enable instruction then grants access to nexus debug.
nexus port controller (npc) freescale semiconductor 34-15 pxs20 microcontroller reference manual, rev. 1 figure 34-9. ieee 1149.1-2001 tap controller state machine test logic reset run-test/idle select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pau s e - i r exit2-dr exit2-ir update-dr update-ir 1 0 1 1 1 00 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 note: the value shown adjacent to each state transiti on in this figure represents the value of tms at the time of a rising edge of tck.
nexus port controller (npc) 34-16 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 34.5.3.2 retrieving device idcode the nexus tap controller does not implement th e idcode instruction. however, the device identification message can be output by the npc through the auxiliary out put port or shifted out serially by accessing the nexus device id register through the tap. transmission of the device identification message on the auxiliary output port mdo pins occurs immediately after a write to the pcr, if the npc is enabled. transmission of the devi ce identification message serially via tdo is achiev ed by performing a read of the register contents as described in section 34.5.3.4, selecting a nexus client register . 34.5.3.3 loading nexus-enable instruction access to the npc registers is enabled when the tap c ontroller instruction register is loaded with the nexus-enable instruction. this inst ruction is shifted in via the s elect-ir-scan path and loaded in the update-ir state. at this point, the nexus controller state machine, shown in figure 34-10 , transitions to the reg_select state. the nexus controller has three states: idle, regi ster select, and data access. table 34-10 illustrates the ieee 1149.1 sequence to load the nexus-enable instruction. figure 34-10. nexus controller state machine table 34-10. loading n exus-enable instruction clock tms ieee 1149.1 state nexus state description 0 0 run-test/idle idle ieee 1149.1-2001 tap controller in idle state 1 1 select-dr-scan idle transitional state 2 1 select-ir-scan idle transitional state 3 0 capture-ir idle internal shifter loaded with current instruction 4 0 shift-ir idle tdo becomes active, and the ieee 1149.1-2001 shifter is ready. shift in all but the last bit of the nexus_enable instruction. 3 tcks 12 1 exit1-ir idle last bit of instruction shifted in 13 1 update-ir idle nexus-enable loaded into instruction register 14 0 run-test/idle reg_select ready to be read/write nexus registers idle reg_select data_access nexus-enable=0 nexus-enable=1 test-logic-reset=1 update-dr=1 update-dr=1 nexus-enable=1 && update-ir=1
nexus port controller (npc) freescale semiconductor 34-17 pxs20 microcontroller reference manual, rev. 1 34.5.3.4 selecting a ne xus client register when the nexus-enable instruction is decoded by the tap controller, the input port allows development tool access to all nexus registers. each regist er has a 7-bit address index. all register access is performed via the select-dr-scan path. the ne xus controller defaults to the reg_select state when enabled. accessing a re gister requires two passes through the select-dr-scan path: one pass to sel ect the register and the second pa ss to read/write the register. the first pass through the select-dr-scan path is us ed to enter an 8-bit nexus command consisting of a read/write control bit in th e lsb followed by a 7-bit register address index, as illustrated in figure 34-11 . the read/write control bit is se t to 1 for writes and 0 for reads. the second pass through the select-dr-scan path is used to read or write the register data by shifting in the data (lsb first) during the sh ift-dr state. when reading a register , the register value is loaded into the ieee 1149.1-2001 shifter during the capture-dr state. when writing a register, the value is loaded from the ieee 1149.1-2001 shifter to th e register during the update-dr st ate. when reading a register, there is no requirement to shift out the entire regi ster contents. shifting ma y be terminated once the required number of bits have been acquired. table 34-11 illustrates a sequence which writes a 32-bit value to a register msb lsb 7-bit register index r/w figure 34-11. ieee 1149.1 controller command input table 34-11. write to a 32-bit nexus client register clock tms ieee 1149.1 state nexus state description 0 0 run-test/idle reg_selec t ieee 1149.1-2001 tap controller in idle state 1 1 select-dr-scan reg_select first pass through select-dr-scan path 2 0 capture-dr reg_select internal shifter loaded with current value of controller command input. 3 0 shift-dr reg_select tdo becomes active, and write bit and 6 bits of register index shifted in. 7 tcks 12 1 exit1-dr reg_select last bit of register index shifted into tdi 13 1 update-dr reg_select controller decodes and selects register 14 1 select-dr-scan data_access second pass through select-dr-scan path 15 0 capture-dr data_access internal shifte r loaded with current value of register 16 0 shift-dr data_access tdo becomes active, and outputs current value of register while new value is shifted in through tdi 31 tcks 48 1 exit1-dr data_access last bit of curr ent value shifted out tdo. last bit of new value shifted in tdi. 49 1 update-dr data_access value written to register 50 0 run-test/idle reg_select controller returned to idle state. it could also return to select-dr-scan to write another register.
nexus port controller (npc) 34-18 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 34.5.4 nexus jtag port sharing each of the individual nexus blocks on the device implements a tap cont roller for accessing its registers. when nexus has ownership of the tap, only the block whose nexus-ena ble instruction is loaded has control of the tap. this allows the interface to all of these individual tap controllers to appear to be a single port from outside the device. if no register is se lected as the shift path fo r a nexus block, that block acts like a single-bit shift register, or bypass register. 34.5.5 mcko mcko is an output clock to the development tools us ed for the timing of mseo and mdo pin functions. mcko is derived from the system cl ock and its frequency is determined by the value of the mcko_div field in the pcr. possible operating frequencies include system cloc k, one-half system clock, one-quarter system clock, and one-eighth system clock speed. the npc also generates an mcko clock gating cont rol output signal. this out put can be used by the mcko generation logic to gate the transmission of mcko when the auxiliary port is enabled but not transmitting messages. the setting of the mcko_gt bit inside the p cr determines whether or not mcko gating control is active. th e mcko_gt bit resets to a logic 0. in this state ga ting of mcko is disabled. to enable gating of mcko, the mcko_gt bi t in the pcr is written to a logic 1. 34.5.6 evto sharing the npc block controls sharing of the evto output between all nexus c lients that produce an evto signal. the npc assumes incoming evto signals will be asserted fo r one system clock period. after receiving a single clock period of asserted evto from any nexus client, the npc latches the result, and drives evto for one mcko period on the following clock. when there is no active mcko, such as in disabled mode, the npc drives evto for two system clock periods. evto sharing is active as long as the npc is not in reset. 34.5.7 nexus reset control the jcomp input that is used as th e primary reset signal for the npc is also used by the npc to generate a single-bit reset signal for other nexus blocks. if jcomp is negated, an inte rnal reset is asserted, indicating that all nexus modules should be held in rese t. internal nexus reset is also asserted when the device is in censored mode. 34.5.8 system clock locked indication following a power-on reset, mdo[0] can be monitored to provide the lo ck status of the system clock. mdo[0] is driven to a l ogic 1 until the system cloc k achieves lock after exit ing power-on reset. once the system clock is locked, mdo[0] is negated and tools may begi n nexus configuration. loss of lock conditions that occur subsequent to the exit of power-on reset and the initial lock of the system clock do not cause a nexus reset, and therefor e do not result in mdo[0] driven high.
nexus port controller (npc) freescale semiconductor 34-19 pxs20 microcontroller reference manual, rev. 1 34.6 initialization/application information 34.6.1 accessing npc tool-mapped registers to initialize the tap for nexus register a ccesses, the following sequence is required: 1. enable the nexus tap controller 2. load the tap controller with the nexus-enable instruction to write control data to npc tool-mapped re gisters, the followi ng sequence is required: 1. write the 7-bit register index a nd set the write bit to select the register with a pass through the select-dr-scan path in the ta p controller state machine. 2. write the register value with a second pass through the select-dr-scan path. note that the prior value of this register is shifted out during the write. to read status and control data from npc tool-m apped registers, the following sequence is required: 1. write the 7-bit register index and clear the write bit to sel ect register with a pass through select-dr-scan path in the ta p controller state machine. 2. read the register value with a second pass through the select-dr-scan path. data shifted in is ignored. see the ieee-isto 5001-2003 standard for more detail.
nexus port controller (npc) 34-20 freescale semiconductor pxs20 microcontroller reference manual, rev. 1
oscillators freescale semiconductor 35-1 pxs20 microcontroller reference manual, rev. 1 chapter 35 oscillators this chapter describes the following modules on this device: ? internal rc oscillator (ircosc) ? external oscillator (xosc) 35.1 ircosc 16 mhz internal rc oscillator the internal rc oscillator has a nom inal frequency of 16 mhz. the majo r features of the oscillator are: ? glitch-free oscillation ? 6-bit trimming the value of resistor is trimmed back using trim rct rim[5:0] of the rc_ctl re gister, so that the output clock frequency is never out of 1 % of 16 mhz over the process. after the oscillator is trimmed within this range using trim bits, the variation ov er the voltage and temperature is 5%. after power on reset, the trimming bi ts are provided by the flash options. table 35-1. rc digital interface registers - base address 0xc3fe_0060 register name address offset reset value rc_ctl 0x00 0x0000 offset 0x0 access: user read supervisor read/write 0123456789101112131415 r0000000000 rctrim w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset: 0000000000000000 = unimplemented or reserved figure 35-1. rc control register (rc_ctl)
oscillators 35-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 35.2 xosc external oscillator the external crystal oscillator (xos c) works in the range of 4?40 mhz. the xosc digital interface contains control and status registers accessible to applications. main features are: ? oscillator clock available interrupt ? oscillator bypass mode 35.2.1 functional description the external crystal oscillator circuit includes an internal oscillator dr iver and an external crystal circuitry. it provides an output clock that can be provided to th e fmpll or used as a reference clock to specific modules depending on system needs. the external crystal oscillator can be controll ed by the mc_me. the oscon bit of me_xxx_mcr registers controls the powerdown of oscillator based on the current device mode while s_osc of me_gs register provides the oscillat or clock available status. after system reset, the oscillator is powered down, and software must en able the oscillator when required. whenever the external crystal oscill ator is switched on from the off state, osccnt counter starts and when it reaches the value eocv[7:0]*512, the oscillator clock becomes available to the system. also an interrupt pending bit i_osc of osc_ctl register is set. an interrupt wi ll be generated if the interrupt mask bit m_osc is set. the oscillator circuit can be bypassed by setting osc_ctl[oscbyp]. this bit can only be set by the software. system reset is needed to reset this bit. in this bypass mode, the output clock has the same polarity as external clock applied on xtalout pin and the oscillator stat us is forced to ?1?. the bypass configuration is independent of th e powerdown mode of the oscillator. table 35-3 shows the truth table of different configurations of the oscillator. table 35-2. rc_ctl field descriptions field description rctrim main rc trimming bits table 35-3. truth table of the external crystal oscillator oscon oscbyp xtalin xtalout xosc_clk xosc mode 0 0 no crystal, hiz no crystal, hiz 0 power down, iddq x 1 x ext clock xtalout bypass, osc disabled 1 0 crystal crystal xtalout normal, osc enabled gnd ext clock xtalout normal, osc enabled
oscillators freescale semiconductor 35-3 pxs20 microcontroller reference manual, rev. 1 35.2.2 nvm interface the nvm provides the xosc with initial configurati on information based on the flash memory option bit located at biu4[1], the xosc osc illation margin bit, as follows: ? if biu4[1] = 1, the oscillation margin is hi gher, but the xosc consumes more power. ? if biu4[1] = 0, the oscillation margin is lo wer, and the xosc consumes less power. see the data sheet for the recommended value based on the oscillator frequency. 35.2.3 register description offset 0x0 access: user read supervisor read/write 0123456789101112131415 r oscbyp 1 notes: 1 you can read this field, and you can write a value of ?1? to it . writing a ?0? has no effect. a reset will also clear this bit. 0000000 eocv w reset: 0000000010000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r m_osc 0000000 i_osc 2 2 you can write a value of "0" or "1" to this field. however, writing a "1" will clear this field, and writing "0" will have no effect on the field value. 0 w reset: 0000000000000000 = unimplemented or reserved figure 35-2. external crystal oscillator control register (osc_ctl)
oscillators 35-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 table 35-4. rc_ctl field descriptions field description oscbyp external crystal oscillator bypass this bit specifies whether the osc illator should be bypassed or not. system reset is needed to reset this bit. 0: oscillator output is used as root clock. 1: xtalout is used as root clock. eocv end of count value these bits specify the end of count value to be used for comparison by the oscillator stabilization counter osccnt after reset or whenever it is swit ched on from the off state. this counting period ensures that external oscillator cl ock signal is stable before it can be selected by the system. when oscillator counter reaches the valu e eocv[7:0]*512, oscillator available interrupt request is generated. the reset value of this field depends on the device specification. the osccnt counter will be kept under reset if oscillator bypass mode is selected. m_osc external crystal oscillator clock interrupt mask 0: external crystal oscillato r clock interrupt is masked. 1: external crystal oscillato r clock interrupt is enabled. i_osc external crystal oscillator clock interrupt this bit is set by hardware when osccnt counter reac hes the count value eocv[7:0]*512. it is cleared by software by writing ?1?. 0: no oscillator clock interrupt occurred. 1: oscillator clock interrupt pending.
periodic interrupt timer (pit) freescale semiconductor 36-1 pxs20 microcontroller reference manual, rev. 1 chapter 36 periodic interrupt timer (pit) 36.1 introduction figure 36-1 shows the pit block diagram. figure 36-1. pit block diagram 36.1.1 overview this specification describes the func tion of the periodic interrupt timer block (pit). the pit is an array of timers that can be used to rais e interrupts and trigger dma channels. 36.1.2 features the main features of this block are: ? timers can generate dma trigger pulses ? timers can generate interrupts ? all interrupts are maskable ? independent timeout periods for each timer timer n timer 1 . . . pit registers peripheral interrupts peripheral pit . . . triggers bus bus clock
periodic interrupt timer (pit) 36-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 36.2 signal description the pit module has no external pins. 36.3 memory map and register description this section provides a detailed description of all registers accessi ble in the pit module. 36.3.1 memory map table 36-1 gives an overview on all pit registers. note register address = base address + a ddress offset, where the base address is defined at the mcu level and the a ddress offset is defined at the module level. note reserved registers will read as 0, writes will have no effect. table 36-1. pit memory map address offset use access 0x000 pit module control register r/w 0x004 - 0x0fc reserved r 0x100 - 0x10c timer channel 0 1 notes: 1 see ta bl e 3 6 - 2 0x110 - 0x11c timer channel 1 1 0x120 - 0x12c timer channel 2 1 0x130 - 0x13c timer channel 3 1 0x140 - 0x1fc reserved r table 36-2. timer channel n address offset use access channel + 0x00 timer load value register r/w channel + 0x04 current timer value register r channel + 0x08 timer control register r/w channel + 0x0c timer flag register r/w
periodic interrupt timer (pit) freescale semiconductor 36-3 pxs20 microcontroller reference manual, rev. 1 36.3.2 register descriptions this section describes in address order all the pit registers and their individual bits. 36.3.2.1 pit module control register (pitmcr) this register controls whether the timer clocks s hould be enabled and whether the timers should run in debug mode. table 36-3. pitmcr field descriptions 36.3.2.2 timer load value register (ldval) these registers select the timeout period for the timer interrupts. offset 0x000 access: read/write 0123456789101112131415 r 0 0 0 0 0 00000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0000 0 0 0 0 0 mdis frz w reset0000000000000000 figure 36-2. pit module co ntrol registers (pitmcr) field description mdis module disable. this is used to disable the module clock. this bit should be enabled before any other setup is done. 0 clock for pit timers is enabled (default) 1 clock for pit timers is disabled frz freeze. allows the timers to be stopped when the device enters debug mode. 0 = timers continue to run in debug mode. 1 = timers are stopped in debug mode.
periodic interrupt timer (pit) 36-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 36.3.2.3 current timer value register (cval) these registers indicate th e current timer position. offset channel_base + 0x00 access: read/write 0123456789101112131415 r tsv31 tsv30 tsv29 tsv28 tsv27 tsv26 tsv25 tsv24 t sv23 tsv22 tsv21 tsv20 tsv19 tsv18 tsv17 tsv16 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tsv15 tsv14 tsv13 tsv12 tsv11 tsv10 tsv9 tsv8 tsv7 tsv6 tsv5 tsv4 tsv3 tsv2 tsv1 tsv0 w reset0000000000000000 figure 36-3. timer load value register (ldval) table 36-4. ldval field descriptions field description tsv n time start value bits. these bits set the timer star t value. the timer will count down until it reaches 0, then it will generate an interrupt and load this register value again. writing a new value to this register will not restart the timer, instead the value will be loaded once the timer expires. to abort the current cycle and start a timer peri od with the new valu e, the timer must be disabled and enabled again (see figure 36-8 ).
periodic interrupt timer (pit) freescale semiconductor 36-5 pxs20 microcontroller reference manual, rev. 1 36.3.2.4 timer contro l register (tctrl) these register contain the control bits for each timer. offset channel_base + 0x04 access: read-only 0123456789101112131415 r tvl31 tvl30 tvl29 tvl28 tvl27 tvl26 tvl25 tvl24 tvl23 tvl22 tvl21 tvl20 tvl19 tvl18 tvl17 tvl16 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tvl15 tvl14 tvl13 tvl12 tvl11 tvl10 tvl9 tvl8 tvl7 tvl6 tvl5 tvl4 tvl3 tvl2 tvl1 tvl0 w reset0000000000000000 figure 36-4. current timer value register (cval) table 36-5. cval field descriptions field description tvl n current timer value. these bits represent the cu rrent timer value. note that the timer uses a downcounter. note: the timer values will be frozen in debug mo de if the frz bit is set in the pit module control register (see figure 36-2 ).
periodic interrupt timer (pit) 36-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 36.3.2.5 timer flag register (tflg) these registers hold the pit interrupt flags. offset channel_base + 0x08 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000000000 tie ten w reset0000000000000000 figure 36-5. timer control register (tctrl) table 36-6. tctrl field descriptions field description tie timer interrupt enable bit. 0 interrupt requests from timer x are disabled 1 interrupt will be requested whenever tif is set when an interrupt is pending (tif set), enablin g the interrupt will immediately cause an interrupt event. to avoid this, the associated tif flag must be cleared first. ten timer enable bit. 0 timer will be disabled 1 timer will be active
periodic interrupt timer (pit) freescale semiconductor 36-7 pxs20 microcontroller reference manual, rev. 1 36.4 functional description 36.4.1 general this section gives detailed informat ion on the internal operati on of the module. each timer can be used to generate trigger pulses as well as to generate inte rrupts, each interrupt will be available on a separate interrupt line. 36.4.1.1 timers the timers generate triggers at periodic intervals, wh en enabled. they load their start values, as specified in their ldval registers, then count down until they reach 0. then they load their respective start value again. each time a timer reaches 0, it will gene rate a trigger pulse, and set the interrupt flag. all interrupts can be enabled or masked (by setting th e tie bits in the tctrl re gisters). a new interrupt can be generated only after th e previous one is cleared. if desired, the current counter value of the timer can be read via the cval registers. offset channel_base + 0x0c access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000000000000 tif w reset0000000000000000 figure 36-6. timer flag register (tflg) table 36-7. tflg field descriptions field description tif time interrupt flag. tif is set to 1 at the end of the timer period.this flag can be cleared only by writing it with a 1. writing a 0 has no effect. if enabled (tie = 1), tif causes an interrupt request. 0 time-out has not yet occurred 1 time-out has occurred
periodic interrupt timer (pit) 36-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 the counter period can be restarte d, by first disabling, then enabling the timer with the ten bit (see figure 36-7 ). the counter period of a runni ng timer can be modified, by first disabli ng the timer, settin g a new load value and then enabling the timer again (see figure 36-8 ). it is also possible to change th e counter period without restarting the timer by wr iting the ldval register with the new load value. this value will then be loaded after the next trigger event (see figure 36-9 ). figure 36-7. stopping and starting a timer figure 36-8. modifying running timer period figure 36-9. dynamically setting a new load value 36.4.1.2 debug mode in debug mode the timers will be frozen - this is intended to aid software development, allowing the developer to halt the proces sor, investigate the current state of th e system (e.g. the timer values) and then continue the operation. 36.4.2 interrupts all of the timers support interrupt generation. refer to th e mcu specification for re lated vector addresses and priorities. p1 p1 timer enabled disable timer p1 start value = p1 trigger event p1 re-enable timer p1 timer enabled disable timer, start value = p1 trigger event re-enable timer p1 set new load value p2 p2 p2 p1 p1 timer enabled new start value p2 set p1 p2 start value = p1 p2 trigger event
periodic interrupt timer (pit) freescale semiconductor 36-9 pxs20 microcontroller reference manual, rev. 1 timer interrupts can be disa bled by setting the tie bits to zero. the timer interrupt flags (tif) are set to 1 when a timeout occurs on the associated timer, and are cleared to 0 by writing a 1 to that tif bit. 36.5 initialization and application information 36.5.1 example configuration in the example configuration: ? the pit clock has a frequency of 50 mhz ? timer 1 shall create an interrupt every 5.12 ms ? timer 3 shall create a trigger event every 30 ms first the pit module needs to be activated by writin g a 0 to the mdis bit in the pitctrl register. the 50 mhz clock frequency equates to a clock period of 20 ns . timer 1 needs to trigger every 5.12 ms/20 ns = 256000 cycles and timer 3 every 30 ms/20 ns = 1500000 cycles. the value for the ldval register trigger would be calculated as (period / clock period) -1. this means that ldval1 with 0003e7f f hex and ldval3 with 0016e35f hex. the interrupt for timer 1 is enabled by setting tie in the tctrl1 register. the ti mer is started by writing a 1 to bit ten in the tctrl1 register. timer 3 shall be used only for triggering. therefore ti mer 3 is started by writi ng a 1 to bit ten in the tctrl3 register, bit tie stays at 0. the following example code matches the described setup: // turn on pit pit_ctrl = 0x00; // timer 1 pit_ldval1 = 0x0003e7ff; // setup timer 1 for 256000 cycles pit_tctrl1 = tie; // enable timer 1 interrupts pit_tctrl1 |= ten; // start timer 1 // timer 3 pit_ldval3 = 0x0016e35f; // setup timer 3for 1500000 cycles pit_tctrl3 = ten; // start timer 3
periodic interrupt timer (pit) 36-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1
peripheral bridge (pbridge) freescale semiconductor 37-1 pxs20 microcontroller reference manual, rev. 1 chapter 37 peripheral bridge (pbridge) 37.1 introduction the peripheral bridge (pbridge) is the interface between the syst em bus and on-chip peripherals. accesses that fall within the address space of th e pbridge are decoded to provide individual module selects for peripheral devices on the slave bus interface. the pbridge will automatically ma nage peripheral access requests from software. in other words, you can access a peripheral using its memory-mapped interface without ha ving to configure the pbridge. however, the pbridge also supports special periphe ral access, such as memory protection, that is available for you to use if you need it. this device includes two instanti ations of the pbridge. these are called pbridge_0 and pbridge_1. 37.2 block interface figure 37-1. pbridge interface 37.3 features the following list summarizes th e key features of the pbridge: ? includes a 32-bit address bus and 64-bit data bus ? supports 32-bit slave peripherals (byte, halfwor d, and word reads and writes are supported by the bridge) ? provides configurable pe r-master access protections peripheral bridge system bus system bus crossbar switch (xbar) on-platform peripherals (pbridge) memory protection unit (mpu) off-platform peripherals
peripheral bridge (pbridge) 37-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? provides configurable per-peripheral access prot ections for both on-platform and off-platform peripherals 37.4 memory map and register description 37.4.1 register access all registers are 32-bit registers and can only be accessed in supervisor mode by trusted bus masters. additionally, these registers must only be read from or written to by a 32-bit aligned access. two system clock cycles are required for read accesses and three system cl ock cycles are required for write accesses to the pbridge registers. 37.4.2 memory map each register in the pbridge module has a si ze of 32 bits. the registers are listed in table 37-1 . the memory map organization is shown in table 37-2 . the organizational hierarchy is as follows: ? the module has multiple registers with the same register name (mprot, pacr, opacr), each at a different address offset. ? each register has multiple similarly-na med fields, each with a different number. ? each field has subfields as defi ned elsewhere in this section. accesses to registers or register fiel ds marked as reserved will return undefined data on reads, and will be ignored on writes. table 37-1. pbridge registers offset from pbridge_base pbridge0_0 = 0xfff0_0000 pbridge_1 = 0xfff0_4000 register access 1 notes: 1 in this column, r/w = read/write, r = read-only, and w = write-only. reset value location 0x0000?0x0007 2 2 this memory range contains reserved areas. see ta b l e 3 7 - 2 . master protection registers (mprot) r/w ? 3 3 see the associated description for more information. on page 37-3 0x0008?0x001f reserved 0x0020?0x003f 2 peripheral access control registers (pacr) r/w ? 3 on page 37-4 0x0040?0x006f 2 off-platform peripheral access control registers (opacr) r/w ? 3 on page 37-5 0x0070?0x3fff reserved
peripheral bridge (pbridge) freescale semiconductor 37-3 pxs20 microcontroller reference manual, rev. 1 37.4.3 register descriptions 37.4.3.1 master protec tion registers (mprot) each mprot register contains one or more 4-bit fields, called mprot n , as shown in table 37-2 . each of these fields defines the access privil ege level associated with bus master n in the platform. the registers provide one field pe r bus master. see section 15.1.4, logical master ids , for a list of master numbers and names. each mprot n field has the structure described in figure 37-2 and table 37-4 . table 37-2. pbridge memory map address offset register name bit numbers 0?3 4?7 8?11 12?15 16?19 20?23 24?27 28?31 0x0000 mprot mprot0 mprot1 mprot2 mprot3 mprot4 mprot5 mprot6 reserved 0x0004 (cut1) reserved 0x0004 (cut2/3) mprot8 mprot9 0x0020 pacr pacr0 pacr1 reserved pacr4 reserved 0x0024 reserved pacr9 reserved pacr14 pacr15 0x0028 pacr16 pacr17 pacr18 reserved 0x002c reserved 0x0040 opacr reserved opacr4 opacr5 opacr6 reserved 0x0044 reserved 0x0048 opacr16 opacr17 reserved opacr23 0x004c opacr24 reserved opacr31 0x0050 opacr32 opacr33 reserved opacr35 reserved opacr38 opacr39 0x0054 opacr40 opacr41 opacr42 reserved 0x0058 opacr48 opacr49 reserved 0x005c reserved opacr58 opacr59 reserved opacr62 reserved 0x0060 reserved opacr66 reserved opacr68 opacr69 reserved 0x0064 reserved 0x0068 reserved opacr86 opacr87 0x006c opacr88 opacr89 opacr90 reserved opacr92 opacr93 reserved
peripheral bridge (pbridge) 37-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 37-2. mprot n field structure 37.4.3.2 peripheral access control registers (pacr) each pacr register contains one or more 4-bit fields, called pacr n , as shown in table 37-2 . each of these fields defines the access levels supported by the associated module. the li sts of modules and their corresponding numbers are shown in table 37-6 . each pacr n field has the structure described in figure 37-3 and table 37-5 . 0123 r 0 mtr mtw mpl w reset 0see ta bl e 3 7 - 3 see ta bl e 3 7 - 3 see ta bl e 3 7 - 3 table 37-3. mprot n field reset values n mode mtr mtw mpl 0 lsm and dpm 1 1 1 1dpm1 1 1 8 lsm and dpm 1 1 1 9 (on cut1) lsm and dpm 1 1 1 9 (on cut2/3) dpm (on cut2/3) 1 1 1 all others lsm and dpm 0 0 0 table 37-4. mprot n field structure descriptions subfield description mtr master trusted for reads. this bit determines whether the master is trusted for read accesses. 0 this master is not trusted for read accesses. 1 this master is trusted for read accesses. mtw master trusted for writes. this bit determines whether the master is trusted for write accesses. 0 this master is not trusted for write accesses. 1 this master is trusted for write accesses. mpl master privilege level. this bit determines how the privilege level of the master is determined. 0 accesses from this master are forced to user-mode. 1 accesses from this master are not forced to user-mode.
peripheral bridge (pbridge) freescale semiconductor 37-5 pxs20 microcontroller reference manual, rev. 1 figure 37-3. pacr n field structure 37.4.3.3 off-platform pe ripheral access contro l registers (opacr) the opacr defines the access leve ls supported by the associated m odule. each opacr has a format identical to the pacr described in section 37.4.3.2, periphe ral access control registers (pacr). 0123 r 0 sp wp tp w reset 0100 1 notes: 1 the reset state of pacr0[tp] is 1, not 0. pacr0 [sp] and pacr0[tp] are hard wired to 1 and cannot be changed. therefore, untrusted masters or user-mode accesses are always denied. table 37-5. pacr n field structure descriptions subfield description sp supervisor protect. this bit determines whether the peripheral requires supervisor privilege level for access. 0 this peripheral does not require supervisor privilege level for accesses. 1 this peripheral requires supervisor privilege level for accesses. the mprotx[mpl] control bit for the master must be set. if not, the access is te rminated with an error response and no peripheral access is initiated on the ips bus. wp write protect. this bit determines wh ether the peripheral allows write accesses. 0 this peripheral allows write accesses. 1 this peripheral is write protected. if a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the ips bus. tp trusted protect. this bit determines whether the per ipheral allows accesses from an untrusted master. 0 accesses from an untrusted master are allowed. 1 accesses from an untrusted master are not allow ed. if an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the ips bus. table 37-6. on-platform peripherals and pacr numbers peripheral pacr number pbridge 0 xbar 1 mpu 4 sema4 9 swt 14 stm 15 ecsm 16 edma 17 intc 18
peripheral bridge (pbridge) 37-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 the lists of off-platform modules and th eir corresponding numbers are listed in table 37-7 . the opacr number mirrors the pctl column of table 2-1 in chapter 2, memory map . table 37-7. off-platform peripherals and opacr numbers peripheral opacr number dspi 0 4 dspi 1 5 dspi 2 6 flexcan 0 16 flexcan 1 17 dma_mux 23 flexray controller 24 bam 31 adc0 32 adc1 33 ctu 35 etimer 0 38 etimer 1 39 etimer 2 40 flexpwm 0 41 flexpwm 1 42 linflex 0 48 linflex 1 49 crc 58 fccu 59 swg 62 flash0 66 siul 68 wkpu 69 sscm 86 mc_me 87 mc_cgm 88 mc_rgm 89 mc_pcu 90 pit 92 stcu 93
peripheral bridge (pbridge) freescale semiconductor 37-7 pxs20 microcontroller reference manual, rev. 1 37.5 functional description the pbridge serves as an interface between a system bus and the peripheral (slave) bus. it functions as a protocol translator. acces ses that fall within the address space of the pbridge are decoded to provide individual module selects for periphera l devices on the slave bus interface. there is no need to configure the pbridge registers unless the default master and/or peripheral access privileges need to be changed. 37.5.1 access support aligned 64-bit word accesses, halfword accesses, and byte accesses are supported for the peripherals. peripheral registers must not be misaligned, although no explicit chec king is performe d by the pbridge. note data accesses that cross a 32 -bit boundary are not supported. 37.5.1.1 peripheral write buffering buffered writes are not supported by the pbridge. 37.5.1.2 read cycles two-clock read accesses are possibl e with the pbridge when the reque sted access size is 32-bits or smaller, and is not misali gned across a 32-bit boundary. 37.5.1.3 write cycles three clock write accesses are possible with the pbri dge when the requested access size is 32-bits or smaller. misaligned writes that cr oss a 32-bit boundary are not supported. 37.5.2 general operation slave peripherals are modules that contain readable/wri table control and status re gisters. the system bus master reads and writes these re gisters through the pbridge. the p bridge generates module enables, the module address, transfer attribut es, byte enables, and writ e data as inputs to th e slave peripherals. the pbridge captures read data from the slave interface and dr ives it on the system bus. the pbridge occupies a 64 mb portion of the address space. the register maps of the slave peripherals are located on 16-kb boundaries. each slave peripheral is allocated one 16-kb block of the memory map, and is activated by one of the module enables from the pbridge. the pbridge is responsible for indica ting to slave peripherals if an access is in supe rvisor or user mode. all edma and flexray transfers are done in supervisor mode.
peripheral bridge (pbridge) 37-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1
power control unit (mc_pcu) freescale semiconductor 38-1 pxs20 microcontroller reference manual, rev. 1 chapter 38 power control unit (mc_pcu) 38.1 introduction 38.1.1 overview the power control unit (mc_pcu) acts as a bridge for mapping the pmu peripheral to the mc_pcu address space. figure 38-1 depicts the mc_pcu block diagram. registers platform interface mc_pcu figure 38-1. mc_pcu block diagram mapped module interface mapped peripheral core
power control unit (mc_pcu) 38-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 38.1.2 features the mc_pcu includes the following features: ? maps the pmu registers to the mc_pcu address space 38.2 external signal description the mc_pcu has no connections to any external pins . 38.3 memory map and register definition 38.3.1 memory map note any access to unused registers as we ll as write accesses to read-only registers will: ? not change register content ? cause a transfer error table 38-1. mc_pcu register description address name description size access location user supervisor test 0xc3fe _8040 pcu_pstat power domain status register word read read read on page 38-3 table 38-2. mc_pcu memory map address name 01232756789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0xc3fe _80004 ? 0xc3fe _803c reserved 0xc3fe _8040 pcu_pstat r0000000000000000 w r pd0 w 0x044 ? 0x07c reserved
power control unit (mc_pcu) freescale semiconductor 38-3 pxs20 microcontroller reference manual, rev. 1 38.3.2 register descriptions all registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. the bytes are ordered according to big endian. for example, the pd0 field of the pcu_pstat register may be accessed as a word at address 0xc3fe_8040, as a half-word at address 0xc3fe_8042, or as a byte at address 0xc3fe_8043. 38.3.2.1 power domain status register (pcu_pstat) this register reflects the power stat us of all available power domains. 0xc3fe _8080 ? 0xc3fe _80fc pmu registers 0xc3fe _8100 ? 0xc3fe _bffc reserved address 0xc3fe_8040 access: user read, supervisor read, test read 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pd0 w reset0000000000000001 figure 38-2. power domain status register (pcu_pstat) table 38-3. power domain status register (pcu_pstat) field descriptions field description pd n power status for power domain # n 0 power domain is inoperable 1 power domain is operable table 38-2. mc_pcu memory map (continued) address name 01232756789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
power control unit (mc_pcu) 38-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1
power management unit (pmu) freescale semiconductor 39-1 pxs20 microcontroller reference manual, rev. 1 chapter 39 power management unit (pmu) 39.1 overview the pmu generates the 1.2 v core lo gic supply from a 3.3 v (nominal) input supply by means of a linear voltage regulator driving an external npn bipolar transistor (e mitter-follower configurat ion) or an internal pmos fet. the pmu always starts up usi ng the internal ballast transistor. it then executes an automatic procedure that detects (during the system re set phase) whether an extern al ballast transistor is operational. if a functional external ballast transistor is detected, the system is supplied by the extern al transistor only. the information whether the internal or the external ballast tr ansistor is used is availa ble via a bit in one of the pmu registers. the operating voltages are monitored by a set of on-chip supervisory circui ts to ensure that this device works within the correct volta ge range. these circuits are: ? low-voltage inhibit (lvi), also known as low-voltage detector (lvd) ? high-voltage inhibit (hvi), also known as high-voltage detector (hvd) ? comparators main digital low- and high-voltage m onitoring circuits are tested by inte grated self test circuitry. the voltage regulator, io and flash dedicated low voltag e monitoring circuitries ar e redundant in order to improve the safety coverage. the lvds and the comp arators provide their output signals to the reset generation module (mc_rgm) and to the fccu. 39.2 block diagram the pmu block diagram and it s components are shown in figure 39-1 and table 39-1 , respectively.
power management unit (pmu) 39-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 39-1. pmu block diagram 39.3 high-power regulators the pmu includes two high-power re gulators, hpreg1 and hpreg2. hpreg1 uses internal ballast to support the core current, whereas hp reg2 gets on only when external npn is present on board to supply core current. the devi ce always powers up using hpreg1. if an external npn is present, the device then makes a transition from hpreg1 to hpreg2. this transition is dynamic. once hpreg2 is fully operational, controller part of hpreg1 is switched off. if an external npn is connected to the device, hpreg2 takes control. the output voltage of hpreg2 is higher than hpreg1. this gu arantees that internal ba llast (hpreg1) gets off as soon as external npn takes control. the base of the bipolar is driven by a control signal generate d by the control part and available on a dedicated pin (bctrl). table 39-1. pmu blocks abbreviation block name block function hpreg1 high-power regulator 1 provides internal ballast to support core current hpreg2 high-power regulator 2 provides external npn to support core current lvd_main_1 low-voltage detector 1 mon itors the 3.3 v supply of vddio lvd_main_2 low-voltage detector 2 mon itors the 3.3 v supply of vddreg lvd_main_3 low-voltage detector 3 mon itors the 3.3 v supply of vddflash lvd_dig_main main digital low-voltage detector monitors the 1.2 v digital core supply (hpvdd) lvd_dig_bkup backup digital low-voltage detecto r assists in the self-test of lvd_dig_main hvd_dig_main main digital high-voltage detector monitors the 1.2 v digital core supply (hpvdd) hvd_dig_bkup backup digital high-voltage detector assists in the self-test of lvd_dig_main lvd_main_1 lvd_main_2 lvd_main_3 lvd_dig_main lvd_dig_bkup hvd_dig_main hvd_dig_bkup power-on circuitry hpreg1 hpreg2 vddio and flash memory core core current comparator
power management unit (pmu) freescale semiconductor 39-3 pxs20 microcontroller reference manual, rev. 1 the supported bipolar transistor are the bcp68 (on semiconductor) and the bcx68 (infineon). immediately after power-on reset, the pmu trims the output voltage us ing factory-specified parameters. the nominal target output af ter this trimming is 1.28 v. the stabilization for hpreg is achieved using an exte rnal capacitance. the minimum required value is two 6 ? f capacitors. note the aforementioned minimum external ca pacitance value has to take into account the tolerance, temperature, vol tage and aging variation. be sure to limit the series inductance per pad to less than 13 nh. 39.4 high- and low-voltage detectors (hvd, lvd) two kind of lvds are available: ? lvd_main (3 blocks) for the 3.3v input supply with thresholds at 3.3 v level ? lvd_dig for the 1.2 v output voltage lvd_main_1 senses the vddio supply and provides information to the sy stem if vddio is not in the proper range. if the voltage is not in the proper range, the sy stem responds with a reset. lvd_main_2 senses the vddreg supply and provides in formation to the system if vddreg is not in the proper range. if the voltage is not in the proper range, the system responds with a reset. lvd_main_3 senses the vddflash s upply and provides information to the system if vddflash is not in the proper range. if the voltage is not in the proper range, the system responds with a reset. the lvd_dig_main and lvd_dig_bkup blocks se nse the hpreg output an d provides information to the system if the output is not in the proper range. if the output is not in the proper range, the system responds with a reset. the hvd_dig_main and hvd_dig_bkup blocks also sense the hpreg output and provides information to the system if the output is not in the proper range. if the output is not in the proper range, the system responds with a reset. the por is required to initialize the device during s upply rise. the por works only on the rising edge of main supply. to ensure its functioning during the foll owing rising edge of the supply, it is reset by the output of either of main_lvd_1 or main_lvd_2 or main_lvd_3. when main supply reaches below the lower voltage threshold of any of these lvds, po r is reset and ready to work on next rising edge. when supply is below the por threshold, por output will be high and will follow the supply. when sufficient supply threshold is reached, por will trigger and give ?0? level as output 39.4.1 current comparator this block mirrors a portion of the current flowing th rough the internal ballast. this current is compared with a reference current. if this ballast current is mo re than the reference curren t, the output of the block is logic ?0? which indicates that there is no external npn available on the board. in reverse case the output
power management unit (pmu) 39-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 of the block is logic ?1? which indicates the availabi lity of the external npn. along with this circuit an option byte might also available to give the information about the availability of external npn. 39.5 power-up and initialization after the device powers up, the pmu: ? automatically detects whether an external ballast is present ? applies the factory-specified trimming to the output ? performs the built-in self-test (bist) the high-voltage detector is disabl ed while the pmu is initializating (detecting the external ballast and applying proper trimmi ng), especially during the pha se where the switchover occu rs. therefore, if during that time there is an overshoot of the 1.2 v supply, no reset is triggered. 39.6 built in self-test (bist) the pmu provides (to the user) the so ftware capability to check the run of the bist proc edure, generating non-critical faults (n cfs) or critical faults (cf) conditions for the fccu module. to provide the necessary redundancy, the logic and of the two compar ator outputs (from the main and back-up circuitries) is us ed as global system reset. at each power-on, the self-test circuitr y is able to detect a failure of one of the tw o lvds and to provide an ncf to the fccu. the bist flow is shown in figure 39-2 . the bist execution is controlled by the pmuctrl_ctrl[silht] field. figure 39-2. built-in self test flow table 39-2 shows the critical and non-critical faul ts generated by the pmu during bist mode. lv d (silht = 00) write silht = 01 idle mode test mode (silht = 01) hvd test mode (silht = 10) write silht = 10 automatically at the end of test
power management unit (pmu) freescale semiconductor 39-5 pxs20 microcontroller reference manual, rev. 1 all faults are monitored by the following fields in the pmuctrl_fault register: ?lhcf ?lncf ? hncf before clearing the hvd and lvd crit ical fault by means of the fccu, you must clear the following four pending fields in the pm uctrl_irqs register: ?mlvdp ?blvdp ? mhvdp ? bhvdp the critical fault number will be kept asserted as long as one of these fields is '1'. when the pmu enters lvd or hvd test mode, it is not allowed to enter stop mode. if the device enters stop mode after the pending status pi n has been set it is not possible to reset it by sw until the cpu clock is stopped. the pmu can assert two fa ults on flash voltage monitor, two fa ults on io voltage monitor and two faults on regulator voltage monitor (corresponding to failure of either the main or backup lvds). they are asserted (active low) during the power up phase, if a rising edge is not detected on the related lvd. each fault from the pmu sets: ? its corresponding pending bit inside the pmuctrl_ir qs register. if the associated interrupt in the pmuctrl_irqe register is enabled, the pmu will send an irq to the intc. ? its corresponding non critical fault 39.7 memory map and register description the pmu memory map is shown in table 39-3 . the pmu registers are mapped into the mc_pcu address space (base address: 0xc3fe_8080). table 39-2. fault assertion conditions fault number signal ncf[13] lvd bist ok in test mode/ lvd nok in user mode ncf[14] hvd bist ok in test mode/ hvd nok in user mode ncf[15] 1 notes: 1 it can only be checked once after destructive reset. once cleared they will be disabled permanently until the next destructive reset lvd vreg fault detected by self-checking ncf[16] 1 lvd flash fault detected by self-checking ncf[17] 1 lvd io fault detected by self-checking cf[21] lvd/hvd bist failure result in test mode
power management unit (pmu) 39-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 39.7.1 pmuctrl status register (pmuctrl_status) figure 39-3. pmuctrl status register (pmuctrl_status) table 39-3. pmu memory map register name address offset location reserved 0x04?0x3f ? pmu status register (pmuctrl_status) 0x40 on page 39-6 pmu control register (pmuctrl_ctrl) 0x44 on page 39-7 reserved 0x49?0x6f ? pmu mask fault register (pmuctrl_maskf) 0x70 on page 39-7 pmu fault monitor register (pmuctrl_fault) 0x74 on page 39-8 pmu interrupt request status register (pmuctrl_irqs) 0x78 on page 39-9 pmu interrupt request enable register (pmuctrl_irqe) 0x7c on page 39-11 address: base + 0x40 0123456789101112131415 r 11 enpn 0 0000 0000 0000 w reset 1100000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rctb 0000 000000 0110 w reset 0100000000000110 table 39-4. pmuctrl_status field descriptions field description enpn external npn status flag 0 external npn not detected 1 external npn detected ctb configuration trace bits. this field describes the pmu use case after initialization. 00 reserved (not used on this device) 01 internal ballast mode without npn 10 external ballast mode detection with npn 11 reserved (not used on this device)
power management unit (pmu) freescale semiconductor 39-7 pxs20 microcontroller reference manual, rev. 1 39.7.2 pmuctrl control re gister (pmuctrl_ctrl) this register allows you to start or stop the lvd/hvd bist procedure. figure 39-4. pmuctrl contro l register (pmuctrl_ctrl) 39.7.3 pmuctrl mask fault register (pmuctrl_maskf) this register allows you to mask the possible non-critical faults that are described in the pmuctrl_fault register. address: base + 0x44 0123456789101112131415 r 0 0 00 0000 0000 0000 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000 000000 00 silht w reset 0000000000000000 table 39-5. pmuctrl_ctrl field descriptions field description silht start idle or lvd or hvd bist on main and backup lines 00 idle mode 01 start main and backup lvd bist mode 10 start main and backup hvd bist mode 11 reserved note: on the completion of the lvd/hvd bist operation, the silht field clears itself (returns to idle mode).
power management unit (pmu) 39-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 39-5. pmuctrl mask faul t register (pmuctrl_maskf) 39.7.4 pmuctrl fault monitor register (pmuctrl_fault) figure 39-6. pmuctrl fault moni tor register (pmuctrl_fault) address: base + 0x70 0123456789101112131415 r mf_bb 0000 0000 0000 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000 000000 00 00 w reset 0000000000000000 table 39-6. pmuctrl_maskf field descriptions field description mf_bb mask fault bypass ballast. this field defines the mask for the nbypass_ballast_lv[3:0] bus. 0 mf_bb[n], means bypass_ballast_lv[n] = ?0 ?; where n goes from 3 down to 0. 1 mf_bb[n], means bypass_ballast_lv[n] = not nbypass_ballast_lv[n]; where n goes from 3 down to 0. address: base + 0x74 0123456789101112131415 r bb_lv 0000 0000 0 flncf ioncf rencf w reset 1000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000 000000 0 lhcf lncf hncf w reset 0000000000000000
power management unit (pmu) freescale semiconductor 39-9 pxs20 microcontroller reference manual, rev. 1 39.7.5 pmuctrl interrupt request status register (pmuctrl_irqs) this register allows you to read a nd clear the various pmu in terrupt status bits. to clear these bits, write a ?1? to them. table 39-7. pmuctrl_fault field descriptions field description bb_lv bypass ballast low voltage. this field moni tors the not of nbyp ass_ballast_lv[3:0] bus. 0 bb_lv[n] = not (nbypass_ballast_lv[n] = ?1?); where n goes from 3 down to 0 1 bb_lv[n] = not (nbypass_ballast_lv[n] = ?0?); where n goes from 3 down to 0 flncf flash memory voltage monitor non-critical fault 0 no flash memory voltage monitor fault is active 1 flash memory voltage monitor fault is active ioncf io voltage monitor non-critical fault 0 no io voltage monitor fault is active 1 io voltage monitor fault is active rencf regulator voltage monitor non-critical fault 0 no regulator voltage monitor fault is active 1 regulator voltage monitor fault is active lhcf low high voltage detector critical fault 0 no low high voltage fault is active 1 low high voltage fault is active lncf low voltage detector non-critical fault 0 no low voltage fault is active 1 low voltage fault is active hncf high voltage detector non-critical fault 0 no high voltage fault is active 1 high voltage fault is active
power management unit (pmu) 39-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 39-7. pmuctrl interrupt request status register (pmuctrl_irqs) address: base + 0x78 0123456789101112131415 r 0000 0000 00 mfvmp bfvmp mivmp bivmp mrvmp brvmp w w1c w1c w1c w1c w1c w1c reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000 000000 mlvdp blvdp mhvdp bhvdp w w1c w1c w1c w1c reset 0000000000000000 table 39-8. pmuctrl_irqs field descriptions field description mfvmp main flash voltage monitor interrupt pending. 0 no main flash voltage monitor interrupt fault error 1 main flash voltage monitor interrupt fault error bfvmp backup flash voltage monitor interrupt pending. 0 no backup flash voltage monitor interrupt fault error 1 backup flash voltage monitor interrupt fault error mivmp main io voltage monitor interrupt pending. 0 no main io voltage monitor interrupt fault error 1 main io voltage monitor interrupt fault error bivmp backup io voltage monitor interrupt pending. 0 no back_up io voltage monitor interrupt fault error 1 back_up io voltage monitor interrupt fault error mrvmp main regulator voltage monitor interrupt pending. 0 no main regulator voltage monitor interrupt fault error 1 main regulator voltage monitor interrupt fault error brvmp backup regulator voltage monitor interrupt enable. 0 no backup regulator voltage monitor interrupt fault error 1 backup regulator voltage monitor interrupt fault error mlvdp main low voltage detector error interrupt pending. 0 no main low voltage detector out interrupt error 1 main low voltage detector out interrupt error blvdp backup low voltage detector error interrupt pending. 0 no backup low voltage detector out interrupt error 1 backup low voltage detector out interrupt error
power management unit (pmu) freescale semiconductor 39-11 pxs20 microcontroller reference manual, rev. 1 39.7.6 pmuctrl interrupt request enable register (pmuctrl_irqe) this register allows you to enable or disable the various pmu interrupts. figure 39-8. pmuctrl interrupt request enable register (pmuctrl_irqe) mhvdp main high voltage detector error interrupt pending. 0 no main high voltage detector out interrupt error 1 main high voltage detector out interrupt error bhvdp backup high voltage detector error interrupt pending. 0 no back_up high voltage detector out interrupt error 1 back_up low voltage detector out interrupt error address: base + 0x7c 0123456789101112131415 r 0000 0000 00 mfvme bfvme mivme bivme mrvme brvme w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000 000000 mlvde blvde mhvde bhvde w reset 0000000000000000 table 39-9. pmuctrl_irqe field descriptions field description mfvme main flash voltage monitor interrupt enable. 0 main flash voltage monitor interrupt fault error disabled 1 main flash voltage monitor interrupt fault error enabled bfvme backup flash voltage monitor interrupt enable. 0 backup flash voltage monitor interrupt fault error disabled 1 backup flash voltage monitor interrupt fault error enabled mivme main io voltage monitor interrupt enable. 0 main io voltage monitor interrupt fault error disabled 1 main io voltage monitor interrupt fault error enabled bivme backup io voltage monitor interrupt enable. 0 backup io voltage monitor interrupt fault error disabled 1 backup io voltage monitor interrupt fault error enabled table 39-8. pmuctrl_irqs field descriptions (continued) field description
power management unit (pmu) 39-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 mrvme main regulator voltage monitor interrupt enable. 0 main regulator voltage monitor interrupt fault error disabled 1 main regulator voltage monitor interrupt fault error enabled brvme backup regulator voltage monitor interrupt enable. 0 back_up regulator voltage monitor interrupt fault error disabled 1 back_up regulator voltage monitor interrupt fault error enabled mlvde main low voltage detector error interrupt enable. 0 main low voltage detector out interrupt error disabled 1 main low voltage detector out interrupt error enabled blvde backup low voltage detector error interrupt enable. 0 backup low voltage detector out interrupt error disabled 1 backup low voltage detector out interrupt error enabled mhvde main high voltage detector error interrupt enable. 0 main high voltage detector out interrupt error disabled 1 main high voltage detector out interrupt error enabled bhvde backup high voltage detector error interrupt enable. 0 no backup high voltage detector out interrupt error disabled 1 backup low voltage detector out interrupt error enabled table 39-9. pmuctrl_irqe field descriptions (continued) field description
register protection (reg_prot) freescale semiconductor 40-1 pxs20 microcontroller reference manual, rev. 1 chapter 40 register protection (reg_prot) 40.1 introduction 40.1.1 overview the reg_prot module offers a mechanism to protect defined memory-mapped address locations in a module under protection from being written. the a ddress locations that can be protected are module-specific. the protection module is located between the m odule under protection and the pbridge. (for an explanation of the re g_prot and module base addresses, see section 40.3, memory map and register definition .) this is shown in figure 40-1 . figure 40-1. reg_prot block diagram 40.1.2 features the reg_prot includes these distinctive features: ? restrict write accesses for the module unde r protection to supervisor mode only ? lock registers for first 6 kb of memory-mapped address space ? write to address mirror automa tically sets corre sponding lock bit ? once configured lock bits can be protected from changes pbridge supervisor access / lock registers module under protection reg_prot module write data address / access size uaa hlb gcr access allowed? peripheral enable other control signals peripheral enable
register protection (reg_prot) 40-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 40.1.3 modes of operation the reg_prot module is operable when the module under protection is operable. 40.2 external signal description there are no external signals. 40.3 memory map and register definition this section provides a detailed description of the memory map of a module using the reg_prot. the original 16 kb module memory space is divided into 5 areas as shown in figure 40-2 . figure 40-2. reg_prot memory diagram area 1 is 6 kb and holds the norma l functional module registers and is transparent for all read/write operations. area 2 is 2 kb starting at address 0x1800 is a reserved area, which shall not be accessed. area 3 is 6 kb, starting at addres s 0x2000 and is a mirror of area 1. a read/write access to these 0x2000+x addresses will read/write the regi ster at address x. however, a write access to address 0x2000+x will additionally set the optional soft lock bits for this address x in the same cycle as the register at address x is written. this provides an atomic write and lock operation. not all registers in area 1 need to have protection defined by associated soft lock bits. for unpr otected registers at addres s y, accesses to address 0x2000+y will be identical to accesse s at address y. only for register s implemented in area 1 and defined as protectable soft lock bits will be available in area 4. module register space base + 0x0000 6kb 2 kb reserved mirror module register space 6kb 1.5 kb lock bits with user defined base + 0x1800 base + 0x2000 base + 0x3800 soft locking function 512 bytes configuration base + 0x3e00 base + 0x3fff area 1 area 2 area 3 area 4 area 5
register protection (reg_prot) freescale semiconductor 40-3 pxs20 microcontroller reference manual, rev. 1 area 4 is 1.5 kb and holds the soft lock bits, one bit pe r byte in area 1. the four soft lock bits associated with one module register word are arranged at byt e boundaries in the memory map. the soft lock bit registers can be directly written using a bit mask. area 5 is 512 bytes and holds the configuration bits of the protection mode. th ere is one configuration hard lock bit per module that prevents all further mo difications to the soft lo ck bits and can only be cleared by a system reset once set. the other bits, if set, will allow user acce ss to the protected module. if any locked byte is accessed with a write transaction, a transf er error will be issued to the system and the write transaction will not be ex ecuted. this is true even if not all accessed bytes are locked. accessing unimplemented 32-bit regi sters in areas 4 and 5 will result in a transfer error. 40.3.1 memory map figure 40-1 gives an overview on the reg_prot registers implemented. note reserved registers in area #2 will be handled according to the protected ip (module under protection). table 40-1. reg_prot memory map address offset use location 0x0000 module register 0 (mr0) on page 40-4 0x0001 module register 1 (mr1) on page 40-4 0x0002 module register 2 (mr2) on page 40-4 0x0003? 0x17ff module register 3 (mr3) - module register 6143(mr6143) on page 40-4 0x1800? 0x1fff reserved 0x2000 module register 0 (mr0) + set soft lock bit 0 (lmr0) on page 40-4 0x2001 module register 1 (mr1) + set soft lock bit 1 (lmr1) on page 40-4 0x2002? 0x37ff module register 2 (mr2) + set soft lock bit 2 (lmr2) - module register 6143 (mr6143) + set soft lock bit 6143 (lmr6143) on page 40-4 0x3800 soft lock bit register 0 (slbr0): soft lock bits 0-3 on page 40-4 0x3801 soft lock bit register 1 (slbr1): soft lock bits 4-7 on page 40-4 0x3802? 0x3dff soft lock bit register 2 (slbr2): soft lock bits 8-11 - soft lock bit register 1535 (slbr1535): soft lock bits 6140-6143 on page 40-4 0x3e00? 0x3ffb reserved 0x3ffc global configuration register (gcr) on page 40-5
register protection (reg_prot) 40-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 40.3.2 register descriptions this section describes in address order all the reg_pr ot registers. each descri ption includes a standard register diagram with an associated figure number. details of register bit and field function follow the register diagrams, in bit order. 40.3.2.1 module registers (mr0-6143) this is the lower 6 kb module memory space which hol ds all the functional regi sters of the module that is protected by the reg_prot module. 40.3.2.2 module register and set soft lock bit (lmr0-6143) this is memory area #3 that provides mirrored acce ss to the mr0-6143 registers with the side effect of setting soft lock bits in case of a write access to a mr that is defined as protectable by the locking mechanism. each mr is protectable by one associated bit in a slbr n [slb m ], according to the mapping described in table 40-2 . 40.3.2.3 soft lock bit register (slbr0-1535) these registers hold the soft lock bits fo r the protected registers in memory area #1. figure 40-3. key to register fields always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit offset: 0x3800-0x3dff access: read always supervisor write 01234567 r0000 slb0 slb1 slb2 slb3 w we0 we1 we2 we3 reset00000000 figure 40-4. soft lock bit register (slbr n )
register protection (reg_prot) freescale semiconductor 40-5 pxs20 microcontroller reference manual, rev. 1 table 40-3 gives some examples how slbr n [slb] and mr n go together. 40.3.2.4 global configuration register (gcr) this register is used to make global c onfigurations related with the reg_prot. table 40-2. slbr n field descriptions field description we0 we1 we2 we3 write enable bits for soft lock bits (slb): we0 enables writing to slb0 we1 enables writing to slb1 we2 enables writing to slb2 we3 enables writing to slb3 1 value is written to slb 0 slb is not modified slb0 slb1 slb2 slb3 soft lock bits for one mr n register: slb0 can block accesses to mr{ n *4 + 0} slb1 can block accesses to mr{ n *4 + 1} slb2 can block accesses to mr{ n *4 + 2} slb3 can block accesses to mr{ n *4 + 3} 1 associated mr n byte is locked against write accesses 0 associated mr n byte is unprotected and writeable table 40-3. soft lock bits vs. protected address soft lock bit protected address slbr0[slb0] mr0 slbr0[slb1] mr1 slbr0[slb2] mr2 slbr0[slb3] mr3 slbr1[slb0] mr4 slbr1[slb1] mr5 slbr1[slb2] mr6 slbr1[slb3] mr7 slbr2[slb0] mr8 ... ... offset: 0x3ffc access: read always supervisor write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r hlb 0000000 uaa 00000000000000000000000 w reset00000000000000000000000000000000 figure 40-5. global configuration register (gcr)
register protection (reg_prot) 40-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 note the gcr[uaa] bit has no effect on the allowed access modes for the registers in the reg_prot module. 40.4 functional description 40.4.1 general this module provides a generic regist er (address) write-prot ection mechanism. the protection size can be: ? 32-bit (address == multiples of 4) ? 16-bit (address == multiples of 2) ? 8-bit (address == multiples of 1) ? unprotected (address == multiples of 1) the list of protected modules and registers is shown in section 40.6, pxs20 registers under protection. for all addresses that are protected there are slbr n [slb m ] bits that specify whether the address is locked. when an address is locked it can only be read but not written in any mode (s upervisor/normal). if an address is unprotected the corresponding slbr n [slb m ] bit is always 0b0 no ma tter what software is writing to. 40.4.2 change lock settings to change the setting whether an address is locked or unlocked the corresponding slbr n [slb m ] bit needs to be changed. this can be done using the fo llowing methods: ? modify the slbr n [slb m ] directly by writing to area #4 ? set the slbr n [slb m ] bit(s) by writing to the mirror module space (area #3) both methods are explained in the following sections. table 40-4. gcr field descriptions field description hlb hard lock bit. this register can not be cleared on ce it is set by software. it ca n only be cleared by a system reset. 1 all slb bits are write protected and can not be modified. 0 all slb bits are accessible and can be modified. uaa user access allowed. 1 the registers in the module under protection can be accessed in the mode defined for the module registers without any addi tional restrictions. 0 the registers in the module under protection ca n only be written in supervisor mode. all write accesses in non-supervisor mode are not executed and a transfer error is issued. this access restriction is in addition to any access rest rictions imposed by the protected ip module.
register protection (reg_prot) freescale semiconductor 40-7 pxs20 microcontroller reference manual, rev. 1 40.4.2.1 change lock settings directly via area #4 memory area #4 contains the lock bits. they can be modified by writing to them. each slbr n [slb m ] bit has a mask bit slbr n [we m ] which protects it from bein g modified. this masking makes clear-modify-write op erations unnecessary. figure 40-6 shows two modification examples . in the left example there is a write access to the slbr n register specifying a mask value wh ich allows modification of all slbr n [slb m ] bits. the example on the right specifies a mask which only al lows modification of the bits slbr n [slb{3:1}]. figure 40-6. change lock settings directly via area #4 figure 40-6 showed four registers that can be protected with 8-bit protection. regi sters with 16- and 32- bit protection are shown in figure 40-7 and figure 40-8 , respectively. figure 40-7. change lock settings for 16-bit protected addresses on the right side of figure 40-7 you can see that the data written to slbr n [slb{0}] is automatically written to slbr n [slb{1}] as well. this is done because the a ddress reflected by slbr n [slb{0}] is has 16-bit protection. note that in th is case the write enable slbr n [we{0}] must be set while slbr n [we{1}] does not matter. as the enable bits slbr n [we{3:2}] are cleared the lock bits slbr n [slb{3:2}] remain unchanged. in the example on the left side of figure 40-7 the data written to slbr n [slb{0}] is mirrored to slbr n [slb{1}] and the data written to slbr n [slb{2}] is mirrored to slbr n [slb{3}] as for both registers the write enables are set. figure 40-8 shows a register with 32-bit protection. when slbr n [we{0}] is set the data written to slbr n [slb{0}] is automatically written to slbr n [slb{3:1}] also. otherwise slbr n [slb{3:0}] remains unchanged. 1 slb3 slb2 slb1 slb0 slbr n [we{3:0}] slbr n [slb{3:0}] slb3 slb2 slb1 slb0 slbr n [slb{3:0}] change allowed to slb3 write data to slb2 to slb1 to slb0 1 1 1 1slbr n [we{3:0}] to slb3 write data to slb2 to slb1 to slb0 1 1 0 change allowed slb0 slb1 slb2 slb3 slbr update lock bits 1slbr n [we{3:0}] to slb0 write data to slb1 to slb2 to slb3 x1x slb0 slb1 slb2 slb3 slbr update lock bits 1slbr n [we{3:0}] to slb0 write data to slb1 to slb2 to slb3 x00
register protection (reg_prot) 40-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 40-8. change lock settings for 32-bit protected addresses figure 40-9 shows an example of mixed protection size configuration. figure 40-9. change lock se ttings for mixed protection the data written to slbr n [slb{0}] is mirrored to slbr n [slb{1}] as the corresponding register is 16-bit protected. the data written to slbr n [slb{2}] is blocked as th e corresponding register is unprotected. the data written to slbr n [slb{3}] is written to slbr n [slb{3}]. 40.4.2.2 enable lock ing via mirror m odule space (area #3) it is possible to enable locking fo r a register after writing to it. to do so, you must use the mirrored module address space. figure 40-10 shows one example. figure 40-10. enable locking via mirror module space (area #3) when writing to address 0x0008 the registers mr9 and mr8 in the protected module are updated. the corresponding lock bits rema in unchanged (left part of figure 40-7 ). 1 slb0 slb1 slb2 slb3 slbr n [we{3:0}] slbr[slb{3:0}] update lock bits to slb0 write data to slb1 to slb2 to slb3 xxx slb0 slb1 0 slb3 slbr update lock bits 1slbr n .we[3:0] to slb0 write data to slb1 to slb2 to slb3 xx1 slbr 2 we{3:0} 00000000 slb{3:0} 16-bit write to address 0x0008 no change write to mr{9:8} slbr 2 we{3:0} 00001100 slb{3:0} 16-bit write to address 0x2008 set lock bits write to mr{9:8}
register protection (reg_prot) freescale semiconductor 40-9 pxs20 microcontroller reference manual, rev. 1 when writing to address 0x2008 the registers mr9 and mr8 in the protected module are updated. the corresponding lock bits slbr2[slb {1:0}] are set while the lock bits slbr2[slb{3:2}] remain unchanged (right part of figure 40-7 ). figure 40-11 shows an example where some addres ses are protected and some are not: figure 40-11. enable locking for protected and unprotected addresses in the example in figure 40-11 addresses 0x0c and 0x0d are unprot ected. therefore their corresponding lock bits slbr3[slb{1:0}] are always 0b0 (shown in bold). when doing a 32-bit write access to address 0x200c only lock bits slbr3[slb{3:2}] are set while bits slbr3[slb{1:0}] stay cleared. note lock bits can only be set via writes to the mirror module space. reads from the mirror module space will not change the lock bits. 40.4.2.3 write protection for locking bits changing the locking bits through any of the procedures mentioned in section 40.4.2.1, change lock settings directly via area #4, and section 40.4.2.2, enable locking via mirror module space (area #3), is only possible as long as the bi t gcr[hlb] is cleared. once this bit is set the lock ing bits can no longer be modified until there was a system reset. 40.4.3 access errors the protection module generates tran sfer errors under several circumst ances. for the area definition refer to figure 40-2 1. if accessing area #1 or area #3, the protection m odule will pass on any access error from the underlying protected module. 2. if user mode is not allowed, user writes to all ar eas will assert a transfer error and the writes will be blocked. 3. if accessing the reserved area #2, a transfer error will be asserted. 4. if accessing unimplemented 32-bit registers in area #4 and area #5 a tr ansfer error will be asserted. 5. if writing to a register in area #1 and area #3 with soft lock bit set for any of the affected bytes a transfer error is asserted and the write will be blocked. also the comp lete write operation to non-protected bytes in th is word is ignored. 6. if writing to a soft lock register in area #4 with the hard lock bit being set a transfer error is asserted. 7. any write operation in any access mode to area #3 while hard lock bit gcr.hlb is set slbr 3 we{3:0} 0000 00 00 slb{3:0} before write access slbr 3 we{3:0} 0000 00 11 slb{3:0} 32-bit write to address 0x200c set lock bits write to mr{15:12} after write access
register protection (reg_prot) 40-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 40.5 initialization/application information 40.5.1 reset the reset state of each individua l bit is shown within the regi ster description section (see section 40.3.2, register descriptions ). in summary, after re set, locking for all mr n registers is disabl ed. the registers can be accessed in supervisor mode only. 40.5.2 writing c code using th e register protection scheme there is a set of macros pr ovided as part of the devi ce specific header file, wh ich defines the memory map, the peripheral registers, and the fiel ds of these registers. these macros are intended to make working with the register protection scheme easier for the developers of device driver software and/or other application code. this section describes thes e macros and how to use them. a first macro is made available to perform a write to the mirrored module register space (area 3). as described in this document, this results in concur rently setting the correspondi ng soft lock bit, while writing to the module register. there are three flavors of this macro, to account for the different size of the related module register (the value of is either 8, 16, or 32 bit): write_with_lock(, ) this macro writes the value into the register assuming a register size of . the parameter must be the name of a register using the notation in the device specific header file. a second set of macros is made ava ilable to work with the soft lock bi ts provided by the register protection scheme. the value of these bits associated with a pa rticular module register can be retrieved, set, and cleared. the macros provided for this purpose are: get_softlock(,) set_softlock() clr_softlock() the macro get_softlock retrieves the value of the so ft lock bit register associated with the given register and stores it in the variable ; which is always an eight bit value. the other two macros (set_softlock, clr_softlock ) set or clear the softlock bi ts associated with the given register ; assuming this register has a size of 8, 16, or 32 bit as i ndicated by the macro name. for all three macros, the parameter must be the name of a register using the notation in the device specific header file. three more macros are made availabl e to modify bits in the global c onfiguration register (gcr) of the protection gasket for the corresponding block. in contrast to the earlier ones, these macros receive the base address of the corresponding block (usually name d _baseaddress) as a parameter. set_hardlock(base) sets the hard lock bit hl b in the gcr register asso ciated with the module iden tified by the given base address . user_access_forbidden(base)
register protection (reg_prot) freescale semiconductor 40-11 pxs20 microcontroller reference manual, rev. 1 clears the user access allowed bit uaa in the gcr register associated with the module identified by the given base address . when cleared, this bit denies any write access to the protected module in user mode and generates a transf er error in case of an attempt to write a protected register. user_access_allowed(base) sets the user access allowed bit u aa in the gcr register associated with the module identified by the given base address . when set, this bit permits write accesse s to the protected m odule in user mode when the corresponding register are not additionally protecte d by other means. finally, two more macros are provided to permit dire ct access to the registers in the register protection gasket using the same semantic as other register definitions in the device specific header file: lock_slb(thereg) provides the content of the soft lock bit register a ssociated with the register ; the parameter must be the name of the corresponding module regi ster using the notation in the device specific header file. lock_gcr(base) provides the content of the global c onfiguration register g cr for the block identified by its base address ; the parameter must be th e base address of the corresponding block. 40.6 pxs20 registers under protection table 40-5. pxs20 register protection module register size offset protect size adc_0 mcr 32 0x0 32-bit adc_0 imr 32 0x20 32-bit adc_0 cimr0 32 0x24 32-bit adc_0 wtimr 32 0x34 32-bit adc_0 edmae 32 0x40 32-bit adc_0 edmar0 32 0x44 32-bit adc_0 thrhlr0 32 0x60 32-bit adc_0 thrhlr1 32 0x64 32-bit adc_0 thrhlr2 32 0x68 32-bit adc_0 thrhlr3 32 0x6c 32-bit adc_0 pscr 32 0x80 32-bit adc_0 psr0 32 0x84 32-bit adc_0 ctr0 32 0x94 32-bit adc_0 ncmr0 32 0xa4 32-bit adc_0 jcmr0 32 0xb4 32-bit adc_0 pdedr 32 0xc8 32-bit adc_0 thrhlr4 32 0x280 32-bit
register protection (reg_prot) 40-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 adc_0 thrhlr5 32 0x284 32-bit adc_0 thrhlr6 32 0x288 32-bit adc_0 thrhlr7 32 0x28c 32-bit adc_0 thrhlr8 32 0x290 32-bit adc_0 thrhlr9 32 0x294 32-bit adc_0 thrhlr10 32 0x298 32-bit adc_0 thrhlr11 32 0x29c 32-bit adc_0 thrhlr12 32 0x2a0 32-bit adc_0 thrhlr13 32 0x2a4 32-bit adc_0 thrhlr14 32 0x2a8 32-bit adc_0 thrhlr15 32 0x2ac 32-bit adc_0 cwselr0 32 0x2b0 32-bit adc_0 cwselr1 32 0x2b4 32-bit adc_0 cwenr0 32 0x2e0 32-bit adc_0 aworr0 32 0x2f0 32-bit adc_0 stcr1 32 0x340 32-bit adc_0 stcr2 32 0x344 32-bit adc_0 stcr3 32 0x348 32-bit adc_0 stbrr 32 0x34c 32-bit adc_0 staw0r 32 0x380 32-bit adc_0 staw1ar 32 0x384 32-bit adc_0 staw1br 32 0x388 32-bit adc_0 staw2r 32 0x38c 32-bit adc_0 staw3r 32 0x390 32-bit adc_0 staw4r 32 0x394 32-bit adc_1 mcr 32 0x0 32-bit adc_1 imr 32 0x20 32-bit adc_1 cimr0 32 0x24 32-bit adc_1 wtimr 32 0x34 32-bit adc_1 edmae 32 0x40 32-bit adc_1 edmar0 32 0x44 32-bit adc_1 thrhlr0 32 0x60 32-bit adc_1 thrhlr1 32 0x64 32-bit adc_1 thrhlr2 32 0x68 32-bit adc_1 thrhlr3 32 0x6c 32-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) freescale semiconductor 40-13 pxs20 microcontroller reference manual, rev. 1 adc_1 pscr 32 0x80 32-bit adc_1 psr0 32 0x84 32-bit adc_1 ctr0 32 0x94 32-bit adc_1 ncmr0 32 0xa4 32-bit adc_1 jcmr0 32 0xb4 32-bit adc_1 pdedr 32 0xc8 32-bit adc_1 thrhlr4 32 0x280 32-bit adc_1 thrhlr5 32 0x284 32-bit adc_1 thrhlr6 32 0x288 32-bit adc_1 thrhlr7 32 0x28c 32-bit adc_1 thrhlr8 32 0x290 32-bit adc_1 thrhlr9 32 0x294 32-bit adc_1 thrhlr10 32 0x298 32-bit adc_1 thrhlr11 32 0x29c 32-bit adc_1 thrhlr12 32 0x2a0 32-bit adc_1 thrhlr13 32 0x2a4 32-bit adc_1 thrhlr14 32 0x2a8 32-bit adc_1 thrhlr15 32 0x2ac 32-bit adc_1 cwselr0 32 0x2b0 32-bit adc_1 cwselr1 32 0x2b4 32-bit adc_1 cwenr0 32 0x2e0 32-bit adc_1 aworr0 32 0x2f0 32-bit adc_1 stcr1 32 0x340 32-bit adc_1 stcr2 32 0x344 32-bit adc_1 stcr3 32 0x348 32-bit adc_1 stbrr 32 0x34c 32-bit adc_1 staw0r 32 0x380 32-bit adc_1 staw1ar 32 0x384 32-bit adc_1 staw1br 32 0x388 32-bit adc_1 staw2r 32 0x38c 32-bit adc_1 staw3r 32 0x390 32-bit adc_1 staw4r 32 0x394 32-bit cmu_0 csr 32 0x0 32-bit cmu_0 hfrefr_a 32 0x8 32-bit cmu_0 lfrefr_a 32 0xc 32-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) 40-14 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 cmu_0 mdr 32 0x18 32-bit cmu_1 csr 32 0x0 32-bit cmu_1 hfrefr_a 32 0x8 32-bit cmu_1 lfrefr_a 32 0xc 32-bit cmu_1 mdr 32 0x18 32-bit cmu_2 csr 32 0x0 32-bit cmu_2 hfrefr_a 32 0x8 32-bit cmu_2 lfrefr_a 32 0xc 32-bit cmu_2 mdr 32 0x18 32-bit crc cfg0 32 0x0 32-bit crc cfg1 32 0x10 32-bit crc cfg2 32 0x20 32-bit ctu tgsisr 32 0x0 32-bit ctu tgscr 16 0x4 16-bit ctu t0cr 16 0x6 16-bit ctu t1cr 16 0x8 16-bit ctu t2cr 16 0x000a 16-bit ctu t3cr 16 0x000c 16-bit ctu t4cr 16 0x000e 16-bit ctu t5cr 16 0x10 16-bit ctu t6cr 16 0x12 16-bit ctu t7cr 16 0x14 16-bit ctu tgsccr 16 0x16 16-bit ctu tgscrr 16 0x18 16-bit ctu clcr1 32 0x001c 32-bit ctu clcr2 32 0x20 32-bit ctu thcr1 32 0x24 32-bit ctu thcr2 32 0x28 32-bit ctu clr1 16 0x002c 16-bit ctu clr2 16 0x002e 16-bit ctu clr3 16 0x30 16-bit ctu clr4 16 0x32 16-bit ctu clr5 16 0x34 16-bit ctu clr6 16 0x36 16-bit ctu clr7 16 0x38 16-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) freescale semiconductor 40-15 pxs20 microcontroller reference manual, rev. 1 ctu clr8 16 0x003a 16-bit ctu clr9 16 0x003c 16-bit ctu clr10 16 0x003e 16-bit ctu clr11 16 0x40 16-bit ctu clr12 16 0x42 16-bit ctu clr13 16 0x44 16-bit ctu clr14 16 0x46 16-bit ctu clr15 16 0x48 16-bit ctu clr16 16 0x004a 16-bit ctu clr17 16 0x004c 16-bit ctu clr18 16 0x004e 16-bit ctu clr19 16 0x50 16-bit ctu clr20 16 0x52 16-bit ctu clr21 16 0x54 16-bit ctu clr22 16 0x56 16-bit ctu clr23 16 0x58 16-bit ctu clr24 16 0x005a 16-bit ctu cr 16 0x006c 16-bit ctu fcr 32 0x70 32-bit ctu th1 32 0x74 32-bit ctu ctuir 16 0x00c4 16-bit ctu cotr 16 0x00c6 16-bit ctu ctucr 16 0x00c8 16-bit ctu filter 16 0xca 16-bit ctu expected_a 16 0xcc 16-bit ctu expected_b 16 0xce 16-bit ctu cnt_range 16 0xd0 16-bit codeflash mcr 32 0x0 32-bit codeflash lml 32 0x4 32-bit codeflash hbl 32 0x8 32-bit codeflash sll 32 0xc 32-bit codeflash biu0 32 0x1c 32-bit codeflash biu1 32 0x20 32-bit codeflash biu2 32 0x24 32-bit codeflash ut0 32 0x3c 32-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) 40-16 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 codeflash ut1 32 0x40 32-bit codeflash ut2 32 0x44 32-bit codeflash um0 32 0x48 32-bit codeflash um1 32 0x4c 32-bit codeflash um2 32 0x50 32-bit codeflash um3 32 0x54 32-bit codeflash um4 32 0x58 32-bit codeflash mcr 32 0x0 32-bit codeflash lml 32 0x4 32-bit codeflash hbl 32 0x8 32-bit codeflash sll 32 0xc 32-bit codeflash biu0 32 0x1c 32-bit codeflash biu1 32 0x20 32-bit codeflash biu2 32 0x24 32-bit codeflash ut0 32 0x3c 32-bit codeflash ut1 32 0x40 32-bit codeflash ut2 32 0x44 32-bit codeflash um0 32 0x48 32-bit codeflash um1 32 0x4c 32-bit codeflash um2 32 0x50 32-bit codeflash um3 32 0x54 32-bit codeflash um4 32 0x58 32-bit edma chconfig0 8 0x0 8-bit edma chconfig1 8 0x1 8-bit edma chconfig2 8 0x2 8-bit edma chconfig3 8 0x3 8-bit edma chconfig4 8 0x4 8-bit edma chconfig5 8 0x5 8-bit edma chconfig6 8 0x6 8-bit edma chconfig7 8 0x7 8-bit edma chconfig8 8 0x8 8-bit edma chconfig9 8 0x9 8-bit edma chconfig10 8 0xa 8-bit edma chconfig11 8 0xb 8-bit edma chconfig12 8 0xc 8-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) freescale semiconductor 40-17 pxs20 microcontroller reference manual, rev. 1 edma chconfig13 8 0xd 8-bit edma chconfig14 8 0xe 8-bit edma chconfig15 8 0xf 8-bit dspia mcr 32 0x0 32-bit dspia tcr 32 0x8 32-bit dspia ctar0 32 0xc 32-bit dspia ctar1 32 0x10 32-bit dspia ctar2 32 0x14 32-bit dspia ctar3 32 0x18 32-bit dspia rser 32 0x30 32-bit dspib mcr 32 0x0 32-bit dspib tcr 32 0x8 32-bit dspib ctar0 32 0xc 32-bit dspib ctar1 32 0x10 32-bit dspib ctar2 32 0x14 32-bit dspib ctar3 32 0x18 32-bit dspib rser 32 0x30 32-bit dspic mcr 32 0x0 32-bit dspic tcr 32 0x8 32-bit dspic ctar0 32 0xc 32-bit dspic ctar1 32 0x10 32-bit dspic ctar2 32 0x14 32-bit dspic ctar3 32 0x18 32-bit dspic rser 32 0x30 32-bit etimer0 comp10 16 0x0 16-bit etimer0 comp20 16 0x2 16-bit etimer0 load0 16 0x8 16-bit etimer0 ctrl10 16 0xe 16-bit etimer0 ctrl20 16 0x10 16-bit etimer0 ctrl30 16 0x12 16-bit etimer0 intedma0 16 0x16 16-bit etimer0 cmpld10 16 0x18 16-bit etimer0 cmpld20 16 0x1a 16-bit etimer0 ccctrl0 16 0x1c 16-bit etimer0 filt0 16 0x1e 16-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) 40-18 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 etimer0 comp11 16 0x20 16-bit etimer0 comp21 16 0x22 16-bit etimer0 load1 16 0x28 16-bit etimer0 ctrl11 16 0x2e 16-bit etimer0 ctrl21 16 0x30 16-bit etimer0 ctrl31 16 0x32 16-bit etimer0 intedma1 16 0x36 16-bit etimer0 cmpld11 16 0x38 16-bit etimer0 cmpld21 16 0x3a 16-bit etimer0 ccctrl1 16 0x3c 16-bit etimer0 filt1 16 0x3e 16-bit etimer0 comp12 16 0x40 16-bit etimer0 comp22 16 0x42 16-bit etimer0 load2 16 0x48 16-bit etimer0 ctrl12 16 0x4e 16-bit etimer0 ctrl22 16 0x50 16-bit etimer0 ctrl32 16 0x52 16-bit etimer0 intedma2 16 0x56 16-bit etimer0 cmpld12 16 0x58 16-bit etimer0 cmpld22 16 0x5a 16-bit etimer0 ccctrl2 16 0x5c 16-bit etimer0 filt2 16 0x5e 16-bit etimer0 comp13 16 0x60 16-bit etimer0 comp23 16 0x62 16-bit etimer0 load3 16 0x68 16-bit etimer0 ctrl13 16 0x6e 16-bit etimer0 ctrl23 16 0x70 16-bit etimer0 ctrl33 16 0x72 16-bit etimer0 intedma3 16 0x76 16-bit etimer0 cmpld13 16 0x78 16-bit etimer0 cmpld23 16 0x7a 16-bit etimer0 ccctrl3 16 0x7c 16-bit etimer0 filt3 16 0x7e 16-bit etimer0 comp14 16 0x80 16-bit etimer0 comp24 16 0x82 16-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) freescale semiconductor 40-19 pxs20 microcontroller reference manual, rev. 1 etimer0 load4 16 0x88 16-bit etimer0 ctrl14 16 0x8e 16-bit etimer0 ctrl24 16 0x90 16-bit etimer0 ctrl34 16 0x92 16-bit etimer0 intedma4 16 0x96 16-bit etimer0 cmpld14 16 0x98 16-bit etimer0 cmpld24 16 0x9a 16-bit etimer0 ccctrl4 16 0x9c 16-bit etimer0 filt4 16 0x9e 16-bit etimer0 comp15 16 0xa0 16-bit etimer0 comp25 16 0xa2 16-bit etimer0 load5 16 0xa8 16-bit etimer0 ctrl15 16 0xae 16-bit etimer0 ctrl25 16 0xb0 16-bit etimer0 ctrl35 16 0xb2 16-bit etimer0 intedma5 16 0xb6 16-bit etimer0 cmpld15 16 0xb8 16-bit etimer0 cmpld25 16 0xba 16-bit etimer0 ccctrl5 16 0xbc 16-bit etimer0 filt5 16 0xbe 16-bit etimer0 wdtol 16 0x100 16-bit etimer0 wdtoh 16 0x102 16-bit etimer0 enbl 16 0x10c 16-bit etimer0 dreq0 16 0x110 16-bit etimer0 dreq1 16 0x112 16-bit etimer1 comp10 16 0x0 16-bit etimer1 comp20 16 0x2 16-bit etimer1 load0 16 0x8 16-bit etimer1 ctrl10 16 0xe 16-bit etimer1 ctrl20 16 0x10 16-bit etimer1 ctrl30 16 0x12 16-bit etimer1 intedma0 16 0x16 16-bit etimer1 cmpld10 16 0x18 16-bit etimer1 cmpld20 16 0x1a 16-bit etimer1 ccctrl0 16 0x1c 16-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) 40-20 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 etimer1 filt0 16 0x1e 16-bit etimer1 comp11 16 0x20 16-bit etimer1 comp21 16 0x22 16-bit etimer1 load1 16 0x28 16-bit etimer1 ctrl11 16 0x2e 16-bit etimer1 ctrl21 16 0x30 16-bit etimer1 ctrl31 16 0x32 16-bit etimer1 intedma1 16 0x36 16-bit etimer1 cmpld11 16 0x38 16-bit etimer1 cmpld21 16 0x3a 16-bit etimer1 ccctrl1 16 0x3c 16-bit etimer1 filt1 16 0x3e 16-bit etimer1 comp12 16 0x40 16-bit etimer1 comp22 16 0x42 16-bit etimer1 load2 16 0x48 16-bit etimer1 ctrl12 16 0x4e 16-bit etimer1 ctrl22 16 0x50 16-bit etimer1 ctrl32 16 0x52 16-bit etimer1 intedma2 16 0x56 16-bit etimer1 cmpld12 16 0x58 16-bit etimer1 cmpld22 16 0x5a 16-bit etimer1 ccctrl2 16 0x5c 16-bit etimer1 filt2 16 0x5e 16-bit etimer1 comp13 16 0x60 16-bit etimer1 comp23 16 0x62 16-bit etimer1 load3 16 0x68 16-bit etimer1 ctrl13 16 0x6e 16-bit etimer1 ctrl23 16 0x70 16-bit etimer1 ctrl33 16 0x72 16-bit etimer1 intedma3 16 0x76 16-bit etimer1 cmpld13 16 0x78 16-bit etimer1 cmpld23 16 0x7a 16-bit etimer1 ccctrl3 16 0x7c 16-bit etimer1 filt3 16 0x7e 16-bit etimer1 comp14 16 0x80 16-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) freescale semiconductor 40-21 pxs20 microcontroller reference manual, rev. 1 etimer1 comp24 16 0x82 16-bit etimer1 load4 16 0x88 16-bit etimer1 ctrl14 16 0x8e 16-bit etimer1 ctrl24 16 0x90 16-bit etimer1 ctrl34 16 0x92 16-bit etimer1 intedma4 16 0x96 16-bit etimer1 cmpld14 16 0x98 16-bit etimer1 cmpld24 16 0x9a 16-bit etimer1 ccctrl4 16 0x9c 16-bit etimer1 filt4 16 0x9e 16-bit etimer1 comp15 16 0xa0 16-bit etimer1 comp25 16 0xa2 16-bit etimer1 load5 16 0xa8 16-bit etimer1 ctrl15 16 0xae 16-bit etimer1 ctrl25 16 0xb0 16-bit etimer1 ctrl35 16 0xb2 16-bit etimer1 intedma5 16 0xb6 16-bit etimer1 cmpld15 16 0xb8 16-bit etimer1 cmpld25 16 0xba 16-bit etimer1 ccctrl5 16 0xbc 16-bit etimer1 filt5 16 0xbe 16-bit etimer1 enbl 16 0x10c 16-bit etimer1 dreq0 16 0x110 16-bit etimer1 dreq1 16 0x112 16-bit etimer2 comp10 16 0x0 16-bit etimer2 comp20 16 0x2 16-bit etimer2 load0 16 0x8 16-bit etimer2 ctrl10 16 0xe 16-bit etimer2 ctrl20 16 0x10 16-bit etimer2 ctrl30 16 0x12 16-bit etimer2 intedma0 16 0x16 16-bit etimer2 cmpld10 16 0x18 16-bit etimer2 cmpld20 16 0x1a 16-bit etimer2 ccctrl0 16 0x1c 16-bit etimer2 filt0 16 0x1e 16-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) 40-22 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 etimer2 comp11 16 0x20 16-bit etimer2 comp21 16 0x22 16-bit etimer2 load1 16 0x28 16-bit etimer2 ctrl11 16 0x2e 16-bit etimer2 ctrl21 16 0x30 16-bit etimer2 ctrl31 16 0x32 16-bit etimer2 intedma1 16 0x36 16-bit etimer2 cmpld11 16 0x38 16-bit etimer2 cmpld21 16 0x3a 16-bit etimer2 ccctrl1 16 0x3c 16-bit etimer2 filt1 16 0x3e 16-bit etimer2 comp12 16 0x40 16-bit etimer2 comp22 16 0x42 16-bit etimer2 load2 16 0x48 16-bit etimer2 ctrl12 16 0x4e 16-bit etimer2 ctrl22 16 0x50 16-bit etimer2 ctrl32 16 0x52 16-bit etimer2 intedma2 16 0x56 16-bit etimer2 cmpld12 16 0x58 16-bit etimer2 cmpld22 16 0x5a 16-bit etimer2 ccctrl2 16 0x5c 16-bit etimer2 filt2 16 0x5e 16-bit etimer2 comp13 16 0x60 16-bit etimer2 comp23 16 0x62 16-bit etimer2 load3 16 0x68 16-bit etimer2 ctrl13 16 0x6e 16-bit etimer2 ctrl23 16 0x70 16-bit etimer2 ctrl33 16 0x72 16-bit etimer2 intedma3 16 0x76 16-bit etimer2 cmpld13 16 0x78 16-bit etimer2 cmpld23 16 0x7a 16-bit etimer2 ccctrl3 16 0x7c 16-bit etimer2 filt3 16 0x7e 16-bit etimer2 comp14 16 0x80 16-bit etimer2 comp24 16 0x82 16-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) freescale semiconductor 40-23 pxs20 microcontroller reference manual, rev. 1 etimer2 load4 16 0x88 16-bit etimer2 ctrl14 16 0x8e 16-bit etimer2 ctrl24 16 0x90 16-bit etimer2 ctrl34 16 0x92 16-bit etimer2 intedma4 16 0x96 16-bit etimer2 cmpld14 16 0x98 16-bit etimer2 cmpld24 16 0x9a 16-bit etimer2 ccctrl4 16 0x9c 16-bit etimer2 filt4 16 0x9e 16-bit etimer2 comp15 16 0xa0 16-bit etimer2 comp25 16 0xa2 16-bit etimer2 load5 16 0xa8 16-bit etimer2 ctrl15 16 0xae 16-bit etimer2 ctrl25 16 0xb0 16-bit etimer2 ctrl35 16 0xb2 16-bit etimer2 intedma5 16 0xb6 16-bit etimer2 cmpld15 16 0xb8 16-bit etimer2 cmpld25 16 0xba 16-bit etimer2 ccctrl5 16 0xbc 16-bit etimer2 filt5 16 0xbe 16-bit etimer2 enbl 16 0x10c 16-bit etimer2 dreq0 16 0x110 16-bit etimer2 dreq1 16 0x112 16-bit fccu cfg 32 0x8 32-bit fccu cf_cfg0 32 0xc 32-bit fccu ncf_cfg0 32 0x1c 32-bit fccu cfs_cfg0 32 0x2c 32-bit fccu cfs_cfg1 32 0x30 32-bit fccu ncfs_cfg0 32 0x4c 32-bit fccu ncfs_cfg1 32 0x50 32-bit fccu ncfe0 32 0x94 32-bit fccu ncf_toe0 32 0xa4 32-bit fccu ncf_to 32 0xb4 32-bit fccu cfg_to 32 0xb8 32-bit fccu cff 32 0xd8 32-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) 40-24 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 fccu ncff 32 0xdc 32-bit fccu irq_en 32 0xe4 32-bit flexcan_a mcr 32 0x0000 32-bit flexcan_a ctrl 32 0x0004 32-bit flexcan_a rxgmask 32 0x0010 32-bit flexcan_a rx14mask 32 0x0014 32-bit flexcan_a rx15mask 32 0x0018 32-bit flexcan_a imask1 32 0x0028 32-bit flexcan_a msg0_cs 32 0x80 32-bit flexcan_a msg0_id 32 0x84 32-bit flexcan_a msg1_cs 32 0x90 32-bit flexcan_a msg1_id 32 0x94 32-bit flexcan_a msg2_cs 32 0xa0 32-bit flexcan_a msg2_id 32 0xa4 32-bit flexcan_a msg3_cs 32 0xb0 32-bit flexcan_a msg3_id 32 0xb4 32-bit flexcan_a msg4_cs 32 0xc0 32-bit flexcan_a msg4_id 32 0xc4 32-bit flexcan_a msg5_cs 32 0xd0 32-bit flexcan_a msg5_id 32 0xd4 32-bit flexcan_a msg6_cs 32 0xe0 32-bit flexcan_a msg6_id 32 0xe4 32-bit flexcan_a msg7_cs 32 0xf0 32-bit flexcan_a msg7_id 32 0xf4 32-bit flexcan_a msg8_cs 32 0x100 32-bit flexcan_a msg8_id 32 0x104 32-bit flexcan_a msg9_cs 32 0x110 32-bit flexcan_a msg9_id 32 0x114 32-bit flexcan_a msg10_cs 32 0x120 32-bit flexcan_a msg10_id 32 0x124 32-bit flexcan_a msg11_cs 32 0x130 32-bit flexcan_a msg11_id 32 0x134 32-bit flexcan_a msg12_cs 32 0x140 32-bit flexcan_a msg12_id 32 0x144 32-bit flexcan_a msg13_cs 32 0x150 32-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) freescale semiconductor 40-25 pxs20 microcontroller reference manual, rev. 1 flexcan_a msg13_id 32 0x154 32-bit flexcan_a msg14_cs 32 0x160 32-bit flexcan_a msg14_id 32 0x164 32-bit flexcan_a msg15_cs 32 0x170 32-bit flexcan_a msg15_id 32 0x174 32-bit flexcan_a msg16_cs 32 0x180 32-bit flexcan_a msg16_id 32 0x184 32-bit flexcan_a msg17_cs 32 0x190 32-bit flexcan_a msg17_id 32 0x194 32-bit flexcan_a msg18_cs 32 0x1a0 32-bit flexcan_a msg18_id 32 0x1a4 32-bit flexcan_a msg19_cs 32 0x1b0 32-bit flexcan_a msg19_id 32 0x1b4 32-bit flexcan_a msg20_cs 32 0x1c0 32-bit flexcan_a msg20_id 32 0x1c4 32-bit flexcan_a msg21_cs 32 0x1d0 32-bit flexcan_a msg21_id 32 0x1d4 32-bit flexcan_a msg22_cs 32 0x1e0 32-bit flexcan_a msg22_id 32 0x1e4 32-bit flexcan_a msg23_cs 32 0x1f0 32-bit flexcan_a msg23_id 32 0x1f4 32-bit flexcan_a msg24_cs 32 0x200 32-bit flexcan_a msg24_id 32 0x204 32-bit flexcan_a msg25_cs 32 0x210 32-bit flexcan_a msg25_id 32 0x214 32-bit flexcan_a msg26_cs 32 0x220 32-bit flexcan_a msg26_id 32 0x224 32-bit flexcan_a msg27_cs 32 0x230 32-bit flexcan_a msg27_id 32 0x234 32-bit flexcan_a msg28_cs 32 0x240 32-bit flexcan_a msg28_id 32 0x244 32-bit flexcan_a msg29_cs 32 0x250 32-bit flexcan_a msg29_id 32 0x254 32-bit flexcan_a msg30_cs 32 0x260 32-bit flexcan_a msg30_id 32 0x264 32-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) 40-26 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 flexcan_a msg31_cs 32 0x270 32-bit flexcan_a msg31_id 32 0x274 32-bit flexcan_a rximr0 32 0x0880 32-bit flexcan_a rximr1 32 0x0884 32-bit flexcan_a rximr2 32 0x0888 32-bit flexcan_a rximr3 32 0x088c 32-bit flexcan_a rximr4 32 0x0890 32-bit flexcan_a rximr5 32 0x0894 32-bit flexcan_a rximr6 32 0x0898 32-bit flexcan_a rximr7 32 0x089c 32-bit flexcan_a rximr8 32 0x08a0 32-bit flexcan_a rximr9 32 0x08a4 32-bit flexcan_a rximr10 32 0x08a8 32-bit flexcan_a rximr11 32 0x08ac 32-bit flexcan_a rximr12 32 0x08b0 32-bit flexcan_a rximr13 32 0x08b4 32-bit flexcan_a rximr14 32 0x08b8 32-bit flexcan_a rximr15 32 0x08bc 32-bit flexcan_a rximr16 32 0x08c0 32-bit flexcan_a rximr17 32 0x08c4 32-bit flexcan_a rximr18 32 0x08c8 32-bit flexcan_a rximr19 32 0x08cc 32-bit flexcan_a rximr20 32 0x08d0 32-bit flexcan_a rximr21 32 0x08d4 32-bit flexcan_a rximr22 32 0x08d8 32-bit flexcan_a rximr23 32 0x08dc 32-bit flexcan_a rximr24 32 0x08e0 32-bit flexcan_a rximr25 32 0x08e4 32-bit flexcan_a rximr26 32 0x08e8 32-bit flexcan_a rximr27 32 0x08ec 32-bit flexcan_a rximr28 32 0x08f0 32-bit flexcan_a rximr29 32 0x08f4 32-bit flexcan_a rximr30 32 0x08f8 32-bit flexcan_a rximr31 32 0x08fc 32-bit flexcan_b mcr 32 0x0000 32-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) freescale semiconductor 40-27 pxs20 microcontroller reference manual, rev. 1 flexcan_b ctrl 32 0x0004 32-bit flexcan_b rxgmask 32 0x0010 32-bit flexcan_b rx14mask 32 0x0014 32-bit flexcan_b rx15mask 32 0x0018 32-bit flexcan_b imask1 32 0x0028 32-bit flexcan_b msg0_cs 32 0x80 32-bit flexcan_b msg0_id 32 0x84 32-bit flexcan_b msg1_cs 32 0x90 32-bit flexcan_b msg1_id 32 0x94 32-bit flexcan_b msg2_cs 32 0xa0 32-bit flexcan_b msg2_id 32 0xa4 32-bit flexcan_b msg3_cs 32 0xb0 32-bit flexcan_b msg3_id 32 0xb4 32-bit flexcan_b msg4_cs 32 0xc0 32-bit flexcan_b msg4_id 32 0xc4 32-bit flexcan_b msg5_cs 32 0xd0 32-bit flexcan_b msg5_id 32 0xd4 32-bit flexcan_b msg6_cs 32 0xe0 32-bit flexcan_b msg6_id 32 0xe4 32-bit flexcan_b msg7_cs 32 0xf0 32-bit flexcan_b msg7_id 32 0xf4 32-bit flexcan_b msg8_cs 32 0x100 32-bit flexcan_b msg8_id 32 0x104 32-bit flexcan_b msg9_cs 32 0x110 32-bit flexcan_b msg9_id 32 0x114 32-bit flexcan_b msg10_cs 32 0x120 32-bit flexcan_b msg10_id 32 0x124 32-bit flexcan_b msg11_cs 32 0x130 32-bit flexcan_b msg11_id 32 0x134 32-bit flexcan_b msg12_cs 32 0x140 32-bit flexcan_b msg12_id 32 0x144 32-bit flexcan_b msg13_cs 32 0x150 32-bit flexcan_b msg13_id 32 0x154 32-bit flexcan_b msg14_cs 32 0x160 32-bit flexcan_b msg14_id 32 0x164 32-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) 40-28 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 flexcan_b msg15_cs 32 0x170 32-bit flexcan_b msg15_id 32 0x174 32-bit flexcan_b msg16_cs 32 0x180 32-bit flexcan_b msg16_id 32 0x184 32-bit flexcan_b msg17_cs 32 0x190 32-bit flexcan_b msg17_id 32 0x194 32-bit flexcan_b msg18_cs 32 0x1a0 32-bit flexcan_b msg18_id 32 0x1a4 32-bit flexcan_b msg19_cs 32 0x1b0 32-bit flexcan_b msg19_id 32 0x1b4 32-bit flexcan_b msg20_cs 32 0x1c0 32-bit flexcan_b msg20_id 32 0x1c4 32-bit flexcan_b msg21_cs 32 0x1d0 32-bit flexcan_b msg21_id 32 0x1d4 32-bit flexcan_b msg22_cs 32 0x1e0 32-bit flexcan_b msg22_id 32 0x1e4 32-bit flexcan_b msg23_cs 32 0x1f0 32-bit flexcan_b msg23_id 32 0x1f4 32-bit flexcan_b msg24_cs 32 0x200 32-bit flexcan_b msg24_id 32 0x204 32-bit flexcan_b msg25_cs 32 0x210 32-bit flexcan_b msg25_id 32 0x214 32-bit flexcan_b msg26_cs 32 0x220 32-bit flexcan_b msg26_id 32 0x224 32-bit flexcan_b msg27_cs 32 0x230 32-bit flexcan_b msg27_id 32 0x234 32-bit flexcan_b msg28_cs 32 0x240 32-bit flexcan_b msg28_id 32 0x244 32-bit flexcan_b msg29_cs 32 0x250 32-bit flexcan_b msg29_id 32 0x254 32-bit flexcan_b msg30_cs 32 0x260 32-bit flexcan_b msg30_id 32 0x264 32-bit flexcan_b msg31_cs 32 0x270 32-bit flexcan_b msg31_id 32 0x274 32-bit flexcan_b rximr0 32 0x0880 32-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) freescale semiconductor 40-29 pxs20 microcontroller reference manual, rev. 1 flexcan_b rximr1 32 0x0884 32-bit flexcan_b rximr2 32 0x0888 32-bit flexcan_b rximr3 32 0x088c 32-bit flexcan_b rximr4 32 0x0890 32-bit flexcan_b rximr5 32 0x0894 32-bit flexcan_b rximr6 32 0x0898 32-bit flexcan_b rximr7 32 0x089c 32-bit flexcan_b rximr8 32 0x08a0 32-bit flexcan_b rximr9 32 0x08a4 32-bit flexcan_b rximr10 32 0x08a8 32-bit flexcan_b rximr11 32 0x08ac 32-bit flexcan_b rximr12 32 0x08b0 32-bit flexcan_b rximr13 32 0x08b4 32-bit flexcan_b rximr14 32 0x08b8 32-bit flexcan_b rximr15 32 0x08bc 32-bit flexcan_b rximr16 32 0x08c0 32-bit flexcan_b rximr17 32 0x08c4 32-bit flexcan_b rximr18 32 0x08c8 32-bit flexcan_b rximr19 32 0x08cc 32-bit flexcan_b rximr20 32 0x08d0 32-bit flexcan_b rximr21 32 0x08d4 32-bit flexcan_b rximr22 32 0x08d8 32-bit flexcan_b rximr23 32 0x08dc 32-bit flexcan_b rximr24 32 0x08e0 32-bit flexcan_b rximr25 32 0x08e4 32-bit flexcan_b rximr26 32 0x08e8 32-bit flexcan_b rximr27 32 0x08ec 32-bit flexcan_b rximr28 32 0x08f0 32-bit flexcan_b rximr29 32 0x08f4 32-bit flexcan_b rximr30 32 0x08f8 32-bit flexcan_b rximr31 32 0x08fc 32-bit flexpwm0 init0 16 0x0002 16-bit flexpwm0 ctrl20 16 0x0004 16-bit flexpwm0 ctrl10 16 0x0006 16-bit flexpwm0 val_00 16 0x0008 16-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) 40-30 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 flexpwm0 val_10 16 0x000a 16-bit flexpwm0 val_20 16 0x000c 16-bit flexpwm0 val_30 16 0x000e 16-bit flexpwm0 val_40 16 0x0010 16-bit flexpwm0 val_50 16 0x0012 16-bit flexpwm0 octrl0 16 0x0018 16-bit flexpwm0 inten0 16 0x001c 16-bit flexpwm0 edmaen0 16 0x001e 16-bit flexpwm0 tctrl0 16 0x0020 16-bit flexpwm0 dismap0 16 0x0022 16-bit flexpwm0 dtcnt00 16 0x0024 16-bit flexpwm0 dtcnt10 16 0x0026 16-bit flexpwm0 captctrlx0 16 0x0030 16-bit flexpwm0 captcmpx0 16 0x0032 16-bit flexpwm0 init1 16 0x0052 16-bit flexpwm0 ctrl21 16 0x0054 16-bit flexpwm0 ctrl11 16 0x0056 16-bit flexpwm0 val_01 16 0x0058 16-bit flexpwm0 val_11 16 0x005a 16-bit flexpwm0 val_21 16 0x005c 16-bit flexpwm0 val_31 16 0x005e 16-bit flexpwm0 val_41 16 0x0060 16-bit flexpwm0 val_51 16 0x0062 16-bit flexpwm0 octrl1 16 0x0068 16-bit flexpwm0 inten1 16 0x006c 16-bit flexpwm0 edmaen1 16 0x006e 16-bit flexpwm0 tctrl1 16 0x0070 16-bit flexpwm0 dismap1 16 0x0072 16-bit flexpwm0 dtcnt01 16 0x0074 16-bit flexpwm0 dtcnt11 16 0x0076 16-bit flexpwm0 captctrlx1 16 0x0080 16-bit flexpwm0 captcmpx1 16 0x0082 16-bit flexpwm0 init2 16 0x00a2 16-bit flexpwm0 ctrl22 16 0x00a4 16-bit flexpwm0 ctrl12 16 0x00a6 16-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) freescale semiconductor 40-31 pxs20 microcontroller reference manual, rev. 1 flexpwm0 val_02 16 0x00a8 16-bit flexpwm0 val_12 16 0x00aa 16-bit flexpwm0 val_22 16 0x00ac 16-bit flexpwm0 val_32 16 0x00ae 16-bit flexpwm0 val_42 16 0x00b0 16-bit flexpwm0 val_52 16 0x00b2 16-bit flexpwm0 octrl2 16 0x00b8 16-bit flexpwm0 inten2 16 0x00bc 16-bit flexpwm0 edmaen2 16 0x00be 16-bit flexpwm0 tctrl2 16 0x00c0 16-bit flexpwm0 dismap2 16 0x00c2 16-bit flexpwm0 dtcnt02 16 0x00c4 16-bit flexpwm0 dtcnt12 16 0x00c6 16-bit flexpwm0 captctrlx2 16 0x00d0 16-bit flexpwm0 captcmpx2 16 0x00d2 16-bit flexpwm0 init3 16 0x00f2 16-bit flexpwm0 ctrl23 16 0x00f4 16-bit flexpwm0 ctrl13 16 0x00f6 16-bit flexpwm0 val_03 16 0x00f8 16-bit flexpwm0 val_13 16 0x00fa 16-bit flexpwm0 val_23 16 0x00fc 16-bit flexpwm0 val_33 16 0x00fe 16-bit flexpwm0 val_43 16 0x0100 16-bit flexpwm0 val_53 16 0x0102 16-bit flexpwm0 octrl3 16 0x108 16-bit flexpwm0 inten3 16 0x010c 16-bit flexpwm0 edmaen3 16 0x010e 16-bit flexpwm0 tctrl3 16 0x0110 16-bit flexpwm0 dismap3 16 0x0112 16-bit flexpwm0 dtcnt03 16 0x0114 16-bit flexpwm0 dtcnt13 16 0x0116 16-bit flexpwm0 captctrlx3 16 0x0120 16-bit flexpwm0 captcmpx3 16 0x0122 16-bit flexpwm0 outen 16 0x0140 16-bit flexpwm0 mask 16 0x0142 16-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) 40-32 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 flexpwm0 swcout 16 0x0144 16-bit flexpwm0 dtsrcsel 16 0x0146 16-bit flexpwm0 mctrl 16 0x0148 16-bit flexpwm0 fctrl 16 0x014c 16-bit flexpwm1 init0 16 0x0002 16-bit flexpwm1 ctrl20 16 0x0004 16-bit flexpwm1 ctrl10 16 0x0006 16-bit flexpwm1 val_00 16 0x0008 16-bit flexpwm1 val_10 16 0x000a 16-bit flexpwm1 val_20 16 0x000c 16-bit flexpwm1 val_30 16 0x000e 16-bit flexpwm1 val_40 16 0x0010 16-bit flexpwm1 val_50 16 0x0012 16-bit flexpwm1 octrl0 16 0x0018 16-bit flexpwm1 inten0 16 0x001c 16-bit flexpwm1 edmaen0 16 0x001e 16-bit flexpwm1 tctrl0 16 0x0020 16-bit flexpwm1 dismap0 16 0x0022 16-bit flexpwm1 dtcnt00 16 0x0024 16-bit flexpwm1 dtcnt10 16 0x0026 16-bit flexpwm1 captctrlx0 16 0x0030 16-bit flexpwm1 captcmpx0 16 0x0032 16-bit flexpwm1 init1 16 0x0052 16-bit flexpwm1 ctrl21 16 0x0054 16-bit flexpwm1 ctrl11 16 0x0056 16-bit flexpwm1 val_01 16 0x0058 16-bit flexpwm1 val_11 16 0x005a 16-bit flexpwm1 val_21 16 0x005c 16-bit flexpwm1 val_31 16 0x005e 16-bit flexpwm1 val_41 16 0x0060 16-bit flexpwm1 val_51 16 0x0062 16-bit flexpwm1 octrl1 16 0x0068 16-bit flexpwm1 inten1 16 0x006c 16-bit flexpwm1 edmaen1 16 0x006e 16-bit flexpwm1 tctrl1 16 0x0070 16-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) freescale semiconductor 40-33 pxs20 microcontroller reference manual, rev. 1 flexpwm1 dismap1 16 0x0072 16-bit flexpwm1 dtcnt01 16 0x0074 16-bit flexpwm1 dtcnt11 16 0x0076 16-bit flexpwm1 captctrlx1 16 0x0080 16-bit flexpwm1 captcmpx1 16 0x0082 16-bit flexpwm1 init2 16 0x00a2 16-bit flexpwm1 ctrl22 16 0x00a4 16-bit flexpwm1 ctrl12 16 0x00a6 16-bit flexpwm1 val_02 16 0x00a8 16-bit flexpwm1 val_12 16 0x00aa 16-bit flexpwm1 val_22 16 0x00ac 16-bit flexpwm1 val_32 16 0x00ae 16-bit flexpwm1 val_42 16 0x00b0 16-bit flexpwm1 val_52 16 0x00b2 16-bit flexpwm1 octrl2 16 0x00b8 16-bit flexpwm1 inten2 16 0x00bc 16-bit flexpwm1 edmaen2 16 0x00be 16-bit flexpwm1 tctrl2 16 0x00c0 16-bit flexpwm1 dismap2 16 0x00c2 16-bit flexpwm1 dtcnt02 16 0x00c4 16-bit flexpwm1 dtcnt12 16 0x00c6 16-bit flexpwm1 captctrlx2 16 0x00d0 16-bit flexpwm1 captcmpx2 16 0x00d2 16-bit flexpwm1 init3 16 0x00f2 16-bit flexpwm1 ctrl23 16 0x00f4 16-bit flexpwm1 ctrl13 16 0x00f6 16-bit flexpwm1 val_03 16 0x00f8 16-bit flexpwm1 val_13 16 0x00fa 16-bit flexpwm1 val_23 16 0x00fc 16-bit flexpwm1 val_33 16 0x00fe 16-bit flexpwm1 val_43 16 0x0100 16-bit flexpwm1 val_53 16 0x0102 16-bit flexpwm1 octrl3 16 0x108 16-bit flexpwm1 inten3 16 0x010c 16-bit flexpwm1 edmaen3 16 0x010e 16-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) 40-34 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 flexpwm1 tctrl3 16 0x0110 16-bit flexpwm1 dismap3 16 0x0112 16-bit flexpwm1 dtcnt03 16 0x0114 16-bit flexpwm1 dtcnt13 16 0x0116 16-bit flexpwm1 captctrlx3 16 0x0120 16-bit flexpwm1 captcmpx3 16 0x0122 16-bit flexpwm1 outen 16 0x0140 16-bit flexpwm1 mask 16 0x0142 16-bit flexpwm1 swcout 16 0x0144 16-bit flexpwm1 dtsrcsel 16 0x0146 16-bit flexpwm1 mctrl 16 0x0148 16-bit flexpwm1 fctrl 16 0x014c 16-bit flexray mcr 16 0x2 16-bit flexray symbadhr 16 0x4 16-bit flexray symbadlr 16 0x6 16-bit flexray stbscr 16 0x8 16-bit flexray mbdsr 16 0xc 16-bit flexray mbssutr 16 0xe 16-bit flexray pocr 16 0x14 16-bit flexray gifer 16 0x16 16-bit flexray pier0 16 0x1c 16-bit flexray pier1 16 0x1e 16-bit flexray symator 16 0x3e 16-bit flexray sftor 16 0x42 16-bit flexray sftccsr 16 0x44 16-bit flexray sfidrfr 16 0x46 16-bit flexray sfidafvr 16 0x48 16-bit flexray sfidafmr 16 0x4a 16-bit flexray nmvlr 16 0x58 16-bit flexray ticcr 16 0x5a 16-bit flexray ti1cysr 16 0x5c 16-bit flexray ti1mtor 16 0x5e 16-bit flexray ti2cr0 16 0x60 16-bit flexray ti2cr1 16 0x62 16-bit flexray mtsacfr 16 0x80 16-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) freescale semiconductor 40-35 pxs20 microcontroller reference manual, rev. 1 flexray mtsbcfr 16 0x82 16-bit flexray rfrfctr 16 0x9a 16-bit flexray pcr0 16 0xa0 16-bit flexray pcr1 16 0xa2 16-bit flexray pcr2 16 0xa4 16-bit flexray pcr3 16 0xa6 16-bit flexray pcr4 16 0xa8 16-bit flexray pcr5 16 0xaa 16-bit flexray pcr6 16 0xac 16-bit flexray pcr7 16 0xae 16-bit flexray pcr8 16 0xb0 16-bit flexray pcr9 16 0xb2 16-bit flexray pcr10 16 0xb4 16-bit flexray pcr11 16 0xb6 16-bit flexray pcr12 16 0xb8 16-bit flexray pcr13 16 0xba 16-bit flexray pcr14 16 0xbc 16-bit flexray pcr15 16 0xbe 16-bit flexray pcr16 16 0xc0 16-bit flexray pcr17 16 0xc2 16-bit flexray pcr18 16 0xc4 16-bit flexray pcr19 16 0xc6 16-bit flexray pcr20 16 0xc8 16-bit flexray pcr21 16 0xca 16-bit flexray pcr22 16 0xcc 16-bit flexray pcr23 16 0xce 16-bit flexray pcr24 16 0xd0 16-bit flexray pcr25 16 0xd2 16-bit flexray pcr26 16 0xd4 16-bit flexray pcr27 16 0xd6 16-bit flexray pcr28 16 0xd8 16-bit flexray pcr29 16 0xda 16-bit flexray pcr30 16 0xdc 16-bit flexray mbccfr0 16 0x102 16-bit flexray mbfidr0 16 0x104 16-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) 40-36 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 flexray mbccfr1 16 0x10a 16-bit flexray mbfidr1 16 0x10c 16-bit flexray mbccfr2 16 0x112 16-bit flexray mbfidr2 16 0x114 16-bit flexray mbccfr3 16 0x11a 16-bit flexray mbfidr3 16 0x11c 16-bit flexray mbccfr4 16 0x122 16-bit flexray mbfidr4 16 0x124 16-bit flexray mbccfr5 16 0x12a 16-bit flexray mbfidr5 16 0x12c 16-bit flexray mbccfr6 16 0x132 16-bit flexray mbfidr6 16 0x134 16-bit flexray mbccfr7 16 0x13a 16-bit flexray mbfidr7 16 0x13c 16-bit flexray mbccfr8 16 0x142 16-bit flexray mbfidr8 16 0x144 16-bit flexray mbccfr9 16 0x14a 16-bit flexray mbfidr9 16 0x14c 16-bit flexray mbccfr10 16 0x152 16-bit flexray mbfidr10 16 0x154 16-bit flexray mbccfr11 16 0x15a 16-bit flexray mbfidr11 16 0x15c 16-bit flexray mbccfr12 16 0x162 16-bit flexray mbfidr12 16 0x164 16-bit flexray mbccfr13 16 0x16a 16-bit flexray mbfidr13 16 0x16c 16-bit flexray mbccfr14 16 0x172 16-bit flexray mbfidr14 16 0x174 16-bit flexray mbccfr15 16 0x17a 16-bit flexray mbfidr15 16 0x17c 16-bit flexray mbccfr16 16 0x182 16-bit flexray mbfidr16 16 0x184 16-bit flexray mbccfr17 16 0x18a 16-bit flexray mbfidr17 16 0x18c 16-bit flexray mbccfr18 16 0x192 16-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) freescale semiconductor 40-37 pxs20 microcontroller reference manual, rev. 1 flexray mbfidr18 16 0x194 16-bit flexray mbccfr19 16 0x19a 16-bit flexray mbfidr19 16 0x19c 16-bit flexray mbccfr20 16 0x1a2 16-bit flexray mbfidr20 16 0x1a4 16-bit flexray mbccfr21 16 0x1aa 16-bit flexray mbfidr21 16 0x1ac 16-bit flexray mbccfr22 16 0x1b2 16-bit flexray mbfidr22 16 0x1b4 16-bit flexray mbccfr23 16 0x1ba 16-bit flexray mbfidr23 16 0x1bc 16-bit flexray mbccfr24 16 0x1c2 16-bit flexray mbfidr24 16 0x1c4 16-bit flexray mbccfr25 16 0x1ca 16-bit flexray mbfidr25 16 0x1cc 16-bit flexray mbccfr26 16 0x1d2 16-bit flexray mbfidr26 16 0x1d4 16-bit flexray mbccfr27 16 0x1da 16-bit flexray mbfidr27 16 0x1dc 16-bit flexray mbccfr28 16 0x1e2 16-bit flexray mbfidr28 16 0x1e4 16-bit flexray mbccfr29 16 0x1ea 16-bit flexray mbfidr29 16 0x1ec 16-bit flexray mbccfr30 16 0x1f2 16-bit flexray mbfidr30 16 0x1f4 16-bit flexray mbccfr31 16 0x1fa 16-bit flexray mbfidr31 16 0x1fc 16-bit flexray mbccfr32 16 0x202 16-bit flexray mbfidr32 16 0x204 16-bit flexray mbccfr33 16 0x20a 16-bit flexray mbfidr33 16 0x20c 16-bit flexray mbccfr34 16 0x212 16-bit flexray mbfidr34 16 0x214 16-bit flexray mbccfr35 16 0x21a 16-bit flexray mbfidr35 16 0x21c 16-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) 40-38 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 flexray mbccfr36 16 0x222 16-bit flexray mbfidr36 16 0x224 16-bit flexray mbccfr37 16 0x22a 16-bit flexray mbfidr37 16 0x22c 16-bit flexray mbccfr38 16 0x232 16-bit flexray mbfidr38 16 0x234 16-bit flexray mbccfr39 16 0x23a 16-bit flexray mbfidr39 16 0x23c 16-bit flexray mbccfr40 16 0x242 16-bit flexray mbfidr40 16 0x244 16-bit flexray mbccfr41 16 0x24a 16-bit flexray mbfidr41 16 0x24c 16-bit flexray mbccfr42 16 0x252 16-bit flexray mbfidr42 16 0x254 16-bit flexray mbccfr43 16 0x25a 16-bit flexray mbfidr43 16 0x25c 16-bit flexray mbccfr44 16 0x262 16-bit flexray mbfidr44 16 0x264 16-bit flexray mbccfr45 16 0x26a 16-bit flexray mbfidr45 16 0x26c 16-bit flexray mbccfr46 16 0x272 16-bit flexray mbfidr46 16 0x274 16-bit flexray mbccfr47 16 0x27a 16-bit flexray mbfidr47 16 0x27c 16-bit flexray mbccfr48 16 0x282 16-bit flexray mbfidr48 16 0x284 16-bit flexray mbccfr49 16 0x28a 16-bit flexray mbfidr49 16 0x28c 16-bit flexray mbccfr50 16 0x292 16-bit flexray mbfidr50 16 0x294 16-bit flexray mbccfr51 16 0x29a 16-bit flexray mbfidr51 16 0x29c 16-bit flexray mbccfr52 16 0x2a2 16-bit flexray mbfidr52 16 0x2a4 16-bit flexray mbccfr53 16 0x2aa 16-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) freescale semiconductor 40-39 pxs20 microcontroller reference manual, rev. 1 flexray mbfidr53 16 0x2ac 16-bit flexray mbccfr54 16 0x2b2 16-bit flexray mbfidr54 16 0x2b4 16-bit flexray mbccfr55 16 0x2ba 16-bit flexray mbfidr55 16 0x2bc 16-bit flexray mbccfr56 16 0x2c2 16-bit flexray mbfidr56 16 0x2c4 16-bit flexray mbccfr57 16 0x2ca 16-bit flexray mbfidr57 16 0x2cc 16-bit flexray mbccfr58 16 0x2d2 16-bit flexray mbfidr58 16 0x2d4 16-bit flexray mbccfr59 16 0x2da 16-bit flexray mbfidr59 16 0x2dc 16-bit flexray mbccfr60 16 0x2e2 16-bit flexray mbfidr60 16 0x2e4 16-bit flexray mbccfr61 16 0x2ea 16-bit flexray mbfidr61 16 0x2ec 16-bit flexray mbccfr62 16 0x2f2 16-bit flexray mbfidr62 16 0x2f4 16-bit flexray mbccfr63 16 0x2fa 16-bit flexray mbfidr63 16 0x2fc 16-bit fmpll0 cr 32 0x0 32-bit fmpll0 mr 32 0x4 32-bit fmpll1 cr 32 0x0 32-bit fmpll1 mr 32 0x4 32-bit linflex_0 lincr1 32 0x0 32-bit linflex_0 linier 32 0x4 32-bit linflex_0 uartcr 32 0x10 32-bit linflex_0 lintcsr 32 0x18 32-bit linflex_0 linocr 32 0x1c 32-bit linflex_0 lintocr 32 0x20 32-bit linflex_0 linfbrr 32 0x24 32-bit linflex_0 linibrr 32 0x28 32-bit linflex_0 lincr2 32 0x30 32-bit linflex_0 bidr 32 0x34 32-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) 40-40 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 linflex_0 ifer 32 0x40 32-bit linflex_0 ifmr 32 0x48 32-bit linflex_0 ifcr20 32 0x4c 32-bit linflex_0 ifcr21 32 0x50 32-bit linflex_0 ifcr22 32 0x54 32-bit linflex_0 ifcr23 32 0x58 32-bit linflex_0 ifcr24 32 0x5c 32-bit linflex_0 ifcr25 32 0x60 32-bit linflex_0 ifcr26 32 0x64 32-bit linflex_0 ifcr27 32 0x68 32-bit linflex_0 ifcr28 32 0x6c 32-bit linflex_0 ifcr29 32 0x70 32-bit linflex_0 ifcr210 32 0x74 32-bit linflex_0 ifcr211 32 0x78 32-bit linflex_0 ifcr212 32 0x7c 32-bit linflex_0 ifcr213 32 0x80 32-bit linflex_0 ifcr214 32 0x84 32-bit linflex_0 ifcr215 32 0x88 32-bit linflex_0 gcr 32 0x8c 32-bit linflex_0 uartpto 32 0x90 32-bit linflex_0 edmatxe 32 0x98 32-bit linflex_0 edmarxe 32 0x9c 32-bit linflex_1 lincr1 32 0x0 32-bit linflex_1 linier 32 0x4 32-bit linflex_1 uartcr 32 0x10 32-bit linflex_1 lintcsr 32 0x18 32-bit linflex_1 linocr 32 0x1c 32-bit linflex_1 lintocr 32 0x20 32-bit linflex_1 linfbrr 32 0x24 32-bit linflex_1 linibrr 32 0x28 32-bit linflex_1 lincr2 32 0x30 32-bit linflex_1 bidr 32 0x34 32-bit linflex_1 ifer 32 0x40 32-bit linflex_1 ifmr 32 0x48 32-bit linflex_1 ifcr20 32 0x4c 32-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) freescale semiconductor 40-41 pxs20 microcontroller reference manual, rev. 1 linflex_1 ifcr21 32 0x50 32-bit linflex_1 ifcr22 32 0x54 32-bit linflex_1 ifcr23 32 0x58 32-bit linflex_1 ifcr24 32 0x5c 32-bit linflex_1 ifcr25 32 0x60 32-bit linflex_1 ifcr26 32 0x64 32-bit linflex_1 ifcr27 32 0x68 32-bit linflex_1 ifcr28 32 0x6c 32-bit linflex_1 ifcr29 32 0x70 32-bit linflex_1 ifcr210 32 0x74 32-bit linflex_1 ifcr211 32 0x78 32-bit linflex_1 ifcr212 32 0x7c 32-bit linflex_1 ifcr213 32 0x80 32-bit linflex_1 ifcr214 32 0x84 32-bit linflex_1 ifcr215 32 0x88 32-bit linflex_1 gcr 32 0x8c 32-bit linflex_1 uartpto 32 0x90 32-bit linflex_1 edmatxe 32 0x98 32-bit linflex_1 edmarxe 32 0x9c 32-bit mc_cgm (cut1) cgm_oc_en 32 0x0 32-bit mc_cgm (cut1) cgm_ocds_sc 32 0x4 32-bit mc_cgm (cut1) cgm_sc_dc0 8 0xc 8-bit mc_cgm (cut1) cgm_ac0_sc 32 0x10 32-bit mc_cgm (cut1) cgm_ac0_dc0 8 0x14 8-bit mc_cgm (cut1) cgm_ac0_dc1 8 0x15 8-bit mc_cgm (cut1) cgm_ac1_sc 32 0x18 32-bit mc_cgm (cut1) cgm_ac1_dc0 8 0x1c 8-bit mc_cgm (cut1) cgm_ac2_sc 32 0x20 32-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) 40-42 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 mc_cgm (cut1) cgm_ac2_dc0 8 0x24 8-bit mc_cgm (cut1) cgm_ac3_sc 32 0x28 32-bit mc_cgm (cut1) cgm_ac4_sc 32 0x30 32-bit mc_cgm (cut2/3) cgm_oc_en 32 0x370 32-bit mc_cgm (cut2/3) cgm_ocds_sc 32 0x374 32-bit mc_cgm (cut2/3) cgm_sc_dc0 8 0x37c 8-bit mc_cgm (cut2/3) cgm_ac0_sc 32 0x380 32-bit mc_cgm (cut2/3) cgm_ac0_dc0 8 0x384 8-bit mc_cgm (cut2/3) cgm_ac0_dc1 8 0x385 8-bit mc_cgm (cut2/3) cgm_ac1_sc 32 0x388 32-bit mc_cgm (cut2/3) cgm_ac1_dc0 8 0x38c 8-bit mc_cgm (cut2/3) cgm_ac2_sc 32 0x390 32-bit mc_cgm (cut2/3) cgm_ac2_dc0 8 0x394 8-bit mc_cgm (cut2/3) cgm_ac3_sc 32 0x398 32-bit mc_cgm (cut2/3) cgm_ac4_sc 32 0x3a0 32-bit mc_me mc_me 32 0x8 32-bit mc_me me_im 32 0x10 32-bit mc_me me_test_mc 32 0x024 32-bit mc_me me_safe_mc 32 0x028 32-bit mc_me me_drun_mc 32 0x02c 32-bit mc_me me_run0_mc 32 0x030 32-bit mc_me me_run1_mc 32 0x034 32-bit mc_me me_run2_mc 32 0x038 32-bit mc_me me_run3_mc 32 0x03c 32-bit mc_me me_halt0_mc 32 0x040 32-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) freescale semiconductor 40-43 pxs20 microcontroller reference manual, rev. 1 mc_me me_stop0_mc 32 0x048 32-bit mc_me me_run_pc0 32 0x080 32-bit mc_me me_run_pc1 32 0x084 32-bit mc_me me_run_pc2 32 0x088 32-bit mc_me me_run_pc3 32 0x08c 32-bit mc_me me_run_pc4 32 0x090 32-bit mc_me me_run_pc5 32 0x094 32-bit mc_me me_run_pc6 32 0x098 32-bit mc_me me_run_pc7 32 0x09c 32-bit mc_me me_lp_pc0 32 0x0a0 32-bit mc_me me_lp_pc1 32 0x0a4 32-bit mc_me me_lp_pc2 32 0x0a8 32-bit mc_me me_lp_pc3 32 0x0ac 32-bit mc_me me_lp_pc4 32 0x0b0 32-bit mc_me me_lp_pc5 32 0x0b4 32-bit mc_me me_lp_pc6 32 0x0b8 32-bit mc_me me_lp_pc7 32 0x0bc 32-bit mc_me me_pctl4 8 0xc4 8-bit mc_me me_pctl5 8 0xc5 8-bit mc_me me_pctl6 8 0xc6 8-bit mc_me me_pctl16 8 0xd0 8-bit mc_me me_pctl17 8 0xd1 8-bit mc_me me_pctl24 8 0xd8 8-bit mc_me me_pctl32 8 0xe0 8-bit mc_me me_pctl33 8 0xe1 8-bit mc_me me_pctl35 8 0xe3 8-bit mc_me me_pctl38 8 0xe6 8-bit mc_me me_pctl39 8 0xe7 8-bit mc_me me_pctl40 8 0xe8 8-bit mc_me me_pctl41 8 0xe9 8-bit mc_me me_pctl42 8 0xea 8-bit mc_me me_pctl48 8 0xf0 8-bit mc_me me_pctl49 8 0xf1 8-bit mc_me me_pctl58 8 0xfa 8-bit mc_me me_pctl62 8 0xfe 8-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) 40-44 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 mc_me me_pctl92 8 0x11c 8-bit mc_rgm rgm_fear 16 0x10 16-bit mc_rgm rgm_fess 16 0x18 16-bit mc_rgm rgm_fbre 16 0x1c 16-bit pit pitmcr 32 0x0 32-bit pit ldval0 32 0x100 32-bit pit tctrl0 32 0x108 32-bit pit ldval1 32 0x110 32-bit pit tctrl1 32 0x118 32-bit pit ldval2 32 0x120 32-bit pit tctrl2 32 0x128 32-bit pit ldval3 32 0x130 32-bit pit tctrl3 32 0x138 32-bit pmu ctrl 32 0x44 32-bit pmu irqe 32 0x7c 32-bit ctl 32 0x0 32-bit siul irer 32 0x0018 32-bit siul ireer 32 0x0028 32-bit siul ifeer 32 0x002c 32-bit siul ifer 32 0x0030 32-bit siul pcr0 16 0x0040 16-bit siul pcr1 16 0x0042 16-bit siul pcr2 16 0x0044 16-bit siul pcr3 16 0x0046 16-bit siul pcr4 16 0x0048 16-bit siul pcr5 16 0x004a 16-bit siul pcr6 16 0x004c 16-bit siul pcr7 16 0x004e 16-bit siul pcr8 16 0x50 16-bit siul pcr9 16 0x52 16-bit siul pcr10 16 0x54 16-bit siul pcr11 16 0x56 16-bit siul pcr12 16 0x58 16-bit siul pcr13 16 0x005a 16-bit siul pcr14 16 0x005c 16-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) freescale semiconductor 40-45 pxs20 microcontroller reference manual, rev. 1 siul pcr15 16 0x005e 16-bit siul pcr16 16 0x60 16-bit siul pcr17 16 0x62 16-bit siul pcr18 16 0x64 16-bit siul pcr19 16 0x66 16-bit siul pcr20 16 0x68 16-bit siul pcr21 16 0x006a 16-bit siul pcr22 16 0x006c 16-bit siul pcr23 16 0x006e 16-bit siul pcr24 16 0x70 16-bit siul pcr25 16 0x72 16-bit siul pcr26 16 0x74 16-bit siul pcr27 16 0x76 16-bit siul pcr28 16 0x78 16-bit siul pcr29 16 0x007a 16-bit siul pcr30 16 0x007c 16-bit siul pcr31 16 0x007e 16-bit siul pcr32 16 0x80 16-bit siul pcr33 16 0x82 16-bit siul pcr34 16 0x84 16-bit siul pcr36 16 0x88 16-bit siul pcr37 16 0x008a 16-bit siul pcr38 16 0x008c 16-bit siul pcr39 16 0x008e 16-bit siul pcr42 16 0x94 16-bit siul pcr43 16 0x96 16-bit siul pcr44 16 0x98 16-bit siul pcr45 16 0x009a 16-bit siul pcr46 16 0x009c 16-bit siul pcr47 16 0x009e 16-bit siul pcr48 16 0x00a0 16-bit siul pcr49 16 0x00a2 16-bit siul pcr50 16 0x00a4 16-bit siul pcr51 16 0x00a6 16-bit siul pcr52 16 0x00a8 16-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) 40-46 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 siul pcr53 16 0x00aa 16-bit siul pcr54 16 0x00ac 16-bit siul pcr55 16 0x00ae 16-bit siul pcr56 16 0x00b0 16-bit siul pcr57 16 0x00b2 16-bit siul pcr58 16 0x00b4 16-bit siul pcr59 16 0x00b6 16-bit siul pcr60 16 0x00b8 16-bit siul pcr62 16 0x00bc 16-bit siul pcr64 16 0x00c0 16-bit siul pcr66 16 0x00c4 16-bit siul pcr68 16 0x00c8 16-bit siul pcr69 16 0x00ca 16-bit siul pcr70 16 0x00cc 16-bit siul pcr71 16 0x00ce 16-bit siul pcr73 16 0x00d2 16-bit siul pcr74 16 0x00d4 16-bit siul pcr75 16 0x00d6 16-bit siul pcr76 16 0x00d8 16-bit siul pcr77 16 0x00da 16-bit siul pcr78 16 0x00dc 16-bit siul pcr79 16 0x00de 16-bit siul pcr80 16 0x00e0 16-bit siul pcr83 16 0x00e6 16-bit siul pcr84 16 0x00e8 16-bit siul pcr85 16 0x00ea 16-bit siul pcr86 16 0x00ec 16-bit siul pcr87 16 0x00ee 16-bit siul pcr88 16 0x00f0 16-bit siul pcr89 16 0x00f2 16-bit siul pcr90 16 0x00f4 16-bit siul pcr91 16 0x00f6 16-bit siul pcr92 16 0x00f8 16-bit siul pcr93 16 0x00fa 16-bit siul pcr94 16 0x00fc 16-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) freescale semiconductor 40-47 pxs20 microcontroller reference manual, rev. 1 siul pcr95 16 0x00fe 16-bit siul pcr98 16 0x104 16-bit siul pcr99 16 0x106 16-bit siul pcr100 16 0x108 16-bit siul pcr101 16 0x010a 16-bit siul pcr102 16 0x010c 16-bit siul pcr103 16 0x010e 16-bit siul pcr104 16 0x110 16-bit siul pcr105 16 0x112 16-bit siul pcr106 16 0x114 16-bit siul pcr107 16 0x116 16-bit siul pcr108 16 0x118 16-bit siul pcr109 16 0x11a 16-bit siul pcr110 16 0x11c 16-bit siul pcr111 16 0x11e 16-bit siul pcr112 16 0x120 16-bit siul pcr113 16 0x122 16-bit siul pcr114 16 0x124 16-bit siul pcr115 16 0x126 16-bit siul pcr116 16 0x128 16-bit siul pcr117 16 0x12a 16-bit siul pcr118 16 0x12c 16-bit siul pcr119 16 0x12e 16-bit siul pcr120 16 0x130 16-bit siul pcr121 16 0x132 16-bit siul pcr122 16 0x134 16-bit siul pcr123 16 0x136 16-bit siul pcr124 16 0x138 16-bit siul pcr125 16 0x13a 16-bit siul pcr126 16 0x13c 16-bit siul pcr127 16 0x13e 16-bit siul pcr128 16 0x140 16-bit siul pcr129 16 0x142 16-bit siul pcr130 16 0x144 16-bit siul pcr131 16 0x146 16-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) 40-48 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 siul pcr132 (cut2/3 only) 16 0x148 16-bit siul psmi0 8 0x0500 8-bit siul psmi1 8 0x0501 8-bit siul psmi2 8 0x0502 8-bit siul psmi3 8 0x0503 8-bit siul psmi7 8 0x0507 8-bit siul psmi8 8 0x0508 8-bit siul psmi9 8 0x0509 8-bit siul psmi10 8 0x050a 8-bit siul psmi11 8 0x050b 8-bit siul psmi12 8 0x050c 8-bit siul psmi13 8 0x050d 8-bit siul psmi14 8 0x050e 8-bit siul psmi15 8 0x050f 8-bit siul psmi16 8 0x0510 8-bit siul psmi17 8 0x0511 8-bit siul psmi18 8 0x0512 8-bit siul psmi19 8 0x0513 8-bit siul psmi20 8 0x0514 8-bit siul psmi21 8 0x0515 8-bit siul psmi22 8 0x0516 8-bit siul psmi23 8 0x0517 8-bit siul psmi24 8 0x0518 8-bit siul psmi25 8 0x0519 8-bit siul psmi26 8 0x051a 8-bit siul psmi27 8 0x051b 8-bit siul psmi28 8 0x051c 8-bit siul psmi29 8 0x051d 8-bit siul psmi30 8 0x051e 8-bit siul psmi31 8 0x051f 8-bit siul psmi32 8 0x0520 8-bit siul psmi33 8 0x0521 8-bit siul psmi34 8 0x0522 8-bit siul psmi35 8 0x0523 8-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) freescale semiconductor 40-49 pxs20 microcontroller reference manual, rev. 1 siul psmi36 8 0x0524 8-bit siul psmi37 8 0x0525 8-bit siul psmi38 8 0x0526 8-bit siul psmi39 8 0x0527 8-bit siul psmi40 8 0x0528 8-bit siul psmi41 8 0x0529 8-bit siul psmi42 8 0x052a 8-bit siul mpgpdo0 32 0x0c80 32-bit siul mpgpdo1 32 0x0c84 32-bit siul mpgpdo2 32 0x0c88 32-bit siul mpgpdo3 32 0x0c8c 32-bit siul mpgpdo4 32 0x0c90 32-bit siul mpgpdo5 32 0x0c94 32-bit siul mpgpdo6 32 0x0c98 32-bit siul mpgpdo7 32 0x0c9c 32-bit siul mpgpdo8 32 0x0ca0 32-bit siul ifmc0 32 0x1000 32-bit siul ifmc1 32 0x1004 32-bit siul ifmc2 32 0x1008 32-bit siul ifmc3 32 0x100c 32-bit siul ifmc4 32 0x1010 32-bit siul ifmc5 32 0x1014 32-bit siul ifmc6 32 0x1018 32-bit siul ifmc7 32 0x101c 32-bit siul ifmc8 32 0x1020 32-bit siul ifmc9 32 0x1024 32-bit siul ifmc10 32 0x1028 32-bit siul ifmc11 32 0x102c 32-bit siul ifmc12 32 0x1030 32-bit siul ifmc13 32 0x1034 32-bit siul ifmc14 32 0x1038 32-bit siul ifmc15 32 0x103c 32-bit siul ifmc16 32 0x1040 32-bit siul ifmc17 32 0x1044 32-bit siul ifmc18 32 0x1048 32-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
register protection (reg_prot) 40-50 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 siul ifmc19 32 0x104c 32-bit siul ifmc20 32 0x1050 32-bit siul ifmc21 32 0x1054 32-bit siul ifmc22 32 0x1058 32-bit siul ifmc23 32 0x105c 32-bit siul ifmc24 32 0x1060 32-bit siul ifmc25 32 0x1064 32-bit siul ifmc26 32 0x1068 32-bit siul ifmc27 32 0x106c 32-bit siul ifmc28 32 0x1070 32-bit siul ifmc29 32 0x1074 32-bit siul ifmc30 32 0x1078 32-bit siul ifmc31 32 0x107c 32-bit siul ifcpr 32 0x1080 32-bit sscm error 16 0x6 16-bit sscm debugport 16 0x8 16-bit sscm sctr 32 0x24 32-bit swg ctrl 32 0x0 32-bit wkpu ncr 32 0x8 32-bit xosc ctl 32 0x0 32-bit table 40-5. pxs20 register protection (continued) module register size offset protect size
reset generation module (mc_rgm) freescale semiconductor 41-1 pxs20 microcontroller reference manual, rev. 1 chapter 41 reset generation module (mc_rgm) 41.1 introduction 41.1.1 overview the reset generation module (mc_rgm) centralizes the different rese t sources and manages the reset sequence of the device. it provides a register inte rface and the reset sequencer. various registers are available to monitor and control the device reset seque nce. the reset sequencer is a state machine which controls the different phases ( phase0 , phase1 , phase2 , phase3 , and idle ) of the reset sequence and controls the reset signals generated in the system. figure 41-1 depicts the mc_rgm block diagram.
reset generation module (mc_rgm) 41-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 41.1.2 features the mc_rgm contains the functiona lity for the following features: ? ?destructive? resets management ? ?functional? resets management ? signalling of reset events after eac h reset sequence (reset status flags) ? conversion of reset events to safe mode or interrupt request events ? short reset seque nce configuration a[4:2] reset_b registers platform interface core mc_rgm figure 41-1. mc_rgm block diagram mc_me power-on 1.2 v low-voltage detected 1.2 v high-voltage detected 2.7 v low-voltage det. (vreg) 2.7 v low-voltage det. (flash) 2.7 v low-voltage det. (i/o) software ?destructive? reset (cut2/3) jtag initiated reset core reset software ?functional? reset core watchdog reset pll0 fail oscillator freq. too low system clock freq. too high/low fccu safe mode request software watchdog timer pll1 fail flash, ecc, or lock-step error cmu1/2 clock freq. too high/low self-test completed fccu soft reaction request fccu hard reaction request functional reset filter boot mode capture destructive reset filter reset state machine sscm peripherals mc_cgm
reset generation module (mc_rgm) freescale semiconductor 41-3 pxs20 microcontroller reference manual, rev. 1 ? bidirectional reset behavior configuration ? boot mode capture on reset_b deassertion 41.1.3 reset sources the different reset sources are organized into two families: ?destructive? and ?functional?. ? a ?destructive? reset source is as sociated with an event related to a critical - usually hardware - error or dysfunction. when a ?destr uctive? reset event occurs, the fu ll reset sequence is applied to the device starting from phase0 . this resets the full device ensu ring a safe start-up state for both digital and analog modules. ?destructive? resets are ? power-on reset ? 1.2 v low-voltage detected ? 1.2 v high-voltage detected ? 2.7 v low-voltage det. (vreg) ? 2.7 v low-voltage det. (flash) ? 2.7 v low-voltage det. (i/o) ? cut2/3: software ?destructive? reset ? a ?functional? reset source is associated with an event related to a less-critical - usually non-hardware - error or dysfunction. when a ?func tional? reset event occurs, a partial reset sequence is applied to the device starting from phase1 . in this case, most digital modules are reset normally, while analog modules or spec ific digital modules? (e.g. debug modules, flash modules) state is preserved. ?functional? resets are ? external reset ? jtag initiated reset ? core reset ? software ?functional? reset ? core watchdog reset ? pll0 fail ? oscillator freq. too low ? system clock freq. too high/low ?fccu safe mode request ? software watchdog timer ? pll1 fail ? flash, ecc, or lock-step error ? cmu1/2 clock freq. too high/low ? self-test completed ? fccu soft reaction request ? fccu hard reaction request
reset generation module (mc_rgm) 41-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 when a reset is triggered, the mc_rgm state mach ine is activated and proceeds through the different phases (i.e. phasen states). each phase is associated with a particular device reset being provided to the system. a phase is completed when all corresponding phase completion ga tes from either the system or internal to the mc_rgm are acknowledged. the device re set associated with the phase is then released, and the state machine proceeds to the next phase up to entering the idle phase. during this entire process, the mc_me state machine is held in reset mode. only at the end of the reset sequence, when the idle phase is reached, does the mc_me enter the drun mode. alternatively, it is possibl e for software to configure some reset source events to be converted from a reset to either a safe mode request issued to the mc_me or to an interrupt issued to the core (see section 41.3.1.3, functional event rese t disable register (rgm_ferd) and section 41.3.1.5, functional event alternate re quest register (rgm_fear) for ?functional? resets). 41.2 external signal description the mc_rgm interfaces to the bidirectional reset pin reset_b and the boot mode pins pa [ 4 : 2 ] . 41.3 memory map and register definition note any access to unused registers as we ll as write accesses to read-only registers will: ? not change register content table 41-1. mc_rgm register summary address name description size access location user supervisor test 0xc3fe _4000 rgm_fes functional event status half-word read read/write 1 read/write 1 on page 41-8 0xc3fe _4002 rgm_des destructive event status half-word read read/write 1 notes: 1 individual bits cleared on writing ?1? read/write 1 on page 41-10 0xc3fe _4004 rgm_ferd functional event reset disable half-word read read/write 2 2 write once: ?0? = enable, ?1? = disable. read/write 2 on page 41-12 0xc3fe _4006 rgm_derd destructive event reset disable half-word read read read on page 41-14 0xc3fe _4010 rgm_fear functional event alternate request half-word read read/write read/write on page 41-15 0xc3fe _4018 rgm_fess functional event short sequence half-word read read/write read/write on page 41-16 0xc3fe _401c rgm_fbre functional bidirectional reset enable half-word read read/write read/write on page 41-18
reset generation module (mc_rgm) freescale semiconductor 41-5 pxs20 microcontroller reference manual, rev. 1 ? cause a transfer error table 41-2. mc_rgm memory map address name 01232756789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0xc3fe _4000 rgm_ fes / r f_exr f_fccu_hard f_fccu_soft f_st_done f_cmu12_fhl f_fl_ecc_rcc f_pll1 f_swt f_fccu_safe f_cmu0_fhl f_cmu0_olr f_pll0 f_cwd f_soft (cut1) f_soft_func (cut2/3) f_core f_jtag ww1c 0xc3fe _4002 rgm_ des (cut1) r f_por 00000000 f_lvd27_io f_lvd27_flash f_lvd27_vreg 00 f_hvd12 f_lvd12 ww1c rgm_ des (cut2/3 ) r f_por f_soft_dest 0000000 f_lvd27_io f_lvd27_flash f_lvd27_vreg 00 f_hvd12 f_lvd12 ww1cw1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
reset generation module (mc_rgm) 41-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 0xc3fe _4004 rgm_ ferd r d_exr d_fccu_hard d_fccu_soft d_st_done d_cmu12_fhl d_fl_ecc_rcc d_pll1 d_swt d_fccu_safe d_cmu0_fhl d_cmu0_olr d_pll0 d_cwd d_soft (cut1) d_soft_func (cut2/3) d_core d_jtag w 0xc3fe _4006 rgm_ derd (cut1) r000000000 d_lvd27_io d_lvd27_flash d_lvd27_vreg 00 d_hvd12 d_lvd12 w rgm_ derd (cut2/3 ) r d_soft_dest 00000000 d_lvd27_io d_lvd27_flash d_lvd27_vreg 00 d_hvd12 d_lvd12 w 0xc3fe _4008 ? 0xc3fe _400c reserved 0xc3fe _4010 rgm_ fear r0000 ar_cmu12_fhl 0 ar_pll1 0 ar_fccu_safe ar_cmu0_fhl ar_cmu0_olr ar_pll0 ar_cwd 000 w r0000000000000000 w 0xc3fe _4014 reserved table 41-2. mc_rgm memory map (continued) address name 01232756789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reset generation module (mc_rgm) freescale semiconductor 41-7 pxs20 microcontroller reference manual, rev. 1 41.3.1 register descriptions unless otherwise noted, all registers may be accessed as 32-bit word s, 16-bit half-words, or 8-bit bytes. the bytes are ordered according to big endian. for example, the rgm_des[8:15] register bits may be accessed as a word at address 0xc3fe_4000, as a half-word at addr ess 0xc3fe_4002, or as a byte at address 0xc3fe_4004 (for cut1 ) or 0xc3fe_4003 (for cut2/3). some fields may be read-only, and their reset value of ?1? or ?0? and the corr esponding behavior cannot be changed. 0xc3fe _4018 rgm_ fess r ss_exr ss_fccu_hard ss_fccu_soft ss_st_done ss_cmu12_fhl ss_fl_ecc_rcc ss_pll1 ss_swt 0 ss_cmu0_fhl ss_cmu0_olr ss_pll0 ss_cwd ss_soft (cut1) ss_soft_func (cut2/3) ss_core ss_jtag w r0000000000000000 w 0xc3fe _401c rgm_ fbre r be_exr be_fccu_hard be_fccu_soft be_st_done be_cmu12_fhl be_fl_ecc_rcc be_pll1 be_swt 0 be_cmu0_fhl be_cmu0_olr be_pll0 be_cwd be_soft (cut1) be_soft_func (cut2/3) be_core be_jtag w r0000000000000000 w 0xc3fe _4020 ? 0xc3fe _7ffc reserved table 41-2. mc_rgm memory map (continued) address name 01232756789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reset generation module (mc_rgm) 41-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 41.3.1.1 functional event status register (rgm_fes) this register contains the status of the last asserted functional reset s ources. register bits are cleared as follows: ? for cut1: on write ?1? ? for cut2/3: on write ?1? if the triggering event has already been cleared at the source note for cut2/3: if a ?functional? reset s ource is configured to generate a safe mode request or an interrupt request, so ftware needs to clear the event in the source module at least three system clock cycles before it clears the associated rgm_fes status bit in order to avoid multiple safe mode requests or interrupts for the same event. in order to avoid having to count cycles, it is good practice for software to check whether the rgm_fes has been properly cleared, and if not, clear it again. address 0xc3fe_4000 access: user read, supervisor read/write, test read/write 0123456789101112131415 r f_exr f_fccu_hard f_fccu_soft f_st_done f_cmu12_fhl f_fl_ecc_rcc f_pll1 f_swt f_fccu_safe f_cmu0_fhl f_cmu0_olr f_pll0 f_cwd f_soft (cut1) f_soft_func (cut2/3) f_core f_jtag ww1c reset * 0000000000000000 * this register is reset if and only if one of thefollowing occurs: ?power up ? 1.2 v low-voltage detection (i.e. when the core voltage drops below the point at which the flip-flops can reliably retain their value) figure 41-2. functional event status register (rgm_fes) table 41-3. functional event status register (rgm_fes) field descriptions field description f_exr flag for external reset 0 no external reset event has occurred since either the last clear or the last destructive reset assertion 1 an external reset event has occurred f_fccu_hard flag for fccu hard reaction request 0 no fccu hard reaction request event has occurr ed since either the last clear or the last destructive re set assertion 1 a fccu hard reaction request event has occurred w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
reset generation module (mc_rgm) freescale semiconductor 41-9 pxs20 microcontroller reference manual, rev. 1 f_fccu_soft flag for fccu soft reaction request 0 no fccu soft reaction request event has occurred since either the last clear or the last destructive re set assertion 1 a fccu soft reaction request event has occurred f_st_done flag for self-test completed 0 no self-test completed event has occurred si nce either the last clear or the last destructive re set assertion 1 a self-test completed event has occurred f_cmu12_fhl flag for cmu1/2 clock freq. too high/low 0 no cmu1/2 clock freq. too high/low event has occurred since either the last clear or the last destructive reset assertion 1 a cmu1/2 clock freq. too high/low event has occurred f_fl_ecc_rcc flag for flash, ecc, or lock-step error 0 no flash, ecc, or lock-step error event has o ccurred since either the last clear or the last destructive re set assertion 1 a flash, ecc, or lock-step error event has occurred f_pll1 flag for pll1 fail 0 no pll1 fail event has occurred since either the last clear or the last destructive reset assertion 1 a pll1 fail event has occurred f_swt flag for software watchdog timer 0 no software watchdog timer event has occurred since either the last clear or the last destructive re set assertion 1 a software watchdog timer event has occurred f_fccu_safe flag for fccu safe mode request 0 no fccu safe mode request event has occurred since either the last clear or the last destructive re set assertion 1 a fccu safe mode request event has occurred f_cmu0_fhl flag for system clock freq. too high/low 0 no system clock freq. too high/l ow event has occurred since ei ther the last clear or the last destructive reset assertion 1 a system clock freq. too high/low event has occurred f_cmu0_olr flag for oscillator freq. too low 0 no oscillator freq. too low event has occurred since either the last clear or the last destructive re set assertion 1 a oscillator freq. too low event has occurred f_pll0 flag for pll0 fail 0 no pll0 fail event has occurred since either the last clear or the last destructive reset assertion 1 a pll0 fail event has occurred f_cwd flag for core watchdog reset 0 no core watchdog reset event has occurred since either the last clear or the last destructive re set assertion 1 a core watchdog reset event has occurred table 41-3. functional event status regist er (rgm_fes) field descriptions (continued) field description
reset generation module (mc_rgm) 41-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 41.3.1.2 destructive event st atus register (rgm_des) f_soft (cut1) f_soft_func (cut2/3) flag for software ?functional? reset 0 no software ?functional? reset event has occurr ed since either the last clear or the last destructive re set assertion 1 a software ?functional? reset event has occurred f_core flag for core reset 0 no core reset event has occurred since either the last clear or the last destructive reset assertion 1 a core reset event has occurred f_jtag flag for jtag initiated reset 0 no jtag initiated reset event has occurred since either the last clear or the last destructive re set assertion 1 a jtag initiated reset event has occurred address 0xc3fe_4002 access: user read, supervisor read/write, test read/write 0123456789101112131415 r f_por 00000000 f_lvd27_io f_lvd27_flash f_lvd27_vreg 00 f_hvd12 f_lvd12 ww1c reset * 1000000000000000 * this register is reset if and on ly if one of thefollowing occurs: ? power up ? 1.2 v low-voltage detection (i.e. when the core voltage drops below the point at which the flip-flops can reliably retain their value) figure 41-3. destructive event status register (rgm_des) for cut1 table 41-3. functional event status regist er (rgm_fes) field descriptions (continued) field description w1c w1c w1c w1c w1c
reset generation module (mc_rgm) freescale semiconductor 41-11 pxs20 microcontroller reference manual, rev. 1 this register contains the status of the last asserted destructive re set sources. it can be accessed in read/write on either supervisor mode or test mode. register bits ar e cleared on write ?1?. address 0xc3fe_4002 access: user read, supervisor read/write, test read/write 0123456789101112131415 r f_por f_soft_dest 0000000 f_lvd27_io f_lvd27_flash f_lvd27_vreg 00 f_hvd12 f_lvd12 ww1c w1c reset * 1000000000000000 * this register is reset if and on ly if one of thefollowing occurs: ? power up ? 1.2 v low-voltage detection (i.e. when the core voltage drops below the point at which the flip-flops can reliably retain their value) figure 41-4. destructive event status register (rgm_des) for cut2/3 table 41-4. destructive event status register (rgm_des) field descriptions field description f_por flag for power-on reset 0 no power-on event has occurred since the last clear 1 a power-on event has occurred f_soft_de st (cut2/3) flag for software 'destructive' reset 0 no software 'destructive' reset event has occurred since either the last clear or the last power-on reset assertion 1 a software 'destructive' reset event has occurred f_lvd27_io flag for 2.7 v low-voltage det. (i/o) 0 no 2.7 v low-voltage det. (i/o) event has occurred since either the last clear or the last power-on reset assertion 1 a 2.7 v low-voltage det. (i/o) event has occurred f_lvd27_fl ash flag for 2.7 v low-voltage det. (flash) 0 no 2.7 v low-voltage det. (flash) event has occurred since either the last clear or the last power-on reset assertion 1 a 2.7 v low-voltage det. (flash) event has occurred f_lvd27_v reg flag for 2.7 v low-voltage det. (vreg) 0 no 2.7 v low-voltage det. (vreg) event has occurr ed since either the last clear or the last power-on reset assertion 1 a 2.7 v low-voltage det. (vreg) event has occurred w1c w1c w1c w1c w1c
reset generation module (mc_rgm) 41-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 note the f_por flag is automatically cleared on a 1.2 v low-voltage detected or a 2.7 v low-voltage detected. this means that if the power-up sequence is not monotonic (i.e. the voltage ri ses and then drops enough to trigger a low-voltage detection), the f_por flag may not be set but instead the f_lvd12 or f_lvd27_vreg flag is set on exiting the reset sequence. therefore, if the f_por , f_lvd12 or f_lvd27_vreg flags are set on reset exit, software should interpret the reset cause as power-on. 41.3.1.3 functional event reset disable register (rgm_ferd) this register provides dedicated bits to disable functional reset source s.when a functional reset source is disabled, the associated functiona l event will trigger either a safe mode request or an interrupt request (see section 41.3.1.5, functional event altern ate request register (rgm_fear) ). it can be accessed in read/write in either supervisor mode or test mode. it can be accessed in read only in user mode. each byte can be written only once after power-on reset. some fields are read-only, with a por valu e of 1 or 0, and the corresponding behavior cannot be changed. f_hvd12 flag for 1.2 v high-voltage detected 0 no 1.2 v high-voltage detected event has occurred since either the last clear or the last power-on reset assertion 1 a 1.2 v high-voltage detected event has occurred f_lvd12 flag for 1.2 v low-voltage detected 0 no 1.2 v low-voltage detected event has occurred si nce either the last clear or the last power-on reset assertion 1 a 1.2 v low-voltage detected event has occurred address 0xc3fe_4004 access: user read, supervisor read/write, test read/write 0123456789101112131415 r d_exr d_fccu_hard d_fccu_soft d_st_done d_cmu12_fhl d_fl_ecc_rcc d_pll1 d_swt d_fccu_safe d_cmu0_fhl d_cmu0_olr d_pll0 d_cwd d_soft (cut1) d_soft_func (cut2/3) d_core d_jtag w reset * 0000000010000000 * this register is reset if and on ly if one of thefollowing occurs: ? power up ? 1.2 v low-voltage detection (i.e. when the core voltage drops below the point at which the flip-flops can reliably retain their value) figure 41-5. functional event reset disable register (rgm_ferd) table 41-4. destructive event status register (rgm_des) field descriptions (continued) field description
reset generation module (mc_rgm) freescale semiconductor 41-13 pxs20 microcontroller reference manual, rev. 1 table 41-5. functional event reset disable register (rgm_ferd) field descriptions field description d_exr disable external reset 0 an external reset event triggers a reset sequence d_fccu_h ard disable fccu hard reaction request 0 a fccu hard reaction request event triggers a reset sequence d_fccu_s oft disable fccu soft reaction request 0 a fccu soft reaction request event triggers a reset sequence d_st_don e disable self-test completed 0 a self-test completed event triggers a reset sequence d_cmu12_f hl disable cmu1/2 clock freq. too high/low 0 a cmu1/2 clock freq. too high/low event triggers a reset sequence 1 a cmu1/2 clock freq. too high/low event generates either a safe mode or an interrupt request depending on the value of rgm_fear.ar_cmu12_fhl d_fl_ecc_ rcc disable flash, ecc, or lock-step error 0 a flash, ecc, or lock-step error event triggers a reset sequence d_pll1 disable pll1 fail 0 a pll1 fail event triggers a reset sequence 1 a pll1 fail event generates either a safe mode or an interrupt request depending on the value of rgm_fear.ar_pll1 d_swt disable software watchdog timer 0 a software watchdog timer event triggers a reset sequence d_fccu_sa fe disable fccu safe mode request 1a fccu safe mode request event generates a safe mode request d_cmu0_f hl disable system clock freq. too high/low 0 a system clock freq. too high/low event triggers a reset sequence 1 a system clock freq. too high/low event generates either a safe mode or an interrupt request depending on the value of rgm_fear.ar_cmu0_fhl d_cmu0_o lr disable oscillator freq. too low 0 a oscillator freq. too low event triggers a reset sequence 1 a oscillator freq. too low event generates either a safe mode or an interrupt request depending on the value of rgm_fear.ar_cmu0_olr d_pll0 disable pll0 fail 0 a pll0 fail event triggers a reset sequence 1 a pll0 fail event generates either a safe mode or an interrupt request depending on the value of rgm_fear.ar_pll0 d_cwd disable core watchdog reset 0 a core watchdog reset event triggers a reset sequence 1 a core watchdog reset event generates either a safe mode or an interrupt request depending on the value of rgm_fear.ar_cwd d_soft (cut1) d_soft_fu nc (cut2/3) disable software ?functional? reset 0 a software ?functional? reset event triggers a reset sequence
reset generation module (mc_rgm) 41-14 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 41.3.1.4 destructive event reset disable register (rgm_derd) this register provides dedicated bits to disable particular destructive reset sources. it can be accessed in read-only in supervisor mode, test mode, and user mode. d_core disable core reset 0 a core reset event triggers a reset sequence d_jtag disable jtag initiated reset 0 a jtag initiated reset event triggers a reset sequence address 0xc3fe_4006 access: user read, supervisor read, test read 0123456789101112131415 r 000000000 d_lvd27_io d_lvd27_flash d_lvd27_vreg 00 d_hvd12 d_lvd12 w reset * 0000000000000000 * this register is reset if and on ly if one of thefollowing occurs: ? power up ? 1.2 v low-voltage detection (i.e. when the core voltage drops below the point at which the flip-flops can reliably retain their value) figure 41-6. destructive event reset disable register (rgm_derd) for cut1 address 0xc3fe_4006 access: user read, supervisor read, test read 0123456789101112131415 r 0 d_soft_dest 0000000 d_lvd27_io d_lvd27_flash d_lvd27_vreg 00 d_hvd12 d_lvd12 w reset * 0000000000000000 * this register is reset if and on ly if one of thefollowing occurs: ? power up ? 1.2 v low-voltage detection (i.e. when the core voltage drops below the point at which the flip-flops can reliably retain their value) figure 41-7. destructive event reset disable register (rgm_derd) for cut2/3 table 41-5. functional event reset disable register (rgm_ferd) field descriptions (continued) field description
reset generation module (mc_rgm) freescale semiconductor 41-15 pxs20 microcontroller reference manual, rev. 1 41.3.1.5 functional event alternat e request register (rgm_fear) this register defines an alternat e request to be generated when a reset on a functional event has been disabled. the alternate re quest can be either a safe mode request to mc_me or an interrupt request to the system. it can be accessed in read /write in either supervisor mode or test mode. it can be accessed in read only in user mode. table 41-6. destructive event reset disable register (rgm_derd) field descriptions field description d_soft_de st (cut2/3) disable software 'destructive' reset 0 a software 'destructive' reset event triggers a reset sequence d_lvd27_io disable 2.7 v low-voltage det. (i/o) 0 a 2.7 v low-voltage det. (i/o) event triggers a reset sequence d_lvd27_fl ash disable 2.7 v low-voltage det. (flash) 0 a 2.7 v low-voltage det. (flash) event triggers a reset sequence d_lvd27_v reg disable 2.7 v low-voltage det. (vreg) 0 a 2.7 v low-voltage det. (vreg) event triggers a reset sequence d_hvd12 disable 1.2 v high-voltage detected 0 a 1.2 v high-voltage detected event triggers a reset sequence d_lvd12 disable 1.2 v low-voltage detected 0 a 1.2 v low-voltage detected event triggers a reset sequence address 0xc3fe_4010 access: user read, supervisor read/write, test read/write 0123456789101112131415 r 0000 ar_cmu12_fhl 0 ar_pll1 0 ar_fccu_safe ar_cmu0_fhl ar_cmu0_olr ar_pll0 ar_cwd 000 w reset * 0000000000000000 * this register is reset if and only if one of thefollowing occurs: ?power up ? 1.2 v low-voltage detection (i.e. when the core voltage drops below the point at which the flip-flops can reliably retain their value) figure 41-8. functional event altern ate request register (rgm_fear)
reset generation module (mc_rgm) 41-16 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 41.3.1.6 functional event short sequence register (rgm_fess) this register defines whic h reset sequence will be do ne when a functional reset sequence is triggered. the functional reset sequence can either start from phase1 or from phase3 , skipping phase1 and phase2 . table 41-7. functional event alternate request register (rgm_fear) field descriptions field description ar_cmu12_ fhl alternate request for cmu1/2 clock freq. too high/low 0 generate a safe mode request on a cmu1/2 clock freq. t oo high/low event if the reset is disabled 1 generate an interrupt request on a cmu1/2 clock freq . too high/low event if the reset is disabled ar_pll1 alternate request for pll1 fail 0 generate a safe mode request on a pll1 fail event if the reset is disabled 1 generate an interrupt request on a pll1 fail event if the reset is disabled ar_fccu_s afe alternate request for fccu safe mode request 0 generate a safe mode request on a fccu safe mode request event if the reset is disabled ar_cmu0_f hl alternate request for system clock freq. too high/low 0 generate a safe mode request on a system clock freq. too high/low event if the reset is disabled 1 generate an interrupt request on a system clock freq. too high/low event if the reset is disabled ar_cmu0_ olr alternate request for os cillator freq. too low 0 generate a safe mode request on a oscillator freq. too low event if the reset is disabled 1 generate an interrupt request on a oscillator fr eq. too low event if the reset is disabled ar_pll0 alternate request for pll0 fail 0 generate a safe mode request on a pll0 fail event if the reset is disabled 1 generate an interrupt request on a pll0 fail event if the reset is disabled ar_cwd alternate request for core watchdog reset 0 generate a safe mode request on a core watchdog reset event if the reset is disabled 1 generate an interrupt request on a core watchdog reset event if the reset is disabled address 0xc3fe_4018 access: user read, supervisor read/write, test read/write 0123456789101112131415 r ss_exr ss_fccu_hard ss_fccu_soft ss_st_done ss_cmu12_fhl ss_fl_ecc_rcc ss_pll1 ss_swt 0 ss_cmu0_fhl ss_cmu0_olr ss_pll0 ss_cwd ss_soft ss_core ss_jtag w reset * 0010000000000000 * this register is reset if and on ly if one of thefollowing occurs: ? power up ? 1.2 v low-voltage detection (i.e. when the core voltage drops below the point at which the flip-flops can reliably retain their value) figure 41-9. functi onal event short sequence register (rgm_fess)
reset generation module (mc_rgm) freescale semiconductor 41-17 pxs20 microcontroller reference manual, rev. 1 note this could be useful for fast reset se quence, for example to skip flash reset. it can be accessed in read/write in ei ther supervisor mode or test mode. it can be accessed in read in user mode. table 41-8. functional event short sequence register (rgm_fess) field descriptions field description ss_exr short sequence for external reset 0 the reset sequence triggered by an external reset event will start from phase1 1 the reset sequence triggered by an external reset event will start from phase3 , skipping phase1 and phase2 ss_fccu_h ard short sequence for fccu hard reaction request 0 the reset sequence triggered by a fccu hard reaction request event will start from phase1 ss_fccu_s oft short sequence for fccu soft reaction request 1 the reset sequence triggered by a fccu soft reaction request event will start from phase3 , skipping phase1 and phase2 ss_st_don e short sequence for self-test completed 0 the reset sequence triggered by a self -test completed event will start from phase1 ss_cmu12_ fhl short sequence for cmu1/2 clock freq. too high/low 0 the reset sequence triggered by a cmu1/2 clock freq. too high/low event will start from phase1 1 the reset sequence triggered by a cmu1/2 clock freq. too high/low event will start from phase3 , skipping phase1 and phase2 ss_fl_ecc _rcc short sequence for flash, ecc, or lock-step error 0 the reset sequence triggered by a flash, ecc, or lock-step error event will start from phase1 ss_pll1 short sequence for pll1 fail 0 the reset sequence triggered by a pll1 fail event will start from phase1 1 the reset sequence triggered by a pll1 fail event will start from phase3 , skipping phase1 and phase2 ss_swt short sequence for so ftware watchdog timer 0 the reset sequence triggered by a software watchdog timer event will start from phase1 ss_cmu0_f hl short sequence for system clock freq. too high/low 0 the reset sequence triggered by a system clock freq. too high /low event will start from phase1 1 the reset sequence trig gered by a system clock freq. too high/low event will start from phase3 , skipping phase1 and phase2 ss_cmu0_ olr short sequence for os cillator freq. too low 0 the reset sequence triggered by a oscillator freq. too low event will start from phase1 1 the reset sequence triggered by a oscillator freq. too low event will start from phase3 , skipping phase1 and phase2 ss_pll0 short sequence for pll0 fail 0 the reset sequence triggered by a pll0 fail event will start from phase1 1 the reset sequence triggered by a pll0 fail event will start from phase3 , skipping phase1 and phase2 ss_cwd short sequence for core watchdog reset 0 the reset sequence triggered by a core watchdog reset event will start from phase1 1 the reset sequence triggered by a core watchdog reset event will start from phase3 , skipping phase1 and phase2
reset generation module (mc_rgm) 41-18 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 note this register is reset on any enabled ?destructive? or ?functional? reset event. 41.3.1.7 functional bidirectional r eset enable register (rgm_fbre) this register enables the ge neration of an external rese t on functional reset. it can be accessed in read/write in either supervisor mode or test mode. it can be accessed in read in user mode. ss_soft short sequence for softw are ?functional? reset 0 the reset sequence triggered by a software ?functional? reset event will start from phase1 1 the reset sequence triggered by a software ?functional? reset event will start from phase3 , skipping phase1 and phase2 ss_core short sequence for core reset 0 the reset sequence triggered by a core reset event will start from phase1 1 the reset sequence triggered by a core reset event will start from phase3 , skipping phase1 and phase2 ss_jtag short sequence for jtag initiated reset 0 the reset sequence triggered by a jtag initiated reset event will start from phase1 1 the reset sequence triggered by a jtag initiated reset event will start from phase3 , skipping phase1 and phase2 address 0xc3fe_401c access: user read, supervisor read/write, test read/write 0123456789101112131415 r be_exr be_fccu_hard be_fccu_soft be_st_done be_cmu12_fhl be_fl_ecc_rcc be_pll1 be_swt 0 be_cmu0_fhl be_cmu0_olr be_pll0 be_cwd be_soft be_core be_jtag w reset * 0110111101111111 * this register is reset if and on ly if one of thefollowing occurs: ? power up ? 1.2 v low-voltage detection (i.e. when the core voltage drops below the point at which the flip-flops can reliably retain their value) figure 41-10. functional bidirectional reset enable register (rgm_fbre) table 41-8. functional event short sequence regi ster (rgm_fess) field de scriptions (continued) field description
reset generation module (mc_rgm) freescale semiconductor 41-19 pxs20 microcontroller reference manual, rev. 1 table 41-9. functional bidirectional reset enab le register (rgm_fbre) field descriptions field description be_exr bidirectional reset enable for external reset 0 reset_b is asserted on an external reset event if the reset is enabled 1 reset_b is not asserted on an external reset event be_fccu_h ard bidirectional reset enable for fccu hard reaction request 0 reset_b is asserted on afccu hard reacti on request event if the reset is enabled 1 reset_b is not asserted on a fccu hard reaction request event be_fccu_s oft bidirectional reset enable for fccu soft reaction request 0 reset_b is asserted on a fccu soft reacti on request event if the reset is enabled 1 reset_b is not asserted on a fccu soft reaction request event be_st_don e bidirectional reset enable for self-test completed 0 reset_b is asserted on a self-test co mpleted event if the reset is enabled 1 reset_b is not asserted on a self-test completed event be_cmu12_ fhl bidirectional reset enable for cmu1/2 clock freq. too high/low 0 reset_b is asserted on a cmu1/2 clock freq. too high/low event if the reset is enabled 1 reset_b is not asserted on a cmu1 /2 clock freq. too high/low event be_fl_ecc _rcc bidirectional reset enable for flash, ecc, or lock-step error 0 reset_b is asserted on a flash, ecc, or lo ck-step error event if the reset is enabled 1 reset_b is not asserted on a flash, ecc, or lock-step error event be_pll1 bidirectional reset enable for pll1 fail 0 reset_b is asserted on a pll1 fail event if the reset is enabled 1 reset_b is not asserted on a pll1 fail event be_swt bidirectional reset enable for software watchdog timer 0 reset_b is asserted on a software watchdog timer event if the reset is enabled 1 reset_b is not asserted on a software watchdog timer event be_cmu0_f hl bidirectional reset enable for system clock freq. too high/low 0 reset_b is asserted on a system clock freq. too high/low event if the reset is enabled 1 reset_b is not asserted on a system clock freq. too high/low event be_cmu0_ olr bidirectional reset enable for oscillator freq. too low 0 reset_b is asserted on a oscillator freq. too low event if the reset is enabled 1 reset_b is not asserted on a oscillator freq. too low event be_pll0 bidirectional reset enable for pll0 fail 0 reset_b is asserted on a pll0 fail event if the reset is enabled 1 reset_b is not asserted on a pll0 fail event be_cwd bidirectional reset enable for core watchdog reset 0 reset_b is asserted on a core watchdog reset event if the reset is enabled 1 reset_b is not asserted on a core watchdog reset event be_soft bidirectional reset enable for software ?functional? reset 0 reset_b is asserted on a software ?functi onal? reset event if the reset is enabled 1 reset_b is not asserted on a software ?functional? reset event
reset generation module (mc_rgm) 41-20 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 41.4 functional description 41.4.1 reset state machine the main role of mc_rgm is the ge neration of the reset se quence which ensures that the correct parts of the device are reset based on the reset source event. this is summarized in table 41-10 . note jtag logic has its own independent rese t control and is not controlled by the mc_rgm in any way. the reset sequence is comprised of five phases managed by a state machin e, which ensures that all phases are correctly processed thr ough waiting for a minimum dur ation and until al l processes that need to occur during that phase have been completed before proceeding to the next phase. the state machine used to produce the reset sequence is shown in figure 41-11 . be_core bidirectional reset enable for core reset 0 reset_b is asserted on a core re set event if the reset is enabled 1 reset_b is not asserted on a core reset event be_jtag bidirectional reset enable for jtag initiated reset 0 reset_b is asserted on a jtag initia ted reset event if the reset is enabled 1 reset_b is not asserted on a jtag initiated reset event table 41-10. mc_rgm reset implications source what gets reset external reset assertion 1 notes: 1 ?external reset assertion? means t hat the reset_b pin is asserted by the mc_rgm until the end of reset phase3 boot mode capture power-on reset all yes yes ?destructive? resets all except some clock/reset management yes yes external reset all except some clock/reset management and debug programmable 2 2 the assertion of the external reset is controlled via the rgm_fbre register yes ?functional? resets all except some clock/reset management and debug programmable 2 programmable 3 3 the boot mode is captured if the external reset is asserted shortened ?functional? resets 4 4 the short sequence is enabled via the rgm_fess register flip-flops except some clock/reset management programmable 2 programmable 3 table 41-9. functional bidirectional reset enable register (rgm_fbre) field descriptions (continued) field description
reset generation module (mc_rgm) freescale semiconductor 41-21 pxs20 microcontroller reference manual, rev. 1 41.4.1.1 phase0 phase this phase is entered immediately from any phase on a power-on or enab led ?destructive? reset event. the reset state machine exits phase0 and enters phase1 on verification of the following: ? all enabled ?destructive? re sets have been processed ? all processes that need to be done in phase0 are completed figure 41-11. mc_rgm state machine phase0 phase1 phase2 phase3 idle duration ? 3 16 mhz internal rc oscillator clock cycles vreg and 16 mhz internal rc oscillator stabilization done duration ? 350 16 mhz internal rc oscillator clock cycles duration ???? 16 mhz internal rc oscillator clock cycles flash initialization done duration ?? 40 ? 16 mhz internal rc oscillator clock cycles power-on or enabled ?destructive? reset enabled non-shortened external or ?functional? reset 1 enabled shortened external or ?functional? reset trimming, self-test configuration, and fccu initialization done reset_b released
reset generation module (mc_rgm) 41-22 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? vreg and 16 mhz internal rc oscillator stabilization ? a minimum of 3 16 mhz in ternal rc oscillator clock cycles have elapsed since power-up completion and the last enabled ?destructive? reset event 41.4.1.2 phase1 phase this phase is entered either on exit from phase0 or immediately from phase2 , phase3 , or idle on a non-masked external or ?functiona l? reset event if it has not been configured to trigger a ?short? sequence. the reset state machine exits phase1 and enters phase2 on verification of the following: ? all enabled, non-shortened ?functiona l? resets have been processed ? a minimum of 350 16 mhz in ternal rc oscillator clock cycles have elapsed si nce the last enabled external or non-shortened ?functional? reset event 41.4.1.3 phase2 phase this phase is entered on exit from phase1 . the reset state machine exits phase2 and enters phase3 on verification of the following: ? all processes that need to be done in phase2 are completed ? flash initialization ? a minimum of 8 16 mhz internal rc oscillat or clock cycles have elapsed since entering phase2 41.4.1.4 phase3 phase this phase is a entered either on exit from phase2 or immediately from idle on an enabled, shortened ?functional? reset event. the reset state machine exits phase3 and enters idle on verification of the following: ? all processes that need to be done in phase3 are completed ? trimming, self-test configurat ion, and fccu initialization ? a minimum of 40 16 mhz inte rnal rc oscillator clock cycles have elapsed since the last enabled, shortened ?functional? reset event 41.4.1.5 idle phase this is the final phase a nd is entered on exit from phase3 . when this phase is reached, the mc_rgm releases control of the system to the platform and waits for new reset events that can trigger a reset sequence. the actual mbist and lbist execution is performed during this phase. (see chapter 42, self-test control unit (stcu), and chapter 48, system status and configuration module (sscm). ) 41.4.2 destructive resets a ?destructive? reset indicates that an event has occu rred after which critical re gister or memory content can no longer be guaranteed.
reset generation module (mc_rgm) freescale semiconductor 41-23 pxs20 microcontroller reference manual, rev. 1 the status flag associated with a given ?destructive? reset event ( rgm_des.f_< destructive reset > bit) is set when the ?destructive? reset is asserted an d the power-on reset is not asserted. it is possible for multiple status bits to be set simultaneously, and it is software?s responsibilit y to determine which reset source is the most critical for the application. the device?s low-voltage detector threshold ensures that, when 1.2 v low-voltage detected is enabled, the supply is sufficient to have the de structive event correctly propagated th rough the digital logic. therefore, if a given ?destructive? reset is enabled, the mc_rgm ensures that the associated reset event will be correctly triggered to the full system . however, if the given ?destructive? reset is di sabled and the voltage goes below the digital functional th reshold, functionality can no longer be ensured, and the reset may or may not be asserted. an enabled destructive reset will trigger a reset sequence starting from the beginning of phase0 . 41.4.3 external reset the mc_rgm manages the external reset coming from reset_b . the detection of a falling edge on reset_b will start the reset sequence from the beginning of phase1 . the status flag associated with the external reset falling edge event ( rgm_fes.f_exr bit) is set when the external reset is asserted and the power-on reset is not asserted. the external reset can optionall y be disabled by writing bit rgm_ferd.d_exr . note the rgm_ferd register can be written only once between two power-on reset events. an enabled external reset will normally trigge r a reset sequence starti ng from the beginning of phase1 . nevertheless, the rgm_fess register enables the further configur ing of the reset sequence triggered by the external reset. when rgm_fess.ss_exr is set, the external reset will trigger a reset sequence starting directly from the beginning of phase3 , skipping phase1 and phase2 . this can be useful especially when an external reset should not reset the flash. the mc_rgm may also assert the external reset if the reset sequence was triggered by one of the following: ? a power-on reset ? a ?destructive? reset event ? an external reset event ? a ?functional? reset event configured via the rgm_fbre register to assert the external reset in this case, the external rese t is asserted until the end of phase3 . 41.4.4 functional resets a ?functional? reset indicates that an event has occurr ed after which it can be guaranteed that critical register and memory content is still intact.
reset generation module (mc_rgm) 41-24 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 the status flag associated with a given ?functional? reset event ( rgm_fes.f_< functional reset > bit) is set when the ?functional? reset is asserted and th e power-on reset is not asse rted. it is possible for multiple status bits to be set simultaneously, and it is software?s responsibilit y to determine which reset source is the most critical for the application. the ?functional? reset can be optionally disabled by software writing bit rgm_ferd.d_< functional reset > . note the rgm_ferd register can be written only once between two power-on reset events. an enabled functional reset will normally trigge r a reset sequence starti ng from the beginning of phase1 . nevertheless, the rgm_fess register enables the further c onfiguring of the reset sequence triggered by a functional reset. when rgm_fess.ss_< functional reset > is set, the associated ?functional? reset will trigge r a reset sequence starting dire ctly from the beginning of phase3 , skipping phase1 and phase2 . this can be useful especially in case a functional reset should not reset the flash module. see chapter 32, mode entry module (mc_me) , for details on the drun mode. 41.4.5 alternate event generation the mc_rgm provides alternative events to be genera ted on reset source asserti on. when a reset source is asserted, the mc_rgm normally enters the reset seque nce. alternatively, it is possible for some reset source events to be converted from a reset to either a safe mode request issued to the mc_me or to an interrupt request issued to the core. alternate event selection for a gi ven reset source is made via the rgm_ferd and rgm_fear registers as shown in table 41-11 . the alternate event is cleared by deas serting the source of the request (i .e. at the reset source that caused the alternate request) and also clearing the appropriate rgm_fes status bit. note alternate requests ( safe mode as well as interru pt requests) are generated regardless of whether the system clock is running. table 41-11. mc_rgm alternate event selection rgm_ferd bit value rgm_fear bit value generated event 0 x reset 10 safe mode request 1 1 interrupt request
reset generation module (mc_rgm) freescale semiconductor 41-25 pxs20 microcontroller reference manual, rev. 1 note if a masked ?functional? reset event which is configured to generate a safe mode/interrupt request occurs during phase1 , it is ignored, and the mc_rgm will not send any safe mode /interrupt request to the mc_me. 41.4.6 boot mode capturing the mc_rgm samples pa[4:2] whenever reset_b is asserted until five ir cosc clock cycles before its deassertion edge. the resu lt of the sampling is used at the beginning of reset phase3 for boot mode selection and is retained after reset_b has been deasserted for subse quent boots after reset sequences during which reset_b is not asserted. note in order to ensure that the boot mode is correctly captured, the application needs to apply the valid boot mode value the entire time that reset_b is asserted. note reset_b can be low as a consequence of the internal reset generation. this will force re-sampling of the boot mode pins. (see table 41-10 for details.)
reset generation module (mc_rgm) 41-26 freescale semiconductor pxs20 microcontroller reference manual, rev. 1
self-test control unit (stcu) freescale semiconductor 42-1 pxs20 microcontroller reference manual, rev. 1 chapter 42 self-test control unit (stcu) 42.1 introduction the self-test control unit (stcu) is a component w ithin the overall safety integrity subsystem. the stcu controls the sequencing of the device?s self test before the primary user application starts running (apps sw). the goal of the self te st is to detect physical defects in the digital logic and embedded memories with enough coverage to meet the require d safety integrity level (sil) of the system. the sscm interface is able to write the configuration parameters once af ter one of the trigger events has been detected by the system. the ips interface is mainly able to read the stcu registers after the self-test sequence is over. on cut1, the user-visible purpose of the stcu is to display the results of the self test. 42.1.1 acronyms, abbreviations, and terms table 42-1 contains acronyms, abbreviations, and terms used in this document. table 42-1. acronyms and abbreviated terms term meaning apps sw user applications software bist built-in self test (general term that includes both lbist and mbist) cf critical faults cpu central processing unit fccu fault collection control unit hw hardware in general ips integrated peripheral system bus interface lbist logic built-in self test mbist memory built-in self test mc_rgm reset generation module misr multiple input shift register (for lbist result signatures) ncf non-critical faults sil safety integrity level (industry standard) safety integrity subsystem collection of hardware and software workin g together to implement the required sil sir stay in reset (type of fault) sscm system status and configuration module sw software in general
self-test control unit (stcu) 42-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 42.1.2 the safety integrity subsystem figure 42-1 shows the stcu as a component of the safety integrity subsystem on the device. figure 42-1. the stcu within the safety integrity subsystem integrity sw safety integrity software (a comp onent within the safety integrity subsystem) wdg watchdog timers table 42-1. acronyms and abbreviated terms (continued) term meaning lbist partitions mbist partitions sscm stcu integrity sw fccu mc_rgm stcu reset event nvm component 1 notes: 1 components are the hardware and software that ma ke up a subsystem. events that affect subsystem behavior are also included. description fccu the fault collection control unit collects erro rs and controls the safety state of the device. integrity sw the safety integrity software checks the stcu status before passing control over to apps sw. lbist partitions the set of individual logic block partitions included in the self test mbist partitions the set of individual embedded memory blocks included in the self test mc_rgm reset generation module nvm the flash nonvolatile memory contai ns the initial self-test parameters. sscm the system status and configuration module is the central control for device configuration after reset. stcu the self test control unit manages the device self test. stcu reset event the following reset events trigge r the sscm to activate the stcu: ? power-on reset ? destructive reset ? external reset
self-test control unit (stcu) freescale semiconductor 42-3 pxs20 microcontroller reference manual, rev. 1 when an stcu reset event occurs, the de vice goes through a two-phase boot sequence: 1. self-test phase: see figure 42-2 . 2. functional-reset phase: see figure 42-3 . figure 42-2. boot sequence phase 1: self test sscm nvm read parameters stcu fccu failures done run tests run tests 5 4 6 7 load parameters 3 2 mc_rgm lbist partitions mbist partitions detect status 1 1. after an stcu reset event, the sscm detect s that the device self test has not been run yet. 2. the sscm reads the self-t est parameters from flas h nonvolatile me mory (nvm). 3. the sscm loads the self-test parameters in to the stcu and passe s control over to the stcu. 4. the stcu manages the mbists and updates its internal status. 5. the stcu manages the lbists and updates its internal status. 6. if faults are detected, the stcu re ports the test failures to the fccu. 7. the stcu signals the mc_r gm that the tests are comp lete, and the boot sequence proceeds to the next phase (see figure 42-3 ). stcu reset event note: all steps described in the box above are executed only after (not before) the mc_rgm is in idle phase.
self-test control unit (stcu) 42-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 42-3. boot sequence phase 2: functional reset the functional reset s hown in step 1 of figure 42-3 does not reset the mbist or lbist results. therefore, after mc_rgm passes thr ough phase1, phase2, phase3, and idle, the stcu is still aware of the mbist and lbist status and does not generate a ne w functional reset. it thus allows the sscm to continue. 42.1.3 integrity sw operations the integrity sw should perform opera tions based on the stcu status condi tions after the self test. even if no errors are reported, the integr ity sw should confirm that all mbis t and lbist finished successfully and no further error is flagged. this software confirma tion prevents a fault within the stcu itself from incorrectly indicating that the self test passed. 42.1.3.1 reported errors in the case of reported errors, the integrity sw should: ? read the stcu_lbs flag register to determine which lbists failed. ? read the stcu_lbe flag register to determine which lbists did not finish. ? read the stcu_mbsl and stcu_mbsh flag re gisters to determine which mbists failed. ? read the stcu_mbel and stcu_mbeh flag regi sters to determine which mbists did not finish. ? read the stcu_err register to check whethe r there has been an internal stcu failure. 42.1.3.2 no reported errors in the case of no reported errors, the in tegrity sw should confirm the following: sscm stcu check results 3 reset mc_rgm 1 detect status 2 integrity sw pass control apps sw 4 1. the mc_rgm triggers a functional reset. 2. the sscm detects that the device self test has been run and passe s control over to the cpus. 3. the integrity sw checks the results of the self test. see section 42.1.3, integrity sw operations . 4. if the integrity software check passes, the device can be considered as ok and control can be passed to the apps software (applications).
self-test control unit (stcu) freescale semiconductor 42-5 pxs20 microcontroller reference manual, rev. 1 ? the signature registers of each of the lbist re sults match their corresponding expected values: for each lbist: ? read the stcu_lbmisrel/h and stcu_lbi st_nmisrrl/h registers to check the coherency with the stcu_lbs and stcu_lbe bits. ? read the registers described in section 42.1.3.1, reported errors, and verify that their values are as expected. 42.2 stcu main features the stcu features include the following: ? performs a one-time self test after an stcu reset event ? provides register interfaces for both software and hardware: ? hardware: sscm write-one -time register interface ? software: ips register interface ? manages lbists ? manages mbists (embedded memory blocks) ? performs self-checking: the self checker monitors critical internal signa ls during the self test. ? provides a rich set of st atus and error information: ? timeout flags if the self test does not star t or finish within a limited amount of time ? status flags for individual lbist and mbist operations ? flags for stcu internal errors ? software can confirm the integr ity of the lbist status inform ation by directly comparing the expected and actual resu lts the lbist operations. 42.3 block diagram and components figure 42-4 shows a block diagram of the stcu. figure 42-4. stcu block diagram ips interface lbist engine mbist engine collector watchdog timers registers sscm read parameters load parameters stcu check results fccu failures sscm interface run tests run tests lbist partitions mbist partitions functional reset done mc_rgm nvm detect status stcu reset event integrity sw
self-test control unit (stcu) 42-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 the main components of the stcu are: ? registers : hold the self-test parameters and status flags: scheduling ac tivity, lbist setup, critical/non-critical/stay- in-reset fault mapping, misr expected values. see section 42.4, memory map and register definition . the ips and sscm interfaces provide access: ? sscm interface ?the sscm uses this interface to progr am the stcu?s self-test parameters without cpu intervention. a write-once mechanism disables the sscm interface to prevent the stcu parameters from being reloaded af ter the self test has been performed. ? ips interface ?software running on the cpus use this slave bus to access registers. ? collector : collects and updates the status and error c onditions related to the l/mbist execution and stcu internal operation. the collector sends the bist error information to the fccu and signals the mc_rgm to begin a functional reset. ? watchdog timers: provide a double functionality to: ? protect against dead-lock or ru naway condition during the self test ? verify that each l/mbist has been comp leted in its assigne d l/mbist time slot ? lbist engine : manages the testing of logic blocks on the device. ? mbist engine : manages the testing of embedded memory blocks. 42.4 memory map and register definition all registers shown in this section are defined as visible by the ips interface. the stcu contains registers for: ? bist status reporting (finished, successfull) ? stcu status reporting (internal errors) ? bypassing selftest mode ? key registers used to clear error flags 42.4.1 memory map the stcu memory map is listed in table 42-2 . for lbist partitioning, see section 42.5, lbist partitioning.
self-test control unit (stcu) freescale semiconductor 42-7 pxs20 microcontroller reference manual, rev. 1 table 42-2. stcu register map offset from stcu_base (0xc3ff_4000) 1 notes: 1 n is a variable representing the repeated regist er blocks of the multiple lbists and mbists: n ranges from 0 to 2. register name access 2 2 in this column, r/w = read/write, r = read-only, and w = write-only. location 0x0000?0x0004 reserved 0x0008 (cut1) reserved 0x0008 (cut2/3) stcu sk code register (stcu_skc) w on page 42-8 0x000c (cut1) stcu configuration register (stcu_cfg) r on page 42-9 0x000c (cut2/3) reserved 0x0010?0x0018 reserved 0x001c stcu error register (stcu_err) r [cut1] r/w [cut2/3] on page 42-9 0x0020 (cut1) reserved 0x0020 (cut2/3) stcu error key register (stcu_errk) w on page 42-11 0x0024 stcu lbist status register (stcu_lbs) r on page 42-12 0x0028 stcu lbist end flag register (stcu_lbe) r on page 42-13 0x002c?0x0038 reserved 0x003c stcu mbist status lo w register (stcu_mbsl) r on page 42-13 0x0040 stcu mbist status hi gh register (stcu_mbsh) r on page 42-14 0x0044 stcu mbist end flag low register (stcu_mbel) r on page 42-15 0x0048 stcu mbist end flag high register (stcu_mbeh)cut2/3 r on page 42-15 0x004c?0x0084 reserved 0x0088 (cut1) reserved 0x0088 + ( n 0x20) (cut2/3) stcu lbist misr expected low register (stcu_lb_misrel) r on page 42-16 0x008c (cut1) reserved 0x008c + ( n 0x20) (cut2/3) stcu lbist misr expected high register (stcu_lb_misreh) r on page 42-17 0x0090 + ( n 0x20) stcu lbist misr read low register (stcu_lb_misrrl) r on page 42-17 0x0094 + ( n 0x20) stcu lbist misr read high register (stcu_lb_misrrh) r on page 42-18 0x0098?0x7fff reserved
self-test control unit (stcu) 42-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 42.4.2 register conventions the following bus operations (cont iguous byte enables) are supported: ? word (32 bits) data read operations ? word (32 bits) data write operat ion for write-enabled registers the registers of the stcu are accessi ble in each access mode: user or su pervisor. reading and writing to reserved areas results in unexpected behavior. 42.4.3 detailed register descriptions 42.4.3.1 stcu sk code regist er (stcu_skc) [cut2/3 only] the stcu_skc register implements the security key code mechanism n eeded to access in write mode to the other stcu registers. in orde r to unlock the stcu access after: ? the power-on, destructive or external reset ? the completation of the stcu run the sw (ips bus) or the sscm interfaces have to apply the following sequence: ? write the key1 into the stcu_skc register ? write the key2 into the stcu_skc register after the self-test sequence has been completed or th e bypass feature has been enabled ( setting the bit byp into the stcu_cfg), the sscm interface is no longer available. in case of invalid access or sequence (k ey1/2 have to be applied consecuti vely), a transfer error on the ips or sscm bus is asserted depending on the selected source. the stcu wr ite access is locked and to unlock the access the sequence has to be applied again. in case the stcu register access last more cycles than the one define d into the hard-coded wdg time-out, the stcu write access is locked and the wdg and register itf clocks are switched off. also in this case, in order to enable again the write access to the stcu and the wdg and register itf clocks, it is required to apply again the sequence. the stcu_skc register is not r eadable. the value 0x00000000 is always returned in case of a read operation.
self-test control unit (stcu) freescale semiconductor 42-9 pxs20 microcontroller reference manual, rev. 1 42.4.3.2 stcu configuration regi ster (stcu_cfg) [cut1 only] the stcu_cfg register includes th e global configuration of the stcu. 42.4.3.3 stcu error re gister (stcu_err) the stcu_err register includes the status flags for the stcu internal error conditions that occurred during the configuration or the self test. the stcu_err fields can be cleared by softwa re depending on the applied unlocked sequence: address: base + 0x0008 (cut2/3 only) access: user write-only 0123456789101112131415 r w skc[31:16] reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r w skc[15:0] reset0000000000000000 figure 42-5. stcu sk code register (stcu_skc) [cut2/3 only] table 42-3. stcu_skc field descriptions field description skc skc: stcu security key code = 0xabfc1893: key1 to unlock the write access the stcu (when not protected) = 0x319a6c2f: key2 to unlock the write access the stcu (when not protected) address: base + 0x000c [cut1 only] access: user read-only 0123456789101112131415 r 0 0000 0 00 0000 0 000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 000000byp 0000 0000 w reset0000000000000000 figure 42-6. stcu configuration register (stcu_cfg) [cut1 only] table 42-4. stcu_cfg field descriptions field description byp bypass mode 0: stcu is active. 1: stcu is in bypass mode. the self test is bypassed.
self-test control unit (stcu) 42-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? write the keys into the stcu_errk ? set/clear the stcu_err register where ? key1 allows to clear the fields that have a value of 1 by writing a 0 to those fields ? key2 allows to set the fields that have a value of 0 by writing a 1 to those fields in case of invalid access (wr ong or missing key), a transfer error is asserted (it depends on the selected bus interface) and the writing operati on on stcu_err register is ignored. address: base + 0x001c access: user read-only 0123456789101112131415 r 0 000 0 000 0000 0 000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0000 cfsf ncfsf sirsf 0000 wdto 0 enge invp w reset0000000000000000 figure 42-7. stcu error regi ster (stcu_err) for cut1 address: base + 0x001c access: user read-only 0123456789101112131415 r 0 000 0 000 0000 0 000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0000 cfsf ncfsf 0 0000 wdto 0 enge invp w reset0000000000000000 figure 42-8. stcu error register (stcu_err) for cut2/3
self-test control unit (stcu) freescale semiconductor 42-11 pxs20 microcontroller reference manual, rev. 1 42.4.3.4 stcu error key register (stcu_errk) [cut2/3 only] the stcu_errk register, available on cut2/3 only, im plements the security key code to access to the stcu_err register. in order to write the stcu_err register, software must: ? write the keyx into the stcu_errk ? set/clear the stcu_err register wher:e ? key1 allows to clear the bit at 1 ? key2 allows to set the bit at 0 in case of invalid access, a transfer error on the ips or sscm bus is asserted (i t depends on the selected bus interface) and the key is cleared. to unlock the set/clear operation on the stcu_err register the key1 or key2 has to be applied again. only one access mode (set/clear) at the time is allowed. the la st key written into this register defines the access mode. in case the stcu register access last more cycles than the one defined into the hard-coded watchdog time-out or there is a transfer error or the ips or sscm bus operati on performed just after the key1/key2 table 42-5. stcu_err field descriptions field description cfsf critical faults status flag this flag reports the global status of the cf. 0: no errors that trigger the cf condition occurred. 1: at least one error that triggers the cf condition occurred. ncfsf non critical faults status flag 0: no errors that trigger the ncf condition occurred. 1: at least one error that triggers the ncf condition occurred. sirsf (cut1) stay in reset faults status flag 0: no errors which trigger the sir condition 1: there are errors which trigger the sir condition in the typical condition, it should not be possible to read the content of this re gister when this bit is set because the system should be permanently under re set. however, for diagnostic purposes, the system could exit from reset to allow sw to check the flag and attempt to trace the failure. wdto watchdog timeout 0: the self test completed within the assigned watchdog time. 1: the self test did not complete within the assigned watchdog time. this bit is also set when the stcu is activated but the self test is not run. enge engine error 0: valid engine execution 1: invalid engine execution. invp invalid pointer 0: valid linked pointer list 1: invalid linked pointer list. the following conditions set this bit: ? initial lbist or mbist pointer is out of range ? lbist is selected when mbist is concurrently running or vice versa ? error in the lbist/mbist linking (e xecution generates an infinite loop)
self-test control unit (stcu) 42-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 keys has been written into stcu_errk is not a writ e operation into the stcu_err register, the key is cleared. the stcu_errk register is not readable. the valu e 00000000h is always returned in case of a read operation. 42.4.3.5 stcu lbist status register (stcu_lbs) the stcu_lbs register includes the results corr esponding to the execution of each lbist. the stcu_lbs register is automatically set following the completion of the lbist run. address: base + 0x0020 access: user write-only 0123456789101112131415 r w err_sk[31:16] reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r w err_sk[15:0] reset0000000000000000 figure 42-9. stcu error key regist er (stcu_errk) [cut2/3 only] table 42-6. stcu_errk field descriptions field description err_sk stcu_errk security key 0xf175_9034: key1 to reset the stcu_err bits at 1 0x9531_b0c6: key2 to set the stcu_err bits at 0 address: base + 0x0024 access: user read/write 0123456789101112131415 r 0 000 0 00 0 0000 0 000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 000000 0 00000lbs2lbs1lbs0 w reset0000000000000000 figure 42-10. stcu lbist status register (stcu_lbs) table 42-7. stcu_lbs field descriptions field description lbsx lbist status 0: failed lbist execution 1: no fault detected during the bist execution
self-test control unit (stcu) freescale semiconductor 42-13 pxs20 microcontroller reference manual, rev. 1 note a bist counts as successfull when no fault was detected during execution (see lbs) and its execution is finished (see lbe). note the status of lbist4 is refl ected in (mapped onto) lbs2. 42.4.3.6 stcu lbist end fl ag register (stcu_lbe) the stcu_lbe register includes the end flag relate d to the execution of each lbist. the stcu_lbe register is automatically updated foll owing the completion of the lbist run. note a bist counts as successfull when no fault was detected during execution (see lbs) and its execution is finished (see lbe). note the status of lbist4 is refl ected in (mapped onto) lbe2. 42.4.3.7 stcu mbist status low register (stcu_mbsl) the stcu_mbsl register includes the results corr esponding to the execution of each mbist. the stcu_mbsl register is auto matically set following the completion of the mbist run. address: base + 0x0028 access: user read-only 0123456789101112131415 r 0 000 0 00 0 0000 0 000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 000000 0 00000lbe2lbe1lbe0 w reset0000000000000000 figure 42-11. stcu lbist end flag register (stcu_lbe) table 42-8. stcu_lbe field descriptions field description lbex lbist end status 0: lbist execution is not finished. 1: lbist execution is finished.
self-test control unit (stcu) 42-14 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 note a bist counts as successfull when no fault was detected during execution (see mbsl, mbsh) and its execution is finished (see mbel, mbeh). 42.4.3.8 stcu mbist status high register (stcu_mbsh) the stcu_mbsh register includes the results corr esponding to the executi on of each mbist. the stcu_mbsh register is automatically set following the completion of the mbist run. address: base + 0x003c access: user read-only 0123456789101112131415 rmbs 31 mbs 30 mbs 29 mbs 28 mbs 27 mbs 26 mbs 25 mbs 24 mbs 23 mbs 22 mbs 21 mbs 20 mbs 19 mbs 18 mbs 17 mbs 16 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rmbs 15 mbs 14 mbs 13 mbs 12 mbs 11 mbs 10 mbs 9 mbs 8 mbs 7 mbs 6 mbs 5 mbs 4 mbs 3 mbs 2 mbs 1 mbs 0 w reset0000000000000000 figure 42-12. stcu mbist status low register (stcu_mbsl) table 42-9. stcu_mbsl field descriptions field description bits 0:31 mbsx: mbist status 0: failed mbist execution 1: no fault detected during the bist execution address: base + 0x0040 access: user read/write 0123456789101112131415 r 0 000 0 00 0 0000 0 000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 000000 0 00000 mbs 34 mbs 33 mbs 32 w reset0000000000000000 figure 42-13. stcu mbist status high register (stcu_mbsh)
self-test control unit (stcu) freescale semiconductor 42-15 pxs20 microcontroller reference manual, rev. 1 note a bist counts as successfull when no fault was detected during execution (see mbsl, mbsh) and its execution is finished (see mbel, mbeh). 42.4.3.9 stcu mbist end flag low register (stcu_mbel) the stcu_mbel register includes the end flag related to the execution of each mbist. the stcu_mbel register is automatically updated following the completion of the mbist run. note a bist counts as successfull when no fault was detected during execution (see mbsl, mbsh) and its execution is finished (see mbel, mbeh). 42.4.3.10 stcu mbist end flag high register (stcu_mbeh) the stcu_mbeh register includes the end flag re lated to the execution of each mbist. the stcu_mbeh register is automatically updated following the completion of the mbist run. table 42-10. stcu_mbsh field descriptions field description mbsx mbist status 0: failed mbist execution 1: no fault detected during the bist execution address: base + 0x0044 access: user read-only 0123456789101112131415 rmbe 31 mbe 30 mbe 29 mbe 28 mbe 27 mbe 26 mbe 25 mbe 24 mbe 23 mbe 22 mbe 21 mbe 20 mbe 19 mbe 18 mbe 17 mbe 16 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rmbe 15 mbe 14 mbe 13 mbe 12 mbe 11 mbe 10 mbe 9 mbe 8 mbe 7 mbe 6 mbe 5 mbe 4 mbe 3 mbe 2 mbe 1 mbe 0 w reset0000000000000000 figure 42-14. stcu mbist end flag low register (stcu_mbel) table 42-11. stcu_mbel field descriptions field description mbex : mbist end status 0: mbist execution is not finished. 1: mbist execution is finished.
self-test control unit (stcu) 42-16 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 note a bist counts as successfull when no fault was detected during execution (see mbsl, mbsh) and its execution is finished (see mbel, mbeh). 42.4.3.11 stcu lbist misr expected lo w register (stcu_lb_misrel) [cut2/3 only] the stcu_lb_misrel register define s the lsb part of the expected misr of each lbist controller. address: base + 0x0048 access: user read-only 0123456789101112131415 r 0 000 0 00 0 0000 0 000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 000000 0 00000 mbe 34 mbe 33 mbe 32 w reset0000000000000000 figure 42-15. stcu mbist end flag high register (stcu_mbeh) table 42-12. stcu_mbeh field descriptions field description bits 0:28 reserved these are reserved bits. these bits are always read as ?0? and must always be written with ?0?. bits 29:31 mbex: mbist end status 0: mbist execution is not finished. 1: mbist execution is finished. address: base + 0x0088 + ( n 0x20) 1 [cut2/3 only] notes: 1 the n variable represents the repeated regi ster blocks of the multiple lbists: n ranges from 0 up to 2. access: user read 0123456789101112131415 r misrel[31:16] w reset1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r misrel[15:0] w reset1111111111111111 figure 42-16. stcu lbist misr expected low register (stcu_lb_misrel) [cut2/3 only]
self-test control unit (stcu) freescale semiconductor 42-17 pxs20 microcontroller reference manual, rev. 1 42.4.3.12 stcu lbist misr expected hi gh register (stcu_lb_misreh) [cut2/3 only] the stcu_lb_misreh register defi nes the msb part of the expected misr of each lb ist controller. 42.4.3.13 stcu lbist misr read low register (stcu_lb_misrrl) the stcu_lb_misrrl registers report the lsb part of the misr obtained at the end of each lbist. table 42-13. stcu_lb_misrel field descriptions field description misrel misr expected low part misrel defines the low part of the expected misr. address: base + 0x008c + ( n 0x20) 1 [cut2/3 only] notes: 1 the n variable represents the repeated regi ster blocks of the multiple lbists: n ranges from 0 up to 2. access: user read 0123456789101112131415 r misreh[31:16] w reset1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r misreh[15:0] w reset1111111111111111 figure 42-17. stcu lbist misr expected high register (stcu_lb_misreh) [cut2/3 only] table 42-14. stcu_lb_misreh field descriptions field description misreh misr expected high part misreh defines the high par t of the expected misr. address: base + 0x0090 + ( n 0x20) 1 notes: 1 the n variable represents the repeated regi ster blocks of the multiple lbists: n ranges from 0 up to 2. access: user read/write 0123456789101112131415 rmisrrl w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rmisrrl w reset0000000000000000 figure 42-18. stcu lbist misr read low register (stcu_lb_misrrl)
self-test control unit (stcu) 42-18 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 42.4.3.14 stcu lbist misr read high register (stcu_lb_misrrh) the stcu_lb_misrrh registers repo rt the msb part of the misr obt ained at the end of each lbist. 42.5 lbist partitioning the lbist partitioning scheme for cut1 a nd cut2/3 of this device is shown in table 42-17 and table 42-18 , respectively. table 42-15. stcu_lb_misrrl field descriptions field description bits 0:31 misrrl: misr read low part contains the low word of the misr obtained at the end of the lbist address: base + 0x0094 + ( n 0x20) 1 notes: 1 the n variable represents the repeated regi ster blocks of the multiple lbists: n ranges from 0 up to 2. access: user read-only 0123456789101112131415 r misrrh w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r misrrh w reset0000000000000000 figure 42-19. stcu lbist misr read high register (stcu_lb_misrrh) table 42-16. stcu_lb_misrrh field descriptions field description bits 0:31 misrrh: misr read high part contains the high word of the misr obtained at the end of the lbist
self-test control unit (stcu) freescale semiconductor 42-19 pxs20 microcontroller reference manual, rev. 1 table 42-17. lbist partitioning for cut1 lbist partition module 0 core_0 axbs_0 mpu_0 aips_0 aips_0 off-platform read mux aips_0 on-platform read mux pflashc_0 sramc_0 dma_0 dmachmux_0 stm_0 swt_0 intc_0 ecsm_0 sema4_0 cache parity propagation_0 tsens_0 sramc_0 read mux
self-test control unit (stcu) 42-20 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 1 core_1 xbar_1 mpu_1 aips_1 pbridge_1 off-platform read mux pbridge_1 on-platform read mux pflashc_1 sramc_1 edma_1 dmachmux_1 stm_1 swt_1 intc_1 ecsm_1 sema4_1 cache parity propagation_1 tsens_1 sramc_1 read mux 2flexpwm_0 etimer_0 adc_0 ctu 3flexpwm_1 etimer_1 adc_1 4sscm table 42-17. lbist partitioning for cut1 (continued) lbist partition module
self-test control unit (stcu) freescale semiconductor 42-21 pxs20 microcontroller reference manual, rev. 1 table 42-18. lbist partitioning for cut2/3 lbist partition module 0 core_0 xbar_0 mpu_0 pbridge_0 pflashc_0 sramc_0 dma_0 dmachmux_0 stm_0 swt_0 intc_0 ecsm_0 sema4_0 tsens_0 flexpwm_0 etimer_0 adc_0 ctu 1 core_1 axbs_1 mpu_1 aips_1 pflashc_1 sramc_1 dma_1 dmachmux_1 stm_1 swt_1 intc_1 ecsm_1 sema4_1 tsens_1 flexpwm_1 etimer_1 adc_1
self-test control unit (stcu) 42-22 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 42.6 mbist partitioning 4 rccu5?0 wkpu linflexd_0 linflexd_1 etimer_2 dspi_0 dspi_1 dspi_2 flexray pit flexcan_0 flexcan_1 crc cmu_1 cmu_2 fmpll_0 fmpll_1 siul swg npc mc_me mc_pcu flash fccu iomux table 42-19. mbist partitioning mbist type module 0 sram system ram (128 kb plus ecc) 1 sram system ram (128 kb plus ecc) 2 sram system ram (128 kb plus ecc) 3 sram system ram (128 kb plus ecc) 4 sram system ram (128 kb plus ecc) table 42-18. lbist partitioning for cut2/3 (continued) lbist partition module
self-test control unit (stcu) freescale semiconductor 42-23 pxs20 microcontroller reference manual, rev. 1 42.7 self-test bypass and mbist-only mode the default stcu configuration as it is located in the test flash memory leads to a full self-test after an stcu reset event (running all mbists and lbists). besides this, two confi gurations are available: 5 sram system ram (128 kb plus ecc) 6 sram system ram (128 kb plus ecc) 7 sram system ram (128 kb plus ecc) 8 sram platform i-cache, sor 0 9 sram platform i-cache, sor 0 10 sram platform i-cache, sor 0 11 sram platform i-cache, sor 0 12 sram platform cache tag, sor 0 13 sram platform cache tag, sor 0 14 sram platform cache tag, sor 0 15 sram platform cache tag, sor 0 16 sram dma memory, sor 0 17 sram platform i-cache, sor 1 18 sram platform i-cache, sor 1 19 sram platform i-cache, sor 1 20 sram platform i-cache, sor 1 21 sram platform cache tag, sor 1 22 sram platform cache tag, sor 1 23 sram platform cache tag, sor 1 24 sram platform cache tag, sor 1 25 sram dma memory, sor 1 26 sram flexcan rx buffer, rxim_ram 27 sram flexcan rx buffer, rxim_ram 28 sram flexcan tx buffer, mb_ram 29 sram flexcan tx buffer, mb_ram 30 sram flexray lut 31 sram flexray lut 32 sram flexray data table 33 rom flexray rom 34 rom bam rom table 42-19. mbist partitioning (continued) mbist type module
self-test control unit (stcu) 42-24 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? bypass self-test mode (dis abling the whole self-test) ? mbist-only mode (d isabling all lbists) to configure those cases, a specific hexadecimal code needs to be adde d to the shadow flash memory. this code will be provided in a fu ture revision of this documen t or through application notes.
semaphore unit (sema4) freescale semiconductor 43-1 pxs20 microcontroller reference manual, rev. 1 chapter 43 semaphore unit (sema4) 43.1 introduction pxs20 contains two sema4 units. in a dual-processor chip, semaphores are used to let each processor know who has control of common memory. before a core can update or read memory coherently , it has to check the semaphore to see if the other core is not already updating the memory. if the semaphore is clear, it can write common memory, but if it is set, it has to wait for the othe r core to finish and clear the semaphore. the semaphore unit (sema4) provides the hardware support needed in multi-core systems for implementing semaphores and provide a simple mechan ism to achieve lock/unloc k operations via a single write access. this approach elimin ates architecture-speci fic implementations like atomic (indivisible) read-modify-write instructions or reservation mechanisms. the result is an architecture-neutral solution that provides hardware-enforced gate s as well as other useful system functions related to the gating mechanisms. on pxs20, the sema4 unit is intended for use when us ing the device in dual processor mode. when using the device in lock step mode, the sema4 unit is disabled and its interr upt sources deasserted. in this chapter, the two instantiations of the e200z4d core on pxs20 are re ferred to as e200z4d_0 and e200z4d_1. (the e200z4d_0 instan tiation runs from reset in dual processor mode.) 43.1.1 block diagram figure 43-1 is a simplified block diagram of the sema 4 unit that illustrates the functionality and interdependence of major blocks. in the diagram, the register blocks name d gate0, gate1, ..., gate 15 include the finite state machines implementing the semaphore gates plus the interrupt notification logic.
semaphore unit (sema4) 43-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 43-1. sema4 block diagram 43.1.2 features the sema4 unit implements hardware -enforced semaphores as a periphe ral device and has these major features: ? support for 16 hardware-enforced gates in a dual-processor configuration ? each hardware gate appears as a three-state, 2-bi t state machine, with all 16 gates mapped as an array of bytes ? three-state implementation ? if gate = 0b00, then state = unlocked ? if gate = 0b01, then state = locked by e200z4d_0 (master id = 0) ips_wdata ips_addr decode mux ips bus 31 0 control ips_rdata 31 0 aips_master 2 0 = = master_eq_cp{0,1} gate0 gate1 gate2 gate3 gate12 gate13 gate14 gate15 = = wdata_eq_{unlock, cp[0-1]_lock} = cp0_semaphore_int cp1_semaphore_int
semaphore unit (sema4) freescale semiconductor 43-3 pxs20 microcontroller reference manual, rev. 1 ? if gate = 0b10, then state = locked by e200z4d_1 (master id = 1) ? uses the bus master id number as a reference at tribute plus the specif ied data patterns to validate all write operations ? after it is locked, the gate must be unlocked by a write of zeroes from the locking processor ? optionally enabled interrupt notific ation after a failed lock write provides a mechanism to indicate the gate is unlocked ? secure reset mechanisms are supported to clear the contents of individual semaphore gates or notification logic, a nd clear_all capability note semaphore gates that are locked when entering sleep mode are cleared by the internal reset generate d when exiting sleep mode. 43.1.3 modes of operation the sema4 unit does not support a ny special modes of operation. 43.2 signal description the sema4 unit does not include any external signals. 43.3 memory map and register description the sema4 programming model map is shown in table 43-1 . the address of each register is given as an offset to the sema4 base address. registers are listed in address orde r, identified by complete name and mnemonic, and list the type of accesses allowed. table 43-1. sema4 memory map address offset register location 0x0000 sema4_gate00?semaphores gate 0 on page 43-4 0x0001 sema4_gate01?semaphores gate 1 on page 43-4 0x0002 sema4_gate02?semaphores gate 2 on page 43-4 0x0003 sema4_gate03?semaphores gate 3 on page 43-4 0x0004 sema4_gate04?semaphores gate 4 on page 43-4 0x0005 sema4_gate05?semaphores gate 5 on page 43-4 0x0006 sema4_gate06?semaphores gate 6 on page 43-4 0x0007 sema4_gate07?semaphores gate 7 on page 43-4 0x0008 sema4_gate08?semaphores gate 8 on page 43-4 0x0009 sema4_gate09?semaphores gate 9 on page 43-4 0x000a sema4_gate10?semaphores gate 10 on page 43-4 0x000b sema4_gate11?semaphores gate 11 on page 43-4 0x000c sema4_gate12?semaphores gate 12 on page 43-4
semaphore unit (sema4) 43-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 43.3.1 semaphores gate n register (sema4_gate n ) each semaphore gate is implemented in a 2-bit finite state machine, right-j ustified in a byte data structure. the hardware uses the bus master num ber in conjunction with the data pa tterns to validate all attempted write operations. only processor bus masters can modify th e gate registers. after it is locked, a gate must be opened (unlocked) by the locking processor core. multiple gate values can be read in a single access, but only a single gate at a time can be updated via a write operation. 16- and 32-bit writes to multiple gate s are allowed, but the writ e data operand must update the state of a single gate only. a byte write data value of 0x03 is de fined as no operation and does not affect the state of the corresponding gate register. attempts to write multiple gates in a single-aligned access with a size larger than an 8-bit (byte) reference generate an error termination and do not allow any gate state changes. figure 43-2. sema4 gate n register (sema4_gate n ) 0x000d sema4_gate13?semaphores gate 13 on page 43-4 0x000e sema4_gate14?semaphores gate 14 on page 43-4 0x000f sema4_gate15?semaphores gate 15 on page 43-4 0x0010?0x003f reserved 00x040 sema4_cp0ine?semaphores cp0 irq notification enable on page 43-5 0x0042?0x0047 reserved 0x0048 sema4_cp1ine?semaphores cp1 irq notification enable on page 43-5 0x004a?0x07f reserved 0x0080 sema4_cp0ntf?semaphor es cp0 irq notification on page 43-5 0x008 2?00x087 reserved 0x0088 sema4_cp1ntf?semaphor es cp1 irq notification on page 43-5 0x008a?0x00ff reserved 0x0100 sema4_rstgt?semaphores reset gate on page 43-6 0x0102 reserved 0x0104 sema4_rstntf?semaphores reset irq notification on page 43-8 0x0106?0x3fff reserved offset: n ( n = 0x0, 0x1,0x2,..., 0xf) access: user read/write 01234567 r 0 0 0 000 gtfsm w reset00000000 table 43-1. sema4 memory map (continued) address offset register location
semaphore unit (sema4) freescale semiconductor 43-5 pxs20 microcontroller reference manual, rev. 1 43.3.2 semaphores processor n irq notification enable (sema4_cp{0,1}ine) the application of a hardware se maphore module provides an opportunity for implementation of helpful system-level features. an ex ample is an optional mechanism to genera te a processor interru pt after a failed lock attempt. traditional software gate functions exec ute a spin-wait loop in an effort to obtain and lock the referenced gate. with this module, the processor that fails in the lock attempt could continue with other tasks and allow a properly-enabled notification interrupt to return its execution to the original lock function. the optional notification inte rrupt function consists of two register s for each processor: an interrupt notification enable register (sema4_cp n ine) and the interrupt re quest register (sema4_cp n ntf). to support implementations with more than 16 gates, these registers can be referenced with aligned 16- or 32-bit accesses. for the sema4_cp n ine registers, unimplemented bits read as zeroes and writes are ignored. figure 43-3. semaphores processor n irq notification enable (sema4_cp{0,1}ine) 43.3.3 semaphores processor n irq notification (sema4_cp{0,1}ntf) the notification interrupt is generated via a unique fi nite state machine, one per hardware gate. this machine operates in the following manner: table 43-2. sema4_gate n field descriptions field description gtfsm gate finite state machine. the hardware gate is maintained in a three-state implementation, defined as: 00 the gate is unlocked (free). 01 the gate has been locked by processor 0. 10 the gate has been locked by processor 1. 11 this state encoding is never used and therefore reserved. attempted writes of 0x03 are treated as no operation and do not affect the gate state machine. note: the state of the gate reflects t he last processor that locked it, which can be useful during system debug. offset: 0x0040 (sema4_cp0ine) 0x0048 (sema4_cp1ine) access: user read/write 0123456789101112131415 r ine0 ine1 ine2 ine3 ine4 ine5 ine6 ine7 ine8 ine9 ine1 0 ine1 1 ine1 2 ine1 3 ine1 4 ine1 5 w reset0000000000000000 table 43-3. sema4_cp{0,1}ntf field descriptions field description ine n interrupt request notification enable n . this field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate n . 0 the generation of the notification interrupt is disabled. 1 the generation of the notification interrupt is enabled.
semaphore unit (sema4) 43-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? when an attempted lock fails, the fsm enters a first state where it waits until the gate is unlocked. ? after it is unlocked, the fsm enters a second stat e where it generates an interrupt request to the failed lock processor. ? when the failed lock processor succeeds in locki ng the gate, the irq is automatically negated and the fsm returns to the idle state. however, if the other processor locks the gate again, the fsm returns to the first state, negates the interrupt re quest, and waits for the gate to be unlocked again. the notification interrupt request is implemented in a 3-bit, five-state machine, where two specific states are encoded and program-visible as sema4_cp0ntf[gn n ] and sema4_cp1ntf[gn n ]. figure 43-4. semaphores processor n irq notification (sema4_cp{0,1}ntf) 43.3.4 semaphores (secure) reset gate n (sema4_rstgt) although the intent of the hardware gate implementation specifies a prot ocol where the locking processor must unlock the gate, it is recognized that system operation may require a reset function to re-initialize the state of any gate(s) without requiring a system-level reset. to support this special gate re set requirement, the sema4 unit impl ements a secure reset mechanism which allows a hardware gate (or all the gates) to be initialized by following a specific dual-write access pattern. using a technique similar to that required for the servicing of a so ftware watchdog timer, the secure gate reset requires two consecutive writes with predefined da ta patterns from the same processor to force the clearing of the specified ga te(s). the required access pattern is: 1. a processor performs a 16-bit write to the se ma4_rstgt memory location. the most significant byte (sema4_rstgt[rstgdp]) must be 0xe2; the least significant byte is a ?don?t care? for this reference. 2. the same processor then perfor ms a second 16-bit write to th e sema4_rstgt lo cation. for this write, the upper byte (sema4_rstgt[rstgdp]) is the logical complement of the first data pattern (0x1d) and the lower byte (sema4_rstgt[rstgtn]) specifies the gate(s) to be reset. this gate field can specify a single gate be cleared or that all gates are cleared. offset: 0x0080 (sema4_cp0ntf) 0x0088 (sema4_cp1ntf) access: user read-only 0123456789101112131415 r gn0 gn1 gn2 gn3 gn4 gn5 gn6 gn7 gn8 gn9 gn1 0 gn1 1 gn1 2 gn1 3 gn1 4 gn1 5 w reset0000000000000000 table 43-4. sema4_cp{0,1}ntf field descriptions field description gn n gate n notification. this read-only field is a bitmap of the interrupt request notification from a failed attempt to lock gate n . 0 no notification interrupt generated. 1 notification interrupt generated.
semaphore unit (sema4) freescale semiconductor 43-7 pxs20 microcontroller reference manual, rev. 1 3. reads of the sema4_rstgt location return information on the 2-bit state machine (sema4_rstgt[rstgsm]) which implements this function, the bus master performing the reset (sema4_rstgt[rstgms]) and th e gate number(s) last cleared (sema4_rstgt[rstgtn]). reads of the sema4_rst gt register do not affe ct the secure reset finite state machine in any manner. figure 43-5. semaphores (secure) reset gate n (sema4_rstgt) offset: 0x0100 (sema4_rstgt ) access: user read/write 0123456789101112131415 r 0 0 rstgsm 0 rstgms rstgtn wrstgdp reset0000000000000000
semaphore unit (sema4) 43-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 43.3.5 semaphores (secure) reset irq notification (sema4_rstntf) as with the case of the secure rese t function and the hardware gates, it is recognized that system operation may require a reset function to re-initialize the st ate of the irq notificati on logic without requiring a system-level reset. to support this special notificat ion reset requirement, the sema4 unit implements a secure reset mechanism which allows an irq notification (or all the notifications) to be initialized by following a specific dual-write access pattern. wh en successful, the specified irq notification state machine(s) are reset. using a technique si milar to that required for the servicing of a software watchdog timer, the secure table 43-5. sema4_rstgt field descriptions field description rstgsm reset gate finite state mach ine. the reset state machine is maintained in a 2-bit, three-state implementation, defined as: 00 idle, waiting for the first data pattern write. 01 waiting for the second data pattern write. 10 the 2-write sequence has completed. generate th e specified gate reset(s). after the reset is performed, this machine returns to the idle (waiting for first data pattern write) state. 11 this state encoding is never used and therefore reserved. reads of the sema4_rstgt regist er return the encod ed state machine value. note the rstgsm = 0b10 state is valid for a single machine cycle only, so it is impossible for a read to return this value. rstgms reset gate bus master. this 3-bit read-only field records the logical number of the bus master performing the gate reset function. the reset function requires that the two consecutive writes to this register be initiated by the same bus master to succeed. this field is updated each time a write to this register occurs. rstgtn reset gate number. this 8-bit field specifies the specific hardware gate to be reset. this field is updated by the second write. if rstgtn < 64, then reset the single gate defined by rstgtn, else reset all the gates . the corresponding secure irq notification state machine(s) are also reset. rstgdp reset gate data pattern. this write-only field is accessed with the specified data patterns on the two consecutive writes to enable the gate reset mechanism. for the first write, rstgdp = 0xe2 while the second write requires rstgdp = 0x1d. master master id e200z4d_0 0 e200z4d_1 1 edma 2 flexray 3 ?4 ?5 ?6 ?7
semaphore unit (sema4) freescale semiconductor 43-9 pxs20 microcontroller reference manual, rev. 1 reset mechanism requires two consecutive writes with predefined data patterns from the same processor to force the clearing of the irq notifi cation(s). the required access pattern is: 1. a processor performs a 16-bit write to the sema4_rstntf memory location. the most significant byte (sema4_rstntf[ rstndp]) must be 0x47; the l east significant byte is a ?don?t care? for this reference. 2. the same processor performs a second 16-bit write to the sema4_rstntf location. for this write, the upper byte (sema4_rstntf[rstndp]) is the logical complement of the first data pattern (0xb8) and the lower byte (sema4_rstntf[ rstntn]) specifies th e notification(s) to be reset. this field can specify a single notification be cleared or that all notifications are cleared. 3. reads of the sema4_rstntf location return information on the 2-bit state machine (sema4_rstntf[rstnsm]) that im plements this function, the bus master performing the reset (sema4_rstntf[rstnms]) and the not ification number(s) last cleared (sema4_rstntf[rstntn]). reads of the sema4_rstntf register do not affect the secure reset finite state machine in any manner. figure 43-6. semaphores (secure) re set irq notificati on (sema4_rstntf) offset: sema4_base + 0x0104 access: user read/write 0123456789101112131415 r 0 0 rstnsm 0 rstnms rstntn wrstndp reset0000000000000000
semaphore unit (sema4) 43-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 43.4 functional description multi-processor systems require a function that can be used to safely and easily provide a locking mechanism that is then used by system software to control access to shared data structures, shared hardware resources, and etc. th ese gating mechanisms are used by the software to serialize (and synchronize) writes to shared data and/or resources to prevent race conditions and preserve memory coherency between processes and processors. for example, if processor x enters a section of code where shared data values are to be updated or read coherently, it must fi rst acquire a semaphore. this locks, or closes , a software gate. afte r the gate has been locked, a properly architected softwa re system does not allow other processes (or processors) to execute the same code segment or modify the shared data structure protected by the gate, that is, other table 43-6. sema4_rstntf field descriptions field description rstnsm reset notification finite state machine. the re set state machine is maintained in a 2-bit, three-state implementation, defined as: 00 idle, waiting for the first data pattern write. 01 waiting for the second data pattern write. 10 the two-write sequence has completed. generate the specified notification reset(s). after the reset is performed, this machine returns to the idle (waiting for first data pattern write) state. 11 this state encoding is neve r used and therefore reserved. reads of the sema4_rstntf regist er return the encoded state machine value. note the rstnsm = 0b10 state is valid for a single machine cycle only, so it is impossible for a read to return this value. rstnms reset notification bus master. this 3-bit read-only field records the logical number of the bus master performing the notification reset func tion. the reset function requires that the two consecutive writes to this register be initiated by the same bus master to succeed. this field is updated each time a write to this register occurs. rstntn reset notification number. this 8-bit field specifies the specific irq notification state machine to be reset. this field is updated by the second write. if rstntn < 64, then reset the single irq notification machine defined by rstntn, else reset all the notifications. rstndp reset notification data pattern. this write-only field is accessed with the specified data patterns on the two consecutive writes to enable the notification reset mechanism. for the first write, rstndp = 0x47 while the second write requires rstndp = 0xb8. master master id e200z4d_0 0 e200z4d_1 1 edma 2 flexray 3 ?4 ?5 ?6 ?7
semaphore unit (sema4) freescale semiconductor 43-11 pxs20 microcontroller reference manual, rev. 1 processes/processors are locked out . many software implementations in clude a spin-wait loop within the lock function until the locking of the gate is accomplished. after the lock has been obt ained, processor x continues execution and updates the data values protected by the part icular lock. afte r the updates are complete, processor x unlocks (or op ens) the software gate, allowing ot her processes/processors access to the updated data values. there are three important rules th at must be followed for a corr ectly implemented system solution: ? all writes to shared data values or shared hard ware resources must be pr otected by a gate variable. ? after a processor locks a gate, accesses to the shared data or resources by other processes/processors must be blocked. th is is enforced by software conventions. ? the processor that locks a partic ular gate is the only processor th at can unlock, or open, that gate. information in the hardware gate identifying the locking processor can be useful for system-level debugging. the hennessy/patterson text on computer architectur e offers this description of software gating: ?one of the major requirements of a shared-memor y architecture multiprocessor is being able to coordinate processes that are working on a common task. typically, a programmer will use lock variables to synchronize the processes. the difficulty for the architect of a multiproces sor is to provide a mech anism to decide which processor gets the lock and to provide the operati on that locks a variable. arbitration is easy for shared-bus multiprocessors, since the bus is the onl y path to memory. the processor that gets the bus locks out all the other proces sors from memory. if the cpu a nd bus provide an atomic swap operation, programmers can cr eate locks with the proper semantics. the adjective atomic is key, for it means that a proce ssor can both read a location and set it to the locked value in the same bus operation, preventing any other pr ocessor from reading or writi ng memory.? [hennessy/patterson, computer architecture: a quantitative approach , ppg. 471-472] the classic text continues with a desc ription of the steps required to lock /unlock a variable using an atomic swap instruction. ?assume that 0 means unlocked and 1 means locked. a processor first reads the lock variable to test its state. a processor keeps reading and test ing until the value indicates that the lock is unlocked. the processor then races against all othe r processes that were si milarly ?spin waiting? to see who can lock the variable first. all processes use a swap in struction that reads the old value and stores a 1 into the lock variable. the single winner will see the 0, and the losers will see a 1 that was placed there by the winner. (the losers will continue to set the variable to the locked value, but that doesn?t matter.) the winning processor exec utes the code after the lock and then stores a 0 into the lock when it exits, starting the race all over again. testing the ol d value and then setting to a new value is why the atomic swap instruction is called test and set in some instruction sets.? [hennessy/patterson, computer architecture: a quantitative approach , ppg. 472-473] the sole drawback to a hardware-based semaphore m odule is the limited numbe r of semaphores versus the infinite number that can be supported with power architect ure reservation instructions.
semaphore unit (sema4) 43-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 43.4.1 semaphore usage example 1: inter-processor communication do ne with software interrupts and semaphores... ? the e200z4d_1 uses software interrupts to tell th e e200z4d_0 that new data is available, or the e200z4d_0 does the same to tell the e200z4d_1 that there is new data avai lable for transmission. ? because only eight software interrupts are avai lable, the user may need ram locations or general-purpose registers in the siu to refi ne the meaning of the software interrupt. ? messages are passed between cores in a defined section of system ram. ? before a core updates a message, it must check the associated semaphore to see if the other core is in the process of updating the same message. if the ram not be ing updated, then the semaphore must first be locked, then the me ssage can be updated. a software inte rrupt can be sent to the other core and the semaphore can be unloc ked. if the ram is being update d, the cpu must wait for the other core to unlock the semaphore before proceeding with update. ? using the same memory location for bidirecti onal communication might be difficult, so two one-way message areas might work better. ? for example, if both cores wa nt to update the same location, then the following sequence may occur. 1. the e200z4d_1 locks the semaphore, updates the memory, unlocks the semaphore, and generates a software in terrupt to the e200z4d_0. 2. before the e200z4d_0 takes the software inte rrupt request, it finds the semaphore to be unlocked, so it writes new data to the memory. 3. the e200z4d_0 software interrupt isr reads the data sent to the e200z 4d_1, not the data sent from the e200z4d_1, and performs an incorrect operation. ? semaphores do not prevent this situation from occurring. example 2: coherent r ead done with semaphores... ? the e200z4d_0 wants to coherently read a section of shared memory. ? the e200z4d_0 should check that the semaphore fo r the shared memory is not currently set. ? the e200z4d_0 should set the semaphore for the sh ared memory to prevent the e200z4d_1 from updating the shared memory. ? the e200z4d_0 reads the required data, then unlock the semaphore. 43.5 initialization information the reset state of the sema4 unit allows it to begin operation without the need for any further initialization. all the internal state machines ar e cleared by any reset event, allowing the unit to immediately begin operation. 43.6 application information in an operational multi-core system, most interactions involving the se ma4 unit involves reads and writes to the sema4_gate n registers for implementation of the hard ware-enforced software gate functions. typical code segments for gate func tions perform the following operations:
semaphore unit (sema4) freescale semiconductor 43-13 pxs20 microcontroller reference manual, rev. 1 ? to lock (close) a gate ? the processor performs a byte write of logical_processor_number + 1 to gate[i] ? the processor reads back gate[i] and chec ks for a value of l ogical_processor_number + 1 if the compare indicates the expected value then the gate is locked; proceed with the protected code segment else lock operation failed; repeat process beginning with byte wr ite to gate[i] in spin-wait loop, or proceed with another execution path and wa it for failed lock interrupt notification a simple c-language example of a gatelock function is shown in example 43-1 . this function follows the hennessy/patterson example. example 43-1. sample gatelock function #define unlock 0 #define cp0_lock 1 #define cp1_lock 2 void gatelock (n) int n; /* gate number to lock */ { int i; int current_value; int locked_value; i = processor_number(); /* obtain logical cpu number */ if (i == 0) locked_value = cp0_lock; else locked_value = cp1_lock; /* read the current value of the gate and wait until the state == unlock */ do { current_value = gate[n]; } while (current_value != unlock); /* the current value of the gate == unlock. attempt to lock the gate for this processor. spin-wait in this loop until gate ownership is obtained */ do { gate[n] = locked_value; /* write gate with processor_number + 1 */ current_value = gate[n]; /* read gate to verify ownership was obtained */ } while (current_value != locked_value); } ? to unlock (open) a gate ? after completing the protected code segment, the locking processor pe rforms a byte write of zeroes to gate[i], unlocking (opening) the gate in this example, a reference to processor_number() is used to retrieve th is hardware configuration value. typically, the logical proce ssor numbers are defined by a hardwire d input vector to the individual
semaphore unit (sema4) 43-14 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 cores. for powerpc cores, there is a processor id register (pir) which is spr 286 and contai ns this value. a single instruction can be used to move the cont ents of the pir into a general-purpose register: mfspr rx,286 where rx is the destination gp rn. other architectures may support a specific instruction to move the contents of the logical processor num ber into a general-purpose register, e.g., rdcpn rx for a read cpu number instruction. if the optional failed lock irq notification mechanis ms are used, then accesses to the related registers (sema4_cp n ine, sema4_ cp n ntf) are required. there is no required negation of the failed lock write notification interrupt as the request is automatically negated by the sema4 unit once the gate has been successfully locked by the failing processor. finally, in the event a system state requires a soft ware-controlled reset of a gate or irq notification register(s), accesses to the secure reset cont rol registers (sema4_rstgt, sema4_rstntf) are required. for these situations, it is recommended that the appropriate irq notification enable(s) (sema4_cp n ine) bits be disabled before initiating the secure reset 2-write se quence to avoid any race conditions involving spurious no tification interrupt requests. 43.7 dma requests there are no dma requests associated with the sema4 unit.
sine wave generator (swg) freescale semiconductor 44-1 pxs20 microcontroller reference manual, rev. 1 chapter 44 sine wave generator (swg) 44.1 introduction the sine wave generator (swg) gene rates a high-quality sinusoidal volta ge signal. it can be programmed with the desired oscillation freque ncy and amplitude voltage. a wide frequency range (1?50 khz in 16 hz steps) is easily programmable throug h a simple register interface. th e linearity/noise performances are carefully optimized through digital processing. figure 44-1 shows a block diagram of the swg. figure 44-1. swg block diagram 44.2 features ? input clock frequency range: 12?20 mhz ? output sinusoidal signal: ? frequency range: 1?50 khz ? peak-to-peak amplitude: 0.47?2.26 v 44.3 memory map and register description the memory map of the swg is shown in table 44-1 . the address of each register is given as an offset to the swg base address. registers are listed in addre ss order, identified by complete name and mnemonic, and list the type of accesses allowed. 44.3.1 swg control register (swg_ctrl) this register controls the operation of the swg. table 44-1. swg memory map address offset register location 0x0 swg control register (swg_ctrl) on page 44-1 0x4 swg status register (swg_stat) on page 44-3 swg input clock x phase generator sin(x) generator digital-to- analog converter sinusoidal signal out
sine wave generator (swg) 44-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 44-2. swg control register (swg_ctrl) address: base + 0x0 0123456789101112131415 r ldos nro 1 notes: 1 for cut1, this field must be set to 1 by software bef ore using the swg. this fiel d is reserved for cut2/3. ioampl 0 0 semask 00000 s0h1 pds w reset 0000000000000001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r iofreq w reset 0000000000000000 table 44-2. swg_ctrl field descriptions field description ldos load sine wave frequency 0 wait for i/o sine wave frequency 1 load i/o sine wave frequency note: the i/o frequency is loaded by waiting until ldos = 0 and then setting ldos = 1. nro noise reduction enable 0 noise reduction feature is enabled (signal-to-noise ratio improved) 1 noise reduction feature is disabled (signal-to-noise ratio not improved) ioampl output sine wave amplitude (see table 44-3 ) semask swg error interrupt mask 0 mask the swg error interrupt source 1 enable the swg error interrupt source s0h1 stop mode behavior 0 in stop mode, the swg enters power down mode only if pds = 1. 1 in stop mode, the swg always enters power down mode. pds enter/exit power down mode 0 force the swg to exit power down mode 1 force the swg to enter power down mode iofreq output sine wave frequency (see section 44.4.2, output sine wave frequency )
sine wave generator (swg) freescale semiconductor 44-3 pxs20 microcontroller reference manual, rev. 1 44.3.2 swg status re gister (swg_stat) this register indicates whether an error interrupt is pending and al lows you to force this interrupt. figure 44-3. swg status register (swg_stat) table 44-3. sine wave amplitude as a function of swg_ctrl[ioampl] swg_ctrl[ioampl] sine wave ampl itude (v) amplitude step (v) 0b0000 0.467 ? 0b0001 0.538 0.072 0b0010 0.611 0.072 0b0011 0.682 0.072 0b0100 0.754 0.072 0b0101 0.826 0.072 0b0110 0.898 0.072 0b0111 0.969 0.072 0b1000 1.09 0.12 0b1001 1.258 0.168 0b1010 1.426 0.168 0b1011 1.595 0.168 0b1100 1.761 0.168 0b1101 1.929 0.168 0b1110 2.097 0.168 0b1111 2.264 0.168 address: base + 0x4 0123456789101112131415 r00000000 serr 000 ferr 000 w w1c reset 0000000000000001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset 0000000000000000
sine wave generator (swg) 44-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 44.4 functional description 44.4.1 swg operation after a power-on reset after a power-on reset, the swg produces a dc value (no sinusoidal fluctuations). 44.4.2 output sine wave frequency the output sine wave frequency f is controlled by the swg_ctrl[iofreq] field according to equation 44-1 : eqn. 44-1 where both frequencies are in hz and iofreq is in decimal format. iofreq must be chosen to ensure that f remains between 1 and 50 khz. 44.4.3 output sine wave amplitude the amplitude of the output sine wave is controll ed by the swg_ctrl[ioampl] field as described in table 44-3 . 44.5 initialization / application information 44.5.1 changing the output frequency to change the output frequency: 1. determine the required value of swg_ctrl[iofreq] using equation 44-1 . 2. ensure that swg_ctrl[ldos] = 0. 3. write the new value of the swg_ctrl[iofreq] field. 4. set swg_ctrl[ldos]. the swg will begin producing the new sine wave frequency two input cl ock cycles after this procedure is completed. table 44-4. swg_stat field descriptions field description serr error interrupt status bit 0 no error interrupt pending 1 error interrupt pending note: you can clear this bit by writing a ?1? to it. ferr force error interrupt 0 an error interrupt will not be forced 1 an error interrupt will be forced (serr will be set two clock cycles after ferr is set) f inputfrequency 1048576 ------------------------------------------ ?? ?? iofreq ? =
sine wave generator (swg) freescale semiconductor 44-5 pxs20 microcontroller reference manual, rev. 1 44.5.2 preserving the swg_ctrl data after you make a change to the swg_ctrl register, th e swg expects that you will preserve this data for at least 50 clock cycles. fail ure to do so may cause unexpe cted output from the swg.
sine wave generator (swg) 44-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1
software watchdog timer (swt) freescale semiconductor 45-1 pxs20 microcontroller reference manual, rev. 1 chapter 45 software watchdog timer (swt) 45.1 introduction 45.1.1 overview the software watchdog timer (swt) is a peripheral module that can prev ent system lockup in situations such as software getting trapped in a loop or if a bus transa ction fails to terminate. when enabled, the swt requires periodic execution of a wa tchdog servicing operation. the servic ing operation resets the timer to a specified time-out period. if this servicing action does not occur before the timer expires the swt generates an interrupt or ha rdware reset. the swt can be configured to generate a reset or interrupt on an initial time-out, a reset is always ge nerated on a second consecutive time-out. 45.1.2 features the swt has the following features: ? 32-bit time-out register to set the time-out period ? fixed selection of ircosc clock for timer operation ? programmable selection of window mode or regular servicing ? programmable selection of reset or interrupt on an initial time-out ? programmable selection of fixed or keyed servicing ? master access protection ? hard and soft configuration lock bits on this device, the swt is always driven by the ircosc. 45.1.3 modes of operation the swt supports three device m odes of operation: normal, debug a nd stop. when the swt is enabled in normal mode, its counter runs continuously. in debug mode, operation of the counter is controlled by the frz bit in the swt_cr. if the frz bit is set, the counter is stopped in debug mode, otherwise it continues to run. in stop mode, operation of the counter is controlled by the stp bit in the swt_cr. if the stp bit is set, the counter is stopped in stop mode, otherwise it continues to run. 45.2 external signal description the swt module does not have a ny external interface signals. 45.3 memory map and register definition the swt programming model has seve n 32-bit registers. the program ming model can only be accessed using 32-bit (word) accesses. references using a differ ent size are invalid. other types of invalid accesses
software watchdog timer (swt) 45-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 include: writes to read only regist ers, incorrect values written to the service register when enabled, accesses to reserved addr esses and accesses by master s without permission. if th e ria bit in the swt_cr is set then the swt generates a system reset on an invalid access otherwise a bus error is generated. if either the hlk or slk bits in the swt_cr are set then the swt_cr, swt_to, swt_wn, swt_sk registers are read only. 45.3.1 memory map the swt memory map is shown in table 45-1 . the reset values of swt_cr, swt_to and swt_wn are device specific. these values are determined by swt inputs. 45.3.2 register descriptions the following sections detail the individua l registers within the swt programming model. 45.3.2.1 swt control register (swt_cr) the swt_cr contains fields for conf iguring and controlling the swt. the reset value of this register is device specific. some devices can be configured to automatically cl ear the swt_cr[wen] bit during the boot process. this register is read only if either the swt_cr[hl k] or swt_cr[slk] bits are set. table 45-1. swt memory map address offset register name register description size (bits) access 0x0000 swt_cr swt control register 32 r/w 0x0004 swt_ir swt interrupt register 32 r/w 0x0008 swt_to swt time-out register 32 r/w 0x000c swt_wn swt window register 32 r/w 0x0010 swt_sr swt service register 32 r/w 0x0014 swt_co swt counter output register 32 r 0x0018 swt_sk swt service key register 32 r/w 0x001c- 0x3fff - reserved - -
software watchdog timer (swt) freescale semiconductor 45-3 pxs20 microcontroller reference manual, rev. 1 table 45-2. swt_cr field descriptions offset 0x0000 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r map 0 map 1 map 2 map 3 map 4 map 5 map 6 map 7 00000 0 00 w reset1111111100000 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 00000keyria wnd itr hlk slk 1 stp frz wen w reset0000000100011 0 10 figure 45-1. swt control register (swt_cr) field description mapn master access protection for ma ster n. the platform bus master assignments are device specific. 0 = access for the master is not enabled 1 = access for the master is enabled key keyed service mode. 0 = fixed service sequence, the fixed sequence 0xa602, 0xb480 is used to service the watchdog 1 = keyed service mode, two pseudorandom key values are used to service the watchdog ria reset on invalid access. 0 = invalid access to the swt generates a bus error 1 = invalid access to the swt causes a system reset if wen=1 wnd window mode. 0 = regular mode, service sequence can be done at any time 1 = windowed mode, the service sequence is only valid when the down counter is less than the value in the swt_wn register. itr interrupt then reset. 0 = generate a reset on a time-out 1 = generate an interrupt on an initial time-out, reset on a second consecutive time-out hlk hard lock. this bit is only cleared at reset. 0 = swt_cr, swt_to, swt_wn and swt_sk are read/write registers if slk=0 1 = swt_cr, swt_to, swt_wn and swt_sk are read only registers slk soft lock. this bit is cleared by writing the unlock sequence to the service register. 0 = swt_cr, swt_to swt_wn and swt_sk are read/write registers if hlk=0 1 = swt_cr, swt_to, swt_wn and swt_sk are read only registers stp stop mode control. allows the watchdog time r to be stopped when the device enters stop mode. 0 = swt counter continues to run in stop mode 1 = swt counter is stopped in stop mode
software watchdog timer (swt) 45-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 45.3.2.2 swt interrupt register (swt_ir) the swt_ir contains the time-out interrupt flag. table 45-3. swt_ir field descriptions 45.3.2.3 swt time-out register (swt_to) the swt time-out (swt_to) register contains the 32-bit time-out period. th e reset value for this register is device specific. this re gister is read only if either the swt_cr[hlk ] or swt_cr[slk] bits are set. frz debug mode control. allows the watchdog time r to be stopped when the device enters debug mode. 0 = swt counter continues to run in debug mode 1 = swt counter is stopped in debug mode wen watchdog enabled. 0 = swt is disabled 1 = swt is enabled offset 0x0004 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r0000000000000 0 00 w reset0000000000000 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0000000 0 0 00000tif w reset0000000000000 0 00 figure 45-2. swt interrupt register (swt_ir) field description tif time-out interrupt flag. the flag and interrupt are cleared by writing a 1 to this bit. writing a 0 has no effect. 0 = no interrupt request. 1 = interrupt request due to an initial time-out. field description
software watchdog timer (swt) freescale semiconductor 45-5 pxs20 microcontroller reference manual, rev. 1 figure 45-3. swt time-out register (swt_to) table 45-4. swt_to register field descriptions 45.3.2.4 swt window register (swt_wn) the swt window (swt_wn) register c ontains the 32-bit window start valu e. this register is cleared on reset. this register is read only if either the swt_cr[hlk] or sw t_cr[slk] bits are set. figure 45-4. swt window register (swt_wn) table 45-5. swt_wn regi ster field descriptions 45.3.2.5 swt service register (swt_sr) the swt time-out (swt_sr) service register is the ta rget for service operation wr ites used to reset the watchdog timer. offset 0x008 access: read/write 012345678910111213141516171819202122232425262728293031 r wto w reset00000000000000111111110111100000 field description wto watchdog time-out period in clock cycles. an internal 32-bit down counter is loaded with this value or 0x100 which ever is greater when the service sequ ence is written or when the swt is enabled. offset 0x00c access: read/write 012345678910111213141516171819202122232425262728293031 r wst w reset00000000000000000000000000000000 field description wst window start value. when window mode is enabled, the service sequence can only be written when the internal down counter is less than this value.
software watchdog timer (swt) 45-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 45-5. swt service register (swt_sr) table 45-6. swt_sr field descriptions 45.3.2.6 swt counter output register (swt_co) the swt counter output (swt_co) regi ster is a read only register that shows the value of the internal down counter when the swt is disabled. caution do not access the swt_co register in lock step mode (lsm). figure 45-6. swt counter output register (swt_co) table 45-7. swt_co register field descriptions offset 0x010 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0000000000000 00000000 00 0 0 00 w wsc reset00000000000000000000000000000000 field description wsc watchdog service code.this field is used to serv ice the watchdog and to clear the soft lock bit (swt_cr[slk]). if the swt_cr[key] bi t is set, two pseudorandom key values are written to service the watchdog, see section 45.4 for details. otherwise, the sequence 0xa602 followed by 0xb480 is written to the wsc field. to clear the soft lock bit (swt_cr[slk]), the value 0xc520 followed by 0xd928 is written to the wsc field. offset 0x014 access: read only 012345678910111213141516171819202122232425262728293031 r cnt w reset00000000000000000000000000000000 field description cnt watchdog count. when the watchdog is disabled (s wt_cr[wen]=0) this field shows the value of the internal down counter. when the watchdog is enabled the value of this field is 0x0000_0000. values in this field can lag behind the internal counter value for up to six system plus eight counter clock cycles. therefore, the value read from this field immediately after disabling the watchdog may be higher than the actual value of the internal counter.
software watchdog timer (swt) freescale semiconductor 45-7 pxs20 microcontroller reference manual, rev. 1 45.3.2.7 swt service key register (swt_sk) the swt service key (swt_sk) register holds the prev ious (or initial) service ke y value. this register is read only if either the swt_cr [hlk] or swt_cr[slk] bits are set. figure 45-7. swt service key register (swt_sk) 45.4 functional description the swt is a 32-bit timer desi gned to enable the system to recover in situations such as software getting trapped in a loop or if a bus trans action fails to terminate. it includ es a control regist er (swt_cr), an interrupt register (swt_ir), a ti me-out register (swt_to), a window register (swt_wn), a service register (swt_sr), a counter out put register (swt_co) and a se rvice key register (swt_sk). the swt_cr includes bits to enable the timer, set c onfiguration options and lo ck configuration of the module. the watchdog is enabled by setting th e swt_cr[wen] bit. the reset value of the swt_cr[wen] bit is device specific. if the reset va lue of this bit is 1, the watchdog starts operation automatically after reset is release d. some devices can be c onfigured to clear this bit automatically during the boot process. the swt_to register holds the watc hdog time-out period in clock cycles unless the value is less than 0x100 in which case the time-out period is set to 0x100. th is time-out period is loaded into an internal 32-bit down counter when the swt is enabled and each time a valid service opera tion is performed. the swt down counter is always driven by the ircosc cl ock . the reset value of the swt_to register is device specific. the configuration of the swt can be lo cked through use of either a soft lock or a hard lock. in either case, when locked the swt_cr, swt_to, swt_wn and swt_sk registers are read only. the hard lock is enabled by setting the swt_cr[hlk] bi t which can only be cleared by a re set. the soft lock is enabled by setting the swt_cr[slk] bit and is cleared by writing the unlock seque nce to the service register. the unlock sequence is a write of 0xc 520 followed by a write of 0xd928 to the swt_sr[wsc] field. there is no timing requirement between the two writes. the unlock sequence logic ignores service sequence writes and recognizes the 0xc520, 0xd928 sequence regardless of prev ious writes. the unlock sequence can be written at any time and does not require the swt_cr[wen] bit to be set. offset 0x018 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0000000000000 00000000 00 0 0 00 w sk reset00000000000000000000000000000000 table 45-8. swt_sk field descriptions field description sk service key.this field is the previous (or initial) service key value used in keyed service mode. if swt_cr[key] is set, the next key value to be written to the swt_sr is (17*sk+3) mod 2 16 .
software watchdog timer (swt) 45-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 when enabled, the swt requires periodi c execution of a servic ing operation which cons ists of writing two values to the swt_sr. writing the proper sequence of values loads the internal down counter with the time-out period. there is no timing requirement between th e two writes and the service sequence logic ignores unlock sequence writes. if the swt_cr[key] bit is zero, the fixed se quence 0xa602, 0xb480 is written to the swt_sr[wsc] field to service the watchdog. if the swt_cr[key] bit is set, then two pseudorandom keys are writ ten to the swt_sr[wsc] field to serv ice the watchdog. the key values are determined by the pseudorandom key generator defined in figure 45-8 . this algorithm will generate a sequence of 2 16 different key values before repeating. the state of the key generator is held in the swt_sk register. for example, if swt_sk[sk] is 0x0100 then the se rvice sequence keys are 0x1103, 0x2136. in this mode, each time a valid key is writte n to the swt_sr register, the swt_sk register is updated. so, after servicing the watchdog by writing 0x1103 and then 0x2136 to the swt_sr[wsc] field, swt_sk[sk] is 0x2136 and the next key sequence is 0x3499, 0x7e2c. figure 45-8. pseudorandom key generator accesses to swt registers occur with no peripheral bus wait states. (the peripheral bus bridge may add one or more system wait states.) however, due to synchronization logic in th e swt design, r ecognition of the service sequence or configurati on changes may require up to three system plus seven counter clock cycles. if window mode is enabled (swt_cr[wnd] bit is se t), the service sequence must be performed in the last part of the time-out period defined by the window register. the window is open when the down counter is less than the value in the swt_wn register. outs ide of this window, service sequence wr ites are invalid accesses and generate a bus error or reset depending on the value of th e swt_cr[ria] bit. for example, if the swt_to register is set to 5000 and swt_wn register is set to 1000 then th e service sequence must be performed in the last 20% of the time-out period. there is a short lag in the time it takes for the window to open due to synchronization logic in the watchdog design. this delay c ould be up to three system plus four counter clock cycles. the interrupt then reset bit (swt_cr[itr]) controls the action taken when a time-out occurs. if the swt_cr[itr] bit is not set, a reset is generated im mediately on a time-out. if the swt_cr[itr] bit is set, an initial time-out causes the swt to generate an inte rrupt and load the down c ounter with the time-out period. if the service sequen ce is not written before the second c onsecutive time-out, the swt generates a system reset. the interrupt is indicated by the ti me-out interrupt flag (swt _ir[tif]). the interrupt request is cleared by writing a one to the swt_ir[tif] bit. the swt_co register shows the va lue of the down counter when the watchdog is disabled. when the watchdog is enabled this register is cleared. the value shown in this register can lag behind the value in the internal counter for up to six syst em plus eight counter clock cycles. the swt_co can be used during a so ftware self test of the swt. fo r example, the swt can be enabled and not serviced for a fixed period of time less than the time-out value. then the swt can be disabled (swt_cr[wen] cleared) and the value of the swt_co read to determine if the internal down counter is working properly. sk n+1 = (17*sk n +3) mod 2 16
static ram (sram) freescale semiconductor 46-1 pxs20 microcontroller reference manual, rev. 1 chapter 46 static ram (sram) 46.1 introduction the sram provides the following features: ? 128 kb of general- purpose static ram ? sram can be read/writte n from any bus master ? byte, halfword, word and doubleword addressable ? single-bit correction and double-bit error detection 46.2 sram operating mode the sram has only one operating mode.t here is no stand-by mode available. 46.3 registers the internal sram has no regist ers. registers for the sram ecc are located in the ecsm. 46.4 sram ecc mechanism the sram ecc detects the following condi tions and produces the following results: ? detects and corrects all 1-bit errors ? detects and flags all 2-bit erro rs as non-correctable errors ? detects 39-bit reads (32-bit data bus plus the 7-bit ecc) that return all zeros or all ones, asserts an error indicator on the bus cycle, and sets the error flag sram does not detect all er rors greater than 2 bits. internal sram write operations are pe rformed on the following byte boundaries: ? 1 byte (0:7 bits) ? 2 bytes (0:15 bits) ? 4 bytes or 1 word (0:31 bits) if the entire 32 data bits are written to sram, no re ad operation is performed and the ecc is calculated across the 32-bit data bus. the 8-bit ecc is appe nded to the data segment and written to sram. if the write operation is less than the entire 32-bit data width (1-, or 2-byte segment), the following occurs: 1. the ecc mechanism checks the entire 32-bit data bus for errors, detecting and either correcting or flagging errors. table 46-1. sram operating modes mode configuration normal (functional) allows reads and writes of sram.
static ram (sram) 46-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 2. the write data bytes (1-, or 2- byte segment) are merged with the corrected 32 bits on the data bus. 3. the ecc is then calculated on the resulti ng 32 bits formed in the previous step. 4. the 7-bit ecc result is appended to the 32 bits from the data bus, and th e 39-bit value is then written to sram. 46.4.1 access timing the system bus is a two-stage pipe lined bus, which makes the timing of any access dependent on the access during the previous clock. table 46-2 lists the various combinations of read and write operations to sram and the number of wait states used for the each operation. the table columns contain the following information: current operation lists the type of sram operation executing currently previous operation lists the valid types of sram operations that can precede the current sram operation (valid operation dur ing the preceding clock) wait states lists the number of wait states (bus clocks) the operation requires which depends on the combination of the cu rrent and previous operation table 46-2. number of wait states required for sram operations current operation previous operatio n number of wait states required read operation read idle 1 pipelined read 8-, 16-, or 32-bit write 0 (read from the same address) 1 (read from a different address) pipelined read read 0 write operation 8-, or 16-bit write idle 1 read pipelined 8-, or 16-bit write 2 32-bit write 8-, or 16-bit write 0 (write to the same address) pipelined 8-, 16-, or 32-bit write 8-, 16-, or 32-bit write 0 32-bit write idle 0 32-bit write read
static ram (sram) freescale semiconductor 46-3 pxs20 microcontroller reference manual, rev. 1 46.4.2 reset effects on sram accesses on cut1 on cut1, asynchronous reset will possi bly corrupt ram if it asserts dur ing a read or write operation to sram. the completion of that access depends on the cycl e at which the reset occurs. data read from or written to sram before the reset event occurred is retained, and no other addr ess locations are accessed or changed. in case of no acce ss ongoing when reset occurs, the ram corruption does not happen. instead synchronous reset (sw reset) should be used in controlled function (without ram accesses) in case initialization procedure is needed without ram initialization. 46.5 functional description ecc checks are performed during the read portion of an sram ecc read/wri te (r/w) operation, and ecc calculations are performed dur ing the write portion of a read/w rite (r/w) operation. because the ecc bits can contain random data after the device is powered on, the sram must be initialized by executing 32-bit write operations prior any read accesses. this is also true for implicit read accesses caused by any write accesses of less than 32-bit as discussed in "ecc mechanism". 46.6 initialization and application informations to use the sram, the ecc must check all bits that require initialization after power on. all writes must specify an even number of regist ers performed on 32-bit word-aligned boundaries. if the write is not the entire 32-bits (8-, or 16-bits), a read / modify / write operation is generated that checks the ecc value upon the read. refer to section 46.4, sram ecc mechanism . note you must initialize sram, even if th e application does not use ecc reporting.
static ram (sram) 46-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1
system integration unit lite (siul) freescale semiconductor 47-1 pxs20 microcontroller reference manual, rev. 1 chapter 47 system integration unit lite (siul) 47.1 introduction this chapter describes the system in tegration unit lite (siul), which is used for the management of the pads and their configuration. it controls the multiplexi ng of the alternate functions used on all pads as well as being responsible for the management of the external interrupts to the device. 47.2 overview the system integration unit lite (siul) contro ls the mcu pad configuration, ports, general-purpose input and output (gpio) signals and external interrupts with trigger event configuration. figure 47-1 is a block diagram of the siul and its interfaces to other system components. the module provides dedicated general-purpose pads that can be conf igured as either inputs or outputs. when configured as an output, you can write to an inte rnal register to control the state driven on the associated output pad. when configured as an input , you can detect the state of the associated pad by reading the value from an internal register. when conf igured as an input and out put, the pad value can be read back, which can be used a method of chec king if the written value appeared on the pad.
system integration unit lite (siul) 47-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 47-1. siul block diagram ips bus data pad input io interrupt interrupt controller ips master - configuration - glitch filter pad config (iomuxc) pad cfg (pcrs) gpio functionality number of gpio number 32 4 mux pa ds 108 siul interrupt functionality of gpio number of gpio
system integration unit lite (siul) freescale semiconductor 47-3 pxs20 microcontroller reference manual, rev. 1 47.3 features the system integration unit lite supports these distinctive features: ?gpio ? 121 pins which are user-confi gurable inputs and/or outputs ? 22 pins have user-configurable gene ral purpose input (gpi) functionality ? 99 pins have user-configurable genera l purpose input/ouput (gpio) functionality ? dedicated input and output re gisters for each gpio pin ? external interrupts ? 4 system interrupt vectors for 32 interrupt sources ? 32 programmable digi tal glitch filters ? independent interrupt mask ? edge detection ? system configuration ? pad configuration control 47.3.1 register protection the individual registers of system integration unit lite are protected from accidental writes, see chapter 40, register protection (reg_prot) . 47.4 external signal description the pad configuration allows flexible , centralized control of the pin el ectrical characteristics of the mcu with the gpio control providing cent ralized general purpose i/o for an mcu that multiplexes gpio with other signals at the i/o pads. these other signals, or alternate functions , will normally be the peripherals functions. the internal multiplexing al lows user selection of the input to chip-level signal multiplexors. each gpio port communicates via 16 i/o channels. in order to use the pad as a gpio, the corresponding pad configuration registers (pcr) for all pads used in the port must be configured as gpio rather than as the alternate pad function. table 47-1 lists the external pins used by the siul. ( table 47-1. siul signal properties name i/o type function system configuration gpio i/o general-purpose i/o external interrupt eirq[0:8, 10:18, 22, 30:31, 35:38, 77:81, 96:97] input external interrupt request input
system integration unit lite (siul) 47-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 47.4.1 detailed signal descriptions 47.4.1.1 general-purpose i/o pins the gpio pins provide general-purpose input a nd output function. the gpio pins are generally multiplexed with other i/o pin functions. each gpio input and output is separately cont rolled by an input (gpdi n_n ) or output (gpdo n_n ) register. see section 47.5.2.10, gpio pad data output registers (gpdo) and section 47.5.2.11, gpio pad data input registers (gpdi) . 47.4.1.2 external interrupt request input pins (eirq[0:31]) the eirq[0:31] are connected to the siu inputs. rising or falling edge events are enabled by setting the corresponding bits in the siu_ireer or the siu_ifeer register. see section 47.5.2.5, interrupt rising-edge event enab le register (ireer) and section 47.5.2.6, interrupt fall ing-edge event enable register (ifeer) . 47.5 memory map and register description this section provides a detailed description of all registers accessibl e in the siul module. 47.5.1 siul memory map table 47-2 gives an overview on the siul registers implemented. table 47-2. siul memory map address offset register name description location 0x0004 midr1 mcu id register #1 on page 47-6 0x0008 midr2 mcu id register #2 on page 47-7 (0x000c?0x0013) ? reserved 0x0014 isr interrupt st atus flag register on page 47-7 0x0018 irer interrupt request enable register on page 47-8 (0x001c?0x0027) ? reserved 0x0028 ireer interrupt rising edge event enable on page 47-9 0x002c ifeer interrupt falling-edge event enable on page 47-9 0x0030 ifer ifer interrupt filter enable register on page 47-10 (0x0034?0x003f) ? reserved 0x0040?0x0116 pcr0?pcr n pad configuration registers on page 47-10 (0x0118?0x04ff) ? reserved 0x0500?0x0528 psmi0_3? psmi40_43 pad selection for multiplexed inputs on page 47-12 (0x052a?0x05ff) ? reserved
system integration unit lite (siul) freescale semiconductor 47-5 pxs20 microcontroller reference manual, rev. 1 note a transfer error will be issued when trying to access completely reserved register space. 47.5.2 register description this section describes in a ddress order all the siul regi sters. each description incl udes a standard register diagram. details of register bit a nd field function follow the register diagrams, in bit or der. the numbering convention of register is msb=0; however the numbering of in ternal field is lsb=0, for example, partnum[5] = midr1[10]. figure 47-2. key to register fields 0x0600?0x0668 gpdo 1 gpio pad data output register on page 47-13 (0x066c?0x07ff) ? reserved 0x0800?0x0868 gpdi 2 gpio pad data input register on page 47-14 (0x086c?0x0bff) ? reserved 0x0c00?0x0c0c pgpdo0? pgpdo3 parallel gpio pad data out register on page 47-15 (0x0c10?0x0c3f) ? reserved 0x0c40?0x0c4c pgpdi0? pgpdi3 parallel gpio pad data in register on page 47-15 (0x0c50?0x0c7f) ? reserved 0x0c80?0x0c98 mpgpdo0? mpgpdo6 masked parallel gpio pad data out register on page 47-17 (0x0c9c?0x0fff) ? reserved 0x1000?0x107c ifmc0? ifmc31 interrupt filter maximum counter register on page 47-18 0x1080 ifcp interrupt filter clock prescaler register on page 47-18 (0x1084?0x3fff) ? reserved notes: 1 check the pin-muxing table ( section 3.4, pin muxing ) if gpo functionality is available. 2 check the pin-muxing table ( section 3.4, pin muxing ) if gpi functionality is available. always 1 always 0 r/w bit read - bit write - write 1 bit self - 0 n/ a reads 1 reads 0 bit only bit only bit bit to clear w1c clear bit bit table 47-2. siul memory map (continued) address offset register name description location
system integration unit lite (siul) 47-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 47.5.2.1 mcu id register 1 (midr1) this register contains informat ion that identifies the device. address: base + 0x0004 access: read only 0123456789101112131415 r partnum w reset reset values depend on the device and package type as shown in ta bl e 4 7 - 3 . 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r csp pkg[4:0] major_mask minor_mask w reset reset values depend on the device and package type as shown in table 47-3 . 00 reset values depend on the device and package type as shown in ta b l e 4 7 - 3 . figure 47-3. mcu id register 1 (midr1) table 47-3. midr1 field descriptions field description partnum mcu part number read-only, device part number of the mcu. 0101_0110_0100_0011: device with 1 mb flash memory for the full part number this field needs to be combined with midr2.partnum[23:16] csp always reads back 0 pkg package settings can by read by software to determine the package type that is used for the particular device: 0b01101: 144-pin qfp 0b01000: 257-pin bga major_mask major mask revision cut1: 0x0 cut2: 0x1 cut3: 0x1 minor_mask minor mask revision cut1: 0x0 cut2: 0x0 cut3: 0x1
system integration unit lite (siul) freescale semiconductor 47-7 pxs20 microcontroller reference manual, rev. 1 47.5.2.2 mcu id register 2 (midr2) 47.5.2.3 interrupt status flag register (isr) this register holds the interrupt flags. address: base + 0x0008 access: read only 0123456789101112131415 r sf flash_size_1 flash_size_2 w reset 0011000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r partnum[23:16] fr w reset 0100110000000001 figure 47-4. mcu id register 2 (midr2) table 47-4. midr2 field descriptions field description sf manufacturer 0: freescale flash_size_1 coarse granularity for flash memory size combine with flash_size_2 to calculate the actual memory size. 0b0110: 1 mb flash_size_2 fine granularity for flash memory size combine with flash_size_1 to calculate the actual memory size. 0b0000: 0 x (flash_size_1 ? 8) 0b0010: 2 x (flash_size_1 ? 8) 0b0100: 4 x (flash_size_1 ? 8) partnum [23:16] ascii character in mcu part number 0x4c: l (pxs20) family fr flexray present 1: flexray is present 0: flexray is not present
system integration unit lite (siul) 47-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 47.5.2.4 interrupt request enable register (irer) this register is used to enable the inte rrupt messaging to the interrupt controller. address: base + 0x0014 access: user read/write (write 1 to clear) 012345678910111213141516171819202122232425262728293031 r eif[31:0] w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset 00000000000000000000000000000000 figure 47-5. interrupt status flag register (isr) table 47-5. isr field descriptions field description eif[x] external interrupt status flag x this flag can be cleared only by writing a 1. writin g a 0 has no effect. if enabled (irer[x]), eif[x] causes an interrupt request. 0: no interrupt event has occurred on the pad 1: an interrupt event as defined by ireer[x] and ifeer[x] has occurred address: base + 0x0018 access: user read/write 012345678910111213141516171819202122232425262728293031 r eire[31:0] w reset 00000000000000000000000000000000 figure 47-6. interrupt request enable register (irer) table 47-6. irer field descriptions field description eire[x] external interrupt request enable x 1: a set eir[x] bit causes an interrupt request 0: interrupt requests from the corresponding eir[x] bit are disabled
system integration unit lite (siul) freescale semiconductor 47-9 pxs20 microcontroller reference manual, rev. 1 47.5.2.5 interrupt rising-edge event enable register (ireer) this register enables rising-edge triggere d events on the corresponding interrupt pads. 47.5.2.6 interrupt falling-edge ev ent enable register (ifeer) this register enables falling- edge triggered events on th e corresponding interrupt pads. note if both the iree and ifee bits are cleared for the same inte rrupt source, the interrupt status flag for the corres ponding external interr upt will never be set. address: base + 0x0028 access: user read/write 0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728293031 r iree[31:0] w reset 00000000000000000000000000000000 figure 47-7. interrupt rising-edge event enable register (ireer) table 47-7. ireer field descriptions field description iree[x] enable rising-edge events to cause the eif[x] bit to be set. 1: rising-edge event is enabled 0: rising-edge event is disabled address: base + 0x002c access: user read/write 012345678910111213141516171819202122232425262728293031 r ifee[31:0] w reset 00000000000000000000000000000000 figure 47-8. interrupt falling-edge event enable register (ifeer) table 47-8. ifeer field descriptions field description ifee[x] enable falling-edge events to cause the eif[x] bit to be set. 1: falling-edge event is enabled 0: falling-edge event is disabled
system integration unit lite (siul) 47-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 47.5.2.7 interrupt filter enable register (ifer) this register is used to enable or disable a digital filter counter on the in terrupt pads to fi lter out glitches on the inputs. 47.5.2.8 pad configuration registers (pcr0?pcr132) the pad configuration regist ers allow configuration of the static electrical and functional characteristics associated with i/o pads. each pcr contro ls the characteristics of a single pad. see table 3-5 for the mapping of pcr to pads. note 16- and 32-bit accesses are supported. address: base + 0x0030 access: user read/write 012345678910111213141516171819202122232425262728293031 r ife[31:0] w reset 00000000000000000000000000000000 figure 47-9. interrupt filter enable register (ifer) table 47-9. ifer field descriptions field description ife[x] enable digital glitch filt er on the interrupt pad input. 1: filter is enabled 0: filter is disabled address: base + 0x0040 (pcr0)(122 registers) base + 0x0042 (pcr1) ... base + 0x0148 (pcr132) access: user read/write 0123456789101112131415 r smc apc pa obe ibe ode src wpe wps w reset 00000000 1 notes: 1 the reset value of the ibe- bit of the pad configuration registers pcr2, 3, 4, 21 is '1' in distinction from the remaining pcr registers 0000000 2 2 the reset value of the wpe- bit of the pad configuration re gisters pcr2, 3, 4, 21 is '1' in distinction from the remaining pcr registers 0 3 3 the reset value of the wps- bit of the pad configurat ion registers pcr21 is '1' in distinction from the remaining pcr registers figure 47-10. pad configuration registers (pcr0)
system integration unit lite (siul) freescale semiconductor 47-11 pxs20 microcontroller reference manual, rev. 1 table 47-10. pcr0 field descriptions field description smc safe mode control this bit supports the overriding of the automatic de activation of the output buffer of the associated pad upon entering safe mode of the soc. 1: in soc safe mode, the output buffer remains functional. 0: in soc safe mode, the output buffer of the pad is disabled. apc analog pad control this bit enables the usage of the pad as analog input. 1: analog input path switch can be enabled by the adc. 0: analog input path from the pad is gated and can not be used. pa[1:0] pad output assignment this field is used to select the function that is al lowed to drive the output of a multiplexed pad. the pa field size can vary from zero to two bits, depending on the number of output functions associated with this pad. 00: alternative mode 0: gpio. 01: alternative mode 1 10: alternative mode 2 11: alternative mode 3 note: number of bit depending of the number of actual alternate function. please refer to datasheet obe output buffer enable this bit enables the output buffer of the pad in case the pad is in gpio mode. 1: output buffer of the pad is enabled when pa = 00. 0: output buffer of the pad is disabled when pa = 00. ibe input buffer enable this bit enables the input buffer of the pad. 1: input buffer of the pad is enabled. 0: input buffer of the pad is disabled. ode open drain output enable this bit controls output driver configuration for th e pads connected to this signal. either open drain or push/pull driver configurations can be sele cted. this feature applie s to output pads only. 1: open drain enable signal is asserted for the pad. 0: open drain enable signal is negated for the pad. src slew rate control src = 0 slowest configuration src = 1 fastest configuration wpe weak pull up/down enable this bit controls whether the weak pull up/d own devices are enabled/disabled for the pad connected to this signal. 1: weak pull device enable signal is asserted for the pad. 0: weak pull device enable signal is negated for the pad. wps weak pull up/down select this bit controls whether weak pull up or weak pull down devices are used for the pads connected to this signal when weak pull up/down devices are enabled. 1: the pull up enabled. 0: the pull down enabled.
system integration unit lite (siul) 47-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 47.5.2.9 pad selection for mult iplexed inputs (psmi0_3?psmi40_43 1 ) these registers define pads as input to peripheral functions. figure 47-11 and table 47-11 present the structure of the psmi0_3 re gister. the structur e of the other 10 psmi registers is similar, with numbers modified appropriately. 1.psmi43 does not exist; the register name includes the number 43 due to the sequential naming convention of these registers. address: base + 0x0500 - 0x0528 (11 registers) access: user read/write 0123456789101112131415 r 0000 padsel0 0000 pa d s e l 1 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 padsel2 0000 pa d s e l 3 w reset 0000000000000000 figure 47-11. pad selection for multiplexed inputs register (psmi0_3) table 47-11. psmi0_3 field descriptions field description padsel0?3 pad selection bits each padsel field selects the pad currently used for a certain input function (see ta b l e 3 - 5 ). example: in function: lin0 rxd psmi32_35 padsel0: 00: b[3] 01: b[7]
system integration unit lite (siul) freescale semiconductor 47-13 pxs20 microcontroller reference manual, rev. 1 47.5.2.10 gpio pad data output registers (gpdo) these registers can be used to set or clear a single gpio pa d with a byte access. example 47-1. accessing gpdo ports check if gpio exists in pin muxing table ( section 3.4, pin muxing ) write pad data output register for a[0] which is gpio[0]. 32 bit write to address 0x0600 + 0x0000 ==> register after write 0x--------_--------_--------_------- write pad data output register for a[4] which is gpio[4]. 32 bit write to address 0x0600 + 0x0004 ==> register after write 0x--------_--------_--------_------- write pad data output register for g[2] which is gpio[89]. 32 bit write to address 0x0600 + 0x0016 ==> register after write 0x--------_--------_-------_-------- 8 bit write to address 0x0600 + 0x0017 address for 32 bit accesses = 0x0600 + [hex [ [gpio number / 4]** ] ** returns the integer portion of the division address: base + 0x0600?0x0668 (27 re gisters) access: user read/write 0123456789101112131415 r 0000000pdo [0] 0000000pdo [1] w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000pdo [2] 0000000pdo [3] w reset 0000000000000000 figure 47-12. port gpio pad data output register 0?3 (gpdo0_3) table 47-12. gpdo0_3 field descriptions field description pdo[x] pad data out this bit stores the data to be driven out on the ex ternal gpio pad controlled by this register. 1: logic high value is driven on the corresponding gpio pad when the pad is configured as an output 0: logic low value is driven on the corresponding gpio pad when the pad is configured as an output
system integration unit lite (siul) 47-14 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 47.5.2.11 gpio pad data input registers (gpdi) these registers can be used to read the gpio pad data with a byte access. table 47-13. gpdo0_3?gpdi104_107 field descriptions example 47-2. accessing gpdi ports check if gpio exists in pin muxing table ( section 3.4, pin muxing ) read pad data input register for a[0] which is gpio[0]. 32 bit read from address 0x0600 + 0x0000 ==> return value 0x--------_--------_--------_------- write pad data input register for a[4] which is gpio[4]. 32 bit read from address 0x0600 + 0x0004 ==> return value 0x--------_--------_--------_------- write pad data input register for g[2] which is gpio[89]. 32 bit read from address 0x0600 + 0x0016 ==> return value 0x--------_--------_-------_-------- 8 bit read from address 0x0600 + 0x0017 address for 32 bit accesses = 0x0800 + [hex [gpio number / 4]** ] ** returns the integer portion of the division address: base + 0x0800?0x0868 (27 registers) access: user read 0123456789101112131415 r 0000000pdi [0] 0000000pdi [1] w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000pdi [2] 0000000pdi [3] w reset 0000000000000000 figure 47-13. port gpio pad data input register 0?3 (gpdi0_3?gpdi104_107)) field description pdi[x] pad data in this bit stores the value of the external gpio pad associated with this register. 1: the value of the data in signal for the corresponding gpio pad is logic high 0: the value of the data in signal for the corresponding gpio pad is logic low
system integration unit lite (siul) freescale semiconductor 47-15 pxs20 microcontroller reference manual, rev. 1 47.5.2.12 parallel gpio pad data out register (pgpdo0?pgpdo3) these registers are used to set or clear the respective pads of the device. see section 3.5, mapping of ports to pgpdo/i registers . table 47-14. pgpdo0?pgpdo3 field descriptions note the pgpdo registers access the same physical resource as the pdo and mpgpdo address locations. so me examples of the mapping: ppdo[0][0] = pdo[0] ppdo[2][0] = pdo[32] 47.5.2.13 parallel gpio pad data in register (pgpdi0?pgpdi3) these registers hold the synchronized input value from the pads. see section 3.5, mapping of ports to pgpdo/i registers . address: base + 0x0c00?0x0c0c (4 registers) access: user read/write 0123456789101112131415 r ppdo[x][15:0] w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ppdo[x+1][15:0] w reset 0000000000000000 figure 47-14. parallel gpio pad data out register (pgpdo0?pgpdo3) field description ppdo[x] parallel pad data out write or read the data register that stores the value to be driven on the pad in output mode. accesses to this register location are coherent with accesses to the bit-wise gpio pad data output registers (gpdo). the x and bit index define which ppdo register bit is equivalent to which pdo register bit according to the following equation: ppdo[x][y] = pdo[(x*16)+y]
system integration unit lite (siul) 47-16 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 table 47-15. pgpdi0_3 field descriptions address: base + 0x0c40?0x0c4c (4 registers) access: user read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r ppdi[x][15:0] w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ppdi[x+1][15:0] w reset 0000000000000000 figure 47-15. parallel gpio pad data in register (pgpdi0?pgpdi3) field description ppdi[x] parallel pad data in read the current pad value. accesses to this register location are coherent with accesses to the bit-wise gpio pad data input registers (gpdi). the x and bit index define which ppdi register bit is equivalent to which pdi register bit according to the following equation: ppdi[x][y] = pdi[(x*16)+y]
system integration unit lite (siul) freescale semiconductor 47-17 pxs20 microcontroller reference manual, rev. 1 47.5.2.14 masked parallel gpio pad data out regi ster (mpgpdo0?mpgpdo6) this register can be used to selectively modify the pad values associated to ppdo[x][15:0]. the mpgpdo[x] register may only be accessed with 32-bit writes. 8-bit or 16-bit writes will not modify any bits in the register and cause a transfer error response by the module. read accesses will return 0. table 47-16. mpgpdo0_6 field descriptions address: base + 0x0c80?0x0c98 (7 registers) access: user read/write 0123456789101112131415 r 0000000000000000 w mask[x][15:0] reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000000000000 w mppdo[x][15:0] reset 0000000000000000 figure 47-16. masked parallel gpio pad data out register (mpgpdo0) field description mask[x] [15:0] mask field each bit corresponds to one data bit in the mppdo[x] register at the same bit location. 1: the associated bit value in the mppdo[x] field is written 0: the associated bit value in the mppdo[x] field is ignored mppdo[x] [15:0] masked parallel pad data out write the data register that stores the value to be driven on the pad in output mode. accesses to this register location are coherent with accesses to the bit-wise gpio pad data output registers (gpdo). the x and bit index define which mppdo register bit is equivalent to which pdo register bit according to the following equation: mppdo[x][y] = pdo[(x*16)+y]
system integration unit lite (siul) 47-18 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 47.5.2.15 interrupt filter maximum counter register (ifmc0?ifmc31) these registers are used to confi gure the filter counter associated with each digita l glitch filter. 47.5.2.16 interrupt filter cloc k prescaler register (ifcpr) this register is used to configure a clock prescaler that is used to se lect the clock for all digital filter counters in the siul. address: base + 0x1000?0x107c (32 registers) access: user read/write 0123456789101112131415 r 0000000000000000 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000000000 maxcntx w reset 0000000000000000 figure 47-17. interrupt filter maximum counter register (ifmc0?ifmc31) table 47-17. ifmc0_31 field descriptions field description maxcntx maximum interrupt filter counter setting. filter period = t(ck)*3 (for 2 < maxcnt < 6 ) filter period = t(ck)*maxcntx (for maxcnt = 6,7,.... 15 ) for maxcnt = 0, 1, 2 the filter behaves as all pass filter. maxcntx can be 0 to 15; t(ck): prescaled filter clock period, which is irc clock prescaled to ifcp value; t(irc): basic filter clock period: 62.5 ns (f = 16 mhz).
system integration unit lite (siul) freescale semiconductor 47-19 pxs20 microcontroller reference manual, rev. 1 table 47-18. ifcpr field descriptions 47.6 functional description 47.6.1 general this section provides a functional descripti on of the system integration unit lite. 47.6.2 pad control the siul controls the configurat ion and electrical characteristic of the device pads. it provides a consistent interface for all pads, both on a by-port and a by-bit basis. the siul allows you to configure each pad as either a general purpos e input output pad (gpio) or as one or more al ternate functions (input or output). the pad configuration registers (pcr n , see section 47.5.2.8, pad configuration registers (pcr0?pcr132) ) allow software control of the static electric al characteristics of external pins with a single write. these pcrs are used to configure the following pad features: ? open drain output enable ? input hysteresis enable ? slew rate control ? pull control ? pad assignment ? control of analog path switches ? safe mode configuration address: base + 0x1080 access: user read/write 0123456789101112131415 r 0000000000000000 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000000000 ifcp[3:0] w reset 0000000000000000 figure 47-18. interrupt filter clock prescaler register (ifcpr) field description ifpc [3:0] interrupt filter clock prescaler setting prescaled filter clock period = t(irc) x (ifcp + 1) t(irc) is the internal oscillator period. ifcp can be 0 to 15
system integration unit lite (siul) 47-20 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 47.6.3 general purpose input and output pads (gpio) the siul allows each pad to be c onfigured as either a ge neral purpose input out put pad (gpio), and as one or more alternate functions (i nput or output), the function of wh ich is normally determined by the peripheral that will use the pad. the siul manages gpio pads organize d as ports that can be accessed for data reads and writes as 32-bit, 16-bit or 8-bit. as shown in figure 47-19 , all port accesses are identical with each read or write being performed only at a different location to access a different port width. figure 47-19. data port width configur ations for different port width accesses this implementation requires that the registers are arranged in such a wa y as to support this range of port widths without having to split reads or writes into multiple accesses. the siul has separate data input (gpdi n_n , see section 47.5.2.11, gpio pad data input registers (gpdi) ) and data output (gpdo n_n , see section 47.5.2.10, gpio pad data output registers (gpdo) ) registers for all pads, allowing the possibility of read ing back an input or output value of a pad directly. this allows you to validate the pad configuration rather than confirming the value that wa s written to the data register by accessing the data input registers. the data output registers support both read and writ e operations. the data input registers support read access only. when the pad is configured to use one of its alternat e functions, the data input va lue reflect the respective value of the pad. if a write operation is performed to the data output regi ster for a pad configured as an alternate function (non gpio), this write will not be reflected by th e pad value until rec onfigured to gpio. the allocation of what i nput function is connected to the pin is defined by the psmi registers (pcr n , see section 47.5.2.8, pad configurati on registers (pcr0?pcr132) ). 47.6.4 external interrupts the siul supports 32 external interrupts, eirq0-eirq31. the siul supports four interr upt vectors to the interrupt controller. ea ch vector interrupt has eight external interrupts combined together with the presence of flag generating an interrupt fo r that vector if enabled. all of the external interrupt pads wi thin a single group have equal priority. refer to figure 47-20 for an overview of the exte rnal interrupt implementation: 31 23 siu base+ 0x0000 15 7 0 siu base+ 15 7 0 siu base+ 15 7 0 siu base+ 70 0x0003 siu base+ 70 0x0002 siu base+ 70 0x0001 siu base+ 70 0x0000 0x0002 0x0000 32-bit port 16-bit port 16-bit port 8-bit port 8-bit port 8-bit port 8-bit port
system integration unit lite (siul) freescale semiconductor 47-21 pxs20 microcontroller reference manual, rev. 1 figure 47-20. external interrupt pad diagram 47.6.4.1 external interrupt management each interrupt can be enabled or disabled independently. this can be performed using the interrupt request enable register (irer - section 47.5.2.4, interrupt request enable register (irer) ). a pad defined as an external in terrupt can be configured to recognize interrupts with an active rising edge, an active falling edge or both edges bei ng active. a setting of having both e dge events disabled is reserved and should not be configured. the active eirq edge is controlled through th e configuration of the registers ireer and ifeer. each external interrupt supports an individual flag which is held in the flag register (isr - section 47.5.2.3, interrupt status flag register (isr) ). this register is a writ e-1-to-clear register type, preventing inadvertent overwriting of other flags in the same register. 47.7 pin muxing for pin muxing, see chapter 3, signal description. interrupt controller int vectors eif[31:24] eif[23:16] eif[15:8] eif[7:0] ire[31:0] pads iree[31:0] interrupt edge enable ifee[31:0] falling rising edge detection glitch filter ife[31:0] maxcount[x] irq glitch filter enable glitch filter counter_n ifcp[3:0] glitch filter prescaler interrupt enable or or or or irq_31_24 irq_23_16 irq_15_08 irq_07_00
system integration unit lite (siul) 47-22 freescale semiconductor pxs20 microcontroller reference manual, rev. 1
system status and configuration module (sscm) freescale semiconductor 48-1 pxs20 microcontroller reference manual, rev. 1 chapter 48 system status and configuration module (sscm) 48.1 introduction 48.1.1 overview the system status and configur ation module (sscm), shown in figure 48-1 , provides central device functionality. figure 48-1. sscm block diagram 48.1.2 features the sscm includes these distinctive features: ? system configuration and status ? memory sizes/status ? device mode and security status ? determine boot vector ? search code flash for bootable sector ? dma status ? device identification inform ation (mcu id registers) bus system status and configuration module interface password comparator revid hardmacro core logic system status peripheral interface bus debug port
system status and configuration module (sscm) 48-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? debug status port enable and selection ? bus and peripheral abort enable/disable 48.1.3 modes of operation the sscm operates identically in all system modes. 48.2 external signal description the sscm has no external pins. 48.3 memory map/register definition this section provides a detailed description of all memory-mapped registers in the sscm. table 48-1 shows the memory map for the sscm. note that all addresses are offsets; the absolute address may be calculated by adding the specified offset to the base address of the sscm. all registers are accessible via 8- bit, 16-bit or 32-bit accesses unle ss otherwise noted. however, 16-bit accesses must be aligned to 16-bit boundaries, and 32 -bit accesses must be al igned to 32-bit boundaries. as an example, the status regi ster is accessible by a 16-bit re ad/write to address ?base + 0x0002?, but performing a 16-bit access to ?base + 0x0003? is illegal. table 48-1. module memory map address register size access mode 1 notes: 1 u = user mode, s = supervisor mode, t = test mode, v = dfv mode, a = all (no restrictions) base + 0x0000 system status (status) 16 bits r/w a base + 0x0002 system memory and id (memconfig) 16 bits r a base + 0x0004 reserved 16 bits reads/writes have no effect. a base + 0x0006 error configuration (error) 16 bits r/w a base + 0x0008 debug status port (debugport) 16 bits r/w a base + 0x000a reserved 16 bits reads/writes have no effect. a base + 0x000c password comparison register high word 32 bits r/w a base + 0x0010 password comparison register low word 32 bits r/w a base + 0x0014 reserved 32 bits reads/writes have no effect. a base + 0x0018 dpm boot register 32 bits r a base + 0x001c dpm boot key register 32 bits r a base + 0x0020 user option status register 32 bits r a base + 0x0024 sscm control register 32 bits r/w a base + 0x0028 to base + 0x3fff reserved see note 2 2 if enabled at the soc level, accessing these register addresses will cause bus aborts.
system status and configuration module (sscm) freescale semiconductor 48-3 pxs20 microcontroller reference manual, rev. 1 48.3.1 register descriptions the following registers are available in the sscm. those bits that are shaded out are reserved for future use. to optimize future compatibility, these bits should be masked out during any read/wri te operations to avoid conflict with future revisions. 48.3.1.1 system status register (status) the system status register is a read-only register that reflects the current state of the system. address: base + 0x0000 access: read / write 012 3 456789101112131415 r lsm cer 0 nxen1 nxen pub sec 0 bmode vle abd 0 0 0 w clear reset: 0/1 1 notes: 1 reset value depends on the associated option bit. 00 0 00000/10/10/11 0000 = reserved figure 48-2. status (status) register table 48-2. status allowed register accesses 8-bit 16-bit 32-bit read allowed allowed allowed write allowed allowed allowed table 48-3. status field descriptions field description lsm lock step mode. this field indicates how the two proce ssor cores of the device are used. lock step mode (lsm) is used to increase safety, decoupled parallel mode (dpm) is used to increase performance. 1 device is in lock step mode (lsm) 0 device is in decoupled parallel mode (dpm) note: this field is used only to see what mode (lsm or dpm) the chip is in. to configure the chip to run in one of these modes, see section 4.4, selecting lsm or dpm. cer configuration error. this field indicates that the sscm has detected a configuration error during bootup. 1 device configuration is not correct 0 no configuration problem detected by the sscm nxen1 processor 1 nexus enabled. nxen processor 0 nexus enabled.
system status and configuration module (sscm) 48-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 48.3.1.2 system memory and id register (memconfig) the system memory configur ation register is a read-o nly register that reflects the memory configuration of the system. it also contains the jtag id. pub public serial access status. this bit indicates whether serial boot mode with public password is allowed. 1 serial boot mode with public password is allowed 0 serial boot mode with private flash password is al lowed, provided the key hasn?t been swallowed sec security status. this bit reflects th e current security state of the flash. 1 the flash is secured 0 the flash is not secured vle variable length instruction mode. when booting from flash, th is field indicates that the code stored there is using the vle instruction set. the value of this field is determined by the rchw field of the flash boot sector. 1 main flash contains vle code 0 main flash contains standard ppc code bmode device boot mode. 000 (reserved for flexray boot serial boot loader) 001 can serial boot loader 010 sci serial boot loader 011 single chip 100 expanded chip this field is only updated during reset. abd autobaud. indicates that autobaud detection is active when in sci or can serial boot loader mode. no meaning in other modes. note: autobaud functionality is not supported on this chip. address base + 0x0002 access: read only r 0123456789101112131415 rjpin ivldmrev0 w reset: 0/1 1 notes: 1 reset value is soc-specific. 0/1 1 0/1 1 0/1 1 0/1 1 0/1 1 0/1 1 0/1 1 0/1 1 0/1 1 0/1 2 2 reset value depends on boot mode and securi ty status (see soc documentation). 0/1 1 0/1 1 0/1 1 0/1 1 0 = reserved figure 48-3. system memory and id (memconfig) register table 48-3. status field descriptions (continued) field description
system status and configuration module (sscm) freescale semiconductor 48-5 pxs20 microcontroller reference manual, rev. 1 48.3.1.3 error configuration (error) the error configuration register is a read-write register that controls the error handling of the system. table 48-4. memconfig field descriptions field description jpin jtag part id number ivld instruction flash vali d. this bit identifies whether or not the on-chip instruction fl ash is accessible in the system memory map. the flash may not be accessible due to security limitations, or because there is no flash in the system. 1 instruction flash is accessible 0 instruction flash is not accessible mrev minor mask revision table 48-5. memconfig allowed register accesses 8-bit 16-bit 32-bit read allowed allowed allowed (also reads status register) write not allowed not allowed not allowed address : base + 0x0006 access: read/write 0123456789101112131415 r00000000000000paerae w reset:0000000000000000 = reserved figure 48-4. error confi guration (error) register
system status and configuration module (sscm) 48-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 48.3.1.4 debug status port register (debugport) the debug status port register is us ed to (optionally) provide debug data on a set of pins. consult the soc guide for this information. table 48-6. error field descriptions field description pae peripheral bus abort enable. this bit enables bus aborts on any access to a peripheral slot that is not used on the device. this feature is intended to aid in debugging when developing application code. 1 illegal accesses to non-existing peripherals produce a prefetch or data abort exception 0 illegal accesses to non-existing peripherals do not produce a prefetch or data abort exception rae register bus abort enable. this bit enables bus aborts on illegal accesses to off-platform peripherals. illegal accesses are defined as reads or writes to reserved addresses within the address space for a particular peripheral. this feature is intended to aid in de bugging when developing application code. 1 illegal accesses to peripherals produce a prefetch or data abort exception 0 illegal accesses to peripherals do not produce a prefetch or data abort exception note: transfers to peripheral bus resources may be aborted even before they reach the peripheral bus (i.e. at the aips level). in this case, the per_abort and reg_abort register bits will have no effect on the abort. table 48-7. error allowed register accesses 8-bit 16-bit 32-bit read allowed allowed allowed write allowed allowed not allowed address: base + 0x0008 access: read/write 0123456789101112131415 r0000000000000debug_mode w reset:0000000000000000 = reserved for future use figure 48-5. debug status port (debugport) register
system status and configuration module (sscm) freescale semiconductor 48-7 pxs20 microcontroller reference manual, rev. 1 48.3.1.5 password comparison registers (pwcmph and pwcmpl) these registers allow to unsecure the device, if the co rrect password is known. they are intended for device-internal operation only. table 48-8. debugport field descriptions field description debug_ mode debug status port mode. this field selects the al ternate debug functionality for the debug status port 000 no alternate functionality selected 001 mode 1 selected 010 mode 2 selected 011 mode 3 selected 100 mode 4 selected 101 mode 5 selected 110 mode 6 selected 111 mode 7 selected ta b l e 4 8 - 9 describes the functionality of the debug status port in each mode. table 48-9. debug status port modes pin 1 notes: 1 all signals are active high, unless otherwise noted mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 0 status[0] status[8] memconfig[0] memconfig[8] reserved reserved reserved 1 status[1] status[9] memconfig[1] memconfig[9] reserved reserved reserved 2 status[2] status[10] memconfig[2] memconfig[10] reserved reserved reserved 3 status[3] status[11] memconfig[3] memconfig[11] reserved reserved reserved 4 status[4] status[12] memconfig[4] memconfig[12] reserved reserved reserved 5 status[5] status[13] memconfig[5] memconfig[13] reserved reserved reserved 6 status[6] status[14] memconfig[6] memconfig[14] reserved reserved reserved 7 status[7] status[15] memconfig[7] memconfig[15] reserved reserved reserved table 48-10. debugport allowed register accesses 8-bit 16-bit 32-bit read allowed allowed not allowed write allowed allowed not allowed
system status and configuration module (sscm) 48-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 address: 0x000c access: read/write 0123456789101112131415 r0000000000000000 wpwd_hi reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 wpwd_hi reset0000000000000000 figure 48-6. password comparison register high word (pwcmph) address: 0x0010 access: read/write 0123456789101112131415 r0000000000000000 w pwd_lo reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w pwd_lo reset0000000000000000 figure 48-7. password comparison register low word (pwcmpl) table 48-11. password comparison register field descriptions field description pwd_hi upper 32 bits of the password pwd_lo lower 32 bits of the password table 48-12. pwcmph/l allowed register accesses 8-bit 16-bit 32-bit 1 notes: 1 all 32-bit accesses must be aligned to 32-bit addresses (i.e. 0x0, 0x4, 0x8 or 0xc). read allowed allowed allowed write not allowed not allowed allowed
system status and configuration module (sscm) freescale semiconductor 48-9 pxs20 microcontroller reference manual, rev. 1 in order to unsecure the device, the password need s to be written first the upper word to the pwcmph register, then the lower word to the pwcmpl regist er. the sscm will then insert a delay, compare the password and if the password is correct, unlock the device. 48.3.1.6 dpm boot register (dpmboot) address: base + 0x0018 access: read/write 0123456789101112131415 rp2boot w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rp2boot dvle 0 w reset: 0000000000000000 = writes have no effect on this bit figure 48-8. dpm boot (dpmboot) register table 48-13. dpmboot field descriptions field description p2boot determines the location from which the 2nd processor will bo ot, once the main processor releases it from reset. this field is only used if the device is operating in dpm mode. dvle determines whether the 2nd processor will start executing vle mode (1=vle mode, 0=booke mode). this field is only used if the device is operating in dpm mode.
system status and configuration module (sscm) 48-10 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 48.3.1.7 boot key register (dpmkey) address: base + 0x001c access: read/write 0123456789101112131415 r0000000000000000 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w key reset: 0000000000000000 = writes have no effect on this bit figure 48-9. boot key register (dpmkey) register table 48-14. dpmkey field descriptions field description key control key. this field is used to activate the second core in dp mode. the sequence following sequece is required: - write to the dpmboot register - write the value 0101101011110000 (0x5af0) to the key field - write the value 1010010100001111 (0xa50f) to the key field after this the second core will start executing from the address specified in the dpmboot register.
system status and configuration module (sscm) freescale semiconductor 48-11 pxs20 microcontroller reference manual, rev. 1 48.3.1.8 user option status register (uops) 48.3.1.9 sscm control register (sctr) address: base + 0x0020 access: read only 0123456789101112131415 ruopt w reset: varies depending on the contents of the shadow block 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ruopt w reset: varies depending on the contents of the shadow block = writes have no effect on this bit figure 48-10. user option status (uops) register table 48-15. uops field descriptions field description uopt shows the values read from the user option bits location in the flash memory (see section 23.1.7, user option bits ). address: base + 0x0024 access: read/write 0123456789101112131415 r0000000000000000 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000tfe00 w reset: 0000000000000000 = writes have no effect on this bit figure 48-11. sscm control (sctr) register
system status and configuration module (sscm) 48-12 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 48.4 functional description the primary purpose of the sscm is to provide information about the cu rrent state and configuration of the system that may be useful for configuring application softwa re and for debug of the system. 48.5 initialization/application information 48.5.1 reset the reset state of each individual bit is shown within the register description section (see section 48.3.1, register descriptions ). table 48-16. sctr field descriptions field description tfe test flash enable - setting this bit will map the testflash array to offset 0 of the flash address space. this bit can only be set one time. once it has been set and cleared it will re main cleared until the next device reset. note that it is not possible to access the main flash memory array while tfe is set.
system timer module (stm) freescale semiconductor 49-1 pxs20 microcontroller reference manual, rev. 1 chapter 49 system timer module (stm) 49.1 introduction 49.1.1 overview the system timer module (stm) is a 32-bit timer designed to suppor t commonly required system and application software timing func tions. the stm includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. the counter is driven by the system clock divided by an 8-bit prescale value (1 to 256). 49.1.2 features the stm has the following features: ? one 32-bit up counter with 8-bit prescaler ? four 32-bit compare channels ? independent interrupt source for each channel ? counter can be stopped in debug mode 49.1.3 modes of operation the stm supports two device modes of operation: nor mal and debug. when the st m is enabled in normal mode, its counter runs continuously. in debug mode, operation of the counter is controlled by the frz bit in the stm_cr register. if the frz bi t is set, the counter is stopped in debug mode, otherwise it continues to run. 49.2 external signal description the stm does not have any external interface signals. 49.3 memory map and register definition the stm programming model has fourt een 32-bit registers. the stm regi sters can only be accessed using 32-bit (word) accesses. attempted refe rences using a different size or to a reserved address generates a bus error termination. 49.3.1 memory map the stm memory map is shown in table 49-1 .
system timer module (stm) 49-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 49.3.2 register descriptions the following sections detail the individua l registers within the stm programming model. figure 49-1 shows the conventions used in the register figures. 49.3.2.1 stm control register (stm_cr) the stm control register (stm_cr) includes the prescale value, free ze control and timer enable bits. table 49-1. stm memory map address offset register name register description size (bits) access location 0x0000 stm_cr stm control register 32 r/w on page 49-2 0x0004 stm_cnt stm counter value 32 r/w on page 49-3 0x0008 reserved 32 r/w 0x000c reserved 32 r/w 0x0010 stm_ccr0 stm channel 0 control register 32 r/w on page 49-4 0x0014 stm_cir0 stm channel 0 interrupt register 32 r/w on page 49-4 0x0018 stm_cmp0 stm channel 0 compare register 32 r/w on page 49-5 0x001c reserved 32 r/w 0x0020 stm_ccr1 stm channel 1 control register 32 r/w on page 49-4 0x0024 stm_cir1 stm channel 1 interrupt register 32 r/w on page 49-4 0x0028 stm_cmp1 stm channel 1 compare register 32 r/w on page 49-5 0x002c reserved 32 r/w 0x0030 stm_ccr2 stm channel 2 control register 32 r/w on page 49-4 0x0034 stm_cir2 stm channel 2 interrupt register 32 r/w on page 49-4 0x0038 stm_cmp2 stm channel 2 compare register 32 r/w on page 49-5 0x003c reserved 32 r/w 0x0040 stm_ccr3 stm channel 3 control register 32 r/w on page 49-4 0x0044 stm_cir3 stm channel 3 interrupt register 32 r/w on page 49-4 0x0048 stm_cmp3 stm channel 3 compare register 32 r/w on page 49-5 0x004c - 0x3fff reserved always reads 1 1always reads 0 0r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0n/a bit w1c bit figure 49-1. key to register fields
system timer module (stm) freescale semiconductor 49-3 pxs20 microcontroller reference manual, rev. 1 table 49-2. stm_cr field descriptions 49.3.2.2 stm count register (stm_cnt) the stm count register (stm_cnt) holds the timer count value. offset 0x000 access: read/write 0123456789101112131415 r 0 0 0 0 0 00000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cps 0 0 00 00 frz ten w reset0000000000000000 figure 49-2. stm control register (stm_cr) field description cps counter prescaler. selects the clock divide value for the prescaler (1 - 256). 0x00 = divide system clock by 1 0x01 = divide system clock by 2 ... 0xff = divide system clock by 256 frz freeze. allows the timer counter to be stopped when the device enters debug mode. 0 = stm counter continues to run in debug mode. 1 = stm counter is stopped in debug mode. ten timer counter enabled. 0 = counter is disabled. 1 = counter is enabled. offset 0x004 access: read/write 012345678910111213141516171819202122232425262728293031 r cnt w reset00000000000000000000000000000000 figure 49-3. stm count register (stm_cnt)
system timer module (stm) 49-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 table 49-3. stm_cnt field descriptions 49.3.2.3 stm channel cont rol register (stm_ccrn) the stm channel control register (stm_ccrn) has the enable bit for channel n of the timer. table 49-4. stm_ccrn field descriptions 49.3.2.4 stm channel interrupt register (stm_cirn) the stm channel interrupt register (stm_cirn) has the interrupt flag for channel n of the timer. field description cnt timer count value used as the time base for all chan nels. when enabled, the counter increments at the rate of the system clock divided by the prescale value. offset 0x10+0x10*n access: read/write 0123456789101112131415 r 0 0 0 0 0 00000000 0 00 w reset0000000000000 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 00000000 0 0 0 000 cen w reset0000000000000 0 00 figure 49-4. stm channel control register (stm_ccrn) field description cen channel enable. 0 = the channel is disabled. 1 = the channel is enabled.
system timer module (stm) freescale semiconductor 49-5 pxs20 microcontroller reference manual, rev. 1 table 49-5. stm_cirn field descriptions 49.3.2.5 stm channel comp are register (stm_cmpn) the stm channel compare regi ster (stm_cmpn) holds the compare value for channel n. table 49-6. stm_cmpn register field descriptions offset 0x14+0x10*n access: read/write 0123456789101112131415 r 0 0 0 0 0 00000000 0 00 w reset0000000000000 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 00000000 0 0 0 000cif w w1c reset0000000000000 0 00 figure 49-5. stm channel interrupt register (stm_cirn) field description cif channel interrupt flag 0 = no interrupt request. 1 = interrupt request due to a match on the channel. offset 0x18+0x10*n access: read/write 012345678910111213141516171819202122232425262728293031 r cmp w reset00000000000000000000000000000000 figure 49-6. stm channel compare register (stm_cmpn) field description cmp compare value for channel n. if the stm_ccrn[cen] bit is set and the stm_cmpn register matches the stm_cnt register, a channel interrupt request is generated and the stm_cirn[cif] bit is set.
system timer module (stm) 49-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 49.4 functional description the system timer module (stm) is a 32-bit timer designed to suppor t commonly required system and application software timing func tions. the stm includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. the stm has one 32-bit up counter (stm_cnt) that is used as the time base for all channels. when enabled, the counter increments at the system clock frequency divided by a prescale value. the stm_cr[cps] field sets the divider to any value in the range from 1 to 256. the counter is enabled with the stm_cr[ten] bit. when enabled in normal m ode the counter continuously increments. when enabled in debug mode the coun ter operation is controlled by the stm_cr[frz] bit. when the stm_cr[frz] bit is set, the counter is stopped in debug mode, otherw ise it continues to run in debug mode. the counter rolls over at 0xffff_ffff to 0x0000_0000 with no restrictions at this boundary. the stm has four identical compare channels. e ach channel includes a channel control register (stm_ccrn), a channel interrupt re gister (stm_cirn) and a channe l compare register (stm_cmpn). the channel is enabled by setting the stm_ccrn[cen ] bit. when enabled, the channel will set the stm_cir[cif] bit and generate an interrupt request when the channel compare register matches the timer counter. the interrupt request is cl eared by writing a 1 to the stm_cirn[cif] bit. a write of 0 to the stm_cirn[cif] bit has no effect. note stm counter does not advance when the system clock is stopped.
temperature sensor (tsens) freescale semiconductor 50-1 pxs20 microcontroller reference manual, rev. 1 chapter 50 temperature sensor (tsens) 50.1 introduction the tsens module provides an analog voltage that is proportional to the internal temperature of the pxs20. this voltage can be sampled by the adc and converted to an actual temperature by using factory-programmed ca libration constants. figure 50-1 shows a block diagram of the tsens module. the module operates on the principles of a basic silicon bandgap sensor that measures the difference in base-emi tter voltages of multiple transistors, which can be related to the abso lute temperature of the device. figure 50-1. tsens block diagram 50.2 features the tsens has the following features: ? temperature monitoring range: ?40?150 ? c ? sensitivity: approximately 5.14 mv/ ? c 50.3 signals the tsens does not use any input signals external to the device. the tsens outputs one analog signal, v tsens . depending on the tsens mode of operation, v tsens is proportional or inversely proportional to the device temperature. see chapter 9, analog-to-digital converter (adc) , for information on which adc channels are connected to v tsens . 50.4 modes of operation the tsens has two modes of operation: ? proportional to absolute temperature (ptat) ? v tsens increases linearly with increasing temperature sensing diodes bias v be0 v be1 level shifter + logic analog delay 2-to-1 mux 1 2-to-1 mux 2 instr. amp v tsens mode adc ctr1[tsensor_sel] select
temperature sensor (tsens) 50-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 ? complementary to absolute temperature (ctat) ? v tsens decreases linearly with increasing temperature the mode of operation is controll ed by the ctr1[tsensor_sel] field in the adc, as described in section 9.3.10.2, conversion timing register 1 (ctr1) . 50.5 obtaining the device temperature using tsens in order to obtain the device temperat ure using tsens, you must do the following: ? extract the necessary tsens calibration consta nts from the pxs20 test flash memory (see section 50.5.1, tsens calibration constants ) ?measure v tsens in ptat and ctat modes ? calculate the device temperature using the equations in section 50.5.2, equations for converting tsens voltage to device temperature the need for the measurements in two different modes is driven by th e fact that alt hough the tsens output is linear in either mode , the intercept of the v tsens -t plot varies si gnificantly based on the adc reference voltage. performing the two measurem ents allows the resulting equati ons to be independent of this reference voltage. 50.5.1 tsens calibra tion constants the equations needed to convert vt sens to a device temp erature depend on four ca libration constants as described in table 50-1 . these constants are determined during fact ory testing of the px s20 and stored in the pxs20 test flash memory as specified in section 23.1.8, test flash memory . 50.5.2 equations for converting ts ens voltage to device temperature in the equations below: ?v p is the v tsens output in ptat mode in v ?v c is the v tsens output in ctat mode in v ?p n and c n are the calibration c onstants described in section 50.5.1, tsens cali bration constants ? t is the device temperature in ? c first, calculate the constant factor k: table 50-1. tsens calibration constants constant description p 1 ptat voltage (in v) measured at 150 ? c p 2 ptat voltage (in v) measured at -40 ? c c 1 ctat voltage (in v) measured at 150 ? c c 2 ctat voltage (in v) measured at -40 ? c
temperature sensor (tsens) freescale semiconductor 50-3 pxs20 microcontroller reference manual, rev. 1 next, calculate the bandgap voltage v bgap : next, calculate three ratios r as follows: finally, calculate the device temperature: k p 1 p 2 ? c 2 c 1 ? ------------------ = v bgap v p kv c ? + = r 1 p 1 c 1 ? v bgap ----------------- - = r 2 p 2 c 2 ? v bgap ----------------- - = r v p v c ? v bgap ------------------ - = t 40 ? 150 rr 2 ? ?? ? r 1 r 2 ? ?? --------------------------------- - + =
temperature sensor (tsens) 50-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1
wakeup unit (wkpu) freescale semiconductor 51-1 pxs20 microcontroller reference manual, rev. 1 chapter 51 wakeup unit (wkpu) 51.1 introduction 51.1.1 overview the wkpu supports one external source that can cause non-maskable interrupt re quests or wakeup events. figure 51-1 is a block diagram of the wkpu and it s interfaces to other system components. figure 51-1. wkpu block diagram 51.1.2 features the wkpu supports: ? 1 nmi source ? 1 analog glitch filter ? independent interrupt destination: non-maskable interrupt, critical inte rrupt, or machine check request ? edge detection ? cconfigurable system wakeup tri ggering from a detected nmi event ips bus pad s pbridge mode / power ctl wakeup 0 cpu cores 0 nmi / wakeup - configuration wakeup unit iomux 0 0 filter filter bypass nmi enable
wakeup unit (wkpu) 51-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 51.2 external signal description the nmi input pin can be used as a non-maskable interrupt source in nor mal run mode or as a chip wakeup source during stop0 mode. note be aware that the wakeup pins are en abled in all modes. therefore, the wakeup pins should be correctly term inated to ensure minimal current consumption. any unused wakeup signal input should be terminated by using an external pull-up or pull-down. 51.3 memory map and register description this section provides a detailed description of all registers accessibl e in the wkpu module. 51.3.1 memory map figure 51-1 gives an overview on the wkpu registers implemented. note reserved registers will read as 0, writ es will have no effect . if supported and enabled by the chip, a transfer error wi ll be issued when trying to access completely reserved register space. 51.3.2 register descriptions this section describes in address order all the wkpu registers. each description includes a standard register diagram with an associated figure number. details of register bit and field function follow the register diagrams, in bit order. 51.3.2.1 nmi status flag register (nsr) this register holds the non-mask able interrupt status flags. table 51-1. wkpu memory map address offset use abbreviation size supported access sizes 0x0000 nmi status flag register nsr 32 32/16/8 0x0004 - 0x0007 reserved 0x0008 nmi configuration register ncr 32 32/16/8 0x000c - 0x3fff reserved figure 51-2. key to register fields always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit
wakeup unit (wkpu) freescale semiconductor 51-3 pxs20 microcontroller reference manual, rev. 1 51.3.2.2 nmi configurat ion register (ncr) this register holds the configuration bits for the non-maskable interrupt settings. address: 0x0000 access: user read/write (write 1 to clear) 01234567 r nif0novf0000000 ww1c w1c reset00000000 8 9 10 11 12 13 14 15 r00000000 w reset00000000 16 17 18 19 20 21 22 23 r00000000 w reset00000000 24 25 26 27 28 29 30 31 r00000000 w reset00000000 figure 51-3. nmi status flag register (nsr) table 51-2. nsr field descriptions field description nif0 nmi status flag 0. this flag can be cleared only by writing a 1. writing a 0 has no effect. if enabled (nree0 or nfee0 set), nif0 causes an interrupt request. 1 an event as defined by nree0 and nfee0 has occurred 0 no event has occurred on the pad novf0 nmi overrun status flag 0. this flag can be clea red only by writing a 1. writing a 0 has no effect. it will be a copy of the current nif0 value whenever a nmi event occurs, thereby indicating to the software that a nmi occurred while the last one wa s not yet serviced. if enabled (nree0 or nfee0 set), novf0 causes an interrupt request. 1 an overrun has occurred on nmi pin 0 no overrun has occurred on nmi pin
wakeup unit (wkpu) 51-4 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 address: 0x0008 access: user read/write 01234567 r nlock0 ndss0 nwre0 0 nree0 nfee0 nfe0 w reset00000000 8 9 10 11 12 13 14 15 r00000000 w reset00000000 16 17 18 19 20 21 22 23 r00000000 w reset00000000 24 25 26 27 28 29 30 31 r00000000 w reset00000000 figure 51-4. nmi config uration register (ncr) table 51-3. ncr field descriptions field description nlock0 nmi configuration lock register 0. writing a 1 to this bit locks the configurat ion for the nmi until it is unlocked by a system reset. writing a 0 has no effect. ndss0 nmi destination source select 0. 00 non-maskable interrupt 01 critical interrupt 10 machine check request 11 reserved - no nmi, critical interrupt, or machine check request generated
wakeup unit (wkpu) freescale semiconductor 51-5 pxs20 microcontroller reference manual, rev. 1 note writing a ?0? to both nree0 and nf ee0 disables the nmi functionality completely (i.e. no system wakeup or interrupt will be generated on any pad activity)! 51.4 functional description 51.4.1 general this section provides a complete f unctional description of the wkpu. 51.4.2 non-maskable interrupts the wkpu supports one non-maskable interrupt. the wkpu supports the generation of 3 types of in terrupts for the nmi input pin. the wkpu supports the capturing of a second event before the interrupt is cleared, thus re ducing the chance of losing an nmi event. nmi passes through a bypassabl e analog glitch filter. note glitch filter control a nd pad configuration should be done while the nmi is disabled in order to avoid erroneou s triggering by glitches caused by the configuration process itself. nwre0 nmi wakeup request enable 0. 1 a set nif0 bit or set novf0 bit causes a system wakeup request 0 system wakeup requests from the corresponding nif0 bit are disabled nree0 nmi rising-edge events enable 0. 1 rising-edge event is enabled 0 rising-edge event is disabled nfee0 nmi falling-edge events enable 0. 1 falling-edge event is enabled 0 falling-edge event is disabled nfe0 nmi filter enable 0. enable analog glitch filter on the nmi pad input. 1 filter is enabled 0 filter is disabled table 51-3. ncr field descriptions (continued) field description
wakeup unit (wkpu) 51-6 freescale semiconductor pxs20 microcontroller reference manual, rev. 1 figure 51-5. nmi pad diagram 51.4.2.1 nmi management the nmi can be enabled or disabled as required by the application. this can be performed using the single ncr register laid out to contain all confi guration bits in a single byte (see figure 51-4 ). the nmi pin can be configured by the user to recogn ize interrupts with an active rising edge, an active falling edge or both edges being active. a setti ng of having both edge events disabled results in no in terrupt being detected and should not be configured. the active nmi edge is controlled by the user th rough the configuration of the nree and nfee bits. note after reset, nree and nfee are set to ?0?, therefore the nmi functionality is disabled after reset and must be enabled explicitly by software. the nmi destination interrupt is c ontrolled by the user through the c onfiguration of the ndss bits. see table 51-3 for details. the nmi supports a status flag and an overrun flag which are located in the nsr register (see figure 51-3 ). this register is a clear-by-write-1 register type, pr eventing inadvertent overwriti ng of other flags in the same register. the stat us flag is set whenever an nmi event is detected. the overrun flag is set whenever an nmi event is detected and the status fl ag is set (i.e. has not yet been cleared). glitch filter edge detect flag overrun destination nmi critical irq machine check wakeup enable cpu mode/ pwr ctl ndss[0] nwre[0] nree[0] nfee[0] nfe[0] nmi configuration register (ncr) nmi
wakeup unit (wkpu) freescale semiconductor 51-7 pxs20 microcontroller reference manual, rev. 1 note the overrun flag is cleared by writing a ?1? to the appropriate overrun bit in the nsr register. if the status bit is cl eared and the overrun b it is still set, the pending interrupt will not be cleared.
wakeup unit (wkpu) 51-8 freescale semiconductor pxs20 microcontroller reference manual, rev. 1
revision history freescale semiconductor a-1 pxs20 microcontroller reference manual, rev. 1 appendix a revision history this appendix describes corrections to the pxs20 microcontroller reference manual . for convenience, the corrections ar e grouped by revision. since this is the first revision of this document, there are no changes.
revision history a-2 freescale semiconductor pxs20 microcontroller reference manual, rev. 1


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