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features ? core ? arm926ej-s? arm ? thumb ? processor running up to 400 mhz @ 1.0v +/- 10% ? 16 kbytes data cache, 16 kbytes inst ruction cache, memory management unit ? memories ? one 128-kbyte internal rom embedding secure bootstrap routine ? one 32-kbyte internal sram, single-cycle access at system speed ? 32-bit external bus interface supp orting 8-bank ddr2/lp ddr, sdr/lpsdr, static memories ? mlc/slc nand controller, with up to 24-bit programmable multi-bit error correcting code (pmecc) ? system running up to 133 mhz ? power-on reset, reset controller, shut down controller, periodic interval timer, watchdog timer and real time clock ? boot mode select option, remap command ? internal low power 32 khz rc and fast 12 mhz rc oscillators ? selectable 32768 hz low-power oscillator, 16 mhz oscillator, one pll for the system and one pll optimized for usb ?six 32-bit-layer ahb bus matrix ? dual peripheral bridge with dedicated programmable clock ? one dual port 8-channel dma controller ? advanced interrupt controller and debug unit ? two programmable exte rnal clock signals ? low power mode ? shut down controller with four 32-bit battery backup registers ? clock generator and power management controller ? very slow clock operating mode, software pr ogrammable power optimization capabilities ? peripherals ? lcd controller ? usb device full speed with dedicated on-chip transceiver ? usb host full speed with dedicated on-c hip transceiver ? one high speed sd card and sdio host controller ? two master/slave serial peripheral interfaces ? two three-channel 32-bit timer/counters ? one synchronous serial controller ? one four-channel 16-bit pwm controller ? two two-wire interfaces ? four usarts plus two uarts ? one 12-channel 10-bit analog-to-digital converter with up to 5-wire resistive touch screen support ? write protected registers ? cryptography ? trng true random number generator compliant with nist special publication 800-22 ? aes 256-, 192-, 128-bit key algorithm compliant with fips publication 197 ? sha (sha1 and sha256) complian t with fips publication 180-2 ? 256 fuse bits for crypto key and 64 fuse bits for device configuration, including jtag disable and forced boot from the on-chip rom ? i/o ? four 32-bit parallel input/output controllers ? 105 programmable i/o lines multiplexed with up to three peripheral i/os ? input change interrupt capability on each i/o line, optional schmitt trigger input ? individually programmable open-drain, pull-up and pull-down resistor, synchronous output ? packages: 217-ball bga, pitch 0.8 mm, and 247-ball bga, pitch 0.5 mm at91sam arm-based embedded mpu sam9n12 SAM9CN11 sam9cn12 11063gCatarmC09-oct-12
2 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1. description the arm926ej-s based sam9cn12 features the frequently requested combination of user interface functionality and high data rate connectivity, including lcd controller, resistive touch-screen, multiple uart s, spi, i2c, full speed usb host and device and sdio. the sam9cn12 supports the latest generation of lpddr/ddr2 and nand flash memory interfaces for program and data storage. an internal 133 mhz multi-layer bus architecture associated with 8 dma channels, a distributed memory including a 32-kbyte sram, sustains the high bandwidth required by the processor and the high speed peripherals. embedded on sam9cn12, on-chip hardware accelerators with dma support, enable high- speed data encryption and authentication of the transferred data or application. supported standards are up to 256-bit aes, and fips publication 180-2 compliant sha1 and sha256. a true random number generator is embedded for key generation and exchange protocols. there are fuse bits for crypto key (sam9cn12), user configuration (sam9n12 and SAM9CN11) and device configuration (all). sam9cn12 includes a secured boot rom. sam9n12 and SAM9CN11 include a standard boot rom. the i/os support 1.8v or 3.3v operation, which are independently configurable for the mem- ory interface and peripheral i/os. this feature completely eliminates the need for any external level shifters. in addition it supports 0.8 ball pitch package for low cost pcb manufacturing. the sam9cn12 power management controller features efficient clock gating and a battery backup section minimizing power consumption in active and standby modes. there are several devices. the following table shows the embedded features. table 1-1. devices device sam9n12 SAM9CN11 sam9cn12 standard boot with bsc x x - secured boot - - x trng x x x aes - x x sha - x x
3 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 2. block diagram figure 2-1. sam9n12/cn11/cn12 block diagram aic apb plla system controller pmc pit wdt osc 32k shdc rstc por dbgu 4 gpbr usart0 usart1 usart2 usart3 spi0 osc16m piob por pioc rtc rc piod ssc pio pio arm926ej-s jtag / boundary scan in-circuit emulator mmu bus interface id icache 16 kbytes dcache 16 kbytes pioa npcs2 npcs1 spck mosi miso npcs0 npcs3 rts0-3 sck0-3 txd0-3 rdx0-3 adoul tsadtrig tsadvreff gndana vddana ad1ur ad2ll ad3lr ad4pi gpad5-gpad11 cts0-3 tdi tdo tms tck jtagsel rtck bms fiq irq drxd dtxd pck0-pck1 vddbu shdn wkup xin nrst xout xin32 xout32 vddcore ntrst tc0 tc1 tc2 tc3 tc4 tc5 12m rc utxd0-utxd1 urdx0-urdx1 uart0 uart1 spi1 hsmci0 sd/sdio fifo mci0_ck mci0_da0-mci0_da3 mci0_cda lcd dma 12-ch 10-bit adc touchscreen pio pwm peripheral bridge peripheral bridge tk tf td rd rf rk 8-ch dma pwm0-pwm3 ebi static memory controller d0-d15 a0/nbs0 ncs0 ncs1/sdcs nrd nwr0/nwe nwr1/nbs1 sdck, #sdck, sdcke ras, cas sdwe, sda10 a1/nbs2/nwr2/dqm2 nandoe, nandwe nwait ncs2, ncs3, ncs4, ncs5 nandcs dqm[0..1] dqs[0..1] nandale, nandcle pio d16-d31 nwr3/nbs3/dqm3 a20-a25 twi0 twi1 twck0-twck1 twd0-twd1 multi-layer ahb matrix ddr2/lpddr sdr/lpsdr controller sram 32 kbytes a2-a15, a19 a16/ba0 a18/ba2 a17/ba1 nand flash controller pmecc pmerrloc tclk0-tclk5 tioa0-tioa5 tiob0-tiob5 lcddat0-lcddat23 lcdvsync,lcdhsync lcdpck ldden,lcdpwm lcddisp aes * trng sha * usb fs ohci dma hdp hdm usb fs device ddm ddp transceiver dpram transceiver fuse box pllb rom 128 kbytes * except sam9n12
4 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 3. signal description table 3-1 gives details on the signal names classified by peripheral. table 3-1. signal description list signal name function type active level clocks, oscillators and plls xin main oscillator input input xout main oscillator output output xin32 slow clock oscillator input input xout32 slow clock oscillator output output vbg bias voltage reference for usb analog pck0 - pck1 programmable clock output output shutdown, wakeup logic shdn shut-down control output wkup wake-up input input ice and jtag tck test clock input tdi test data in input tdo test data out output tms test mode select input jtagsel jtag selection input rtck return test clock output reset/test nrst microcontroller reset i/o low ntrst test reset signal input bms boot mode select input debug unit - dbgu drxd debug receive data input dtxd debug transmit data output advanced interrupt controller - aic irq external interrupt input input fiq fast interrupt input input pio controller - pioa - piob - pioc - piod pa0 - pa31 parallel io controller a i/o pb0 - pb18 parallel io controller b i/o pc0 - pc31 parallel io controller c i/o pd0 - pd21 parallel io controller d i/o
5 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 external bus interface - ebi d0 -d15 data bus i/o d16 -d31 data bus i/o a0 - a25 address bus output nwait external wait signal input low static memory controller - smc ncs0 - ncs5 chip select lines output low nwr0 - nwr3 write signal output low nrd read signal output low nwe write enable output low nbs0 - nbs3 byte mask signal output low nand flash support nfd0-nfd15 nand flash i/o i/o nandcs nand flash chip select output low nandoe nand flash output enable output low nandwe nand flash write enable output low ddr2/sdram/lpddr controller sdck,#sdck ddr2/sdram differential clock output sdcke ddr2/sdram clock enable output high sdcs ddr2/sdram controller chip select output low ba[0..2] bank select output low sdwe ddr2/sdram write enable output low ras - cas row and column signal output low sda10 sdram address 10 line output dqs[0..1] data strobe i/o dqm[0..3] write data mask output high speed multimedia card interface - hsmci mci_ck multimedia card clock i/o mci_cda multimedia ca rd slot command i/o mci_da0 - mci_da7 multimedia card slot data i/o universal synchronous asynchrono us receiver transmitter- usartx sckx usartx serial clock i/o txdx usartx transmit data output rxdx usartx receive data input rtsx usartx request to send output ctsx usartx clear to send input table 3-1. signal description list (continued) signal name function type active level
6 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 universal asynchronous receiver transmitter - uartx utxdx uartx transmit data output urxdx uartx receive data input synchronous serial controller - ssc td ssc transmit data output rd ssc receive data input tk ssc transmit clock i/o rk ssc receive clock i/o tf ssc transmit frame sync i/o rf ssc receive frame sync i/o timer counter - tcx x=0..5 tclkx tc channel x external clock input input tioax tc channel x i/o line a i/o tiobx tc channel x i/o line b i/o serial peripheral interface - spix spix_miso master in slave out i/o spix_mosi master out slave in i/o spix_spck spi serial clock i/o spix_npcs0 spi peripheral chip select 0 i/o low spix_npcs1- spix_npcs3 spi peripheral chip select output low two-wire interface -twix twdx two-wire serial data i/o twckx two-wire serial clock i/o pulse width modulation controller- pwm pwm0 - pwm3 pulse width modulation output output usb device full speed port - udp ddp usb device data + analog ddm usb device data - analog usb host full speed port - uhp hdp usb host data + analog hdm usb host data - analog lcd controller - lcdc lcddat 0-23 lcd data bus output lcdvsync lcd vertical synchronization output lcdhsync lcd horizontal synchronization output lcdpck lcd pixel clock output table 3-1. signal description list (continued) signal name function type active level
7 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 when reset state is stated, the configuration is defined by the reset state column of the pin description table. lcdden lcd data enable output lcdpwm lcd contrast control output lcddisp lcd display enable output analog-to-digital converter - adc ad0 xp_ul top/upper left channel analog ad1 xm_ur bottom/upper right channel analog ad2 yp_ll right/lower left channel analog ad3 ym_sense left/sense channel analog ad4 lr lower right channel analog ad5-ad11 7 analog inputs analog adtrg adc trigger input advref adc reference analog table 3-1. signal description list (continued) signal name function type active level table 3-2. sam9n12/cn11/cn12 i/o type description i/o type signal name voltag e range analog pull-up pull-up value (ohm) pull-down pull-down value (ohm) schmitt trigger gpio all pio lines except following 1.65-3.6v switchable 50-100k switchable 50-100k switchable gpio_clk mcick, spi0spck, spi1spck 1.65-3.6v switchable 50-100k switchable 50-100k switchable gpio_clk2 lcddotck 1.65-3.6v switchable 50-100k switchable 50-100k switchable gpio_ana adx, gpadx 3.0-3.6v i switchable 50-100k switchable ebi all data lines (input/output) except the following 1.65-1.95v, 3.0-3.6v switchable 50-100k switchable 50-100k ebi_o all address and control lines (output only) except the following 1.65-1.95v, 3.0-3.6v reset state 50-100k reset state 50-100k ebi_clk sdck, #sdck 1.65-1.95v, 3.0-3.6v rstjtag nrst, ntrst, bms, tck, tdi, tms, tdo, rtck 3.0-3.6v reset state 100k reset state 100k reset state sysc wkup, shdn, jtagsel, shdn 1.65-3.6v reset state 100k reset state 15k reset state vbg vbg 0.9-1.1v i usbfs hdp, hdm, ddp, ddm 3.0-3.6v i/o clock xin, xout, xin32, xout32 1.65-3.6v i/o
8 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 4. package and pinout the sam9cn12 is available in 217-ball and 247-ball bga packages. 4.1 mechanical overview of the 217-ball bga package figure 4-1 shows the orientation of the 217-ball bga package figure 4-1. orientation of the 217-ball bga package 4.2 mechanical overview of the 247-ball bga package figure 4-2 shows the orientation of the 247-ball bga package figure 4-2. orientation of the 247-ball bga package top view ball a1 12 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 abcdefghj kl m nprtu bottom view ball a1
9 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 4.3 217-ball bga package pinout table 4-1. bga217 pin description ball power rail i/o type primary alternate pio peripheral a pio peripheral b pio peripheral c reset state signal dir signal dir signal dir signal dir signal dir signal, dir, pu, pd, st t3 vddiop0 gpio pa0 i/o txd0 o spi1_npcs1 o pio, i, pu, st u2 vddiop0 gpio pa1 i/o rxd0 i spi0_npcs2 o pio, i, pu, st u3 vddiop0 gpio pa2 i/o rts0 o pio, i, pu, st p4 vddiop0 gpio pa3 i/o cts0 i pio, i, pu, st t4 vddiop0 gpio pa4 i/o sck0 i/o pio, i, pu, st u4 vddiop0 gpio pa5 i/o txd1 o pio, i, pu, st p5 vddiop0 gpio pa6 i/o rxd1 i pio, i, pu, st r4 vddiop0 gpio pa7 i/o txd2 o spi0_npcs1 o pio, i, pu, st u6 vddiop0 gpio pa8 i/o rxd2 i spi1_npcs0 i/o pio, i, pu, st r5 vddiop0 gpio pa9 i/o drxd i pio, i, pu, st r6 vddiop0 gpio pa10 i/o dtxd o pio, i, pu, st t5 vddiop0 gpio pa11 i/o spi0_miso i/o mcda4 i/o pio, i, pu, st t6 vddiop0 gpio pa12 i/o spi0_mosi i/o mcda5 i/o pio, i, pu, st u5 vddiop0 gpio_clk pa13 i/o spi0_spck i/o mcda6 i/o pio, i, pu, st u7 vddiop0 gpio pa14 i/o spi0_npcs0 i/o mcda7 i/o pio, i, pu, st t7 vddiop0 gpio pa15 i/o mcda0 i/o pio, i, pu, st r7 vddiop0 gpio pa16 i/o mccda i/o pio, i, pu, st u8 vddiop0 gpio_clk pa17 i/o mcck i/o pio, i, pu, st p8 vddiop0 gpio pa18 i/o mcda1 i/o pio, i, pu, st t8 vddiop0 gpio pa19 i/o mcda2 i/o pio, i, pu, st r8 vddiop0 gpio pa20 i/o mcda3 i/o pio, i, pu, st u9 vddiop0 gpio pa21 i/o tioa0 i/o spi1_miso i/o pio, i, pu, st u10 vddiop0 gpio pa22 i/o tioa1 i/o spi1_mosi i/o pio, i, pu, st t9 vddiop0 gpio_clk pa23 i/o tioa2 i/o spi1_spck i/o pio, i, pu, st u11 vddiop0 gpio pa24 i/o tclk0 i tk i/o pio, i, pu, st t10 vddiop0 gpio pa25 i/o tclk1 i tf i/o pio, i, pu, st r9 vddiop0 gpio pa26 i/o tclk2 i td o pio, i, pu, st u12 vddiop0 gpio pa27 i/o tiob0 i/o rd i pio, i, pu, st t11 vddiop0 gpio pa28 i/o tiob1 i/o rk i/o pio, i, pu, st u13 vddiop0 gpio pa29 i/o tiob2 i/o rf i/o pio, i, pu, st r10 vddiop0 gpio pa30 i/o twd0 i/o spi1_npcs3 o pio, i, pu, st t12 vddiop0 gpio pa31 i/o twck0 o spi1_npcs2 o pio, i, pu, st e4 vddana gpio pb0 i/o rts2 o pio, i, pu, st f3 vddana gpio pb1 i/o cts2 i pio, i, pu, st f4 vddana gpio pb2 i/o sck2 i/o pio, i, pu, st f2 vddana gpio pb3 i/o spi0_npcs3 o pio, i, pu, st
10 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 g4 vddana gpio_clk pb4 i/o pio, i, pu, st g3 vddana gpio pb5 i/o pio, i, pu, st d2 vddana gpio_ana pb6 i/o ad7 i pio, i, pu, st e2 vddana gpio_ana pb7 i/o ad8 i pio, i, pu, st d1 vddana gpio_ana pb8 i/o ad9 i pio, i, pu, st f1 vddana gpio_ana pb9 i/o ad10 i pck1 o pio, i, pu, st e1 vddana gpio_ana pb10 i/o ad11 i pck0 o pio, i, pu, st a1 vddana gpio_ana pb11 i/o ad0 i pwm0 o pio, i, pu, st c3 vddana gpio_ana pb12 i/o ad1 i pwm1 o pio, i, pu, st b1 vddana gpio_ana pb13 i/o ad2 i pwm2 o pio, i, pu, st c2 vddana gpio_ana pb14 i/o ad3 i pwm3 o pio, i, pu, st d3 vddana gpio_ana pb15 i/o ad4 i pio, i, pu, st c1 vddana gpio_ana pb16 i/o ad5 i i pio, i, pu, st e3 vddana gpio_ana pb17 i/o ad6 i i pio, i, pu, st d4 vddana gpio pb18 i/o irq i adtrg i pio, i, pu, st g2 vddiop1 gpio pc0 i/o lcddat0 o twd1 i/o pio, i, pu, st g1 vddiop1 gpio pc1 i/o lcddat1 o twck1 o pio, i, pu, st h4 vddiop1 gpio pc2 i/o lcddat2 o tioa3 i/o pio, i, pu, st j1 vddiop1 gpio pc3 i/o lcddat3 o tiob3 i/o pio, i, pu, st h3 vddiop1 gpio pc4 i/o lcddat4 o tclk3 i pio, i, pu, st j3 vddiop1 gpio pc5 i/o lcddat5 o tioa4 i/o pio, i, pu, st h2 vddiop1 gpio pc6 i/o lcddat6 o tiob4 i/o pio, i, pu, st h1 vddiop1 gpio pc7 i/o lcddat7 o tclk4 i pio, i, pu, st k2 vddiop1 gpio pc8 i/o lcddat8 o utxd0 o pio, i, pu, st j2 vddiop1 gpio pc9 i/o lcddat9 o urxd0 i pio, i, pu, st l1 vddiop1 gpio pc10 i/o lcddat10 o pwm0 o pio, i, pu, st k1 vddiop1 gpio pc11 i/o lcddat11 o pwm1 o pio, i, pu, st l2 vddiop1 gpio pc12 i/o lcddat12 o tioa5 i/o pio, i, pu, st k3 vddiop1 gpio pc13 i/o lcddat13 o tiob5 i/o pio, i, pu, st m1 vddiop1 gpio pc14 i/o lcddat14 o tclk5 i pio, i, pu, st m2 vddiop1 gpio_clk pc15 i/o lcddat15 o pck0 o pio, i, pu, st k4 vddiop1 gpio pc16 i/o lcddat16 o utxd1 o pio, i, pu, st m3 vddiop1 gpio pc17 i/o lcddat17 o urxd1 i pio, i, pu, st n1 vddiop1 gpio pc18 i/o lcddat18 o pwm0 o pio, i, pu, st n2 vddiop1 gpio pc19 i/o lcddat19 o pwm1 o pio, i, pu, st n3 vddiop1 gpio pc20 i/o lcddat20 o pwm2 o pio, i, pu, st p1 vddiop1 gpio pc21 i/o lcddat21 o pwm3 o pio, i, pu, st p2 vddiop1 gpio pc22 i/o lcddat22 o txd3 o pio, i, pu, st table 4-1. bga217 pin description (continued) ball power rail i/o type primary alternate pio peripheral a pio peripheral b pio peripheral c reset state signal dir signal dir signal dir signal dir signal dir signal, dir, pu, pd, st
11 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 p3 vddiop1 gpio pc23 i/o lcddat23 o rxd3 i pio, i, pu, st r1 vddiop1 gpio pc24 i/o lcddisp o rts3 o pio, i, pu, st r3 vddiop1 gpio pc25 i/o cts3 i pio, i, pu, st r2 vddiop1 gpio pc26 i/o lcdpwm o sck3 i/o pio, i, pu, st t1 vddiop1 gpio pc27 i/o lcdvsync o rts1 o pio, i, pu, st m4 vddiop1 gpio pc28 i/o lcdhsync o cts1 i pio, i, pu, st n4 vddiop1 gpio_clk pc29 i/o lcdden o sck1 i/o pio, i, pu, st t2 vddiop1 gpio_clk2 pc30 i/o lcdpck o pio, i, pu, st u1 vddiop1 gpio pc31 i/o fiq i pck1 o pio, i, pu, st p15 vddnf ebi pd0 i/o nandoe o pio, i, pu n14 vddnf ebi pd1 i/o nandwe o pio, i, pu m15 vddnf ebi pd2 i/o a21/nandale o a21,o, pd m14 vddnf ebi pd3 i/o a22/nandcle o a22,o, pd p16 vddnf ebi pd4 i/o ncs3 o pio, i, pu m17 vddnf ebi pd5 i/o nwait i pio, i, pu l15 vddnf ebi pd6 i/o d16 o pio, i, pu l16 vddnf ebi pd7 i/o d17 o pio, i, pu l17 vddnf ebi pd8 i/o d18 o pio, i, pu k17 vddnf ebi pd9 i/o d19 o pio, i, pu k16 vddnf ebi pd10 i/o d20 o pio, i, pu k15 vddnf ebi pd11 i/o d21 o pio, i, pu j17 vddnf ebi pd12 i/o d22 o pio, i, pu j16 vddnf ebi pd13 i/o d23 o pio, i, pu h17 vddnf ebi pd14 i/o d24 o pio, i, pu j15 vddnf ebi pd15 i/o d25 o a20 o a20, o, pd g17 vddnf ebi pd16 i/o d26 o a23 o a23, o, pd h16 vddnf ebi pd17 i/o d27 o a24 o a24, o, pd h15 vddnf ebi pd18 i/o d28 o a25 o a25, o, pd f17 vddnf ebi pd19 i/o d29 o ncs2 o pio, i, pu g16 vddnf ebi pd20 i/o d30 o ncs4 o pio, i, pu e17 vddnf ebi pd21 i/o d31 o ncs5 o pio, i, pu h8 h9 h10 vddiom power vddiom i i j14 k14 l14 vddnf power vddnf i i table 4-1. bga217 pin description (continued) ball power rail i/o type primary alternate pio peripheral a pio peripheral b pio peripheral c reset state signal dir signal dir signal dir signal dir signal dir signal, dir, pu, pd, st
12 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 j8 j9 j10 k9 k10 gndiom gnd gndiom i i p9 p12 vddiop0 power vddiop0 i i l3 l4 vddiop1 power vddiop1 i i p6 p7 p13 gndiop gnd gndiop i i d6 vddbu power vddbu i i d5 b3 gndbu gnd gndbu i i c4 vddana power vddana i i b2 gndana gnd gndana i i t16 vddpll power vddpll i i p14 gndpll gnd gndpll i i r14 vddosc power vddosc i i r15 vddusb power vddusb i i n16 vddfuse power vddfuse i i m16 gndfuse gnd gndfuse i t17 gndusb gnd gndusb i i c8 g15 j4 p10 vddcore power vddcore i i d8 h14 k8 p11 gndcore gnd gndcore i i b14 vddiom ebi d0 i/o o, pd a14 vddiom ebi d1 i/o o, pd c14 vddiom ebi d2 i/o o, pd d13 vddiom ebi d3 i/o o, pd c13 vddiom ebi d4 i/o o, pd b13 vddiom ebi d5 i/o o, pd a13 vddiom ebi d6 i/o o, pd c12 vddiom ebi d7 i/o o, pd d12 vddiom ebi d8 i/o o, pd b12 vddiom ebi d9 i/o o, pd c11 vddiom ebi d10 i/o o, pd d11 vddiom ebi d11 i/o o, pd table 4-1. bga217 pin description (continued) ball power rail i/o type primary alternate pio peripheral a pio peripheral b pio peripheral c reset state signal dir signal dir signal dir signal dir signal dir signal, dir, pu, pd, st
13 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 a12 vddiom ebi d12 i/o o, pd b11 vddiom ebi d13 i/o o, pd a11 vddiom ebi d14 i/o o, pd c10 vddiom ebi d15 i/o o, pd d17 vddiom ebi_o a0 o nbs0 o o, pd c17 vddiom ebi_o a1 o nbs2/ dqm2/ nwr2 o o, pd f16 vddiom ebi_o a2 o o, pd b17 vddiom ebi_o a3 o o, pd a17 vddiom ebi_o a4 o o, pd f15 vddiom ebi_o a5 o o, pd e16 vddiom ebi_o a6 o o, pd d16 vddiom ebi_o a7 o o, pd e15 vddiom ebi_o a8 o o, pd g14 vddiom ebi_o a9 o o, pd c16 vddiom ebi_o a10 o o, pd f14 vddiom ebi_o a11 o o, pd b16 vddiom ebi_o a12 o o, pd a16 vddiom ebi_o a13 o o, pd c15 vddiom ebi_o a14 o o, pd d15 vddiom ebi_o a15 o o, pd b15 vddiom ebi_o a16 o ba0 o o, pd e14 vddiom ebi_o a17 o ba1 o o, pd a15 vddiom ebi_o a18 o ba2 o o, pd d14 vddiom ebi_o a19 o o, pd b7 vddiom ebi_o ncs0 o o, pu c5 vddiom ebi_o ncs1 o sdcs o o, pu c7 vddiom ebi_o nrd o o, pu a6 vddiom ebi_o nwr0 o nwre o o, pu c6 vddiom ebi_o nwr1 o nbs1 o o, pu d7 vddiom ebi_o nwr3 o nbs3/ dqm3 o o, pu a10 vddiom ebi_clk sdck o o a9 vddiom ebi_clk #sdck o o d10 vddiom ebi_o sdcke o o, pu b9 vddiom ebi_o ras o o, pu d9 vddiom ebi_o cas o o, pu b10 vddiom ebi_o sdwe o o, pu b6 vddiom ebi_o sda10 o o, pu c9 vddiom ebi_o dqm0 o o, pu table 4-1. bga217 pin description (continued) ball power rail i/o type primary alternate pio peripheral a pio peripheral b pio peripheral c reset state signal dir signal dir signal dir signal dir signal dir signal, dir, pu, pd, st
14 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 a8 vddiom ebi_o dqm1 o o, pu b8 vddiom ebi dqs0 i/o o, pd a7 vddiom ebi dqs1 i/o o, pd a2 vddana power advref i i p17 vddusb usbfs hdp i/o o, pd n17 vddusb usbfs hdm i/o o, pd r17 vddusb usbfs ddp i/o o, pd r16 vddusb usbfs ddm i/o o, pd a5 vddbu sysc wkup i i, st b5 vddbu sysc shdn o o, pu u15 vddcore rstjtag bms i i, pd, st b4 vddbu sysc jtagsel i i, pd r12 vddiop0 rstjtag tck i i, st r11 vddiop0 rstjtag tdi i i, st u14 vddiop0 rstjtag tdo o o t13 vddiop0 rstjtag tms i i, st t14 vddiop0 rstjtag rtck o o r13 vddiop0 rstjtag nrst i/o i, pu, st t15 vddiop0 rstjtag ntrst i i, pu, st a4 vddbu clock xin32 i i a3 vddbu clock xout32 o o u17 vddiop0 clock xin i i u16 vddiop0 clock xout o o n15 nc table 4-1. bga217 pin description (continued) ball power rail i/o type primary alternate pio peripheral a pio peripheral b pio peripheral c reset state signal dir signal dir signal dir signal dir signal dir signal, dir, pu, pd, st
15 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 4.4 247-ball bga package pinout table 4-2. bga247 pin description ball power rail i/o type primary alternate pio peripheral a pio peripheral b pio peripheral c reset state signal dir signal dir signal dir signal dir signal dir signal, dir, pu, pd, st p3 vddiop0 gpio pa0 i/o txd0 o spi1_npcs1 o pio, i, pu, st r2 vddiop0 gpio pa1 i/o rxd0 i spi0_npcs2 o pio, i, pu, st r9 vddiop0 gpio pa2 i/o rts0 o pio, i, pu, st n5 vddiop0 gpio pa3 i/o cts0 i pio, i, pu, st p10 vddiop0 gpio pa4 i/o sck0 i/o pio, i, pu, st r3 vddiop0 gpio pa5 i/o txd1 o pio, i, pu, st r10 vddiop0 gpio pa6 i/o rxd1 i pio, i, pu, st t2 vddiop0 gpio pa7 i/o txd2 o spi0_npcs1 o pio, i, pu, st p6 vddiop0 gpio pa8 i/o rxd2 i spi1_npcs0 i/o pio, i, pu, st t3 vddiop0 gpio pa9 i/o drxd i pio, i, pu, st u2 vddiop0 gpio pa10 i/o dtxd o pio, i, pu, st p5 vddiop0 gpio pa11 i/o spi0_miso i/o mcda4 i/o pio, i, pu, st v2 vddiop0 gpio pa12 i/o spi0_mosi i/o mcda5 i/o pio, i, pu, st v1 vddiop0 gpio_clk pa13 i/o spi0_spck i/o mcda6 i/o pio, i, pu, st w2 vddiop0 gpio pa14 i/o spi0_npcs0 i/o mcda7 i/o pio, i, pu, st w1 vddiop0 gpio pa15 i/o mcda0 i/o pio, i, pu, st v3 vddiop0 gpio pa16 i/o mccda i/o pio, i, pu, st r5 vddiop0 gpio_clk pa17 i/o mcck i/o pio, i, pu, st u3 vddiop0 gpio pa18 i/o mcda1 i/o pio, i, pu, st v4 vddiop0 gpio pa19 i/o mcda2 i/o pio, i, pu, st u4 vddiop0 gpio pa20 i/o mcda3 i/o pio, i, pu, st v5 vddiop0 gpio pa21 i/o tioa0 i/o spi1_miso i/o pio, i, pu, st u5 vddiop0 gpio pa22 i/o tioa1 i/o spi1_mosi i/o pio, i, pu, st r6 vddiop0 gpio_clk pa23 i/o tioa2 i/o spi1_spck i/o pio, i, pu, st r7 vddiop0 gpio pa24 i/o tclk0 i tk i/o pio, i, pu, st u6 vddiop0 gpio pa25 i/o tclk1 i tf i/o pio, i, pu, st v6 vddiop0 gpio pa26 i/o tclk2 i td o pio, i, pu, st r8 vddiop0 gpio pa27 i/o tiob0 i/o rd i pio, i, pu, st u7 vddiop0 gpio pa28 i/o tiob1 i/o rk i/o pio, i, pu, st p11 vddiop0 gpio pa29 i/o tiob2 i/o rf i/o pio, i, pu, st v7 vddiop0 gpio pa30 i/o twd0 i/o spi1_npcs3 o pio, i, pu, st n12 vddiop0 gpio pa31 i/o twck0 o spi1_npcs2 o pio, i, pu, st g6 vddana gpio pb0 i/o rts2 o pio, i, pu, st e3 vddana gpio pb1 i/o cts2 i pio, i, pu, st g5 vddana gpio pb2 i/o sck2 i/o pio, i, pu, st f2 vddana gpio pb3 i/o spi0_npcs3 o pio, i, pu, st e2 vddana gpio_clk pb4 i/o pio, i, pu, st
16 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 e5 vddana gpio pb5 i/o pio, i, pu, st c2 vddana gpio_ana pb6 i/o ad7 i pio, i, pu, st b2 vddana gpio_ana pb7 i/o ad8 i pio, i, pu, st a2 vddana gpio_ana pb8 i/o ad9 i pio, i, pu, st b1 vddana gpio_ana pb9 i/o ad10 i pck1 o pio, i, pu, st a1 vddana gpio_ana pb10 i/o ad11 i pck0 o pio, i, pu, st c7 vddana gpio_ana pb11 i/o ad0 i pwm0 o pio, i, pu, st c8 vddana gpio_ana pb12 i/o ad1 i pwm1 o pio, i, pu, st d3 vddana gpio_ana pb13 i/o ad2 i pwm2 o pio, i, pu, st f5 vddana gpio_ana pb14 i/o ad3 i pwm3 o pio, i, pu, st e6 vddana gpio_ana pb15 i/o ad4 i pio, i, pu, st c9 vddana gpio_ana pb16 i/o ad5 i i pio, i, pu, st d2 vddana gpio_ana pb17 i/o ad6 i i pio, i, pu, st e7 vddana gpio pb18 i/o irq i adtrg i pio, i, pu, st f3 vddiop1 gpio pc0 i/o lcddat0 o twd1 i/o pio, i, pu, st g2 vddiop1 gpio pc1 i/o lcddat1 o twck1 o pio, i, pu, st l7 vddiop1 gpio pc2 i/o lcddat2 o tioa3 i/o pio, i, pu, st g3 vddiop1 gpio pc3 i/o lcddat3 o tiob3 i/o pio, i, pu, st h5 vddiop1 gpio pc4 i/o lcddat4 o tclk3 i pio, i, pu, st m7 vddiop1 gpio pc5 i/o lcddat5 o tioa4 i/o pio, i, pu, st h3 vddiop1 gpio pc6 i/o lcddat6 o tiob4 i/o pio, i, pu, st h2 vddiop1 gpio pc7 i/o lcddat7 o tclk4 i pio, i, pu, st j3 vddiop1 gpio pc8 i/o lcddat8 o utxd0 o pio, i, pu, st m8 vddiop1 gpio pc9 i/o lcddat9 o urxd0 i pio, i, pu, st j5 vddiop1 gpio pc10 i/o lcddat10 o pwm0 o pio, i, pu, st k6 vddiop1 gpio pc11 i/o lcddat11 o pwm1 o pio, i, pu, st p9 vddiop1 gpio pc12 i/o lcddat12 o tioa5 i/o pio, i, pu, st l6 vddiop1 gpio pc13 i/o lcddat13 o tiob5 i/o pio, i, pu, st j2 vddiop1 gpio pc14 i/o lcddat14 o tclk5 i pio, i, pu, st k3 vddiop1 gpio_clk pc15 i/o lcddat15 o pck0 o pio, i, pu, st k2 vddiop1 gpio pc16 i/o lcddat16 o utxd1 o pio, i, pu, st k5 vddiop1 gpio pc17 i/o lcddat17 o urxd1 i pio, i, pu, st l3 vddiop1 gpio pc18 i/o lcddat18 o pwm0 o pio, i, pu, st n8 vddiop1 gpio pc19 i/o lcddat19 o pwm1 o pio, i, pu, st l2 vddiop1 gpio pc20 i/o lcddat20 o pwm2 o pio, i, pu, st p8 vddiop1 gpio pc21 i/o lcddat21 o pwm3 o pio, i, pu, st m3 vddiop1 gpio pc22 i/o lcddat22 o txd3 o pio, i, pu, st l5 vddiop1 gpio pc23 i/o lcddat23 o rxd3 i pio, i, pu, st n6 vddiop1 gpio pc24 i/o lcddisp o rts3 o pio, i, pu, st table 4-2. bga247 pin description (continued) ball power rail i/o type primary alternate pio peripheral a pio peripheral b pio peripheral c reset state signal dir signal dir signal dir signal dir signal dir signal, dir, pu, pd, st
17 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 n2 vddiop1 gpio pc25 i/o cts3 i pio, i, pu, st p7 vddiop1 gpio pc26 i/o lcdpwm o sck3 i/o pio, i, pu, st m2 vddiop1 gpio pc27 i/o lcdvsync o rts1 o pio, i, pu, st m5 vddiop1 gpio pc28 i/o lcdhsync o cts1 i pio, i, pu, st n3 vddiop1 gpio_clk pc29 i/o lcdden o sck1 i/o pio, i, pu, st m6 vddiop1 gpio_clk2 pc30 i/o lcdpck o pio, i, pu, st p2 vddiop1 gpio pc31 i/o fiq i pck1 o pio, i, pu, st r14 vddnf ebi pd0 i/o nandoe o pio, i, pu r15 vddnf ebi pd1 i/o nandwe o pio, i, pu t17 vddnf ebi pd2 i/o a21/nandale o a21,o, pd p15 vddnf ebi pd3 i/o a22/nandcle o a22,o, pd r17 vddnf ebi pd4 i/o ncs3 o pio, i, pu m15 vddnf ebi pd5 i/o nwait i pio, i, pu n15 vddnf ebi pd6 i/o d16 o pio, i, pu v13 vddnf ebi pd7 i/o d17 o pio, i, pu l14 vddnf ebi pd8 i/o d18 o pio, i, pu w18 vddnf ebi pd9 i/o d19 o pio, i, pu v18 vddnf ebi pd10 i/o d20 o pio, i, pu w19 vddnf ebi pd11 i/o d21 o pio, i, pu v19 vddnf ebi pd12 i/o d22 o pio, i, pu n18 vddnf ebi pd13 i/o d23 o pio, i, pu l15 vddnf ebi pd14 i/o d24 o pio, i, pu n17 vddnf ebi pd15 i/o d25 o a20 o a20, o, pd m18 vddnf ebi pd16 i/o d26 o a23 o a23, o, pd m17 vddnf ebi pd17 i/o d27 o a24 o a24, o, pd p17 vddnf ebi pd18 i/o d28 o a25 o a25, o, pd l18 vddnf ebi pd19 i/o d29 o ncs2 o pio, i, pu k15 vddnf ebi pd20 i/o d30 o ncs4 o pio, i, pu l17 vddnf ebi pd21 i/o d31 o ncs5 o pio, i, pu e8, e9, e13, f7, f8, f9, g14 vddiom power vddiom i i m14,p 13,u1 0,v9, v10, v11 vddnf power vddnf i i table 4-2. bga247 pin description (continued) ball power rail i/o type primary alternate pio peripheral a pio peripheral b pio peripheral c reset state signal dir signal dir signal dir signal dir signal dir signal, dir, pu, pd, st
18 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 h6, h7, j6, j7, j8, f10, f11, f12, f13, f14, f15, f16 gndiom gnd gndiom i i n11, m12, m13 vddiop0 power vddiop0 i i m9, m10, m11 vddiop1 power vddiop1 i i l10, l11, l12, l13, v14 gndiop gnd gndiop i i b6 vddbu power vddbu i i b7 gndbu gnd gndbu i i f6 vddana power vddana i i c3 gndana gnd gndana i i v17 vddpll power vddpll i i u16 gndpll gnd gndpll i i p14 vddfuse power vddfuse i i n14 gndfuse gnd gndfuse i i r12 vddosc power vddosc i i u13 vddusb power vddusb i i u17 gndusb gnd gndusb i i j12, j13, j14, k10, k11, k12, k13, k14, u15 vddcore power vddcore i i h9, j9, j10, j11, k7, k8 k9, l8, l9 gndcore gnd gndcore i i a19 vddiom ebi d0 i/o i, pd table 4-2. bga247 pin description (continued) ball power rail i/o type primary alternate pio peripheral a pio peripheral b pio peripheral c reset state signal dir signal dir signal dir signal dir signal dir signal, dir, pu, pd, st
19 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 e15 vddiom ebi d1 i/o i, pd c18 vddiom ebi d2 i/o i, pd d15 vddiom ebi d3 i/o i, pd b17 vddiom ebi d4 i/o i, pd e14 vddiom ebi d5 i/o i, pd c16 vddiom ebi d6 i/o i, pd a18 vddiom ebi d7 i/o i, pd b15 vddiom ebi d8 i/o i, pd g12 vddiom ebi d9 i/o i, pd c14 vddiom ebi d10 i/o i, pd d13 vddiom ebi d11 i/o i, pd a16 vddiom ebi d12 i/o i, pd a14 vddiom ebi d13 i/o i, pd b13 vddiom ebi d14 i/o i, pd h13 vddiom ebi d15 i/o i, pd j15 vddiom ebi_o a0 o nbs0 o o k18 vddiom ebi_o a1 o nbs2/ dqm2/ nwr2 o o k17 vddiom ebi_o a2 o o h15 vddiom ebi_o a3 o o j18 vddiom ebi_o a4 o o j17 vddiom ebi_o a5 o o g17 vddiom ebi_o a6 o o h17 vddiom ebi_o a7 o o h18 vddiom ebi_o a8 o o h14 vddiom ebi_o a9 o o g18 vddiom ebi_o a10 o o f18 vddiom ebi_o a11 o o f17 vddiom ebi_o a12 o o e19 vddiom ebi_o a13 o o d19 vddiom ebi_o a14 o o e18 vddiom ebi_o a15 o o g15 vddiom ebi_o a16 o ba0 o o e16 vddiom ebi_o a17 o ba1 o o b19 vddiom ebi_o a18 o ba2 o o d17 vddiom ebi_o a19 o o b9 vddiom ebi_o ncs0 o o, pu b8 vddiom ebi_o ncs1 o sdcs o o, pu e10 vddiom ebi_o nrd o o, pu table 4-2. bga247 pin description (continued) ball power rail i/o type primary alternate pio peripheral a pio peripheral b pio peripheral c reset state signal dir signal dir signal dir signal dir signal dir signal, dir, pu, pd, st
20 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 g10 vddiom ebi_o nwr0 o nwre o o, pu c10 vddiom ebi_o nwr1 o nbs1 o o, pu g9 vddiom ebi_o nwr3 o nbs3/ dqm3 o o, pu b10 vddiom ebi_clk sdck o o b11 vddiom ebi_clk #sdck o o c12 vddiom ebi_o sdcke o o, pu g11 vddiom ebi_o ras o o, pu e12 vddiom ebi_o cas o o, pu h12 vddiom ebi_o sdwe o o, pu h10 vddiom ebi_o sda10 o o, pu a12 vddiom ebi_o dqm0 o o, pu c11 vddiom ebi_o dqm1 o o, pu h11 vddiom ebi dqs0 i/o i, pd e11 vddiom ebi dqs1 i/o i, pd b3 vddana power advref i i t18 vddusb usbfs hdp i/o o, pd u18 vddusb usbfs hdm i/o o, pd p18 vddusb usbfs ddp i/o o, pd r18 vddusb usbfs ddm i/o o, pd c6 vddbu sysc wkup i i, st g8 vddbu sysc shdn o o, pu u14 vddcore rstjtag bms i i, pu, st c4 vddbu sysc jtagsel i i, pd, st c5 vddbu sysc tst i i, pd, st v8 vddiop0 rstjtag tck i i, st u8 vddiop0 rstjtag tdi i i, st p12 vddiop0 rstjtag tdo o o, st r11 vddiop0 rstjtag tms i i, st v12 vddiop0 rstjtag rtck o o, st u11 vddiop0 rstjtag nrst i/o o, pu, st u9 vddiop0 rstjtag ntrst i i, pu, st b4 vddbu clock xin32 i i b5 vddbu clock xout32 o o v16 vddiop0 clock xin i i v15 vddiop0 clock xout o o h8 nc u12 nc r13 nc table 4-2. bga247 pin description (continued) ball power rail i/o type primary alternate pio peripheral a pio peripheral b pio peripheral c reset state signal dir signal dir signal dir signal dir signal dir signal, dir, pu, pd, st
21 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 5. power considerations 5.1 power supplies the sam9n12/cn11/cn12 has several types of power supply pins: table 5-1. sam9n12/cn11/cn12 power supplies name voltag e rang e, nominal associated ground powers vddcore 0.9-1.1v, 1.0v gndcore the core, including the processor, the embedded memories and the peripherals, the internal 12 mhz rc vddiom 1.65-1.95v, 1.8v 3.0-3.6v, 3.3v gndiom the external memory interface i/o lines vddnf 1.65-1.95v, 1.8v 3.0-3.6v, 3.3v gndiom the nand flash i/o and control, d16-d32 and multiplexed smc lines vddiop0 1.65-3.6v gndiop a part of peripherals i/o lines vddiop1 1.65-3.6v gndiop a part of peripherals i/o lines vddbu 1.65-3.6v gndbu the slow clock oscillator, the internal 32-kbyte rc and a part of the system controller vddusb 3.0-3.6v, 3.3v gndusb the usb interface vddpll 0.9-1.1v, 1.0v gndpll the pll cells vddosc 1.65-3.6v gndpll the main oscillator cells vddana 3.0-3.6v, 3.3v gndana the analog to digital converter vddfuse 3.0-3.6v, 3.3v gndfuse fuse box for programming
22 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 6. memories figure 6-1. sam9n12/cn11/cn12 memory mapping 0x1000 0000 0x0000 0000 0x0fff ffff 0xf000 0000 0xefff ffff addre ss memory space intern a l peripher als intern a l memories ebi chip select 0 undefined (ab ort) 1,792 mbytes 0x2000 0000 0x1fff ffff 0x3000 0000 0x2fff ffff 0x4000 0000 0x3fff ffff 0x5000 0000 0x4fff ffff 256 mbytes 256 mbytes 256 mbytes 256 mbytes 256 mbytes notes: (1) can b e rom, ebi1_ncs0 or sram depending on bms and remap 0xffff ffff ebi chip select 3/ nandflash ebi chip select 4 ebi chip select 1/ ddr2/lpddr sdr/lpsdr ebi chip select 2 0xf800 8000 0xf801 0000 spi0 0xf800 c000 tc0, tc1, tc2 mci 0xf000 8000 0xf001 0000 us art0 us art1 twi1 twi0 0xf001 4000 0xffff fe00 0xffff fc00 16 bytes 512 bytes 512 bytes 512 bytes 512 bytes pmc pioc piob pioa dbgu rstc 512 bytes aic 512 bytes 0xffff fe10 16 bytes shdc 0xffff fe20 16 bytes 0xffff fe30 16 bytes pitc 0xffff fe40 16 bytes wdtc 0xffff fe54 4 bytes gpbr 0xffff fe70 res erved peripheral mappin g 0xffff c000 sysc 0xffff ffff pwmc tsadc 0xffff c000 res erved 0xffff ffff 0xf000 0000 0xf801 8000 piod ssc us art2 us art3 0xf801 c000 0xf802 0000 udp 0xf802 4000 rtcc 0xffff fe60 res erved 0xffff fe50 sckcr 16 bytes sys tem controller mapping 0xf801 4000 spi1 1 mbytes 0x0040 0000 0x0050 0000 0x0010 0000 0x0060 0000 uhp ram sram 0x0fff ffff internal memory mappin g boot memory (1) 0x0000 0000 undefined (ab ort) 1 mbytes 1 mbytes rom 1 mbytes 0xf803 8000 0xf000 c000 0xf802 8000 0xf802 c000 0xf803 4000 0x0030 0000 16 bytes 0xffff feb0 0xf803 c000 tc3, tc4, tc5 uart0 uart1 res erved 0xf804 0000 0xf804 8000 0xf804 4000 0xf804 c000 512 bytes 0x0020 0000 1 mbytes 1 mbytes undefined (ab ort) 0xf000 4000 lcdc 0xf805 0000 0xffff fec0 res erved res erved 0xffff f000 0xffff f200 0xffff f400 0xffff f600 0xffff f800 0xffff fa00 0xffff ec00 0xffff ea00 0xffff e800 0xffff e600 0xffff e000 512 bytes matrix 512 bytes smc 512 bytes ddr2/lpddr sdr/lpsdr pmecc 1536 bytes 0xffff ee00 512 bytes dmac 512 bytes 0xffff de00 pmerrloc 512 bytes undefined (ab ort) res erved res erved res erved aes * trng sha 0xf001 8000 res erved fuse 512 bytes 0xffff dc00 ebi chip select 5 0x6fff ffff 0x6000 0000 0x5fff ffff 0x7000 0000 256 mbytes 256 mbytes 256 mbytes * * res erved for sam9n12
23 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 6.1 memory mapping a first level of address decoding is performed by the ahb bus matrix, i.e., the implementation of the advanced high performance bus (ahb) fo r its master and slave interfaces with addi- tional features. decoding breaks up the 4 gbytes of address space into 16 banks of 256 mbytes. the banks 1 to 6 are directed to the ebi that associates th ese banks to the external chip selects ebi_ncs0 to ebi_ncs5. the bank 0 is reserved for the addressing of the internal memories, and a sec- ond level of decoding provides 1mbyte of internal memory area. bank 15 is reserved for the peripherals and provides access to the advanced peripheral bus (apb). other areas are unused and performing an access within them provides an abort to the master requesting such an access. 6.2 embedded memories 6.2.1 internal sram the sam9n12/cn11/cn12 embeds a total of 32 kbytes high-speed sram. after reset and until the remap command is performed, the sram is only accessible at address 0x0030 0000. after remap, the sram also becomes available at address 0x0. 6.2.2 internal rom the sam9cn12 contains the secure bootloader (standard bootloader for sam9n12 and SAM9CN11) and specific tables used to compute slc and mlc nand flash ecc. the rom is mapped at address 0x0010 0000. it is also accessible at address 0x0 (bms = 1) after the reset and before the remap command.
24 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 6.3 external memories overview the sam9n12/cn11/cn12 features an external bus interface to provide interface to a wide range of external memories and to any parallel peripheral. 6.3.1 external bus interface ? integrates three external memory controllers: C static memory controller C ddr2/sdram controller C mlc nand flash ecc controller ? up to 26-bit address bus (up to 64 mbytes linear per chip select) ? up to 6 chips selects, configurable assignment: C static memory controller on ncs 0, ncs1, ncs2, ncs3, ncs4, ncs5 C ddr2/sdram controller (sdcs) or static memory controller on ncs1 C nand flash support on ncs3 6.3.2 static memory controller ? 8- or 16-bit data bus ? multiple access modes supported C byte write or byte select lines C asynchronous read in page mode supported (4- up to 16-byte page size) ? multiple device adaptability C control signals programmable setup, pulse and hold time for each memory bank ? multiple wait state management C programmable wait state generation C external wait request C programmable data float time ? slow clock mode supported 6.3.3 ddr-sdram controller ? supports ddr2-sdram, low-power ddr1-s dram or ddr2-sdram, sdr-sdram and low-power sdr-sdram ? numerous configurations supported C 2k, 4k, 8k, 16k row address memory parts C sdram with 4 internal banks C sdr-sdram with 16-bit or 32-bit data path C ddr-sdram with 16-bit data path C one chip select for sdram device (256 mbytes address space) ? programming facilities C multibank ping-pong access (up to 4 banks or 8 banks opened at same time = reduced average latency of transactions) C timing parameters specified by software C automatic refresh operation, refresh rate is programmable
25 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 C automatic update of ds, tcr and pasr parameters (low-power sdram devices) ? energy-saving capabilities C self-refresh, power-down, active power-down and deep power-down modes supported ? sdram power-up initialization by software ? cas latency of 2, 3 supported ? reset function supported (ddr2-sdram) ? odt (on-die termination) not supported ? auto precharge command not used ? sdr-sdram with 16-bit datapath and eight columns not supported ? ddr2-sdram with eight internal banks supported ? linear and interleaved decoding supported ? clock frequency change in precharge power-down mode not supported ? ocd (off-chip driver) mode not supported 6.3.4 programmable multi-bit error correcting code (pmecc) ? multibit error correcting code. ? algorithm based on binary shortened bose, chaudhuri and hocquenghem (bch) codes. ? programmable error correcting capability: 2, 4, 8, 16 and 24 bit of errors per block. ? programmable block size: 512 bytes or 1024 bytes. ? programmable number of block per page: 1, 2, 4 or 8 blocks of data per page. ? programmable spare area size. ? supports spare area ecc protection. ? supports 8 kbytes page size using 1024 bytes/block and 4 kbytes page size using 512 bytes/block. ? multibit error detection is interrupt driven. 6.3.5 programmable multi-bit ecc error location (pmerrloc) ? provides hardware acceleration for determining roots of polynomials defined over a finite field ? programmable finite field gf(2^13) or gf(2^14) ? finds roots of erro r-locator polynomial. ? programmable number of roots.
26 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 7. system controller the system controller is a set of peripherals that allows handling of key elements of the sys- tem, such as power, resets, clocks, time, interrupts, watchdog, etc. the system controller user interface also embed s the registers that configure the matrix and a set of registers for the chip configuration. the chip configuration registers configure the ebi chip select assignment and voltage range for external memories. 7.1 system controller mapping the system controllers peripherals are all mapped within the highest 16 kbytes of address space, between addresses 0xffff e400 and 0xffff ffff. however, all the registers of the system controller are mapped on the top of the address space. all the registers of the system controller can be addressed from a single pointer by using the standard arm instruction set, as the load/store instruction have an indexing mode of 4 kbytes. figure 7-1 on page 27 shows the system controller block diagram. figure 6-1 on page 22 shows the mapping of the user interfaces of the system controller peripherals.
27 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 7.2 system controller block diagram figure 7-1. sam9n12/cn11/cn12 system controller block diagram nrst slck advanced interrupt controller periodic interval timer reset controller pa0-pa31 periph_nreset system controller watchdog timer wdt_fault wdrproc pio controllers power management controller xin xout mainck pllack pit_irq mck proc_nreset wdt_irq periph_irq[2..3] periph_nreset periph_clk[2..30] pck mck pmc_irq nirq nfiq embedded peripherals periph_clk[2..3] pck[0-1] in out enable arm926ej-s slck irq fiq irq fiq periph_irq[5..30] periph_irq[2..30] int int periph_nreset periph_clk[5..30] jtag_nreset por_ntrst proc_nreset periph_nreset dbgu_txd dbgu_rxd pit_irq dbgu_irq pmc_irq rstc_irq wdt_irq rstc_irq slck boundary scan tap controller jtag_nreset debug pck debug idle debug bus matrix mck periph_nreset proc_nreset periph_nreset idle debug unit dbgu_irq mck dbgu_rxd periph_nreset dbgu_txd shut-down controller slck backup_nreset shdn wkup 4 general-purpose backup registers backup_nreset xin32 xout32 pb0-pb18 pc0-pc31 vddbu powered vddcore powered ntrst vddcore por 16 mhz main osc plla vddbu por slow clock osc por_ntrst vddbu usb host full speed port uhpck periph_nreset periph_irq[22] 32-kbyte rc osc pd0-pd21 sckcrsckcr real-time clock rtc_irq slck backup_nreset rtc_alarm ddr sysclk 12 mhz rc osc rtc_alarm lcd pixel clock bscr usb device full speed port udpck periph_nreset periph_irq[23] udpck uhpck pllbck pllb
28 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 7.3 chip identification ? chip id: 0x819a_07a1 ? sam9cn12 chip id extension: 5 ? SAM9CN11 chip id extension: 9 ? sam9n12 chip id extension: 6 ? jtag id: 0x05b3_003f ? arm926 tap id: 0x0792_603f 7.4 backup section the sam9n12/cn11/cn12 features a backup section that embeds: ? rc oscillator ? slow clock oscillator ? real time counter (rtc) ? shutdown controller ? 4 backup registers ? slow clock control register (sckcr) ? a part of the reset controller (rstc) ? this section is powered by the vddbu rail.
29 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 8. peripherals 8.1 peripheral mapping as shown in figure 6-1 , the peripherals are mapped in the upper 256 mbytes of the address space between the addresses 0xfff7 8000 and 0xfffc ffff. each user peripheral is allocated 16 kbytes of address space. 8.2 peripheral identifiers figure 8-1 defines the peripheral identifiers of the sam9n12/cn11/cn12. a peripheral identi- fier is required for the control of the peripheral interrupt with the advanced interrupt controller and for the control of the peripheral clock with the power management controller. table 8-1. sam9n12/cn11/cn12 peripheral identifiers instance id instance name instance descri ption external interrupt wired-or interrupt 0 aic advanced interrupt controller fiq 1 sys system controller interrupt dbgu, pmc, sysc, pmecc, pmerrloc 2 pioa,piob parallel i/o controller a and b 3 pioc,piod parallel i/o controller c and d 4 fuse fuse controller 5 usart0 usart 0 6 usart1 usart 1 7 usart2 usart 2 8 usart3 usart 3 9 twi0 two-wire interface 0 10 twi1 two-wire interface 1 11 reserved 12 hsmci high speed multimedia card interface 13 spi0 serial peripheral interface 0 14 spi1 serial peripheral interface 1 15 uart0 uart 0 16 uart1 uart 1 17 tc0,tc1 timer counter 0,1,2,3,4,5 18 pwm pulse width modulation controller 19 adc adc controller 20 dmac dma controller 21 reserved 22 uhp usb host 23 udp usb device
30 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 8.3 peripheral interr upts and clock control 8.3.1 system interrupt the system interrupt in source 1 is the wired-or of the interrupt signals coming from: ? the ddr2/lpddr controller ? the debug unit ? the periodic interval timer ? the real-time clock ? the watchdog timer ? the reset controller ? the power management controller the clock of these peripherals cannot be deactivated and peripheral id 1 can only be used within the advanced interrupt controller. 8.3.2 external interrupts all external interrupt signals, i.e., the fast interrupt signal fiq or the interrupt signal irq, use a dedicated peripheral id. however, there is no clock control associated with these peripheral ids. 8.4 peripheral signal mult iplexing on i/o lines the sam9n12/cn11/cn12 features 4 pio contro llers, pioa, piob, pioc and piod, which multiplex the i/ o lines of the peripheral set. each pio controller controls 32 lines, 19 lines, 32 lines and 22 lines respectively for pioa, piob, pioc and piod. each line can be assigned to one of three peripheral functions, a, b or c. refer to section 4. package and pinout and the package pinout tables, table 4-1 , table 4-2 , depending on the package. 8.4.1 reset state the column reset state ( table 4-1 , table 4-2 ) indicates the reset state of the line with mnemonics. ? pio/signal 24 reserved 25 lcdc lcd controller 26 reserved 27 sha secure hash algorithm 28 ssc synchronous serial controller 29 aes advanced encryption standard 30 trng true random number generator 31 aic advanced interrupt controller irq table 8-1. sam9n12/cn11/cn12 peripheral identifiers (continued) instance id instance name instance descri ption external interrupt wired-or interrupt
31 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 indicates whether the pio line resets in i/o mode or in peripheral mode. if pio is mentioned, the pio line is maintained in a static state as soon as the reset is released. as a result, the bit corresponding to the pio line in the register pio_psr (peripheral status register) resets low. if a signal name is mentioned in the reset state column, the pio line is assigned to this function and the corresp onding bit in pio_psr resets high. th is is the case on pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released. ? i/o indicates whether the signal is input or output state. ? pu/pd indicates whether pull-up or pull-down, or nothing is enabled. ?st indicates if schmitt trigger is enabled. note: example: the pb18 reset state column shows pio, i, pu, st. that means the line pio18 is configured as an input with pull- up and schmitt trigger enabled. pd14 reset state is pio, i, pu. that means pio input with pull-up. pd15 re set state is a20, o, pd which means output address line 20 with pull-down. 8.4.2 pio line selection peripheral a, b or c is selected thanks to the pio_abcdsr1 and pio_abcdsr2 registers in the pio controller interface. table 8-2. pio line selection px value in pio_abcdsr2 px value in pio_abcdsr1 a, b or c 00a 01b 10c
32 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 8.5 fuse box features sam9cn12 embeds 320 one time programming (otp) bits. when the otp bit is set, it is seen as 1. the user interface allows the user to perform the following operations: 8.5.1 read ? 10 registers sr0-sr9 that reflect otp bit state ? msk field (write-once) allow user to mask registers sr1 to sr9 ? all otp bits are read as 1 when vddfuse is floating, all security features are set. 8.5.2 write ? done in one 32-bit data register ? sel field to select the 32-bit word 0 to 9
33 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 9. arm926ej-s processor overview 9.1 description the arm926ej-s processor is a member of the arm9 ? family of general-purpose microproces- sors. the arm926ej-s implements arm architectu re version 5tej and is targeted at multi- tasking applications where full memory management, high performance, low die size and low power are all important features. the arm926ej-s processor supports the 32- bit arm and 16-bit thumb instruction sets, enabling the user to trade off between high performance and high code density. it also supports 8-bit java instruction set and includes features fo r efficient execution of java bytecode, provid- ing a java performance similar to a jit (just-in-time compilers), for the next generation of java- powered wireless and embedded devices. it includes an enhanced multiplier design for improved dsp performance. the arm926ej-s processor supports the arm debug architecture and includes logic to assist in both hardware and software debug. the arm926ej-s provides a complete high performance processor subsystem, including: ? an arm9ej-s ? integer core ? a memory management unit (mmu) ? separate instruction and data amba ahb bus interfaces ? separate instruction and data tcm interfaces 9.2 embedded characteristics ? arm9ej-s ? based on arm ? architecture v5tej with jazelle technology C three instruction sets Carm ? high-performance 32-bit instruction set Cthumb ? high code density 16-bit instruction set C jazelle ? 8-bit instruction set ? 5-stage pipeline architectu re when jazelle is not used C fetch (f) C decode (d) C execute (e) Cmemory (m) Cwriteback (w) ? 6-stage pipeline when jazelle is used Cfetch C jazelle/decode (two cycles) Cexecute Cmemory Cwriteback ? icache and dcache C virtually-addressed 4-wa y set associative caches C 8 words per line
34 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 C critical-word first cache refilling C write-though and write-back operation for dcache only C pseudo-random or round-robin replacement C cache lockdown registers C cache maintenance ? write buffer C 16-word data buffer C 4-address address buffer C software control drain ? dcache write-back buffer C 8 data word entries C one address entry C software control drain ? tightly-coupled memory (tcm) C separate instruction and data tcm interfaces C provides a mechanism for dma support ? memory management unit (mmu) C access permission for sections C access permission for large pages and small pages C 16 embedded domains C 64 entry instruction tlb and 64 entry data tlb ? memory access C 8-, 16-, and 32-bit data types C separate amba ahb buses for both the 32-bit data interface and the 32-bit instructions interface ? bus interface unit C arbitrates and schedules ahb requests C enables multi-layer ahb to be implemented C increases overall bus bandwidth C makes system architecture mode flexible
35 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 9.3 block diagram figure 9-1. arm926ej-s internal functional block diagram cp15 system configuration coprocessor external coprocessor interface trace port interface arm9ej-s processor core dtcm interface data tlb instruction tlb itcm interface data cache ahb interface and write buffer instruction cache write data read data instruction fetches data address instruction address data address instruction address instruction tcm data tcm mmu amba ahb external coprocessors etm9
36 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 9.4 arm9ej-s processor 9.4.1 arm9ej-s operating states the arm9ej-s processor can operate in three different states, each with a specific instruction set: ? arm state: 32-bit, word-aligned arm instructions. ? thumb state: 16-bit, halfword-aligned thumb instructions. ? jazelle state: variable length, byte-aligned jazelle instructions. in jazelle state, all instru ction fetches are in words. 9.4.2 switching state the operating state of the arm9ej-s core can be switched between: ? arm state and thumb state using the bx and blx instructions, and loads to the pc ? arm state and jazelle state using the bxj instruction all exceptions are entered, handled and exited in arm state. if an exception occurs in thumb or jazelle states, the processor reverts to arm state. the transition back to thumb or jazelle states occurs automatically on return from the exception handler. 9.4.3 instruction pipelines the arm9ej-s core uses two kinds of pipelines to increase the speed of the flow of instructions to the processor. a five-stage (five clock cycles) pipeline is used for arm and thumb states. it consists of fetch, decode, execute, memory and writeback stages. a six-stage (six clock cycles) pipeline is us ed for jazelle state it consists of fetch, jazelle/decode (two clock cycles), execute, memory and writeback stages. 9.4.4 memory access the arm9ej-s core supports byte (8-bit), half-word (16-bit) and word (32-bit) access. words must be aligned to four-byte boundaries, half-words must be aligned to two-byte boundaries and bytes can be placed on any byte boundary. because of the nature of the pipelines, it is possible for a value to be required for use before it has been placed in the register bank by the actions of an earlier instruction. the arm9ej-s con- trol logic automatically detects these cases and stalls the core or forward data. 9.4.5 jazelle technology the jazelle technology enables direct and efficient execution of java byte codes on arm pro- cessors, providing high performance for the next generation of java-powered wireless and embedded devices. the new java feature of arm9ej-s can be described as a hardware emulation of a jvm (java virtual machine). java mode will appear as another state: instead of executing arm or thumb instructions, it executes java byte codes. the java byte code decoder logic implemented in arm9ej-s decodes 95% of executed byte codes and turns them into ar m instructions without any overhead, while less frequently used byte codes are broken down into optimized sequences of arm instructions. the hardware/software split is invisible to the programmer, invisible to the application and invisible to the operating system . all existing arm registers are re-used in jazelle state and all registers then have particular functions in this mode.
37 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 minimum interrupt latency is maintained across both arm state and java state. since byte codes execution can be restarted, an interrupt automatically triggers the core to switch from java state to arm state for the execution of the interrupt handler. this means that no special provision has to be made for handling interrupts while executing byte codes, whether in hard- ware or in software. 9.4.6 arm9ej-s operating modes in all states, there are seven operation modes: ? user mode is the usual arm program executio n state. it is used for executing most application programs ? fast interrupt (fiq) mode is used for handling fast interrupts. it is suitable for high-speed data transfer or channel process ? interrupt (irq) mode is used for general-purpose interrupt handling ? supervisor mode is a protected mode for the operating system ? abort mode is entered after a data or instruction prefetch abort ? system mode is a privileged user mode for the operating system ? undefined mode is entered when an undefined instruction exception occurs mode changes may be made under software control, or may be brought about by external inter- rupts or exception processing. most application programs execute in user mode. the non-user modes, known as privileged modes, are entered in or der to service interrupts or exceptions or to access protecte d resources. 9.4.7 arm9ej-s registers the arm9ej-s core has a total of 37 registers. ? 31 general-purpose 32-bit registers ? 6 32-bit status registers table 9-1 shows all the registers in all modes. table 9-1. arm9tdmi modes and registers layout user and system mode supervisor mode abort mode undefined mode interrupt mode fast interrupt mode r0 r0 r0 r0 r0 r0 r1 r1 r1 r1 r1 r1 r2 r2 r2 r2 r2 r2 r3 r3 r3 r3 r3 r3 r4 r4 r4 r4 r4 r4 r5 r5 r5 r5 r5 r5 r6 r6 r6 r6 r6 r6 r7 r7 r7 r7 r7 r7 r8 r8 r8 r8 r8 r8_fiq r9 r9 r9 r9 r9 r9_fiq r10 r10 r10 r10 r10 r10_fiq r11 r11 r11 r11 r11 r11_fiq
38 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 the arm state register set contains 16 directly-a ccessible registers, r0 to r15, and an additional register, the current program status register (cpsr). registers r0 to r13 are general-purpose registers used to hold either data or address va lues. register r14 is used as a link register that holds a value (return address) of r15 when bl or blx is executed. register r15 is used as a pro- gram counter (pc), whereas the current program status register (cpsr) contains condition code flags and the current mode bits. in privileged modes (fiq, supervisor, abort, irq, undefined), mode-specific banked registers (r8 to r14 in fiq mode or r13 to r14 in the other modes) become available. the corresponding banked registers r14_fiq, r14_svc, r14_abt, r14_irq, r14_und are similarly used to hold the val- ues (return address for each mode) of r15 (pc) when interrupts and exceptions arise, or when bl or blx instructions are executed within interrupt or exception routines. there is another reg- ister called saved program status register (spsr) that becomes available in privileged modes instead of cpsr. this register contains condition code flags and the current mode bits saved as a result of the exception that caused entry to the current (privileged) mode. in all modes and due to a software agreement, register r13 is used as stack pointer. the use and the function of all the registers described above should obey arm procedure call standard (apcs) which defines: ? constraints on the use of registers ? stack conventions ? argument passing and result return for more details, refer to arm software development kit. the thumb state register set is a subset of the arm state set. the programmer has direct access to: ? eight general-purpose registers r0-r7 ? stack pointer, sp ? link register, lr (arm r14) ?pc ? cpsr r12 r12 r12 r12 r12 r12_fiq r13 r13_svc r13_abort r13_undef r13_irq r13_fiq r14 r14_svc r14_abort r14_undef r14_irq r14_fiq pc pc pc pc pc pc cpsr cpsr cpsr cpsr cpsr cpsr spsr_svc spsr_abort spsr_undef spsr_irq spsr_fiq mode-specific banked registers table 9-1. arm9tdmi modes and registers layout (continued) user and system mode supervisor mode abort mode undefined mode interrupt mode fast interrupt mode
39 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 there are banked re gisters sps, lrs and spsrs for each priv ileged mode (for more details see the arm9ej-s technical reference manual, revision r1p2 page 2-12). 9.4.7.1 status registers the arm9ej-s core contains one cpsr, and fi ve spsrs for exception handlers to use. the program status registers: ? hold information about the most recently performed alu operation ? control the enabling and disabling of interrupts ? set the processor operation mode figure 9-2. status register format figure 9-2 shows the status register format, where: ? n: negative, z: zero, c: carry, and v: overflow are the four alu flags ? the sticky overflow (q) flag can be set by certain multiply and fractional arithmetic instructions like qadd, qdadd, qsub, qdsub, smlaxy, and smlawy needed to achieve dsp operations. the q flag is sticky in that, when set by an instru ction, it remains set unt il explicitly cleared by an msr instruction writing to the cpsr. instructions cannot execute conditionally on the status of the q flag. ? the j bit in the cpsr indicates when the ar m9ej-s core is in jazelle state, where: C j = 0: the processor is in arm or thumb state, depending on the t bit C j = 1: the processor is in jazelle state. ? mode: five bits to encode the current processor mode 9.4.8 exceptions 9.4.8.1 exception types and priorities the arm9ej-s supports five types of exceptions. each type drives the arm9ej-s in a privi- leged mode. the types of exceptions are: ? fast interrupt (fiq) ? normal interrupt (irq) ? data and prefetched aborts (abort) ? undefined instruction (undefined) ? software interrupt and reset (supervisor) nz cv q ji f t mode reserved mode bits thumb state bit fiq disable irq disable jazelle state bit reserved sticky overflow overflow carry/borrow/extend zero negative/less than 31 30 29 28 27 24 7 6 5 0
40 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 when an exception occurs, the banked version of r14 and the spsr for the exception mode are used to save the state. more than one exception can happen at a time, therefore the arm9ej-s takes the arisen excep- tions according to the following priority order: ? reset (highest priority) ? data abort ?fiq ?irq ?prefetch abort ? bkpt, undefined instruction, and softwa re interrupt (swi) (lowest priority) the bkpt, or undefined instruction, and swi exceptions are mutually exclusive. note that there is one exception in the priority scheme: when fiqs are enabled and a data abort occurs at the same time as an fiq, the arm9ej-s core enters the data abort handler, and pro- ceeds immediately to fiq vector. a normal return from the fiq causes the data abort handler to resume execution. data aborts must have higher priority than fiqs to ensure that the transfer error does not escape detection. 9.4.8.2 exception modes and handling exceptions arise whenever the normal flow of a program must be halted temporarily, for exam- ple, to service an interrupt from a peripheral. when handling an arm exception, the arm9ej-s core performs the following operations: 1. preserves the address of the next instruction in the appropriate link register that cor- responds to the new mode that has been entered. when the exception entry is from: C arm and jazelle states, the arm9ej-s copies the address of the next instruction into lr (current pc(r15) + 4 or pc + 8 depending on the exception). C thumb state, the arm9ej-s writes the value of the pc into lr, offset by a value (current pc + 2, pc + 4 or pc + 8 depending on the exception) that causes the program to resume from the correct place on return. 2. copies the cpsr into the appropr iate spsr. 3. forces the cpsr mode bits to a value that depends on the exception. 4. forces the pc to fetch the next instruction from the relevant exception vector. the register r13 is also banked across exception modes to provide each exception handler with private stack pointer. the arm9ej-s can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions. when an exception has completed, the exception handler must move both the return value in the banked lr minus an offset to the pc and the spsr to the cpsr. the offset value varies according to the type of exception. this action restores both pc and the cpsr. the fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or remove the requirement for register saving wh ich minimizes the overhead of context switching. the prefetch abort is one of the aborts that indicates that the current memory access cannot be completed. when a prefetch abort occurs, the arm9ej-s marks the prefetched instruction as invalid, but does not take the exception until th e instruction reaches the execute stage in the
41 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 pipeline. if the instruction is not executed, for ex ample because a branch occurs while it is in the pipeline, the abort does not take place. the breakpoint (bkpt) instruction is a new feat ure of arm9ej-s that is destined to solve the problem of the prefetch abort. a breakpoint instruction operates as though the instruction caused a prefetch abort. a breakpoint instruction does not cause the arm9ej-s to take the prefetch abort exception until the instruction reaches the execute stage of the pipeline. if the instruction is not executed, for example because a branch occurs while it is in the pipeline, the breakpoint does not take place. 9.4.9 arm instruction set overview the arm instruction set is divided into: ? branch instructions ? data processing instructions ? status register transfer instructions ? load and store instructions ? coprocessor instructions ? exception-generating instructions arm instructions can be executed conditionally. every instruction contains a 4-bit condition code field (bits[31:28]). table 9-2 gives the arm instruction mnemonic list. table 9-2. arm instruction mnemonic list mnemonic operation mnemonic operation mov move mvn move not add add adc add with carry sub subtract sbc subtract with carry rsb reverse subtract rsc reverse subtract with carry cmp compare cmn compare negated tst test teq test equivalence and logical and bic bit clear eor logical exclusive or orr logical (inclusive) or mul multiply mla multiply accumulate smull sign long multiply umull unsigned long multiply smlal signed long multiply accumulate umlal unsigned long multiply accumulate msr move to status register mrs move from status register b branch bl branch and link bx branch and exchange swi software interrupt ldr load word str store word ldrsh load signed halfword ldrsb load signed byte ldrh load half word strh store half word ldrb load byte strb store byte
42 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 9.4.10 new arm instruction set . notes: 1. a thumb blx contains two consecutiv e thumb instructions, and takes four cycles. 9.4.11 thumb instruction set overview the thumb instruction set is a re-encoded subset of the arm instruction set. the thumb instruction set is divided into: ? branch instructions ? data processing instructions ? load and store instructions ldrbt load register byte with translation strbt store register byte with tr a n s l a t i o n ldrt load register with translation strt store register with tr a n s l a t i o n ldm load multiple stm store multiple swp swap word swpb swap byte mcr move to coprocessor mrc move from coprocessor ldc load to coprocessor stc store from coprocessor cdp coprocessor data processing table 9-2. arm instruction mnemonic list (continued) mnemonic operation mnemonic operation table 9-3. new arm instruction mnemonic list mnemonic operation mnemonic operation bxj branch and exchange to java mrrc move double from coprocessor blx (1) branch, link and exchange mcr2 alternative move of arm reg to coprocessor smlaxy signed multiply accumulate 16 * 16 bit mcrr move double to coprocessor smlal signed multiply accumulate long cdp2 alternative coprocessor data processing smlawy signed multiply accumulate 32 * 16 bit bkpt breakpoint smulxy signed multiply 16 * 16 bit pld soft preload, memory prepare to load from address smulwy signed multiply 32 * 16 bit strd store double qadd saturated add stc2 alternative store from coprocessor qdadd saturated add with double ldrd load double qsub saturated subtract ldc2 alternative load to coprocessor qdsub saturated subtract with double clz count leading zeroes
43 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? load and store multiple instructions ? exception-generating instruction table 9-4 gives the thumb instruction mnemonic list. table 9-4. thumb instruction mnemonic list mnemonic operation mnemonic operation mov move mvn move not add add adc add with carry sub subtract sbc subtract with carry cmp compare cmn compare negated tst test neg negate and logical and bic bit clear eor logical exclusive or or r logical (inclusive) or lsl logical shift left lsr logical shift right asr arithmetic shift right ror rotate right mul multiply blx branch, link, and exchange b branch bl branch and link bx branch and exchange swi software interrupt ldr load word str store word ldrh load half word strh store half word ldrb load byte strb store byte ldrsh load signed halfword ldrsb load signed byte ldmia load multiple stmia store multiple push push register to stack pop pop register from stack bcc conditional branch bkpt breakpoint
44 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 9.5 cp15 coprocessor coprocessor 15, or system control coprocessor cp15, is used to configure and control all the items in the list below: ? arm9ej-s ? caches (icache, dcache and write buffer) ?tcm ?mmu ? other system options to control these features, cp15 provides 16 additional registers. see table 9-5 . notes: 1. register locations 0,5, and 13 each provid e access to more than one register. the register accessed depends on the value of the opcode_2 field. 2. register location 9 provides access to more than one register. the register accessed depends on the value of the crm field. table 9-5. cp15 registers register name read/write 0 id code (1) read/unpredictable 0 cache type (1) read/unpredictable 0 tcm status (1) read/unpredictable 1 control read/write 2 translation table base read/write 3 domain access control read/write 4 reserved none 5 data fault status (1) read/write 5 instruction fault status (1) read/write 6 fault address read/write 7 cache operations read/write 8 tlb operations unpredictable/write 9 cache lockdown (2) read/write 9 tcm region read/write 10 tlb lockdown read/write 11 reserved none 12 reserved none 13 fcse pid (1) read/write 13 context id (1) read/write 14 reserved none 15 test configuration read/write
45 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 9.5.1 cp15 registers access cp15 registers can only be accessed in privileged mode by: ? mcr (move to coprocessor from arm register) instruction is used to write an arm register to cp15. ? mrc (move to arm register from coprocessor) instruction is used to read the value of cp15 to an arm register. other instructions like cdp, ldc, stc can cause an undefined instruction exception. the assembler code for these instructions is: mcr/mrc{cond} p15, opcode_1, rd, crn, crm, opcode_2. the mcr, mrc instructions bit pattern is shown below: ? crm[3:0]: specified coprocessor action determines specific coprocessor action. its value is dependen t on the cp15 register used. for details, refer to cp15 spe- cific register behavior. ? opcode_2[7:5] determines specific coprocessor operation code. by default, set to 0. ? rd[15:12]: arm register defines the arm register whose value is transferred to the co processor. if r15 is chosen, the result is unpredictable. ? crn[19:16]: coprocessor register determines the destination coprocessor register. ? l: instruction bit 0 = mcr instruction 1 = mrc instruction ? opcode_1[23:20]: coprocessor code defines the coprocessor specific code. value is c15 for cp15. ? cond [31:28]: condition for more details, see chapter 2 in arm926ej-s trm. 31 30 29 28 27 26 25 24 c o n d 1110 23 22 21 20 19 18 17 16 opcode_1 l crn 15 14 13 12 11 10 9 8 r d 1111 76543210 opcode_2 1 crm
46 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 9.6 memory management unit (mmu) the arm926ej-s processor implements an enhanced arm architecture v5 mmu to provide vir- tual memory features required by operati ng systems like symbian os , windowsce, and linux. these virtual memory features are memory access permission controls and virtual to physical address translations. the virtual address generated by the cpu core is converted to a modified virtual address (mva) by the fcse (fast context switch extens ion) using the value in cp15 register13. the mmu translates modified virtual addresses to physical addresses by using a single, two-level page table set stored in physical memory. each entry in the set contains the access permissions and the physical address that correspond to the virtual address. the first level translation tables contain 4096 entries indexed by bits [31:20] of the mva. these entries contain a pointer to either a 1 mb secti on of physical memory along with attribute infor- mation (access permissions, domain, etc.) or an entry in the second level translation tables; coarse table and fine table. the second level translation tables contain tw o subtables, coarse table and fine table. an entry in the coarse table contains a pointer to both large pages and small pages along with access permissions. an entry in the fine table contains a pointer to large, small and tiny pages. table 7 shows the different attributes of each page in the physical memory. the mmu consists of: ? access control logic ? translation look-aside buffer (tlb) ? translation table walk hardware 9.6.1 access control logic the access control logic controls access information for every entry in the translation table. the access control logic checks two pieces of access information: domain and access permissions. the domain is the primary access control mechanism for a memory region; there are 16 of them. it defines the conditions necessary for an access to proceed. the domain determines whether the access permissions are used to qualify the access or whether they should be ignored. the second access control mechanism is access permissions that are defined for sections and for large, small and tiny pages. sections and tiny pages have a single set of access permissions whereas large and small pages can be associated with 4 sets of access permissions, one for each subpage (quarter of a page). table 9-6. mapping details mapping name mapping size access permission by subpage size section 1m byte section - large page 64k bytes 4 separated subpages 16k bytes small page 4k bytes 4 separated subpages 1k byte tiny page 1k byte tiny page -
47 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 9.6.2 translation look-aside buffer (tlb) the translation look-aside buffer (tlb) caches translated entries and thus avoids going through the translation process every time. when the tlb contains an entry for the mva (modi- fied virtual address), the access control logic dete rmines if the access is permitted and outputs the appropriate physical address corresponding to the mva. if access is not permitted, the mmu signals the cpu core to abort. if the tlb does not contain an entry for the mva, the translation table walk hardware is invoked to retrieve the translation information from the translation table in physical memory. 9.6.3 translation table walk hardware the translation table walk hardware is a logic that traverses the translation tables located in physical memory, gets the ph ysical address and access permissions and updates the tlb. the number of stages in the hardware table walking is one or two depending whether the address is marked as a section-mapped access or a page-mapped access. there are three sizes of page-mapped accesses and one size of section-mapped access. page- mapped accesses are for large pages, small pages and tiny pages. the translation process always begins with a level one fetch. a section-mapped access requires only a level one fetch, but a page-mapped access requires an additional level two fetch. for further details on the mmu, please refer to chapter 3 in arm926ej-s technical reference manual. 9.6.4 mmu faults the mmu generates an abort on the following types of faults: ? alignment faults (for data accesses only) ? translation faults ? domain faults ? permission faults the access control mechanism of the mmu detects the conditions that produce these faults. if the fault is a result of memory access, the mmu aborts the access and signals the fault to the cpu core.the mmu retains status and address information about faults generated by the data accesses in the data fault status register and fault address register. it also retains the status of faults generated by instruction fetches in the instruction fault status register. the fault status register (register 5 in cp15) indicates the cause of a data or prefetch abort, and the domain number of the aborted access when it happens. the fault address register (register 6 in cp15) holds the mva associated with the access that caused the data abort. for further details on mmu faults, please refer to chapte r 3 in arm926ej-s technical reference manual. 9.7 caches and write buffer the arm926ej-s contains a 16kb instruction cache (icache), a 16kb data cache (dcache), and a write buffer. al though the icache and dcache share common features, each still has some specific mechanisms. the caches (icache and dcache) are four-way se t associative, addressed, indexed and tagged using the modified virtual address (mva), with a ca che line length of eight words with two dirty bits for the dcache. the icache and dcache provide mechanisms for cache lockdown, cache pollution control, and line replacement.
48 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 a new feature is now supported by arm926ej-s caches called allocate on read-miss commonly known as wrapping. this feature enables the caches to perform cr itical word first cache refilling. this means that when a request for a word caus es a read-miss, the cache performs an ahb access. instead of loading the whole line (eight words), the cache loads the critical word first, so the processor can reach it quickly, and then the remaining words, no matter where the word is located in the line. the caches and the write buffer are controlled by the cp15 register 1 (control), cp15 register 7 (cache operations) and cp15 register 9 (cache lockdown). 9.7.1 instruction cache (icache) the icache caches fetched instructions to be executed by the processor. the icache can be enabled by writing 1 to i bit of the cp15 register 1 and disabled by writing 0 to this same bit. when the mmu is enabled, all instruction fetches are subject to translation and permission checks. if the mmu is disabled, all instructions fetches are cachable, no protection checks are made and the physical address is flat-mapped to the modified virtual address. with the mva use disabled, context switching incurs icache cleaning and/or invalidating. when the icache is disabled, all instruction fetches appear on external memory (ahb) (see tables 4-1 and 4-2 in page 4-4 in arm926ej-s trm). on reset, the icache entries are invalidated and the icache is disabled. for best performance, icache should be enabled as soon as possible after reset. 9.7.2 data cache (dcache) and write buffer arm926ej-s includes a dcache and a write buffer to reduce the effect of main memory band- width and latency on data access performance. the operations of dcache and write buffer are closely connected. 9.7.2.1 dcache the dcache needs the mmu to be enabled. all data accesses are subject to mmu permission and translation checks. data acce sses that are aborted by the mmu do not cause linefills or data accesses to appear on the amba asb interface. if the mmu is disabled, all data accesses are noncachable, nonbufferable, with no protecti on checks, and appear on the ahb bus. all addresses are flat-mapped, va = mva = pa, whic h incurs dcache cleaning and/or invalidating every time a context switch occurs. the dcache stores the physical address tag (pa tag) from which every line was loaded and uses it when writing modified lines back to external memory. this means that the mmu is not involved in write-back operations. each line (8 words) in the dcache has two dirty bits, one for the first four words and the other one for the second four words. these bits, if set, mark the associated half- lines as dirty. if the cache line is replaced due to a linefill or a cache cl ean operation, the dirty bits are used to decide whether all, half or none is written back to memory. dcache can be enabled or disabled by writing either 1 or 0 to bit c in register 1 of cp15 (see tables 4-3 and 4-4 on page 4-5 in arm926ej-s trm). the dcache supports write-through and write-back cache operations, selected by memory region using the c and b bits in the mmu translation tables.
49 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 the dcache contains an eight data word entr y, single address entry write-back buffer used to hold write-back data for cache line eviction or cleaning of dirty cache lines. the write buffer can hold up to 16 words of data and four separate addresses. dcache and write buffer operations are closely connected as their configuration is set in each section by the page descriptor in the mmu translation table. 9.7.2.2 write buffer the arm926ej-s contains a write buffer that has a 16-word data buffer and a four- address buf- fer. the write buffer is used for all writes to a bufferable region, write-through region and write- back region. it also allows to avoid stalling the processor when writes to external memory are performed. when a store occurs, data is written to the write buffer at core speed (high speed). the write buffer then completes the store to external memory at bus speed (typically slower than the core speed). during this time, the arm9ej-s processor can preform other tasks. dcache and write buffer support write-back and write-through memory regions, controlled by c and b bits in each section and page descriptor within the mmu translation tables. 9.7.2.3 write-though operation when a cache write hit occurs, the dcache line is updated. the updated data is then written to the write buffer which transfers it to external memory. when a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. 9.7.2.4 write-back operation when a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not up-to-date with those in the external memory. when a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory.
50 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 9.8 bus interface unit the arm926ej-s features a bus interface unit (biu) that arbitrates and schedules ahb requests. the biu implements a multi-layer ahb, based on the ahb-lite protocol, that enables parallel access paths between multiple ahb masters and slaves in a system. this is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. the multi-master bus architecture has a number of benefits: ? it allows the development of multi-master systems with an increased bus bandwidth and a flexible architecture. ? each ahb layer becomes simple because it only has one master, so no arbitration or master- to-slave muxing is required. ahb layers, implementing ahb-lite protocol, do not have to support request and grant, nor do they have to support retry and split transactions. ? the arbitration becomes effective when more than one master wants to access the same slave simultaneously. 9.8.1 supported transfers the arm926ej-s processor performs all ahb accesses as single word, bursts of four words, or bursts of eight words. any arm9ej-s core request that is not 1, 4, 8 word s in size is split into packets of these sizes. note that the atmel ? bus is ahb-lite protocol compliant, hence it does not support split and retry requests. table 8 gives an overview of the supported transfers and different kinds of transactions they are used for. 9.8.2 thumb instruction fetches all instructions fetches, regardless of the state of arm9ej-s core, are made as 32-bit accesses on the ahb. if the arm9ej-s is in thumb state, then two instructions can be fetched at a time. 9.8.3 address alignment the arm926ej-s biu performs address alignment checking and aligns ahb addresses to the necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word boundaries. table 9-7. supported transfers hburst[2:0] description single single transfer single transfer of word, half word, or byte: ? data write (ncnb, ncb, wt, or wb that has missed in dcache) ? data read (ncnb or ncb) ? nc instruction fetch (prefetched and non-prefetched) ? page table walk read incr4 four-word incrementing burst half-line cache write-back, instruction pr efetch, if enabled. four-word burst ncnb, ncb, wt, or wb write. incr8 eight-word incrementing burst full-line cache writ e-back, eight-word burst ncnb, ncb, wt, or wb write. wrap8 eight-word wrapping burst cache linefill
51 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 10. debug and test 10.1 description the sam9cn12 features a number of complementary debug and test capabilities. a common jtag/ice (in-circuit emulator) port is used for standard debugging functions, such as down- loading code and single-stepping through programs. the debug unit provides a two-pin uart that can be used to upload an application into internal sram. it manages the interrupt handling of the internal commtx and commrx signals t hat trace the activity of the debug communica- tion channel. a set of dedicated deb ug and test input/ou tput pins gives direct acce ss to these capabilities from a pc-based test environment. 10.2 embedded characteristics debug capabilities can be forbidden with a fuse bit. ? arm926 real-time in-circuit emulator C two real-time watchpoint units C two independent registers: debug control register and debug status register C test access port accessible through jtag protocol C debug communications channel ? debug unit Ctwo-pin uart C debug communication channel interrupt handling C chip id register ? ieee1149.1 jtag boundary-scan on all digital pins .
52 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 10.3 block diagram figure 10-1. debug and test block diagram ice-rt arm9ej-s dbgu pio drxd dtxd tms tck tdi jtagsel tdo reset tap: test access port boundary port ice/jtag ta p arm926ej-s por rtck ntrst dma
53 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 10.4 application examples 10.4.1 debug environment figure 10-2 on page 53 shows a complete debug environment example. the ice/jtag inter- face is used for standard debugging functions, such as downloading code and single-stepping through the program. a software debugger running on a personal computer provides the user interface for configuring a trace port interf ace utilizing the ice/jtag interface. figure 10-2. application debug and trace environment example at91sam9-based application board ice/ jtag interface host debugger ice/ jtag connector at91sam9 te r m i n a l rs232 connector
54 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 10.4.2 test environment figure 10-3 on page 54 shows a test environment example. test vectors are sent and inter- preted by the tester. in this example, the board in test is designed using a number of jtag- compliant devices. these devi ces can be connected to form a single scan chain. figure 10-3. application test environment example 10.5 debug and test pin description jtag interface ice/ jtag connector at91sam9-based application board in test at91sam9 te st a d a p t o r ch i p 2 ch i p n ch i p 1 te st e r table 10-1. debug and test pin list pin name function type active level reset/test nrst microcontroller reset input/output low ice and jtag ntrst test reset signal input low tck test clock input tdi test data in input tdo test data out output tms test mode select input rtck returned test clock output jtagsel jtag selection input debug unit drxd debug receive data input dtxd debug transmit data output
55 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 10.6 functional description 10.6.1 embeddedice the arm9ej-s embeddedice-rt ? is supported via the ice/jtag port. it is connected to a host computer via an ice interface. debug support is implemented using an arm9ej-s core embedded within the arm926ej-s. the internal state of the arm926ej-s is examined through an ice/jtag port which allows instructions to be serially inserted into the pipeline of the core without using the external data bus. therefore, when in debug state, a store-multiple (stm) can be inserted into the instruction pipeline. this exports the contents of the arm9ej-s registers. this data can be serially shifted out without affecting the rest of the system. there are two scan chains inside the arm9ej -s processor which support testing, debugging, and programming of the embeddedice-rt. the scan chains are controlled by the ice/jtag port. embeddedice mode is selected when jtagsel is low. it is not possible to switch directly between ice and jtag operations. a chip reset must be performed after jtagsel is changed. for further details on the embeddedice-rt, see the arm document: arm9ej-s technical reference manual (ddi 0222a). 10.6.2 jtag signal description tms is the test mode select input which controls the transitions of the test interface state machine. tdi is the test data input line which supplies the data to the jtag registers (boundary scan register, instruction register, or other data registers). tdo is the test data output line which is used to serially output the data from the jtag regis- ters to the equipment controlling the test. it carries the sampled values from the boundary scan chain (or other jtag registers) and propagates them to the next chip in the serial test circuit. ntrst (optional in ieee standard 1149.1) is a test-reset input which is mandatory in arm cores and used to reset the debug logic. on atmel arm926ej-s-based cores, ntrst is a power on reset output. it is asserted on power on. if necessary, the user can also reset the debug logic with the ntrst pin assertion during 2.5 mck periods. tck is the test clock input which enables the te st interface. tck is pulsed by the equipment controlling the test and not by the tested device. it can be pulsed at any frequency. note the maximum jtag clock rate on arm926ej-s cores is 1/6th the clock of the cpu. this gives 5.45 khz maximum initial jtag clock rate for an ar m9e running from the 32.768 khz slow clock. rtck is the return test clock. not an ieee standard 1149.1 signal added for a better clock handling by emulators. from some ice interface probes, this return signal can be used to syn- chronize the tck clock and take not care about the given ratio between the ice interface clock and system clock equal to 1/6th. this signal is only available in jtag ice mode and not in boundary scan mode. 10.6.3 debug unit the debug unit provides a two-pin (dxrd a nd txrd) usart that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. moreover, the association with two peripheral data controller channels permits packet handling of these tasks with processor time reduced to a minimum.
56 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 the debug unit also manages the interrupt handling of the commtx and commrx signals that come from the ice and that trace the activity of the debug communication channel.the debug unit allows blockage of access to the system through the ice interface. a specific register, the debug unit chip id register, gives information about the product version and its internal configuration. for further details on the debug unit, see the debug unit section. 10.6.4 ieee 1149.1 jtag boundary scan ieee 1149.1 jtag boundary scan allows pin-level access independent of the device packaging technology. ieee 1149.1 jtag boundary scan is enabled when jtagsel is high. the sample, extest and bypass functions are implemented. in ice debug mode, the ar m processor responds with a non-jtag ch ip id that identifi es the processo r to the ice system. this is not ieee 1149.1 jtag-compliant. it is not possible to switch directly between jtag and ice operations. a chip reset must be per- formed after jtagsel is changed. a boundary-scan descriptor language (bsdl) file is provided to set up test.
57 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 10.6.5 jtag id code register access: read-only ? version[31:28]: product version number set to 0x0. ? part number[27:12]: product part number product part number is 0x05b3 ? manufacturer identity[11:1] set to 0x01f. bit[0] required by ieee std. 1149.1. set to 0x1. jtag id code value is 0x05b3_003f. 31 30 29 28 27 26 25 24 version part number 23 22 21 20 19 18 17 16 part number 15 14 13 12 11 10 9 8 part number manufacturer identity 76543210 manufacturer identity 1
58 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12
59 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 59 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 11. advanced interrupt controller (aic) 11.1 description the advanced interrupt controller (aic) is an 8-level priority, individually maskable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources. it is designed to sub- stantially reduce the software and real-time overhead in handling internal and external interrupts. the aic drives the nfiq (fast interrupt request) and the nirq (standard interrupt request) inputs of an arm processor. inputs of the aic are either internal peripheral interrupts or external inter- rupts coming from the product's pins. the 8-level priority controller allows the user to define the priority for each interrupt source, thus permitting higher priority interrupts to be serviced even if a lower priority interrupt is being treated. internal interrupt sources can be programmed to be level sensitive or edge triggered. external interrupt sources can be programmed to be positive-edge or negative-edge triggered or high- level or low-level sensitive. the fast forcing feature redirects any internal or external interrupt source to provide a fast inter- rupt rather than a normal interrupt. 11.2 embedded characteristics ? controls the interrupt lines (nirq and nfiq) of an arm ? processor ? thirty-two individually maskable and vectored interrupt sources C source 0 is reserved for the fast interrupt input (fiq) C source 1 is reserved for system peripherals C source 2 to source 31 control up to thirty embedded peripheral interrupts or external interrupts C programmable edge-triggered or level-sensitive internal sources C programmable positive/negative edge-triggered or high/low level-sensitive external sources ? 8-level priority controller C drives the normal interrupt of the processor C handles priority of the interrupt sources 1 to 31 C higher priority interrupts can be served during service of lower priority interrupt ? vectoring C optimizes interrupt service routine branch and execution C one 32-bit vector register per interrupt source C interrupt vector register reads the corresponding current interrupt vector ?protect mode C easy debugging by preventing automatic operations when protect models are enabled ?fast forcing C permits redirecting any normal interrupt source to the fast interrupt of the processor
60 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 60 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? general interrupt mask C provides processor synchronization on ev ents without triggering an interrupt ? write protected registers 11.3 block diagram figure 11-1. block diagram 11.4 application block diagram figure 11-2. description of the application block aic apb arm processor fiq irq0-irqn embedded peripheralee peripheral embedded peripheral embedded up to thirty-two sources nfiq nirq advanced interrupt controller embedded peripherals external peripherals (external interrupts) standalone applications rtos drivers hard real time tasks os-based applications os drivers general os interrupt handler
61 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 61 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 11.5 aic detailed block diagram figure 11-3. aic detailed block diagram 11.6 i/o line description 11.7 product dependencies 11.7.1 i/o lines the interrupt signals fiq and irq0 to irqn are normally multiplexed through the pio control- lers. depending on the features of the pio controller used in the product, the pins must be programmed in accordance with their assigned interrupt function. this is not applicable when the pio controller used in the product is transparent on the input path. 11.7.2 power management the advanced interrupt controller is continuously clocked. the power management controller has no effect on the advanced interrupt controller behavior. the assertion of the advanced interrupt controller outputs, either nirq or nfiq, wakes up the arm processor while it is in idle mode. the general interrupt mask feature enables the aic to fiq pio controller advanced interrupt controller irq0-irqn pioirq embedded peripherals external source input stage internal source input stage fast forcing interrupt priority controller fast interrupt controller arm processor nfiq nirq power management controller wake up user interface apb processor clock table 11-1. i/o line description pin name pin description type fiq fast interrupt input irq0 - irqn interrupt 0 - interrupt n input table 11-2. i/o lines instance signal i/o line peripheral aic fiq pc31 a aic irq pb18 a
62 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 62 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 wake up the processor without asserting the interr upt line of the processor, thus providing syn- chronization of the processor on an event. 11.7.3 interrupt sources the interrupt source 0 is always located at fiq. if the product does not feature an fiq pin, the interrupt source 0 cannot be used. the interrupt source 1 is always located at system interrupt. this is the result of the or-wiring of the system peripheral interrupt lines. when a system interrupt occurs, the service routine must first distinguish the cause of the interrupt . this is performed by reading successively the status registers of the above mentioned system peripherals. the interrupt sources 2 to 31 can either be connected to the interrupt outputs of an embedded user peripheral or to external interrupt lines . the external interrupt lines can be connected directly, or through the pio controller. the pio controllers are considered as user peripherals in the scope of interrupt handling. accordingly, the pio controller interrupt lines are connected to the interrupt sources 2 to 31. the peripheral identification defined at the product level corresponds to the interrupt source number (as well as the bit number controlling the clock of the peri pheral). conseq uently, to sim- plify the description of the functional operations and the user interface, the interrupt sources are named fiq, sys, and pid2 to pid31. 11.8 functional description 11.8.1 interrupt source control 11.8.1.1 interrupt source mode the advanced interrupt controller independently programs each interrupt source. the src- type field of the corresponding aic_smr (source mode register) selects the interrupt condition of each source. the internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in level-sensitive mode or in edge-triggered mode. the active level of the internal interrupts is not important for the user. the external interrupt sources can be programmed either in high level-sensitive or low level-sen- sitive modes, or in positive edge-triggered or negative edge-triggered modes. 11.8.1.2 interrupt source enabling each interrupt source, including the fiq in source 0, can be enabled or disabled by using the command registers; aic_iecr (interrupt enable command register) and aic_idcr (interrupt disable command register). this set of registers conducts enabling or disabling in one instruc- tion. the interrupt mask can be read in the aic_imr register. a disabled interrupt does not affect servicing of other interrupts. 11.8.1.3 interrupt clearing and setting all interrupt sources programmed to be edge-triggered (including the fiq in source 0) can be individually set or cleared by writing respectively the aic_iscr and aic_iccr registers. clear- ing or setting interrupt sources programmed in level-sensitive mode has no effect.
63 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 63 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 the clear operation is perfunctory, as the softwa re must perform an acti on to reinitialize the memorization circuitry activated when the source is programmed in edge-triggered mode. however, the set operation is available for auto-test or software debug purposes. it can also be used to execute an aic-implementation of a software interrupt. the aic features an automatic clear of the current interrupt when the aic_ivr (interrupt vector register) is read. only the interrupt source being detected by the aic as the current interrupt is affected by this operation. ( see priority controller on page 65. ) the automatic clear reduces the operations required by the interrupt service routine entry code to reading the aic_ivr. note that the automatic interrupt clear is disabled if the interrupt source has the fast forcing feature enabled as it is considered uniquely as a fiq source. (for further details, see fast forcing on page 69. ) the automatic clear of the interrupt source 0 is performed when aic_fvr is read. 11.8.1.4 interrupt status for each interrupt, the aic operation originates in aic_ipr (interrupt pending register) and its mask in aic_imr (interrupt mask register). aic_ipr enables the actual activity of the sources, whether masked or not. the aic_isr register reads the number of the current interrupt (see priority controller on page 65 ) and the register aic_cisr gives an image of the signals nirq and nfiq driven on the processor. each status referred to above can be used to optimize the interrupt handling of the systems. figure 11-4. internal interrupt source input stage edge detector clearset source i aic_ipr aic_imr aic_iecr aic_idcr aic_iscr aic_iccr fast interrupt controller or priority controller ff le v el/ edge aic_smri (srctype)
64 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 64 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 11-5. external interrupt source input stage 11.8.2 interrupt latencies global interrupt latencies depend on several parameters, including: ? the time the software masks the interrupts. ? occurrence, either at the processor level or at the aic level. ? the execution time of the instruction in progress when the interrupt occurs. ? the treatment of higher priority interrupts and the resynchronization of the hardware signals. this section addresses only the hardware resync hronizations. it gives details of the latency times between the event on an external interrupt leading in a valid interrupt (edge or level) or the assertion of an internal interrupt source and the assertion of the nirq or nfiq line on the pro- cessor. the resynchronization time depends on the programming of the interrupt source and on its type (internal or external). for the standard interrupt, resynchronization times are given assuming there is no higher priority in progress. the pio controller multiplexing has no effect on the interrupt latencies of the external interrupt sources. figure 11-6. external interrupt edge triggered source edge detector clear set pos./neg. aic_iscr aic_iccr source i ff level/ edge high/low aic_smri srctype aic_ipr aic_imr aic_iecr aic_idcr fast interrupt controller or priority controller maximum fiq latency = 4 cycles maximum irq latency = 4 cycles nfiq nirq mck irq or fiq (positive edge) irq or fiq (negative edge)
65 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 65 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 11-7. external interrupt level sensitive source figure 11-8. internal interrupt edge triggered source figure 11-9. internal interrupt level sensitive source 11.8.3 normal interrupt 11.8.3.1 priority controller an 8-level priority controller drives the nirq line of the processor, depending on the interrupt conditions occurring on the interrupt sources 1 to 31 (except for those programmed in fast forcing). maximum irq latency = 3 cycles maximum fiq latency = 3 cycles mck irq or fiq (high level) irq or fiq (low level) nirq nfiq mck nirq peripheral interrupt becomes active maximum irq latency = 4.5 cycles mck nirq maximum irq latency = 3.5 cycles peripheral interrupt becomes active
66 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 66 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 each interrupt source has a programmable priority le vel of 7 to 0, which is user-definable by writ- ing the prior field of the corresponding aic_smr (source mode register). level 7 is the highest priority and level 0 the lowest. as soon as an interrupt condition occurs, as defined by the srctype field of the aic_smr (source mode register), the nirq line is asserted. as a new interrupt condition might have hap- pened on other interrupt sources since the nirq has been asserted, the priority controller determines the current interrupt at the time the aic_ivr (interrupt vector register) is read. the read of aic_ivr is the entry point of the interrupt handling which allows the aic to consider that the interrupt has been taken into account by the software. the current priority level is defined as the priority level of the current interrupt. if several interrupt sources of equal priority are pending and enabled when the aic_ivr is read, the interrupt with the lowest interrupt source number is serviced first. the nirq line can be asserted only if an interrupt cond ition occurs on an in terrupt source with a higher priority. if an interrupt condition happens (or is pending) during the interrupt treatment in progress, it is delayed until the software indicates to the aic the end of the current service by writing the aic_eoicr (end of interrupt command register). the write of aic_eoicr is the exit point of the interrupt handling . 11.8.3.2 interrupt nesting the priority controller utilizes interr upt nesting in order for the high priority interrup t to be handled during the service of lower priori ty interrupts. this requires the interrupt service routines of the lower interrupts to re-enable the interrupt at the processor level. when an interrupt of a higher priority happens during an already occurring interrupt service rou- tine, the nirq line is re-asserted. if the interrupt is enabled at the core level, the current execution is interrupted and the new interrupt service routine should read the aic_ivr. at this time, the current interrupt number and its priority level are pushed into an embedded hardware stack, so that they are saved and restored when the higher priority interrupt servicing is finished and the aic_eoicr is written. the aic is equipped with an 8-leve l wide hardware stack in order to support up to eight interrupt nestings pursuant to having eight priority levels. 11.8.3.3 interrupt vectoring the interrupt handler addresses corresponding to each interrupt source can be stored in the reg- isters aic_svr1 to aic_svr31 (source vector register 1 to 31). when the processor reads aic_ivr (interrupt vector register), the value written into aic_svr corresponding to the cur- rent interrupt is returned. this feature offers a way to branch in one single instruction to the handler corresponding to the current interrupt, as aic_ivr is mapped at the absolute address 0xffff f100 and thus acces- sible from the arm interrupt vector at address 0x0000 0018 through the following instruction: ldr pc,[pc,# -&f20] when the processor executes this instruction, it loads the read value in aic_ivr in its program counter, thus branching the execution on the correct interrupt handler. this feature is often not used when the application is based on an operating system (either real time or not). operating systems often have a single entry point for all the interrupts and the first task performed is to discern the source of the interrupt.
67 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 67 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 however, it is strongly recommended to port the operating system on at91 products by support- ing the interrupt vectoring. this can be performed by defining all the aic_svr of the interrupt source to be handled by the operating system at the address of its interrupt handler. when doing so, the interrupt vectoring permits a critical inte rrupt to transfer the execution on a specific very fast handler and not onto the operating systems general interrupt handler. this facilitates the support of hard real-time tasks (input/outputs of voice/audio buffers and software peripheral han- dling) to be handled efficiently and independently of the application running under an operating system. 11.8.3.4 interrupt handlers this section gives an overview of the fast interrupt handling sequence when using the aic. it is assumed that the programmer understands the architecture of the arm processor, and espe- cially the processor interrupt mode s and the associated status bits. it is assumed that: 1. the advanced interrupt controller has been programmed, aic_svr registers are loaded with corresponding interrupt service routine addresses and interrupts are enabled. 2. the instruction at the arm interrupt exception vector address is required to work with the vectoring ldr pc, [pc, # -&f20] when nirq is asserted, if the bit i of cpsr is 0, the sequence is as follows: 1. the cpsr is stored in spsr_i rq, the current value of the program coun ter is loaded in the interrupt link register (r14_irq) and the program counter (r15) is loaded with 0x18. in the following cycle during fetch at address 0x1c, the arm core adjusts r14_irq, dec- rementing it by four. 2. the arm core enters interrupt mode, if it has not already done so. 3. when the instruction loaded at address 0x18 is executed, the program counter is loaded with the value read in aic_ivr. reading the aic_ivr has the following effects: C sets the current interrupt to be the pending and enabled interrupt with the highest priority. the current level is the priority level of the current interrupt. C de-asserts the nirq line on the processor. even if vectoring is not used, aic_ivr must be read in order to de-assert nirq. C automatically clears the interrupt, if it has been programmed to be edge-triggered. C pushes the current level and the current interrupt number on to the stack. C returns the value written in the aic_svr corresponding to the current interrupt. 4. the previous step has the effect of branc hing to the corresponding interrupt service routine. this should start by saving the link register (r14_irq) and spsr_irq. the link register must be decremented by four when it is saved if it is to be restored directly into the program counter at the end of the interrupt. for example, the instruction sub pc, lr, #4 may be used. 5. further interrupts can then be unmasked by clearing the i bit in cpsr, allowing re- assertion of the nirq to be taken into account by the core. this can happen if an inter- rupt with a higher priority than the current interrupt occurs. 6. the interrupt handler can th en proceed as required, saving the registers that will be used and restoring them at the end. during this phase, an interrupt of higher priority than the current leve l will restart the sequence from step 1.
68 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 68 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 note: if the interrupt is programmed to be level sensitiv e, the source of the interrupt must be cleared dur- ing this phase. 7. the i bit in cpsr must be set in order to mask interrupts before exiting to ensure that the interrupt is completed in an orderly manner. 8. the end of interrupt command register (aic_eoicr) must be written in order to indi- cate to the aic that the current interrupt is finished. this causes the current level to be popped from the stack, restoring the previous current level if one exists on the stack. if another interrupt is pending, with lower or equal priority than the old current level but with higher priority than the new current level, the nirq line is re-asserted, but the inter- rupt sequence does not immediately start because the i bit is set in the core. spsr_irq is restored. fina lly, the saved value of the link regi ster is restored directly into the pc. this has the effect of returning from the interrupt to whatever was being exe- cuted before, and of loading the cpsr with the stored spsr, masking or unmasking the interrupts depending on the state saved in spsr_irq. note: the i bit in spsr is significant. if it is set, it indicates that the arm core was on the verge of masking an interrupt when the mask instruction was in terrupted. hence, when spsr is restored, the mask instruction is comple ted (interrupt is masked). 11.8.4 fast interrupt 11.8.4.1 fast interrupt source the interrupt source 0 is the only source which can raise a fast interrupt request to the processor except if fast forcing is used. the interrupt so urce 0 is generally connected to a fiq pin of the product, either directly or through a pio controller. 11.8.4.2 fast interrupt control the fast interrupt logic of the aic has no priority controller. the mode of interrupt source 0 is programmed with the aic_smr0 and the field prior of this register is not used even if it reads what has been written. the fi eld srctype of aic_smr0 enables programming the fast inter- rupt source to be positive-edge triggered or negative-edge triggered or high-level sensitive or low-level sensitive writing 0x1 in the aic_iecr (interrupt enable command register) and aic_idcr (interrupt disable command register) respectively enables and disables the fast interrupt. the bit 0 of aic_imr (interrupt mask register) indicates whet her the fast interrupt is enabled or disabled. 11.8.4.3 fast interrupt vectoring the fast interrupt handler address can be stor ed in aic_svr0 (source vector register 0). the value written into this register is returned when the processor reads aic_fvr (fast vector reg- ister). this offers a way to branch in one single instruction to the interrupt handler, as aic_fvr is mapped at the absolute address 0xffff f104 and thus accessible from the arm fast inter- rupt vector at address 0x0000 001c through the following instruction: ldr pc,[pc,# -&f20] when the processor executes this instruction it loads the value read in aic_fvr in its program counter, thus branching the execution on the fast interrupt handler. it also automatically per- forms the clear of the fast interrupt source if it is programmed in edge-triggered mode. 11.8.4.4 fast interrupt handlers this section gives an overview of the fast interrupt handling sequence when using the aic. it is assumed that the programmer understands the architecture of the arm processor, and espe- cially the processor interrupt modes and associated status bits.
69 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 69 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 assuming that: 1. the advanced interrupt controller has been programmed, aic_svr0 is loaded with the fast interrupt service routine address, and the interrupt source 0 is enabled. 2. the instruction at address 0x1c (fiq exception vector address) is required to vector the fast interrupt: ldr pc, [pc, # -&f20] 3. the user does not need nested fast interrupts. when nfiq is asserted, if the bit f of cpsr is 0, the sequence is: 1. the cpsr is stored in spsr_fiq, the current value of the program counter is loaded in the fiq link register (r14_fiq) and the program counter (r15) is loaded with 0x1c. in the following cycle, during fetch at address 0x20, the arm core ad justs r14_fiq, decre- menting it by four. 2. the arm core enters fiq mode. 3. when the instruction loaded at address 0x1c is executed, the program counter is loaded with the value read in aic_fvr. re ading the aic_fvr has effect of automati- cally clearing the fast interrupt, if it has been programmed to be edge triggered. in this case only, it de-asserts the nfiq line on the processor. 4. the previous step enables branching to the corresponding interrupt service routine. it is not necessary to save the link register r14_fiq and spsr_fiq if nested fast interrupts are not needed. 5. the interrupt handler can then proceed as required. it is not necessary to save regis- ters r8 to r13 because fiq mode has its own dedicated registers and the user r8 to r13 are banked. the other registers, r0 to r7, must be saved before being used, and restored at the end (before the next step). note that if the fast interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase in order to de-assert the interrupt source 0. 6. finally, the link register r14_fiq is restored into the pc after decrementing it by four (with instruction sub pc, lr, #4 for example). this has the effect of returning from the interrupt to whatever was being exec uted before, loading the cpsr with the spsr and masking or unmasking the fast interrupt depending on the state saved in the spsr. note: the f bit in spsr is significant. if it is set, it indicates that the arm core was just about to mask fiq interrupts when the mask instru ction was interrupted. hence wh en the spsr is restored, the interrupted instruction is completed (fiq is masked). another way to handle the fast interrupt is to map the interrupt service routine at the address of the arm vector 0x1c. this method does not use the vectoring, so that reading aic_fvr must be performed at the very beginning of the handler operation. however, this method saves the execution of a branch instruction. 11.8.4.5 fast forcing the fast forcing feature of the advanced interrupt controller provides redirection of any normal interrupt source on the fast interrupt controller. fast forcing is enabled or disabl ed by writing to the fast forcing enable register (aic_ffer) and the fast forcing disable register (aic_ff dr). writing to these registers results in an update of the fast forcing status register (aic_ffsr) that controls the feature for each inter- nal or external interrupt source. when fast forcing is disabled, the interrupt sources are handled as described in the previous pages.
70 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 70 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 when fast forcing is enabled, the edge/level programming and, in certain cases, edge detec- tion of the interrupt s ource is still active but the source c annot trigger a normal interrupt to the processor and is not seen by the priority handler. if the interrupt source is programmed in level- sensitive mode and an active level is sampled, fast forcing results in the assertion of the nfiq line to the core. if the interrupt source is programmed in edge-triggered mode and an active edge is detected, fast forcing results in the assertion of the nfiq line to the core. the fast forcing feature does not affect the source 0 pending bit in the interrupt pending reg- ister (aic_ipr). the fiq vector register (aic_fvr) reads the contents of the source vector register 0 (aic_svr0), whatever the source of the fast interrupt may be. the read of the fvr does not clear the source 0 when the fast forcing feature is used and the interrupt source should be cleared by writing to the interrupt cl ear command register (aic_iccr). all enabled and pending interrupt sources that have the fast forcing feature enabled and that are programmed in edge-triggered mode must be cleared by writing to the interrupt clear command register. in doing so, they are cleared independently and thus lost interrupts are prevented. the read of aic_ivr does not clear the source that has the fast forcing feature enabled. the source 0, reserved to the fast interrupt, continues operating normally and becomes one of the fast interrupt sources. figure 11-10. fast forcing 11.8.5 protect mode the protect mode permits reading the interrupt vector register without performing the associ- ated automatic operations. this is necessary when working with a debug system. when a debugger, working either with a debug monitor or the arm processor's ice, stops the applica- tions and updates the opened windows, it might read the aic user interface and thus the ivr. this has undesirable consequences: ? if an enabled interrupt with a higher priority than the current one is pending, it is stacked. ? if there is no enabled pending interrupt, the spurious vector is returned. source 0 _ fiq input stage automatic clear input stage automatic clear source n aic_ipr aic_imr aic_ffsr aic_ipr aic_imr priority manager nfiq nirq read ivr if source n is the current interrupt and if fast forcing is disabled on source n. read fvr if fast forcing is disabled on sources 1 to 31.
71 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 71 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 in either case, an end of interrupt command is necessary to acknowledge and to restore the context of the aic. this operation is generally not performed by the debug system as the debug system would become strongly intrusive and caus e the application to enter an undesired state. this is avoided by using the protect mode. wr iting prot in aic_dcr (debug control register) at 0x1 enables the protect mode. when the protect mode is enabled, the aic performs interrupt stacking only when a write access is performed on the aic_ivr. therefore, the interrupt service routines must write (arbitrary data) to the aic_ivr just after reading it. the new context of the aic, including the value of the interrupt status register (aic_isr), is updated with the current interrupt only when aic_ivr is written. an aic_ivr read on its own (e.g., by a debugger), modifies neither the aic context nor the aic_isr. extra aic_ivr reads perform the same operations. however, it is recommended to not stop the processor between the read and the write of aic_ivr of the interrupt service routine to make sure the debugger does not modify the aic context. to summarize, in normal operating mode, the read of aic_ivr performs the following opera- tions within the aic: 1. calculates active interrupt (higher than current or spurious). 2. determines and returns the vector of the active interrupt. 3. memorizes the interrupt. 4. pushes the current priority level onto the internal stack. 5. acknowledges the interrupt. however, while the protect mode is activated, only operations 1 to 3 are performed when aic_ivr is read. operations 4 and 5 are only performed by the aic when aic_ivr is written. software that has been written and debugged using the protect mode runs correctly in normal mode without modification. however, in normal mode the aic_ivr write has no effect and can be removed to optimize the code. 11.8.6 spurious interrupt the advanced interrupt controller features protection against spurious interrupts. a spurious interrupt is defined as being the assertion of an interrupt source long enough for the aic to assert the nirq, but no longer present when aic_ivr is read. this is most prone to occur when: ? an external interrupt source is programmed in level-sensitive mode and an active level occurs for only a short time. ? an internal interrupt source is programmed in level sensitive and the output signal of the corresponding embedded peripheral is activated for a short time. (as in the case for the watchdog.) ? an interrupt occurs just a few cycles before the software begins to mask it, thus resulting in a pulse on the interrupt source. the aic detects a spurious interrupt at the time the aic_ivr is read while no enabled interrupt source is pending. when this happens, the aic returns the value stored by the programmer in aic_spu (spurious vector register). the pr ogrammer must store the address of a spurious interrupt handler in aic_spu as part of the application, to enable an as fast as possible return to the normal execution flow. this handler writes in aic_eoicr and performs a return from interrupt.
72 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 72 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 11.8.7 general interrupt mask the aic features a general interrupt mask bit to prevent interrupts from reaching the processor. both the nirq and the nfiq lines are driven to their inactive state if the bit gmsk in aic_dcr (debug control register) is set. however, this mask does not prevent waking up the processor if it has entered idle mode. this function facilitates synchronizing the processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle an interrupt. it is strongly recommended to use this mask with caution. 11.9 write protection registers to prevent any single software error that may corrupt aic behavior, the registers listed below can be write-protected by setting the wpen bit in the aic write protect mode register (aic_wpmr). if a write access in a write- protected register is detected, then the wpvs flag in the aic write protect status register (aic_wpsr) is set and the wpvsrc fi eld indicates in which register the write access has been attempted. the wpvs flag is automatically reset after re ading the aic write prot ect status register. the protected registers are: ? aic source mode register on page 74 ? aic source vector register on page 75 ? aic spurious interrupt vector register on page 87 ? aic debug control register on page 88
73 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 73 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 11.10 advanced interrupt controll er (aic) user interface 11.10.1 base address the aic is mapped at the address 0xffff f000 . it has a total 4-kbyte addressing space. this permits the vectoring fea- ture, as the pc-relative load/store instructions of the arm processor support only a 4-kbyte offset. notes: 1. the reset value of this register depends on the level of the external interrupt source. all other sources are cleared a t reset, thus not pending. 2. pid2...pid31 bit fields refer to the identifiers as defined in the peripheral identifiers section of the product datasheet. 3. values in the version register vary with the version of the ip block implementation. table 11-3. register mapping offset register name access reset 0x00 source mode register 0 aic_smr0 read-write 0x0 0x04 source mode register 1 aic_smr1 read-write 0x0 --- --- --- --- --- 0x7c source mode register 31 aic_smr31 read-write 0x0 0x80 source vector register 0 aic_svr0 read-write 0x0 0x84 source vector register 1 aic_svr1 read-write 0x0 --- --- --- --- --- 0xfc source vector register 31 aic_svr31 read-write 0x0 0x100 interrupt vector register aic_ivr read-only 0x0 0x104 fiq interrupt vector register aic_fvr read-only 0x0 0x108 interrupt status register aic_isr read-only 0x0 0x10c interrupt pending register (2) aic_ipr read-only 0x0 (1) 0x110 interrupt mask register (2) aic_imr read-only 0x0 0x114 core interrupt status register aic_cisr read-only 0x0 0x118 - 0x11c reserved --- --- --- 0x120 interrupt enable command register (2) aic_iecr write-only --- 0x124 interrupt disable command register (2) aic_idcr write-only --- 0x128 interrupt clear command register (2) aic_iccr write-only --- 0x12c interrupt set command register (2) aic_iscr write-only --- 0x130 end of interrupt command register aic_eoicr write-only --- 0x134 spurious interrupt vector register aic_spu read-write 0x0 0x138 debug control register aic_dcr read-write 0x0 0x13c reserved --- --- --- 0x140 fast forcing enable register (2) aic_ffer write-only --- 0x144 fast forcing disable register (2) aic_ffdr write-only --- 0x148 fast forcing status register (2) aic_ffsr read-only 0x0 0x14c - 0x1e0 reserved --- --- --- 0x1e4 write protect mode register aic_wpmr read-write 0x0 0x1e8 write protect status register aic_wpsr read-only 0x0 0x1ec - 0x1fc reserved
74 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 74 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 11.10.2 aic source mode register name: aic_smr0..aic_smr31 address: 0xfffff000 access read-write reset: 0x0 this register can only be written if the wpen bit is cleared in aic write protect mode register ? prior: priority level the priority level is programmable from 0 (lowest priority) to 7 (highest priority). the priority level is not used for the fi q in the related smr register aic_smr0. ? srctype: interrupt source type the active level or edge is not programmable for the internal interrupt sources. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 C srctype C C prior value name description 0x0 int_level_sensitive high level sensitive for internal source low level sensitive for external source 0x1 int_edge_triggered positive edge triggered for internal source negative edge triggered for external source 0x2 ext_high_level high level sensitive for internal source high level sensitive for external source 0x3 ext_positive_edge positive edge triggered for internal source positive edge triggered for external source
75 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 75 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 11.10.3 aic source vector register name: aic_svr0..aic_svr31 address: 0xfffff080 access: read-write reset: 0x0 this register can only be written if the wpen bit is cleared in aic write protect mode register ? vector: source vector the user may store in these registers the addresses of the corresponding handler for each interrupt source. 31 30 29 28 27 26 25 24 vector 23 22 21 20 19 18 17 16 vector 15 14 13 12 11 10 9 8 vector 76543210 vector
76 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 76 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 11.10.4 aic interrupt vector register name: aic_ivr address: 0xfffff100 access: read-only reset: 0x0 ? irqv: interrupt vector register the interrupt vector register contains the vector programmed by the user in the source vector register corresponding to the current interrupt. the source vector register is indexed using the current interrupt number when the interrupt vector register is read. when there is no current interrupt, the interrupt vector register reads the value stored in aic_spu. 31 30 29 28 27 26 25 24 irqv 23 22 21 20 19 18 17 16 irqv 15 14 13 12 11 10 9 8 irqv 76543210 irqv
77 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 77 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 11.10.5 aic fiq vector register name: aic_fvr address: 0xfffff104 access: read-only reset: 0x0 ? fiqv: fiq vector register the fiq vector register contains the vector programmed by the user in the source vector register 0. when there is no fast interrupt, the fiq vector register reads the value stored in aic_spu. 31 30 29 28 27 26 25 24 fiqv 23 22 21 20 19 18 17 16 fiqv 15 14 13 12 11 10 9 8 fiqv 76543210 fiqv
78 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 78 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 11.10.6 aic interrupt status register name: aic_isr address: 0xfffff108 access: read-only reset: 0x0 ? irqid: current interrupt identifier the interrupt status register returns the current interrupt source number. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCC i r q i d
79 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 79 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 11.10.7 aic interrupt pending register name: aic_ipr address: 0xfffff10c access: read-only reset: 0x0 ? fiq, sys, pid2-pid31: interrupt pending 0 = corresponding interrupt is not pending. 1 = corresponding interrupt is pending. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq
80 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 80 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 11.10.8 aic interrupt mask register name: aic_imr address: 0xfffff110 access: read-only reset: 0x0 ? fiq, sys, pid2-pid31: interrupt mask 0 = corresponding interrupt is disabled. 1 = corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq
81 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 81 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 11.10.9 aic core interrupt status register name: aic_cisr address: 0xfffff114 access: read-only reset: 0x0 ? nfiq: nfiq status 0 = nfiq line is deactivated. 1 = nfiq line is active. ? nirq: nirq status 0 = nirq line is deactivated. 1 = nirq line is active. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCn i r qn f i q
82 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 82 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 11.10.10 aic interrupt enable command register name: aic_iecr address: 0xfffff120 access: write-only ? fiq, sys, pid2-pid31: interrupt enable 0 = no effect. 1 = enables corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq
83 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 83 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 11.10.11 aic interrupt disable command register name: aic_idcr address: 0xfffff124 access: write-only ? fiq, sys, pid2-pid31: interrupt disable 0 = no effect. 1 = disables corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq
84 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 84 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 11.10.12 aic interrupt clear command register name: aic_iccr address: 0xfffff128 access: write-only ? fiq, sys, pid2-pid31: interrupt clear 0 = no effect. 1 = clears corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq
85 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 85 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 11.10.13 aic interrupt set command register name: aic_iscr address: 0xfffff12c access: write-only ? fiq, sys, pid2-pid31: interrupt set 0 = no effect. 1 = sets corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq
86 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 86 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 11.10.14 aic end of interrupt command register name: aic_eoicr address: 0xfffff130 access: write-only the end of interrupt command register is used by the interrupt routine to indicate that the interrupt treatment is complete. any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt treatment. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCCC
87 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 87 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 11.10.15 aic spurious interrupt vector register name: aic_spu address: 0xfffff134 access: read-write reset: 0x0 this register can only be written if the wpen bit is cleared in aic write protect mode register ? sivr: spurious interrupt vector register the user may store the address of a spurious interrupt handler in this register. the written value is returned in aic_ivr in case of a spurious interrupt and in aic_fvr in case of a spurious fast interrupt. 31 30 29 28 27 26 25 24 sivr 23 22 21 20 19 18 17 16 sivr 15 14 13 12 11 10 9 8 sivr 76543210 sivr
88 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 88 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 11.10.16 aic debug control register name: aic_dcr address: 0xfffff138 access: read-write reset: 0x0 this register can only be written if the wpen bit is cleared in aic write protect mode register ? prot: protection mode 0 = the protection mode is disabled. 1 = the protection mode is enabled. ? gmsk: general mask 0 = the nirq and nfiq lines are normally controlled by the aic. 1 = the nirq and nfiq lines are tied to their inactive state. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCg m s kp r o t
89 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 89 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 11.10.17 aic fast forcing enable register name: aic_ffer address: 0xfffff140 access: write-only ? sys, pid2-pid31: fast forcing enable 0 = no effect. 1 = enables the fast forcing feature on the corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys C
90 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 90 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 11.10.18 aic fast forcing disable register name: aic_ffdr address: 0xfffff144 access: write-only ? sys, pid2-pid31: fast forcing disable 0 = no effect. 1 = disables the fast forcing feature on the corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys C
91 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 91 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 11.10.19 aic fast forcing status register name: aic_ffsr address: 0xfffff148 access: read-only ? sys, pid2-pid31: fast forcing status 0 = the fast forcing feature is disabled on the corresponding interrupt. 1 = the fast forcing feature is enabled on the corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys C
92 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 92 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 11.10.20 aic write protect mode register name: aic_wpmr address: 0xfffff1e4 access: read-write reset: see table 11-3 ? wpen: write protect enable 0 = disables the write protect if wpkey co rresponds to 0x414943 ("aic" in ascii). 1 = enables the write protect if wpkey corresponds to 0x414943 ("aic" in ascii). protects the registers: ? aic source mode register on page 74 ? aic source vector register on page 75 ? aic spurious interrupt vector register on page 87 ? aic debug control register on page 88 ? wpkey: write protect key should be written at value 0x414943 ("aic" in ascii). writing any other value in this field aborts the write operation of the wpen bit. always reads as 0. 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 w p e n
93 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 93 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 11.10.21 aic write protect status register name: aic_wpsr address: 0xfffff1e8 access: read-only reset: see table 11-3 ? wpvs: write protect violation status 0 = no write protect violation has occurred since the last read of the aic_wpsr register. 1 = a write protect violation has occurred since the last read of the aic_wpsr register. if this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field wpvsrc. ? wpvsrc: write protect violation source when wpvs is active, this field indicates the write-protected register (t hrough address offset or code) in which a write access has been attempted. note: reading aic_wpsr automatically clears all fields. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 wpvsrc 15 14 13 12 11 10 9 8 wpvsrc 76543210 w p v s
94 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 94 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12
95 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 12. boot strategies 12.1 12.1 sam9cn12 only the sam9cn12 embeds a secure boot allowing firmware stored in external non-volatile mem- ory to be protected. the content of the external nvm is encrypted and signed base d using a 256-bit aes algorithm. prior to booting from the externally stored firmware, the secure boot will authenticate the firm- ware, decrypt it and store it in on-chip memory. access to the on-chip memory is prevented and the maximum size of the firmware should not exceed 24 kb. the programming of the external memory can only be done by the sam9cn12 using a unique key stored in the on-chip otp memory. herewith the software is uniquely linked to each sam9cn12 device. a direct copy of the nvm memory will not run on another sam9cn12 devic e, improving the firmware protection even further. for software development the user should use the SAM9CN11 without secure boot and full access to on-chip memory for debug. once the firmware development has been completed, the SAM9CN11 should be replaced by the sam9cn12 and programmed via usb with secure sam- ba. refer to the secured application note "secure boot on sam9cn12" for more details (nda required). 12.2 12.2 SAM9CN11 and sam9n12 only the system always boots at address 0x0. to ensure maximum boot possibilities, the memory layout can be changed thanks to the bms pin. this allows the user to layout the rom or an external memory to 0x0. the sampling of the bms pin is done at reset. if bms is detected at 0 , the controller boots on the memory connected to chip select 0 of the external bus interface. in this boot mode, the chip starts with its default parameters (all registers in their reset state), including as follows: ? the main clock is the on-chip 12 mhz rc oscillator ? the static memory controller is configured with its default parameters the user software in the external memory performs a complete configuration: ? enable the 32,768 hz oscillator if best accuracy is needed ? program the pmc (main oscilla tor enable or bypass mode) ? program and start the pll ? reprogram the smc setup, cycle, hold, mode timi ng registers for ebi cs0, to adapt them to the new clock ? switch the system clock to the new value if bms is detected at 1 , the boot memory is the embedded rom and the boot program described below is executed. ( section 12.2.1 rom code )
96 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 12.2.1 rom code the rom code is a boot program contained in the embedded rom. it is also called first level bootloader. the rom code performs several steps: ? basic chip initialization: xtal or external clock frequency detection ? attempt to retrieve a valid code from external non-volatile memories (nvm) ? execution of a monitor called sam-ba ? monitor, in case no valid application has been found on any nvm 12.2.2 flow diagram the rom code implements the algorithm shown below in figure 12-1 . figure 12-1. rom code algorithm flow diagram 12.2.3 chip setup at boot start-up, the processor clock (pck) and the master clock (mck) source is the 12 mhz fast rc oscillator. initialization follows the steps described below: 1. stack setup for arm supervisor mode. 2. main oscillator detection: the main clock is switched to the 32 khz rc oscillator to allow external clock frequency to be measur ed. then the main osc illator is enabled and set in bypass mode. if the moscsels bit rises, an external clock is connected, and the next step is main clock selection (3) . if not, the bypass mode is cleared to attempt external quartz detection. this detection is successful when the moscxts and moscsels bits rise, else the 12 mhz fast rc internal oscillator is used as the main clock. 3. main clock selection : the master clock source is switched from the slow clock to the main oscillator without prescaler. the pmc status regist er is polled to wait for mck ready. pck and mck are now the main clock. 4. c variable initialization: non zero-initialized data is in itialized in the ram (copy from rom to ram). zero-initialized data is set to 0 in the ram. sam-ba monitor copy and run it in internal sram ye s chip setup valid boot code found in one nvm no
97 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 5. plla initialization : plla is configured to get a pck at 48 mhz and an mck at 48 mhz. if an external clock or crystal frequency running at 12 mhz is found, then the plla is configured to allow communicatio n on the usb link for the sam-ba monitor; else the main clock is swit ched to the internal 12 mhz fast rc, but usb will not be activated. providing a clock frequency not at 12 mhz but between 4 and 28 mhz will be considered by the rom code as 12 mhz, and pll settings will be configured accordingly. 12.2.4 nvm boot 12.2.4.1 nvm boot sequence the boot sequence on external memory devices can be controlled using the boot sequence register (bscr). the 3 lsbs of the bscr are available to control the sequence. the user can then choose to bypass some steps shown in figure 12-2 nvm bootloader sequence diagram according to the bscr value. table 12-1. external clock and crystal frequencies allowed for boot sequence (in mhz) 41 2 28 boot on external memories yes yes yes sam-ba monitor through dbgu yes yes yes sam-ba monitor through usb no yes no table 12-2. boot sequence register values bscr value spi0 npcs0 sdcard nand flash spi0 npcs1 twi eeprom sam-ba monitor 0yyyy yy 1y-yy yy 2y--y yy 3y--y yy 4y--- yy 5---- -y 6---- -y 7---- -y
98 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 12-2. nvm bootloader sequence diagram spi0 cs0 flash boot spi0 cs1 flash boot ye s ye s t wi eeprom bo o t ye s nand flash boot co p y f r o m nand flash t o sram ru n ye s nand flash boot loader no sd card boot co p y f r o m sd ca r d t o sra m ru n ye s sd card bootloader no device se t u p no no sa m - ba monitor co p y f r o m spi fl a sh t o sra m co p y f r o m spi fl a sh t o sra m spi flash boot loader spi flash boot loader ru n ru n no co p y f r o m t wi eeprom t o sra m twi eeprom boot loade r ru n
99 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 12.2.4.2 nvm bootloader program description figure 12-3. nvm bootloader program diagram the nvm bootloader program first in itializes the pios related to th e nvm device. then it config- ures the right peripheral depending on the nvm and tries to access this memory. if the initialization fails, it restores the reset values for the pio and the peripheral and then tries the same operations on the next nvm of the sequence. if the initialization is successful, the nvm bootloader program reads the beginning of the nvm and determines if the nvm contains valid code. if the nvm does not contain valid code, the nvm bootloader program restores the reset value for the peripherals and then tries the same operations on the next nvm of the sequence. en d valid code detection in nvm ye s copy the valid code from external nvm to internal sram. rest ore t he reset values for t he peripherals. perform the remap and set the pc to 0 to jump to the downloaded application initialize nvm nvm cont ains valid code ye s st a r t initialization ok ? rest ore t he reset values for the peripherals and jump to next boot solution no no
100 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 if valid code is found, this code is loaded from nvm into internal sram and executed by branch- ing at address 0x0000_0000 after remap. this code may be the application code or a second- level bootloader. all the calls to functions are pc relative and do not use absolute addresses. figure 12-4. remap action after download completion 12.2.4.3 valid code detection there are two kinds of valid code detection. arm exception vectors check the nvm bootloader program reads and analyzes the first 28 bytes corresponding to the first seven arm exception vectors. except for the si xth vector, these bytes must implement the arm instructions for either branch or load pc with pc relative addressing. figure 12-5. ldr opcode figure 12-6. b opcode unconditional instruction: 0xe for bits 31 to 28 load pc with pc relative addressing instruction: C rn = rd = pc = 0xf C i==0 (12-bit immediate value) C p==1 (pre-indexed) C u offset added (u==1) or subtracted (u==0) Cw==1 remap internal rom internal rom 0x0010_0000 0x0000_0000 internal sram 0x0030_0000 internal sram internal rom 0x0010_0000 0x0000_0000 internal sram 0x0030_0000 31 28 27 24 23 20 19 16 15 12 11 0 111001 i pu1w0 rn rd oset 31 28 27 24 23 0 11101010 oset (24 bits)
101 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 the sixth vector, at offset 0x14, contains the size of the image to download. the user must replace this vector with the users own vector. this information is described below. figure 12-7. structure of the arm vector 6 the value has to be smaller than 24 kbytes. this size is the internal sram size minus the stack size used by the rom code at the end of the internal sram. example an example of valid vectors follows: 00 ea000006 b 0x20 04 eafffffe b 0x04 08 ea00002f b _main 0c eafffffe b 0x0c 10 eafffffe b 0x10 14 00001234 b 0x14 <- code size = 4660 bytes 18 eafffffe b 0x18 boot.bin file check this method is the one used on fat formatted sdcard. the boot program must be a file named boot.bin written in the root directory of the file system. its size must not exceed the maxi- mum size allowed: 24 kbytes (0x6000). 12.2.4.4 detailed memory boot procedures nand flash boot: nand flash detection after nand flash interface configuration, a reset command is sent to the memory. the boot program first tries to find valid software on a nand flash device connected to ebi cs3, with data lines connected to d0-d7, then on nand flash connected to d16-d23. hardware ecc detection and correction are provided by the pmecc peripheral (refer to the pmecc section in the datasheet for more information). the boot program is able to retrieve nand flash parameters and ecc requirements using two methods as follows: ? the detection of a specific header written at the beginning of the first page of nand flash, or ? through the onfi parameters for onfi compliant memories. 31 0 size of t he code t o download in byt es
102 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 12-8. boot nand flash download end no no copy the v alid code from extern a l nvm to internal sram. read nand flash and pmecc par ameters from the header read nand fl ash and pmecc par ameters from the onfi restore the reset v alues for the peripher als . perform the remap and set the pc to 0 to ju mp to the downloaded application initia lize nand flash interf ace send reset command first page contains v alid header nand fl ash is onfi compliant start restore the reset v alues for the peripher als and j u mp to next bootab le memory ye s ye s
103 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 nand flash specific header detection this is the first method used to determine nand flash parameters. after initialization and reset command, the boot program reads the first page without ecc check, to determine if the nand parameter header is present. the header is made of 52 times the same 32-bit word (for redun- dancy reasons) which must contain nand and pmecc parameters used to correctly perform the read of the rest of the data in the nand. this 32-bit word is described below: ? usepmecc: use pmecc 0 = do not use pmecc to detect and correct the data. 1 = use pmecc to detect and correct the data. ? nbsectorperpage: number of sectors per page ? sparesize: size of the spare zone in bytes ? eccbitreq: number of ecc bits required ? sectorsize: size of the ecc sector 0 = for 512 bytes. 1 = for 1024 bytes per sector. other value for future use. ? eccoffset: offset of the first ecc byte in the spare zone a value below 2 is not allo wed and will be considered as 2. ? key: value 0xc must be written here to validate the content of the whole word. if the header is valid, the boot program will continue with the detection of valid code. 31 30 29 28 27 26 25 24 key - eccoffset 23 22 21 20 19 18 17 16 eccoffset sectorsize 15 14 13 12 11 10 9 8 eccbitreq sparesize 76543210 sparesize nbsectorperpage usepmecc
104 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 onfi 2.2 parameters in case no valid header has b een found, the boot program will check if the nand flash is onfi compliant, sending a read id command (0x90) with 0x20 as parameter for the address. if the nand flash is onfi compliant, the boot program retrieves the following parameters with the help of the get parameter page command: ? number of bytes per page (byte 80) ? number of bytes in spare zone (byte 84) ? number of ecc bit correction required (byte 112) ? ecc sector size: by default set to 512 bytes, or 1024 bytes if the ecc bit capability above is 0xff by default, onfi nand flash det ection will turn on the usepmecc parameter, and ecc correc- tion algorithm is automatically activated. once the boot program retrieves the parameter, using one of the two methods described above, it will read the first page again, with or without ecc, depending on the usepmecc parameter. then it looks for a valid code programmed just after the header offset 0xd0. if the code is valid, the program is copied at the beginning of the internal sram. note: booting on 16-bit nand flash is not possible, only 8-bit nand flash memories are supported. nand flash boot: pmecc error detection and correction nand flash boot procedure uses pmecc to det ect and correct errors during nand flash read operations in two cases: ? when the usepmecc flag is set in the specific nand header. if the flag is not set, no ecc correction is performed during nand flash page read. ? when the nand flash has been detected using onfi parameters. the rom code embeds the software used in the process of ecc detection/correction: the galois field tables, and the function pmecc_correctionalgo(). the user does not need to embed it in other software. this function can be called by user software when pmecc status returns errors after a read page command. its address can be retrieved by reading the third vector of the rom code interrupt vector table, at address 0x100008. the api of this function is: unsigned int pmecc_correctionalgo(at91ps_pmecc ppmecc, at91ps_pmerrloc ppmerrloc, pmecc_paramdesc_struct *pmecc_desc, unsigned int pmecc_status, unsigned int pagebuffer) ppmecc: pointer to the pmecc base address, ppmerrloc: pointer to the pmerrloc base address, pmecc_desc: pointer to the pmecc descriptor, pmecc_status: the status returned by the read of pmeccisr register;
105 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 pagebuffer: address of the buffer containing the page to be corrected. the pmecc descriptor structure is: typedef struct _pmecc_paramdesc_struct { unsigned int pagesize; unsigned int sparesize; unsigned int sectorsize; // 0 for 512, 1 for 1024 bytes unsigned int errbitnbrcapability; unsigned int eccsizebyte; unsigned int eccstartaddr; unsigned int eccendaddr; unsigned int nandwr; unsigned int spareena; unsigned int modeauto; unsigned int clkctrl; unsigned int interrupt; int tt; int mm; int nn; short *alpha_to; short *index_of; short partialsyn[100]; short si[100]; /* sigma table */ short smu[tt_max + 2][2 * tt_max + 1]; /* polynom order */ short lmu[tt_max + 1]; } pmecc_paramdesc_struct;
106 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 the galois field tables are mapped in the rom just after the rom code, as described in figure 12-9 below: figure 12-9. galois field table mapping for a full description and an example of how to use the pmecc detection and correction fea- ture, refer to the software package dedicated to this device on atmels web site. sd card boot the sd card bootloader uses mci0. it looks for a boot.bin file in the root directory of a fat12/16/32 formatted sd card. supported sd card devices sd card boot supports all sd card memories compliant with sd memo ry card specification v2.0. this includes sdhc cards. spi flash boot two kinds of spi flash are supported: spi serial flash and spi dataflash ? . the spi flash bootloader tries to boot on spi0 chip select 0, first looking for spi serial flash, and then for spi dataflash. it uses only one valid code detection: analysis of arm exception vectors. the spi flash read is done by means of a continuous read command from address 0x0. this command is 0xe8 for dataflash an d 0x0b for serial flash devices. rom code 0x0010_8000 0x0010_0000 galois field tables for 1024-byte sectors correction galois field tables for 512-byte sectors correction 0x0011_0000
107 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 supported dataflash devices the spi flash boot program supports all atmel dataflash devices. supported serial flash devices the spi flash boot program supports all spi se rial flash devices res ponding correctly at both get status and continuous read commands. twi eeprom boot the twi eeprom bootloader uses the twi0. it uses only one valid code detection. it analyzes the arm exception vectors. supported twi eeprom devices twi eeprom boot supports all i 2 c-compatible twi eeprom memories using 7-bit device address 0x50. 12.2.4.5 hardware and software constraints the nvm drivers use several pios in peripheral mode to communicate with external memory devices. care must be taken when these pios are used by the application. the devices con- nected could be unintentionally driven at boot time, and electrical conflicts between output pins used by the nvm drivers and th e connected devices may occur. to assure correct functionality, it is recommended to plug in critical devices to other pins not used by nvm. table 12-4 contains a list of pins that are driven during the boot program execution. these pins are driven during the boot sequence for a period of less than 1 second if no correct boot program is found. table 12-3. dataflash device device density page size (bytes) number of pages at45db011 1 mbit 264 512 at45db021 2 mbits 264 1024 at45db041 4 mbits 264 2048 at45db081 8 mbits 264 4096 at45db161 16 mbits 528 4096 at45db321 32 mbits 528 8192 at45db642 64 mbits 1056 8192
108 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 before performing the jump to the application in internal sram, all the pios and peripherals used in the boot program are set to their reset state. 12.2.5 sam-ba monitor if no valid code has been found in nvm during the nvm bootloader sequence, the sam-ba monitor program is launched. the sam-ba monitor principle is to: C initialize dbgu and usb C check if usb device enumeration has occurred C check if characters have been received on the dbgu once the communication interface is identified, the application runs in an in finite loop waiting for different commands as listed in table 12-5 . table 12-4. pio driven during boot program execution nvm bootloader peri pheral pin pio line nand ebi cs3 smc nandoe piod0 ebi cs3 smc nandwe piod1 ebi cs3 smc nandcs piod4 ebi cs3 smc nand ale a21 ebi cs3 smc nand cle a22 ebi cs3 smc cmd/addr/data d[16:0] sd card mci0 mci0_ck pioa17 mci0 mci0_d0 pioa15 mci0 mci0_d1 pioa18 mci0 mci0_d2 pioa19 mci0 mci0_d3 pioa20 spi flash spi0 mosi pioa10 spi0 miso pioa11 spi0 spck pioa13 spi0 npcs0 pioa14 spi0 npcs1 pioa7 twi0 eeprom twi0 twd0 pioa30 twi0 twck0 pioa31 sam-ba monitor dbgu drxd pioa9 dbgu dtxd pioa10
109 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 12-10. sam-ba monitor diagram 12.2.5.1 command list ? mode commands: C normal mode configures sam-ba monitor to send / receive data in binary format, C terminal mode configures sam-ba monitor to send / receive data in ascii format. ? write commands: write a byte ( o ), a halfword ( h ) or a word ( w ) to the target. C address : address in hexadecimal. C value : byte, halfword or word to write in hexadecimal. C output : > ? read commands: read a byte ( o ), a halfword ( h ) or a word ( w ) from the target. character(s) received on dbgu ? run monitor wait for command on the usb link run monitor wait for command on the dbgu link usb enumeration successful ? ye s ye s no no init dbgu and usb no valid code in nvm table 12-5. commands available through the sam-ba monitor command action argument(s) example n set normal mode no argument n # t set terminal mode no argument t # o write a byte address, value# o 200001,ca# o read a byte address,# o 200001,# h write a half word address, value# h 200002,cafe# h read a half word address,# h 200002,# w write a word address, value# w 200000,cafedeca# w read a word address,# w 200000,# s send a file address,# s 200000,# r receive a file address, nbofbytes# r 200000,1234# g go address# g 200200# v display version no argument v #
110 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 C address : address in hexadecimal. C output : the byte, halfword or word read in hexadecimal followed by > ? send a file ( s ): send a file to a specified address. C address : address in hexadecimal. C output : > note: there is a time-out on this command which is reached when the prompt > appears before the end of the command execution. ? receive a file ( r ): receive data into a file from a specified address C address : address in hexadecimal. C nbofbytes : number of bytes in hexadecimal to receive. C output : > ?go ( g ): jump to a specified address and execute the code. C address : address to jump in hexadecimal. C output : >once returned from the program execution. if the executed program does not handle the link register at its entry and does not re turn, the prompt will not be displayed. ? get version ( v ): return the boot program version. C output : version, date and time of rom code followed by >. 12.2.5.2 dbgu serial port communication is performed through the dbgu serial port initialized to 115,200 baud, 8 bits of data, no parity, 1 stop bit. supported external crystal/external clocks the sam-ba monitor supports a frequency of 12 mhz to allow dbgu communication for both external crystal and external clock. xmodem protocol the send and receive file commands use the xmodem protocol to communicate. any terminal performing this protocol can be used to send th e application file to the target. the size of the binary file to send depends on the sram size embedded in the product. in all cases, the size of the binary file must be lower than the sram si ze because the xmodem protocol requires some sram memory in order to work. the xmodem protocol supported is the 128-byte l ength block. this protocol uses a two-charac- ter crc16 to guarantee detection of a maximum bit error. xmodem protocol with crc is accurate provided both sender and receiver report successful transmission. each block of the transfer looks like: <255-blk #><--128 da ta bytes--> in which: C = 01 hex C = binary number, starts at 01, increments by 1, and wraps 0ffh to 00h (not to 01) C <255-blk #> = 1s complement of the blk#. C = 2 bytes crc16 figure 12-11 shows a transmission using this protocol.
111 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 12-11. xmodem transfer example 12.2.5.3 usb device port supported external crystal / external clocks the frequencies supported by sam-ba monitor to allow usb communication are 4, 8, 12 or 16 mhz crystal or external clock. usb class the device uses the usb communication device class (cdc) drivers to take advantage of the installed pc rs-232 software to talk over the usb. the cdc class is implemented in all releases of windows ? , from windows 98se ? to windows xp ? . the cdc document, available at www.usb.org , describes how to implement devices su ch as isdn modems and virtual com ports. the vendor id is atmels vendor id 0x03eb. the product id is 0x6124. these references are used by the host operating system to mount the correct driver. on windows systems, the inf files contain the correspondence between vendor id and product id. enumeration process the usb protocol is a master/slave protocol. the host starts the enumeration, sending requests to the device through the control endpoint. the device handles standard requests as defined in the usb specification. host device soh 01 fe data[128] crc crc c ack soh 02 fd data[128] crc crc ack soh 03 fc data[100] crc crc ack eot ack table 12-6. handled standard requests request definition get_descriptor returns the current device configuration value. set_address sets the device address for all future device access. set_configuration sets the device configuration. get_configuration returns the curr ent device configuration value.
112 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 the device also handles some class requests defined in the cdc class. unhandled requests are stalled. communication endpoints there are two communication endpoints and endpoint 0 is used for the enumeration process. endpoint 1 is a 64-byte bulk out endpoint and endpoint 2 is a 64-byte bulk in endpoint. sam- ba boot commands are sent by the host through endpoint 1. if required, the message is split by the host into several data payloads by the host driver. if the command requires a response, the host can send in transactions to pick up the response. get_status returns status for the specified recipient. set_feature used to set or enable a specific feature. clear_feature used to clear or disable a specific feature. table 12-7. handled class requests request definition set_line_coding configures dte rate, stop bits, parity and number of character bits. get_line_coding requests current dte rate, stop bits, parity and number of character bits. set_control_line_state rs-232 signal used to tell the dte device is now present. table 12-6. handled standard requests (continued) request definition
113 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 113 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 13. boot sequence controller (bsc) 13.1 description the system controller embeds a boot sequence configuration register to save timeout delays on boot. the boot sequence is programmable through the boot sequence configuration regis- ter (bscr). this register is powered by vddbu, the modification is saved and applied after the next reset. the register is taking factory va lue in case of battery removing. this register is programmable with user programs or sam-ba and key-protected. 13.2 embedded characteristics ? vddbu powered register 13.3 product dependencies ? product-dependent order 13.4 boot sequence controller (bsc) user interface table 13-1. register mapping offset register name access reset 0x0 boot sequence configuration register bsc_cr read-write C
114 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 114 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 13.4.1 boot sequence configuration register name: bsc_cr address: 0xfffffd54 access: read-write factory value: 0x0000_0000 ? boot: boot media sequence this value is defined in the product-dep endent rom code. it is only written if bootkey carries the valid value. ?bootkey 0x6683 (bsc_key): valid key to write bsc_cr register; it needs to be written at the same time as the boot field. other values disable the write acce ss. this key field is write-only. 31 30 29 28 27 26 25 24 bootkey 23 22 21 20 19 18 17 16 bootkey 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 boot
115 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 14. reset controller (rstc) 14.1 description the reset controller (rstc), based on power-on reset cells, handles all the resets of the sys- tem without any external components. it reports which reset occurred last. the reset controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 14.2 embedded characteristics ? manages all resets of the system, including C external devices through the nrst pin C processor reset C peripheral set reset C backed-up peripheral reset ? based on 2 embedded power-on reset cells ? reset source status C status of the last reset C either general reset, wake-up reset, software reset, user reset, watchdog reset ? external reset signal shaping ?amba ? -compliant interface C interfaces to the arm ? advanced peripheral bus 14.3 block diagram figure 14-1. reset controller block diagram nrst startup counter proc_nreset wd_fault periph_nreset backup_neset slck reset state manager reset controller rstc_irq nrst manager exter_nreset nrst_out main supply por wdrproc user_reset backup supply por
116 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 14.4 functional description 14.4.1 reset controller overview the reset controller is made up of an nrst manager, a startup counter and a reset state manager. it runs at slow clock and generates the following reset signals: ? proc_nreset: processor reset line. it also resets the watchdog timer. ? backup_nreset: affects all the peripherals powered by vddbu. ? periph_nreset: affects the whole set of embedded peripherals. ? nrst_out: drives the nrst pin. these reset signals are asserted by the reset controller, either on external events or on soft- ware action. the reset state manager controls the generation of reset signals and provides a signal to the nrst manager when an assertion of the nrst pin is required. the nrst manager shapes the nrst assertion during a programmable ti me, thus controlling external device resets. the startup counter waits for the complete crystal oscillator startu p. the wait de lay is given by the crystal oscillator startup time maximum value that can be foun d in the section crystal oscil- lator characteristics in the electrical characteristics section of the product documentation. the reset controller mode register (rstc_mr), allowing the configuration of the reset con- troller, is powered with vddbu, so that its configuration is saved as long as vddbu is on. 14.4.2 nrst manager after power-up, nrst is an output during the erstl time defined in the rstc. when erstl elapsed, the pin behaves as an input and all the system is held in reset if nrst is tied to gnd by an external signal. the nrst manager samples the nrst input pin and drives this pin low when required by the reset state manager. figure 14-2 shows the block diagram of the nrst manager. figure 14-2. nrst manager nrst signal the nrst manager handles the nrst input line asynchronously. when the line is low, a user reset is immediately reported to the reset state manager. when the nrst goes from low to high, the internal reset is synchroniz ed with the slow clock to provide a safe internal de-assertion of reset. ex t e r n a l re se t ti m e r ursts erstl ext er_nreset rstc_ m r rstc_ sr nrstl nrst_out nrst user_reset
117 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 the level of the pin nrst can be read at any ti me in the bit nrstl (nrst level) in rstc_sr. as soon as the pin nrst is asserted, the bit ur sts in rstc_sr is set. this bit clears only when rstc_sr is read. 14.4.2.1 nrst external reset control the reset state manager asserts the signal ext_nreset to assert the nrst pin. when this occurs, the nrst_out signal is driven low by the nrst manager for a time programmed by the field erstl in rstc_mr. this assertion duration, named externa l_reset_length, lasts 2 (erstl+1) slow clock cycles. this gives the approximate duration of an assertion between 60 s and 2 seconds. note that erstl at 0 defines a two-cycle duration for the nrst pulse. this feature allows the reset controller to shape the nrst pin level, and thus to guarantee that the nrst line is driven low for a time compliant with potential external devices connected on the system reset. as the field is within rstc_mr, which is backed -up, this field can be used to shape the system power-up reset for devi ces requiring a longer startup time than the slow clock oscillator. 14.4.3 bms sampling the product matrix manages a boot memory that depends on the level on the bms pin at reset. the bms signal is sampled three slow clock cycl es after the core power-on-reset output rising edge. figure 14-3. bms sampling 14.4.4 reset states the reset state manager handles the different reset sources and generates the internal reset signals. it reports the reset status in the field rsttyp of the status register (rstc_sr). the update of the field rsttyp is performed when the processor reset is released. 14.4.4.1 general reset a general reset occurs when vddbu and vddcore are powered on. the backup supply por cell output rises and is filtered with a startup counter, which operates at slow clock. the pur- pose of this counter is to make sure the slow clock oscillator is stable before starting up the device. the length of startup ti me is hardcoded to comply with the slow clock oscillator startup time. slck core supply por output bms sampling delay = 3 cycles bms signal proc_nreset xxx h or l
118 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 after this time, the processor clock is released at slow clock and all the other signals remain valid for 3 cycles for proper processor and logic reset. then, all the reset signals are released and the field rsttyp in rstc_sr reports a general reset. as the rstc_mr is reset, the nrst line rises 2 cycles after the backup_nreset, as erstl defaults at value 0x0. when vddbu is detected low by the backup suppl y por cell, all resets signals are immedi- ately asserted, even if the main supply por cell does not report a main supply shutdown. vddbu only activates the backup_nreset signal. the backup_nreset must be released so that any other reset can be generated by vddcore (main supply por output). figure 14-4 shows how the general reset affects the reset signals. figure 14-4. general reset state 14.4.4.2 wake-up reset the wake-up reset occurs when the main supply is down. when the main supply por output is active, all the reset signals are asserted except backup_nreset. when the main supply pow- ers up, the por output is resynchronized on slow clock. the processor clock is then re-enabled during 3 slow clock cycles, depending on the requirements of the arm processor. at the end of this delay, the processor and other reset signals rise. the field rsttyp in rstc_sr is updated to report a wake-up reset. the nrst_out remains asserted for ext ernal_reset_length cycles. as rstc_mr is backed-up, the programmed number of cycles is applicable. slck periph_nreset proc_nreset backup supply por output nrst (nrst_out) external reset length = 2 cycles startup time mck processor startup backup_nreset any freq. rsttyp xxx 0x0 = general reset xxx main supply por output bms sampling
119 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 14-5. when the main supply is detected fa lling, the reset signals are immediatel y asserted. this transition is syn- chronous with the output of the main supply por.wake-up reset 14.4.4.3 user reset the user reset is entered when a low level is detected on the nrst pin when a falling edge occurs on nrst (reset activation), internal reset lines are immediately asserted. the processor reset and the peripheral reset are asserted. the user reset is left when nrst rises, after a two-cycle resynchronization time and a 3-cycle processor startup. the processor clock is re-enabled as soon as nrst is confirmed high. when the processor reset signal is released, the rsttyp field of the status register (rstc_sr) is loaded with the value 0x4, indicating a user reset. the nrst manager guarantees that the nrst line is asserted for external_reset_length slow clock cycles, as programmed in the field erstl. how- ever, if nrst does not rise after extern al_reset_length because it is driven low externally, the internal reset lines remain asserted until nrst actually rises. slck periph_nre set proc_nreset main supply por output nrst (nrst_out) external reset length = 4 cycles (erstl = 1) mck processor start up back up_nreset any fre q. resynch. 2 cycles rsttyp xxx 0x1 = w a keup reset xxx
120 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 14-6. user reset state 14.4.4.4 software reset the reset controller offers several commands used to assert the different reset signals. these commands are performed by writing the control register (rstc_cr) with the following bits at 1: ? procrst: writing procrst at 1 resets the processor and the watchdog timer. ? perrst: writing perrst at 1 resets all the embedded peripherals, including the memory system, and, in particular, the remap command. the peripheral reset is generally used for debug purposes. except for debug purposes, perrst must always be used in conjunction with procrst (perrst and procrst set both at 1 simultaneously.) ? extrst: writing extrst at 1 asserts low the nrst pin during a time defined by the field erstl in the mode register (rstc_mr). the software reset is entered if at least one of these bits is set by the software. all these com- mands can be performed independently or simultaneously. the software reset lasts 3 slow clock cycles. the internal reset signals are asserted as soon as the register write is performed. this is detected on the master clock (mck). they are released when the software reset is left, i.e.; syn- chronously to slck. if extrst is set, the nrst_out signal is asserted depending on the programming of the field erstl. however, the result ing falling edge on nrst does not lead to a user reset. if and only if the procrst bit is set, the reset controller reports the software status in the field rsttyp of the status register (rstc_sr). other software resets are not reported in rsttyp. slck periph_nreset proc_nreset nrst nrst (nrst_out) >= external reset length mck processor startup any freq. rsttyp any xxx resynch. 2 cycles 0x4 = user reset
121 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 as soon as a software operation is detected, the bit srcmp (software reset command in prog- ress) is set in the status register (rstc_sr). it is cleared as soon as the software reset is left. no other software reset can be performed while the srcmp bit is set, and writing any value in rstc_cr has no effect. figure 14-7. software reset 14.4.4.5 watchdog reset the watchdog reset is entered when a watchdog fault occurs. this state lasts 3 slow clock cycles. when in watchdog reset, assertion of t he reset signals depends on the wdrproc bit in wdt_mr: ? if wdrproc is 0, the processor reset and the peripheral reset are asserted. the nrst line is also asserted, depending on the programming of the field erstl. however, the resulting low level on nrst does not result in a user reset state. ? if wdrproc = 1, only the processor reset is asserted. the watchdog timer is reset by the proc_nreset si gnal. as the watchdog fault always causes a processor reset if wdrsten is set, the watc hdog timer is always reset after a watchdog reset and the watchdog is enabled by default and with a period set to a maximum. when the wdrsten in wdt_mr bit is reset, the watchdog fault has no impact on the reset controller. slck periph_nreset if perrst=1 proc_nreset if procrst=1 write rstc_cr nrst (nrst_out) if extrst=1 external reset length 8 cycles (erstl=2) mck processor startup = 3 cycles any freq. rsttyp any xxx 0x3 = software reset resynch. 1 to 2 cycles srcmp in rstc_sr
122 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 14-8. watchdog reset 14.4.5 reset state priorities the reset state manager manages the following priorities between the different reset sources, given in descending order: ? backup reset ? wake-up reset ? user reset ? watchdog reset ? software reset particular cases are listed below: ? when in user reset: C a watchdog event is impossible because the watchdog timer is being reset by the proc_nreset signal. C a software reset is impossible, since the processor reset is being activated. ? when in software reset: C a watchdog event has priority over the current state. C the nrst has no effect. ? when in watchdog reset: C the processor reset is active and so a software reset cannot be programmed. C a user reset cannot be entered. 14.4.6 reset controller status register the reset controller status register (rstc_sr) provides several status fields: ? rsttyp field: this field gives the type of the last reset, as explained in previous sections. only if wdrproc = 0 slck periph_nreset proc_nreset wd_fault nrst (nrst_out) external reset length 8 cycles (erstl=2) mck processor startup = 3 cycles any freq. rsttyp any xxx 0x2 = watchdog reset
123 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? srcmp bit: this field indicates that a software reset command is in progress and that no further software reset should be performed until the end of the current one. this bit is automatically cleared at the end of the current software reset. ? nrstl bit: the nrstl bit of the status register gives the level of the nrst pin sampled on each mck rising edge. ? ursts bit: a high-to-low transition of the nrst pin sets the ursts bit of the rstc_sr register. this transition is also detected on the master clock (mck) rising edge (see figure 14-9 ). reading the rstc_sr status register resets the ursts bit. figure 14-9. reset controller status and interrupt mck nrst nrstl 2 cycle resynchronization 2 cycle resynchronization ursts read rstc_sr peripheral access rstc_irq if (ursten = 0) and (urstien = 1)
124 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 14.5 reset controller (rstc) user interface note: 1. the reset value of rstc_sr either reports a general reset or a wake-up reset depending on last rising power supply. table 14-1. register mapping offset register name access reset back-up reset 0x00 control register rstc_cr write-only - 0x04 status register rstc_sr read-only 0x0000_0001 0x0000_0000 0x08 mode register rstc_mr read-write - 0x0000_0000
125 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 14.5.1 reset controller control register name: rstc_cr address: 0xfffffe00 access: write-only ? procrst: processor reset 0 = no effect. 1 = if key is correct, resets the processor. ? perrst: peripheral reset 0 = no effect. 1 = if key is correct, resets the peripherals. ? extrst: external reset 0 = no effect. 1 = if key is correct, asserts the nrst pin. ?key: password should be written at value 0xa5. writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCC C 76543210 CCCCe x t r s tp e r r s tCp r o c r s t
126 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 14.5.2 reset controller status register name: rstc_sr address: 0xfffffe04 access: read-only ? ursts: user reset status 0 = no high-to-low edge on nrst happened since the last read of rstc_sr. 1 = at least one high-to-low transition of nrst has been detected since the last read of rstc_sr. ? rsttyp: reset type reports the cause of the last processor reset. r eading this rstc_sr does not reset this field. ? nrstl: nrst pin level registers the nrst pin level at master clock (mck). ? srcmp: software reset command in progress 0 = no software command is being performed by the reset controller. the reset controller is ready for a software command. 1 = a software reset command is being performed by the reset controller. the reset controller is busy. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCs r c m pn r s t l 15 14 13 12 11 10 9 8 CCCCC r s t t y p 76543210 CCCCCCCu r s t s rsttyp reset type comments 0 0 0 general reset both vddcore and vddbu rising 0 0 1 wake up reset vddcore rising 0 1 0 watchdog reset watchdog fault occurred 0 1 1 software reset processor re set required by the software 1 0 0 user reset nrst pin detected low
127 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 14.5.3 reset controller mode register name: rstc_mr address: 0xfffffe08 access: read-write ? erstl: external reset length this field defines the external reset length. the external reset is asserted during a time of 2 (erstl+1) slow clock cycles. this allows assertion duration to be programmed between 60 s and 2 seconds. ?key: password should be written at value 0xa5. writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCC e r s t l 76543210 CC C CCCC
128 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12
129 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 129 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 15. real time clock (rtc) 15.1 description the real-time clock (rtc) peripheral is de signed for very low power consumption. it combines a complete time-of-day clock with alarm and a two-hundred-year gregorian calen- dar, complemented by a programmable periodic interrupt. the alarm and calendar registers are accessed by a 32-bit data bus. the time and calendar values are coded in binary-coded decimal (bcd) format. the time format can be 24-hour mode or 12-hour mode with an am/pm indicator. updating time and calendar fields and configuri ng the alarm fields are performed by a parallel capture on the 32-bit data bus. an entry control is performed to avoid loading registers with incompatible bcd format data or with an incompatible date according to the current month/year/century. 15.2 embedded characteristics ? low power consumption ? full asynchronous design ? two hundred year gregorian calendar ? programmable periodic interrupt ? time, date and alarm 32-bit parallel load 15.3 block diagram figure 15-1. rtc block diagram 15.4 product dependencies 15.4.1 power management the real-time clock is cont inuously clocked at 32768 hz. the power management controller has no effect on rtc behavior. bus interface 32768 divider time slow clock: slck bus interface date rtc interrupt entry control interrupt control
130 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 130 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 15.4.2 interrupt within the system controller, th e rtc interrupt is or-wired with all the other module interrupts. only one system controller interrupt line is connected on one of the internal sources of the inter- rupt controller. rtc interrupt requires the interrupt controller to be programmed first. when a system controller interrupt occurs, the service routine must first determine the cause of the interrupt. this is done by reading each status register of the system controller peripherals successively. 15.5 functional description the rtc provides a full binary-coded decimal (b cd) clock that includes century (19/20), year (with leap years), month, date, day, hours, minutes and seconds. the valid year range is 1900 to 2099 in gregorian mode, a two-hundred-year calendar. the rtc can operate in 24-hour mode or in 12-hour mode with an am/pm indicator. corrections for leap years are included (all years di visible by 4 being leap years). this is correct up to the year 2099. 15.5.1 reference clock the reference clock is slow clock (slck). it can be driven internally or by an external 32.768 khz crystal. during low power modes of the processor, the osc illator runs and power c onsumption is critical. the crystal selection has to take into account the current consumption for power saving and the frequency drift due to temperature effect on the circuit for time accuracy. 15.5.2 timing the rtc is updated in real time at one-second intervals in normal mode for the counters of sec- onds, at one-minute intervals for the counter of minutes and so on. due to the asynchronous operation of the rtc with respect to the rest of the chip, to be certain that the value read in the rtc registers (century, year, month, date, day, hours, minutes, sec- onds) are valid and stable, it is necessary to read these registers twice. if the data is the same both times, then it is valid. therefore, a minimu m of two and a maximum of three accesses are required. 15.5.3 alarm the rtc has five programmable fields: month, date, hours, minutes and seconds. each of these fields can be enabled or disabled to match the alarm condition: ? if all the fields are enabled, an alarm flag is generated (the corresponding flag is asserted and an interrupt generated if enabled) at a given month, date, hour/minute/second. ? if only the seconds field is enabled, then an alarm is generated every minute. depending on the combination of fields enabled, a large number of possibilit ies are available to the user ranging from minutes to 365/366 days.
131 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 131 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 15.5.4 error checking verification on user interface data is performed when accessing the century, year, month, date, day, hours, minutes, seconds and alarms. a chec k is performed on illegal bcd entries such as illegal date of the month with regard to the year and century configured. if one of the time fields is not correct, the data is not loaded into the register/counter and a flag is set in the validity register. the user can not reset this flag. it is reset as soon as an acceptable value is programmed. this avoids any further si de effects in the hardware. the same procedure is done for the alarm. the following checks are performed: 1. century (check if it is in range 19 - 20) 2. year (bcd entry check) 3. date (check range 01 - 31) 4. month (check if it is in bcd range 01 - 12, check validity regarding date) 5. day (check range 1 - 7) 6. hour (bcd checks: in 24-hour mode, check range 00 - 23 and check that am/pm flag is not set if rtc is set in 24-hour mode; in 12-hour mode check range 01 - 12) 7. minute (check bcd and range 00 - 59) 8. second (check bcd and range 00 - 59) note: if the 12-hour mode is selected by means of the rtc_mode register, a 12-hour value can be pro- grammed and the returned value on rtc_time will be the corresponding 24-hour value. the entry control checks the value of the am/pm indicato r (bit 22 of rtc_time register) to determine the range to be checked. 15.5.5 updating time/calendar to update any of the time/calendar fields, the user must first stop the rtc by setting the corre- sponding field in the control register. bit updtim must be set to update time fields (hour, minute, second) and bit updcal must be set to update calendar fields (century, year, month, date, day). then the user must poll or wait for the interrupt (if enabled) of bit ackupd in the status regis- ter. once the bit reads 1, it is mandatory to clear this flag by writing the corresponding bit in rtc_sccr. the user can now write to the appropriate time and calendar register. once the update is finished, the user must reset (0) updtim and/or updcal in the control when entering programming mode of the calendar fields, the time fields remain enabled. when entering the programming mode of the time fields, both time and calendar fields are stopped. this is due to the location of the calendar logic circuity (downstream for low-power consider- ations). it is highly recommended to prepare all the fields to be updated before entering programming mode. in successive update operations, the user must wait at least one second after resetting the updtim/updcal bit in the rtc_cr (control register) before setting these bits again. this is done by waiting for the se c flag in the status register before setting updtim/updcal bit. after resetting updtim/updcal, the sec flag must also be cleared.
132 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 132 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 15-2. update sequence prepa re time or calendar fields set updtim and/or updcal bit(s ) in rtc_cr rea d rtc_sr ackupd = 1 ? clea r ackupd b it in rtc_sccr update time and/or calendar v alues in rtc_timr/rtc_calr clear updtim and/or updcal bit in rtc_cr no ye s begin end polling or irq (if enab led)
133 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 133 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 15.6 real time clock (r tc) user interface note: if an offset is not listed in the table it must be considered as reserved. table 15-1. register mapping offset register name access reset 0x00 control register rtc_cr read-write 0x0 0x04 mode register rtc_mr read-write 0x0 0x08 time register rtc_timr read-write 0x0 0x0c calendar register rtc_calr read-write 0x01210720 0x10 time alarm register rtc_timalr read-write 0x0 0x14 calendar alarm register rtc_calalr read-write 0x01010000 0x18 status register rtc_sr read-only 0x0 0x1c status clear command r egister rtc_sccr write-only C 0x20 interrupt enable register rtc_ier write-only C 0x24 interrupt disable re gister rtc_idr write-only C 0x28 interrupt mask register rtc_imr read-only 0x0 0x2c valid entry register rtc_ver read-only 0x0 0x30C0xf8 reserved register C C C 0xfc reserved register C C C
134 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 134 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 15.6.1 rtc control register name: rtc_cr address: 0xfffffeb0 access: read-write ? updtim: update request time register 0 = no effect. 1 = stops the rtc time counting. time counting consists of second, minute and hour counters. time counters can be programmed once this bit is set and acknowledged by the bit ackupd of the status register. ? updcal: update request calendar register 0 = no effect. 1 = stops the rtc calendar counting. calendar counting consists of day, date, month, year and century counters. calendar counters can be programmed once this bit is set. ? timevsel: time ev ent selection the event that generates the flag timev in rtc_sr (status register) depends on the value of timevsel. ? calevsel: calendar event selection the event that ge nerates the flag calev in rtc_sr depends on the value of calevsel 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCC c a l evsel 15 14 13 12 11 10 9 8 CCCCCC t i m e v s e l 76543210 CCCCCCu p d c a lu p d t i m value name description 0 minute minute change 1 hour hour change 2 midnight every day at midnight 3 noon every day at noon value name description 0 week week change (every monday at time 00:00:00) 1 month month change (every 01 of each month at time 00:00:00) 2 year year change (every janu ary 1 at time 00:00:00) 3C
135 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 135 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 15.6.2 rtc mode register name: rtc_mr address: 0xfffffeb4 access: read-write ? hrmod: 12-/24-hour mode 0 = 24-hour mode is selected. 1 = 12-hour mode is selected. all non-significant bits read zero. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCCh r m o d
136 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 136 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 15.6.3 rtc time register name: rtc_timr address: 0xfffffeb8 access: read-write ? sec: current second the range that can be set is 0 - 59 (bcd). the lowest four bits encode the units. the higher bits encode the tens. ? min: current minute the range that can be set is 0 - 59 (bcd). the lowest four bits encode the units. the higher bits encode the tens. ? hour: current hour the range that can be set is 1 - 12 (bcd) in 12-hour mode or 0 - 23 (bcd) in 24-hour mode. ? ampm: ante meridiem post meridiem indicator this bit is the am/pm in dicator in 12-hour mode. 0 = am. 1 = pm. all non-significant bits read zero. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 Ca m p m h o u r 15 14 13 12 11 10 9 8 Cm i n 76543210 Cs e c
137 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 137 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 15.6.4 rtc calendar register name: rtc_calr address: 0xfffffebc access: read-write ? cent: current century the range that can be set is 19 - 20 (bcd). the lowest four bits encode the units. the higher bits encode the tens. ? year: current year the range that can be set is 00 - 99 (bcd). the lowest four bits encode the units. the higher bits encode the tens. ? month: current month the range that can be set is 01 - 12 (bcd). the lowest four bits encode the units. the higher bits encode the tens. ? day: current day in current week the range that can be set is 1 - 7 (bcd). the coding of the number (which number represents which day) is user-defined as it has no effect on the date counter. ? date: current day in current month the range that can be set is 01 - 31 (bcd). the lowest four bits encode the units. the higher bits encode the tens. all non-significant bits read zero. 31 30 29 28 27 26 25 24 CC d a t e 23 22 21 20 19 18 17 16 day month 15 14 13 12 11 10 9 8 year 76543210 Cc e n t
138 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 138 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 15.6.5 rtc time alarm register name: rtc_timalr address: 0xfffffec0 access: read-write ? sec: second alarm this field is the alarm field corresponding to the bcd-coded second counter. ? secen: second alarm enable 0 = the second-matching alarm is disabled. 1 = the second-matching alarm is enabled. ? min: minute alarm this field is the alarm field corresponding to the bcd-coded minute counter. ? minen: minute alarm enable 0 = the minute-matching alarm is disabled. 1 = the minute-matching alarm is enabled. ? hour: hour alarm this field is the alarm field corresponding to the bcd-coded hour counter. ? ampm: am/pm indicator this field is the alarm field corresponding to the bcd-coded hour counter. ? houren: hour alarm enable 0 = the hour-matching alarm is disabled. 1 = the hour-matching alarm is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 houren ampm hour 15 14 13 12 11 10 9 8 minen min 76543210 secen sec
139 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 139 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 15.6.6 rtc calendar alarm register name: rtc_calalr address: 0xfffffec4 access: read-write ? month: month alarm this field is the alarm field corresponding to the bcd-coded month counter. ? mthen: month alarm enable 0 = the month-matching alarm is disabled. 1 = the month-matching alarm is enabled. ?date: date alarm this field is the alarm field corresponding to the bcd-coded date counter. ? dateen: date alarm enable 0 = the date-matching alarm is disabled. 1 = the date-matching alarm is enabled. 31 30 29 28 27 26 25 24 dateen C date 23 22 21 20 19 18 17 16 mthen C C month 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCCC
140 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 140 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 15.6.7 rtc status register name: rtc_sr address: 0xfffffec8 access: read-only ? ackupd: acknowledge for update 0 = time and calendar registers cannot be updated. 1 = time and calendar registers can be updated. ? alarm: alarm flag 0 = no alarm matching condition occurred. 1 = an alarm matching condition has occurred. ? sec: second event 0 = no second event has occurred since the last clear. 1 = at least one second event has occurred since the last clear. ? timev: time event 0 = no time event has occurred since the last clear. 1 = at least one time event has occurred since the last clear. the time event is selected in the timevsel field in rt c_cr (control register) and can be any one of the following events: minute change, hour change, noon, midnight (day change). ? calev: calendar event 0 = no calendar event has occurred since the last clear. 1 = at least one calendar event has occurred since the last clear. the calendar event is selected in the calevsel field in rtc_cr and can be any one of the following events: week change, month change and year change. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 C C C calev timev sec alarm ackupd
141 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 141 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 15.6.8 rtc status clear command register name: rtc_sccr address: 0xfffffecc access: write-only ? ackclr: acknowledge clear 0 = no effect. 1 = clears corresponding status flag in the status register (rtc_sr). ? alrclr: alarm clear 0 = no effect. 1 = clears corresponding status flag in the status register (rtc_sr). ? secclr: second clear 0 = no effect. 1 = clears corresponding status flag in the status register (rtc_sr). ? timclr: time clear 0 = no effect. 1 = clears corresponding status flag in the status register (rtc_sr). ? calclr: calendar clear 0 = no effect. 1 = clears corresponding status flag in the status register (rtc_sr). 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 C C C calclr timclr secclr alrclr ackclr
142 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 142 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 15.6.9 rtc interrupt enable register name: rtc_ier address: 0xfffffed0 access: write-only ? acken: acknowledge update interrupt enable 0 = no effect. 1 = the acknowledge for update interrupt is enabled. ? alren: alarm interrupt enable 0 = no effect. 1 = the alarm interrupt is enabled. ? secen: second event interrupt enable 0 = no effect. 1 = the second periodic interrupt is enabled. ? timen: time event interrupt enable 0 = no effect. 1 = the selected time event interrupt is enabled. ? calen: calendar event interrupt enable 0 = no effect. ? 1 = the selected calendar event interrupt is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 C C C calen timen secen alren acken
143 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 143 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 15.6.10 rtc interrupt disable register name: rtc_idr address: 0xfffffed4 access: write-only ? ackdis: acknowledge update interrupt disable 0 = no effect. 1 = the acknowledge for update interrupt is disabled. ? alrdis: alarm interrupt disable 0 = no effect. 1 = the alarm interrupt is disabled. ? secdis: second event interrupt disable 0 = no effect. 1 = the second periodic interrupt is disabled. ? timdis: time event interrupt disable 0 = no effect. 1 = the selected time event interrupt is disabled. ? caldis: calendar event interrupt disable 0 = no effect. 1 = the selected calendar event interrupt is disabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 C C C caldis timdis secdis alrdis ackdis
144 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 144 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 15.6.11 rtc interrupt mask register name: rtc_imr address: 0xfffffed8 access: read-only ? ack: acknowledge update interrupt mask 0 = the acknowledge for update interrupt is disabled. 1 = the acknowledge for update interrupt is enabled. ? alr: alarm interrupt mask 0 = the alarm interrupt is disabled. 1 = the alarm interrupt is enabled. ? sec: second event interrupt mask 0 = the second periodic interrupt is disabled. 1 = the second periodic interrupt is enabled. ? tim: time event interrupt mask 0 = the selected time event interrupt is disabled. 1 = the selected time event interrupt is enabled. ? cal: calendar event interrupt mask 0 = the selected calendar event interrupt is disabled. 1 = the selected calendar event interrupt is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCc a lt i ms e ca l ra c k
145 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 145 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 15.6.12 rtc valid entry register name: rtc_ver address: 0xfffffedc access: read-only ? nvtim: non-valid time 0 = no invalid data has been detected in rtc_timr (time register). 1 = rtc_timr has contained invalid data since it was last programmed. ? nvcal: non-valid calendar 0 = no invalid data has been detected in rtc_calr (calendar register). 1 = rtc_calr has contained invalid data since it was last programmed. ? nvtimalr: non-valid time alarm 0 = no invalid data has been detected in rtc_timalr (time alarm register). 1 = rtc_timalr has contained invalid data since it was last programmed. ? nvcalalr: non-valid calendar alarm 0 = no invalid data has been detected in rtc_calalr (calendar alarm register). 1 = rtc_calalr has contained invalid data since it was last programmed. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCn v c a l a l rn v t i m a l rn v c a ln v t i m
146 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 146 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12
147 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 16. periodic interval timer (pit) 16.1 description the periodic interval timer (pit) provides the operating systems scheduler interrupt. it is designed to offer maximum accuracy and efficient management, even for systems with long response time. 16.2 embedded characteristics ? 20-bit programmable counter plus 12-bit interval counter ? reset-on-read feature ? both counters work on master clock/16 ?amba ? -compliant interface C interfaces to the arm ? advanced peripheral bus 16.3 block diagram figure 16-1. periodic interval timer 20-bit counter mck/16 piv pit_mr cpiv pit_pivr picnt 12-bit adder 0 0 read pit_pivr cpiv picnt pit_piir pits pit_sr set reset pitien pit_mr pit_irq 1 0 10 mck prescaler =
148 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 16.4 functional description the periodic interval timer aims at providing pe riodic interrupts for use by operating systems. the pit provides a programmable overflow counter and a reset-on-read feature. it is built around two counters: a 20-bit cpiv counter and a 12-bit picnt counter. both counters work at master clock /16. the first 20-bit cpiv counter increments from 0 up to a programmable overflow value set in the field piv of the mode register (pit_mr). when the counter cpiv reaches this value, it resets to 0 and increments the periodic interval counter, picnt. the status bit pits in the status regis- ter (pit_sr) rises and triggers an interrupt, provided the interrupt is enabled (pitien in pit_mr). writing a new piv value in pit_mr does not reset/restart the counters. when cpiv and picnt values are obtained by reading the periodic interval value register (pit_pivr), the overflow counter (picnt) is rese t and the pits is cleared, thus acknowledging the interrupt. the value of picnt gives the number of periodic intervals elapsed since the last read of pit_pivr. when cpiv and picnt values are obtained by reading the periodic interval image register (pit_piir), there is no effect on the counters cpiv and picnt, nor on the bit pits. for exam- ple, a profiler can read pit_piir without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading pit_pivr. the pit may be enabled/disabled using the pite n bit in the pit_mr register (disabled on reset). the piten bit only becomes effective when the cpiv value is 0. figure 16-2 illustrates the pit counting. after the pit enable bit is re set (piten= 0), the cpiv goes on counting until the piv value is reached, and is then reset. pit restarts counting, only if the piten is set again. the pit is stopped when the core enters debug state.
149 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 16-2. enabling/disabling pit with piten mck prescaler piv piv - 1 0 piten 10 0 15 cpiv 1 restarts mck prescaler 0 1 apb cycle read pit_pivr 0 picnt pits (pit_sr) mck apb interface apb cycle
150 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 16.5 periodic interval time r (pit) user interface table 16-1. register mapping offset register name access reset 0x00 mode register pit_mr read-write 0x000f_ffff 0x04 status register pit_sr read-only 0x0000_0000 0x08 periodic interval value register pit_pivr read-only 0x0000_0000 0x0c periodic interval image register pit_piir read-only 0x0000_0000
151 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 16.5.1 periodic interval timer mode register name: pit_mr address: 0xfffffe30 access: read/write ? piv: periodic interval value defines the value compared with the primary 20-bit counter of the periodic interval timer (cpiv). the period is equal to (piv + 1). ? piten: period interval timer enabled 0 = the periodic interval timer is disabled when the piv value is reached. 1 = the periodic interval timer is enabled. ? pitien: periodic interval timer interrupt enable 0 = the bit pits in pit_sr has no effect on interrupt. 1 = the bit pits in pit_sr asserts interrupt. 31 30 29 28 27 26 25 24 CCCCCCp i t i e np i t e n 23 22 21 20 19 18 17 16 CCCC p i v 15 14 13 12 11 10 9 8 piv 76543210 piv
152 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 16.5.2 periodic interval timer status register name: pit_sr address: 0xfffffe34 access: read-only ? pits: periodic interval timer status 0 = the periodic interval timer has not reached piv since the last read of pit_pivr. 1 = the periodic interval timer has reached piv since the last read of pit_pivr. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCCp i t s
153 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 16.5.3 periodic interval timer value register name: pit_pivr address: 0xfffffe38 access: read-only reading this register clears pits in pit_sr. ? cpiv: current periodic interval value returns the current value of the periodic interval timer. ? picnt: periodic interval counter returns the number of occurrences of periodic intervals since the last read of pit_pivr. 31 30 29 28 27 26 25 24 picnt 23 22 21 20 19 18 17 16 picnt cpiv 15 14 13 12 11 10 9 8 cpiv 76543210 cpiv
154 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 16.5.4 periodic interval timer image register name: pit_piir address: 0xfffffe3c access: read-only ? cpiv: current periodic interval value returns the current value of the periodic interval timer. ? picnt: periodic interval counter returns the number of occurrences of periodic intervals since the last read of pit_pivr. 31 30 29 28 27 26 25 24 picnt 23 22 21 20 19 18 17 16 picnt cpiv 15 14 13 12 11 10 9 8 cpiv 76543210 cpiv
155 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 17. watchdog timer (wdt) 17.1 description the watchdog timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. it features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 khz). it can generate a general reset or a processor reset only. in addition, it can be stopped while the processor is in debug mode or idle mode. 17.2 embedded characteristics ? 12-bit key-protected programmable counter ? provides reset or interrupt signals to the system ? counter may be stopped while the processor is in debug state or in idle mode ?amba ? -compliant interface C interfaces to the arm ? advanced peripheral bus 17.3 block diagram figure 17-1. watchdog timer block diagram = 0 10 set reset read wdt_sr or reset wdt_fault (to reset controller) set reset wdfien wdt_int wdt_mr slck 1/128 12-bit down counter current value wdd wdt_mr <= wdd wdv wdrstt wdt_mr wdt_cr reload wdunf wderr reload write wdt_mr wdt_mr wdrsten
156 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 17.4 functional description the watchdog timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. it is supplied with vddcore. it re starts with initial values on processor reset. the watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field wdv of the mode register (wdt_m r). the watchdog timer uses the slow clock divided by 128 to establish the maximum watchdo g period to be 16 seconds (with a typical slow clock of 32.768 khz). after a processor reset, the value of wdv is 0xfff, corresponding to the maximum value of the counter with the external reset generation enabled (field wdrsten at 1 after a backup reset). this means that a default watchdog is running at reset, i.e., at power-up. the user must either disable it (by setting the wddis bit in wd t_mr) if he does not expect to use it or must reprogram it to meet the maximum watchdog period the application requires. the watchdog mode register (wdt_mr) can be written only once. only a processor reset resets it. writing the wdt_mr register reloads the timer with the newly programmed mode parameters. in normal operation, the user reloads the watchdog at regular intervals before the timer under- flow occurs, by writing the control register (wdt_cr) with the bit wdrstt to 1. the watchdog counter is then immediately reloaded from wdt_mr and restarted, and the slow clock 128 divider is reset and restarted. the wdt_cr register is write-protected. as a result, writing wdt_cr without the correct hard-coded key has no effect. if an underflow does occur, the wdt_fault signal to the reset controller is asserted if the bit wdrsten is set in the mode register (wdt_mr). moreover, the bit wdunf is set in the watchdog status register (wdt_sr). to prevent a software deadlock that continuously triggers the watchdog, the reload of the watchdog must occur while the watchdog counter is within a window between 0 and wdd, wdd is defined in the watchdog mode register wdt_mr. any attempt to restart the watchdog while the watchdog counter is between wdv and wdd results in a watchdog error, even if the watchdog is disabled. the bit wderr is updated in the wdt_sr and the wdt_fault signal to the reset controller is asserted. note that this feature can be disabled by programming a wdd value greater than or equal to the wdv value. in such a configuration, restarti ng the watchdog timer is permitted in the whole range [0; wdv] and does not generate an error. this is the default configuration on reset (the wdd and wdv values are equal). the status bits wdunf (watchdog underflow ) and wderr (watchdog error) trigger an inter- rupt, provided the bit wdfien is set in the mode register. the signal wdt_fault to the reset controller causes a watchdog reset if the wdrsten bit is set as already explained in the reset controller programmer datasheet. in that case, the processor and the watchdog timer are reset, and the wderr and wdunf flags are reset. if a reset is generated or if wdt_sr is read, the status bits are reset, the interrupt is cleared, and the wdt_fault signal to the reset controller is deasserted. writing the wdt_mr reloads and restarts the down counter. while the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits wdidlehlt and wddbghlt in the wdt_mr.
157 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 17-2. watchdog behavior 0 wdv wdd wdt_cr = wdrstt watchdog fault normal behavior watchdog error watchdog underflow fff if wdrsten is 1 if wdrsten is 0 forbidden window permitted window
158 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 17.5 watchdog timer (wdt) user interface table 17-1. register mapping offset register name access reset 0x00 control register wdt_cr write-only - 0x04 mode register wdt_mr read-write once 0x3fff_2fff 0x08 status register wdt_sr read-only 0x0000_0000
159 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 17.5.1 watchdog timer control register name: wdt_cr address: 0xfffffe40 access: write-only ? wdrstt: watchdog restart 0: no effect. 1: restarts the watchdog. ?key: password should be written at value 0xa5. writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCCw d r s t t
160 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 17.5.2 watchdog timer mode register name: wdt_mr address: 0xfffffe44 access: read-write once ? wdv: watchdog counter value defines the value loaded in the 12-bit watchdog counter. ? wdfien: watchdog fault interrupt enable 0: a watchdog fault (underflow or error) has no effect on interrupt. 1: a watchdog fault (underflow or error) asserts interrupt. ? wdrsten: watchdog reset enable 0: a watchdog fault (underflow or error) has no effect on the resets. 1: a watchdog fault (underflow or error) triggers a watchdog reset. ? wdrproc: watchdog reset processor 0: if wdrsten is 1, a watchdog fault (underflow or error) activates all resets. 1: if wdrsten is 1, a watchdog fault (underflow or error) activates the processor reset. ? wdd: watchdog delta value defines the permitted range for reloading the watchdog timer. if the watchdog timer value is less than or equal to w dd, writing wdt_cr with wdrs tt = 1 restarts the timer. if the watchdog timer value is greater than wdd, writing wdt_cr with wdrstt = 1 causes a watchdog error. ? wddbghlt: watchdog debug halt 0: the watchdog runs when the processor is in debug state. 1: the watchdog stops when the processor is in debug state. ? wdidlehlt: watchdog idle halt 0: the watchdog runs when the system is in idle mode. 1: the watchdog stops when the system is in idle state. ? wddis: watchdog disable 0: enables the watchdog timer. 1: disables the watchdog timer. 31 30 29 28 27 26 25 24 wdidlehlt wddbghlt wdd 23 22 21 20 19 18 17 16 wdd 15 14 13 12 11 10 9 8 wddis wdrproc wdrsten wdfien wdv 76543210 wdv
161 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 17.5.3 watchdog timer status register name: wdt_sr address: 0xfffffe48 access: read-only ? wdunf: watchdog underflow 0: no watchdog underflow occurred since the last read of wdt_sr. 1: at least one watchdog underflow occurred since the last read of wdt_sr. ? wderr: watchdog error 0: no watchdog error occurred since the last read of wdt_sr. 1: at least one watchdog error occurred since the last read of wdt_sr. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCw d e r rw d u n f
162 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12
163 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 163 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 18. shutdown controller (shdwc) 18.1 description the shutdown controller controls the pow er supplies vddio and vddcore and the wake-up detection on debounced input lines. 18.2 embedded characteristics ? shutdown and wake-up logic C software assertion of the shdw output pin C programmable de-assertion from the wkup input pins ? amba-compliant interface C interfaces to the arm advanced peripheral bus 18.3 block diagram figure 18-1. shutdown contro ller block diagram 18.4 i/o lines description shutdown wake-up shutdown output controller shdn wkup0 shdw wkmode0 shutdown controller rtc alarm rttwken shdw_mr shdw_mr shdw_cr cptwk0 wakeup0 rtcwk shdw_sr shdw_sr set set reset reset read shdw_sr read shdw_sr slck table 18-1. i/o lines description name description type wkup0 wake-up 0 input input shdn shutdown output output
164 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 164 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 18.5 product dependencies 18.5.1 power management the shutdown controller is continuously clock ed by slow clock. the power management con- troller has no effect on the behavior of the shutdown controller. 18.6 functional description the shutdown controller manages the main power supply. to do so, it is supplied with vddbu and manages wake-up input pins and one output pin, shdn. a typical application connects the pin shdn to the shutdown input of the dc/dc converter pro- viding the main power supplies of the system , and especially vddcore and/or vddio. the wake-up inputs (wkup0) connect to any push-buttons or signal that wake up the system. the software is able to control the pin s hdn by writing the shutdown control register (shdw_cr) with the bit shdw at 1. the shutdow n is taken into account only 2 slow clock cycles after the write of shdw_ cr. this register is password-protected and so the value written should contain the correct key for the command to be taken into account. as a result, the system should be powered down. a level change on wkup0 is used as wake-up. wake-up is configured in the shutdown mode register (shdw_mr). the transition detector can be programmed to detect either a positive or negative transition or any level change on wkup 0. the detection can also be disabled. pro- gramming is performed by defining wkmode0. moreover, a debouncing circuit can be programmed for wkup0. the debouncing circuit filters pulses on wkup0 shorter than the programmed number of 16 slck cycles in cptwk0 of the shdw_mr register. if the programmed level change is detected on a pin, a counter starts. when the counter reaches the value programmed in the corresponding field, cptwk0, the shdn pin is released. if a new input change is detected before the counter reaches the corre- sponding value, the counter is stopped and cleared. wakeup0 of the status register (shdw_sr) reports the detection of the programmed events on wkup0 with a reset after the read of shdw_sr. the shutdown controller can be programmed so as to activate the wake-up using the rtc alarm (the detection of the rising edge of the rtc alarm is synchronized with slck). this is done by writing the shdw_mr register using the rtcwken field. when enabled, the detection of the rtc alarm is reported in the rtcwk bit of the shdw_sr status register. it is reset after the read of shdw_sr. when using the rtc alarm to wake up th e system, the user must ensure that the rtc alarm status flag is clea red before shutting down the system.otherwise, no rising edge of the status flag may be detected and the wake-up fails fail.
165 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 165 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 18.7 shutdown controller (shdwc) user interface table 18-2. register mapping offset register name access reset 0x00 shutdown control register shdw_cr write-only - 0x04 shutdown mode register shdw_mr read-write 0x0000_0303 0x08 shutdown status register shdw_sr read-only 0x0000_0000
166 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 166 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 18.7.1 shutdown control register name: shdw_cr address: 0xfffffe10 access: write-only ? shdw: shutdown command 0 = no effect. 1 = if key is correct, asserts the shdn pin. ?key: password should be written at value 0xa5. writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCCs h d w
167 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 167 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 18.7.2 shutdown mode register name: shdw_mr address: 0xfffffe14 access: read/write ? wkmode0: wake-up mode 0 ? cptwk0: counter on wake-up 0 defines the number of 16 slow clock cycles, the level detection on the corresponding input pin shall last before the wake- up event occurs. because of the internal synchro nization of wkup0, the shdn pin is released (cptwk x 16 + 1) slow clock cycles after the event on wkup. ? rtcwken: real-time clock wake-up enable 0 = the rtc alarm signal has no effect on the shutdown controller. 1 = the rtc alarm signal forces the de-assertion of the shdn pin. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCr t c w k e nC 15 14 13 12 11 10 9 8 CC C C 76543210 cptwk0 C C wkmode0 wkmode[1:0] wake-up inpu t transition selection 0 0 none. no detection is performed on the wake-up input 0 1 low to high level 1 0 high to low level 1 1 both levels change
168 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 168 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 18.7.3 shutdown status register name: shdw_sr address: 0xfffffe18 access: read-only ? wakeup0: wake-up 0 status 0 = no wake-up event occurred on the corresponding wake-up input since the last read of shdw_sr. 1 = at least one wake-up event occurred on the corresponding wake-up input since the last read of shdw_sr. ? rtcwk: real-time clock wake-up 0 = no wake-up alarm from the rtc occurred since the last read of shdw_sr. 1 = at least one wake-up alarm from the rtc occurred since the last read of shdw_sr. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCr t c w kC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCCw akeup0
169 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 169 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 19. general purpose backup registers (gpbr) 19.1 description the system controller embeds four general-purpose backup registers. 19.2 embedded characteristics ? four 32-bit general purpose backup registers 19.3 general purpose backup regist ers (gpbr) user interface table 19-1. register mapping offset register name access reset 0x0 general purpose backup register 0 sys_gpbr0 read-write C ... ... ... ... ... 0xc general purpose backup register 3 sys_gpbr3 read-write C
170 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 170 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 19.3.1 general purpose backup register x name: sys_gpbrx address: 0xfffffe60 access: read-write ? gpbr_value: value of gpbr x 31 30 29 28 27 26 25 24 gpbr_value 23 22 21 20 19 18 17 16 gpbr_value 15 14 13 12 11 10 9 8 gpbr_value 76543210 gpbr_value
171 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 171 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 20. slow clock controller (sckc) 20.1 description the system controller embeds a slow clock controller. the slow clock can be ge nerated either by an ex ternal 32,768 hz crystal oscillator or by the on- chip 32 khz rc oscillator. the 32,768 hz crystal oscillator can be bypassed by setting the bit osc32byp to accept an external slow clock on xin32. the internal 32 khz rc oscillator and the 32,768 hz oscillator can be enabled by setting to 1, respectively, rcen bit and osc32en bit in the system controller user interface. the oscsel command selects the slow clock source. 20.2 embedded characteristics ? 32 khz rc oscillator or 32,768 hz oscillator selector ?vddbu powered
172 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 172 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 20.3 block diagram figure 20-1. block diagram rcen, osc32en, oscsel and osc32byp bits are located in the slow clock control register (sckcr) located at address 0xfffffe50 in the backed up part of the system controller and so are preserved while vddbu is present. after a vddbu power on reset, the default configuration is rcen = 1, osc32en = 0 and oscsel = 0, allowing the system to start on the internal 32 khz rc oscillator. the programmer controls the slow clock switching by software and so must take precautions during the switching phase. 20.3.1 switch from internal 32 khz rc oscillator to the 32,768 hz crystal oscillator to switch from the internal 32 khz rc oscillator to the 32,768 hz crystal oscillator, the program- mer must execute the following sequence: ? switch the master clock to a source different from slow clock (pll or main oscillator) through the power management controller. ? enable the 32,768 hz oscillator by setting the bit osc32en to 1. ? wait 32,768 hz startup time for clock stabilization (software loop). ? switch from internal 32 khz rc oscillator to 32,768 hz oscillator by setting the bit oscsel to 1. ? wait 5 slow clock cycles for internal resynchronization. ? disable the 32 khz rc oscillator by setting the bit rcen to 0. 20.3.2 bypass the 32,768 hz oscillator the following steps must be added to bypass the 32,768 hz oscillator: ? an external clock must be connected on xin32. ? enable the bypass path osc32byp bit set to 1. ? disable the 32,768 hz oscillator by setting the bit osc32en to 0. on chip rc osc slow clock slck xin32 xout32 slow clock oscillator osc32en rcen oscsel osc32byp
173 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 173 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 20.3.3 switch from the 32,768 hz crystal oscillator to internal 32 khz rc oscillator the same procedure must be followed to switch from a 32,768 hz crystal to the internal 32 khz rc oscillator: ? switch the master cloc k to a source different from slow clock (pll or main oscillator). ? enable the internal 32 khz rc oscillator fo r low power by setting the bit rcen to 1 ? wait internal 32 khz rc oscillator startup time for clock stabilization (software loop). ? switch from 32,768 hz oscillator to internal 32 khz rc oscillator by setting the bit oscsel to 0. ? wait 5 slow clock cycles for internal resynchronization. ? disable the 32,768 hz oscillator by setting the bit osc32en to 0. 20.4 slow clock configurati on (sckc) user interface table 20-1. register mapping offset register name access reset 0x0 slow clock configuration register sckc_cr read-write 0x0000_0001
174 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 174 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 20.4.1 slow clock configuration register name: sckc_cr address: 0xfffffe50 access: read-write reset: 0x0000_0001 ? rcen: internal 32 khz rc oscillator 0: 32 khz rc oscillator is disabled. 1: 32 khz rc oscillator is enabled. ? osc32en: 32,768 hz oscillator 0: 32,768 hz oscilla tor is disabled. 1: 32,768 hz osc illator is enabled. ? osc32byp: 32,768hz oscillator bypass 0: 32,768 hz oscillator is not bypassed. 1: 32,768 hz oscillator is bypassed, ac cept an external slow clock on xin32. ? oscsel: slow clock selector 0 (rc): slow clock is inte rnal 32 khz rc oscillator. 1 (xtal): slow clock is 32,768 hz oscillator. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 C C C C oscsel osc32byp osc32en rcen
175 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 175 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 21. clock generator 21.1 description the clock generator user interface is embedded within the power management controller and is described in section 22.12 power management controller (pmc) user interface . however, the clock generator registers are named ckgr_. 21.2 embedded characteristics the clock generator is made up of: ? one low power 32768 hz slow clock oscillator with bypass mode ? one low-power 32 khz rc oscillator ? one low-power 12 mhz rc oscillator ? one 16 mhz main oscillato r, which can be bypassed. ? one 400 to 800 mhz programmable plla, capable to provide the clock mck to the processor, and to the peripherals. this pll has an input divider to offer a wider range of output frequencies from the 16 mhz input, the only limitation being the lowest input frequency shall be higher or equal to 2 mhz. ? one 100 mhz programmable pllb dedicated to usb full speed operations. this pll has an input divider to offer a wider range of output frequencies from the 16 mhz input, the only limitation being the lowest input frequency shall be higher or equal to 2 mhz.
176 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 176 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 21.3 block diagram figure 21-1. clock generator block diagram po w er management controller xin xout main clock mainck co n t r o l st a t u s plla and divider plla clock pllack 16m main oscillator on chi p 32k rc osc sl o w cl o c k slck xin32 xout32 slow clock oscillator cl o ck gen er at o r rcen oscsel osc32en osc32byp on chi p 12m rc osc moscrcen m oscsel pllb and divider pllbck usb clocks
177 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 177 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 21.4 slow clock selection the slow clock can be generated either by an external 32,768 hz crystal or by the on-chip 32 khz rc oscillator. the 32,768 hz crystal oscillator can be bypassed by setting the bit osc32byp to accept an external slow clock on xin32. the internal 32 khz rc oscillator and the 32,768 hz oscillator can be enabled by setting to 1, respectively, rcen bit and osc32en bit in the system controller user interface. the oscsel command selects the slow clock source. figure 21-2. slow clock rcen, osc32en,oscsel and osc32byp bits are located in the slow clock control register (sckcr) located at address 0xfffffe50 in the backed up part of the system controller and so are preserved while vddbu is present. after a vddbu power on reset, the default configuration is rcen = 1, osc32en = 0 and osc- sel = 0, bypass = 0, allowing th e system to start on the in ternal 32 khz rc oscillator. the programmer controls the slow clock switching by software and so must take precautions during the switching phase. 21.4.1 switch from internal 32 khz rc oscillator to the 32,768 hz crystal to switch from internal 32 khz rc oscillator to the 32,768 hz crystal, th e programmer must exe- cute the following sequence: ? switch the master clock to a source different from slow clock (pll or main oscillator) through the power management controller. ? enable the 32,768 hz oscillator by setting the bit osc32en to 1. ? wait 32,768 hz startup time for clock stabilization (software loop). ? switch from internal 32 khz rc to 32,768 hz oscillator by setting the bit oscsel to 1. ? wait 5 slow clock cycles for internal resynchronization. ? disable the 32 khz rc oscillator by setting the bit rcen to 0. ? switch the master clock back to the slow clock domain on chip rc osc slow clock slck xin32 xout32 slow clock oscillator osc32en rcen oscsel osc32byp
178 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 178 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 21.4.2 bypass the 32768 hz oscillator the following step must be added to bypass th e 32768 hz oscillator. ? an external clock must be connected on xin32. ? enable the bypass path osc32byp bit set to 1. ? disable the 32768 hz oscillator by setting the bit osc32en to 0. 21.4.3 switch from the 32,768 hz crystal to internal 32 khz rc oscillator the same procedure must be followed to switch from a 32,768 hz crystal to the internal 32 khz rc oscillator. ? switch the master cloc k to a source different from slow clock (pll or main oscillator). ? enable the internal 32 khz rc oscillator fo r low power by setting the bit rcen to 1 ? wait internal 32 khz rc startup time for clock stabilization (software loop). ? switch from 32768 hz oscillator to inte rnal rc by setting the bit oscsel to 0. ? wait 5 slow clock cycles for internal resynchronization. ? disable the 32768 hz oscillator by setting the bit osc32en to 0. ? switch the master clock back to the slow clock domain
179 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 179 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 21.4.4 slow clock configuration register name: sckcr address: 0xfffffe50 access: read-write reset: 0x0000_0001 ? rcen: internal 32 khz rc 0: 32 khz rc is disabled 1: 32 khz rc is enabled ? osc32en: 32768 hz oscillator 0: 32768 hz osc illator is disabled 1: 32768 hz osc illator is enabled ? osc32byp: 32768 hz oscillator bypass 0: 32768 hz oscilla tor is not bypassed 1: 32768 hz oscillator is bypassed, accept an extern al slow clock on xin32 ? oscsel: slow clock selector 0: slow clock is internal 32 khz rc 1: slow clock is 32768 hz oscillator 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCo s c s e lo s c 3 2 b y po s c 3 2 e nr c e n
180 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 180 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 21.5 main clock figure 21-3. main clock block diagram the main clock has two sources: ? 12 mhz fast rc oscillator which starts very quickly and is used at startup ? 3 to 20 mhz crystal oscillator, which can be bypassed 21.5.1 12 mhz fast rc oscillator after reset, the 12 mhz fast rc oscillator is enabled and it is selected as the source of mck. mck is the default clock selected to start up the system. please refer to the dc characteristics section of the product datasheet. the software can disable or enable the 12 mhz fast rc oscillator with the moscrcen bit in the clock generator main osc illator register (ckgr_mor). when disabling the main clock by clearing the moscrcen bit in ckgr_mor, the moscrcs bit in the power management controller status register (pmc_sr) is automatically cleared, indicating the main clock is off. setting the moscrcs bit in the power management controller interrupt enable register (pmc_ier) can trigger an interrupt to the processor. xin xout moscxten moscxtcnt moscxts main clock frequency counter mainf mainrdy slck slow clock 3-20 mhz crystal oscillator 3-20 mhz crystal oscillator counter moscrcen 12 mhz fast rc oscillator moscrcs moscrcf moscrcen moscxten moscsel moscsel moscsels 1 0 mainck main clock
181 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 181 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 21.5.2 3 to 20 mhz crystal oscillator after reset, the 3 to 20 mhz crystal oscillator is disabled and it is not selected as the source of mainck. the user can select the 3 to 20 mhz crystal osc illator to be the source of mainck, as it provides a more accurate frequency. the so ftware enables or disables the main oscillator so as to reduce power consumption by cleari ng the moscxten bit in the main oscillator register (ckgr_mor). when disabling the main oscillator by clearing the moscxten bit in ckgr_mor, the moscxts bit in pmc_sr is automatically cl eared, indicating the main clock is off. when enabling the main oscillator, the user must initiate the ma in oscillator coun ter with a value corresponding to the startup time of the oscillat or. this startup time depends on the crystal fre- quency connected to the oscillator. when the moscxten bit and the moscxtcnt are written in ckgr_mor to enable the main oscillator, the moscxts bit in the power mana gement controller status register (pmc_sr) is cleared and the counter starts counting down on the slow clock divided by 8 from the moscx- tcnt value. since the moscxtcnt value is c oded with 8 bits, the maximum startup time is about 62 ms. when the counter reaches 0, the moscxts bit is se t, indicating that the main clock is valid. setting the moscxts bit in pmc_imr can trigger an interrupt to the processor. 21.5.3 main clock oscillator selection the user can select either the 12 mhz fast rc oscillator or the 3 to 20 mhz crystal oscillator to be the source of main clock. the advantage of the 12 mhz fast rc oscillator is to have fast startup time, this is why it is selected by default (to start up the system) and when entering in wait mode. the advantage of the 3 to 20 mhz crystal oscillator is that it is very accurate. the selection is made by writing the mosc sel bit in the main oscillator register (ckgr_mor). the switch of the main clock source is glitch free, so there is no need to run out of slck, pllack or upllck in order to change the selection. the moscsels bit of the power management controller status register (pmc_sr) allows knowing when the switch sequence is done. setting the moscsels bit in pmc_imr can trigger an interrupt to the processor. 21.5.4 software sequence to detect the presence of fast crystal the frequency meter carried on ckgr_mcfr register is operating on the selected main clock and not on fast crystal clo ck nor fast rc oscillator clock. therefore, to check for the presence of a fast cr ystal clock, it is necessary to switch the main clock on fast crystal clock. the following software sequence order must be followed: C mck must select the slow cloc k (css=0 in pll_mckr register). C wait for the mckrdy flag in pll_sr register to be 1. C the fast crystal must be enabled by programming 1 in moscxten field in ckgr_mor register with moscxtst field being programmed to the appropriate value (see electrical characteristics chapter).
182 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 182 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 C wait for the moscxts flag to be 1 in pll_sr register to get the end of startup period of the fast crystal oscillator. C then, moscsel must be programmed to 1 in ckgr_mor register to select fast main crystal oscillator for main clock. C the moscsel must be read until its value equals 1. C then moscsels status flag must be checked in pll_sr register. at this point, 2 cases may occur (e ither moscsels = 0 or moscsels = 1). C if moscsels = 1, there is a valid crystal connected and its frequency can be determined by initiating a frequency measure by programming rcmeas in ckgr_mcfr register. C if moscsels = 0, there is no fast crystal clock (either no crystal connected or an out of specification crystal clock). C a frequency measure can reinforce this status by initiating a frequency measure by programming rcmeas in ckgr_mcfr register. C if moscsels = 0, the selection of the main clock must be programmed back to main rc oscillator by writing moscsel to 0 prior to disable the fast crystal oscillator. C if moscsels = 0, the crystal oscillato r can be disabled (moscxten = 0 in ckgr_mor register). 21.5.5 main clock frequency counter the device features a main clock frequency counter that provides the frequency of the main clock. the main clock frequency counter is reset and starts incrementing at the main clock speed after the next rising edge of the slow clock in the following cases: ? when the 12 mhz fast rc oscillator clock is sele cted as the source of main clock and when this oscillator becomes stable (i.e ., when the moscrcs bit is set) ? when the 3 to 20 mhz crystal oscillator is sele cted as the source of main clock and when this oscillator becomes stable (i.e ., when the moscxts bit is set) ? when the main clock oscilla tor selection is modified then, at the 16th falling edge of slow clock, the mainfrdy bit in the clock generator main clock frequency register (ckgr_mcfr) is set and the counter stops counting. its value can be read in the mainf field of ckgr_mcfr and gi ves the number of main clock cycles during 16 periods of slow clock, so th at the frequency of the 12 mhz fa st rc oscillator or 3 to 20 mhz crystal oscillator can be determined. 21.6 divider and pll block the pll embeds an input divider to increase the accuracy of the resulting clock signals. how- ever, the user must respect the pll minimum input frequency when programming the divider. figure 21-4 shows the block diagram of the divider and pll block.
183 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 183 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 21-4. divider and pll block diagram 21.6.1 divider and phase lock loop programming the divider can be set between 1 and 255 in steps of 1. when a divider field (div) is set to 0, the output of the corresponding divider and the pll out put is a continuous signal at level 0. on reset, each div field is set to 0, thus the corresponding pll input clock is set to 0. the pll allows multiplication of the dividers out puts. the pll clock signal has a frequency that depends on the respective source signal frequency and on the parameters div and mul. the factor applied to the source signal frequency is (mul + 1)/div. when mul is written to 0, the corresponding pll is disabled and its power consumption is saved. re-enabling the pll can be performed by writing a value higher than 0 in the mul field. whenever the pll is re-enabled or one of its parameters is changed, the lock bit (locka or lockb) in pmc_sr is automatically cleared. the values written in the pllcount field (plla- count or pllbcount) in ckgr_pllr (ckgr_ pllar or ckgr_pllbr), are loaded in the pll counter. the pll counter then decrements at the speed of the slow clock until it reaches 0. at this time, the lock bit is set in pmc_sr and can trigger an interrupt to the processor. the user has to load the number of slow clock cycles required to cover the pll transient time into the pllcount field. during the plla or pllb initialization, the pmc_pllicpr register must be programmed correctly. the plla clock can be divided by 2 by writ ing the plladiv2 bit in pmc_mckr register. divider b divb pll b mulb diva pll a co u n t er pllbcount lockb pll a co u n t er pllacount locka mula outb outa slck p lla c k pllbc k divider a pll b mainck
184 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 184 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 22. power management controller (pmc) 22.1 description the power management controller (pmc) optimizes power consumption by controlling all sys- tem and user peripheral clocks. the pmc enables/disables the clock inputs to many of the peripherals and the core. 22.2 embedded characteristics the power management controller provides all the clock signals to the system. pmc input clocks: ? pllack: from plla ? pllbck: from pllb and dedicated to usb clock generation. ? slck: slow clock from external 32 khz oscillator or internal 32 khz rc ? mainck: main clock from external 16 mhz oscillator or internal 12 mhz rc pmc output clocks: ? processor clock pck. ? master clock mck, in particular to the matrix, the memory interfaces, the peripheral bridge. the divider can be 2, 3 or 4. ? each peripheral embeds its own divider, programmable in the pmc user interface. ? 133 mhz ddr system clock note: ddr system clock is not available when ma ster clock (mck) equals processor clock (pck). ? lcd pixel clock that can use ddr system clock or mck, the choice is done in the lcd user interface. ? uhp clock (uhpck), required by usb host port operations. ? udp clock (udpck), required by usb device port operations. ? two programmable clock outputs: pck0 and pck1 this allows software control of five flex ible operating modes: ? normal mode, processor and peripherals running at a programmable frequency ? idle mode, processor stopped waiting for an interrupt ? slow clock mode, processor and peripherals running at low frequency ? standby mode, mix of idle and backup mode, peripheral running at low frequency, processor stopped waiting for an interrupt ? backup mode, main power supplies off, vddbu powered by a battery
185 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 185 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 22.3 block diagram figure 22-1. general clock block diagram 22.4 master clock controller the master clock controller provides selection and division of the master clock (mck). mck is the clock provided to all the peripherals and the memory controller. the master clock is selected from one of the clocks provided by the clock generator. selecting the slow clock provides a slow clock signal to the whole device. selecting the main clock saves power consumption of the plls. the master clock controller is made up of a cloc k selector and a prescaler. it also contains a master clock divider which allows the processor clock to be faster than the master clock. the master clock selection is made by writi ng the css field (clock source selection) in pmc_mckr (master clock register). the prescaler supports the division by a power of 2 of the selected clock between 1 and 64. the pres field in pmc_mckr programs the prescaler. each time pmc_mckr is written to define a ne w master clock, the mckr dy bit is cleared in pmc_sr. it reads 0 until the master clock is es tablished. then, the mckrdy bit is set and can trigger an interrupt to the processor. this feature is useful when switching from a high-speed clock to a lower one to inform the software when the change is actually done. 22.5 processor clock controller the pmc features a processor clock controller (pck) that implements the processor idle mode. the processor clock can be disabled by writing the system clock disable register (pmc_scdr). the status of this clock (at least for debug purposes) can be read in the system clock status register (pmc_scsr). the processor clock (pck) is enabled after a reset and is automatically re-enabled by any enabled interrupt. the processor idle mode is ac hieved by disabling the processor clock and entering wait for interrupt mode. the processor clock is automatically re-enabled by any 2x mck ddrck /2 mck periph_clk[..] int slck mainck pllack pck processor clock controller mas ter clock controller peripher als clock controller on/off /1 /2 /3 /4 slck mainck prescaler /1,/2,/4,...,/64 progr ammab le clock controller pck[..] on/off /1,/2 divider x /1 /1.5 /2 divider pllbck pllbck prescaler /1,/2,/3,/4,...,/64
186 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 186 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 enabled fast or normal interrupt, or by the reset of the product. note: the arm wait for interrupt mode is entered by a cp15 coprocessor operation. refer to the atmel application note, optimiz- ing power consumption for at91sam9261-based systems, lit. number 6217. ( http://www.atmel.com/dyn/resources/prod_documents/doc6217.pdf ) when the processor clock is disabled, the current instruct ion is finished before the clock is stopped, but this does not pre- vent data transfers from other masters of the system bus. 22.6 usb device and host clocks the usb source clock is always generated from the pll b output. if using the usb, the user must program the pll to generate a 48 mhz, a 96 mhz or a 192 mhz signal with an accuracy of 0.25% depending on the usbdiv bit in ckgr_pllbr. when the pll b output is stable, i.e., the lockb is set: the usb host clock can be enabled by setting the uhp bit in pmc_scer. to save power on this peripheral when it is not used, the user can set the uhp bit in pmc_scdr. the uhp bit in pmc_scsr gives the activity of this clock. th e usb host port require both the 12/48 mhz signal and the master clock. the master clock may be controlled via the master clock controller. the usb device clock can be enabled by setti ng the udp bit in pmc_scer. to save power on this peripheral when it is not used, the user can set the udp bit in pmc_scdr. the udp bit in pmc_scsr gives the activity of this clock. the usb device port require both the 48 mhz signal and the master clock. the master clock may be controlled via the master clock controller. usb clock controller 22.7 lp-ddr/ddr2 clock the power management controller controls the clocks of the ddr memory. the ddr clock can be enabled and disabled wit h ddrck bit respectively in pmc_scer and pmc_sder registers. at reset ddr clock is disabled to save power consumption. in the case mdiv = 00, (pck = mck) and ddrck clock is not available. if input clock is pllack/plladiv2 the ddr controller can drive ddr2 and lp-ddr at up to 133mhz with mdiv = 11. to save plla power consumption, the user can choose upllck an input clock for the system. in this case the ddr controller can drive ld- ddr at up to 120mhz. 22.8 peripheral clock controller the power management controller controls the cl ocks of each embedded peripheral by means of the peripheral clock controller. the user can individually enable and disable the clock on the usb source clock udp clock (udpck) udp usbdiv divider /1,/2,/4 uhp clock (uhpck) uhp
187 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 187 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 peripherals and select a division factor from mck. this is done through the peripheral control register (pmc_pcr). in order to save power consumption, the division factor can be 1, 2, 4 or 8. pmc_pcr is a regis- ter that features a command and acts like a mailbo x. to write the division factor on a particular peripheral, the user needs to write a write comm and, the peripheral id and the chosen divi- sion factor. to read the current division factor on a particular peripheral, the user just needs to write the read command and the peripheral id. code example to select divider 8 for peripheral 2 and enable its clock: write_register(pmc_pcr,0x10031002) code example to read the divider of peripheral 4: write_register(pmc_pcr,0x00000004) when a peripheral clock is disabled, the clock is immediately stopped. the peripheral clocks are automatically disabled after a reset. in order to stop a peri pheral, it is recommended that the syst em software wait until the peripheral has executed its last programmed operation before disabling the clock. this is to avoid data cor- ruption or erroneous behavior of the system. the bit number within the peripheral control registers is the peripheral identifier defined at the product level. generally, the bit number corresponds to the interrupt source number assigned to the peripheral. 22.9 programmable clock output controller the pmc controls 2 signals to be output on external pins pckx. each signal can be indepen- dently programmed via the pmc_pckx registers. pckx can be independently selected between the slow clock, the master clock, the pllack/plladiv2, the utmi pll output and the main clock by writing the css field in pmc_pckx. each output signal can also be divide d by a power of 2 between 1 and 64 by writing the pres (prescaler) field in pmc_pckx. each output signal can be enabled and disabled by writing 1 in the corresponding bit, pckx of pmc_scer and pmc_scdr, respectively. status of the active programmable output clocks are given in the pckx bits of pmc_scsr (system clock status register). moreover, like the pck, a status bit in pmc_sr indicates that the programmable clock is actu- ally what has been programmed in the programmable clock registers. as the programmable clock controller does not manage with glitch prevention when switching clocks, it is strongly recommended to disable the programmable clock before any configuration change and to re-enable it after the change is actually performed. 22.10 programming sequence 1. enabling the 12 mh z main oscillator: the main oscillator is enabled by setting the moscen field in the ckgr_mor register. in some cases it may be advantageous to define a st art-up time. this can be achieved by writ- ing a value in the oscount field in the ckgr_mor register.
188 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 188 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 once this register has been correctly configured, the user must wait for moscs field in the pmc_sr register to be se t. this can be done either by polling the status regist er or by wait- ing the interrupt line to be raised if the associated interrupt to moscs has been enabled in the pmc_ier register. 2. setting plla and divider: all parameters needed to configure plla and t he divider are located in the ckgr_pllar register. the diva field is used to control the divider itself. a value between 0 and 255 can be pro- grammed. divider output is divider input divided by diva parameter. by default diva parameter is set to 0 which means that divider is turned off. the outa field is used to select the plla output frequency range. the mula field is the plla multiplier factor. this parameter can be programmed between 0 and 254. if mula is set to 0, plla will be turned off, otherwis e the plla outp ut frequency is plla input frequency multiplied by (mula + 1). the pllacount field specifies the number of slow clock cycles before locka bit is set in the pmc_sr register after ckgr_pllar register has been written. once the pmc_pllar register has been written, the user must wait for the locka bit to be set in the pmc_sr register. this can be done eith er by polling the status register or by wait- ing the interrupt line to be raised if the associated interrupt to locka has been enabled in the pmc_ier register. all parameters in ckgr_pllar can be programmed in a single write operation. if at some stage one of the following parameters, mula, diva is modified, locka bit will go low to indicate that plla is not ready yet. when plla is locked, locka will be set again. the user is constrained to wait for locka bit to be set before using the plla output clock. code example: write_register(ckgr_pllar,0x00040805) if plla and divider are enabled, the plla input clock is the main clock. plla output clock is plla input clock multiplied by 5. once ck gr_pllar has been written, locka bit will be set after eight slow clock cycles. 3. setting pll b and divider b: all parameters needed to configure pll b and divider b are located in the ckgr_pllbr register. the divb field is used to control divider b itself. a value between 0 and 255 can be pro- grammed. divider b output is divider b input divided by divb parameter. by default divb parameter is set to 0 which means that divider b is turned off. the outb field is used to select the pll b output frequency range. the mulb field is the pll b multiplier factor. this parameter can be programmed between 0 and 2047. if mulb is set to 0, pll b will be turned off, otherwis e the pll b output fre- quency is pll b input frequency multiplied by (mulb + 1).
189 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 189 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 the pllbcount field specifies the number of slow clock cycles before lockb bit is set in the pmc_sr register after ckgr_pllbr register has been written. once the pmc_pllb register has been written, the user must wait for the lockb bit to be set in the pmc_sr register. this can be done eith er by polling the status register or by wait- ing the interrupt line to be raised if the associated interrupt to lockb has been enabled in the pmc_ier register. all parameters in ckgr_pllbr can be programmed in a single write operation. if at some stage one of the following parameters, mulb, divb is modified, lockb bit will go low to indicate that pll b is not ready yet. when pl l b is locked, lockb will be set again. the user is constrained to wait for lockb bit to be set before using the pll a output clock. the usbdiv field is used to control the additional divider by 1, 2 or 4, which generates the usb clock(s). code example: write_register(ckgr_pllbr,0x00040805) if pll b and divider b are enabled, the pll b in put clock is the main clock. pll b output clock is pll b input clock multiplied by 5. once ckgr_pllbr has been written, lockb bit will be set after eight slow clock cycles. 4. selection of master clock and processor clock the master clock and the processor clock are configurable via the pmc_mckr register. the css field is used to select the clock sour ce of the master clock and processor clock dividers. by default, the selected clock source is main clock. the pres field is used to control the mast er/processor clock prescaler. the user can choose between different values (1, 2, 4, 8, 16, 32, 64). prescaler output is the selected clock source divided by pres parameter. by default, pres parameter is set to 1 which means that the input clock of the master clock and processor clock dividers is equal to slow clock. the mdiv field is used to control the master clock divider. it is possible to choose between different values (0, 1, 2, 3). the master cl ock output is master/processor clock prescaler output divided by 1, 2, 4 or 3, depending on the value programmed in mdiv. the plladiv2 field is used to control the plla clock divider. it is possible to choose between different values (0, 1). the pmc plla clock input is divid ed by 1 or 2, depending on the value programmed in plladiv2. by default, mdiv and plladiv2 are set to 0, which indicates that processor clock is equal to the master clock. once the pmc_mckr register has been written, the user must wait for the mckrdy bit to be set in the pmc_sr register. this can be done either by polling the status register or by waiting for the interrupt line to be raised if the associated interrupt to mckrdy has been enabled in the pmc_ier register.
190 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 190 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 the pmc_mckr register must not be programmed in a single write operation. the pre- ferred programming sequence for the pmc_mckr register is as follows: ? if a new value for css field corresponds to plla clock, C program the pres field in the pmc_mckr register. C wait for the mckrdy bit to be set in the pmc_sr register. C program the css field in the pmc_mckr register. C wait for the mckrdy bit to be set in the pmc_sr register. ? if a new value for css field corresponds to main clock or slow clock, C program the css field in the pmc_mckr register. C wait for the mckrdy bit to be set in the pmc_sr register. C program the pres field in the pmc_mckr register. C wait for the mckrdy bit to be set in the pmc_sr register. if at some stage one of the following parameters, css or pres, is modified, the mckrdy bit will go low to indicate that the master clock and the processor clock are not ready yet. the user must wait for mckrdy bit to be set again before using the master and processor clocks. note: if plla clock was selected as the master clock and the user decides to modify it by writing in ckgr_pllar, the mckrdy flag will go low while plla is unlocked. once plla is locked again, lock goes high and mckrdy is set. while plla is unlocked, the master clock select ion is automatically changed to main clock. for further information, see section 22.11.2 . clock switching waveforms on page 193 . code example: write_register(pmc_mckr,0x00000001) wait (mckrdy=1) write_register(pmc_mckr,0x00000011) wait (mckrdy=1) the master clock is main clock divided by 16. the processor clock is the master clock. 5. selection of programmable clocks programmable clocks are controlled via registers; pmc_scer, pmc_scdr and pmc_scsr. programmable clocks can be enabled and/or disabled via the pmc_scer and pmc_scdr registers. depending on the system used, 2 programmable cl ocks can be enabled or dis- abled. the pmc_scsr provides a clear indi cation as to which programmable clock is enabled. by default all programmable clocks are disabled. pmc_pckx registers are used to configure programmable clocks. the css and cssmck fields are used to sele ct the programmable clock divider source. five clock options are available: main clock, slow clock, master clock, pllack, upllck. by default, the clock source selected is slow clock. the pres field is used to control the programmable clock prescaler. it is possible to choose between different values (1, 2, 4, 8, 16, 32, 64). programmable clock output is prescaler
191 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 191 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 input divided by pres parameter. by default, the pres parameter is set to 1 which means that master clock is equal to slow clock. once the pmc_pckx register has been programmed, the corresponding programmable clock must be enabled and the user is constrai ned to wait for the pckrdyx bit to be set in the pmc_sr register. this can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to pckrdyx has been enabled in the pmc_ier register. all parameters in pmc_ pckx can be programmed in a single write operation. if the css and pres parameters are to be modified, the corresponding programmable clock must be disabled first. the parameters can then be modified. once this has been done, the user must re-enable the programmable clock and wait for the pckrdyx bit to be set. code example: write_register(pmc_pck0,0x00000015) programmable clock 0 is main clock divided by 32. 6. enabling peripheral clocks once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via registers pmc_pcer and pmc_pcdr. depending on the system used, 19 peripheral clocks ca n be enabled or disabled. the pmc_pcr provides a clear view as to which peripheral clock is enabled. note: each enabled peripheral clock corresponds to master clock. code examples: write_register(pmc_pcer,0x00000110) peripheral clocks 4 and 8 are enabled. write_register(pmc_pcdr,0x00000010) peripheral clock 4 is disabled.
192 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 192 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 22.11 clock switching details 22.11.1 master clock switching timings table 22-1 and table 22-2 give the worst case ti mings required for the master clock to switch from one selected clock to another one. this is in the event that the prescaler is de-activated. when the prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be added. notes: 1. pll designates either the plla or the upll clock. 2. pllcount designates either pllacount or upllcount. table 22-1. clock switching timings (worst case) from main clock slck pll clock to main clock C 4 x slck + 2.5 x main clock 3 x pll clock + 4 x slck + 1 x main clock slck 0.5 x main clock + 4.5 x slck C 3 x pll clock + 5 x slck pll clock 0.5 x main clock + 4 x slck + pllcount x slck + 2.5 x pllx clock 2.5 x pll clock + 5 x slck + pllcount x slck 2.5 x pll clock + 4 x slck + pllcount x slck table 22-2. clock switching timings between two plls (worst case) from plla clock pllb clock to plla clock 2.5 x plla clock + 4 x slck + pllacount x slck 3 x plla clock + 4 x slck + 1.5 x plla clock pllb clock 3 x pllb clock + 4 x slck + 1.5 x pllb clock 2.5 x pllb clock + 4 x slck + pllbcount x slck
193 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 193 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 22.11.2 clock switching waveforms figure 22-2. switch master clock from slow clock to pll clock figure 22-3. switch master clock from main clock to slow clock slow clock lock mckrdy master clock write pmc_mckr pll clock slow clock main clock mckrdy master clock write pmc_mckr
194 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 194 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 22-4. change plla programming figure 22-5. programmable clock output programming slow clock slow clock plla clock locka mckrdy master clock write ckgr_pllar pll clock pckrdy pckx output write pmc_pckx write pmc_scer write pmc_scdr pckx is disabled pckx is enabled pll clock is selected
195 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 195 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 22.12 power management contro ller (pmc) user interface table 22-3. register mapping offset register name access reset 0x0000 system clock enable register pmc_scer write-only n.a. 0x0004 system clock disable register pmc_scdr write-only n.a. 0x0008 system clock status regi ster pmc_scsr read-only 0x0000_0005 0x0010 peripheral clock enable register pmc _pcer write-only n.a. 0x0014 peripheral clock disable register pmc_pcdr write-only C 0x0018 peripheral clock status register pmc_pcsr read-only 0x0000_0000 0x000c - 0x0018 reserved C C C 0x001c reserved C C C 0x0020 main oscillator register ckgr_mor read-write 0x0100_0001 0x0024 main clock frequency register ckgr_mcfr read-write 0x0000_0000 0x0028 plla register ckgr_pllar read-write 0x0000_3f00 0x002c pllb register ckgr_pllbr read-write 0x0000_3f00 0x0030 master clock register pmc_mckr read-write 0x0000_0001 0x0034 reserved C C C 0x0038 usb clock register pmc_usb read-write 0x0000_0000 0x003c reserved C C C 0x0040 programmable clock 0 register pmc_pck0 read-write 0x0000_0000 0x0044 programmable clock 1 register pmc_pck1 read-write 0x0000_0000 0x0048 - 0x005c reserved C C C 0x0060 interrupt enable register pmc_ier write-only n.a. 0x0064 interrupt disable register pmc_idr write-only n.a. 0x0068 status register pmc_sr read-only 0x0001_0008 0x006c interrupt mask register pmc_imr read-only 0x0000_0000 0x0070 - 0x0078 reserved C C C 0x0080 pll charge pump current register pmc_pllicpr write-only 0x0100_0100 0x0084-0x00e0 reserved C C C 0x00e4 write protect mode register pmc_wpmr read-write 0x0000_0000 0x00e8 write protect status register pmc_wpsr read-only 0x0000_0000 0x00ec-0x0108 reserved C C C 0x010c peripheral control register pmc_pcr read-write 0x0000_0000
196 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 196 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 22.12.1 pmc system clock enable register name: pmc_scer address: 0xfffffc00 access: write-only ? ddrck: ddr clock enable 0 = no effect. 1 = enables the ddr clock. ? lcdck: lcd clock enable 0 = no effect. 1 = enables the lcd clock. ? uhp: usb host ohci clocks enable 0 = no effect. 1 = enables the uhp48m and uhp12m ohci clocks. ? udp: usb device clock enable 0 = no effect. 1 = enables the usb device clock. ? pckx: programmable clock x output enable 0 = no effect. 1 = enables the corresponding programmable clock output. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCp c k 1p c k 0 76543210 udp uhp C C lcdck ddrck C C
197 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 197 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 22.12.2 pmc system clock disable register name: pmc_scdr address: 0xfffffc04 access: write-only ? pck: processor clock disable 0 = no effect. 1 = disables the processor clock. this is used to enter the processor in idle mode. ? ddrck: ddr clock disable 0 = no effect. 1 = disables the ddr clock. ? lcdck: lcd clock disable 0 = no effect. 1 = disables the lcd clock. ? uhp: usb host ohci clock disable 0 = no effect. 1 = disables the uhp48m and uhp12m ohci clocks. ? udp: usb device clock enable 0 = no effect. 1 = disables the usb device clock. ? pckx: programmable clock x output disable 0 = no effect. 1 = disables the corresponding programmable clock output. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCp c k 1p c k 0 76543210 udp uhp C C lcdck ddrck C pck
198 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 198 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 22.12.3 pmc system clock status register name: pmc_scsr address: 0xfffffc08 access: read-only ? pck: processor clock status 0 = the processor clock is disabled. 1 = the processor clock is enabled. ? ddrck: ddr clock status 0 = the ddr clock is disabled. 1 = the ddr clock is enabled. ? lcdck: lcd clock status 0 = the lcd clock is disabled. 1 = the lcd clock is enabled. ? uhp: usb host port clock status 0 = the uhp48m and uhp12m ohci clocks are disabled. 1 = the uhp48m and uhp12m ohci clocks are enabled. ? udp: usb device port clock status 0 = the usb device clock is disabled. 1 = the usb device clock is enabled. ? pckx: programmable clock x output status 0 = the corresponding programmable clock output is disabled. 1 = the corresponding programmable clock output is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCp c k 1p c k 0 76543210 udp uhp C C lcdck ddrck C pck
199 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 199 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 22.12.4 pmc peripheral clock enable register name: pmc_pcer address: 0xfffffc10 access: write-only ? pidx: peripheral clock x enable 0 = no effect. 1 = enables the corresponding peripheral clock. note: pid2 to pid31 refer to identifiers as defined in the section peripheral identifiers in the product datasheet. note: programming the control bits of the peripheral id that ar e not implemented has no effect on the behavior of the pmc. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 - -
200 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 200 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 22.12.5 pmc peripheral clock disable register name: pmc_pcdr address: 0xfffffc14 access: write-only ? pidx: peripheral clock x disable 0 = no effect. 1 = disables the corresponding peripheral clock. note: pid2 to pid31 refer to identifiers as defined in the section peripheral identifiers in the product datasheet. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 - -
201 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 201 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 22.12.6 pmc peripheral clock status register name: pmc_pcsr address: 0xfffffc18 access: read-only ? pidx: peripheral clock x status 0 = the corresponding peripheral clock is disabled. 1 = the corresponding peripheral clock is enabled. note: pid2 to pid31 refer to identifiers as defined in the section peripheral identifiers in the product datasheet. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 C C
202 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 202 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 22.12.7 pmc clock generator main oscillator register name: ckgr_mor address: 0xfffffc20 access: read-write ?key: password should be written at value 0x37. writing any other value in this field aborts the write operation. ? moscxten: main crystal oscillator enable a crystal must be connected between xin and xout. 0 = the main crystal oscillator is disabled. 1 = the main crystal oscillator is enabled. moscxtby must be set to 0. when moscxten is set, the moscxts flag is set once the main crystal oscillator startup time is achieved. ? moscxtby: main crystal oscillator bypass 0 = no effect. 1 = the main crystal oscillator is bypass ed. moscxten must be set to 0. an ex ternal clock must be connected on xin. when moscxtby is set, the moscxts flag in pmc_sr is automatically set. clearing moscxten and moscxtby bits allows resetting the moscxts flag. ? moscrcen: main on-chip rc oscillator enable 0 = the main on-chip rc oscillator is disabled. 1 = the main on-chip rc oscillator is enabled. when moscrcen is set, the mo scrcs flag is set once the main on-chip rc oscillator startup time is achieved. ? moscxtst: main crystal oscillator start-up time specifies the number of slow clock cycles multiplied by 8 for the main crystal oscillator start-up time. ? moscsel: main oscillator selection 0 = the main on-chip rc oscillator is selected. 1 = the main crystal os cillator is selected. ? cfden: clock failure detector enable 0 = the clock failure de tector is disabled. 1 = the clock failure de tector is enabled. 31 30 29 28 27 26 25 24 CCCCCCc f d e nm o s c s e l 23 22 21 20 19 18 17 16 key 15 14 13 12 11 10 9 8 moscxtst 76543210 CCCCm o s crcen C moscxtby moscxten
203 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 203 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 22.12.8 pmc clock generator main clock frequency register name: ckgr_mcfr address: 0xfffffc24 access: read-write ? mainf: main clock frequency gives the number of main clock cycles within 16 slow clock periods. ? mainfrdy: main clock ready 0 = mainf value is not valid or the main oscillator is disabled. 1 = the main oscillator has been enabled pr eviously and mainf value is available. ? rcmeas: rc measure this bit is write-only. 0 = no effect. 1 = restart a measure of the main rc frequency. mainf will carry the new frequency as soon as a low to high transition occurs on mainfrdy flag. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCr c m e a sCCCm a i n f r d y 15 14 13 12 11 10 9 8 mainf 76543210 mainf
204 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 204 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 22.12.9 pmc clock generator plla register name: ckgr_pllar address: 0xfffffc28 access: read-write possible limitations on plla input frequencies and multiplier factors should be checked before using the pmc. warning: bit 29 must always be set to 1 when programming the ckgr_pllar register. ? diva: divider a 0 = divider output is 0 1 = divider is bypassed 2 up to 255 = divider output is the selected clock divided by diva ? pllacount: plla counter specifies the number of slow clock cycles before the lo cka bit is set in pmc_sr after ckgr_pllar is written. ? outa: plla clock frequency range to optimize clock performance, this field must be programmed as specified in pll characteristics in the electrical char- acteristics section of the product datasheet. ? mula: plla multiplier 0 = the plla is deactivated. 1 up to 254 = the plla clock frequency is the plla input frequency multiplied by mula+ 1. 31 30 29 28 27 26 25 24 CC1CC m u l a 23 22 21 20 19 18 17 16 mula 15 14 13 12 11 10 9 8 outa pllacount 76543210 diva
205 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 205 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 22.12.10 pmc clock generator pllb register name: ckgr_pllbr address: 0xfffffc2c access: read-write possible limitations on pllb input frequencies and multiplier factors should be checked before using the pmc. ? divb: divider b 0 = divider output is 0 1 = divider is bypassed 2 up to 255 = divider output is the selected clock divided by divb ? pllbcount: pllb counter specifies the number of slow clock cycles before the lo ckb bit is set in pmc_sr after ckgr_pllbr is written. ? outb: pllb clock frequency range to optimize clock performance, this field must be programmed as specified in pll characteristics in the electrical char- acteristics section of the product datasheet. ? mulb: pllb multiplier 0 = the pllb is deactivated. 1 up to 254 = the pllb clock frequency is the pllb input frequency multiplied by mulb+1. 31 30 29 28 27 26 25 24 CCCCC m u l b 23 22 21 20 19 18 17 16 mulb 15 14 13 12 11 10 9 8 outb pllbcount 76543210 divb
206 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 206 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 22.12.11 pmc master clock register name: pmc_mckr address: 0xfffffc30 access: read-write ? css: master/processor clock source selection ? pres: master/processor clock prescaler 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCp l l a d i v 2CC m d i v 76543210 Cp r e sC Cc s s value name description 0 slow_clk slow clock is selected 1 main_clk main clock is selected 2 plla_clk pllack/plladiv2 is selected 3 pllb_clk pllbck is selected value name description 0 clock_div1 selected clock 1 clock_div2 selected clock divided by 2 2 clock_div4 selected clock divided by 4 3 clock_div8 selected clock divided by 8 4 clock_div16 selected clock divided by 16 5 clock_div32 selected clock divided by 32 6 clock_div64 selected clock divided by 64 7 reserved reserved
207 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 207 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? mdiv: master clock division ? plladiv2: plla divisor by 2 value name description 0e q _ p c k master clock is prescaler output clock divided by 1. warning: ddrck is not available. 1p c k _ d i v 2 master clock is prescaler output clock divided by 2. ddrck is equal to mck. 2p c k _ d i v 4 master clock is prescaler output clock divided by 4. ddrck is equal to mck. 3p c k _ d i v 3 master clock is prescaler output clock divided by 3. ddrck is equal to mck. value name description 0 not_div2 plla clock frequency is divided by 1. 1 div2 plla clock frequency is divided by 2.
208 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 208 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 22.12.12 usb clock register name: pmc_usb address: 0xfffffc38 access: read-write ? usbs: usb ohci input clock selection 0 = usb clock disabled. 1 = usb clock input is pllb. ? usbdiv: divider for usb clock usb clock is input clock divided by usbdiv+1. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCC u s b d i v 76543210 CCCCCCCu s b s
209 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 209 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 22.12.13 pmc programmable clock register name: pmc_pckx address: 0xfffffc40 access: read-write ? css: master clock source selection ? pres: programmable clock prescaler 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 Cp r e sC c s s value name description 0 slow_clk slow clock is selected 1 main_clk main clock is selected 2 plla_clk pllack/plladiv2 is selected 3 pllb_clk pllbck is selected 4 mck_clk master clock is selected value name description 0 clock_div1 selected clock 1 clock_div2 selected clock divided by 2 2 clock_div4 selected clock divided by 4 3 clock_div8 selected clock divided by 8 4 clock_div16 selected clock divided by 16 5 clock_div32 selected clock divided by 32 6 clock_div64 selected clock divided by 64 7 reserved reserved
210 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 210 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 22.12.14 pmc interrupt enable register name: pmc_ier address: 0xfffffc60 access: write-only ? moscxts: main crystal oscillator status interrupt enable ? locka: plla lock interrupt enable ? lockb: pllb lock interrupt enable ? mckrdy: master clock ready interrupt enable ? pckrdyx: programmable clock ready x interrupt enable ? moscsels: main oscillator selection status interrupt enable ? moscrcs: main on-chip rc status interrupt enable ? cfdev: clock failure detector event interrupt enable 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCc f d e vm o s c r c sm o s c s e l s 15 14 13 12 11 10 9 8 CCCCCCp c k r d y 1p c k r d y 0 76543210 CCCCm c k r d yl o c k bl o c k am o s c x t s
211 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 211 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 22.12.15 pmc interrupt disable register name: pmc_idr address: 0xfffffc64 access: write-only ? moscxts: main crystal oscillator status interrupt disable ? locka: plla lock interrupt disable ? lockb: pllb lock interrupt disable ? mckrdy: master clock ready interrupt disable ? pckrdyx: programmable clock ready x interrupt disable ? moscsels: main oscillator selection status interrupt disable ? moscrcs: main on-chip rc status interrupt disable ? cfdev: clock failure detector event interrupt disable 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCc f d e vm o s c r c sm o s c s e l s 15 14 13 12 11 10 9 8 CCCCCCp c k r d y 1p c k r d y 0 76543210 CCCCm c k r d yl o c k bl o c k am o s c x t s
212 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 212 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 22.12.16 pmc status register name: pmc_sr address: 0xfffffc68 access: read-only ? moscxts: main xtal oscillator status 0 = main xtal oscilla tor is not stabilized. 1 = main xtal osc illator is stabilized. ? locka: plla lock status 0 = plla is not locked 1 = plla is locked. ? lockb: pllb lock status 0 = pllb is not locked 1 = pllb is locked. ? mckrdy: master clock status 0 = master clock is not ready. 1 = master clock is ready. ? oscsels: slow clock oscillator selection 0 = internal slow clock rc oscillator is selected. 1 = external slow clock 32 khz oscillator is selected. ? pckrdyx: programmable clock ready status 0 = programmable clock x is not ready. 1 = programmable clock x is ready. ? moscsels: main oscillator selection status 0 = selection is in progress. 1 = selection is done. ? moscrcs: main on-chip rc oscillator status 0 = main on-chip rc osc illator is not stabilized. 1 = main on-chip rc o scillator is stabilized. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 C C C fos cfds cfdev moscrcs moscsels 15 14 13 12 11 10 9 8 CCCCCCp c k r d y 1p c k r d y 0 76543210 oscsels C C C mckrdy lockb locka moscxts
213 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 213 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? cfdev: clock failure detector event 0 = no clock failure detection of the main on-chip rc oscillator clock has oc curred since the last read of pmc_sr. 1 = at least one clock failure det ection of the main on-chip rc oscillator clock has occurred si nce the last read of pmc_sr. ? cfds: clock failure detector status 0 = a clock failure of the main on-chip rc oscillator clock is not detected. 1 = a clock failure of the main on-chip rc oscillator clock is detected. ? fos: clock failure detector fault output status 0 = the fault output of the clock failure detector is inactive. 1 = the fault output of the clock failure detector is active.
214 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 214 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 22.12.17 pmc interrupt mask register name: pmc_imr address: 0xfffffc6c access: read-only ? moscxts: main crystal oscillator status interrupt mask ? locka: plla lock interrupt mask ? lockb: pllb lock interrupt mask ? mckrdy: master clock ready interrupt mask ? pckrdyx: programmable clock ready x interrupt mask ? moscsels: main oscillator selection status interrupt mask ? moscrcs: main on-chip rc status interrupt mask ? cfdev: clock failure detector event interrupt mask 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCc f d e vm o s c r c sm o s c s e l s 15 14 13 12 11 10 9 8 CCCCCCp c k r d y 1p c k r d y 0 76543210 CCCCm c k r d yl o c k bl o c k am o s c x t s
215 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 215 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 22.12.18 pll charge pump current register name: pmc_pllicpr address: 0xfffffc80 access: write-only ? icplla: charge pump current to optimize clock performance, this field must be programmed as specified in pll a characteristics in the electrical char- acteristics section of the product datasheet. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCCi c p l l a
216 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 216 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 22.12.19 pmc write protect mode register name: pmc_wpmr address: 0xfffffce4 access: read-write reset: see table 22-3 ? wpen: write protect enable 0 = disables the write protect if wpkey co rresponds to 0x504d43 (pmc in ascii). 1 = enables the write protect if wpkey corresponds to 0x504d43 (pmc in ascii). protects the registers: ? pmc system clock enable register on page 196 ? pmc system clock disable register on page 197 ? pmc clock generator main clock frequency register on page 203 ? pmc clock generator plla register on page 204 ? pmc master clock register on page 206 ? pmc programmable clock register on page 209 ? pmc programmable clock register on page 209 ? pll charge pump current register on page 215 ? wpkey: write protect key should be written at value 0x504d43 (pmc in ascii). writing an y other value in this field aborts the write operation of the wpen bit. always reads as 0. 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 CCCCCCCw p e n
217 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 217 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 22.12.20 pmc write protect status register name: pmc_wpsr address: 0xfffffce8 access: read-only reset: see table 22-3 ? wpvs: write protect violation status 0 = no write protect violation has occurred since the last read of the pmc_wpsr register. 1 = a write protect violation has occurred since the last read of the pmc_wpsr register. if this violation is an unauthor- ized attempt to write a protected register, the associated violation is reported into field wpvsrc. ? wpvsrc: write protect violation source when wpvs is active, this field indicates the write-protected register (t hrough address offset or code) in which a write access has been attempted. reading pmc_wpsr automatically clears all fields. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 wpvsrc 15 14 13 12 11 10 9 8 wpvsrc 76543210 CCCCCCCw p v s
218 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 218 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 22.12.21 pmc peripheral control register name: pmc_pcr address: 0xfffffd0c access: write-only ? pid: peripheral id peripheral id selection from pid2 to pid31 pid2 to pid31 refer to identifiers as defined in the section peripheral identifiers in the product datasheet. ? cmd: command 0: read mode 1: write mode ? div: divisor value ? en: enable 0: selected peripheral clock is disabled 1: selected peripheral clock is enabled 31 30 29 28 27 26 25 24 CCCe nCCCC 23 22 21 20 19 18 17 16 CCCCCC div 15 14 13 12 11 10 9 8 CCC cmd CCCC 76543210 CC pid value name description 0 periph_div_mck peripheral clock is mck 1 periph_div2_mck peripheral clock is mck/2 2 periph_div4_mck peripheral clock is mck/4 3 periph_div8_mck peripheral clock is mck/8
219 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 219 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23. parallel input/outp ut controller (pio) 23.1 description the parallel input/output controller (pio) manages up to 32 fully programmable input/output lines. each i/o line may be dedicated as a general-purpose i/o or be assigned to a function of an embedded peripheral. this assures effective optimization of the pins of a product. each i/o line is associated with a bit number in all of the 32-bit registers of the 32-bit wide user interface. each i/o line of the pio controller features: ? an input change interrupt enabling level change detection on any i/o line. ? additional interrupt modes enab ling rising edge, falling edge, low level or high level detection on any i/o line. ? a glitch filter providing rejection of glitches lower than one-half of pio clock cycle. ? a debouncing filter providing rejection of unwanted pulses from key or push button operations. ? multi-drive capability similar to an open drain i/o line. ? control of the pull-up and pull-down of the i/o line. ? input visibility a nd output control. the pio controller also features a synchronous output providing up to 32 bits of data output in a single write operation. 23.2 embedded characteristics ? up to 32 programmable i/o lines ? fully programmable through set/clear registers ? multiplexing of four peripheral functions per i/o line ? for each i/o line (whether assigned to a peripheral or used as general purpose i/o) C input change interrupt C programmable glitch filter C programmable debouncing filter C multi-drive option enables driving in open drain C programmable pull up on each i/o line C pin data status register, supplies visibility of the level on the pin at any time C additional interrupt modes on a programmable event: rising edge, falling edge, low level or high level C lock of the configuration by the connected peripheral ? synchronous output, provides set and clear of several i/o lines in a single write ? write protect registers ? programmable schmitt trigger inputs ? programmable i/o delay ? programmable i/o drive
220 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 220 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.3 block diagram figure 23-1. block diagram figure 23-2. application block diagram embedded peripher al embedded peripher al pio interr upt pio controller up to 32 pins pmc up to 32 peripher al ios up to 32 peripher al ios pio clock apb interr upt controller data, enab le pin 31 pin 1 pin 0 data, enab le on-chip peripherals pio controller on-chip peripheral drivers control & command driver keyboard driver keyboard driver general purpose i/os external devices
221 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 221 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.4 product dependencies 23.4.1 pin multiplexing each pin is configurable, according to product definition as either a general-purpose i/o line only, or as an i/o line multiplexed with one or two peripheral i/os. as the multiplexing is hard- ware defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the pio controllers required by their application. when an i/o line is general-purpose only, i.e. not multiplexed with any peripheral i/o, programming of the pio controller regarding the assignment to a peripheral has no effect and only the pio con- troller can control how the pin is driven by the product. 23.4.2 external interrupt lines the interrupt signals fiq and irq0 to irqn are most generally multiplexed through the pio controllers. however, it is not necessary to assign the i/o line to the interrupt function as the pio controller has no effect on inputs and the interrupt lines (fiq or irqs) are used only as inputs. 23.4.3 power management the power management controller controls the pio controller clock in order to save power. writing any of the registers of the user interface does not require the pio controller clock to be enabled. this means that the configuration of the i/o lines does not require the pio controller clock to be enabled. however, when the clock is disabled, not all of t he features of the pio controller are available, including glitch filtering. note that the input change interrupt, interrupt modes on a programma- ble event and the read of the pin level require the clock to be validated. after a hardware reset, the pio clock is disabled by default. the user must configure the power management controller before any access to the input line information. 23.4.4 interrupt generation for interrupt handling, the pio controllers are considered as user peripherals. this means that the pio controller interrupt lines are connected among the interrupt sources 2 to 31. refer to the pio controller peripheral identifier in the produc t description to identify the interrupt sources dedicated to the pio controllers. the pio controller interrupt can be generated only if the pio controller clock is enabled.
222 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 222 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.5 functional description the pio controller features up to 32 fully-programmable i/o lines. most of the control logic asso- ciated to each i/o is represented in figure 23-3 . in this description each signal shown represents but one of up to 32 possible indexes. figure 23-3. i/o line control logic 1 0 1 0 1 0 1 0 dq dq dff 1 0 1 0 11 00 01 10 programmable glitch or debouncing filter pio_pdsr[0] pio_isr[0] pio_idr[0] pio_imr[0] pio_ier[0] pio interrupt (up to 32 possible inputs) pio_isr[31] pio_idr[31] pio_imr[31] pio_ier[31] pad pio_pudr[0] pio_pusr[0] pio_puer[0] pio_mddr[0] pio_mdsr[0] pio_mder[0] pio_codr[0] pio_odsr[0] pio_sodr[0] pio_pdr[0] pio_psr[0] pio_per[0] pio_abcdsr1[0] pio_odr[0] pio_osr[0] pio_oer[0] resynchronization stage peripheral a input peripheral d output enable peripheral a output enable event detector dff pio_ifdr[0] pio_ifsr[0] pio_ifer[0] pio clock clock divider pio_ifscsr[0] pio_ifscer[0] pio_ifscdr[0] pio_scdr slow clock peripheral b output enable peripheral c output enable 11 00 01 10 peripheral d output peripheral a output peripheral b output peripheral c output pio_abcdsr2[0] peripheral b input peripheral c input peripheral d input
223 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 223 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.5.1 pull-up and pull-down resistor control each i/o line is designed with an embedded pull-up resistor and an embedded pull-down resis- tor. the pull-up resistor can be enabled or disabl ed by writing respectively pio_puer (pull-up enable register) and pio_pudr (pull-up disable resistor). writing in these registers results in setting or clearing the corresponding bit in pio_pusr (pull-up status register). reading a 1 in pio_pusr means the pull-up is disabled and reading a 0 means the pull-up is enabled. the pull-down resistor can be enabled or disabled by writing respectively pio_ppder (pull-down enable register) and pio_ppddr (pull-down disable resistor). writing in these registers results in setting or clearing the corresponding bit in pio_ppdsr (pull-down status register). reading a 1 in pio_ppdsr means the pull-up is disabled and reading a 0 means the pull-down is enabled. enabling the pull-down resistor while the pull-up resistor is still enabled is not possible. in this case, the write of pio_ppder for the concerned i/o line is discarded. likewise, enabling the pull-up resistor while the pull-down resistor is still enabled is not possible. in this case, the write of pio_puer for the concerned i/o line is discarded. control of the pull-up resistor is possible regardless of the configuration of the i/o line. after reset, all of the pull-ups are enabled, i.e. pio_pusr resets at the value 0x0, and all the pull-downs are disabled, i.e. pio_ppdsr resets at the value 0xffffffff. 23.5.2 i/o line or peripheral function selection when a pin is multiplexed with one or two peripheral functions, the selection is controlled with the registers pio_per (pio enable register) and pio_pdr (pio disable register). the regis- ter pio_psr (pio status register) is the resu lt of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the pio controller. a value of 0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the pio_abcdsr1 and pio_abcdsr2 (abcd select regi sters). a value of 1 indicates the pin is controlled by the pio controller. if a pin is used as a general purpose i/o line (not multiplexed with an on-chip peripheral), pio_per and pio_pdr have no effect and pio_psr returns 1 for the corresponding bit. after reset, most generally, the i/o lines are controlled by the pio controller, i.e. pio_psr resets at 1. however, in some events, it is important that pio lines are controlled by the periph- eral (as in the case of memory chip select lines that must be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). thus, the reset value of pio_psr is defined at the product level, depending on the multiplexing of the device. 23.5.3 peripheral a or b or c or d selection the pio controller provides multiplexing of up to four peripheral functions on a single pin. the selection is performed by writ ing pio_abcdsr1 and pio_abcdsr2 (abcd select registers). for each pin: ? the corresponding bit at level 0 in pio_abcdsr1 and the corresponding bit at level 0 in pio_abcdsr2 means peripheral a is selected. ? the corresponding bit at level 1 in pio_abcdsr1 and the corresponding bit at level 0 in pio_abcdsr2 means peripheral b is selected. ? the corresponding bit at level 0 in pio_abcdsr1 and the corresponding bit at level 1 in pio_abcdsr2 means periph eral c is selected.
224 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 224 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? the corresponding bit at level 1 in pio_abcdsr1 and the corresponding bit at level 1 in pio_abcdsr2 means periph eral d is selected. note that multiplexing of peripheral lines a, b, c and d only affects the output line. the periph- eral input lines are always connected to the pin input. after reset, pio_abcdsr1 and pio_abcdsr2 are 0, thus indicating that all the pio lines are configured on peripheral a. however, peripheral a generally does not drive the pin as the pio controller resets in i/o line mode. writing in pio_abcdsr1 and pio_abcdsr2 man ages the multiplexing regardless of the con- figuration of the pin. however, assignment of a pin to a peripheral function requires a write in the peripheral selection registers (pio_abcdsr1 and pio_abcdsr2) in addition to a write in pio_pdr.
225 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 225 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.5.4 output control when the i/0 line is assigned to a peripheral func tion, i.e. the corresponding bit in pio_psr is at 0, the drive of the i/o line is controlled by the peripheral. peripheral a or b or c or d depending on the value in pio_abcdsr1 and pio_abcds r2 (abcd select registers) determines whether the pin is driven or not. when the i/o line is controlled by the pio controller, the pin can be configured to be driven. this is done by writing pio_oer (output enable register) and pio_odr (output disable register). the results of these write operations are detected in pio_osr (output status register). when a bit in this register is at 0, the corresponding i/o line is used as an input only. when the bit is at 1, the corresponding i/o line is driven by the pio controller. the level driven on an i/o line can be determined by writing in pio_sodr (set output data register) and pio_codr (cle ar output data register). these write operations respectively set and clear pio_odsr (output data status register), which represents the data driven on the i/o lines. writing in pio_oer and pio_odr manage s pio_osr whether the pin is configured to be controlled by the pio controller or assigned to a peripheral function. this enables configura- tion of the i/o line prior to setting it to be managed by the pio controller. similarly, writing in pio_sodr and pio_codr effects pio_odsr. this is important as it defines the first level driven on the i/o line. 23.5.5 synchronous data output clearing one (or more) pio line(s) and setting another one (or more) pio line(s) synchronously cannot be done by using pio_sodr and pio_codr registers. it requires two successive write operations into two different registers. to overcome this, the pio controller offers a direct con- trol of pio outputs by single write access to pio_odsr (output data status register).only bits unmasked by pio_owsr (output write status register) are written. the mask bits in pio_owsr are set by writing to pio_ower (output write enable register) and cleared by writing to pio_owdr (out put write disable register). after reset, the synchronous data output is disabled on all the i/o lines as pio_owsr resets at 0x0. 23.5.6 multi drive control (open drain) each i/o can be independently programmed in open drain by using the multi drive feature. this feature permits several drivers to be connected on the i/o line which is driven low only by each device. an external pull-up resistor (or enabling of the internal one) is generally required to guar- antee a high level on the line. the multi drive feature is controlled by pio_mder (multi-driver enable register) and pio_mddr (multi-driver disable register). the multi drive can be selected whether the i/o line is controlled by the pio controller or assigned to a peripheral function. pio_mdsr (multi-driver status register) indicates the pins that are configured to support external drivers. after reset, the multi drive feature is disabled on all pins, i.e. pio_mdsr resets at value 0x0. 23.5.7 output line timings figure 23-4 shows how the outputs are driven either by writing pio_sodr or pio_codr, or by directly writing pio_odsr. this last case is va lid only if the corresponding bit in pio_owsr is set. figure 23-4 also shows when the feedback in pio_pdsr is available.
226 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 226 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 23-4. output line timings 23.5.8 inputs the level on each i/o line can be read through pio_pdsr (pin data status register). this reg- ister indicates the level of the i/o lines regardless of their configuration, whether uniquely as an input or driven by the pio controller or driven by a peripheral. reading the i/o line levels requires the clock of the pio controller to be enabled, otherwise pio_pdsr reads the levels present on the i/o line at the time the clock was disabled. 23.5.9 input glitch and debouncing filters optional input glitch and debouncing filters are independently programmable on each i/o line. the glitch filter can filter a g litch with a duration of less than 1/2 master clock (mck) and the debouncing filter can filter a pulse of less than 1/2 period of a programmable divided slow clock. the selection between glitch filtering or debounce filtering is done by writing in the registers pio_ifscdr (pio input filter slow clock disable register) and pio_ifscer (pio input filter slow clock enable register). writing pio_if scdr and pio_ifscer respectively, sets and clears bits in pio_ifscsr. the current selection status can be checked by reading the register pio_ifscsr (input filter slow clock status register). ? if pio_ifscsr[i] = 0: the glitch filter can filter a glitch with a duration of less than 1/2 period of master clock. ? if pio_ifscsr[i] = 1: the debouncing filter can filter a pulse with a duration of less than 1/2 period of the programmable divided slow clock. for the debouncing filter, the period of the divided slow clock is performed by writing in the div field of the pio_scdr (slow clock divider register) tdiv_slclk = ((div+1)*2).tslow_clock when the glitch or debouncing filter is enabled, a glitch or pulse with a duration of less than 1/2 selected clock cycle (selected clock represents mck or divided slow clock depending on pio_ifscdr and pio_ifscer programming) is autom atically rejected, while a pulse with a duration of 1 selected clock (mck or divided slow clock) cycle or more is accepted. for pulse durations between 1/2 selected clock cycle and 1 selected clock cycle the pulse may or may 2 cycles apb access 2 cycles apb access mck write pio_sodr write pio_odsr at 1 pio_odsr pio_pdsr write pio_codr write pio_odsr at 0
227 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 227 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 not be taken into account, depending on the precise timing of its occurrence. thus for a pulse to be visible it must exceed 1 selected clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 selected clock cycle. the filters also introduce some la tencies, this is illustrated in figure 23-5 and figure 23-6 . the glitch filters are controlled by the regist er set: pio_ifer (input filter enable register), pio_ifdr (input filter disable register) and pio_ifsr (input filter status register). writing pio_ifer and pio_ifdr respectively sets and clears bits in pio_ifsr. this last register enables the glitch filt er on the i/o lines. when the glitch and/or debouncing filter is enabled, it does not modify the behavior of the inputs on the peripherals. it acts only on the value read in pio_pdsr and on the input change interrupt detection. the glitch and debouncing filters require that the pio controller clock is enabled. figure 23-5. input glitch filter timing figure 23-6. input debouncing filter timing mck pin level pio_pdsr if pio_ifsr = 0 pio_pdsr if pio_ifsr = 1 1 cycle 1 cycle 1 cycle up to 1.5 cycles 2 cycles up to 2.5 cycles up to 2 cycles 1 cycle 1 cycle pio_ifcsr = 0 divided slow clock pin level pio_pdsr if pio_ifsr = 0 pio_pdsr if pio_ifsr = 1 1 cycle tdiv_slclk up to 1.5 cycles tdiv_slclk 1 cycle tdiv_slclk up to 2 cycles tmck up to 2 cycles tmck up to 2 cycles tmck up to 2 cycles tmck up to 1.5 cycles tdiv_slclk pio_ifcsr = 1
228 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 228 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.5.10 input edge/level interrupt the pio controller can be programmed to generate an interrupt when it detects an edge or a level on an i/o line. the input edge/level interrupt is controlled by writing pio_ier (interrupt enable register) and pio_idr (interrupt disable register), which respectively enable and dis- able the input change interrupt by setting and clearing the corresponding bit in pio_imr (interrupt mask register). as input change detection is possible only by comparing two succes- sive samplings of the input of the i/o line, t he pio controller clock must be enabled. the input change interrupt is available, regardless of the configuration of the i/o line, i.e. configured as an input only, controlled by the pio controller or assigned to a peripheral function. by default, the interrupt can be generated at any time an edge is detected on the input. some additional interrupt modes can be enabled/disabled by writing in the pio_aimer (addi- tional interrupt modes enable register) and pio_aimdr (additional interrupt modes disable register). the current state of this sele ction can be read through the pio_aimmr (additional interrupt modes mask register) these additional modes are: ? rising edge detection ? falling edge detection ? low level detection ? high level detection in order to select an additional interrupt mode: ? the type of event detection (edge or level) must be selected by writing in the set of registers; pio_esr (edge select register) and pio_lsr (level select register) which enable respectively, the edge and level detection. the current status of this selection is accessible through the pio_elsr (edge/level status register). ? the polarity of the event detection (rising/fa lling edge or high/low level) must be selected by writing in the set of regist ers; pio_fellsr (falling edge /l ow level select register) and pio_rehlsr (rising edge/high level select register) which allow to select falling or rising edge (if edge is selected in the pio_elsr) edge or high or low level detection (if level is selected in the pio_elsr). the current status of this selection is accessible through the pio_frlhsr (fall/rise - low/high status register). when an input edge or level is detected on an i/o line, the corresponding bit in pio_isr (inter- rupt status register) is set. if the correspo nding bit in pio_imr is set, the pio controller interrupt line is asserted. the interrupt signals of the thirty-two channels are ored-wired together to generate a single interrupt signal to the advanced interrupt controller (aic). when the software reads pio_isr, all the interrupts are automatically cleared. this signifies that all the interrupts that are pending when pio_isr is read must be handled. when an interrupt is enabled on a level, the interrupt is generated as long as the interrupt source is not cleared, even if some read accesses in pio_isr are performed.
229 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 229 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 23-7. event detector on input lines (figure represents line 0) 23.5.10.1 example if generating an interrupt is required on the following: ? rising edge on pio line 0 ? falling edge on pio line 1 ? rising edge on pio line 2 ? low level on pio line 3 ? high level on pio line 4 ? high level on pio line 5 ? falling edge on pio line 6 ? rising edge on pio line 7 ? any edge on the other lines the configuration required is described below. 23.5.10.2 interrupt mode configuration all the interrupt sources are enabled by writing 32hffff_ffff in pio_ier. then the additional interrupt mode is enabled for line 0 to 7 by writing 32h0000_00ff in pio_aimer. 23.5.10.3 edge or level detection configuration lines 3, 4 and 5 are configured in level detection by writing 32h0000_0038 in pio_lsr. the other lines are configured in edge detection by default, if they have not been previously con- figured. otherwise, lines 0, 1, 2, 6 and 7 must be configured in edge detection by writing 32h0000_00c7 in pio_esr. 23.5.10.4 falling/rising edge or low/ high level detection configuration. lines 0, 2, 4, 5 and 7 are configured in rising edge or high level detection by writing 32h0000_00b5 in pio_rehlsr. event detector 0 1 0 1 1 0 0 1 edge detector falling edge detector rising edge detector pio_fellsr[0] pio_frlhsr[0] pio_rehlsr[0] low level detector high level detector pio_esr[0] pio_elsr[0] pio_lsr[0] pio_aimdr[0] pio_aimmr[0] pio_aimer[0] event detection on line 0 resynchronized input on line 0
230 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 230 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 the other lines are configured in falling edge or low level detection by default, if they have not been previously configured. othe rwise, lines 1, 3 and 6 must be configured in falling edge/low level detection by writing 32h0000_004a in pio_fellsr. figure 23-8. input change interrupt timings if there are no additional interrupt modes 23.5.11 i/o lines lock when an i/o line is controlled by a peripheral (particularly the pulse width modulation controller pwm), it can become locked by the action of th is peripheral via an input of the pio controller. when an i/o line is locked, the write of the corresponding bit in the registers pio_per, pio_pdr, pio_mder, pio_mddr, p io_pudr, pio_puer, pio_abcdsr1 and pio_abcdsr2 is discarded in order to lock its configuration. the user can know at anytime which i/o line is locked by reading the pio lock status register pio_locksr. once an i/o line is locked, the only way to unlock it is to apply a hardware reset to the pio controller. 23.5.12 programmable i/o delays the pio interface consists of a series of signal s driven by peripherals or directly by software. the simultaneous switching outputs on these busses may lead to a peak of current in the inter- nal and external power supply lines. in order to reduce the current peak in such cases, additional propagation delays can be adjusted independently for pad buffers by means of configuration registers, pio_delay. the additional programmable delays for each supporting range from 0 to 4 ns (worst case pvt). the delay can differ between i/os supporting this feature. delay can be modified per pro- gramming for each i/o. the minimal additional delay that can be programmed on a pad supporting this feature is 1/16 of the maximum programmable delay. only pads pa[15:11], and pa[20:18] can be configured. when programming 0x0 in fields, no delay is added (reset value) and the propagation delay of the pad buffers is the inherent delay of the pad buffer. when programming 0xf in fields, the propagation delay of the corresponding pad is maximal. mck pin level read pio_isr apb access pio_isr apb access
231 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 231 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 23-9. programmable i/o delays 23.5.13 programmable i/o drive it is possible to configure the i/o drive for pads pa[31:0], pb[18:0], pc[31:0]. for any details, refer to the product electrical characteristics. 23.5.14 programmable schmitt trigger it is possible to configure each input for the schmitt trigger. by default the schmitt trigger is active. disabling the schmitt trigger is requested when using the qtouch ? library. 23.5.15 write protection registers to prevent any single software error that may corrupt pio behavior, certain address spaces can be write-protected by setting the wpen bit in the pio write protect mode register (pio_wpmr). if a write access to the protecte d registers is detected, then the wpvs flag in the pio write pro- tect status register (pio_wpsr) is set and the field wpvsrc indicates in which register the write access has been attempted. the wpvs flag is reset by writing the pio write protect mode register (pio_wpmr) with the appropriate access key, wpkey. the protected registers are: ? pio enable register on page 237 ? pio disable register on page 237 ? pio output enable register on page 238 ? pio output disable register on page 239 ? pio input filter enable register on page 240 ? pio input filter disable register on page 240 ? pio multi-driver enable register on page 245 ? pio multi-driver disable register on page 246 ? pio pull up disable register on page 247 delay1 programmable delay line pio paout[0] pain[0] delay2 programmable delay line delayx programmable delay line paout[1] pain[1] paout[2] pain[2]
232 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 232 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? pio pull up enable register on page 247 ? pio peripheral abcd select register 1 on page 249 ? pio peripheral abcd select register 2 on page 250 ? pio output write enable register on page 255 ? pio output write disable register on page 255 ? pio pad pull down disable register on page 253 ? pio pad pull down status register on page 254
233 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 233 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.6 i/o lines programming example the programing example as shown in table 23-1 below is used to obtain the following configuration. ? 4-bit output port on i/o lines 0 to 3, (should be written in a single write operation), open-drain, with pull-up resistor ? four output signals on i/o lines 4 to 7 (to drive leds for example), driven high and low, no pull-up resistor, no pull-down resistor ? four input signals on i/o lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch filters and input change interrupts ? four input signals on i/o line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter ? i/o lines 16 to 19 assigned to peripheral a functions with pull-up resistor ? i/o lines 20 to 23 assigned to peripheral b functions with pull-down resistor ? i/o line 24 to 27 assigned to peripheral c with input change interrupt, no pull-up resistor and no pull-down resistor ? i/o line 28 to 31 assigned to peripheral d, no pull-up resistor and no pull-down resistor table 23-1. programming example register value to be written pio_per 0x0000_ffff pio_pdr 0xffff_0000 pio_oer 0x0000_00ff pio_odr 0xffff_ff00 pio_ifer 0x0000_0f00 pio_ifdr 0xffff_f0ff pio_sodr 0x0000_0000 pio_codr 0x0fff_ffff pio_ier 0x0f00_0f00 pio_idr 0xf0ff_f0ff pio_mder 0x0000_000f pio_mddr 0xffff_fff0 pio_pudr 0xfff0_00f0 pio_puer 0x000f_ff0f pio_ppddr 0xff0f_ffff pio_ppder 0x00f0_0000 pio_abcdsr1 0xf0f0_0000 pio_abcdsr2 0xff00_0000 pio_ower 0x0000_000f pio_owdr 0x0fff_ fff0
234 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 234 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7 parallel input/output cont roller (pio) user interface each i/o line controlled by the pio controller is associated with a bit in each of the pio control- ler user interface registers. each register is 32 bits wide. if a parallel i/o line is not defined, writing to the corresponding bits has no effect. undefined bits read zero. if the i/o line is not mul- tiplexed with any peripheral, the i/o line is controlled by the pio controller and pio_psr returns 1 systematically. table 23-2. register mapping offset register name access reset 0x0000 pio enable register pio_per write-only C 0x0004 pio disable register pio_pdr write-only C 0x0008 pio status register pio_psr read-only (1) 0x000c reserved 0x0010 output enable register pio_oer write-only C 0x0014 output disable register pio_odr write-only C 0x0018 output status regist er pio_osr read-only 0x0000 0000 0x001c reserved 0x0020 glitch input filter enab le register pio_ifer write-only C 0x0024 glitch input filter disab le register pio_ifdr write-only C 0x0028 glitch input filt er status register pio_ ifsr read-only 0x0000 0000 0x002c reserved 0x0030 set output data r egister pio_sodr write-only C 0x0034 clear output data register pio_codr write-only 0x0038 output data status register pio_odsr read-only or (2) read-write C 0x003c pin data status register pio_pdsr read-only (3) 0x0040 interrupt enable register pio_ier write-only C 0x0044 interrupt disable register pio_idr write-only C 0x0048 interrupt mask register pio_imr read-only 0x00000000 0x004c interrupt status register (4) pio_isr read-only 0x00000000 0x0050 multi-driver enable register pio_mder write-only C 0x0054 multi-driver disable register pio_mddr write-only C 0x0058 multi-driver status r egister pio_mdsr read-only 0x00000000 0x005c reserved 0x0060 pull-up disable register pio_pudr write-only C 0x0064 pull-up enable register pio_puer write-only C 0x0068 pad pull-up status register pio_pusr read-only (1) 0x006c reserved
235 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 235 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 0x0070 peripheral select register 1 pio_abcdsr1 read-write 0x00000000 0x0074 peripheral select register 2 pio_abcdsr2 read-write 0x00000000 0x0078 to 0x007c reserved 0x0080 input filter slow clock disa ble register pio_ifscdr write-only C 0x0084 input filter slow clock enable register pio_ifscer write-only C 0x0088 input filter slow clock status register pio_ifscsr read-only 0x00000000 0x008c slow clock divider debouncing register pio_scdr read-write 0x00000000 0x0090 pad pull-down disable register pio_ppddr write-only C 0x0094 pad pull-down enable register pio_ppder write-only C 0x0098 pad pull-down status register pio_ppdsr read-only (1) 0x009c reserved 0x00a0 output write enab le pio_ower write-only C 0x00a4 output write disable pio_owdr write-only C 0x00a8 output write status register pio_owsr read-only 0x00000000 0x00ac reserved 0x00b0 additional interrupt modes enable register pio_aimer write-only C 0x00b4 additional interrupt modes disables register pio_aimdr write-only C 0x00b8 additional interrupt modes mask register pio_aimmr read-only 0x00000000 0x00bc reserved 0x00c0 edge select register pio_esr write-only C 0x00c4 level select register pio_lsr write-only C 0x00c8 edge/level status regi ster pio_elsr read-only 0x00000000 0x00cc reserved 0x00d0 falling edge/low level select register pio_fellsr write-only C 0x00d4 rising edge/ high level select register pio_rehlsr write-only C 0x00d8 fall/rise - low/high status register pio_frlhsr read-only 0x00000000 0x00dc reserved 0x00e0 lock status pio_locksr read-only 0x00000000 0x00e4 write protect mode r egister pio_wpmr read-write 0x0 0x00e8 write protect status register pio_wpsr read-only 0x0 0x00ec to 0x00f8 reserved 0x0100 schmitt trigger register pio_schmitt read-write 0x00000000 0x0104- 0x010c reserved 0x0110 io delay register pio_delayr read-write 0x00000000 table 23-2. register mapping (continued) offset register name access reset
236 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 236 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 notes: 1. reset value depends on the product implementation. 2. pio_odsr is read-only or read/write depending on pio_owsr i/o lines. 3. reset value of pio_pdsr depends on the level of the i/o line s. reading the i/o line levels requires the clock of the pio controller to be enabled, ot herwise pio_pdsr reads the levels present on the i/o line at the time the clock was disabled. 4. pio_isr is reset at 0x0. however, the first read of the register may read a different value as input changes may have occurred. note: if an offset is not listed in the table it must be considered as reserved. 0x0114 i/o drive register 1 pio_driver1 read-write 0x00000000 0x0118 i/o drive register 2 pio_driver2 read-write 0x00000000 0x011c reserved table 23-2. register mapping (continued) offset register name access reset
237 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 237 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.1 pio enable register name: pio_per address: 0xfffff400 (pioa), 0xfffff600 (piob), 0xfffff800 (pioc), 0xfffffa00 (piod) access: write-only this register can only be written if the wpen bit is cleared in pio write protect mode register . ? p0-p31: pio enable 0: no effect. 1: enables the pio to control the corresponding pin (disables peripheral control of the pin). 23.7.2 pio disable register name: pio_pdr address: 0xfffff404 (pioa), 0xfffff604 (piob), 0xfffff804 (pioc), 0xfffffa04 (piod) access: write-only this register can only be written if the wpen bit is cleared in pio write protect mode register . ? p0-p31: pio disable 0: no effect. 1: disables the pio from controllin g the corresponding pi n (enables peripheral control of the pin). 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
238 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 238 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.3 pio status register name: pio_psr address: 0xfffff408 (pioa), 0xfffff608 (piob), 0xfffff808 (pioc), 0xfffffa08 (piod) access: read-only ? p0-p31: pio status 0: pio is inactive on the corresponding i/o line (peripheral is active). 1: pio is active on the corresponding i/o line (peripheral is inactive). 23.7.4 pio output enable register name: pio_oer address: 0xfffff410 (pioa), 0xfffff610 (piob), 0xfffff810 (pioc), 0xfffffa10 (piod) access: write-only this register can only be written if the wpen bit is cleared in pio write protect mode register . ? p0-p31: output enable 0: no effect. 1: enables the output on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
239 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 239 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.5 pio output disable register name: pio_odr address: 0xfffff414 (pioa), 0xfffff614 (piob), 0xfffff814 (pioc), 0xfffffa14 (piod) access: write-only this register can only be written if the wpen bit is cleared in pio write protect mode register . ? p0-p31: output disable 0: no effect. 1: disables the output on the i/o line. 23.7.6 pio output status register name: pio_osr address: 0xfffff418 (pioa), 0xfffff618 (piob), 0xfffff818 (pioc), 0xfffffa18 (piod) access: read-only ? p0-p31: output status 0: the i/o line is a pure input. 1: the i/o line is enabled in output. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
240 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 240 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.7 pio input filter enable register name: pio_ifer address: 0xfffff420 (pioa), 0xfffff620 (piob), 0xfffff820 (pioc), 0xfffffa20 (piod) access: write-only this register can only be written if the wpen bit is cleared in pio write protect mode register . ? p0-p31: input filter enable 0: no effect. 1: enables the input glitch filter on the i/o line. 23.7.8 pio input filter disable register name: pio_ifdr address: 0xfffff424 (pioa), 0xfffff624 (piob), 0xfffff824 (pioc), 0xfffffa24 (piod) access: write-only this register can only be written if the wpen bit is cleared in pio write protect mode register . ? p0-p31: input filter disable 0: no effect. 1: disables the input glitch filter on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
241 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 241 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.9 pio input filter status register name: pio_ifsr address: 0xfffff428 (pioa), 0xfffff628 (piob), 0xfffff828 (pioc), 0xfffffa28 (piod) access: read-only ? p0-p31: input filer status 0: the input glitch filter is disabled on the i/o line. 1: the input glitch filter is enabled on the i/o line. 23.7.10 pio set output data register name: pio_sodr address: 0xfffff430 (pioa), 0xfffff630 (piob), 0xfffff830 (pioc), 0xfffffa30 (piod) access: write-only ? p0-p31: set output data 0: no effect. 1: sets the data to be driven on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
242 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 242 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.11 pio clear output data register name: pio_codr address: 0xfffff434 (pioa), 0xfffff634 (piob), 0xfffff834 (pioc), 0xfffffa34 (piod) access: write-only ? p0-p31: clear output data 0: no effect. 1: clears the data to be driven on the i/o line. 23.7.12 pio output data status register name: pio_odsr address: 0xfffff438 (pioa), 0xfffff638 (piob), 0xfffff838 (pioc), 0xfffffa38 (piod) access: read-only or read-write ? p0-p31: output data status 0: the data to be driven on the i/o line is 0. 1: the data to be driven on the i/o line is 1. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
243 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 243 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.13 pio pin data status register name: pio_pdsr address: 0xfffff43c (pioa), 0xfffff63c (piob), 0xfffff83c (pioc), 0xfffffa3c (piod) access: read-only ? p0-p31: output data status 0: the i/o line is at level 0. 1: the i/o line is at level 1. 23.7.14 pio interrupt enable register name: pio_ier address: 0xfffff440 (pioa), 0xfffff640 (piob), 0xfffff840 (pioc), 0xfffffa40 (piod) access: write-only ? p0-p31: input change interrupt enable 0: no effect. 1: enables the input change interrupt on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
244 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 244 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.15 pio interrupt disable register name: pio_idr address: 0xfffff444 (pioa), 0xfffff644 (piob), 0xfffff844 (pioc), 0xfffffa44 (piod) access: write-only ? p0-p31: input change interrupt disable 0: no effect. 1: disables the input change interrupt on the i/o line. 23.7.16 pio interrupt mask register name: pio_imr address: 0xfffff448 (pioa), 0xfffff648 (piob), 0xfffff848 (pioc), 0xfffffa48 (piod) access: read-only ? p0-p31: input change interrupt mask 0: input change interrupt is disabled on the i/o line. 1: input change interrupt is enabled on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
245 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 245 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.17 pio interrupt status register name: pio_isr address: 0xfffff44c (pioa), 0xfffff64c (piob), 0xfffff84c (pioc), 0xfffffa4c (piod) access: read-only ? p0-p31: input change interrupt status 0: no input change has been detected on the i/o line since pio_isr was last read or since reset. 1: at least one input change has been detected on the i/o line since pio_isr was last read or since reset. 23.7.18 pio multi-driver enable register name: pio_mder address: 0xfffff450 (pioa), 0xfffff650 (piob), 0xfffff850 (pioc), 0xfffffa50 (piod) access: write-only this register can only be written if the wpen bit is cleared in pio write protect mode register . ? p0-p31: multi drive enable. 0: no effect. 1: enables multi dr ive on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
246 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 246 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.19 pio multi-driver disable register name: pio_mddr address: 0xfffff454 (pioa), 0xfffff654 (piob), 0xfffff854 (pioc), 0xfffffa54 (piod) access: write-only this register can only be written if the wpen bit is cleared in pio write protect mode register . ? p0-p31: multi drive disable. 0: no effect. 1: disables multi drive on the i/o line. 23.7.20 pio multi-driver status register name: pio_mdsr address: 0xfffff458 (pioa), 0xfffff658 (piob), 0xfffff858 (pioc), 0xfffffa58 (piod) access: read-only ? p0-p31: multi drive status. 0: the multi drive is disabled on the i/o line. the pin is driven at high and low level. 1: the multi drive is enabled on the i/o line. the pin is driven at low level only. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
247 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 247 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.21 pio pull up disable register name: pio_pudr address: 0xfffff460 (pioa), 0xfffff660 (piob), 0xfffff860 (pioc), 0xfffffa60 (piod) access: write-only this register can only be written if the wpen bit is cleared in pio write protect mode register . ? p0-p31: pull up disable. 0: no effect. 1: disables the pull up resistor on the i/o line. 23.7.22 pio pull up enable register name: pio_puer address: 0xfffff464 (pioa), 0xfffff664 (piob), 0xfffff864 (pioc), 0xfffffa64 (piod) access: write-only this register can only be written if the wpen bit is cleared in pio write protect mode register . ? p0-p31: pull up enable. 0: no effect. 1: enables the pull up resistor on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
248 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 248 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.23 pio pull up status register name: pio_pusr address: 0xfffff468 (pioa), 0xfffff668 (piob), 0xfffff868 (pioc), 0xfffffa68 (piod) access: read-only ? p0-p31: pull up status. 0: pull up resistor is enabled on the i/o line. 1: pull up resistor is disabled on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
249 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 249 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.24 pio peripheral a bcd select register 1 name: pio_abcdsr1 access: read-write this register can only be written if the wpen bit is cleared in pio write protect mode register . ? p0-p31: peripheral select. if the same bit is set to 0 in pio_abcdsr2: 0: assigns the i/o line to the peripheral a function. 1: assigns the i/o line to the peripheral b function. if the same bit is set to 1 in pio_abcdsr2: 0: assigns the i/o line to the peripheral c function. 1: assigns the i/o line to the peripheral d function. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
250 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 250 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.25 pio peripheral a bcd select register 2 name: pio_abcdsr2 access: read-write this register can only be written if the wpen bit is cleared in pio write protect mode register . ? p0-p31: peripheral select. if the same bit is set to 0 in pio_abcdsr1: 0: assigns the i/o line to the peripheral a function. 1: assigns the i/o line to the peripheral c function. if the same bit is set to 1 in pio_abcdsr1: 0: assigns the i/o line to the peripheral b function. 1: assigns the i/o line to the peripheral d function. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
251 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 251 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.26 pio input filter slow clock disable register name: pio_ifscdr address: 0xfffff480 (pioa), 0xfffff680 (piob), 0xfffff880 (pioc), 0xfffffa80 (piod) access: write-only ? p0-p31: pio clock glitch filtering select. 0: no effect. 1: the glitch filter is able to f ilter glitches with a duration < tmck/2. 23.7.27 pio input filter slow clock enable register name: pio_ifscer address: 0xfffff484 (pioa), 0xfffff684 (piob), 0xfffff884 (pioc), 0xfffffa84 (piod) access: write-only ? p0-p31: debouncing filtering select. 0: no effect. 1: the debouncing filter is able to filter pulses with a duration < tdiv_slclk/2. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
252 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 252 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.28 pio input filter slow clock status register name: pio_ifscsr address: 0xfffff488 (pioa), 0xfffff688 (piob), 0xfffff888 (pioc), 0xfffffa88 (piod) access: read-only ? p0-p31: glitch or debouncing filter selection status 0: the glitch filter is able to f ilter glitches with a duration < tmck2. 1: the debouncing filter is able to filter pulses with a duration < tdiv_slclk/2. 23.7.29 pio slow clock divider debouncing register name: pio_scdr address: 0xfffff48c (pioa), 0xfffff68c (piob), 0xfffff88c (pioc), 0xfffffa8c (piod) access: read-write ? divx: slow clock divider selection for debouncing tdiv_slclk = 2*(div+1)*tslow_clock. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CC d i v 76543210 div
253 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 253 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.30 pio pad pull down disable register name: pio_ppddr address: 0xfffff490 (pioa), 0xfffff690 (piob), 0xfffff890 (pioc), 0xfffffa90 (piod) access: write-only this register can only be written if the wpen bit is cleared in pio write protect mode register . ? p0-p31: pull down disable. 0: no effect. 1: disables the pull down resistor on the i/o line. 23.7.31 pio pad pull down enable register name: pio_ppder address: 0xfffff494 (pioa), 0xfffff694 (piob), 0xfffff894 (pioc), 0xfffffa94 (piod) access: write-only this register can only be written if the wpen bit is cleared in pio write protect mode register . ? p0-p31: pull down enable. 0: no effect. 1: enables the pull down resistor on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
254 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 254 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.32 pio pad pull down status register name: pio_ppdsr address: 0xfffff498 (pioa), 0xfffff698 (piob), 0xfffff898 (pioc), 0xfffffa98 (piod) access: read-only this register can only be written if the wpen bit is cleared in pio write protect mode register . ? p0-p31: pull down status. 0: pull down resistor is enabled on the i/o line. 1: pull down resistor is disabled on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
255 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 255 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.33 pio output write enable register name: pio_ower address: 0xfffff4a0 (pioa), 0xfffff6a0 (piob), 0xfffff8a0 (pioc), 0xfffffaa0 (piod) access: write-only this register can only be written if the wpen bit is cleared in pio write protect mode register . ? p0-p31: output write enable. 0: no effect. 1: enables writing pio_odsr for the i/o line. 23.7.34 pio output write disable register name: pio_owdr address: 0xfffff4a4 (pioa), 0xfffff6a4 (piob), 0xfffff8a4 (pioc), 0xfffffaa4 (piod) access: write-only this register can only be written if the wpen bit is cleared in pio write protect mode register . ? p0-p31: output write disable. 0: no effect. 1: disables writing pio_ odsr for the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
256 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 256 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.35 pio output write status register name: pio_owsr address: 0xfffff4a8 (pioa), 0xfffff6a8 (piob), 0xfffff8a8 (pioc), 0xfffffaa8 (piod) access: read-only ? p0-p31: output write status. 0: writing pio_odsr does not affect the i/o line. 1: writing pio_odsr affects the i/o line. 23.7.36 pio additional interrupt modes enable register name: pio_aimer address: 0xfffff4b0 (pioa), 0xfffff6b0 (piob), 0xfffff8b0 (pioc), 0xfffffab0 (piod) access: write-only ? p0-p31: additional interrupt modes enable. 0: no effect. 1: the interrupt source is the event described in pio_elsr and pio_frlhsr. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
257 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 257 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.37 pio additional interrupt modes disable register name: pio_aimdr address: 0xfffff4b4 (pioa), 0xfffff6b4 (piob), 0xfffff8b4 (pioc), 0xfffffab4 (piod) access: write-only ? p0-p31: additional interrupt modes disable. 0: no effect. 1: the interrupt mode is set to the default interrupt mode (both edge detection). 23.7.38 pio additional interrupt modes mask register name: pio_aimmr address: 0xfffff4b8 (pioa), 0xfffff6b8 (piob), 0xfffff8b8 (pioc), 0xfffffab8 (piod) access: read-only ? p0-p31: peripheral cd status. 0: the interrupt source is a both edge detection event 1: the interrupt source is described by the registers pio_elsr and pio_frlhsr 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
258 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 258 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.39 pio edge select register name: pio_esr address: 0xfffff4c0 (pioa), 0xfffff6c0 (piob), 0xfffff8c0 (pioc), 0xfffffac0 (piod) access: write-only ? p0-p31: edge in terrupt selection. 0: no effect. 1: the interrupt source is an edge detection event. 23.7.40 pio level select register name: pio_lsr address: 0xfffff4c4 (pioa), 0xfffff6c4 (piob), 0xfffff8c4 (pioc), 0xfffffac4 (piod) access: write-only ? p0-p31: level interrupt selection. 0: no effect. 1: the interrupt source is a level detection event. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
259 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 259 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.41 pio edge/level status register name: pio_elsr address: 0xfffff4c8 (pioa), 0xfffff6c8 (piob), 0xfffff8c8 (pioc), 0xfffffac8 (piod) access: read-only ? p0-p31: edge/level interrupt source selection. 0: the interrupt source is an edge detection event. 1: the interrupt source is a level detection event. 23.7.42 pio falling edge/low level select register name: pio_fellsr address: 0xfffff4d0 (pioa), 0xfffff6d0 (piob), 0xfffff8d0 (pioc), 0xfffffad0 (piod) access: write-only ? p0-p31: falling edge/low level interrupt selection. 0: no effect. 1: the interrupt source is set to a falling edge detec tion or low level detection ev ent, depending on pio_elsr. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
260 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 260 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.43 pio rising edge/high level select register name: pio_rehlsr address: 0xfffff4d4 (pioa), 0xfffff6d4 (piob), 0xfffff8d4 (pioc), 0xfffffad4 (piod) access: write-only ? p0-p31: rising edge /high level interrupt selection. 0: no effect. 1: the interrupt source is set to a rising edge detecti on or high level detection event, depending on pio_elsr. 23.7.44 pio fall/rise - low/high status register name: pio_frlhsr address: 0xfffff4d8 (pioa), 0xfffff6d8 (piob), 0xfffff8d8 (pioc), 0xfffffad8 (piod) access: read-only ? p0-p31: edge /level interrupt source selection. 0: the interrupt sour ce is a falling edge detection (i f pio_elsr = 0) or low level de tection event (if pio_elsr = 1). 1: the interrupt source is a rising edge detection (if pio_elsr = 0) or high level detection event (if pio_elsr = 1). 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
261 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 261 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.45 pio lock status register name: pio_locksr address: 0xfffff4e0 (pioa), 0xfffff6e0 (piob), 0xfffff8e0 (pioc), 0xfffffae0 (piod) access: read-only ? p0-p31: lock status. 0: the i/o line is not locked. 1: the i/o line is locked. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
262 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 262 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.46 pio write protect mode register name: pio_wpmr address: 0xfffff4e4 (pioa), 0xfffff6e4 (piob), 0xfffff8e4 (pioc), 0xfffffae4 (piod) access: read-write reset: see table 23-2 for more information on write protection registers, refer to section 23.7 parallel input/output controller (pio) user interface . ? wpen: write protect enable 0: disables the write protect if wpkey corresponds to 0x50494f (pio in ascii). 1: enables the write protec t if wpkey correspond s to 0x50494f (pio in ascii). protects the registers: pio enable register on page 237 pio disable register on page 237 pio output enable register on page 238 pio output disable register on page 239 pio input filter enable register on page 240 pio input filter disable register on page 240 pio multi-driver enable register on page 245 pio multi-driver disable register on page 246 pio pull up disable register on page 247 pio pull up enable register on page 247 pio peripheral abcd select register 1 on page 249 pio peripheral abcd select register 2 on page 250 pio output write enable register on page 255 pio output write disable register on page 255 pio pad pull down disable register on page 253 pio pad pull down status register on page 254 ? wpkey: write protect key should be written at value 0x50494f (pio in ascii). writing any other value in this field aborts the write operation of the wpen bit. always reads as 0. 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 CCCCCCC wpen
263 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 263 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.47 pio write protect status register name: pio_wpsr address: 0xfffff4e8 (pioa), 0xfffff6e8 (piob), 0xfffff8e8 (pioc), 0xfffffae8 (piod) access: read-only reset: see table 23-2 ? wpvs: write protect violation status 0: no write protect violation has occurred si nce the last read of the pio_wpsr register. 1: a write protect violation has occurred since the last read of the pio_wpsr register. if this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field wpvsrc. ? wpvsrc: write protect violation source when wpvs is active, this field indicates the write-protected register (t hrough address offset or code) in which a write access has been attempted. note: reading pio_wpsr automatically clears all fields. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 wpvsrc 15 14 13 12 11 10 9 8 wpvsrc 76543210 CCCCCCC wpvs
264 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 264 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.48 pio schmitt trigger register name: pio_schmitt address: 0xfffff500 (pioa), 0xfffff700 (piob), 0xfffff900 (pioc), 0xfffffb00 (piod) access: read-write reset: see figure 23-2 ? schmittx [x=0..31]: 0: schmitt trigger is enabled. 1= schmitt trigger is disabled. 31 30 29 28 27 26 25 24 schmitt31 schmitt30 schmitt29 schmitt28 schmitt27 schmitt26 schmitt25 schmitt24 23 22 21 20 19 18 17 16 schmitt23 schmitt22 schmitt21 schmitt20 schmitt19 schmitt18 schmitt17 schmitt16 15 14 13 12 11 10 9 8 schmitt15 schmitt14 schmitt13 schmitt12 schmitt11 schmitt10 schmitt9 schmitt8 76543210 schmitt7 schmitt6 schmitt5 schmitt4 schmitt3 schmitt2 schmitt1 schmitt0
265 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 265 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.49 pio i/o delay register name: pio_delayr address: 0xfffff510 (pioa), 0xfffff710 (piob), 0xfffff910 (pioc), 0xfffffb10 (piod) access: read-write reset: see figure 23-2 ? delay x: gives the number of elements in the delay line associated to pad x. 31 30 29 28 27 26 25 24 delay7 delay6 23 22 21 20 19 18 17 16 delay5 delay4 15 14 13 12 11 10 9 8 delay3 delay2 76543210 delay1 delay0
266 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 266 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.50 pio i/o drive register 1 name: pio_driver1 address: 0xfffff514 (pioa), 0xfffff714 (piob), 0xfffff914 (pioc), 0xfffffb14 (piod) access: read-write reset: 0x0 ? linex [x=0..15]: drive of pio line x 31 30 29 28 27 26 25 24 line15 line14 line13 line12 23 22 21 20 19 18 17 16 line11 line10 line9 line8 15 14 13 12 11 10 9 8 line7 line6 line5 line4 76543210 line3 line2 line1 line0 value name description 0 hi_drive high drive 1 me_drive medium drive 2 lo_drive low drive 3- r e s e r v e d
267 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 267 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 23.7.51 pio i/o drive register 2 name: pio_driver2 address: 0xfffff518 (pioa), 0xfffff718 (piob), 0xfffff918 (pioc), 0xfffffb18 (piod) access: read-write reset: 0x0 ? linex [x=16..31]: drive of pio line x 31 30 29 28 27 26 25 24 line31 line30 line29 line28 23 22 21 20 19 18 17 16 line27 line26 line25 line24 15 14 13 12 11 10 9 8 line23 line22 line21 line20 76543210 line19 line18 line17 line16 value name description 0 hi_drive high drive 1 me_drive medium drive 2 lo_drive low drive 3- r e s e r v e d
268 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 268 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12
269 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 24. debug unit (dbgu) 24.1 description the debug unit provides a single entry point from the processor for access to all the debug capabilities of atmels arm-based systems. the debug unit features a two-pin uart that can be used for several debug and trace purposes and offers an ideal medium for in-situ programming solutions and debug monitor communica- tions. the debug unit two-pin uart can be used stand-alone for general purpose serial communication. moreover, the association with dma controller channels permits packet han- dling for these tasks with processo r time reduced to a minimum. the debug unit also makes the debug communication channel (dcc) signals provided by the in-circuit emulator of the arm processor visible to the software. these signals indicate the sta- tus of the dcc read and write registers and gener ate an interrup t to the arm processor, making possible the handling of the dcc under interrupt control. chip identifier registers permit recognition of t he device and its revision. these registers inform as to the sizes and types of the on-chip memori es, as well as the set of embedded peripherals. finally, the debug unit features a force ntrst capability that enables the software to decide whether to prevent access to the system via th e in-circuit emulator. th is permits protection of the code, stored in rom. 24.2 embedded characteristics ? system peripheral to facilitate debug of atmel ? arm ? -based systems ? composed of four functions Ctwo-pin uart C debug communication channel (dcc) support C chip id registers C ice access prevention ?two-pin uart C implemented features are usart compatible C independent receiver and transmitter with a common programmable baud rate generator C even, odd, mark or space parity generation C parity, framing and overrun error detection C automatic echo, local loopback and remote loopback channel modes C interrupt generation C support for two dma channels with connection to receiver and transmitter ? debug communication channel support C offers visibility of commrx and co mmtx signals from the arm processor C interrupt generation ? chip id registers C identification of the device revision, sizes of the embedded memories, set of peripherals
270 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? ice access prevention C enables software to prevent system access through the arm processors ice C prevention is made by asserting the ntrst line of the arm processors ice
271 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 24.3 block diagram figure 24-1. debug unit functional block diagram figure 24-2. debug unit application example (peripher al) dma controller baud rate gener ator dcc handler ice access handler tr ansmit receive chip id interr upt control peripher al bridge p ar allel input/ output dtxd drxd power management controller arm processor force_ntr st commrx commtx mck ntrst power-on reset dbgu_irq apb debu g unit table 24-1. debug unit pin description pin name description type drxd debug receive data input dtxd debug transmit data output debug unit rs232 drivers programming tool trace console debug console boot program debug monitor trace manager
272 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 24.4 product dependencies 24.4.1 i/o lines depending on product integration, the debug unit pins may be multiplexed with pio lines. in this case, the programmer must first configure the corresponding pio controller to enable i/o lines operations of the debug unit. 24.4.2 power management depending on product integration, the debug unit clock may be controllable through the power management controller. in this case, the programmer must first configure the pmc to enable the debug unit clock. usually, the peripheral identifier used for this purpose is 1. 24.4.3 interrupt source depending on product integration, the debug unit interrupt line is connected to one of the inter- rupt sources of the advanced interrupt controller. interrupt handling requires programming of the aic before configuring the de bug unit. usually, the debug unit interrupt line connects to the interrupt source 1 of the aic, which may be shared with the real-time clock, the system timer interrupt lines and other system peripheral interrupts, as shown in figure 24-1 . this sharing requires the programmer to determine the source of the interrupt when the source 1 is triggered. 24.5 uart operations the debug unit operates as a uart, (asynchro nous mode only) and supports only 8-bit charac- ter handling (with parity). it has no clock pin. the debug unit's uart is made up of a receiver and a transmitter that operate independently, and a common baud rate generator. receiver timeout and transmitter time guard are not imple- mented. however, all the implemented features are compatible with those of a standard usart. 24.5.1 baud rate generator the baud rate generator provides the bit period clock named baud rate clock to both the receiver and the transmitter. the baud rate clock is the master clock divided by 16 times the value (cd) written in dbgu_brgr (baud rate generator register). if dbgu_brgr is set to 0, the baud rate clock is disabled and the debug unit's uart remains inactive. the maximum allowable baud rate is master clock divided by 16. the minimum allow able baud rate is master clock divided by (16 x 65536). table 24-2. i/o lines instance signal i/o line peripheral dbgu drxd pa9 a dbgu dtxd pa10 a baud rate mck 16 cd ---------------------- =
273 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 24-3. baud rate generator 24.5.2 receiver 24.5.2.1 receiver rese t, enable and disable after device reset, the debug unit receiver is disabled and must be enabled before being used. the receiver can be enabled by writing the control register dbgu_cr with the bit rxen at 1. at this command, the receiver starts looking for a start bit. the programmer can disable the receiver by writ ing dbgu_cr with the bit rxdis at 1. if the receiver is waiting for a start bit, it is immedi ately stopped. however, if the receiver has already detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its operation. the programmer can also put the receiver in it s reset state by writing dbgu_cr with the bit rstrx at 1. in doing so, the receiver immediat ely stops its current operations and is disabled, whatever its current state. if rstrx is applied wh en data is being processed, this data is lost. 24.5.2.2 start detection and data sampling the debug unit only supports asynchronous operations, and this affects only its receiver. the debug unit receiver detects the start of a rece ived character by sampling the drxd signal until it detects a valid start bit. a low level (space) on drxd is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. a space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. when a valid start bit has been detected, the receiver samples the drxd at the theoretical mid- point of each bit. it is assumed that each bit last s 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. the first sampling point is therefore 24 cycles (1.5 -bit periods) after t he falling edge of the st art bit was detected. each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. mck 16-bit counter 0 baud rate clock cd cd out divide by 16 0 1 >1 receiver sampling clock
274 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 24-4. start bit detection figure 24-5. character reception 24.5.2.3 receiver ready when a complete character is received, it is transferred to the dbgu_rhr and the rxrdy sta- tus bit in dbgu_sr (status register) is set. the bit rxrdy is automatically cleared when the receive holding register dbgu_rhr is read. figure 24-6. receiver ready 24.5.2.4 receiver overrun if dbgu_rhr has not been read by the software (o r the peripheral data controller or dma controller) since the last transf er, the rxrdy bit is still set and a new character is received, the ovre status bit in dbgu_sr is set. ovre is cleared when the software writes the control reg- ister dbgu_cr with the bit rststa (reset status) at 1. figure 24-7. receiver overrun 24.5.2.5 parity error each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field par in dbgu_mr. it then compares the result with the received parity sampling clock drxd true start detection d0 baud rate clock d0 d1 d2 d3 d4 d5 d6 d7 drxd true start detection sampling parity bit stop bit example: 8-bit, parity enabled 1 stop 1 bit period 0.5 bit period d0 d1 d2 d3 d4 d5 d6 d7 p s s d0 d1 d2 d3 d4 d5 d6 d7 p drxd read dbgu_rhr rxrdy d0 d1 d2 d3 d4 d5 d6 d7 p s s d0 d1 d2 d3 d4 d5 d6 d7 p drxd rststa rxrdy ovre stop stop
275 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 bit. if different, the parity error bit pare in dbgu_sr is set at the same time the rxrdy is set. the parity bit is cleared when the control register dbgu_cr is written with the bit rststa (reset status) at 1. if a new character is received before the reset status command is written, the pare bit remains at 1. figure 24-8. parity error 24.5.2.6 receiver framing error when a start bit is detected, it generates a character reception when all the data bits have been sampled. the stop bit is also sampled and when it is detected at 0, the frame (framing error) bit in dbgu_sr is set at the same time the rxrdy bit is set. the bit frame remains high until the control register dbgu_cr is written with the bit rststa at 1. figure 24-9. receiver framing error 24.5.3 transmitter 24.5.3.1 transmitter reset, enable and disable after device reset, the debug unit transmitter is disabled and it must be enabled before being used. the transmitter is enabled by writing the control register dbgu_cr with the bit txen at 1. from this command, the transmitter waits for a ch aracter to be written in the transmit holding register dbgu_thr before actually starting the transmission. the programmer can disable the transmitter by writing dbgu_cr with the bit txdis at 1. if the transmitter is not operating, it is immediately stopped. however, if a character is being pro- cessed into the shift register and/or a character has been written in the transmit holding register, the characters are completed before the transmitter is actually stopped. the programmer can also put the transmitter in its reset state by writing the dbgu_cr with the bit rsttx at 1. this immediately stops the transmitter, whether or not it is processing characters. 24.5.3.2 transmit format the debug unit transmitter drives the pin dtxd at the baud rate clock speed. the line is driven depending on the format defined in the mode register and the data stored in the shift register. one start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifte d out as shown on the following figure. the field stop d0 d1 d2 d3 d4 d5 d6 d7 p s drxd rststa rxrdy pare wrong parity bit d0 d1 d2 d3 d4 d5 d6 d7 p s drxd rststa rxrdy frame stop bit detected at 0 stop
276 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 pare in the mode register dbgu_mr defines whether or not a parity bit is shifted out. when a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit. figure 24-10. character transmission 24.5.3.3 transmitter control when the transmitter is enabled, the bit txrdy (transmitter ready) is set in the status register dbgu_sr. the transmission starts when the prog rammer writes in the transmit holding regis- ter dbgu_thr, and after the written character is transferred from dbgu_thr to the shift register. the bit txrdy remains high until a second character is written in dbgu_thr. as soon as the first character is completed, the last character written in dbgu_thr is transferred into the shift register and txrdy rises again, showing that the holding register is empty. when both the shift register and the dbgu_thr are empty, i.e., all the characters written in dbgu_thr have been processed, the bit txempty rises after the last stop bit has been completed. figure 24-11. transmitter control 24.5.4 dma support both the receiver and the transmitter of the debug units uart are connected to a dma con- troller (dmac) channel. the dma controller channels are programmed via registers that are mapped within the dmac user interface. d0 d1 d2 d3 d4 d5 d6 d7 dtxd start bit parity bit stop bit example: parity enabled baud rate clock dbgu_thr shift register dtxd txrdy txempty data 0 data 1 data 0 data 0 data 1 data 1 s s p p write data 0 in dbgu_thr write data 1 in dbgu_thr stop stop
277 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 24.5.5 test modes the debug unit supports three tests modes. these modes of operation are programmed by using the field chmode (channel mode) in the mode register dbgu_mr. the automatic echo mode allows bit-by-bit retr ansmission. when a bit is received on the drxd line, it is sent to the dtxd line. the transm itter operates normally, but has no effect on the dtxd line. the local loopback mode allows the transmitted characters to be received. dtxd and drxd pins are not used and the output of the transmitter is internally connected to the input of the receiver. the drxd pin level has no effect and th e dtxd line is held high , as in idle state. the remote loopback mode directly connects the drxd pin to the dtxd line. the transmitter and the receiver are disabled and have no effec t. this mode allows a bit-by-bit retransmission. figure 24-12. test modes 24.5.6 debug communication channel support the debug unit handles the signals commrx and commtx that come from the debug com- munication channel of the arm processor and are driven by the in-circuit emulator. the debug communication channel contains two registers that are accessible through the ice breaker on the jtag side and through the coprocessor 0 on the arm processor side. as a reminder, the following instructions ar e used to read and write the debug communication channel: receiver transmitter disabled rxd txd receiver transmitter disabled rxd txd v dd disabled receiver transmitter disabled rxd txd disabled automatic echo local loopback remote loopback v dd
278 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 mrc p14, 0, rd, c1, c0, 0 returns the debug communication data read register into rd mcr p14, 0, rd, c1, c0, 0 writes the value in rd to the debug communication data write register. the bits commrx and commtx, which indicate, respectively, that the read register has been written by the debugger but not yet read by the processor, and that the write register has been written by the processor and not yet read by the debugger, are wired on the two highest bits of the status register dbgu_sr. these bits can generate an interrupt. this feature permits han- dling under interrupt a debug link between a debug monitor running on the target system and a debugger. 24.5.7 chip identifier the debug unit features two chip identifier registers, dbgu_cidr (chip id register) and dbgu_exid (extension id). both registers contain a hard-wired value that is read-only. the first register contains the following fields: ? ext - shows the use of the extension identifier register ? nvptyp and nvpsiz - identifies the type of embedded non-volatile memory and its size ? arch - identifies the set of embedded peripherals ? sramsiz - indicates the size of the embedded sram ? eproc - indicates the embedded arm processor ? version - gives the revision of the silicon the second register is device-dependent and reads 0 if the bit ext is 0. 24.5.8 ice access prevention the debug unit allows blockage of access to the system through the arm processor's ice interface. this feature is implemented via th e register force ntrst (dbgu_fnr), that allows assertion of the ntrst signal of the ice interface. writing the bit fntrst (force ntrst) to 1 in this register prevents any activity on the tap controller. on standard devices, the bit fntrst resets to 0 and thus does not prevent ice access. this feature is especially useful on custom rom devices for customers who do not want their on-chip code to be visible.
279 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 24.6 debug unit (dbgu) user interface table 24-3. register mapping offset register name access reset 0x0000 control register dbgu_cr write-only C 0x0004 mode register dbgu_mr read-write 0x0 0x0008 interrupt enable register dbgu_ier write-only C 0x000c interrupt disable register dbgu_idr write-only C 0x0010 interrupt mask register dbgu_imr read-only 0x0 0x0014 status register dbgu_sr read-only C 0x0018 receive holding register dbgu_rhr read-only 0x0 0x001c transmit holding register dbgu_thr write-only C 0x0020 baud rate generator register dbgu_brgr read-write 0x0 0x0024 - 0x003c reserved C C C 0x0040 chip id register dbgu_cidr read-only C 0x0044 chip id extension register dbgu_exid read-only C 0x0048 force ntrst register dbgu_fnr read-write 0x0 0x004c - 0x00fc reserved C C C
280 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 24.6.1 debug unit control register name: dbgu_cr address: 0xfffff200 access: write-only ? rstrx: reset receiver 0 = no effect. 1 = the receiver logic is reset and disabled. if a ch aracter is being received, the reception is aborted. ? rsttx: reset transmitter 0 = no effect. 1 = the transmitter logic is reset and disabled. if a character is being transmitted, the transmission is aborted. ? rxen: receiver enable 0 = no effect. 1 = the receiver is enabled if rxdis is 0. ? rxdis: receiver disable 0 = no effect. 1 = the receiver is disabled. if a character is being processe d and rstrx is not set, the character is completed before the receiver is stopped. ? txen: transmitter enable 0 = no effect. 1 = the transmitter is ena bled if txdis is 0. ? txdis: transmitter disable 0 = no effect. 1 = the transmitter is disabled. if a character is bei ng processed and a character has been written the dbgu_thr and rsttx is not set, both characters are completed before the transmitter is stopped. ? rststa: reset status bits 0 = no effect. 1 = resets the status bits pare, frame and ovre in the dbgu_sr. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCC rststa 76543210 txdis txen rxdis rxen rsttx rstrx CC
281 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 24.6.2 debug unit mode register name: dbgu_mr address: 0xfffff204 access: read-write ? par: parity type ? chmode: channel mode 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 chmode CC pa r C 76543210 CCCCCCCC value name description 0b000 even even parity 0b001 odd odd parity 0b010 space space: parity forced to 0 0b011 mark mark: parity forced to 1 0b1xx none no parity value name description 0b00 norm normal mode 0b01 auto automatic echo 0b10 locloop local loopback 0b11 remloop remote loopback
282 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 24.6.3 debug unit interrupt enable register name: dbgu_ier address: 0xfffff208 access: write-only ? rxrdy: enable rxrdy interrupt ? txrdy: enable txrdy interrupt ? ovre: enable overrun error interrupt ? frame: enable framing error interrupt ? pare: enable parity error interrupt ? txempty: enable txempty interrupt ? commtx: enable commtx (from arm) interrupt ? commrx: enable commrx (from arm) interrupt 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 commrx commtx CCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCC CC C txempty C 76543210 pare frame ovre CC C txrdy rxrdy
283 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 24.6.4 debug unit interrupt disable register name: dbgu_idr address: 0xfffff20c access: write-only ? rxrdy: disable rxrdy interrupt ? txrdy: disable txrdy interrupt ? ovre: disable overrun error interrupt ? frame: disable framing error interrupt ? pare: disable parity error interrupt ? txempty: disable txempty interrupt ? commtx: disable commtx (from arm) interrupt ? commrx: disable commrx (from arm) interrupt 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 commrx commtx CCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCC CC C txempty C 76543210 pare frame ovre CC C txrdy rxrdy
284 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 24.6.5 debug unit interrupt mask register name: dbgu_imr address: 0xfffff210 access: read-only ? rxrdy: mask rxrdy interrupt ? txrdy: disable txrdy interrupt ? ovre: mask overrun error interrupt ? frame: mask framing error interrupt ? pare: mask parity error interrupt ? txempty: mask txempty interrupt ? commtx: mask commtx interrupt ? commrx: mask commrx interrupt 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 commrx commtx CCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCC CC C txempty C 76543210 pare frame ovre CC C txrdy rxrdy
285 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 24.6.6 debug unit status register name: dbgu_sr address: 0xfffff214 access: read-only ? rxrdy: receiver ready 0 = no character has been received since the last re ad of the dbgu_rhr or the receiver is disabled. 1 = at least one complete character has been received, transferred to dbgu_rhr and not yet read. ? txrdy: transmitter ready 0 = a character has been written to dbgu_thr and not yet transferred to the shift register, or the transmitter is disabled. 1 = there is no character written to dbgu_thr not yet transferred to the shift register. ? ovre: overrun error 0 = no overrun error has occurred since the last rststa. 1 = at least one overrun error has occurred since the last rststa. ? frame: framing error 0 = no framing error has occurred since the last rststa. 1 = at least one framing error has occurred since the last rststa. ? pare: parity error 0 = no parity error has occurred since the last rststa. 1 = at least one parity error has occurred since the last rststa. ? txempty: transmitter empty 0 = there are characters in dbgu_thr, or characters being processed by the transmitter, or the transmitter is disabled. 1 = there are no characters in dbgu_thr and there ar e no characters being processed by the transmitter. ? commtx: debug communication channel write status 0 = commtx from the arm processor is inactive. 1 = commtx from the arm processor is active. ? commrx: debug communication channel read status 0 = commrx from the arm processor is inactive. 1 = commrx from the arm processor is active. 31 30 29 28 27 26 25 24 commrx commtx CCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCC CC C txempty C 76543210 pare frame ovre CC C txrdy rxrdy
286 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 24.6.7 debug unit receiver holding register name: dbgu_rhr address: 0xfffff218 access: read-only ? rxchr: received character last received character if rxrdy is set. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 rxchr
287 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 24.6.8 debug unit transmit holding register name: dbgu_thr address: 0xfffff21c access: write-only ? txchr: character to be transmitted next character to be transmitted after the current character if txrdy is not set. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 txchr
288 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 24.6.9 debug unit baud ra te generator register name: dbgu_brgr address: 0xfffff220 access: read-write ? cd: clock divisor 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 cd 76543210 cd value name description 0 disabled dbgu disabled 1m c km c k 2 to 65535 C mck / (cd x 16)
289 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 24.6.10 debug unit chip id register name: dbgu_cidr address: 0xfffff240 access: read-only ? version: version of the device values depend upon the version of the device. ? eproc: embedded processor ? nvpsiz: nonvolatile program memory size 31 30 29 28 27 26 25 24 ext nvptyp arch 23 22 21 20 19 18 17 16 arch sramsiz 15 14 13 12 11 10 9 8 nvpsiz2 nvpsiz 76543210 eproc version value name description 1 arm946es arm946es 2 arm7tdmi arm7tdmi 3 cm3 cortex-m3 4 arm920t arm920t 5 arm926ejs arm926ejs 6c a 5 c o r t e x - a 5 value name description 0n o n e n o n e 18 k 8 k b y t e s 2 16k 16k bytes 3 32k 32k bytes 4C r e s e r v e d 5 64k 64k bytes 6C r e s e r v e d 7 128k 128k bytes 8C r e s e r v e d 9 256k 256k bytes 10 512k 512k bytes 11 C reserved 12 1024k 1024k bytes
290 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? nvpsiz2 second nonvolatile program memory size ? sramsiz: internal sram size 13 C reserved 14 2048k 2048k bytes 15 C reserved value name description 0n o n e n o n e 18 k 8 k b y t e s 2 16k 16k bytes 3 32k 32k bytes 4C r e s e r v e d 5 64k 64k bytes 6r e s e r v e d 7 128k 128k bytes 8C r e s e r v e d 9 256k 256k bytes 10 512k 512k bytes 11 C reserved 12 1024k 1024k bytes 13 C reserved 14 2048k 2048k bytes 15 C reserved value name description 0C r e s e r v e d 11 k 1 k b y t e s 22 k 2 k b y t e s 36 k 6 k b y t e s 4 112k 112k bytes 54 k 4 k b y t e s 6 80k 80k bytes 7 160k 160k bytes 88 k 8 k b y t e s 9 16k 16k bytes 10 32k 32k bytes 11 64k 64k bytes 12 128k 128k bytes value name description
291 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? arch: architecture identifier 13 256k 256k bytes 14 96k 96k bytes 15 512k 512k bytes value name description 0x19 at91sam9xx at91sam9xx series 0x29 at91sam9xexx at91sam9xexx series 0x34 at91x34 at91x34 series 0x37 cap7 cap7 series 0x39 cap9 cap9 series 0x3b cap11 cap11 series 0x40 at91x40 at91x40 series 0x42 at91x42 at91x42 series 0x55 at91x55 at91x55 series 0x60 at91sam7axx at91sam7axx series 0x61 at91sam7aqxx at91sam7aqxx series 0x63 at91x63 at91x63 series 0x70 at91sam7sxx at91sam7sxx series 0x71 at91sam7xcxx at91sam7xcxx series 0x72 at91sam7sexx at91sam7sexx series 0x73 at91sam7lxx at91sam7lxx series 0x75 at91sam7xxx at91sam7xxx series 0x76 at91sam7slxx at91sam7slxx series 0x80 atsam3uxc atsam3uxc series (100-pin version) 0x81 atsam3uxe atsam3uxe series (144-pin version) 0x83 atsam3axc atsam3axc series (100-pin version) 0x84 atsam3xxc atsam3xxc series (100-pin version) 0x85 atsam3xxe atsam3xxe series (144-pin version) 0x86 atsam3xxg atsam3xxg series (208/217-pin version) 0x88 atsam3sxa atsam3sxa series (48-pin version) 0x89 atsam3sxb atsam3sxb series (64-pin version) 0x8a atsam3sxc atsam3sxc series (100-pin version) 0x92 at91x92 at91x92 series 0x93 atsam3nxa atsam3nxa series (48-pin version) 0x94 atsam3nxb atsam3nxb series (64-pin version) 0x95 atsam3nxc atsam3nxc series (100-pin version) 0x98 atsam3sdxa atsam3sdxa series (48-pin version) value name description
292 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? nvptyp: nonvolatile program memory type ? ext: extension flag 0 = chip id has a single register definition without extension 1 = an extended chip id exists. 0x99 atsam3sdxb atsam3sdxb series (64-pin version) 0x9a atsam3sdxc atsam3sdxc series (100-pin version) 0xa5 C reserved 0xf0 at75cxx at75cxx series value name description 0rom rom 1 romless romless or on-chip flash 4 sram sram emulating rom 2 flash embedded flash memory 3 rom_flash rom and embedded flash memory nvpsiz is rom size nvpsiz2 is flash size value name description
293 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 24.6.11 debug unit chip id extension register name: dbgu_exid address: 0xfffff244 access: read-only ? exid: chip id extension reads 0 if the bit ext in dbgu_cidr is 0. 31 30 29 28 27 26 25 24 exid 23 22 21 20 19 18 17 16 exid 15 14 13 12 11 10 9 8 exid 76543210 exid
294 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 24.6.12 debug unit force ntrst register name: dbgu_fnr address: 0xfffff248 access: read-write ? fntrst: force ntrst 0 = ntrst of the arm processors tap controller is driven by the power_on_reset signal. 1 = ntrst of the arm processors tap controller is held low. 31 30 29 28 27 26 25 24 CCCCCCC C 23 22 21 20 19 18 17 16 CCCCCCC C 15 14 13 12 11 10 9 8 CCCCCCC C 7654321 0 CCCCCCC fntrst
295 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 295 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 25. umc fuse controller 25.1 description the fuse controller supports software fuse programming through a 32-bit register, only fuses set to level 1 are programmed. it reads the fuse states on startup and stores them into 32-bit registers. the first 8 fuse status registers (fuse_srx) can be masked and will read as a value of 0 regardle ss of the fuse state when masked. 25.2 embedded characteristics ? software fuse programming ? user write access for fuse ? part of fuse can be masked after read 25.3 block diagram figure 25-1. fuse controller block diagram fuse cells fuse controller fuse states fuse states controls controls
296 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 296 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 25.4 functional description 25.4.1 fuse reading the fuse states are automatically read on core startup and are available for reading in the 10 fuse status (fuse_srx) registers. the fuse states of bits 31 to 0 will be available at fuse_sr0, the fuse states of bits 63 to 32 will be available at fuse_sr1 and so on. fuse_srx registers can be updated manually by using the rrq bit of the fuse control register (fuse_cr). rs and ws bits of the fuse index register (fuse_ir) must be at level one before issuing the read request. figure 25-2. fuse read 25.4.2 fuse programming all the fuses can be written by software. to program fuses, strictly follow the order of the sequence instructions as provided below: 1. select the word to write, using the selw field of the fuse_index register (fuse_ir). 2. write the word to program in the fuse_data register (fuse_dr). 3. check that rs and ws bits of the fuse_index register are at level one (no read and no write pending). 4. write the wrq bit of the fuse_control register (fuse_cr) to begin the fuse program- ming. the key field must be written at the same time with a valu e 0xfb to make the write request valid. writing th e wrq bit will clear the ws bit. 5. check the ws bit of fuse_srx, when ws has a value of 1 the fuse write process is over. only fuses to be set to level 1 are written. outdated clock fuse_srx rrq ws rs up to date
297 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 297 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 25-3. fuse write 25.4.3 fuse masking it is possible to mask the first 8 fuse_srx register s so that they will be read at a value of 0, regardless of the fuse state. to activate fuse masking on the first 8 fuse_srx registers, the msk bit of the fuse mode reg- ister (fuse_mr) must be written to level 1. th e msk bit is write-only. solely a general reset can disable fuse masking. 00 xx xx f use[31:0] fuse[63:32] 01 clock wsel data wrq ws rs
298 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 298 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 25.5 fuse controller (fuse) user interface table 25-1. register mapping offset register name access reset 0x00 fuse control register fuse_cr read-write C 0x04 fuse mode register fuse_mr write-only C 0x08 fuse index register fuse_ir read-write 0x00000000 0x0c fuse data register fuse_dr read-write C 0x10 fuse status register 0 fuse_sr0 read-only 0x00000000 0x14 fuse status register 1 fuse_sr1 read-only 0x00000000 ... ... ... ... ... 0x34 fuse status register 9 fuse_sr9 read-only 0x00000000 0x38 - 0xdc reserved C C C 0xe0 - 0xfc reserved C C C
299 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 299 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 25.5.1 fuse control register name: fuse_cr address: 0xffffdc00 access: read-write ? wrq: write request 0 = no effect. 1 = request the word data to be programmed, ignored if key field is not filled with 0xfb. ? rrq: read request 0 = no effect. 1 = request the fuses to be read and fuse_srx registers ar e updated, i gnored if key field is not filled with 0xfb. ? key: key code this key code is needed to set the wrq bit. 0xfb (valid): valid key. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 key 76543210 CCCCCCr r qw r q
300 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 300 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 25.5.2 fuse mode register name: fuse_mr address: 0xffffdc04 access: write-only ? msk: mask fuse status registers 0 = no effect. 1 = mask the first 8 fuse_srx registers. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCCm s k
301 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 301 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 25.5.3 fuse index register name: fuse_ir address: 0xffffdc08 access: read-write ? ws: write status 0 = write is pending or no write has been requested since general reset. 1 = write of fuses is done. ? rs: read status 0 = read is pending or no read has been requested since general reset. 1 = read of fuses is done. ? wsel: word selection 0-15 = select the word to write. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCC w s e l 76543210 CCCCCCr sw s
302 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 302 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 25.5.4 fuse data register name: fuse_dr address: 0xffffdc0c access: read-write ? data: data to program data to program. only bits of with a value of 1 will be programmed. 31 30 29 28 27 26 25 24 data 23 22 21 20 19 18 17 16 data 15 14 13 12 11 10 9 8 data 76543210 data
303 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 303 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 25.5.5 fuse status register name: fuse_srx [x=0..9] address: 0xffffdc10 access: read-only ? fuse: fuse status indicates the status of corresponding fuses: 0 = unprogrammed. 1 = programmed. 31 30 29 28 27 26 25 24 fuse 23 22 21 20 19 18 17 16 fuse 15 14 13 12 11 10 9 8 fuse 76543210 fuse
304 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 304 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12
305 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 26. bus matrix (matrix) 26.1 description the bus matrix implements a multi-layer ahb, based on the ahb-lite protocol, that enables par- allel access paths between multiple ahb master s and slaves in a system, thus increasing the overall bandwidth. the bus matrix interconnects up to 16 ahb masters to up to 16 ahb slaves. the normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency). the bus matrix user interface is compliant with arm advanced peripheral bus and provides a chip configuration user interface with registers that allow the bus matrix to support application specific features. 26.2 embedded characteristics ? 6-layer matrix, handling requests from 6 masters ? programmable arbitration strategy C fixed-priority arbitration C round-robin arbitration, either with no default master, last accessed default master or fixed default master ? burst management C breaking with slot cycle limit support C undefined burst length support ? one address decoder provided per master C three different slaves may be assigned to each decoded memory area: one for internal rom boot, one after remap ? boot mode select C non-volatile boot memory can be internal rom or external memory on ebi_ncs0 ? remap command C allows remapping of an internal sram in place of the boot non-volatile memory (rom or external flash) C allows handling of dynamic exception vectors
306 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 26.3 matrix masters the bus matrix of the at91sam9cn12 product manages 6 masters, which means that each master can perform an access concurrently with others, to an available slave. each master has its own decoder, which is defined specifically for each master. in order to sim- plify the addressing, all the masters have the same decodings. 26.4 matrix slaves the bus matrix of the at91sam9cn12 product ma nages 5 slaves. each slave has its own arbi- ter, allowing a different arbitration per slave. 26.5 master to slave access all the masters can normally access all the slaves. however, some paths do not make sense, for example allowing access from the usb device high speed dma to the internal peripherals. thus, these paths are forbidden or simply not wired, and shown as - in the following table. table 26-1. list of bus matrix masters master 0 arm926 instruction master 1 arm926 data master 2&3 dma controller master 4 usb host dma master 5 lcd dma table 26-2. list of bus matrix slaves slave 0 internal sram slave 1 internal rom usb host user interface slave 2 external bus interface slave 3 peripheral bridge 0 slave 4 peripheral bridge 1 table 26-3. at91sam9cn12 master to slave access masters 0 1 2&3 4 5 slaves arm926 instruction arm926 data dma usb host dma lcd dma 0 internal sram x x x x x 1 internal rom usb host user interface xx x - - 2 external bus interface x x x x x 3 peripheral bridge 0 x x x - - 4 peripheral bridge 1 x x x - -
307 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 26.6 memory mapping the bus matrix provides one decoder for every ahb master interface. the decoder offers each ahb master several memory mappings. in fact, depending on the product, each memory area may be assigned to several slaves. booting at the same address while using different ahb slaves (i.e. external ram, internal rom or internal flash, etc.) becomes possible. the bus matrix user interface provides mast er remap control regist er (matrix_mrcr) that performs remap action for every master independently. 26.7 special bus granting mechanism the bus matrix provides some speculative bus granting techniques in order to anticipate access requests from some masters. this mechanism reduc es latency at first access of a burst or single transfer as long as the slave is free from any other master access, but does not provide any ben- efit as soon as the slave is continuously acce ssed by more than one master, since arbitration is pipelined and then has no negative effect on the slave bandwidth or access latency. this bus granting mechanism sets a different default master for every slave. at the end of the current access, if no other re quest is pending, the slave remains connected to its associated default master. a slave can be as sociated with three kinds of default masters: no default master, last access master and fixed default master. to change from one kind of default master to another, the bus matrix user interface provides the slave configuration registers, one for each slave, that set a default master for each slave. the slave configuration register contains two fields: defmstr_type and fixed_defmstr. the 2-bit defmstr_type field selects the default mast er type (no default, last access master, fixed default master), whereas the 4-bit fixed_defmstr field selects a fixed default master pro- vided that defmstr_type is set to fi xed default master. please refer to section 26.10.2 bus matrix slave configuration registers on page 314 . 26.7.1 no default master after the end of the current access, if no other request is pending, the slave is disconnected from all masters. no default ma ster suits low-power mode. this configuration incurs one latency clock cycle for the first access of a burst after bus idle. arbitration without default master may be used for masters that perform significant bursts or sev- eral transfers with no idle in between, or if the slave bus bandwidth is widely used by one or more masters. this configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput whatever is the number of requesting masters. 26.7.2 last access master after the end of the current access, if no other request is pending, the slave remains connected to the last master that performed an access request. this allows the bus matrix to remove the one latency cycle for the last master that accessed the slave. other non privileged masters still get one lat ency clock cycle if they want to access the same slave. this technique is useful for masters that mainly perform single accesses or short bursts with some idle cycles in between. this configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput whatever is the number of requesting masters.
308 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 26.7.3 fixed default master after the end of the current access, if no other request is pending, the slave connects to its fixed default master. unlike last access master, the fixed master does not change unless the user modifies it by a software action (field fixed_defmstr of the related matrix_scfg). this allows the bus matrix arbiters to remove the one latency clock cycle for the fixed default master of the slave. every request attempted by this fixed default master will not cause any arbi- tration latency whereas other non privileged masters will still get one latency cycle. this technique is useful for a master that mainly perform single accesses or short bursts with some idle cycles in between. this configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput whatever is the number of requesting masters. 26.8 arbitration the bus matrix provides an arbitration mechanism that reduces latency when conflict cases occur, i.e. when two or more masters try to access the same slave at the same time. one arbiter per ahb slave is provided, thus ar bitrating each slave differently. the bus matrix provides the user with t he possibility of choosing between 2 arbitration types or mixing them for each slave: 1. round-robin arbitration (default) 2. fixed priority arbitration the resulting algorithm may be complemented by selecting a default master configuration for each slave. when a re-arbitration must be done, specific conditions apply. see section 26.8.1 arbitration scheduling on page 308 . 26.8.1 arbitration scheduling each arbiter has the ability to arbitrate between two or more different master requests. in order to avoid burst breaking and also to provide the maximum throughput for slave interfaces, arbitra- tion may only take place during the following cycles: 1. idle cycles: when a slave is not connected to any master or is connected to a master which is not currently accessing it. 2. single cycles: when a slave is currently doing a single access. 3. end of burst cycles: when the current cycle is the last cycle of a burst transfer. for defined length burst, predicted end of burst matches the size of the transfer but is man- aged differently for undefined length burst. see undefined length burst arbitration on page 308 4. slot cycle limit: when the slot cycle counte r has reached the limit value indicating that the current master access is too long and must be broken. see slot cycle limit arbi- tration on page 309 26.8.1.1 undefined length burst arbitration in order to optimize ahb burst lengths and arbitration, it may be interesting to set a maximum for undefined length bursts (incr). the bus matrix prov ides specific logic in order to re-arbitrate before the end of the incr transfer. a predicted end of burst is used as a defined length burst transfer and can be selected from among the following undefined length burst type (ulbt) possibilities:
309 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1. unlimited: no predicted end of burst is generated and theref ore incr burst transfer will not be broken by this way, but will be able to complete unless broken at the slot cycle limit. this is normally the default and should be let as is in order to be able to allow full 1 kilobyte ahb intra-boundary 256-beat word bursts performed by some atmel ahb masters. 2. 1-beat bursts: predicted end of burst is generated at each single transfer inside the incr transfer. 3. 4-beat bursts: predicted end of burst is generated at the end of each 4-beat boundary inside incr transfer. 4. 8-beat bursts: predicted end of burst is generated at the end of each 8-beat boundary inside incr transfer. 5. 16-beat bursts: predicted end of burst is generated at the end of each 16-beat bound- ary inside incr transfer. 6. 32-beat bursts: predicted end of burst is generated at the end of each 32-beat bound- ary inside incr transfer. 7. 64-beat bursts: predicted end of burst is generated at the end of each 64-beat bound- ary inside incr transfer. 8. 128-beat bursts: predicted end of burst is generated at the end of each 128-beat boundary inside incr transfer. use of undefined length 16-beat bursts or less is discouraged since this generally decreases significantly overall bus bandwidth due to arbitration and slave latencies at each first access of a burst. if the master does not permanently and continuous ly request the same slave or has an intrinsi- cally limited average throughput, the ulbt should be let at its default unlimited value, knowing that the ahb specification natively limits all word bursts to 256 beats and double-word bursts to 128 beats because of its 1 kilobyte address boundaries. unless duly needed the ulbt should be let to its default 0 value for power saving. this selection can be done through the field ulbt of the master configuration registers (matrix_mcfg). 26.8.1.2 slot cycle limit arbitration the bus matrix contains specific logic to break long accesses, such as back to back undefined length bursts or very long bursts on a very sl ow slave (e.g., an external low speed memory). at each arbitration time a counter is loaded with t he value previously written in the slot_cycle field of the related slave configuration regist er (matrix_scfg) and decreased at each clock cycle. when the counter elapses, the arbiter has the ability to re-arbitrate at the end of the cur- rent ahb bus access cycle. unless some master has a very tight access late ncy constraint which could lead to data overflow or underflow due to a badly undersized internal fifo with respect to its throughput, the slot cycle limit should be disabled (slot_cycle = 0) or let to its default maximum value in order not to inefficiently break long bursts performed by some atmel masters. however, the slot cycle limit should not be disabled in the very particular case of a master capable of accessing the slave by performing ba ck to back undefined length bursts shorter than the number of ulbt beats with no idle cycle in between, since in this case the arbitration could be frozen all along the bursts sequence.
310 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 in most cases this feature is not needed and should be disabled for power saving. warning: this feature cannot prevent any slave from locking its access indefinitely. 26.8.2 arbitration priority scheme the bus matrix arbitration scheme is organized in priority pools. round-robin priority is used inside the highest and lowest priority pools, whereas fix level prior- ity is used between priority pools and inside the intermediate priority pools. for each slave, each master x is assigned to one of the slave priority pools through the priority registers for slaves (mxpr fields of matrix_pras and matrix_prbs). when evaluating masters requests, this programmed priority level always takes precedence. after reset, all the masters are belonging to the lowest priority pool (mxpr = 0) and so are granted bus access in a true round-robin fashion. the highest priority pool must be specifically reserved for masters requiring very low access latency. if more than one master belong to this pool, these will be granted bus access in a biased round-robin fashion which allow tight and deterministic maximum access latency from ahb bus request. in fact, at worst, any currently high priority ma ster request will be granted after the current bus master access is ended and the other high priority pool masters, if any, have been granted once each. the lowest priority pool shares the remaining bus bandwidth between ahb masters. intermediate priority pools allow fine priority tuning. typically, a moderately latency critical mas- ter or a bandwidth only critical master will use such a priority level. the higher the priority level (mxpr value), the higher the master priority. all combination of mxpr values are allowed for all masters and slaves. for example some mas- ters might be assigned to the highest priority pool (round-robin) and the remaining masters to the lowest priority pool (round-robin), with no master for intermediate fix priority levels. if more than one master is requesting the slave bus, whatever are the respective masters priori- ties, no master will be granted the slave bus for two consecutiv e runs. a master can only get back to back grants as long as it is the only requesting master. 26.8.2.1 fixed priority arbitration this arbitration algorithm is the first and onl y applied between masters from distinct priority pools. it is also used inside priority pools other than the highest and lowest ones (intermediate priority pools). it allows the bus matrix arbiters to dispatch the requests from different masters to the same slave by using the fixed priority defined by the user in the mxpr field for each master inside the matrix_pras and matrix_prbs priority registers. if two or more master requests are active at the same time, the master with the highest priority number mxpr is serviced first. inside intermediate priority pools, if two or more master requests with the same priority are active at the same time, the master with the highest number is serviced first. 26.8.2.2 round-robin arbitration this algorithm is only used inside the highest and lo west priority pools. it allows the bus matrix arbiters to dispatch the requests from different masters to the same slave in a fair way. if two or more master requests are active at the same time inside the priority pool, they are serviced in a round-robin increasing master number order.
311 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 26.9 write protect registers to prevent any single software error that may corrupt matrix behavior, the entire matrix address space from address offset 0x000 to 0x 1fc can be write-protected by setting the wpen bit in the matrix write protect mode register (matrix_wpmr). if a write access to anywhere in the matrix address space from address offset 0x000 to 0x1fc is detected, then the wpvs flag in the matrix write protect st atus register (matrix_wpsr) is set and the field wpvsrc indicates in which register the write access has been attempted. the wpvs flag is reset by writing the matrix write protect mode register (matrix_wpmr) with the appropriate access key wpkey.
312 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 26.10 bus matrix (matrix) user interface table 26-4. register mapping offset register name access reset 0x0000 master configuration register 0 matrix_mcfg0 read-write 0x00000001 0x0004 master configuration register 1 matrix_mcfg1 read-write 0x00000000 0x0008 master configuration register 2 matrix_mcfg2 read-write 0x00000000 0x000c master configuration register 3 matrix_mcfg3 read-write 0x00000000 0x0010 master configuration register 4 matrix_mcfg4 read-write 0x00000000 0x0014 master configuration register 5 matrix_mcfg5 read-write 0x00000000 0x0018 - 0x003c reserved C C C 0x0040 slave configuration register 0 matrix_scfg0 read-write 0x000001ff 0x0044 slave configuration register 1 matrix_scfg1 read-write 0x000001ff 0x0048 slave configuration register 2 matrix_scfg2 read-write 0x000001ff 0x004c slave configuration register 3 matrix_scfg3 read-write 0x000001ff 0x0050 slave configuration register 4 matrix_scfg4 read-write 0x000001ff 0x0054 - 0x007c reserved C C C 0x0080 priority register a for slave 0 matrix_pras0 read-write 0x00000000 0x0084 reserved C C C 0x0088 priority register a for slave 1 matrix_pras1 read-write 0x00000000 0x008c reserved C C C 0x0090 priority register a for slave 2 matrix_pras2 read-write 0x00000000 0x0094 reserved C C C 0x0098 priority register a for slave 3 matrix_pras3 read-write 0x00000000 0x009c reserved C C C 0x00a0 priority register a for slave 4 matrix_pras4 read-write 0x00000000 0x00a4 - 0x00fc reserved C C C 0x0100 master remap control register matrix_mrcr read-write 0x00000000 0x0104 - 0x010c reserved C C C 0x0110 - 0x01e0 chip configuration registers C C C 0x01e4 write protect mode regist er matrix_wpmr read-write 0x00000000 0x01e8 write protect status register matrix_wpsr read-only 0x00000000
313 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 26.10.1 bus matrix master configuration registers name: matrix_mcfg0...matrix_mcfg5 address: 0xffffde00 [0], 0xffffde04 [1], 0xffffde08 [2], 0xffffde0c [3], 0xffffde10 [4], 0xffffde14 [5] access: read-write ? ulbt: undefined length burst type 0: unlimited length burst no predicted end of burst is generated and therefore incr bursts coming from this master can only be broken if the slave slot cycle limit is reached. if the slot cycle limit is not reached, the burst is normally completed by the master, at the lat- est, on the next ahb 1 kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts. 1: single access the undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the incr burst. 2: 4-beat burst the undefined length burst is split into 4-beat bursts, allowing re-arbitration at each 4-beat burst end. 3: 8-beat burst the undefined length burst is split into 8-beat bursts, allowing re-arbitration at each 8-beat burst end. 4: 16-beat burst the undefined length burst is split into 16-beat bursts, allowing re-arbitration at each 16-beat burst end. 5: 32-beat burst the undefined length burst is split into 32-beat bursts, allowing re-arbitration at each 32-beat burst end. 6: 64-beat burst the undefined length burst is split into 64-beat bursts, allowing re-arbitration at each 64-beat burst end. 7: 128-beat burst the undefined length burst is split into 128-beat bursts, allowing re-arbitration at each 128-beat burst end. unless duly needed the ulbt should be let to its default 0 value for power saving. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCC u l b t
314 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 26.10.2 bus matrix slave configuration registers name: matrix_scfg0...matrix_scfg4 address: 0xffffde40 [0], 0xffffde44 [1], 0xffffde48 [2], 0xffffde4c [3], 0xffffde50 [4] access: read-write ? slot_cycle: maximum bus gr ant duration for masters when slot_cycle ahb clock cycles have elapsed since the last arbitration, a new arbitration takes place so as to let an other master access this slave. if an other master is re questing the slave bus, then the current master burst is broken. if slot_cycle = 0, the slot cycle limit feature is disabl ed and bursts always complete unless broken according to the ulbt. this limit has been placed in order to enforce arbitration so as to meet potential latency constraints of masters waiting for slave access or in the particular case of a master performing back to back undefined length bursts indefinitely freezing the arbitration. this limit must not be small. unreasonably small values break every burst and the bus matrix arbitrates without performing any data transfer. the default maximum value is usually an optimal conservative choice. in most cases this feature is not needed and should be disabled for power saving. see section 26.8.1.2 on page 309 . ? defmstr_type: default master type 0: no default master at the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters. this results in a one clock cycle latency for the first access of a burst transfer or for a single access. 1: last default master at the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it. this results in not having one cl ock cycle latency when the last master tries to access the slave again. 2: fixed default master at the end of the current slave access, if no other master r equest is pending, the slave connects to the fixed master the number that has been written in the fixed_defmstr field. this results in not having one cl ock cycle latency when the fixed master tries to access the slave again. ? fixed_defmstr: fixed default master this is the number of the defa ult master for this slave. only used if defmstr_type is 2. specifying the number of a mas- ter which is not connected to the selected slave is equivalent to setting defmstr_type to 0. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 C C fixed_defmstr defmstr_type 15 14 13 12 11 10 9 8 CCCCCCCs l o t _ c y c l e 76543210 slot_cycle
315 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 26.10.3 bus matrix priority registers a for slaves name: matrix_pras0...matrix_pras4 addresses: 0xffffde80 [0], 0xffffde88 [1], 0xffffde90 [2], 0xffffde98 [3], 0xffffdea0 [4] access: read-write ? mxpr: master x priority fixed priority of master x for accessing the selected slave. the higher the number, the higher the priority. all the masters programmed with the same mxpr value for the slave make up a priority pool. round-robin arbitration is used inside the lowest (mxpr = 0) and highest (mxpr = 3) priority pools. fixed priority is used inside intermediate priority pools (mxpr = 1) and (mxpr = 2). see arbitration priority scheme on page 310 for details. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CC m 5 p r CC m 4 p r 15 14 13 12 11 10 9 8 CC m 3 p r CC m 2 p r 76543210 CC m 1 p r CC m 0 p r
316 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 26.10.4 bus matrix master remap control register name: matrix_mrcr address: 0xffffdf00 access: read-write ? rcbx: remap command bit for master x 0: disable remapped address decoding for the selected master 1: enable remapped address decoding for the selected master 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 C C rcb5 rcb4 rcb3 rcb2 rcb1 rcb0
317 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 26.10.5 chip configuration user interface table 26-5. chip configuration user interface offset register name access reset value 0x0110 - 0x0114 reserved C C C 0x0118 ebi chip select assignment re gister ccfg_ebicsa read-write 0x00000000 0x011c - 0x01fc reserved C C C
318 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 26.10.5.1 ebi chip select assignment register name: ccfg_ebicsa access: read/write reset: 0x0000_0000 ? ebi_cs1a: ebi chip select 1 assignment 0 = ebi chip select 1 is assigned to the static memory controller. 1 = ebi chip select 1 is assigned to the ddr2sdr controller. ? ebi_cs3a: ebi chip select 3 assignment 0 = ebi chip select 3 is only assigned to the static memory controller and ebi_ncs3 behaves as defined by the smc. 1 = ebi chip select 3 is assigned to the static memory controller and the nand flash logic is activated. ? ebi_dbpuc: ebi data bus pull-up configuration 0 = ebi d0 - d15 data bus bits are internally pulled-up to the vddiom power supply. 1 = ebi d0 - d15 data bus bits are not internally pulled-up. ? ebi_dbpdc: ebi data bus pull-down configuration 0 = ebi d0 - d15 data bus bits are internally pulled- down to the gnd. 1 = ebi d0 - d15 data bus bits are not internally pulled-down. ? ebi_drive: ebi i/o drive configuration 0 = low drive. data bus + memory load capacitance < tbd pf. 1 = high drive (default). data bus + memory load capacitance < tbd pf. ? nfd0_on_d16: nand flash databus selection 0 = nand flash i/os are connected to d0-d15. vddnf must be equal to vddiom (default). 1 = nand flash i/os are connected to d16-d31. vddnf can be different from or equal to vddiom. this can be used if the smc connects to the nand flash only. using this function with another device on the smc will lead to an unpredictable behavior of that device. in that case, the default value must be selected. 31 30 29 28 27 26 25 24 CCCCCCC nfd0_on_d16 23 22 21 20 19 18 17 16 CCCCCCe b i _ d r i v eC 15 14 13 12 11 10 9 8 CCCCCCe b i _ d b p d c e b i _ d b p u c 76543210 C C C C ebi_cs3a C ebi_cs1a C
319 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 table 26-6. connection examples with various vddnf and vddiom nfd0_on_d16 signals vddiom vddnf external memory 0 nfd0 = d0, ..., nfd15 = d15 1.8v 1.8v ddr2 or lpddr or lpsdr + nand flash 1.8v 0 nfd0 = d0, ..., nfd15 = d15 3.3v 3.3v 32-bit sdr + nand flash 3.3v 1 nfd0 = d16, ..., nfd15 = d31 1.8v 1.8v ddr2 or lpddr or lpsdr + nand flash 1.8v 1 nfd0 = d16, ..., nfd15 = d31 1.8v 3.3v ddr2 or lpddr or lpsdr + nand flash 3.3v 1 nfd0 = d16, ..., nfd15 = d31 3.3v 1.8v 16-bit sdr + nand flash 1.8v
320 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 26.10.6 write protect mode register name: matrix_wpmr address: 0xffffdfe4 access: read-write for more details on matrix_wpmr, refer to section 26.9 write protect registers on page 311 . ? wpen: write protect enable 0 = disables the write protect if wpkey corresponds to 0x4d4154 (mat in ascii). 1 = enables the write protect if wpkey corresponds to 0x4d4154 (mat in ascii). protects the entire matrix address space from address offset 0x000 to 0x1fc. ? wpkey: write protect key (write-only) should be written at value 0x4d4154 (mat in ascii). writing any other value in this field aborts the write operation of the wpen bit. always reads as 0. 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 CCCCCCCw p e n
321 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 26.10.7 write protect status register name: matrix_wpsr address: 0xffffdfe8 access: read-only for more details on matrix_wpsr, refer to section 26.9 write protect registers on page 311 . ? wpvs: write protect violation status 0: no write protect violation has occurred since the last write of the matrix_wpmr. 1: at least one write protect violation has occurred since the last write of the matrix_wpmr. ? wpvsrc: write protect violation source when wpvs is active, this field indica tes the register address offset in which a write access has been attempted. otherwise it reads as 0. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 wpvsrc 15 14 13 12 11 10 9 8 wpvsrc 76543210 CCCCCCCw p v s
322 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12
323 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 27. external memories 27.1 description the external bus interface (ebi) is designed to ensure the successful data transfer between several external devices and the embedded memory controller of an arm-based device. the static memory, ddr, sdram and ecc controllers are all featured external memory con- trollers on the ebi. these external memory controllers are capable of handling several types of external memory and peripheral devices, such as sram, prom, eprom, eeprom, flash, ddr2 and sdram. the ebi operates with 1.8v or 3.3v power supply (vddiom). the ebi also supports the nand flash protocols via integrated circuitry that greatly reduces the requirements for external components. furthermore, the ebi handles data transfers with up to six external devices, each assigned to six address spaces defined by the embedded memory controller. data transfers are performed through a 16-bit or 32-bit data bus, an address bus of up to 26 bits, up to six chip select lines (ncs[5:0]) and several control pins that are generally multiplexed between the different external memory controllers. 27.2 embedded characteristics 32-bit wide interface, supporting: ? 16-bit ddr2/lpddr, 32-bit sdram/lpsdr ? static memories ? nand flash with multi-bit ecc
324 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 27.3 ebi block diagram figure 27-1. organization of the external bus interface external bus interface d[15:0] a[15:2], a19 pio mux logic user interface chip select assignor static memory controller ddr2 lpddr sdram controller bus matrix apb ahb address decoders a16/ba0 a0/nbs0 a1/nwr2/nbs2/dqm2 a17/ba1 ncs0 nrd ncs1/sdcs nwr0/nwe nwr1/nbs1 nwr3/nbs3/dqm3 sdck, sdck#, sdcke dqm[1:0] dqs[1:0] ras, cas sdwe, sda10 d[31:16] a[25:20] ncs4 ncs5 ncs2 nwait nandoe nandwe nand flash logic pmecc pmerrloc controllers a21/nandale a22/nandcle ncs3/nandcs a18/ba2
325 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 27.4 i/o lines description the connection of some signals through the mux logic is not direct and depends on the memory controller in use at the moment. table 27-2 on page 325 details the connections between the two memory controllers and the ebi pins. table 27-1. ebi i/o lines description name function type active level ebi ebi_d0 - ebi_d31 data bus i/o ebi_a0 - ebi_a25 address bus output ebi_nwait external wait signal input low smc ebi_ncs0 - ebi_ncs5 chip select lines output low ebi_nwr0 - ebi_nwr3 wri te signals output low ebi_nrd read signal output low ebi_nwe write enable output low ebi_nbs0 - ebi_nbs3 byte mask signals output low ebi for nand flash support ebi_nandcs nand flash chip select line output low ebi_nandoe nand flash output enable output low ebi_nandwe nand flash write enable output low ddr2/sdram controller ebi_sdck, ebi_sdck# ddr2/sdram differential clock output ebi_sdcke ddr2/sdram clock enable output high ebi_sdcs ddr2/sdram controller chip select line output low ebi_ba0 - 2 bank select output ebi_sdwe ddr2/sdram write enable output low ebi_ras - ebi_cas row and column signal output low ebi_sda10 sdram address 10 line output table 27-2. ebi pins and memory controllers i/o lines connections ebix pins sdram i/o lines smc i/o lines ebi_nwr1/nbs1/cfior nbs1 nwr1 ebi_a0/nbs0 not supported smc_a0 ebi_a1/nbs2/nwr2 not supported smc_a1 ebi_a[11:2] sdramc_a[9:0] smc_a[11:2] ebi_sda10 sdramc_a10 not supported ebi_a12 not supported smc_a12 ebi_a[14:13] sdramc_a[ 12:11] smc_a[14:13] ebi_a[25:15] not supported smc_a[25:15] ebi_d[31:0] d[31:0] d[31:0]
326 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 27.5 application example 27.5.1 hardware interface table 27-3 on page 326 details the connections to be applied between the ebi pins and the external devices for each memory controller. notes: 1. nwr1 enables upper byte writes. nwr0 enables lower byte writes. 2. nwrx enables corresponding byte x writes. (x = 0,1,2 or 3) 3. nbs0 and nbs1 enable respectively lower and upper bytes of the lower 16-bit word. 4. nbs2 and nbs3 enable respectively lower and upper bytes of the upper 16-bit word. 5. d25-31 and a20, a23-a25, ncs2, ncs4 , ncs5 are multiplexed on pd15-pd31. table 27-3. ebi pins and external static device connections signals: ebi_ pins of the interfaced device 8-bit static device 2 x 8-bit static devices 16-bit static device 4 x 8-bit static devices 2 x 16-bit static devices 32-bit static device controller smc d0 - d7 d0 - d7 d0 - d7 d0 - d7 d0 - d7 d0 - d7 d0 - d7 d8 - d15 C d8 - d15 d8 - d15 d8 - d15 d8 - 15 d8 - 15 d16 - d24 C C C d16 - d23 d16 - d23 d16 - d23 d25 - d31 (5) ) C C C d24 - d31 d24 - d31 d24 - d31 a0/nbs0 a0 C nlb C nlb (3) be0 a1/nwr2/nbs2/dqm2 a1 a0 a0 we (2) nlb (4) be2 a2 - a22 (5) a[2:22] a[1:21] a[1:21] a[0:20] a[0:20] a[0:20] a23 - a25 (5) a[23:25] a[22:24] a[22:24] a[21:23] a[21:23] a[21:23] ncs0 cs cs cs cs cs cs ncs1/ddrsdcs cs cs cs cs cs cs ncs2 (5) cs cs cs cs cs cs ncs3/nandcs cs cs cs cs cs cs ncs4 (5) cs cs cs cs cs cs ncs5 (5) cs cs cs cs cs cs nrd oe oe oe oe oe oe nwr0/nwe we we (1) we we (2) we we nwr1/nbs1 C we (1) nub we (2) nub (3) be1 nwr3/nbs3/dqm3 C C C we (2) nub (4) be3
327 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 table 27-4. ebi pins and external device connections signals: ebi_ power supply pins of the interfaced device ddr2/lpddr sdr/lpsdr nand flash controller ddrc sdramc nfc d0 - d15 vddiom d0 - d15 d0 - d15 nfd0-nfd15 (1) d16 - d31 vddnf C d16 - d31 nfd0-nfd15 (1) a0/nbs0 vddiom C C C a1/nwr2/nbs2/dqm2 vddiom C dqm2 C dqm0-dqm1 vddiom dqm0-dqm1 dqm0-dqm1 C dqs0-dqs1 vddiom dqs0-dqs1 C C a2 - a10 vddiom a[0:8] a[0:8] C a11 vddiom a9 a9 C sda10 vddiom a10 a10 C a12 vddiom C C C a13 - a14 vddiom a[11:12] a[11:12] C a15 vddiom a13 C C a16/ba0 vddiom ba0 ba0 C a17/ba1 vddiom ba1 ba1 C a18/ba2 vddiom ba2 ba2 C a19 vddiom C C C a20 vddiom C C C a21/nandale vddnf C C ale a22/nandcle vddnf C C cle a23 - a24 vddiom C C C a25 vddiom C C C ncs0 vddiom C C C ncs1/ddrsdcs vddiom ddrcs sdcs C ncs2 vddiom C C C ncs3/nandcs vddnf C C ce ncs4 vddiom C C C ncs5 vddiom C C C nandoe vddnf C C oe nandwe vddnf C C we nrd vddiom C C C nwr0/nwe vddiom C C C nwr1/nbs1 vddiom C C C nwr3/nbs3/dqm3 vddiom C dqm3 C sdck vddiom ck ck C sdck# vddiom ck# C C
328 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 note: 1. a switch, nfd0_on_d16, enables the user to select nand flash path on d0-d7 or d16-d24 depending on memory power supplies. this switch is located in the ebicsa register in the bus matrix user interface. 27.5.2 connection examples figure 27-2 shows an example of connections be tween the ebi and external devices. figure 27-2. ebi connections to memory devices sdcke vddiom cke cke C ras vddiom ras ras C cas vddiom cas cas C sdwe vddiom we we C pxx vddnf C C ce pxx vddnf C C rdy table 27-4. ebi pins and external device connections (continued) signals: ebi_ power supply pins of the interfaced device ddr2/lpddr sdr/lpsdr nand flash controller ddrc sdramc nfc ebi d0-d31 a2-a15 ras cas sdck sdcke sdwe a0/nbs0 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 nwr1/nbs1 a1/nwr2/nbs2 nwr3/nbs3 ncs1/sdcs d0-d7 d8-d15 a16/ba0 a17/ba1 a18-a25 a10 sda10 sda10 a2-a11, a13 ncs0 ncs2 ncs3 ncs4 ncs5 a16/ba0 a17/ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 a10 sda10 a2-a11, a13 a16/ba0 a17/ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 d16-d23 d24-d31 a10 sda10 a2-a11, a13 a16/ba0 a17/ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 a10 sda10 a2-a11, a13 a16/ba0 a17/ba1 nbs0 nbs1 nbs3 nbs2 nrd/noe nwr0/nwe 128k x 8 sram 128k x 8 sram d0-d7 d0-d7 a0-a16 a0-a16 a1-a17 a1-a17 cs cs oe we d0-d7 d8-d15 oe we nrd/noe a0/nwr0/nbs0 nrd/noe nwr1/nbs1 sdwe sdwe sdwe sdwe
329 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 27.6 product dependencies 27.6.1 i/o lines the pins used for interfacing the external bus interface may be multiplexed with the pio lines. the programmer must first program the pio controller to assign the external bus interface pins to their peripheral function. if i/o lines of the external bus interface are not used by the applica- tion, they can be used for other purposes by the pio controller. 27.7 functional description the ebi transfers data between the internal ahb bus (handled by the bus matrix) and the exter- nal memories or peripheral devices. it controls the waveforms and the parameters of the external address, data and control buses and is composed of the following elements: ? the static memory controller (smc) ? the ddr2/sdram controller (ddr2sdrc) ? the programmable multi-bit ecc controller (pmecc) ? a chip select assignment feature that assigns an ahb address space to the external devices ? a multiplex controller circuit that shares the pins between the different memory controllers ? programmable nand flash support logic 27.7.1 bus multiplexing the ebi offers a complete set of control signal s that share the 32-bit data lines, the address lines of up to 26 bits and the control signals through a multiplex logic operating in function of the memory area requests. multiplexing is specifically organized in or der to guarantee the maintenance of the address and output control lines at a stable state while no ex ternal access is being pe rformed. mult iplexing is also designed to respect the data float times defined in the memory controllers. furthermore, refresh cycles of the ddr2 and sdram are executed independently by the ddr2sdr control- ler without delaying the other external memory controller accesses. 27.7.2 pull-up control the ebi_csa registers in the chip configuration user interface permit enabling of on-chip pull- up resistors on the data bus lines not multiplexed with the pio controller lines. the pull-up resis- tors are enabled after reset. setting the ebix_dbpuc bit disables the pull-up resistors on the d0 to d15 lines. enabling the pull-up resistor on the d16-d31 lines can be performed by program- ming the appropriate pio controller. 27.7.3 drive level the ebi i/os accept two drive level, high and low. this allows to avoid overshoots and give the best performances according to the bus load and external memories. the voltage ranges and the slew rates are dete rmined by programming ebi_drive field in the chip configuration registers locate d in the matrix user interface. at reset the selected cu rrent drive is high.
330 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 27.7.4 power supplies the product embeds a dual power supply for ebi. vddnf for nand flash signals and vddiom for others. this allows to use an 1.8v or 3.3v nand flash inde pendently of sdram power supply. a switch, nfd0_on_d16, enables the user to select nand flash path on d0-d15 or d16-d32 depending on memory power supplies. this switch is located in the register ebicsa in the bus matrix user interface. in the following example the nand flash and the external ram (ddr2 or lpddr or 16-bit lpsdr) are in the same power supply range, (nfd0_on_d16 = 0) d[15:0] ale a[22:21] cle d[15:0] ebi nand flash (1.8v) ddr2 or lpddr or 16-bit lpsdr (1.8v) d[15:0] d[15:0] ale a[22:21] cle d[15:0] ebi nand flash (3.3v) 32bit sdram (3.3v) d[15:0] d[31:16] d[31:16]
331 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 in the following example the nand flash and the external ram (ddr2 or lpddr or 16bit lpsdr) are not in the same power supply range (nfd0_on_d16 = 1). this can be used if the smc connects to the nand flash only. using this function with another device on the smc will lead to an unpredictable behavior of that device. in th at case, the default value must be selected. at reset nfd0_on_d16 = 1 and nand fl ash bus is connected to d16-d31. 27.7.5 static memory controller for information on the static memory controller, refer to the static me mory controller section. 27.7.6 ddr2sdram controller for information on the ddr2sdr contro ller, refer to the ddr2sdrc section. 27.7.7 programmable multi-bit ecc controller for information on the pmecc contro ller, refer to the pmecc section. 27.7.8 nand flash support external bus interfaces 1 integrate circuitr y that interfaces to nand flash devices. 27.7.8.1 external bus interface the nand flash logic is driven by the static memory controller on the ncs3 address space. programming the ebi_csa field in the ebi_csa regi ster in the chip configuration user inter- face to the appropriate value enables the nand flash logic. for details on this register, refer to the bus matrix section. access to an external nand flash device is then made by accessing the address space reserved to ncs3 (i.e., between 0x4000 0000 and 0x4fff ffff). the nand flash logic drives the read and write command signals of the smc on the nandoe and nandwe signals when the ncs3 signal is active. nandoe and nandwe are invalidated as soon as the transfer address fails to lie in the ncs3 address space. see figure 27-3 on page 332 for more information. for details on these waveforms, refer to the static memory controller section. d[15:0] ale a[22:21] cle d[15:0] ebi nand flash (3.3v) ddr2 or lpddr or 16-bit lpsdr (1.8v) d[15:0] d[31:16]
332 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 27.7.8.2 nand flash signals the address latch enable and command latch enable signals on the nand flash device are driven by address bits a22 and a21 of the ebi address bus. the command, address or data words on the data bus of the nand flash device are distinguished by using their address within the ncsx address space. the chip enable (ce) signal of the device and the ready/busy (r/b) signals are connected to pio lines. the ce si gnal then remains asserted even when ncsx is not selected, preventing the device from returning to standby mode. figure 27-3. nand flash application example 27.8 implementation examples the following hardware conf igurations are given for illustration only. the user should refer to the memory manufacturer we b site to check current device availability. d[7:0] ale nandwe nandoe noe nwe a[22:21] cle ad[7:0] pio r/b ebi ce nand flash pio ncsx/nandcs not connected
333 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 27.8.1 2x8-bit ddr2 on ebi 27.8.1.1 hardware configuration 27.8.1.2 software configuration ? assign ebi_cs1 to the ddr2 controller by setti ng the ebi_cs1a bit in the ebi chip select register located in the bus matrix memory space. ? initialize the ddr2 controller depending on the ddr2 device and system bus frequency. the ddr2 initialization se quence is described in the sub-section ddr2 device initialization of the ddrsdrc section. in this case vddnf can be different from vd diom. nand flash device can be 3.3v or 1.8v and wired on d16-d31 data bus. nfd0_on_d16 is to be set to 1.
334 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 27.8.2 16-bit lpddr on ebi 27.8.2.1 hardware configuration 27.8.2.2 software configuration the following configuration has to be performed: ? assign ebi_cs1 to the ddr2 controller by setting the bit ebi_cs1a in the ebi chip select register located in the bus matrix memory space. ? initialize the ddr2 controller depending on the lpddr device and system bus frequency. the lpddr initialization sequence is described in the section low-power ddr1-sdram initial- ization in ddr/sdr sdram controller (ddrsdrc). in this case vddnf can be different from vd diom. nand flash device can be 3.3v or 1.8v and wired on d16-d31 data bus. nfd0_on_d16 is to be set to 1.
335 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 27.8.3 16-bit sdram 27.8.3.1 hardware configuration 27.8.3.2 software configuration the following configuration has to be performed: ? assign the ebi cs1 to the sdram controller by setting the bit ebi_cs1a in the ebi chip select assignment register locate d in the bus matrix memory space. ? initialize the sdram controller depending on the sdram device and system bus frequency. the data bus width is to be programmed to 16 bits. the sdram initialization sequence is described in the section sdram device initialization in sdram controller (sdramc). in this case vddnf can be different from vd diom. nand flash device can be 3.3v or 1.8v and wired on d16-d31 data bus. nfd0_on_d16 is to be set to 1.
336 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 27.8.4 2x16-bit sdram 27.8.4.1 hardware configuration 27.8.4.2 software configuration the following configuration has to be performed: ? assign the ebi cs1 to the sdram controller by setting the bit ebi_cs1a in the ebi chip select assignment register locate d in the bus matrix memory space. ? initialize the sdram controller depending on the sdram device and system bus frequency. the data bus width is to be programmed to 32 bits. the data lines d[16..31] are multiplexed with pio lines and thus the dedicated pios must be programmed in peripheral mode in the pio controller. the sdram initialization sequence is described in the section sdram device initialization in sdram controller (sdramc). in this case, vddnf must be equal to vddiom. the nand flash device must be 3.3v and wired on d0-d15 data bus. nfd0 _on_d16 must be set to 0. a10 a11 d4 a13 dqm0 d2 dqm2 a8 ba0 cas d10 ba1 d5 d12 a6 a3 d9 d14 d15 clk d23 d19 d18 d30 dqm1 d24 d26 a14 d31 d22 d28 d17 d25 d27 d16 d21 dqm3 d29 d20 a3 a4 a13 a9 sda10 a7 a6 a5 a10 a11 a14 a2 a8 d3 cke ras a9 d0 we a5 d6 d7 a2 sda10 d8 d1 a4 d13 d11 a7 sdcs ba0 ba1 clk cke cas ras we a[1..14] d[0..31] vddiom vddiom vddiom vddiom 256 mbits 256 mbits sdram c13 100nf c13 100nf c1 100nf c1 100nf c11 100nf c11 100nf r4 0r r4 0r c2 100nf c2 100nf c8 100nf c8 100nf c3 100nf c3 100nf mt48lc16m16a2 mn2 mt48lc16m16a2 mn2 a0 23 a1 24 a2 25 a3 26 a4 29 a5 30 a6 31 a7 32 a8 33 a9 34 a10 22 ba0 20 a12 36 dq0 2 dq1 4 dq2 5 dq3 7 dq4 8 dq5 10 dq6 11 dq7 13 dq8 42 dq9 44 dq10 45 dq11 47 dq12 48 dq13 50 dq14 51 dq15 53 vdd 1 vss 28 vss 41 vddq 3 vdd 27 n.c1 40 clk 38 cke 37 dqml 15 dqmh 39 cas 17 ras 18 we 16 cs 19 vddq 9 vddq 43 vddq 49 vssq 6 vssq 12 vssq 46 vssq 52 vdd 14 vss 54 a11 35 ba1 21 c4 100nf c4 100nf c5 100nf c5 100nf c12 100nf c12 100nf c6 100nf c6 100nf r3 470k r3 470k c9 100nf c9 100nf c14 100nf c14 100nf mt48lc16m16a2 mn1 mt48lc16m16a2p-75it mt48lc16m16a2 mn1 mt48lc16m16a2p-75it a0 23 a1 24 a2 25 a3 26 a4 29 a5 30 a6 31 a7 32 a8 33 a9 34 a10 22 ba0 20 a12 36 dq0 2 dq1 4 dq2 5 dq3 7 dq4 8 dq5 10 dq6 11 dq7 13 dq8 42 dq9 44 dq10 45 dq11 47 dq12 48 dq13 50 dq14 51 dq15 53 vdd 1 vss 28 vss 41 vddq 3 vdd 27 n.c1 40 clk 38 cke 37 dqml 15 dqmh 39 cas 17 ras 18 we 16 cs 19 vddq 9 vddq 43 vddq 49 vssq 6 vssq 12 vssq 46 vssq 52 vdd 14 vss 54 a11 35 ba1 21 r1 470k r1 470k r2 0r r2 0r c7 100nf c7 100nf c10 100nf c10 100nf
337 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 27.8.5 8-bit nand flash with nfd0_on_d16 = 0 27.8.5.1 hardware configuration 27.8.5.2 software configuration the following configuration has to be performed: ? set nfd0_on_d16 = 0 in the ebi chip select assignment register located in the bus matrix memory space ? assign the ebi cs3 to the nand flash by setting the bit ebi_cs3a in the ebi chip select assignment register ? reserve a21/a22 for ale/cle functions. address and command latches are controlled respectively by setting to 1 the address bits a21 and a22 during accesses. ? configure a pio line as an input to manage the ready/busy signal. ? configure static memory contro ller cs3 setup, pulse, cycle and mode accordingly to nand flash timings, the data bus width and the system bus frequency. d6 d0 d3 d4 d2 d1 d5 d7 nandoe nandwe (any pio) (any pio) ale cle d[0..7] 3v3 3v3 2 gb tsop48 package u1 k9f2g08u0m u1 k9f2g08u0m we 18 n.c 6 vcc 37 ce 9 re 8 n.c 20 wp 19 n.c 5 n.c 1 n.c 2 n.c 3 n.c 4 n.c 21 n.c 22 n.c 23 n.c 24 r/b 7 n.c 26 n.c 27 n.c 28 i/o0 29 n.c 34 n.c 35 vss 36 pre 38 n.c 39 vcc 12 vss 13 ale 17 n.c 11 n.c 10 n.c 14 n.c 15 cle 16 n.c 25 n.c 33 i/o1 30 i/o3 32 i/o2 31 n.c 47 n.c 46 n.c 45 i/o7 44 i/o6 43 i/o5 42 i/o4 41 n.c 40 n.c 48 r2 10k r2 10k c2 100nf c2 100nf r1 10k r1 10k c1 100nf c1 100nf
338 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 27.8.6 16-bit nand flash with nfd0_on_d16 = 0 27.8.6.1 hardware configuration 27.8.6.2 software configuration the software configuration is the same as for an 8-bit nand flash except for the data bus width programmed in the mode register of the static memory controller. d6 d0 d3 d4 d2 d1 d5 d7 d14 d8 d11 d12 d10 d9 d13 d15 nandoe nandwe (any pio) ale cle d[0..15] (any pio) 3v3 3v3 2 gb tsop48 package r1 10k r1 10k r2 10k r2 10k c2 100nf c2 100nf c1 100nf c1 100nf u1 mt29f2g16aabwp-et u1 mt29f2g16aabwp-et we 18 n.c 6 vcc 37 ce 9 re 8 n.c 20 wp 19 n.c 5 n.c 1 n.c 2 n.c 3 n.c 4 n.c 21 n.c 22 n.c 23 n.c 24 r/b 7 i/o0 26 i/o8 27 i/o1 28 i/o9 29 n.c 34 n.c 35 n.c 36 pre 38 n.c 39 vcc 12 vss 13 ale 17 n.c 11 n.c 10 n.c 14 n.c 15 cle 16 vss 25 i/o11 33 i/o2 30 i/o3 32 i/o10 31 i/o15 47 i/o7 46 i/o14 45 i/o6 44 i/o13 43 i/o5 42 i/o12 41 i/o4 40 vss 48
339 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 27.8.7 8-bit nand flash with nfd0_on_d16 = 1 27.8.7.1 hardware configuration figure 27-4. 27.8.7.2 software configuration the following configuration has to be performed: ? set nfd0_on_d16 = 1 in the ebi chip select assignment register located in the bus matrix memory space. ? assign the ebi cs3 to the nand flash by setting the bit ebi_cs3a in the ebi chip select assignment register. ? configure the piod controller to assign the required piod[23..0] to ebi function. ? reserve a21 / a22 for ale / cle functions. address and command latches are controlled respectively by setting to 1 the address bit a21 and a22 during accesses. ? configure a pio line as an input to manage the ready/busy signal. ? configure static memory contro ller cs3 setup, pulse, cycle and mode accordingly to nand flash timings, the data bus width and the system bus frequency.
340 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 27.8.8 16-bit nand flash with nfd0_on_d16 = 1 27.8.8.1 hardware configuration tbd 27.8.8.2 software configuration the software configuration is the same as for an 8-bit nand flash except for the data bus width programmed in the mode register of the static memory controller. 27.8.9 nor flash on ncs0 27.8.9.1 hardware configuration 27.8.9.2 software configuration the default configuration for the static memory controller, byte select mode, 16-bit data bus, read/write controlled by chip select, allows boot on 16-bit non-volatile memory at slow clock. for another configuration, configure the static memory controller cs0 setup, pulse, cycle and mode depending on flash timings and system bus frequency. a21 a22 a1 a2 a3 a4 a5 a6 a7 a8 a15 a9 a12 a13 a11 a10 a14 a16 d6 d0 d3 d4 d2 d1 d5 d7 d14 d8 d11 d12 d10 d9 d13 d15 a17 a20 a18 a19 d[0..15] a[1..22] nrst nwe ncs0 nrd 3v3 3v3 tsop48 package c2 100nf c2 100nf c1 100nf c1 100nf at49bv6416 u1 at49bv6416 u1 a0 25 a1 24 a2 23 a3 22 a4 21 a5 20 a6 19 a7 18 a8 8 a9 7 a10 6 a11 5 a12 4 a13 3 a14 2 a15 1 a16 48 a17 17 a18 16 a21 9 a20 10 a19 15 we 11 reset 12 wp 14 oe 28 ce 26 vpp 13 dq0 29 dq1 31 dq2 33 dq3 35 dq4 38 dq5 40 dq6 42 dq7 44 dq8 30 dq9 32 dq10 34 dq11 36 dq12 39 dq13 41 dq14 43 dq15 45 vccq 47 vss 27 vss 46 vcc 37
341 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 341 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 28. programmable multibit ecc co ntroller (pmecc) for mlc devices 28.1 description the pmecc controller is a programmable binary bch (bose, chaudhuri and hocquenghem) encoder/decoder. this controller can be used to generate redundancy information for both sin- gle-level cell (slc) and multi-le vel cell (mlc) nand flash devices. it supports redundancy for correction of 2, 4, 8, 12 or 24 bits of error per sector of data. 28.2 embedded characteristics ? multibit error correcting code. ? algorithm based on binary shortened bose, chaudhuri and hocquenghem (bch) codes. ? programmable error correcting capability: 2, 4, 8, 12 and 24 bit of errors per sector. ? programmable sector size: 512 bytes or 1024 bytes. ? programmable number of sectors per page: 1, 2, 4 or 8 sectors of data per page. ? programmable spare area size. ? supports spare area ecc protection. ? supports 8 kbytes page size using 1024 bytes per sector and 4 kbytes page size using 512 bytes per sector. ? configurable through apb interface ? multibit error detection is interrupt driven.
342 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 342 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 28.3 block diagram figure 28-1. block diagram 28.4 functional description the nand flash sector size is programmable and can be set to 512 bytes or 1024 bytes. the pmecc module generates redundancy at encoding time, when a nand write page operation is performed. the redundancy is appended to the page and written in the spare area. this opera- tion is performed by the processor. it moves the content of the pmeccx registers into the nand flash memory. the number of re gisters depends on the selected error correction capability, refer to table 28-1 on page 345 . this operation is executed for each sector. at decoding time, the pmecc module generates the remainder of the received codeword by minimal polynomials. when all polynomial remainders for a given sector are set to zero, no error occurred. when the polynomial remainders are other than zero, the codeword is corrupted and further processing is required. the pmecc module generates an interrupt indicating that an error occurred. the processor must read the pmeccisr register. this regi ster indicates which sector is corrupted. to find the error location within a sector, the processor must execute the decoding steps as follows: 1. syndrome computation 2. find the error locator polynomials user interface programmable bch algorithm static memory controller apb mlc/slc nand flash device pmecc controller 8-bit data bus control bus
343 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 343 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 3. find the roots of the error locator polynomial all decoding steps involve finite field computation. it means that a library of finite field arithmetic must be available to perform addition, multiplication and inversion. the finite field arithmetic operations can be performed through the use of a memory mapped lookup table, or direct soft- ware implementation. the software implementat ion presented is bas ed on lookup tables. two tables named gf_log and gf_antilog are used. if alph a is the primitive element of the field, then a power of alpha is in the field. assume beta = alpha ^ index, then beta belongs to the field, and gf_log(beta) = gf_log(alpha ^ index) = index. the gf_antilog tables provide exponent inverse of the element, if beta = alpha ^ index, then gf_antilog(index) = beta. the first step consists of the syndrome computation. the pmecc module computes the remain- ders and software must substitute the power of the primitive element. the procedure implementation is given in section 28.5.1 remainder substitution procedure on page 349 . the second step is the most software intensive. it is the berlekamps iterative algorithm for find- ing the error-location polynomial. the procedure implementation is given in section 28.5.2 find the error location polynomial sigma(x) on page 350 . the last step is finding the root of the error lo cation polynomial. this step can be very software intensive. indeed, there is no straightforward method of finding the roots, except by evaluating each element of the field in the error location polynomial. however a hardware accelerator can be used to find the roots of the polynomial. the programmable multibit error correction code location (pmerrloc) module provides this kind of hardware acceleration.
344 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 344 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 28-2. software/hardware multibit error correction dataflow nand flash program page operation configure pmecc : error correction capability sector size/page size nand write field set to true spare area desired layout move the nand page to external memory whether using dma or processor copy redundancy from pmecc user interface to user defined spare area. using dma or processor. pmecc computes redundancy as the data is written into external memory nand flash read page operation configure pmecc : error correction capability sector size/page size nand write field set to false spare area desired layout move the nand page from external memory whether using dma or processor pmecc computes polynomial remainders as the data is read from external memory pmecc modules indicate if at least one error is detected. if a sector is corrupted use the substitute() function to determine the syndromes. when the table of syndromes is completed, use the get_sigma() function to get the error location polynomial. find the error positions finding the roots of the error location polynomial. and correct the bits. this step can be hardware assisted using the pmerrloc module. hardware accelerator software hardware accelerator software
345 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 345 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 28.4.1 mlc/slc write page operation using pmecc when an mlc write page operation is performed, the pmecc controller is configured with the nandwr field of the pmeccfg register set to one. when the nand spare area contains file system information and redundancy (pmeccx), the spare area is error protected, then the spa- reen bit of the pmeccfg register is set to one. when the nand spare area contains only redundancy info rmation, the spareen bit is set to zero. when the write page operation is terminated, the user writes the redundancy in the nand spare area. this operation can be done with dma assistance. 28.4.1.1 slc/mlc write operation with spare enable bit set when the spareen field of the pmecc_cfg register is set to one, the spare area of the page is encoded with the stream of data of the last sector of the page. this mode is entered by writing one in the data field of the pmecc_ctrl register. when the encoding process is over, the redundancy is written to the spare area in user mode, user field of the pmecc_ctrl must be set to one. table 28-1. relevant redundancy registers bch_err field sector size set to 512 bytes sector size set to 1024 bytes 0 pmecc_ecc0 pmecc_ecc0 1 pmecc_ecc0, pmecc_ecc1 pmecc_ecc0, pmecc_ecc1 2 pmecc_ecc0, pmecc_ecc1, pmecc_ecc2, pmecc_ecc3 pmecc_ecc0, pmecc_ecc1, pmecc_ecc2, pmecc_ecc3 3 pmecc_ecc0, pmecc_ecc1, pmecc_ecc2, pmecc_ecc3, pmecc_ecc4, pmecc_ecc5, pmecc_ecc6 pmecc_ecc0, pmecc_ecc1, pmecc_ecc2, pmecc_ecc3, pmecc_ecc4, pmecc_ecc5, pmecc_ecc6 4 pmecc_ecc0, pmecc_ecc1, pmecc_ecc2, pmecc_ecc3, pmecc_ecc4, pmecc_ecc5, pmecc_ecc6, pmecc_ecc7, pmecc_ecc8, pmecc_ecc9 pmecc_ecc0, pmecc_ecc1, pmecc_ecc2, pmecc_ecc3, pmecc_ecc4, pmecc_ecc5, pmecc_ecc6, pmecc_ecc7, pmecc_ecc8, pmecc_ecc9, pmecc_ecc10 table 28-2. number of relevant ecc bytes per sector, copied from lsbyte to msbyte bch_err field sector size set to 512 bytes sector size set to 1024 bytes 0 4 bytes 4 bytes 1 7 bytes 7 bytes 2 13 bytes 14 bytes 3 20 bytes 21 bytes 4 39 bytes 42 bytes
346 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 346 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 28-3. nand write operation with spare encoding 28.4.1.2 mlc/slc write operation with spare area disabled when the spareen field of pmecc_cfg is set to zero the spare area is not encoded with the stream of data. this mode is entered by wr iting one to the data field of the pmecc_ctrl register. figure 28-4. nand write operation sector 0 512 or 1024 bytes sector 1 sector 2 sector 3 spare pagesize = n * sectorsize sparesize ecc_area start_addr end_addr ecc computation enable signal write nand operation with spareen set to one sector 0 512 or 1024 bytes sector 1 sector 2 sector 3 pagesize = n * sectorsize ecc computation enable signal write nand operation with spareen set to zero
347 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 347 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 28.4.2 mlc/slc read page operation using pmecc 28.4.2.1 mlc/slc read operation with spare decoding when the spare area is protected, the spare area contains valid data. as the redundancy may be included in the middle of the information stream, the user programs the start address and the end address of the ecc area. the controller will automatically skip the ecc area. this mode is entered by writing one in the data field of the pmecc_ctrl register. when the page has been fully retrieved from nand, the ecc area is r ead using the user mode by writing one to the user field of the pmecc_ctrl register. figure 28-5. read operation with spare decoding table 28-3. relevant remain ders registers bch_err field sector size set to 512 by tes sector size set to 1024 bytes 0 pmecc_rem0 pmecc_rem0 1 pmecc_rem0, pmecc_rem1 pmecc_rem0, pmecc_rem1 2 pmecc_rem0, pmecc_rem1, pmecc_rem2, pmecc_rem3, pmecc_rem0, pmecc_rem1, pmecc_rem2, pmecc_rem3 3 pmecc_rem0, pmecc_rem1, pmecc_rem2, pmecc_rem3, pmecc_rem4, pmecc_rem5, pmecc_rem6, pmecc_rem7 pmecc_rem0, pmecc_rem1, pmecc_rem2, pmecc_rem3, pmecc_rem4, pmecc_rem5, pmecc_rem6, pmecc_rem7 4 pmecc_rem0, pmecc_rem1, pmecc_rem2, pmecc_rem3, pmecc_rem4, pmecc_rem5, pmecc_rem6, pmecc_rem7, pmecc_rem8, pmecc_rem9, pmecc_rem10, pmecc_rem11 pmecc_rem0, pmecc_rem1, pmecc_rem2, pmecc_rem3, pmecc_rem4, pmecc_rem5, pmecc_rem6, pmecc_rem7, pmecc_rem8, pmecc_rem9, pmecc_rem10, pmecc_rem11 sector 0 512 or 1024 bytes sector 1 sector 2 sector 3 spare pagesize = n * sectorsize sparesize ecc_area start_addr end_addr remainder computation enable signal read nand operation with spareen set to one and auto set to zero
348 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 348 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 28.4.2.2 mlc/slc read operation if the spare area is not protected with the error correcting code, the redundancy area is retrieved directly. this mode is entered by writing one in the data field of the pmecc_ctrl register. when auto field is set to one the ecc is retrieved automatically, otherwise the ecc must be read using user mode. figure 28-6. read operation 28.4.2.3 mlc/slc user read ecc area this mode allows a manual retrieve of the ecc. this mode is entered writing one in the user field of the pmecc_ctrl register. figure 28-7. user read mode sector 0 512 or 1024 bytes sector 1 sector 2 sector 3 spare pagesize = n * sectorsize sparesize ecc_area start_addr end_addr remainder computation enable signal read nand operation with spareen set to zero and auto set to one ecc_sec0 ecc_sec1 ecc_sec2 ecc_sec3 ecc ecc_area_size ecc_area end_addr addr = 0 partial syndrome computation enable signal
349 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 349 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 28.5 software implementation 28.5.1 remainder substitution procedure the substitute function evaluates the polynomial remainder, with different values of the field primitive elements. the finite field arithmetic addition operation is performed with the exclusive or. the finite field arithmetic multiplication ope ration is performed through the gf_log, gf_antilog lookup tables. the rem2np1 and remn2np3 fields of the pmecc_remx registers contain only odd remain- ders. each bit indicates whether the coefficient of the polynomial remainder is set to zero or not. nb_error_max defines the maximum valu e of the error co rrecting capability. nb_error defines the error correcting capa bility selected at enco ding/decoding time. nb_field_elements defines the number of elements in the field. si[] is a table that holds the current syndrome value, an element of that table belongs to the field. this is also a shared variable for the next step of the decoding operation. oo[] is a table that contains the degree of the remainders. int substitute() { int i; int j; for (i = 1; i < 2 * nb_error_max; i++) { si[i] = 0; } for (i = 1; i < 2*nb_error; i++) { for (j = 0; j < oo[i]; j++) { if (rem2npx[i][j]) { si[i] = gf_antilog[(i * j)%nb_field_elements] ^ si[i]; } } } return 0; }
350 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 350 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 28.5.2 find the error location polynomial sigma(x) the sample code below gives a berlekamp iterativ e procedure for finding the value of the error location polynomial. the input of the procedure is the si[] table defined in the remainder substitution procedure. the output of the procedure is the error location polynomial named smu (sigma mu). the poly- nomial coefficients belong to the field. the smu[ nb_error+1][] is a table that contains all these coefficients. nb_error_max defines the maximum valu e of the error co rrecting capability. nb_error defines the error correcting capa bility selected at enco ding/decoding time. nb_field_elements defines the number of elements in the field. int get_sigma() { int i; int j; int k; /* mu */ int mu[nb_error_max+2]; /* sigma ro */ int sro[2*nb_error_max+1]; /* discrepancy */ int dmu[nb_error_max+2]; /* delta order */ int delta[nb_error_max+2]; /* index of largest delta */ int ro; int largest; int diff; /* */ /* first row */ /* */ /* mu */ mu[0] = -1; /* actually -1/2 */ /* sigma(x) set to 1 */ for (i = 0; i < (2*nb_error_max+1); i++) smu[0][i] = 0; smu[0][0] = 1; /* discrepancy set to 1 */ dmu[0] = 1; /* polynom order set to 0 */ lmu[0] = 0; /* delta set to -1 */ delta[0] = (mu[0] * 2 - lmu[0]) >> 1; /* */ /* second row */
351 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 351 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 /* */ /* mu */ mu[1] = 0; /* sigma(x) set to 1 */ for (i = 0; i < (2*nb_error_max+1); i++) smu[1][i] = 0; smu[1][0] = 1; /* discrepancy set to syndrome 1 */ dmu[1] = si[1]; /* polynom order set to 0 */ lmu[1] = 0; /* delta set to 0 */ delta[1] = (mu[1] * 2 - lmu[1]) >> 1; for (i=1; i <= nb_error; i++) { mu[i+1] = i << 1; /*************************************************/ /* */ /* */ /* compute sigma (mu+1) */ /* and l(mu) */ /* check if discrepancy is set to 0 */ if (dmu[i] == 0) { /* copy polynom */ for (j=0; j<2*nb_error_max+1; j++) { smu[i+1][j] = smu[i][j]; } /* copy previous polynom order to the next */ lmu[i+1] = lmu[i]; } else { ro = 0; largest = -1; /* find largest delta with dmu != 0 */ for (j=0; j largest) { largest = delta[j]; ro = j; }
352 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 352 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 } } /* initialize signal ro */ for (k = 0; k < 2*nb_error_max+1; k ++) { sro[k] = 0; } /* compute difference */ diff = (mu[i] - mu[ro]); /* compute x ^ (2(mu-ro)) */ for (k = 0; k < (2*nb_error_max+1); k ++) { sro[k+diff] = smu[ro][k]; } /* multiply by dmu * dmu[ro]^-1 */ for (k = 0; k < 2*nb_error_max+1; k ++) { /* dmu[ro] is not equal to zero by definition */ /* check that operand are different from 0 */ if (sro[k] && dmu[i]) { /* galois inverse */ sro[k] = gf_antilog[(gf_log[dmu[i]] + (nb_field_elements- gf_log[dmu[ro]]) + gf_log[sro[k]]) % nb_field_elements]; } } /* multiply by dmu * dmu[ro]^-1 */ for (k = 0; k < 2*nb_error_max+1; k++) { smu[i+1][k] = smu[i][k] ^ sro[k]; if (smu[i+1][k]) { /* find the order of the polynom */ lmu[i+1] = k << 1; } } } /* */ /* */ /* end compute sigma (mu+1) */ /* and l(mu) */ /*************************************************/ /* in either case compute delta */ delta[i+1] = (mu[i+1] * 2 - lmu[i+1]) >> 1; /* in either case compute the discrepancy */ for (k = 0 ; k <= (lmu[i+1]>>1); k++)
353 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 353 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 { if (k == 0) dmu[i+1] = si[2*(i-1)+3]; /* check if one operand of the multiplier is null, its index is -1 */ else if (smu[i+1][k] && si[2*(i-1)+3-k]) dmu[i+1] = gf_antilog[(gf_log[smu[i+1][k]] + gf_log[si[2*(i-1)+3-k]])%nn] ^ dmu[i+1]; } } return 0; } 28.5.3 find the error position the output of the get_sigma() procedure is a polynomial stored in the smu[nb_error+1][] table. the error position is the roots of that po lynomial. the degree of this polynomial is very important information, as it gives the number of errors. the pmerrloc module provides a hardware accelerator for this step.
354 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 354 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 28.6 programmable multibit ecc controller (pmecc) user interface table 28-4. register mapping offset register name access reset 0x00000000 pmecc configuration register pmecc_cfg read-write 0x00000000 0x00000004 pmecc spare area size register pmecc_sarea read-write 0x00000000 0x00000008 pmecc start address register pmecc_saddr read-write 0x00000000 0x0000000c pmecc end address register pmecc_eaddr read-write 0x00000000 0x00000010 pmecc clock control register pmecc_clk read-write 0x00000000 0x00000014 pmecc control register pmecc_ctrl write-only 0x00000000 0x00000018 pmecc status regist er pmecc_sr read-only 0x00000000 0x0000001c pmecc interrupt enable r egister pmecc_ier write-only 0x00000000 0x00000020 pmecc interrupt disable register pmecc_idr write-only C 0x00000024 pmecc interrupt mask register pmecc_imr read-only 0x00000000 0x00000028 pmecc interrupt status register pmecc_isr read-only 0x00000000 0x0000002c reserved C C C 0x040+sec_num*(0x40)+0x00 pmecc ecc 0 register pmecc_ecc0 read-only 0x00000000 0x040+sec_num*(0x40)+0x04 pmecc ecc 1 register pmecc_ecc1 read-only 0x00000000 0x040+sec_num*(0x40)+0x08 pmecc ecc 2 register pmecc_ecc2 read-only 0x00000000 0x040+sec_num*(0x40)+0x0c pmecc ecc 3 register pmecc_ecc3 read-only 0x00000000 0x040+sec_num*(0x40)+0x10 pmecc ecc 4 register pmecc_ecc4 read-only 0x00000000 0x040+sec_num*(0x40)+0x14 pmecc ecc 5 register pmecc_ecc5 read-only 0x00000000 0x040+sec_num*(0x40)+0x18 pmecc ecc 6 register pmecc_ecc6 read-only 0x00000000 0x040+sec_num*(0x40)+0x1c pmecc ecc 7 register pmecc_ecc7 read-only 0x00000000 0x040+sec_num*(0x40)+0x20 pmecc ecc 8 register pmecc_ecc8 read-only 0x00000000 0x040+sec_num*(0x40)+0x24 pmecc ecc 9 register pmecc_ecc9 read-only 0x00000000 0x040+sec_num*(0x40)+0x28 pmecc ecc 10 register pmecc_ecc10 read-only 0x00000000 0x240+sec_num*(0x40)+0x00 pmecc rem 0 register pmecc_rem0 read-only 0x00000000 0x240+sec_num*(0x40)+0x04 pmecc rem 1 register pmecc_rem1 read-only 0x00000000 0x240+sec_num*(0x40)+0x08 pmecc rem 2 register pmecc_rem2 read-only 0x00000000 0x240+sec_num*(0x40)+0x0c pmecc rem 3 register pmecc_rem3 read-only 0x00000000 0x240+sec_num*(0x40)+0x10 pmecc rem 4 register pmecc_rem4 read-only 0x00000000 0x240+sec_num*(0x40)+0x14 pmecc rem 5 register pmecc_rem5 read-only 0x00000000 0x240+sec_num*(0x40)+0x18 pmecc rem 6 register pmecc_rem6 read-only 0x00000000 0x240+sec_num*(0x40)+0x1c pmecc rem 7 register pmecc_rem7 read-only 0x00000000 0x240+sec_num*(0x40)+0x20 pmecc rem 8 register pmecc_rem8 read-only 0x00000000 0x240+sec_num*(0x40)+0x24 pmecc rem 9 register pmecc_rem9 read-only 0x00000000
355 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 355 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 0x240+sec_num*(0x40)+0x28 pmecc rem 10 register pmecc_rem10 read-only 0x00000000 0x240+sec_num*(0x40)+0x2c pmecc rem 11 register pmecc_rem11 read-only 0x00000000 0x440 - 0x5fc reserved C C C table 28-4. register mapping (continued) offset register name access reset
356 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 356 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 28.6.1 pmecc configuration register name: pmecc_cfg address: 0xffffe000 access: read-write reset: 0x00000000 ? bch_err: error correct capability ? sectorsz: sector size 0: the ecc computation is based on a sector of 512 bytes. 1: the ecc computation is based on a sector of 1024 bytes. ? pagesize: number of sectors in the page ? nandwr: nand write access :0: nand read access 1: nand write access ? spareen: spare enable C for nand write access: 0: the spare area is skipped 1: the spare area is protected with the last sector of data. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 C C C auto C C C spareen 15 14 13 12 11 10 9 8 nandwr C C pagesize 76543210 C C C sectorsz C bch_err value name description 0 bch_err2 2 errors 1 bch_err4 4 errors 2 bch_err8 8 errors 3 bch_err12 12 errors 4 bch_err24 24 errors value name description 0 pagesize_1sec 1 sector for main area (512 or 1024 bytes) 1 pagesize_2sec 2 sectors for main area (1024 or 2048 bytes) 2 pagesize_4sec 4 sectors for main area (2048 or 4096 bytes) 3 pagesize_8sec 8 errors for main area (4096 or 8192 bytes)
357 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 357 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 C for nand read access: 0: the spare area is skipped. 1: the spare area contains protected data or only redundancy information. ? auto: automatic mode enable this bit is only relevant in nand read mode, when spare enable is activated. 0: indicates that the spare area is not protected. in that case the ecc computation takes into account the ecc area located in the spare area. (within the start address and the end address). 1: indicates that the spare is error protected. in this case, the ecc computation takes into account the whole spare area minus the ecc area in the ecc computation operation.
358 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 358 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 28.6.2 pmecc spare area size register name: pmecc_sarea address: 0xffffe004 access: read-write reset: 0x00000000 ? sparesize: spare area size the spare area size is equal to (sparesize+1) bytes. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCs p a r e s i z e 76543210 sparesize
359 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 359 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 28.6.3 pmecc start address register name: pmecc_saddr address: 0xffffe008 access: read-write reset: 0x00000000 ? startaddr: ecc area start address (byte oriented address) this field indicates the first byte address of the ecc area. location 0 matches the first byte of the spare area. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCs t a r t a d d r 76543210 startaddr
360 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 360 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 28.6.4 pmecc end address register name: pmecc_eaddr address: 0xffffe00c access: read-write reset: 0x00000000 ? endaddr: ecc area end address (byte oriented address) this field indicates the last byte address of the ecc area. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 endaddr 76543210 endaddr
361 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 361 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 28.6.5 pmecc clock control register name: pmecc_clk address: 0xffffe010 access: read-write reset: 0x00000000 ? clkctrl: clock control register the pmecc module data path setup time is set to clkctrl+1. this field indicates the database setup times in number of clock cycles. at 133 mhz, this field must be programmed with 2, indicating that the setup time is 3 clock cycles. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCC c l k c t r l
362 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 362 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 28.6.6 pmecc control register name: pmecc_ctrl address: 0xffffe014 access: write-only reset: 0x00000000 ? rst: reset the pmecc module when set to one, this bit reset pmecc controller, configuration registers remain unaffected. ? data: start a data phase ? user: start a user mode phase ? enable: pmecc module enable pmecc module must always be configured before being activated. ? disable: pmecc module disable pmecc module must always be configured after being deactivated. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 C C disable enable C user data rst
363 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 363 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 28.6.7 pmecc status register name: pmecc_sr address: 0xffffe018 access: read-only reset: 0x00000000 ? busy: the kernel of the pmecc is busy ? enable: pmecc module status 0: the pmecc module is disabled and can be configured. 1: the pmecc module is enabled and the configuration registers cannot be written. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 C C C enable C C C busy
364 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 364 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 28.6.8 pmecc interrupt enable register name: pmecc_ier address: 0xffffe01c access: write-only reset: 0x00000000 ? errie: error interrupt enable 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCCe r r i e
365 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 365 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 28.6.9 pmecc interrupt disable register name: pmecc_idr address: 0xffffe020 access: write reset: 0x00000000 ? errid: error interrupt disable 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCCe r r i d
366 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 366 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 28.6.10 pmecc interrupt mask register name: pmecc_imr address: 0xffffe024 access: read-only reset: 0x00000000 ? errim: error interrupt enable 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCCe r r i m
367 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 367 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 28.6.11 pmecc interrupt status register name: pmecc_isr address: 0xffffe028 access: read-only reset: 0x00000000 ? erris: error interrupt status register when set to one, bit i of the pmeccisr register indicates that sector i is corrupted. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 31 30 29 28 27 26 25 24 erris
368 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 368 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 28.6.12 pmecc ecc x register name: pmecc_eccx [x=0..10] [sec_num=0..7] address: 0xffffe040 [0][0] .. 0xffffe068 [10][0] 0xffffe080 [0][1] .. 0xffffe0a8 [10][1] 0xffffe0c0 [0][2] .. 0xffffe0e8 [10][2] 0xffffe100 [0][3] .. 0xffffe128 [10][3] 0xffffe140 [0][4] .. 0xffffe168 [10][4] 0xffffe180 [0][5] .. 0xffffe1a8 [10][5] 0xffffe1c0 [0][6] .. 0xffffe1e8 [10][6] 0xffffe200 [0][7] .. 0xffffe228 [10][7] access: read-only reset: 0x00000000 ? ecc: bch redundancy this register contains the remainder of the divi sion of the codeword by the generator polynomial. 31 30 29 28 27 26 25 24 ecc 23 22 21 20 19 18 17 16 ecc 15 14 13 12 11 10 9 8 ecc 76543210 ecc
369 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 369 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 28.6.13 pmecc remainder x register name: pmecc_remx [x=0..11] [sec_num=0..7] address: 0xffffe240 [0][0] .. 0xffffe26c [11][0] 0xffffe280 [0][1] .. 0xffffe2ac [11][1] 0xffffe2c0 [0][2] .. 0xffffe2ec [11][2] 0xffffe300 [0][3] .. 0xffffe32c [11][3] 0xffffe340 [0][4] .. 0xffffe36c [11][4] 0xffffe380 [0][5] .. 0xffffe3ac [11][5] 0xffffe3c0 [0][6] .. 0xffffe3ec [11][6] 0xffffe400 [0][7] .. 0xffffe42c [11][7] access: read-only reset: 0x00000000 ? rem2np1: bch remainder 2 * n + 1 when sector size is set to 512 bytes, bit rem2np1[13] is not used and read as zero. if bit i of the rem2np1 field is set to one then the coefficient of the x ^ i is set to one, otherwise the coefficient is zero. ? rem2np3: bch remainder 2 * n + 3 when sector size is set to 512 bytes, bit rem2np3[29] is not used and read as zero. if bit i of the rem2np3 field is set to one then the coefficient of the x ^ i is set to one, otherwise the coefficient is zero. 31 30 29 28 27 26 25 24 CC r e m 2 n p 3 23 22 21 20 19 18 17 16 rem2np3 15 14 13 12 11 10 9 8 CC r e m 2 n p 1 76543210 rem2np1
370 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 370 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12
371 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 371 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 29. programmable multibit ecc erro r location controller (pmerrloc) 29.1 description the pmecc error location controller provides hardware acceleration for determining roots of polynomials over two finite fields: gf(2^13) and gf(2^14). it integrates 24 fully programmable coefficients. these coefficients belong to gf(2^1 3) or gf(2^14). the coefficient programmed in the pmerrloc_sigmax register is the coefficient of degree x in the polynomial. 29.2 embedded characteristics ? provides hardware acceleration for determining roots of polynomials defined over a finite field ? programmable finite field gf(2^13) or gf(2^14) ? finds roots of error locator polynomial ? programmable number of roots 29.3 block diagram figure 29-1. block diagram user interface programmable searching circuit apb pmecc error location controller
372 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 372 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 29.4 functional description the pmerrloc search operation is started as s oon as a write access is detected in the elen register and can be disabled by writing to the eldis register. the eninit field of the elen reg- ister shall be initialized with the number of galois field elements to test. the set of the roots can be limited to a valid range. when the pmeerrloc engine is searching for roots the busy field of the elsr remains asserted. an interrupt is asserted at the end of the computation, and the done bit of the elsir register is set. the err_cnt field of the elisr indicates the number of errors. the error posi- tion can be read in the pmerrlocx registers. table 29-1. eninit field value for a sector size of 512 bytes error correcting capability eninit value 2 4122 4 4148 8 4200 12 4252 24 4408 table 29-2. eninit field value for a sector size of 1024 bytes error correcting capability eninit value 2 8220 4 8248 8 8304 12 8360 24 8528
373 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 373 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 29.5 programmable multibit ecc erro r location (pmerrloc ) user interface table 29-3. register mapping offset register name access reset 0x000 error location configuration register pmerrloc_elcfg read-write 0x00000000 0x004 error location primitive regist er pmerrloc_elprim read-only 0x00000000 0x008 error location enable register pmerrloc_elen read-write 0x00000000 0x00c error location disable register pmerrloc_eldis read-write 0x00000000 0x010 error location status register pmerrloc_elsr read-write 0x00000000 0x014 error location interrupt enable r egister pmerrloc_elier read-only 0x00000000 0x018 error location interrupt disable r egister pmerrloc_elidr read-only 0x00000000 0x01c error location interrupt mask register pmerrloc_elimr read-only 0x00000000 0x020 error location interrupt status register pmerrloc_elisr read-only 0x00000000 0x024 reserved C C C 0x028 pmecc sigma 0 register pmer rloc_sigma0 read-write 0x00000000 ... ... ... ... ... 0x088 pmecc sigma 24 register pmerrloc_sigma24 read-write 0x00000000 0x08c pmecc error location 0 register pmerrloc_el0 read-only 0x00000000 ... ... ... ... ... 0x0e4 pmecc error location 23 register pmerrloc_el23 read-only 0x00000000 0xe8 - 0x1fc reserved C C C
374 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 374 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 29.5.1 error location configuration register name: pmerrloc_elcfg address: 0xffffe600 access: read-write reset: 0x00000000 ? errnum: number of errors ? sectorsz: sector size 0: the ecc computation is based on a 512-byte sector. 1: the ecc computation is based on a 1024-byte sector. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 C C C errnum 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCCs e c t o r s z
375 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 375 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 29.5.2 error location primitive register name: pmerrloc_elprim address: 0xffffe604 access: read-only reset: 0x00000000 ? primitiv: primitive polynomial 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 primitiv 76543210 primitiv
376 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 376 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 29.5.3 error location enable register name: pmerrloc_elen address: 0xffffe608 access: read-write reset: 0x00000000 ? eninit: initial number of bits in the codeword 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CC e n i n i t 76543210 eninit
377 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 377 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 29.5.4 error location disable register name: pmerrloc_eldis address: 0xffffe60c access: read-write reset: 0x00000000 ? dis: disable error location engine 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCCd i s
378 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 378 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 29.5.5 error location status register name: pmerrloc_elsr address: 0xffffe610 access: read-write reset: 0x00000000 ? busy: error location engine busy 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCCb u s y
379 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 379 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 29.5.6 error location interrupt enable register name: pmerrloc_elier address: 0xffffe614 access: read-only reset: 0x00000000 ? done: computation terminated interrupt enable 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCCd o n e
380 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 380 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 29.5.7 error location interrupt disable register name: pmerrloc_elidr address: 0xffffe618 access: read-only reset: 0x00000000 ? done: computation terminated interrupt disable 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCCd o n e
381 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 381 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 29.5.8 error location interrupt mask register name: pmerrloc_elimr address: 0xffffe61c access: read-only reset: 0x00000000 ? done: computation terminated interrupt mask 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCCd o n e
382 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 382 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 29.5.9 error location interrupt status register name: pmerrloc_elisr address: 0xffffe620 access: read-only reset: 0x00000000 ? done: computation terminated interrupt status ? err_cnt: error counter value 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCC e r r _ c n t 76543210 CCCCCCCd o n e
383 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 383 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 29.5.10 error location sigmax register name: pmerrloc_sigmax [x=0..24] address: 0xffffe628 access: read-write reset: 0x00000000 ? sigmax: coefficient of degree x in the sigma polynomial. sigmax belongs to the finite field gf(2^13) when the sector size is set to 512 bytes. sigmax belongs to the finite field gf(2^14) when the sector size is set to 1024 bytes. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CC s i g m a n 76543210 sigman
384 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 384 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 29.5.11 pmecc error locationx register name: pmerrloc_elx [x=0..23] address: 0xffffe68c access: read-only reset: 0x00000000 ? errlocn: error position within the set {sector area, spare area}. errlocn points to 0 when the first bit of the main area is corrupted. if the sector size is set to 512 bytes, the errlocn points to 4096 when the last bit of the sector area is corrupted. if the sector size is set to 1024 bytes, the errlocn points to 8192 when the last bit of the sector area is corrupted. if the sector size is set to 512 bytes, the errlocn points to 4097 when the first bit of the spare area is corrupted. if the sector size is set to 1024 bytes, the errlocn points to 8193 when the first bit of the spare area is corrupted. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 C C errlocn 76543210 errlocn
385 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 30. static memory controller (smc) 30.1 description the static memory controller (smc) generates the signals that control the access to the exter- nal memory devices or peripheral devices. it has 6 chip selects and a 26-bit address bus. the 32-bit data bus can be configured to interface with 8-, 16-, or 32-bit external devices. separate read and write control signals allow for direct memory and peripheral interfacing. read and write signal waveforms are fully parametrizable. the smc can manage wait requests from external devices to extend the current access. the smc is provided with an automatic slow clock mode. in slow clock mode, it switches from user- programmed waveforms to slow-rate specific waveforms on read and write signals. the smc supports asynchronous burst read in page mode access for page size up to 32 bytes. 30.2 embedded characteristics ? 6 chip selects available ? 64-mbyte address space per chip select ? 8-, 16- or 32-bit data bus ? word, halfword, byte transfers ? byte write or byte select lines ? programmable setup, pulse and hold time for read signals per chip select ? programmable setup, pulse and hold ti me for write signals per chip select ? programmable data float time per chip select ? compliant with lcd module ? external wait request ? automatic switch to slow clock mode ? asynchronous read in page mode supported: page size ranges from 4 to 32 bytes
386 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 30.3 i/o lines description 30.4 multiplexed signals table 30-1. i/o line description name description type active level ncs[5:0] static memory controller chip select lines output low nrd read signal output low nwr0/nwe write 0/write enable signal output low a0/nbs0 address bit 0/byte 0 select signal output low nwr1/nbs1 write 1/byte 1 select signal output low a1/nwr2/nbs2 address bit 1/write 2/byte 2 select signal output low nwr3/nbs3 write 3/byte 3 select signal output low a[25:2] address bus output d[31:0] data bus i/o nwait external wait signal input low table 30-2. static memory controller (smc) multiplexed signals multiplexed signal s related function nwr0 nwe byte-write or byte-select access, see byte write or byte select access on page 388 a0 nbs0 8-bit or 16-/32-bit data bus, see data bus width on page 388 nwr1 nbs1 byte-write or byte-select access see byte write or byte sele ct access on page 388 a1 nwr2 nbs2 8-/16-bit or 32-bit data bus, see data bus width on page 388 . byte-write or byte-select access, see byte write or byte select access on page 388 nwr3 nbs3 byte-write or byte-select access see byte write or byte sele ct access on page 388
387 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 30.5 application example 30.5.1 hardware interface figure 30-1. smc connections to st atic memory devices 30.6 product dependencies 30.6.1 i/o lines the pins used for interfacing the static memory controller may be multiplexed with the pio lines. the programmer must first program the pio controller to assign the static memory con- troller pins to their peripheral function. if i/o lines of the smc are not used by the application, they can be used for other purposes by the pio controller. static memory controller d0-d31 a2 - a25 a0/nbs0 nwr0/nwe nwr1/nbs1 a1/nwr2/nbs2 nwr3/nbs3 128k x 8 sram d0 - d7 a0 - a16 oe we cs d0 - d7 d8-d15 a2 - a18 128k x 8 sram d0-d7 cs d16 - d23 d24-d31 128k x 8 sram d0-d7 cs nwr1/nbs1 nwr3/nbs3 nrd nwr0/nwe 128k x 8 sram d0 - d7 oe we cs nrd a1/nwr2/nbs2 ncs0 ncs1 ncs2 ncs3 ncs4 ncs5 ncs6 ncs7 a2 - a18 a0 - a16 nrd oe we oe we nrd a2 - a18 a0 - a16 a2 - a18 a0 - a16
388 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 30.7 external memory mapping the smc provides up to 26 address lines, a[25:0]. this allows each chip select line to address up to 64 mbytes of memory. if the physical memory device connected on one chip select is smaller than 64 mbytes, it wraps around and appears to be repeated within this space. the smc correctly handles any valid access to the memory devi ce within the page (see figure 30-2 ). a[25:0] is only significant for 8-bit memory, a[25:1 ] is used for 16-bit memory, a[25:2] is used for 32-bit memory. figure 30-2. memory connections for eight external devices 30.8 connection to external devices 30.8.1 data bus width a data bus width of 8, 16, or 32 bits can be selected for each chip select. this option is con- trolled by the field dbw in smc_mode (mode register) for the corresponding chip select. figure 30-3 shows how to connect a 512k x 8-bit memory on ncs2. figure 30-4 shows how to connect a 512k x 16-bit memory on ncs2. figure 30-5 shows two 16-bit memories connected as a single 32-bit memory 30.8.2 byte write or byte select access each chip select with a 16-bit or 32-bit data bus can operate with one of two different types of write access: byte write or byte select access . this is controlled by the bat field of the smc_mode register for the corresponding chip select. nrd nwe a[25:0] d[31:0] 8 or 16 or 32 memory enable memory enable memory enable memory enable memory enable memory enable memory enable memory enable output enable write enable a[25:0] d[31:0] or d[15:0] or d[7:0] ncs3 ncs0 ncs1 ncs2 ncs7 ncs4 ncs5 ncs6 ncs[0] - ncs[7] smc
389 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 30-3. memory connection for an 8-bit data bus figure 30-4. memory connection for a 16-bit data bus figure 30-5. memory connection for a 32-bit data bus smc a0 nwe nrd ncs[2] a0 write enable output enable memory enable d[7:0] d[7:0] a[18:2] a[18:2] a1 a1 smc nbs0 nwe nrd ncs[2] low byte enable write enable output enable memory enable nbs1 high byte enable d[15:0] d[15:0] a[19:2] a[18:1] a[0] a1 d[31:16] smc nbs0 nwe nrd ncs[2] nbs1 d[15:0] a[20:2] d[31:16] nbs2 nbs3 byte 0 enable write enable output enable memory enable byte 1 enable d[15:0] a[18:0] byte 2 enable byte 3 enable
390 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 30.8.2.1 byte write access byte write access supports one byte write signal per byte of the data bus and a single read signal. note that the smc does not allow boot in byte write access mode. ? for 16-bit devices: the smc provides nwr0 and nwr1 write signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. one single read signal (nrd) is provided. byte write access is used to connect 2 x 8-bit devices as a 16-bit memory. ? for 32-bit devices: nwr0, nwr1, nwr2 and nwr3, are the write signals of byte0 (lower byte), byte1, byte2 and byte 3 (upper byte) respectively. one single read signal (nrd) is provided. byte write access is used to connect 4 x 8-bit devices as a 32-bit memory. byte write option is illustrated on figure 30-6 . 30.8.2.2 byte select access in this mode, read/write operations can be enabled/disabled at a byte level. one byte-select line per byte of the data bus is provided. one nrd and one nwe signal control read and write. ? for 16-bit devices: the smc provides nbs0 and nbs1 selection signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. byte select access is used to connect one 16-bit device. ? for 32-bit devices: nbs0, nbs1, nbs2 and nbs3, are the selection signals of byte0 (lower byte), byte1, byte2 and byte 3 (upper byte) respectively. byte select access is used to connect two 16-bit devices. figure 30-7 shows how to connect two 16-bit devices on a 32-bit data bus in byte select access mode, on ncs3 (bat = byte select access).
391 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 30-6. connection of 2 x 8-bit devices on a 16-bit bus: byte write option 30.8.2.3 signal multiplexing depending on the bat, only the write signals or the byte select signals are used. to save ios at the external bus interface, control signals at the smc interface are multiplexed. table 30-3 shows signal multiplexing depending on the data bus width and the byte access type. for 32-bit devices, bits a0 and a1 are unused. for 16-bit devices, bit a0 of address is unused. when byte select option is selected, nwr1 to nwr3 are unused. when byte write option is selected, nbs0 to nbs3 are unused. smc a1 nwr0 nrd ncs[3] write enable read enable memory enable nwr1 write enable read enable memory enable d[7:0] d[7:0] d[15:8] d[15:8] a[24:2] a[23:1] a[23:1] a[0] a[0]
392 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 30-7. connection of 2x16-bit data bus on a 32-bit data bus (byte select option) smc nwe nrd ncs[3] write enable read enable memory enable nbs0 d[15:0] d[15:0] d[31:16] a[25:2] a[23:0] write enable read enable memory enable d[31:16] a[23:0] low byte enable high byte enable low byte enable high byte enable nbs1 nbs2 nbs3 table 30-3. smc multiplexed signal translation signal name 32-bit bus 16-bit bus 8-bit bus device type 1x32-bit 2x16-bit 4 x 8- bit 1x16-bit 2 x 8-bit 1 x 8-bit byte access type (bat) byte select byte select byte write byte select byte write nbs0_a0 nbs0 nbs0 nbs0 a0 nwe_nwr0 nwe nwe nwr0 nwe nwr0 nwe nbs1_nwr1 nbs1 nbs1 nwr1 nbs1 nwr1 nbs2_nwr2_a1 nbs2 nbs2 nwr2 a1 a1 a1 nbs3_nwr3 nbs3 nbs3 nwr3
393 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 30.9 standard read and write protocols in the following sections, the byte access type is not considered. byte select lines (nbs0 to nbs3) always have the same timing as the a address bus. nwe represents either the nwe sig- nal in byte select access type or one of the byte write lines (nwr0 to nwr3) in byte write access type. nwr0 to nwr3 have the same ti mings and protocol as nwe. in the same way, ncs represents one of the ncs[0..5] chip select lines. 30.9.1 read waveforms the read cycle is shown on figure 30-8 . the read cycle starts with the address setting on the memory address bus, i.e.: {a[25:2], a1, a0} for 8-bit devices {a[25:2], a1} for 16-bit devices a[25:2] for 32-bit devices. figure 30-8. standard read cycle 30.9.1.1 nrd waveform the nrd signal is characterized by a setup timing, a pulse width and a hold timing. 1. nrd_setup: the nrd setup time is defined as the setup of address before the nrd falling edge; 2. nrd_pulse: the nrd pulse length is the time between nrd falling edge and nrd rising edge; 3. nrd_hold: the nrd hold time is defined as the hold time of a ddress after the nrd rising edge. a[25:2] nbs0,nbs1, nbs2,nbs3, a0, a1 ncs nrd_setup nrd_pulse nrd_hold mck nrd d[31:0] ncs_rd_setup ncs_rd_pulse ncs_rd_hold nrd_cycle
394 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 30.9.1.2 ncs waveform similarly, the ncs signal can be divided into a setup time, pulse length and hold time: 1. ncs_rd_setup: the ncs setup time is defined as the setup time of address before the ncs falling edge. 2. ncs_rd_pulse: the ncs pulse length is the time between ncs falling edge and ncs rising edge; 3. ncs_rd_hold: the ncs hold time is defined as the hold time of address after the ncs rising edge. 30.9.1.3 read cycle the nrd_cycle time is defined as the total duration of the read cycle, i.e., from the time where address is set on the address bus to the point where address may change. the total read cycle time is equal to: nrd_cycle = nrd_setup + nrd_pulse + nrd_hold = ncs_rd_setup + ncs_rd_pulse + ncs_rd_hold all nrd and ncs timings are defined separately for each chip select as an integer number of master clock cycles. to ensure that the nrd and ncs timings are coherent, user must define the total read cycle instead of the hold timing. nrd_cycle implicitly defines the nrd hold time and ncs hold time as: nrd_hold = nrd_cycle - nrd setup - nrd pulse ncs_rd_hold = nrd_cycle - ncs_rd_setup - ncs_rd_pulse 30.9.1.4 null delay setup and hold if null setup and hold parame ters are programmed for nrd and/or ncs, nrd and ncs remain active continuously in case of consecutive read cycles in the same memory (see figure 30-9 ).
395 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 30-9. no setup, no hold on nrd and ncs read signals 30.9.1.5 null pulse programming null pulse is not permitted. pulse must be at least set to 1. a null value leads to unpredictable behavior. 30.9.2 read mode as ncs and nrd waveforms are defined independently of one other, the smc needs to know when the read data is available on the data bus. the smc does not compare ncs and nrd tim- ings to know which signal rises first. the r ead_mode parameter in the smc_mode register of the corresponding chip select indicates wh ich signal of nrd and ncs controls the read operation. 30.9.2.1 read is controlled by nrd (read_mode = 1): figure 30-10 shows the waveforms of a read operation of a typical asynchronous ram. the read data is available t pacc after the falling edge of nrd, and turn s to z after the rising edge of nrd. in this case, the read_mode must be set to 1 (read is controlled by nrd), to indicate that data is available with the rising edge of nrd. the smc samples the read data internally on the rising edge of master clock that generates the rising edge of nrd, whatever the pro- grammed waveform of ncs may be. mck nrd_pulse ncs_rd_pulse nrd_cycle nrd_pulse nrd_pulse ncs_rd_pulse ncs_rd_pulse nrd_cycle nrd_cycle a[25:2] nbs0,nbs1, nbs2,nbs3, a0, a1 ncs nrd d[31:0]
396 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 30-10. read_mode = 1: data is sampled by smc before the rising edge of nrd 30.9.2.2 read is controlled by ncs (read_mode = 0) figure 30-11 shows the typical read cycle of an lcd module. the read data is valid t pacc after the falling edge of the ncs signal and remains va lid until the rising edge of ncs. data must be sampled when ncs is raised. in that case, the read_mode must be set to 0 (read is controlled by ncs): the smc internally samples the data on the rising edge of master clock that generates the rising edge of ncs, whatever the programmed waveform of nrd may be. figure 30-11. read_mode = 0: data is sampled by smc before the rising edge of ncs data sampling t pacc mck a[25:2] nbs0,nbs1, nbs2,nbs3, a0, a1 ncs nrd d[31:0] data sampling t pacc mck d[31:0] a[25:2] nbs0,nbs1, nbs2,nbs3, a0, a1 ncs nrd
397 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 30.9.3 write waveforms the write protocol is similar to the read protocol. it is depicted in figure 30-12 . the write cycle starts with the address setting on the memory address bus. 30.9.3.1 nwe waveforms the nwe signal is characterized by a setu p timing, a pulse width and a hold timing. 1. nwe_setup: the nwe setup time is defined as the setup of address and data before the nwe falling edge; 2. nwe_pulse: the nwe pulse length is the time between nwe falling edge and nwe rising edge; 3. nwe_hold: the nwe hold time is defined as the hold time of address and data after the nwe rising edge. the nwe waveforms apply to all byte-write lines in byte write access mode: nwr0 to nwr3. 30.9.3.2 ncs waveforms the ncs signal waveforms in write operation are not the same that those applied in read opera- tions, but are separately defined: 1. ncs_wr_setup: the ncs setup time is defined as the setup time of address before the ncs falling edge. 2. ncs_wr_pulse: the ncs pulse length is the time between ncs falling edge and ncs rising edge; 3. ncs_wr_hold: the ncs hold time is defined as the hold time of address after the ncs rising edge. figure 30-12. write cycle a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1 ncs nwe_setup nwe_pulse nwe_hold mck nwe ncs_wr_setup ncs_wr_pulse ncs_wr_hold nwe_cycle
398 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 30.9.3.3 write cycle the write_cycle time is defined as the total durat ion of the write cycle, that is, from the time where address is set on the address bus to the point where address may change. the total write cycle time is equal to: nwe_cycle = nwe_setup + nwe_pulse + nwe_hold = ncs_wr_setup + ncs_wr_pulse + ncs_wr_hold all nwe and ncs (write) timings are defined separately for each chip select as an integer num- ber of master clock cycles. to ensure that the nwe and ncs timings are coherent, the user must define the total wr ite cycle instead of the hold timing. this implicitly defines the nwe hold time and ncs (write) hold times as: nwe_hold = nwe_cycle - nwe_setup - nwe_pulse ncs_wr_hold = nwe_cycle - ncs_wr_setup - ncs_wr_pulse 30.9.3.4 null delay setup and hold if null setup parameters are programmed for nwe and/or ncs, nwe and/or ncs remain active continuously in case of consecutive write cycles in the same memory (see figure 30-13 ). how- ever, for devices that perform write operations on the rising edge of nwe or ncs, such as sram, either a setup or a hold must be programmed. figure 30-13. null setup and hold values of ncs and nwe in write cycle 30.9.3.5 null pulse programming null pulse is not permitted. pulse must be at least set to 1. a null value leads to unpredictable behavior. ncs mck nwe, nwr0, nwr1, nwr2, nwr3 d[31:0] nwe_pulse ncs_wr_pulse nwe_cycle nwe_pulse ncs_wr_pulse nwe_cycle nwe_pulse ncs_wr_pulse nwe_cycle a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1
399 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 30.9.4 write mode the write_mode parameter in th e smc_mode register of the corresponding chip select indi- cates which signal controls the write operation. 30.9.4.1 write is controlled by nwe (write_mode = 1): figure 30-14 shows the waveforms of a write operation with write_mode set to 1. the data is put on the bus during the pulse and hold steps of the nwe signal. the internal data buffers are turned out after the nwe_setup time, and until the end of the write cycle, regardless of the programmed waveform on ncs. figure 30-14. write_mode = 1. the write op eration is controlled by nwe 30.9.4.2 write is controlle d by ncs (write_mode = 0) figure 30-15 shows the waveforms of a write operation with write_mode set to 0. the data is put on the bus during the pulse and hold steps of the ncs signal. the internal data buffers are turned out after the ncs_wr_setup time, and until the end of the write cycle, regardless of the programmed waveform on nwe. mck d[31:0] ncs a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1 nwe, nwr0, nwr1, nwr2, nwr3
400 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 30-15. write_mode = 0. the write op eration is controlled by ncs 30.9.5 write protected registers to prevent any single software error that may corrupt smc behavior, the registers listed below can be write-protected by setting the wpen bit in the smc write protect mode register (smc_wpmr). if a write access in a write-protected register is detected, then the wpvs flag in the smc write protect status register (smc_wpsr) is set and the field wpvsrc indicates in which register the write access has been attempted. the wpvs flag is automatically reset after reading the smc write protect status register (smc_wpsr). list of the write-protected registers: ? section 30.16.1 smc setup register ? section 30.16.2 smc pulse register ? section 30.16.3 smc cycle register ? section 30.16.4 smc mode register ? section 30.16.5 smc delay i/o register 30.9.6 coding timing parameters all timing parameters are defined for one chip select and are grouped together in one smc_register according to their type. the smc_setup register groups the definition of all setup parameters: ? nrd_setup, ncs_rd_setup, nwe_setup, ncs_wr_setup the smc_pulse register groups the definition of all pulse parameters: ? nrd_pulse, ncs_rd_pulse, nwe_pulse, ncs_wr_pulse the smc_cycle register groups the definition of all cycle parameters: ? nrd_cycle, nwe_cycle mck d[31:0] ncs nwe, nwr0, nwr1, nwr2, nwr3 a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1
401 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 table 30-4 shows how the timing parameters are coded and their permitted range. 30.9.7 reset values of timing parameters table 30-8, register mapping, on page 422 gives the default value of timing parameters at reset. 30.9.8 usage restriction the smc does not check the validity of the user-programmed parameters. if the sum of setup and pulse parameters is larger than the corresponding cycle parameter, this leads to unpre- dictable behavior of the smc. for read operations: null but positive setup and hold of address and nrd and/or ncs can not be guaranteed at the memory interface because of the propagation dela y of theses signals through external logic and pads. if positive setup and hold values must be verified, then it is strictly recommended to pro- gram non-null values so as to cover possible skews between address, ncs and nrd signals. for write operations: if a null hold value is programmed on nwe, the smc can guarantee a positive hold of address, byte select lines, and ncs signal after the rising edge of nwe. this is true for write_mode = 1 only. see early read wait state on page 402 . for read and write operations: a null value for pulse parameters is forbidden and may lead to unpredictable behavior. in read and write cycles, the setup and hold time parameters are defined in reference to the address bus. for external devices that require setup and hold time between ncs and nrd sig- nals (read), or between ncs and nwe signals (write), these setup and hold times must be converted into setup and hold times in reference to the address bus. 30.10 automatic wait states under certain circumstances, the smc automatica lly inserts idle cycles between accesses to avoid bus contention or operation conflict. 30.10.1 chip select wait states the smc always inserts an idle cycle between 2 transfers on separate chip selects. this idle cycle ensures that there is no bus contention between the de-activation of one device and the activation of the next one. during chip select wait state, all control li nes are turned inactive: nbs0 to nbs3, nwr0 to nwr3, ncs[0..5], nrd lines are all set to 1. table 30-4. coding and range of timing parameters coded value number of bits effective value permitted range coded value effective value setup [5:0] 6 128 x setup[5] + setup[4:0] 0 31 0 128+31 pulse [6:0] 7 256 x pulse[6] + pulse[5:0] 0 63 0 256+63 cycle [8:0] 9 256 x cycle[8:7] + cycle[6:0] 0 127 0 256+127 0 512+127 0 768+127
402 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 30-16 illustrates a chip select wait state between access on chip select 0 and chip select 2. figure 30-16. chip select wait state between a read access on ncs0 and a write access on ncs2 30.10.2 early read wait state in some cases, the smc inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins. this wait state is not generated in addition to a chip select wait state. the early read cycle thus only occurs between a write and read access to the same memory device (same chip select). an early read wait state is automatically inserted if at least one of the following conditions is valid: ? if the write controlling signal has no hold time and the read controlling signal has no setup time ( figure 30-17 ). ? in ncs write controlled mode (write_mode = 0), if there is no hold timing on the ncs signal and the ncs_rd_setup parameter is set to 0, regardless of the read mode ( figure 30-18 ). the write operation must end with a ncs rising edge. without an early read wait state, the write operation could not complete properly. ? in nwe controlled mode (write_mode = 1) and if there is no hold timing (nwe_hold = 0), the feedback of the write control signal is used to control address, data, chip select and byte select lines. if the external write control signal is not inactivated as expected due to load capacitances, an early read wait state is inserted and address, data and control signals are maintained one more cycle. see figure 30-19 . a[25:2] nbs0, nbs1, nbs2, nbs3, a0,a1 ncs0 nrd_cycle chip select wait state nwe_cycle mck ncs2 nrd nwe d[31:0] read to write wait state
403 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 30-17. early read wait state: write with no hold followe d by read with no setup figure 30-18. early read wait state: ncs cont rolled write with no hold followed by a read with no ncs setup write cycle early read wait state mck nrd nwe read cycle no setup no hold d[31:0] nbs0, nbs1, nbs2, nbs3, a0, a1 a[25:2] write cycle (write_mode = 0) early read wait state mck nrd ncs read cycle (read_mode = 0 or read_mode = 1) no setup no hold d[31:0] nbs0, nbs1, nbs2, nbs3, a0,a1 a[25:2]
404 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 30-19. early read wait state: nwe-controlled write with no hold followed by a read with one set-up cycle 30.10.3 reload user configuration wait state the user may change any of the configuration parameters by writing the smc user interface. when detecting that a new user configuration has been written in the user interface, the smc inserts a wait state before starting the next access. the so called reload user configuration wait state is used by the smc to load the new set of parameters to apply to next accesses. the reload configuration wait state is not applied in addition to the chip select wait state. if accesses before and after re-programming the user interface are made to different devices (chip selects), then one single chip select wait state is applied. on the other hand, if accesses before and after writing the user interface are made to the same device, a reload configuration wait state is inserted, even if the change does not concern the current chip select. 30.10.3.1 user procedure to insert a reload configuration wait state, the smc detects a write access to any smc_mode register of the user interface. if the user only modifies timing registers (smc_setup, smc_pulse, smc_cycle registers) in the user interface, he must validate the modification by writing the smc_mode, even if no change was made on the mode parameters. the user must not change the configuration parameters of an smc chip select (setup, pulse, cycle, mode) if accesses are performed on this cs during the modification. any change of the chip select parameters, while fetching the code from a memory connected on this cs, may lead a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1 write cycle (write_mode = 1) early read wait state mck nrd internal write controlling signal external write controlling signal (nwe) d[31:0] read cycle (read_mode = 0 or read_mode = 1) no hold read setup = 1
405 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 to unpredictable behavior. the instructions used to modify the parameters of an smc chip select can be executed from the internal ram or from a memory connected to another cs. 30.10.3.2 slow clock mode transition a reload configuration wait state is also inserted when the slow clock mode is entered or exited, after the end of the current transfer (see slow clock mode on page 415 ). 30.10.4 read to write wait state due to an internal mechanism, a wait cycle is always inserted between consecutive read and write smc accesses. this wait cycle is referred to as a read to write wait stat e in this document. this wait cycle is applied in add ition to chip select and reload user configuration wait states when they are to be inserted. see figure 30-16 on page 402 . 30.11 data float wait states some memory devices are slow to release the exte rnal bus. for such devices, it is necessary to add wait states (data float wait states) after a read access: ? before starting a read access to a different external memory ? before starting a write access to the same device or to a different external one. the data float output time (t df ) for each external memory device is programmed in the tdf_cycles field of the smc_mode register for the corresponding chip select. the value of tdf_cycles indicates the number of data float wait cycles (between 0 and 15) before the external device releases the bus, and represents the time allowed for the data output to go to high impedance after the memory is disabled. data float wait states do not delay internal memory accesses. hence, a single access to an external memory with long t df will not slow down the executio n of a program from internal memory. the data float wait states management depends on the read_mode and the tdf_mode fields of the smc_mode register for the corresponding chip select. 30.11.1 read_mode setting the read_mode to 1 indicates to the smc that the nrd signal is responsible for turn- ing off the tri-state buffers of the external memory device. the data float period then begins after the rising edge of the nrd sign al and lasts tdf_cycles mck cycles. when the read operation is controlled by the ncs signal (read_mode = 0), the tdf field gives the number of mck cycles during which the data bus remains busy after the rising edge of ncs. figure 30-20 illustrates the data float period in nrd-controlled mode (read_mode =1), assuming a data float period of 2 cycles (tdf_cycles = 2). figure 30-21 shows the read oper- ation when controlled by ncs (read_mode = 0) and the tdf_cycles parameter equals 3.
406 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 30-20. tdf period in nrd controlled read access (tdf = 2) figure 30-21. tdf period in ncs controlled read operation (tdf = 3) nbs0, nbs1, nbs2, nbs3, a0, a1 ncs nrd controlled read operation tpacc mck nrd d[31:0] tdf = 2 clock cycles a[25:2] ncs tdf = 3 clock cycles tpacc mck d[31:0] ncs controlled read operation a[25:2] nbs0, nbs1, nbs2, nbs3, a0,a1 nrd
407 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 30.11.2 tdf optimization enabled (tdf_mode = 1) when the tdf_mode of the smc_mode register is set to 1 (tdf optimization is enabled), the smc takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert. figure 30-22 shows a read access controlled by nrd, followed by a write access controlled by nwe, on chip select 0. chip se lect 0 has been programmed with: nrd_hold = 4; read_mode = 1 (nrd controlled) nwe_setup = 3; write_mode = 1 (nwe controlled) tdf_cycles = 6; tdf_mode = 1 (optimization enabled). figure 30-22. tdf optimization: no tdf wait states are inserted if the tdf period is over when the next access begins 30.11.3 tdf optimization disabled (tdf_mode = 0) when optimization is disabled, tdf wait states are inserted at the end of the read transfer, so that the data float period is ended when the second access begins. if the hold period of the read1 controlling signal overlaps the data float period, no additional tdf wait st ates will be inserted. figure 30-23 , figure 30-24 and figure 30-25 illustrate the cases: ? read access followed by a read access on another chip select, ? read access followed by a write access on another chip select, ? read access followed by a write access on the same chip select, with no tdf optimization. a [25:2] ncs0 mck nrd nwe d[31:0] read to write wait state tdf_cycles = 6 read access on ncs0 (nrd controlled) nrd_hold= 4 nwe_setup= 3 write access on ncs0 (nwe controlled)
408 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 30-23. tdf optimization disabled (tdf mode = 0). tdf wait states between 2 read accesses on different chip selects figure 30-24. tdf mode = 0: tdf wait states between a read and a write access on different chip selects tdf_cycles = 6 tdf_cycles = 6 tdf_mode = 0 (optimization disabled) a[ 25:2] read1 cycle chip select wait state mck read1 controlling signal (nrd) read2 controlling signal (nrd) d[31:0] read1 hold = 1 read 2 cycle read2 setup = 1 5 tdf wait states nbs0, nbs1, nbs2, nbs3, a0, a1 tdf_cycles = 4 tdf_cycles = 4 tdf_mode = 0 (optimization disabled) a [25:2] read1 cycle chip select wait state read to write wait state mck read1 controlling signal (nrd) write2 controlling signal (nwe) d[31:0] read1 hold = 1 write2 cycle write2 setup = 1 2 tdf wait states nbs0, nbs1, nbs2, nbs3, a0, a1
409 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 30-25. tdf mode = 0: tdf wait states between read and write accesses on the same chip select 30.12 external wait any access can be extended by an external device using the nw ait input signal of the smc. the exnw_mode field of the smc_mode register on the corresponding chip select must be set to either to 10 (frozen mode) or 11 (ready mode). when the exnw_mode is set to 00 (disabled), the nwait signal is simply ignored on the correspo nding chip select. the nwait signal delays the read or write operation in regards to the read or write controlling signal, depending on the read and write modes of the corresponding chip select. 30.12.1 restriction when one of the exnw_mode is enabled, it is mandatory to program at least one hold cycle for the read/write controlling signal. for that reason, the nwait signal cannot be used in page mode ( ?asynchronous page mode? on page 418 ), or in slow clock mode ( ?slow clock mode? on page 415 ). the nwait signal is assumed to be a response of the external device to the read/write request of the smc. then nwait is examined by the smc only in the pulse state of the read or write controlling signal. the assertion of the nwait signal outside th e expected period has no impact on smc behavior. tdf_cycles = 5 tdf_cycles = 5 tdf_mode = 0 (optimization disabled) a [25:2] read1 cycle read to write wait state mck read1 controlling signal (nrd) write2 controlling signal (nwe) d[31:0] read1 hold = 1 write2 cycle write2 setup = 1 4 tdf wait states nbs0, nbs1, nbs2, nbs3, a0, a1
410 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 30.12.2 frozen mode when the external device asserts the nwait signal (active low), and after internal synchroniza- tion of this signal, the smc state is frozen, i.e., smc internal counters are frozen, and all control signals remain unchanged. when the resynchronized nwait signal is deasserted, the smc completes the access, resuming the access from the point where it was stopped. see figure 30- 26 . this mode must be selected when the external device uses the nwait signal to delay the access and to freeze the smc. the assertion of the nwait sign al outside the expected period is ignored as illustrated in figure 30-27 . figure 30-26. write access with nwait assertion in frozen mode (exnw_mode = 10) exnw_mode = 10 (frozen) write_mode = 1 (nwe_controlled) nwe_pulse = 5 ncs_wr_pulse = 7 a [25:2] mck nwe ncs 432 1 110 1 4 5 63 2 2 2 2 1 0 write cycle d[31:0] nwait frozen state nbs0, nbs1, nbs2, nbs3, a0,a1 internally synchronized nwait signal
411 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 30-27. read access with nwait assertion in frozen mode (exnw_mode = 10) exnw_mode = 10 (frozen) read_mode = 0 (ncs_controlled) nrd_pulse = 2, nrd_hold = 6 ncs_rd_pulse =5, ncs_rd_hold =3 a [25:2] mck ncs nrd 10 43 43 2 555 22 0 210 210 1 read cycle assertion is ignored nwait internally synchronized nwait signal frozen state nbs0, nbs1, nbs2, nbs3, a0,a1
412 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 30.12.3 ready mode in ready mode (exnw_mode = 11), the smc behaves differently. normally, the smc begins the access by down counting the setup and pulse counters of the read/write controlling signal. in the last cycle of the pulse phase, the resynchronized nwait signal is examined. if asserted, the smc suspends the access as shown in figure 30-28 and figure 30-29 . after deassertion, the access is completed: the hold step of the access is performed. this mode must be selected when the external de vice uses deassertion of the nwait signal to indicate its ability to complete the read or write operation. if the nwait signal is deasserted before the end of the pulse, or asserted after the end of the pulse of the controlling read/write signal, it has no impact on the access length as shown in fig- ure 30-29 . figure 30-28. nwait assertion in write access: ready mode (exnw_mode = 11) exnw_mode = 11 (ready mode) write_mode = 1 (nwe_controlled) nwe_pulse = 5 ncs_wr_pulse = 7 a [25:2] mck nwe ncs 432 1 00 0 4 5 63 2 1 1 1 0 write cycle d[31:0] nwait internally synchronized nwait signal wait state nbs0, nbs1, nbs2, nbs3, a0,a1
413 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 30-29. nwait assertion in read access: ready mode (exnw_mode = 11) exnw_mode = 11(ready mode) read_mode = 0 (ncs_controlled) nrd_pulse = 7 ncs_rd_pulse =7 a[25:2] mck ncs nrd 4 5 63200 0 1 4 5 63 2 1 1 read cycle assertion is ignored nwait internally synchronized nwait signal wait state assertion is ignored nbs0, nbs1, nbs2, nbs3, a0,a1
414 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 30.12.4 nwait latency and read/write timings there may be a latency between the assertion of the read/w rite controlling signal and the asser- tion of the nwait signal by the device. t he programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1 cycle. otherwise, the smc may enter the hold state of the access without detecting the nwait signal assertion. this is true in frozen mode as well as in ready mode. th is is illustrated on figure 30-30 . when exnw_mode is enabled (ready or frozen), th e user must program a pulse length of the read and write controllin g signal of at least: minimal pulse length = nwait latency + 2 resynchronization cycles + 1 cycle figure 30-30. nwait latency exnw_mode = 10 or 11 read_mode = 1 (nrd_controlled) nrd_pulse = 5 a [25:2] mck nrd 43 210 0 0 read cycle minimal pulse length nwait latency nwait intenally synchronized nwait signal wait state 2 cycle resynchronization nbs0, nbs1, nbs2, nbs3, a0,a1
415 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 30.13 slow clock mode the smc is able to automatically apply a set of slow clock mode read/write waveforms when an internal signal driven by the power management controller is asserted because mck has been turned to a very slow clock rate (typically 32khz clock rate). in this mode, the user-pro- grammed waveforms are ignored and the slow clock mode waveforms are applied. this mode is provided so as to avoid reprogramming the user interface with appropriate waveforms at very slow clock rate. when activated, the sl ow mode is active on all chip selects. 30.13.1 slow clock mode waveforms figure 30-31 illustrates the read and write operations in slow clock mode. they are valid on all chip selects. table 30-5 indicates the value of read and write parameters in slow clock mode. figure 30-31. read/write cycles in slow clock mode a[ 25:2] ncs 1 mck nwe 1 1 nwe_cycle = 3 a [25:2] mck nrd nrd_cycle = 2 1 1 ncs slow clock mode write slow clock mode read nbs0, nbs1, nbs2, nbs3, a0,a1 nbs0, nbs1, nbs2, nbs3, a0,a1 table 30-5. read and write timing parameters in slow clock mode read parameters duration (cycles) write parameters duration (cycles) nrd_setup 1 nwe_setup 1 nrd_pulse 1 nwe_pulse 1 ncs_rd_setup 0 ncs_wr_setup 0 ncs_rd_pulse 2 ncs_wr_pulse 3 nrd_cycle 2 nwe_cycle 3
416 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 30.13.2 switching from (to) slow clock mode to (from) normal mode when switching from slow clock mode to the nor mal mode, the current slow clock mode transfer is completed at high clock rate, with the set of slow clock mode parameters.see figure 30-32 on page 416 . the external device may not be fast enough to support such timings. figure 30-33 illustrates the recommended procedure to properly switch from one mode to the other. figure 30-32. clock rate transition occurs while the smc is performing a write operation a [25:2] ncs 1 mck nwe 1 1 nwe_cycle = 3 slow clock mode write slow clock mode internal signal from pmc 11 1 2 3 2 nwe_cycle = 7 normal mode write slow clock mode transition is detected: reload configuration wait state this write cycle finishes with the slow clock mode set of parameters after the clock rate transition slow clock mode write nbs0, nbs1, nbs2, nbs3, a0,a1
417 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 30-33. recommended procedure to switch from slow clock mo de to normal mode or from normal mode to slow clock mode a [25:2] ncs 1 mck nwe 1 1 slow clock mode write slow clock mode internal signal from pmc 2 3 2 normal mode write idle state reload configuration wait state nbs0, nbs1, nbs2, nbs3, a0,a1
418 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 30.14 asynchronous page mode the smc supports asynchronous burst reads in page mode, providing that the page mode is enabled in the smc_mode register (pmen field). the page size must be configured in the smc_mode register (ps field) to 4, 8, 16 or 32 bytes. the page defines a set of consecutive bytes into memory. a 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. the msb of data address defines the address of the page in memory, the lsb of address define the address of the data in the page as detailed in table 30-6 . with page mode memory devices, the first access to one page (t pa ) takes longer than the subse- quent accesses to the page (t sa ) as shown in figure 30-34 . when in page mode, the smc enables the user to define different read timings for the first access within one page, and next accesses withi n the page. notes: 1. a denotes the address bus of the memory device 2. for 16-bit devices, the bit 0 of address is ignored. for 32-bit devices, bits [1:0] are ignored. 30.14.1 protocol and timings in page mode figure 30-34 shows the nrd and ncs timings in page mode access. figure 30-34. page mode read protocol (address msb and lsb are defined in table 30-6 ) the nrd and ncs signals are held low during all read transfers, whatever the programmed val- ues of the setup and hold timings in the us er interface may be. moreover, the nrd and ncs table 30-6. page address and data address within a page page size page address (1) data address in the page (2) 4 bytes a[25:2] a[1:0] 8 bytes a[25:3] a[2:0] 16 bytes a[25:4] a[3:0] 32 bytes a[25:5] a[4:0] a[msb] ncs mck nrd d[31:0] ncs_rd_pulse nrd_pulse nrd_pulse tsa tpa tsa a[lsb]
419 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 timings are identical. the pulse length of the first access to the page is defined with the ncs_rd_pulse field of the smc_pulse register. the pulse length of subsequent accesses within the page are defined using the nrd_pulse parameter. in page mode, the programming of the read timings is described in table 30-7 : the smc does not check the coherency of timings. it will always apply the ncs_rd_pulse timings as page access timing (t pa ) and the nrd_pulse for accesses to the page (t sa ), even if the programmed value for t pa is shorter than the programmed value for t sa . 30.14.2 byte access type in page mode the byte access type configuration remains active in page mode. for 16-bit or 32-bit page mode devices that require byte selection signals, configure the bat field of the smc_register to 0 (byt e select access type). 30.14.3 page mode restriction the page mode is not compatible with the use of the nwait signal. using the page mode and the nwait signal may lead to unpredictable behavior. 30.14.4 sequential and non-sequential accesses if the chip select and the msb of addresses as defined in table 30-6 are identical, then the cur- rent access lies in the same page as the previous one, and no page break occurs. using this information, all data within the same page, sequential or not sequential, are accessed with a minimum access time (t sa ). figure 30-35 illustrates access to an 8-bit memory device in page mode, with 8-byte pages. access to d1 causes a page access with a long access time (t pa ). accesses to d3 and d7, though they are not sequential accesses, only require a short access time (t sa ). if the msb of addresses are different, the smc performs the access of a new page. in the same way, if the chip select is diffe rent from the previous access, a page break occurs. if two sequen- tial accesses are made to the page mode memory , but separated by an other internal or external peripheral access, a page break occurs on the second access because the chip select of the device was deasserted between both accesses. table 30-7. programming of read timings in page mode parameter value definition read_mode x no impact ncs_rd_setup x no impact ncs_rd_pulse t pa access time of first access to the page nrd_setup x no impact nrd_pulse t sa access time of subsequent accesses in the page nrd_cycle x no impact
420 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 30-35. access to non-sequential data within the same page a [25:3] a[2], a1, a0 ncs mck nrd page address a1 a3 a7 d[7:0] ncs_rd_pulse nrd_pulse nrd_pulse d1 d3 d7
421 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 30.15 programmable io delays the external bus interface consists of a data bus, an address bus and control signals. the simul- taneous switching outputs on these busses may lead to a peak of current in the internal and external power supply lines. in order to reduce the peak of current in such cases, additional propagation delays can be adjusted independently for pad buffers by means of configuration registers, smc_delay1-8. the additional programmable delays for each io range from 0 to 4 ns (worst case pvt). the delay can differ between ios supporting this feature. delay can be modified per programming for each io. the minimal additional delay that can be programmed on a pad supporting this feature is 1/16 of the maximum programmable delay. when programming 0x0 in fields delay1 to de lay 8, no delay is added (reset value) and the propagation delay of the pad buffers is the inherent delay of the pad buffer. when programming 0xf in field delay1 the propagation del ay of the corresponding pad is maximal. smc_delay1, smc_delay2 allow to configur e delay on d[15:0], smc_delay1[3:0] corre- sponds to d[0] and smc_delay2[3:0] corresponds to d[8]. smc_delay3, smc_delay4 allow to configure delay on d[31:16], smc_delay3[3:0] corre- sponds to d[16] and smc_delay4[3:0] corresponds to d[24]. in case of multiplexing through the pio controller, refer to the alternate function of d[31:16]. smc_delay5, 6, 7 and 8 allow to configure delay on a[25:0], smc_delay5[3:0] corresponds to a[0]. in case of multiplexing through the pio controller, refer to the alternate function of a[25:0]. figure 30-36. programmable io delays delay1 d[0] programmable delay line smc d_out[0] d_in[0] delay2 d[1] programmable delay line d_out[1] d_in[1] delayx d[n] programmable delay line d_out[n] d_in[n] pio a[m] programmable delay line pio delayy a[m]
422 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 30.16 static memory contro ller (smc) user interface the smc is programmed using the registers listed in table 30-8 . for each chip select, a set of 4 registers is used to pro- gram the parameters of the exter nal device connected on it. in table 30-8 , cs_number denotes the chip select number. 16 bytes (0x10) are required per chip select. the user must complete writing the configuration by writing any one of the smc_mode registers. table 30-8. register mapping offset register name access reset 0x10 x cs_number + 0x00 smc setup register smc_setup read-write 0x00000000 0x10 x cs_number + 0x04 smc pulse register smc_pulse read-write 0x01010101 0x10 x cs_number + 0x08 smc cycle register smc_cycle read-write 0x00030003 0x10 x cs_number + 0x0c smc mode register smc_mode read-write 0x10001000 0xc0 smc delay on i/o smc_delay1 read-write 0x00000000 0xc4 smc delay on i/o smc_delay2 read-write 0x00000000 0xc8 smc delay on i/o smc_delay3 read-write 0x00000000 0xcc smc delay on i/o smc_delay4 read-write 0x00000000 0xd0 smc delay on i/o smc_delay5 read-write 0x00000000 0xd4 smc delay on i/o smc_delay6 read-write 0x00000000 0xd8 smc delay on i/o smc_delay7 read-write 0x00000000 0xdc smc delay on i/o smc_delay8 read-write 0x00000000 0xe4 smc write protect mode register smc_wpmr read-write 0x00000000 0xe8 smc write protect status register smc_wpsr read-only 0x00000000 0xec-0xfc reserved - - -
423 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 30.16.1 smc setup register name: smc_setup[0..5] addresses: 0xffffea00 [0], 0xffffea10 [1], 0xffffea20 [2], 0xffffea30 [3], 0xffffea40 [4], 0xffffea50 [5] access: read-write ? nwe_setup: nwe setup length the nwe signal setup length is defined as: nwe setup length = (128* nwe_setup [5] + nwe_setup[4:0]) clock cycles ? ncs_wr_setup: ncs setup length in write access in write access, the ncs signal setup length is defined as: ncs setup length = (128* ncs_wr_setup [5] + ncs_wr_setup[4:0]) clock cycles ? nrd_setup: nrd setup length the nrd signal setup length is defined in clock cycles as: nrd setup length = (128* nrd_setup[5] + nrd_setup[4:0]) clock cycles ? ncs_rd_setup: ncs setup length in read access in read access, the ncs signal setup length is defined as: ncs setup length = (128* ncs_rd_setup [5] + ncs_rd_setup[4:0]) clock cycles 31 30 29 28 27 26 25 24 C C ncs_rd_setup 23 22 21 20 19 18 17 16 C C nrd_setup 15 14 13 12 11 10 9 8 C C ncs_wr_setup 76543210 C C nwe_setup
424 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 30.16.2 smc pulse register name: smc_pulse[0..5] addresses: 0xffffea04 [0], 0xffffea14 [1], 0xffffea24 [2], 0xffffea34 [3], 0xffffea44 [4], 0xffffea54 [5] access: read-write ? nwe_pulse: nwe pulse length the nwe signal pulse length is defined as: nwe pulse length = (256* nwe_pulse[6] + nwe_pulse[5:0]) clock cycles the nwe pulse length must be at least 1 clock cycle. ? ncs_wr_pulse: ncs pulse length in write access in write access, the ncs signal pulse length is defined as: ncs pulse length = (256* ncs_wr_pul se[6] + ncs_wr_pulse[5:0]) clock cycles the ncs pulse length must be at least 1 clock cycle. ? nrd_pulse: nrd pulse length in standard read access, the nrd signal pulse length is defined in clock cycles as: nrd pulse length = (256* nrd_pulse[ 6] + nrd_pulse[5:0]) clock cycles the nrd pulse length must be at least 1 clock cycle. in page mode read access, the nrd_pulse parameter defines the duration of the subsequent accesses in the page. ? ncs_rd_pulse: ncs pulse length in read access in standard read access, the ncs signal pulse length is defined as: ncs pulse length = (256* ncs_rd_pul se[6] + ncs_rd_pulse[5:0]) clock cycles the ncs pulse length must be at least 1 clock cycle. in page mode read access, the ncs_rd_pulse parameter defines the duration of the first access to one page. 31 30 29 28 27 26 25 24 C ncs_rd_pulse 23 22 21 20 19 18 17 16 C nrd_pulse 15 14 13 12 11 10 9 8 C ncs_wr_pulse 76543210 Cn w e _ p u l s e
425 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 30.16.3 smc cycle register name: smc_cycle[0..5] addresses: 0xffffea08 [0], 0xffffea18 [1], 0xffffea28 [2], 0xffffea38 [3], 0xffffea48 [4], 0xffffea58 [5] access: read-write ? nwe_cycle: total write cycle length the total write cycle length is the total duration in clock cycles of the write cycle. it is equal to the sum of the setup, pul se and hold steps of the nwe and ncs signals. it is defined as: write cycle length = (nwe_cycle[8:7 ]*256 + nwe_cycle[6:0]) clock cycles ? nrd_cycle: total read cycle length the total read cycle length is the total duration in clock cycles of the read cycle. it is equal to the sum of the setup, pulse and hold steps of the nrd and ncs signals. it is defined as: read cycle length = (nrd_cycle[8:7] *256 + nrd_cycle[6:0]) clock cycles 31 30 29 28 27 26 25 24 CCCCCCCn r d _ c y c l e 23 22 21 20 19 18 17 16 nrd_cycle 15 14 13 12 11 10 9 8 CCCCCCCn w e _ c y c l e 76543210 nwe_cycle
426 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 30.16.4 smc mode register name: smc_mode[0..5] addresses: 0xffffea0c [0], 0xffffea1c [1], 0xffffea2c [2], 0xffffea3c [3], 0xffffea4c [4], 0xffffea5c [5] access: read-write ? read_mode: 1: the read operation is controlled by the nrd signal. C if tdf cycles are programmed, the external bus is marked busy after the rising edge of nrd. C if tdf optimization is enabled (tdf_mode =1), tdf wait states are inserted after the setup of nrd. 0: the read operation is controlled by the ncs signal. C if tdf cycles are programmed, the external bus is marked busy after the rising edge of ncs. C if tdf optimization is enabled (tdf_mode =1), tdf wait states are inserted after the setup of ncs. ?write_mode 1: the write operation is controlled by the nwe signal. C if tdf optimization is enabled (tdf_mode =1), tdf wa it states will be inserted after the setup of nwe. 0: the write operation is controlled by the ncs signal. C if tdf optimization is enabled (tdf_mode =1), tdf wa it states will be inserted after the setup of ncs. ? exnw_mode: nwait mode the nwait signal is used to extend the current read or writ e signal. it is only taken into account during the pulse phase of the read and writ e controlling signal. when the use of nwait is enable d, at least one cycle hold duration mu st be pro- grammed for the read and write controlling signal. ? disabled mode: the nwait input signal is ignored on the corresponding chip select. ? frozen mode: if asserted, the nwait signal freezes the current read or write cycle. after deassertion, the read/write cycle is resumed from the point where it was stopped. 31 30 29 28 27 26 25 24 CC p s CCCp m e n 23 22 21 20 19 18 17 16 C C C tdf_mode tdf_cycles 15 14 13 12 11 10 9 8 CC d b w CCCb a t 76543210 C C exnw_mode C C write_mode read_mode exnw_mode nwait mode 00d i s a b l e d 01r e s e r v e d 1 0 frozen mode 1 1 ready mode
427 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? ready mode: the nwait si gnal indicates the availa bility of the external device at t he end of the pulse of the controlling read or write signal, to complete the access. if high, the access normally completes. if low, the access is extended until nwait returns high. ? bat: byte access type this field is used only if dbw defines a 16- or 32-bit data bus. ? 1: byte write access type: C write operation is controlled us ing ncs, nwr0, nwr1, nwr2, nwr3. C read operation is controlled using ncs and nrd. ? 0: byte select access type: C write operation is controlled using ncs, nwe, nbs0, nbs1, nbs2 and nbs3 C read operation is controlled using ncs, nrd, nbs0, nbs1, nbs2 and nbs3 ? dbw: data bus width ? tdf_cycles: data float time this field gives the integer number of clock cycles required by the external device to release the data after the rising edge of the read controlling signal. the smc always provide one full cycle of bus turnaround after the tdf_cycles period. the external bus cannot be used by another chip select during tdf_cycles + 1 cycles. from 0 up to 15 tdf_cycles can be set. ? tdf_mode: tdf optimization 1: tdf optimization is enabled. C the number of tdf wait states is optimized using the setup period of the next read/write access. 0: tdf optimization is disabled. C the number of tdf wait states is inserted before the next access begins. ? pmen: page mode enabled 1: asynchronous burst read in page mode is applied on the corresponding chip select. 0: standard read is applied. ? ps: page size if page mode is enabled, this field indicates the size of the page in bytes. dbw data bus width 008 - b i t b u s 011 6 - b i t b u s 103 2 - b i t b u s 11r e s e r v e d ps page size 0 0 4-byte page 0 1 8-byte page 1 0 16-byte page 1 1 32-byte page
428 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 30.16.5 smc delay i/o register name: smc_delay 1-8 addresses: 0xffffeac0 [1] .. 0xffffeadc [8] access: read-write reset: see table 30-8 ? delay x: gives the number of elements in the delay line. 31 30 29 28 27 26 25 24 delay8 delay7 23 22 21 20 19 18 17 16 delay6 delay5 15 14 13 12 11 10 9 8 delay4 delay3 76543210 delay2 delay1
429 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 30.16.6 smc write protect mode register name: smc_wpmr address: 0xffffeae4 access: read-write reset: see table 30-8 ? wpen: write protect enable 0 = disables the write protect if wpkey co rresponds to 0x534d43 (smc in ascii). 1 = enables the write protect if wpkey corresponds to 0x534d43 (smc in ascii). protects the registers listed below: ? section 30.16.1 smc setup register ? section 30.16.2 smc pulse register ? section 30.16.3 smc cycle register ? section 30.16.4 smc mode register ? section 30.16.5 smc delay i/o register ? wpkey: write protect key should be written at value 0x534d43 (smc in ascii). writing an y other value in this field aborts the write operation of the wpen bit. always reads as 0. 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 CCCCCCCw p e n
430 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 30.16.7 smc write protect status register name: smc_wpsr address: 0xffffeae8 access: read-only reset: see table 30-8 ? wpvs: write protect enable 0 = no write protect violation has occurred since the last read of the smc_wpsr register. 1 = a write protect violation occurred since the last read of the smc_wpsr register. if this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field wpvsrc. ? wpvsrc: write protect violation source when wpvs is active, this field indicates the write-protected register (t hrough address offset or code) in which a write access has been attempted. note: reading smc_wpsr automatically clears all fields. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 wpvsrc 15 14 13 12 11 10 9 8 wpvsrc 76543210 CCCCCCCw p v s
431 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 431 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 31. ddr sdr sdram co ntroller (ddrsdrc) 31.1 description the ddr sdr sdram controller (ddrsdrc) is a multiport memory controller. it comprises four slave ahb interfaces. all simultaneous accesses (four independent ahb ports) are inter- leaved to maximize memory bandwidth and minimize transaction latency due to sdram protocol . the ddrsdrc extends the memory capabilities of a chip by providing the interface to an exter- nal 16-bit or 32-bit sdr-sdram device and external 16-bit ddr-sdram device. the page size supports ranges from 2048 to 16384 and the number of columns from 256 to 4096. it supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses. the ddrsdrc supports a read or write burst length of 8 locations which frees the command and address bus to anticipate the next command, thus reducing latency imposed by the sdram protocol and improving the sdram bandwidth. moreover it keeps track of the active row in each bank, thus maximizing sdram performance, e.g., the application may be placed in one bank and data in the other banks. so as to optimize performance, it is advisable to avoid accessing different rows in the same bank. the ddrsdrc supports a cas latency of 2 or 3 and optimizes the read access depending on the frequency. the features of self refresh, power-down and deep power-down modes minimize the consump- tion of the sdram device. the ddrsdrc user inte rface is compliant wit h arm advanced perip heral bus (apb rev2). note: the term sdram device regroups sdr- sdram, low-power sdr-sdram, low-power ddr1-sdram and ddr2-sdram devices. 31.2 embedded characteristics ? amba compliant interface, interfaces directly to the arm advanced high performance bus (ahb) C four ahb interfaces, management of all accesses maximizes memory bandwidth and minimizes transaction latency C ahb transfer: word, half word, byte access ? supports ddr2-sdram, low-power ddr1-s dram or ddr2-sdram, sdr-sdram and low-power sdr-sdram ? numerous configurations supported C 2k, 4k, 8k, 16k row address memory parts C sdram with four and eight internal banks C sdr-sdram with 16- or 32-bit data path C ddr-sdram with 16-bit data path C one chip select for sdram device (256 mbyte address space) ? programming facilities C multibank ping-pong access (up to or 4 banks or 8 banks opened at same time = reduces average latency of transactions) C timing parameters specified by software C automatic refresh operation, refresh rate is programmable
432 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 432 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 C automatic update of ds, tcr and pasr parameters (low-power sdram devices) ? energy-saving capabilities C self-refresh, power-down, active power-down and deep power-down modes supported ? sdram power-up initialization by software ? cas latency of 2, 3 supported ? reset function supported (ddr2-sdram) ? odt (on-die termination) not supported ? auto precharge command not used ? sdr-sdram with 16-bit datapath and eight columns not supported ? ddr2-sdram with eight internal banks supported ? linear and interleaved decoding supported ? sdr-sdram or low-power ddr1-sdram wi th 2 internal banks not supported ? clock frequency change in precharge power-down mode not supported ? ocd (off-chip driver) mode not supported
433 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 433 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 31.3 ddrsdrc module diagram figure 31-1. ddrsdrc module diagram ddrsdrc is partitioned in two blocks (see figure 31-1 ): ? an interconnect-matrix that manages concurrent accesses on the ahb bus between four ahb masters and integrates an arbiter. ? a controller that translates ahb requests (read/write) in the sdram protocol. memory controller finite state machine sdram signal management addr, dqm data asynchronous timing refresh management ddr-sdr device s power m anagement dqs r as ,cas ,we cke clk/nclk odt ddr-sdr controller interconnect ma trix input stage input stage input stage output stage arbiter apb ahb sla ve interf a ce 0 ahb sla v e interf a ce 1 ahb sla ve interf ace 2 ahb sla ve interf ace 3 input stage interf ace apb
434 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 434 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 31.4 initialization sequence the addresses given are for example purposes on ly. the real address depends on implementa- tion in the product. 31.4.1 sdr-sdram initialization the initialization sequence is generated by so ftware. the sdr-sdram devices are initialized by the following sequence: 1. program the memory device type into the memory device register (see section 31.7.8 on page 474 ). 2. program the features of the sdr-sdram device into the timing register (asynchro- nous timing (trc, tras, etc.)), and into the configuration register (number of columns, rows, banks, cas latency) (see section 31.7.3 on page 464 , section 31.7.4 on page 467 and section 31.7.5 on page 469 ). 3. for low-power sdram, temperature-compensated self refresh (tcsr), drive strength (ds) and partial array self refresh (pasr) must be set in the low-power register (see section 31.7.7 on page 472 ). a minimum pause of 200 s is provi ded to precede any signal toggle. 4. a nop command is issued to the sdr-sdram. program nop command into mode register, the application must set mode to 1 in the mode register (see section 31.7.1 on page 462 ). perform a write access to any sdr-sdram address to acknowledge this command. now the clock which dr ives sdr-sdram device is enabled. 5. an all banks precharge command is issued to the sdr-sdram. program all banks precharge command into mode register, the application must set mode to 2 in the mode register (see section 31.7.1 on page 462 ). perform a write access to any sdr- sdram address to acknowledge this command. 6. eight auto-refresh (cbr) cycles are provided. program the auto refresh command (cbr) into mode register, the application must set mode to 4 in the mode register (see section 31.7.1 on page 462 ).performs a write access to any sdr-sdram loca- tion eight times to acknowledge these commands. 7. a mode register set (mrs) cycle is issued to program the parameters of the sdr- sdram devices, in particular cas latency and burst length. the application must set mode to 3 in the mode register (see section 31.7.1 on page 462 ) and perform a write access to the sdr-sdram to acknowledge this command. the write address must be chosen so that ba[1:0] are set to 0. for example, with a 16-bit 128 mb sdr-sdram (12 rows, 9 columns, 4 banks) bank address, the sdram write access should be done at the address 0x20000000. note: this address is for example purposes only. t he real address is dependent on implementation in the product. 8. for low-power sdr-sdram initialization, an extended mode register set (emrs) cycle is issued to program the sdr-sdram parameters (tcsr, pasr, ds). the appli- cation must set mode to 5 in the mode register (see section 31.7.1 on page 462 ) and perform a write access to the sdr-sdram to acknowledge this command. the write address must be chosen so that ba[1] is set to 1 and ba[0] is set to 0. for example, with a 16-bit 128 mb sdram, (12 rows, 9 columns, 4 banks) bank address the sdram write access should be done at the address 0x20800000. 9. the application must go into normal mode, setting mode to 0 in the mode register (see section 31.7.1 on page 462 ) and perform a write access at any location in the sdram to acknowledge this command.
435 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 435 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 10. write the refresh rate into the count field in the ddrsdrc refresh timer register (see page 463 ). (refresh rate = delay between re fresh cycles). the sdr-sdram device requires a refresh every 15.625 s or 7.81 s. with a 100 mhz frequency, the refresh timer count register must to be set with (15.625*100 mhz) = 1562 i.e. 0x061a or (7.81*100 mhz) = 781 i.e. 0x030d after initialization, the sdr-s dram device is fully functional. 31.4.2 low-power ddr1-sdram initialization the initialization sequence is generated by software. the low-power ddr1-sdram devices are initialized by the following sequence: 1. program the memory device type into the memory device register (see section 31.7.8 on page 474 ). 2. program the features of the low-power ddr1-sdram device into the configuration register: asynchronous timing (trc, tras, etc.), number of columns, rows, banks, cas latency. see section 31.7.3 on page 464 , section 31.7.4 on page 467 and section 31.7.5 on page 469 . 3. program temperature compensated self refresh (tcr), partial array self refresh (pasr) and drive strength (ds) into the low-power register. see section 31.7.7 on page 472 . 4. an nop command will be issued to the low-power ddr1-sdram. program nop com- mand into the mode register, the application must set mode to 1 in the mode register (see section 31.7.1 on page 462 ). perform a write access to any ddr1-sdram address to acknowle dge this command. now clocks which drive ddr1-sdram device are enabled. a minimum pause of 200 s will be provid ed to precede any signal toggle. 5. an all banks precharge command is issued to the low-power ddr1-sdram. program all banks precharge command into the mode register, the application must set mode to 2 in the mode register (see section 31.7.1 on page 462 ). perform a write access to any low-power ddr1-sdram address to acknowledge this command 6. two auto-refresh (cbr) cycles are provid ed. program the auto refresh command (cbr) into the mode register, the application must set mode to 4 in the mode register (see section 31.7.1 on page 462 ). perform a write access to any low-power ddr1- sdram location twice to acknowledge these commands. 7. an extended mode register set (emrs) cycle is issued to program the low-power ddr1-sdram parameters (tcsr, pasr, ds). the application must set mode to 5 in the mode register (see section 31.7.1 on page 462 ) and perform a write access to the sdram to acknowledge this command. the write address must be chosen so that ba[1] is set to 1 ba[0] is set to 0. for ex ample, with a 16-bit 128 mb sdram (12 rows, 9 columns, 4 banks) bank address, the low-power ddr1-sdram write access should be done at address 0x20800000. note: this address is for example purposes only. t he real address is dependent on implementation in the product. 8. a mode register set (mrs) cycle is issued to program the parameters of the low-power ddr1-sdram devices, in particular cas late ncy, burst length. the application must set mode to 3 in the mode register (see section 31.7.1 on page 462 ) and perform a write access to the low-power ddr1-sdram to acknowledge this command. the write address must be chosen so that ba[1:0] bits are set to 0. for example, with a 16-bit 128 mb low-power ddr1-sdram (12 rows, 9 columns, 4 banks) bank address, the sdram write access should be done at the address 0x20000000. the application must go into normal mode, setting mode to 0 in the mode register (see section 31.7.1 on
436 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 436 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 page 462 ) and performing a write access at any location in the low-power ddr1- sdram to acknowledge this command. 9. perform a write access to any low-power ddr1-s dram address. 10. write the refresh rate into the count field in the ddrsdrc refresh timer register (see page 463 ). (refresh rate = delay between refresh cycles). the low-power ddr1- sdram device requires a refresh every 15.625 s or 7.81 s. with a 100 mhz fre- quency, the refresh timer count register must to be set with (15.625*100 mhz) = 1562 i.e. 0x061a or (7.81*100 mhz) = 781 i.e. 0x030d 11. after initialization, the low-power ddr1-sdram de vice is fully functional. 31.4.3 ddr2-sdram initialization the initialization sequence is generated by so ftware. the ddr2-sdram de vices are initialized by the following sequence: 1. program the memory device type into the memory device register (see section 31.7.8 on page 474 ). 2. program the features of ddr2-sdram device into the timing register (asynchronous timing (trc, tras, etc.)), and into the configuration register (number of columns, rows, banks, cas latency and output drive strength) (see section 31.7.3 on page 464 , section 31.7.4 on page 467 and section 31.7.5 on page 469 ). 3. an nop command is issued to the ddr2-sdram. program the nop command into the mode register, the application must set mode to 1 in the mode register (see sec- tion 31.7.1 on page 462 ). perform a write access to any ddr2-sdram address to acknowledge this command . now clocks which drive ddr2-sdram device are enabled. a minimum pause of 200 s is provi ded to precede any signal toggle. 4. an nop command is issued to the ddr2-sdram. program the nop command into the mode register, the application must set mode to 1 in the mode register (see sec- tion 31.7.1 on page 462 ). perform a write access to any ddr2-sdram address to acknowledge this command. now cke is driven high. 5. an all banks precharge command is issued to the ddr2-sdram. program all banks precharge command into the mode register, the application must set mode to 2 in the mode register (see section 31.7.1 on page 462 ). perform a write access to any ddr2- sdram address to acknowledge this command 6. an extended mode register set (emrs2) cycle is issued to chose between commer- cial or high temperature operations. the application must set mode to 5 in the mode register (see section 31.7.1 on page 462 ) and perform a write access to the ddr2- sdram to acknowledge this command. the write address must be chosen so that ba[1] is set to 1 and ba[0] is set to 0. for example, with a 16-bit 128 mb ddr2- sdram (12 rows, 9 columns, 4 banks) bank address, the ddr2-sdram write access should be done at the address 0x20800000. note: this address is for example purposes only. t he real address is dependent on implementation in the product. 7. an extended mode register set (emrs3) cycle is issued to set the extended mode register to 0. the application must set mode to 5 in the mode register (see section 31.7.1 on page 462 ) and perform a write access to the ddr2-sdram to acknowledge this command. the write address must be chosen so that ba[1] is set to 1 and ba[0] is set to 1. for example, with a 16-bit 128 mb ddr2-sdram (12 rows, 9 columns, 4 banks) bank address, the ddr2-sdram write access should be done at the address 0x20c00000.
437 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 437 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 8. an extended mode register set (emrs1) cycle is issued to enable dll. the applica- tion must set mode to 5 in the mode register (see section 31.7.1 on page 462 ) and perform a write access to the ddr2-sdram to acknowledge this command. the write address must be chosen so that ba[1] is set to 0 and ba[0] is set to 1. for example, with a 16-bit 128 mb ddr2-sdram (12 rows, 9 columns, 4 banks) bank address, the ddr2-sdram write access should be done at the address 0x20400000. an additional 200 cycles of clock are required for locking dll 9. program dll field into the configuration register (see section 31.7.3 on page 464 ) to high (enable dll reset). 10. a mode register set (mrs) cycle is issued to reset dll. the application must set mode to 3 in the mode register (see section 31.7.1 on page 462 ) and perform a write access to the ddr2-sdram to acknowledge this command. the write address must be chosen so that ba[1:0] bits are set to 0. for example, with a 16-bit 128 mb ddr2- sdram (12 rows, 9 columns, 4 banks) bank address, the sdram write access should be done at the address 0x20000000. 11. an all banks precharge command is issued to the ddr2-sdram. program all banks precharge command into the mode register, the application must set mode to 2 in the mode register (see section 31.7.1 on page 462 ). perform a write access to any ddr2- sdram address to acknowledge this command 12. two auto-refresh (cbr) cycl es are provided. program the auto refresh command (cbr) into the mode register, the application must set mode to 4 in the mode register (see section 31.7.1 on page 462 ). performs a write access to any ddr2-sdram loca- tion twice to acknowledge these commands. 13. program dll field into the configuration register (see section 31.7.3 on page 464 ) to low (disable dll reset). 14. a mode register set (mrs) cycle is issued to program the parameters of the ddr2- sdram devices, in particular cas latency, burst length and to disable dll reset. the application must set mode to 3 in the mode register (see section 31.7.1 on page 462 ) and perform a write access to the ddr2-sdram to acknowledge this command. the write address must be chosen so that ba[1:0] are set to 0. for example, with a 16-bit 128 mb sdram (12 rows, 9 columns, 4 banks) bank address, the sdram write access should be done at the address 0x20000000 15. program ocd field into the configuration register (see section 31.7.3 on page 464 ) to high (ocd calibration default). 16. an extended mode register set (emrs1) c ycle is issued to ocd default value. the application must set mode to 5 in the mode register (see section 31.7.1 on page 462 ) and perform a write access to the ddr2-sdram to acknowledge this command. the write address must be chosen so that ba[1] is set to 0 and ba[0] is set to 1. for exam- ple, with a 16-bit 128 mb ddr2-sdram (12 rows, 9 columns, 4 banks) bank address, the ddr2-sdram write access should be done at the address 0x20400000. 17. program ocd field into the configuration register (see section 31.7.3 on page 464 ) to low (ocd calibration mode exit). 18. an extended mode register set (emrs1) cycle is issued to enable ocd exit. the application must set mode to 5 in the mode register (see section 31.7.1 on page 462 ) and perform a write access to the ddr2-sdram to acknowledge this command. the write address must be chosen so that ba[1] is set to 0 and ba[0] is set to 1. for exam- ple, with a 16-bit 128 mb ddr2-sdram (12 rows, 9 columns, 4 banks) bank address, the ddr2-sdram write access should be done at the address 0x20400000.
438 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 438 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 19. a mode normal command is provided. program the normal mode into mode register (see section 31.7.1 on page 462 ). perform a write access to any ddr2-sdram address to acknowledge this command. 20. perform a write access to any ddr2-sdram address. 21. write the refresh rate into the count field in the refresh timer register (see page 463 ). (refresh rate = delay between refresh cycles). the ddr2-sdram device requires a refresh every 15.625 s or 7.81 s. with a 133 mhz frequency, the refresh timer count register must to be set with (15.625*133 mhz) = 2079 i.e. 0x081f or (7.81*133 mhz) = 1039 i.e. 0x040f. after initialization, the ddr2-sdra m devices are fully functional.
439 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 439 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 31.5 functional description 31.5.1 sdram controller write cycle the ddrsdrc allows burst access or single access in normal mode (mode = 000). whatever the access type, the ddrsdrc keeps track of the active row in each bank, thus maximizing performance. the sdram device is programmed with a burst length equal to 8. this determines the length of a sequential data input by the write command that is set to 8. the latency from write command to data input is fixed to 1 in the case of ddr-sdram devices. in the case of sdr-sdram devices, there is no latency from write command to data input. to initiate a single access, the ddrsdrc che cks if the page access is already open. if row/bank addresses match with the previous row/bank addresses, the controller generates a write command. if the bank addresses are not identical or if bank addresses are identical but the row addresses are not identical, the controller generates a precharge command, activates the new row and initiates a write co mmand. to comply with sdram timing parameters, additional clock cycles are inserted between precharge/active (t rp) comm ands and active/write (t rcd) command. as the burst length is fixed to 8, in the case of single access, it has to stop the burst, otherwise seven invalid values may be written. in the case of sdr-sdram devices, a burst stop command is generated to interrupt the write operation. in the case of ddr-sdram devices, burst stop command is not supported for the burst write operation. in order to then interrupt the write operation, dm must be set to 1 to mask invalid data (see figure 31-2 on page 440 and figure 31-5 on page 441 ) and dqs must continue to toggle. to initiate a burst access, the ddrsdrc uses the transfer type signal pr ovided by the master requesting the access. if the next access is a sequential write access, writing to the sdram device is carried out. if the next access is a write non-sequential access, then an automatic access break is inserted, the ddrsdrc generates a precharge command, activates the new row and initiates a write command. to comply with sdram timing parameters, additional clock cycles are inserted between precharge/acti ve (trp) commands and active/write (trcd) commands. for a definition of timing parameters, refer to section 31.7.4 ddrsdrc timing parameter 0 register on page 467 . write accesses to the sdram devices are burst oriented and the burst length is programmed to 8. it determines the maximum number of column locations that can be accessed for a given write command. when the write command is issued, 8 columns are selected. all accesses for that burst take place within these eight columns, thus the burst wraps within these 8 columns if a boundary is reached. these 8 columns are selected by addr[13:3]. addr[2:0] is used to select the starting location within the block. in the case of incrementing burst (incr/incr 4/incr8/incr16), the addresses can cross the 16-byte boundary of the sdram device. for example, in th e case of ddr-sdram devices, when a transfer (incr4) starts at address 0x0c , the next access is 0x10, but since the burst length is programmed to 8, the next access is at 0x00. since the boundary is reached, the burst is wrapping. the ddrsdrc takes th is feature of the sdram device into account. in the case of transfer starting at address 0x04/0x08/0x0c (ddr-sdram devices) or starting at address 0x10/0x14/0x18/0x1c, two write commands are issued to avoid to wrap when the boundary is reached. the last write command is subject to dm input logic level. if dm is registered high, the corresponding data input is ignored and write access is not done. this avoi ds additional writing being done.
440 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 440 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 31-2. single write access, row closed, low-power ddr1-sdram device figure 31-3. single write access, row closed, ddr2-sdram device sdclk a[12:0] command ba[1:0] 0 row a col a nop prchg nop act nop write nop 0 dm[1:0] 0 3 trp = 2 trcd = 2 dqs[1:0] d[15:0] db da 3 sdclk a[12:0] command ba[1:0] 0 row a col a nop prchg nop act nop write nop 0 dm[1:0] 0 3 trp = 2 trcd = 2 dqs[1:0] d[15:0] db da 3
441 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 441 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 31-4. single write access, row closed, sdr-sdram device figure 31-5. burst write access, row closed, low-power ddr1-sdram device row a col a 3 0 3 nop prchg nop act nop write nop bst sdclk a[12:0] command ba[1:0] 0 0 dm[1:0] trp = 2 d[31:0] dadb trcd = 2 trp = 2 trcd = 2 sdclk row a col a a[12:0] nop prchg nop act nop write nop command 0 ba[1:0] dqs[1:0] da db dc dd de df dg dh d [15:0] 3 0 3 dm[1:0]
442 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 442 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 31-6. burst write access, row closed, ddr2-sdram device figure 31-7. burst write access, row closed, sdr-sdram device a write command can be followed by a read command. to avoid breaking the current write burst, twtr/twrd (bl/2 + 2 = 6 cycles) should be met. see figure 31-8 on page 443 . trp = 2 trcd = 2 sdclk row a col a a[12:0] nop prchg nop act nop write nop command 0 ba[1:0] dqs[1:0] da db dc dd de df dg dh d [15:0] 3 0 3 dm[1:0] row a col a nop prchg nop act nop write nop 0 da db dc dd de df dg dhs f 0 f trp trcd bst nop sdclk a[12:0] command ba[1:0] d[31:0] dm[3:0]
443 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 443 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 31-8. write command followed by a read command without burst write interrupt, low-power ddr1-sdram device in the case of a single write access, write operation should be interrupted by a read access but dm must be input 1 cycle prior to the read command to avoid writing invalid data. see figure 31- 9 on page 443 . figure 31-9. single write access followed by a read access low-power ddr1-sdram devices twrd = bl/2 +2 = 8/2 +2 = 6 twr = 1 sdclk col a col a a[12:0] nop write nop read bst nop command 0 ba[1:0] dqs[1:0] dc dd de df dg dh da db da db d[15:0] 3 0 3 dm[1:0] row a col a nop prchg nop act nop write nop read bst nop 0 data masked sdclk a[12:0] command ba[1:0] dqs[1:0] da db da db d[15:0] 3 0 3 dm[1:0]
444 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 444 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 31-10. single write access followed by a read access, ddr2 -sdram device 31.5.2 sdram controller read cycle the ddrsdrc allows burst access or single access in normal mode (mode =000). whatever access type, the ddrsdrc keeps track of the active row in each bank, thus maximizing perfor- mance of the ddrsdrc. the sdram devices are programmed with a burst length equal to 8 which determines the length of a sequential data output by the read command that is set to 8. the latency from read com- mand to data output is equal to 2 or 3. this value is programmed during the initialization phase (see section 31.4.1 sdr-sdram initialization on page 434 ). to initiate a single access, the ddrsdrc che cks if the page access is already open. if row/bank addresses match with the previous row/bank addresses, the controller generates a read command. if the bank addresses are not identi cal or if bank addresses are identical but the row addresses are not identical, the controller generates a precharge command, activates the new row and initiates a read command. to comply with sdram timing parameters, additional clock cycles are inserted between precharge/ active (trp) commands and active/read (trcd) command. after a read command, additional wait states are generated to comply with cas latency. the ddrsdrc supports a cas latency of two, two and ha lf, and three (2 or 3 clocks delay). as the burst length is fixed to 8, in the case of single access or burst access inferior to 8 data requests, it has to stop the burst otherwise seven or x values could be read. burst stop command (bst) is used to stop output during a burst read. to initiate a burst access, the ddrsdrc checks the transfer type signal . if the next accesses are sequential read acce sses, reading to the sdram device is carried out. if the next access is a read non-sequential access, then an automatic page break can be inserted. if the bank addresses are not identical or if bank addresses are identical but the row addresses are not identical, the controller generates a precharge command, activates the new row and initiates a read command. in the case where the page access is already open, a read command is generated. row a col a nop prchg nop act nop write nop read nop 0 data masked sdclk a[12:0] command ba[1:0] dqs[1:0] da db da db d[15:0] 3 0 3 dm[1:0] twtr
445 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 445 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 to comply with sdram timing parameters, addit ional clock cycles are inserted between pre- charge/active (trp) commands and active/r ead (trcd) commands. the ddrsdrc supports a cas latency of two, two and half, and three (2 or 3 clocks delay). during this delay, the controller uses internal signals to anticipate the next access and improve the performance of the control- ler. depending on the latency(2/3), the ddrsdrc anticipates 2 or 3 read accesses. in the case of burst of specified length, accesses are not anticipated, but if the burst is broken (border, busy mode, etc.), the next access is treated as an incrementing burst of unspecified length, and in function of the latency(2/3), the ddrsdrc anticipates 2 or 3 read accesses. for a definition of timing parameters, refer to section 31.7.3 ddrsdrc configuration register on page 464 . read accesses to the sdram are burst oriented and the burst length is programmed to 8. it determines the maximum number of column locations that can be accessed for a given read command. when the read command is issued, 8 columns are selected. all accesses for that burst take place within these eight columns, me aning that the burst wraps within these 8 col- umns if the boundary is reached. these 8 column s are selected by addr[13:3]; addr[2:0] is used to select the starting location within the block. in the case of incrementing burst (incr/incr 4/incr8/incr16), the addresses can cross the 16-byte boundary of the sdram device. for example, when a transfer (incr4) starts at address 0x0c, the next access is 0x10, but since the burst length is programmed to 8, the next access is 0x00. since the boundary is reach ed, the burst wraps. the ddrsdrc takes into account this feature of the sdram device. in th e case of ddr-sdram devices, transfers start at address 0x04/0x08/0x0c. in the case of sdr-sdram devices, transfers start at address 0x14/0x18/0x1c. two read commands are issued to avoid wrapping when the boundary is reached. the last re ad command may generate ad ditional reading (1 read cmd = 4 ddr words or 1 read cmd = 8 sdr words). to avoid additional reading, it is possible to use the burst stop command to truncate the read burst and to decrease power consumption.
446 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 446 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 31-11. single read access, row close, laten cy = 2,low-power ddr1-sdram device figure 31-12. single read access, row close, latency = 3, ddr2-sdram device trp trcd latency = 2 sdclk row a col a a[12:0] nop prchg nop act nop read bst nop command 0 ba[1:0] dqs[1] dqs[0] da db d[15:0] 3 dm[1:0] trp trcd latency = 2 sdclk row a col a a[12:0] nop prchg nop act nop read command 0 ba[1:0] dqs[1] dqs[0] da db d[15:0] 3 dm[1:0]
447 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 447 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 31-13. single read access, row close, latency = 2, sdr-sdram device figure 31-14. burst read access, latency = 2, low-power ddr1-sdram devices row a col a nop prchg nop act nop read bst nop 0 trp trcd latency = 2 sdclk a[12:0] command ba[1:0] dadb d[31:0] 3 dm[3:0] col a nop read nop 0 latency = 2 sdclk a[12:0] command ba[1:0] dqs[1:0] da db dc dd de df dg dh d[15:0] 3 dm[1:0]
448 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 448 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 31-15. burst read access, latency = 3, ddr2-sdram devices figure 31-16. burst read access, latency = 2, sdr-sdram devices 31.5.3 refresh (auto-refresh command) an auto-refresh command is used to refresh the ddrsdrc. refresh addresses are generated internally by the sdram device and incremented after each auto-refresh automatically. the ddrsdrc generates these auto-refresh commands periodically. a timer is loaded with the value in the register ddrsdrc_tr that indicates the number of clock cycles between refresh cycles. when the ddrsdrc initiates a refresh of an sdram device, internal memory accesses are not delayed. however, if the cpu tries to access the sdram device, the slave indicates that the device is busy. a request of refresh does not interrupt a burst transfer in progress. col a nop read nop 0 latency = 3 sdclk a[12:0] command ba[1:0] dqs[1:0] da db dc dd de df dg dh d[15:0] 3 dm[1:0] latency = 2 sdclk col a a[12:0] nop read nop bst nop command 0 ba[1:0] dadb dcdd dedf dg dh d[31:0] f dm[3:0] dqs[1:0]
449 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 449 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 31.5.4 power management 31.5.4.1 self refresh mode this mode is activated by setting low-powe r command bits [lpcb] to 01 in the ddrsdrc_lpr register self refresh mode is used to reduce power consumption, i.e., when no access to the sdram device is possible. in this case, power consumption is very low. in self refresh mode, the sdram device retains data without external clocking and provides its own internal clocking, thus performing its own auto-refresh cycles. a ll the inputs to the sdram device become dont care except cke, which remains low. as soon as the sdram device is selected, the ddrs- drc provides a sequence of commands and exits self refresh mode. the ddrsdrc re-enables self refresh mode as soon as the sdram device is not selected. it is possible to define when self refresh mode will be enabled by setting the register lpr (see sec- tion 31.7.7 ddrsdrc low-po wer register on page 472 ), timeout command bit: ? 00 = self refresh mode is enabled as soon as the sdram device is not selected ? 01 = self refresh mode is enabled 64 clock cycles after completion of the last access ? 10 = self refresh mode is enabled 128 clock cycles after completion of the last access as soon as the sdram device is no longe r selected, precharge all banks command is generated followed by a self-refrefsh co mmand. if, between these two commands an sdram access is detected, self-refrefsh command will be replaced by an auto- refresh command. according to the applica tion, more auto-refresh commands will be performed when the self refresh mode is enabled during the application. this controller also interfaces low-power sd ram. these devices add a new feature: a single quarter, one half quarter or all banks of the sdram array can be enabled in self refresh mode. disabled banks will be not refreshed in self refresh mode. this feat ure permits to reduce the self refresh current. the extended mode register controls this feature, it includes temperature com- pensated self refresh (tscr), partial array self refresh (pasr) parameters and drive strength (ds). these parameters are set during the initialization phase. after initialization, as soon as pasr/ds/tcsr fields are modified, the extended mode r egister in the memory of the external device is accessed automatica lly and pasr/ds/tcsr bits are updated before entry into self refresh mode if ddrsdrc does not share an external bus with another controller or during a refresh command, and a pending read or write access, if ddrsdrc does share an external bus with another controller. this type of update is a function of the upd_mr bit (see section 31.7.7 ddrsdrc low- power register on page 472 ). the low-power sdr-sdram must remain in self refresh mode for a minimum period of tras periods and may remain in self refresh mode for an indefinite period. (see figure 31-17 ) the low-power ddr1-sdram must remain in self refresh mode for a minimum of trfc periods and may remain in self refresh mode for an indefinite period. the ddr2-sdram must remain in self refres h mode for a minimum of tcke periods and may remain in self refresh m ode for an indefinite period.
450 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 450 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 31-17. self refresh mode entry, timeout = 0 figure 31-18. self refresh mode entry, timeout = 1 or 2 nop read bst nop prchg nop arfsh nop 0 trp enter self refresh mode sdclk a[12:0] command cke ba[1:0] dqs[0:1] da db d[15:0] 3 dm[1:0] nop read bst nop 0 da db 64 or 128 wait states 3 prchg nop arfsh nop trp enter self refresh mode sdclk a[12:0] command cke ba[1:0] dqs[1:0] d[15:0] dm[1:0]
451 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 451 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 31-19. self refresh mode exit figure 31-20. self refresh and automatic update nop valid nop 0 txnrd/txsrd (ddr device) txsr (low-power ddr1 device) txsr (low-power sdr, sdr-sdram device) exit self refresh mode clock must be stable before exiting self refresh mode sdclk a[12:0] command cke ba[1:0] dqs[1:0] dadb d[15:0] 3 dm[1:0] nop nop prchg mrs arfsh nop 0 tmrd enter self refresh mode sdclk a[12:0] command cke ba[1:0] 2 nop update extended mode register trp pasr-tcr-ds
452 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 452 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 31-21. automatic update during auto-r efresh command and sdram access 31.5.4.2 power-down mode this mode is activated by setting the low-power command bits [lpcb] to 10. power-down mode is used when no access to the sdram device is possible. in this mode, power consumption is greater than in self refresh mode. this state is similar to normal mode (no low-power mode/no self refresh mode), but the cke pin is low and the input and output buffers are deactivated as soon the sdram device is no longer accessible. in contrast to self refresh mode, the sdram device cannot remain in low-power mode longer than the refresh period (64 ms). as no auto-refresh oper ations are performed in this mode, the ddrsdrc carries out the refresh operation. in order to exit low-power mode, a nop command is required in the case of low-power sdr-sdram and sdr-sdram devices . in the case of low-power ddr1-sdram devices, the controller generates a nop command during a delay of at least txp. in addition, low-power ddr1-sdram and ddr2-sdram must re main in power-down mode for a mini- mum period of tcke periods. the exit procedure is faster than in self refresh mode. see figure 31-22 on page 453 . the ddrsdrc returns to power-down mode as soon as the sdram device is not selected. it is possible to define when power-down mode is enabled by setting the register lpr, timeout com- mand bit. ? 00 = power-down mode is enabled as soon as the sdram device is not selected ? 01 = power-down mode is enabled 64 clock cycles after completion of the last access ? 10 = power-down mode is enabled 128 clock cycles after co mpletion of th e last access nop nop prchall mrs arfsh nop 0 trfc sdclk a[12:0] command cke ba[1:0] 2 nop update extended mode register trp pasr-tcr-ds act 0 tmrd
453 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 453 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 31-22. power-down entry/exit, timeout = 0 31.5.4.3 deep power-down mode the deep power-down mode is a new feature of the low-power sdram. when this mode is activated, all internal voltage generators inside the device are stopped and all data is lost. this mode is activated by setting the low-power command bits [lpcb] to 11. when this mode is enabled, the ddrsdrc leaves normal mode (mode == 000) and the controller is frozen. to exit deep power-down mode, the low-power bits (lpcb) must be set to 00, an initialization sequence must be generated by software. see section 31.4.2 low-power ddr1-sdram ini- tialization on page 435 . figure 31-23. deep power-down mode entry entry power down mode exit power down mode sdclk a[12:0] read bst nop read command cke 0 ba[1:0] dqs[1:0] da db d[15:0] 3 dm[1:0] nop read bst nop prchg nop deepower nop 0 trp enter deep power-down mode sdclk a[12:0] command cke ba[1:0] dqs[1:0] da db d[15:0] 3 dm[1:0]
454 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 454 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 31.5.4.4 reset mode the reset mode is a feature of the ddr2-sdram. this mode is activated by setting the low- power command bits (lpcb) to 11 and the clock frozen command bit (clk_fr) to 1. when this mode is enabled, the ddrsdrc leaves normal mode (mode == 000) and the control- ler is frozen. before enabling this mode, the end user must assume there is not an access in progress. to exit reset mode, the low-power command bits (lpcb) must be set to 00, clock frozen com- mand bit (clk_fr) set to 0 and an initialization sequence must be generated by software. see section 31.4.3 ddr2-sdram initialization on page 436 . 31.5.5 multi-port functionality the sdram protocol imposes a check of timings prior to performing a read or a write access, thus decreasing the performance of systems. an access to sdram is performed if banks and rows are open (or active). to activate a row in a particular bank, it has to de-active the last open row and open the new row. two sdram commands must be performed to open a bank: pre- charge and active command with respect to trp timing. before performing a read or write command, trcd timing must checked. this operation represents a significative loss. (see figure 31-24 ). figure 31-24. trp and trcd timings the multi-port controller has been designed to mask these timings and thus improve the band- width of the system. ddrsdrc is a multi-port controller since four masters can simultaneously reach the controller. this feature improves the bandwidth of the system because it can detect four requests on the ahb slave inputs and thus anticipate the commands that follow, precharge and active commands in bank x during current access in bank y. this allows trp and trcd timings to be masked (see figure 31-25 ). in the best case, all accesses are done as if the banks and rows were already open. the best condition is met when the four masters work in different banks. in nop prchg nop act nop read bst nop 0 3 trp trcd latency =2 4 cycles before performing a read command sdclk a[12:0] command ba[1:0] dqs[1:0] d[15:0] dm1:0] da db
455 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 455 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 the case of four simultaneous read accesses, when the four banks and associated rows are open, the controller reads with a continuous flow and masks the cas latency for each different access. to allow a continuous flow, the read command must be set at 2 or 3 cycles (cas latency) before the end of current access. this requires that the scheme of arbitration changes since the round-robin arbitration cannot be respected. if the controller anticipates a read access, and thus before the end of current access a master with a high priority arises, then this master will not serviced. the arbitration mechanism reduces latency when conflicts occur, i.e., when two or more masters try to access the sdram device at the same time. the arbitration type is round-robin arbitration. th is algorithm dispatches the requests from differ- ent masters to the sdram device in a round-robin manner. if two or more master requests arise at the same time, the master with the lowest num ber is serviced first, then the others are ser- viced in a round-robin manner. to avoid burst breaking and to provide the maximum throughput for the sdram device, arbitration may only take place during the following cycles: 1. idle cycles: when no master is connected to the sdram device. 2. single cycles: when a slave is currently doing a single access. 3. end of burst cycles: when the current cycle is the last cycle of a burst transfer. for bursts of defined length, predicted end of burst matches the size of the transfer. for bursts of undefined length, predicted end of burst is generated at the end of each four beat boundary inside the incr transfer. 4. anticipated access: when an anticipate re ad access is done while current access is not complete, the arbitration scheme can be changed if the anticipated access is not the next access serviced by the arbitration scheme. figure 31-25. anticipate precharge/active command in bank 2 during read access in bank 1 nop read nop 0 nop prech act read 1 1 2 anticipate command, precharge/active bank 2 trp read access in bank 1 sdclk a[12:0] command ba[1:0] dqs[1:0] da db dc dd de df dg dh di dj dk dl d[15:0] 3 dm1:0]
456 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 456 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 31.5.6 write protected registers to prevent any single software error that ma y corrupt ddrsdrc behavior, the registers listed below can be write-protected by setting the wpen bit in the ddrsdrc write protect mode register (ddrsdrc_wpmr). if a write access in a write-pr otected register is detected, then the wpvs flag in the ddrsdrc write protect status register (ddrsdrc_wpsr) is set and the field wpvsrc indicates in which register the write access has been attempted. the wpvs flag is automatically reset after read ing the ddrsdrc write protect status register (ddrsdrc_wpsr). following is a list of the write protected registers: ? ddrsdrc mode register on page 462 ? ddrsdrc refresh timer register on page 463 ? ddrsdrc configuration register on page 464 ? ddrsdrc timing parameter 0 register on page 467 ? ddrsdrc timing parameter 1 register on page 469 ? ddrsdrc timing parameter 2 register on page 470 ? ddrsdrc memory device register on page 474 ? ddrsdrc high speed register on page 476
457 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 457 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 31.6 software interface/sdram organization, address mapping the sdram address space is organized into banks, rows and columns. the ddrsdrc maps different memory types depending on the values set in the ddrsdrc configuration register. see section 31.7.3 ddrsdrc configuration register on page 464 . the following figures illus- trate the relation between cpu addresses and columns, rows and banks addresses for 16-bit memory data bus widths and 32-bit memory data bus widths. the ddrsdrc supports address mapping in linear mode and interleaved mode. linear mode is a method for address mapping where banks alternate at each last sdram page of current bank. interleaved mode is a method for address mapping where banks alternate at each sdram end page of current bank. the ddrsdrc makes the sdram devices acce ss protocol transparent to the user. table 31-1 to table 31-15 illustrate the sdram device memory mapping seen by the user in correlation with the device structure. variou s configurations are illustrated. 31.6.1 sdram address mapping for 16-bit memory data bus width and four banks table 31-1. linear mapping for sdram configuration, 2k rows, 512/1024/2048/4096 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[10:0] column[8:0] m0 bk[1:0] row[10:0] column[9:0] m0 bk[1:0] row[10:0] column[10:0] m0 bk[1:0] row[10:0] column[11:0] m0 table 31-2. linear mapping for sdram configuration: 4k rows, 512/1024/2048/4096 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[11:0] column[8:0] m0 bk[1:0] row[11:0] column[9:0] m0 bk[1:0] row[11:0] column[10:0] m0 bk[1:0] row[11:0] column[11:0] m0 table 31-3. linear mapping for sdram configuration: 8k rows, 512/1024/2048/4096 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[12:0] column[8:0] m0
458 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 458 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 bk[1:0] row[12:0] column[9:0] m0 bk[1:0] row[12:0] column[10:0] m0 bk[1:0] row[12:0] column[11:0] m0 table 31-3. linear mapping for sdram configuration: 8k rows, 512/1024/2048/4096 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 table 31-4. linear mapping for sdram configuration: 16k rows, 512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[13:0] column[8:0] m0 bk[1:0] row[13:0] column[9:0] m0 bk[1:0] row[13:0] column[10:0] m0 table 31-5. interleaved mapping for sdram configuration, 2k rows, 512/1024/2048/4096 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 row[10:0] bk[1:0] column[8:0] m0 row[10:0] bk[1:0] column[9:0] m0 row[10:0] bk[1:0] column[10:0] m0 row[10:0] bk[1:0] column[11:0] m0 table 31-6. interleaved mapping for sdram configuration: 4k rows, 512/1024/2048/4096 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 row[11:0] bk[1:0] column[8:0] m0 row[11:0] bk[1:0] column[9:0] m0 row[11:0] bk[1:0] column[10:0] m0 row[11:0] bk[1:0] column[11:0] m0 table 31-7. interleaved mapping for sdram configuration: 8k rows, 512/1024/2048/4096 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 row[12:0] bk[1:0] column[8:0] m0
459 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 459 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 31.6.2 sdram address mapping for 16-bit memory data bus width and eight banks row[12:0] bk[1:0] column[9:0] m0 row[12:0] bk[1:0] column[10:0] m0 row[12:0] bk[1:0] column[11:0] m0 table 31-7. interleaved mapping for sdram configuration: 8k rows, 512/1024/2048/4096 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 table 31-8. interleaved mapping for sdram configuration: 16k rows, 512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 row[13:0] bk[1:0] column[8:0] m0 row[13:0] bk[1:0] column[9:0] m0 row[13:0] bk[1:0] column[10:0] m0 table 31-9. linear mapping for sdram configuration: 8k rows, 1024 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[2:0] row[12:0] column[9:0] m0 table 31-10. linear mapping for sdram configuration: 16k rows, 1024 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[2:0] row[13:0] column[9:0] m0 table 31-11. interleaved mapping for sdram configuration: 8k rows, 1024 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 row[12:0] bk[2:0] column[9:0] m0 table 31-12. interleaved mapping for sdram configuration: 16k rows, 1024 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 row[12:0] bk[2:0] column[9:0] m0
460 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 460 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 31.6.3 sdr-sdram address mapping for 32-bit memory data bus width notes: 1. m[1:0] is the byte address inside a 32-bit word. 2. bk[1] = ba1, bk[0] = ba0 table 31-13. sdr-sdram configuration mapping: 2k rows, 256/512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[10:0] column[7:0] m[1:0] bk[1:0] row[10:0] column[8:0] m[1:0] bk[1:0] row[10:0] column[9:0] m[1:0] bk[1:0] row[10:0] column[10:0] m[1:0] table 31-14. sdr-sdram configuration mapping: 4k rows, 256/512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[11:0] column[7:0] m[1:0] bk[1:0] row[11:0] column[8:0] m[1:0] bk[1:0] row[11:0] column[9:0] m[1:0] bk[1:0] row[11:0] column[10:0] m[1:0] table 31-15. sdr-sdram configuration mapping: 8k rows, 256/512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[12:0] column[7:0] m[1:0] bk[1:0] row[12:0] column[8:0] m[1:0] bk[1:0] row[12:0] column[9:0] m[1:0] bk[1:0] row[12:0] column[10:0] m[1:0]
461 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 461 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 31.7 ddr sdr sdram controller (ddrsdr c) user interface the user interface is connected to the apb bus. the ddrsdrc is programmed us ing the registers listed in table 31-16 table 31-16. register mapping offset register name access reset 0x00 ddrsdrc mode register ddrsdrc_mr read-write 0x00000000 0x04 ddrsdrc refresh timer register ddrsdrc_rtr read-write 0x00000000 0x08 ddrsdrc configuration register ddrsdrc_cr read-write 0x7024 0x0c ddrsdrc timing parameter 0 register ddrsdrc_tpr0 read-write 0x20227225 0x10 ddrsdrc timing parameter 1 register ddrsdrc_tpr1 read-write 0x3c80808 0x14 ddrsdrc timing parameter 2 register ddrsdrc_tpr2 read-write 0x2062 0x18 reserved C C C 0x1c ddrsdrc low-power register ddrsdrc_lpr read-write 0x10000 0x20 ddrsdrc memory device register ddrsdrc_md read-write 0x10 0x24 ddrsdrc dll information register ddrsdrc_dll read-only 0x00000001 0x2c ddrsdrc high speed register ddrsdrc_hs read-write 0x0 0x54-0x58 reserved - - - 0x60-0xe0 reserved C C C 0xe4 ddrsdrc write protect mode register ddrsdrc_wpmr read-write 0x00000000 0xe8 ddrsdrc write protect status register ddrsdrc_wpsr read-only 0x00000000
462 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 462 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 31.7.1 ddrsdrc mode register name: ddrsdrc_mr address: 0xffffe800 access: read-write reset: see table 31-16 this register can only be written if the bit wpen is cleared in ddrsdrc write protect mode register on page 477 . ? mode: ddrsdrc command mode this field defines the command issued by the ddrsdrc when th e sdram device is accessed. th is register is used to ini- tialize the sdram device and to activate deep power-down mode. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCC m o d e mode description 000 normal mode. any access to the ddrsdrc will be decoded normally. to activate this mode, command must be followed by a write to the sdram. 001 the ddrsdrc issues a nop comman d when the sdram device is accessed rega rdless of the cycle. to activate this mode, command must be followed by a write to the sdram. 010 the ddrsdrc issues an all banks precharge command when the sdram device is accessed regardless of the cycle. to activate this mode, command must be followed by a write to the sdram. 011 the ddrsdrc issues a load mode register command when the sdram device is accessed regardless of the cycle. to activate this mode, command must be followed by a write to the sdram. 100 the ddrsdrc issues an auto-refresh command when the sdram device is accessed regardless of the cycle. previously, an all banks precharge command must be issued. to activate this mode, command must be followed by a write to the sdram. 101 the ddrsdrc issues an extended load mode register command when the sdram device is accessed regardless of the cycle. to activate this mode, the extended load mode regi ster command must be followed by a write to the sdram. the write in the sdram must be done in the appropriate bank. 110 deep power mode: access to deep power-down mode 111 reserved
463 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 463 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 31.7.2 ddrsdrc refresh timer register name: ddrsdrc_rtr address: 0xffffe804 access: read-write reset: see table 31-16 this register can only be written if the bit wpen is cleared in ddrsdrc write protect mode register on page 477 . ? count: ddrsdrc refresh timer count this 12-bit field is loaded into a timer which generates the refresh pulse. each time the refresh pulse is generated, a refresh sequence is initiated. sdram devices require a refresh of all rows every 64 ms. the value to be loaded depends on th e ddrsdrc clock fre- quency (mck: master clock) and the number of rows in the device. for example, for an sdram with 8192 rows and a 100 mhz ma ster clock, the value of refresh timer count bit is pro- grammed: (((64 x 10 -3 )/8192) x100 x10 6 = 781 or 0x030d. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCC c o u n t 76543210 count
464 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 464 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 31.7.3 ddrsdrc configuration register name: ddrsdrc_cr address: 0xffffe808 access: read-write reset: see table 31-16 this register can only be written if the bit wpen is cleared in ddrsdrc write protect mode register on page 477 . ? nc: number of column bits the reset value is 9 column bits. sdr-sdram devices with eight columns in 16-bit mode are not supported. ? nr: number of row bits the reset value is 12 row bits. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 C decod C nb C actbst C ebishare 15 14 13 12 11 10 9 8 C ocd C C dis_dll dic/ds 76543210 dll cas nr nc nc ddr - column bits sdr - column bits 00 98 01 10 9 10 11 10 11 12 11 nr row bits 00 11 01 12 10 13 11 14
465 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 465 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? cas: cas latency the reset value is 2 cycles. ? dll: reset dll reset value is 0. this field defines the value of reset dll. 0 = disable dll reset. 1 = enable dll reset. this value is used during the power-up sequence. note: this field is found only in ddr2-sdram devices . ? dic/ds: output driver impedance control reset value is 0. this field defines the output drive strength. 0 = normal driver strength. 1 = weak driver strength. this value is used during the power-up sequence. this parameter is found in the datasheet as dic or ds. note: this field is found only in ddr2-sdram devices . ? dis_dll: disable dll reset value is 0. 0 = enable dll 1 = disable dll note: this field is found only in ddr2-sdram devices . ? ocd: off-chip driver reset value is 7. note: ocd is not supported by the controller, but these values must be programmed during the initialization sequence. cas ddr2 cas latency sdr cas latency 000 reserved reserved 001 reserved reserved 010 reserved 2 011 33 100 reserved reserved 101 reserved reserved 110 reserved reserved 111 reserved reserved
466 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 466 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 note: this field is found only in ddr2-sdram devices . ? ebishare: external bus interface is shared the ddr controller embedded in the ebi is used at the same time as another memory controller (smc,..) reset value is 0. 0 = only the ddr controller function is used. 1 = the ddr controller shares the ebi with another memory controller (smc, nand,..) ? actbst: active bank x to burst stop read access bank y reset value is 0. 0 = after an active command in bank x, burst stop command can be issued to another bank to stop current read access. 1 = after an active command in bank x, burst stop command cannot be issued to another bank to stop current read access. this field is unique to sdr-sdram, low-powe r sdr-sdram and low-power ddr1-sdram devices. ? nb: number of banks the reset value is four banks. note: only ddr-sdram 2 devices support eight internal banks. ? decod: type of decoding the reset value is 0: sequential decoding. 0 = sequential decoding. 1 = interleaved decoding. ocd 000 ocd calibration mode exit, maintain setting 111 ocd calibration default nb number of banks 0 4 1 8
467 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 467 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 31.7.4 ddrsdrc timing parameter 0 register name: ddrsdrc_tpr0 address: 0xffffe80c access: read-write reset: see table 31-16 this register can only be written if the bit wpen is cleared in ddrsdrc write protect mode register on page 477 . ? tras: active to precharge delay reset value is 5 cycles. this field defines the delay between an activate command and a precharge command in number of cycles. number of cycles is between 0 and 15. ? trcd: row to column delay reset value is 2 cycles. this field defines the delay between an activate comman d and a read/write command in number of cycles. number of cycles is between 0 and 15. ? twr: write recovery delay reset value is 2 cycles. this field defines the write recovery time in numb er of cycles. number of cycles is between 1 and 15. ? trc: row cycle delay reset value is 7 cycles. this field defines the delay between an activate command and refresh command in number of cycles. number of cycles is between 0 and 15 ? trp: row precharge delay reset value is 2 cycles. this field defines the delay between a precharge command and another command in number of cycles. number of cycles is between 0 and 15. ? trrd: active banka to active bankb reset value is 2 cycles. 31 30 29 28 27 26 25 24 tmrd reduce_wrrd twtr 23 22 21 20 19 18 17 16 trrd trp 15 14 13 12 11 10 9 8 trc twr 76543210 trcd tras
468 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 468 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 this field defines the delay between an active command in banka and an active command in bankb in number of cycles. number of cycles is between 1 and 15. ? twtr: internal write to read delay reset value is 0. this field is unique to low-power ddr 1-sdram devices and ddr2-sdram devices. this field defines the internal write to read command time in number of cycles. number of cycles is between 1 and 7. ? reduce_wrrd: reduce write to read delay reset value is 0. this field reduces the delay between write to read access for low-power ddr-sdram devices with a latency equal to 2. to use this feature, twtr field must be equal to 0. important to note is that some devices do not support this feature. ? tmrd: load mode register command to active or refresh command reset value is 2 cycles. this field defines the delay between a load mode register command and an active or refresh command in number of cycles. number of cycles is between 0 and 15.
469 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 469 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 31.7.5 ddrsdrc timing parameter 1 register name: ddrsdrc_tpr1 address: 0xffffe810 access: read-write reset: see table 31-16 this register can only be written if the bit wpen is cleared in ddrsdrc write protect mode register on page 477 . ? trfc: row cycle delay reset value is 8 cycles. this field defines the delay between a refresh and an activate command or refresh command in number of cycles. num- ber of cycles is between 0 and 31 ? txsnr: exit self refresh delay to non-read command reset value is 8 cycles. this field defines the delay between cke set high and a non read command in number of cycles. number of cycles is between 0 and 255. this field is used for sdr-sdram and dd r-sdram devices. in the case of sdr-sdram devices and low-power ddr1-sdram, this field is equivalent to txsr timing. ? txsrd: exit self refresh delay to read command reset value is 200 cycles. this field defines the delay between cke set high and a read command in number of cycles . number of cycles is between 0 and 255 cycles.this field is unique to dd r-sdram devices. in the case of a low-power ddr1-sdram, this field must be written to 0. ? txp: exit power-down delay to first command reset value is 3 cycles. this field defines the delay between cke set high and a valid command in number of cycles. number of cycles is between 0 and 15 cycles. this field is unique to low-po wer ddr1-sdram devices and ddr2-sdram devices. 31 30 29 28 27 26 25 24 CCCC t x p 23 22 21 20 19 18 17 16 txsrd 15 14 13 12 11 10 9 8 txsnr 76543210 CCC t r f c
470 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 470 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 31.7.6 ddrsdrc timing parameter 2 register name: ddrsdrc_tpr2 address: 0xffffe814 access: read-write reset: see table 31-16 this register can only be written if the bit wpen is cleared in ddrsdrc write protect mode register on page 477 . ? txard: exit active power down delay to read command in mode ?fast exit?. the reset value is 2 cycles. this field defines the delay between cke set high and a read command in number of cycles . number of cycles is between 0 and 15. note: this field is found only in ddr2-sdram devices . ? txards: exit active power down delay to read command in mode ?slow exit?. the reset value is 6 cycles. this field defines the delay between cke set high and a read command in number of cycles . number of cycles is between 0 and 15. note: this field is found only in ddr2-sdram devices . ? trpa: row precharge all delay the reset value is 0 cycle. this field defines the dela y between a precharge all ba nks command and another comma nd in number of cycles. num- ber of cycles is between 0 and 15. note: this field is found only in ddr2-sdram devices . ? trtp: read to precharge the reset value is 2 cycles. this field defines the delay between read command and a precharge command in number of cycle. number of cycles is between 0 and 7. ? tfaw: four active window the reset value is 4 cycles. ddr2 devices with 8-banks (1gb or larger) have an additional requirement: t faw . this requires that no more than four activate commands may be issued in any given t faw (min) period. 31 30 29 28 27 26 25 24 CC CCCCCC 23 22 21 20 19 18 17 16 CC CC t f a w 15 14 13 12 11 10 9 8 trtp trpa 76543210 txards txard
471 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 471 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 number of cycles is between 0 and 15. note: this field is found only in ddr-sd ram 2 devices with eight internal banks
472 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 472 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 31.7.7 ddrsdrc low-power register name: ddrsdrc_lpr address: 0xffffe81c access: read-write reset: see table 31-16 ? lpcb: low-power command bit reset value is 00. 00 = low-power feature is inhibited: no power-down, self refresh and deep power mode are issued to the sdram device. 01 = the ddrsdrc issues a self refresh command to the s dram device, the clock(s) is/a re de-activated and the cke signal is set low. the sdram device leaves the self re fresh mode when accessed and enters it after the access. 10 = the ddrsdrc issues a power-down command to the sdra m device after each access, the cke signal is set low. the sdram device leaves the power-down mode when accessed and enters it after the access. 11 = the ddrsdrc issues a deep power-down command to the low-power sdram device. this mode is unique to low-power sdram devices. ? clk_fr: clock frozen command bit reset value is 0. this field sets the clock low during power-down mode or during deep power-down mode. some sdram devices do not support freezing the clock during power-down mode or during deep power-down mode. refer to the sdram device datasheet for details on this. 1 = clock(s) is/are frozen. 0 = clock(s) is/are not frozen. ? pasr: partial array self refresh reset value is 0. this field is unique to low-power sdram. it is used to specify whether only one quarter, one half or all banks of the sdram array are enabled. disabled banks are not refreshed in self refresh mode. the values of this field are dependant on low-power sdram devices. after the initialization se quence, as soon as pasr field is modified, extended mo de register in the external device mem- ory is accessed automatically and pasr bits are updated. in function of the upd_mr bit, update is done before entering in self refresh mode or during a refresh command and a pending read or write access. 31 30 29 28 27 26 25 24 CC CCCCCC 23 22 21 20 19 18 17 16 C C upd_mr C C C apde 15 14 13 12 11 10 9 8 CC t i m e o u t C d s 76543210 C pasr clk_fr lpcb
473 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 473 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? ds: drive strength reset value is 0. this field is unique to low-power sdram . it selects the driver strength of sdram output. after the initialization sequence, as soon as ds field is mo dified, extended mode register is accessed automatically and ds bits are updated. in function of upd_mr bit, update is done before entering in self refresh mode or during a refresh command and a pending read or write access. ? timeout: low power mode reset value is 00. this field defines when low-power mode is enabled. ? apde: active power down exit time reset value is 1. this mode is unique to ddr2-sdram devices. this mode allows to determine the active power-down mode, which determines performance versus power saving . 0 = fast exit 1 = slow exit after the initialization sequence, as soon as apde field is modified extended mode register, located in the memory of the external device, is accessed automatically and apde bits are updated. in function of the upd_mr bit, update is done before entering in self refresh mode or during a refresh command and a pending read or write access ? upd_mr: update load mode register and extended mode register reset value is 0. this bit is used to enable or disable automatic update of the load mode register and extended mode register. this update is function of ddrsdrc integration in a system. d drsdrc can either share or not share an external bus with another controller. 00 the sdram controller activates the sdram low-power mode immediately after the end of the last transfer. 01 the sdram controller activates the sdram low-power mo de 64 clock cycles after the end of the last transfer. 10 the sdram controller activates the sdram low-power mode 128 clock cycles after the end of the last transfer. 11 reserved 00 update is disabled. 01 ddrsdrc shares external bus. automatic update is done during a refresh command and a pending read or write access in sdram device. 10 ddrsdrc does not share external bus. automatic u pdate is done before entering in self refresh mode. 11 reserved
474 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 474 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 31.7.8 ddrsdrc memory device register name: ddrsdrc_md address: 0xffffe820 access: read-write reset: see table 31-16 this register can only be written if the bit wpen is cleared in ddrsdrc write protect mode register on page 477 . ? md: memory device indicates the type of memory used. reset value is for sdr-sdram device. 000 = sdr-sdram 001 = low-power sdr-sdram 010 = reserved 011 = low-power ddr1-sdram 110 = ddr2-sdram ? dbw: data bus width reset value is 16 bits. 0 = data bus width is 32 bits (reserved for sdr-sdram device). 1 = data bus width is 16 bits. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCd b wC m d
475 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 475 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 31.7.9 ddrsdrc dll register name: ddrsdrc_dll address: 0xffffe824 access: read-only reset: see table 31-16 the dll logic is internally used by the controller in order to delay dqs inputs. this is necessary to center the strobe time and the data valid window. ? mdinc: dll master delay increment 0 = the dll is not incrementing the master delay counter. 1 = the dll is incrementing the master delay counter. ? mddec: dll master delay decrement 0 = the dll is not decrementing the master delay counter. 1 = the dll is decrementing the master delay counter. ?mdovf : dll master delay overflow flag 0 = the master delay counter has not reached its maximum value, or the master is not locked yet. 1 = the master delay counter has reached its maximum value, the master delay counter increment is stopped and the dll forces the master lock. if this flag is set, it means the d drsdrc clock frequency is too low compared to master delay line number of elements. ?mdval : dll master delay value value of the master delay counter. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 mdval 76543210 CCCCCm d o v fm d d e cm d i n c
476 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 476 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 31.7.10 ddrsdrc hi gh speed register name: ddrsdrc_hs address: 0xffffe82c access: read-write reset: see table 31-16 this register can only be written if the bit wpen is cleared in ddrsdrc write protect mode register on page 477 . ? dis_anticip_read: anticip read access 0 = anticip read access is enabled. 1 = anticip read access is disabled (default). dis_anticip_read allows ddr2 read ac cess optimization with multi-port. as this feature is based on the bank open policy, the software must map different buffers in different ddr2 banks to take advantage of that feature. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCC dis_anticip_re ad CC
477 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 477 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 31.7.11 ddrsdrc write protect mode register name: ddrsdrc_wpmr address: 0xffffe8e4 access: read-write reset: see table 31-16 ? wpen: write protect enable 0 = disables the write protect if wpkey corresponds to 0x4444 52 (ddr in ascii). 1 = enables the write protect if wpkey corresponds to 0x444452 (ddr in ascii). protects the registers: ? ddrsdrc mode register on page 462 ? ddrsdrc refresh timer register on page 463 ? ddrsdrc configuration register on page 464 ? ddrsdrc timing parameter 0 register on page 467 ? ddrsdrc timing parameter 1 register on page 469 ? ddrsdrc timing parameter 2 register on page 470 ? ddrsdrc memory device register on page 474 ? ddrsdrc high speed register on page 476 ? wpkey: write protect key should be written at value 0x444452 (ddr in ascii). writing any other value in this field aborts the write operation of the wpen bit. always reads as 0. 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 w p e n
478 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 478 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 31.7.12 ddrsdrc write protect status register name: ddrsdrc_wpsr address: 0xffffe8e8 access: read-only reset: see table 31-16 ? wpvs: write protect violation status 0 = no write protect violation has occurred since the last read of the ddrsdrc_wpsr register. 1 = a write protect violation has occurred since the last read of the ddrsdrc_wpsr register. if this violation is an unau- thorized attempt to write a protected register, the associated violation is reported into field wpvsrc. ? wpvsrc: write protect violation source when wpvs is active, this field indicates the write-protected register (t hrough address offset or code) in which a write access has been attempted. note: reading ddrsdrc_wpsr automatically clears all fields. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 wpvsrc 15 14 13 12 11 10 9 8 wpvsrc 76543210 CCCCCCCw p v s
479 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 479 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 32. dma controller (dmac) 32.1 description the dma controller (dmac) is an ahb-central dma controller core that transfers data from a source peripheral to a destination peripheral over one or more amba buses. one channel is required for each source/destination pair. in the most basic configuration, the dmac has one master interface and one channel. the master interface reads the data from a source and writes it to a destination. two amba transfers are required for each dmac data transfer. this is also known as a dual-access transfer. the dmac is programmed via the apb interface. the dmac embeds 8 channels: 32.2 embedded characteristics ? two masters ? embeds 8 channels ? 16-byte fifo for channel 0 to 7 ?features: C linked list support with status write back operation at end of transfer C word, halfword, byte transfer support. C memory to memory transfer C peripheral to memory C memory to peripheral the dma controller can handle the transfer between peripherals and memory and so receives the triggers from the peripherals below. the hardware interface numbers are also given in table 32-1 . dmac channel number fifo size 016 116 216 316 416 516 616 716
480 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 480 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 table 32-1. dma channel definition instance name t/r dma channel hw interface number hsmci rx/tx 0 spi0 tx 1 spi0 rx 2 spi1 tx 3 spi1 rx 4 usart0 tx 5 usart0 rx 6 usart1 tx 7 usart1 rx 8 usart2 tx 9 usart2 rx 10 usart3 tx 11 usart3 rx 12 twi0 tx 13 twi0 rx 14 twi1 tx 15 twi1 rx 16 uart0 tx 17 uart0 rx 18 uart1 tx 19 uart1 rx 20 ssc tx 21 ssc rx 22 adc rx 23 dbgu tx 24 dbgu rx 25 aes tx 26 aes rx 27 sha tx 28
481 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 481 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 32.3 block diagram figure 32-1. dma controller (dmac) block diagram dma destination dma channel 0 dma destination control state machine destination pointer management dma source control state machine source pointer management dma fifo controller dma fifo up to 64 bytes dma channel 0 read data path from source dma channel 0 write data path to destination dma channel 1 dma channel 2 dma channel n external triggers soft triggers dma req/ack interface trigger manager dma interrupt controller status registers configuration registers atmel apb rev2 interface dma ahb lite master interface 0 dma ahb lite master interface 1 dma global control and data mux dma global request arbiter dma global control and data mux dma global request arbiter dma destination requests pool dma write datapath bundles dma source requests pool dma read datapath bundles dma atmel apb interface dma interrupt dma hardware handshaking interface amba ahb layer 0 amba ahb layer 1
482 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 482 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 32.4 functional description 32.4.1 basic definitions source peripheral: device on an amba layer from where the dmac reads data, which is then stored in the channel fifo. the source peripheral teams up with a destination peripheral to form a channel. destination peripheral: device to which the dmac writes the stored data from the fifo (previ- ously read from the source peripheral). memory: source or destination that is always ready for a dmac transfer and does not require a handshaking interface to interact with the dmac. programmable arbitration policy: modified round robin and fixed priority are available by means of the arb_cfg bit in the global confi guration register (dmac_gcfg). the fixed pri- ority is linked to the channel number. the highest dmac channel number has the highest priority. channel: read/write datapath between a source peripheral on one configured amba layer and a destination peripheral on the same or different amba layer that occurs through the channel fifo. if the source peripheral is not memory, th en a source handshaking interface is assigned to the channel. if the destination peripheral is not memory, then a destination handshaking inter- face is assigned to the channel. source and de stination handshaking interfaces can be assigned dynamically by programming the channel registers. master interface: dmac is a master on the ahb bus reading data from the source and writing it to the destination over the ahb bus. slave interface: the apb interface over which the dmac is programmed. the slave interface in practice could be on the same layer as any of the master interfaces or on a separate layer. handshaking interface: a set of signal registers that conform to a protocol and handshake between the dmac and source or destination peri pheral to control the transfer of a single or chunk transfer between them. this interface is used to request, acknowledge, and control a dmac transaction. a channel can receive a r equest through one of two types of handshaking interface: hardware or software. hardware handshaking interface: uses hardware signals to control the transfer of a single or chunk transfer between the dmac and the source or destination peripheral. software handshaking interface: uses software registers to control the transfer of a single or chunk transfer between the dmac and the source or destination peripheral. no special dmac handshaking signals are needed on the i/o of the peripheral. this mode is useful for interfacing an existing peripheral to the dmac without modifying it. flow controller: the device (either the dmac or source/destination peripheral) that determines the length of and terminates a dmac buffer transfer. if the length of a buffer is known before enabling the channel, then the dmac should be programmed as the flow controller. if the length of a buffer is not known prior to enabling the c hannel, the source or destination peripheral needs to terminate a buffer transfer. in this mode, the peripheral is the flow controller. transfer hierarchy: figure 32-2 on page 483 illustrates the hierarchy between dmac transfers, buffer transfers, chunk or single, and amba transfers (single or burst) for non-memory peripher- als. figure 32-3 on page 483 shows the transfer hierarchy for memory.
483 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 483 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 32-2. dmac transfer hierarchy for non-memory peripheral figure 32-3. dmac transfer hierarchy for memory buffer: a buffer of dmac data. the amount of data (length) is determined by the flow controller. for transfers between the dmac and memory, a buffer is broken directly into a sequence of amba bursts and amba single transfers. for transfers between the dmac and a non-memory peripheral, a buffer is broken into a sequence of dmac transactions (single and chunks). these are in turn broken into a sequence of amba transfers. transaction: a basic unit of a dmac transfer as determined by either the hardware or software handshaking interface. a transaction is only relevant for transfers between the dmac and a source or destination peripheral if the source or destination peripheral is a non-memory device. there are two types of transactions: single transfer and chunk transfer. C single transfer: the length of a single transaction is always 1 and is converted to a single amba access. C chunk transfer: the length of a chunk is programmed into the dmac. the chunk is then converted into a sequence of ahb access.dmac executes each amba burst transfer by performing incremental bursts that are no longer than 16 beats. dmac transfer dma transfer level buffer buffer buffer buffer transfer level chunk transfer chunk transfer chunk transfer single transfer dma transaction level burst transfer amba burst transfer amba burst transfer amba single transfer amba amba transfer level single transfer amba dmac transfer dma transfer level buffer buffer buffer buffer transfer level burst transfer amba burst transfer amba burst transfer amba single transfer amba amba transfer level
484 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 484 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 dmac transfer: software controls the number of buffers in a dmac transfer. once the dmac transfer has completed, then hardware within the dmac disables the channel and can generate an interrupt to signal the completion of the dmac transfer. you can then re-program the channel for a new dmac transfer. single-buffer dmac transfer: consists of a single buffer. multi-buffer dmac transfer: a dmac transfer may consist of multiple dmac buffers. multi-buf- fer dmac transfers are supported through buffer chaining (linked list pointers), auto-reloading of channel registers, and contiguous buffers. the source and destination can independently select which method to use. C linked lists (buffer chaining) ? a descriptor pointer (dscr) points to the location in system memory where the next linked list item (lli) exists. the lli is a set of registers that describe the next buffer (buffer descriptor) and a descriptor pointer register. the dmac fetches the lli at the beginning of every buffer when buffer chaining is enabled. C replay ? the dmac automatically reloads the channel registers at the end of each buffers to the value when the channel was first enabled. C contiguous buffers ? where the address of the next buffer is selected to be a continuation from the end of the previous buffer. picture-in-picture mode: dmac contains a picture-in-picture mode support. when this mode is enabled, addresses are automatically incremented by a programmable value when the dmac channel transfer count reaches a user defined boundary. figure 32-4 on page 484 illustrates a memory mapped image 4:2:2 encoded located at image_base_address in memory. a user defined start address is defined at picture_start_address. the incremented value is set to memory_hole_size = image_width - picture_width, and the boundary is set to picture_width. figure 32-4. picture-in-picture mode support dmac pip tr ans fer s
485 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 485 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 channel locking: software can program a channel to keep the ahb master interface by locking the arbitration for the master bus interface for the duration of a dmac transfer, buffer, or chunk. bus locking: software can program a channel to maintain control of the amba bus by asserting hmastlock for the duration of a dmac transfer, buffer, or transaction (single or chunk). channel locking is asserted for the duration of bus locking at a minimum. 32.4.2 memory peripherals figure 32-3 on page 483 shows the dmac transfer hierarchy of the dmac for a memory periph- eral. there is no handshaking interface with the dmac, and therefore the memory peripheral can never be a flow controller. once the channel is enabled, the transfer proceeds immediately without waiting for a transaction request. the alternative to not having a transaction-level hand- shaking interface is to allow the dmac to at tempt amba transfers to the peripheral once the channel is enabled. if the peripheral slave cannot accept these amba transfers, it inserts wait states onto the bus until it is ready; it is not recommended that more than 16 wait states be inserted onto the bus. by using the handshaking interface, the peripheral can signal to the dmac that it is ready to transmit/receive dat a, and then the dmac can access the peripheral without the peripheral inserting wait states onto the bus. 32.4.3 handshaking interface handshaking interfaces are used at the transaction level to control the flow of single or chunk transfers. the operation of the handshaking interface is different and depends on whether the peripheral or the dmac is the flow controller. the peripheral uses the handshaking interface to in dicate to the dmac that it is ready to trans- fer/accept data over the amba bus. a non-memory peripheral can request a dmac transfer through the dmac using one of two handshaking interfaces: ? hardware handshaking ? software handshaking software selects between the hardware or software handshaking interface on a per-channel basis. software handshaking is accomplished through memory-mapped registers, while hard- ware handshaking is accomplished usin g a dedicated handshaking interface. 32.4.3.1 software handshaking when the slave peripheral requires the dmac to perform a dmac transaction, it communicates this request by sending an interrupt to the cpu or interrupt controller. the interrupt service routine then uses the software registers to initiate and control a dmac transaction. these software registers are used to implement the software handshaking interface. the src_h2sel/dst_h2sel bit in the dmac_cfgx channel c onfiguration register must be set to zero to enable software handshaking. when the peripheral is not the flow controller, then the last transaction register dmac_last is not used, and the values in these registers are ignored. chunk transactions writing a 1 to the dmac_creq[2x] register starts a source chunk transaction request, where x is the channel number. writing a 1 to the dmac_creq[2x+1] register starts a destination chunk transfer request, where x is the channel number.
486 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 486 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 upon completion of the chunk transaction, the hardware clears the dmac_creq[ 2x ] or dmac_creq[2x+1]. single transactions writing a 1 to the dmac_sreq[2x] register starts a source single transaction request, where x is the channel number. writing a 1 to the dmac_s req[2x+1] register starts a destination single transfer request, where x is the channel number. upon completion of the chunk transaction, the hardware clears the dmac_sreq[x] or dmac_sreq[2x+1]. the software can poll the relevant channel bit in the dmac_creq[2x]/dmac_creq[2x+1] and dmac_sreq[x]/dmac_sreq[2x+1] registers. when both are 0, then either the requested chunk or single transaction has completed. 32.4.4 dmac transfer types a dmac transfer may consist of single or multi-buffer transfers. on successive buffers of a multi-buffer transfer, the dmac_saddrx/dmac_daddrx registers in the dmac are repro- grammed using either of the following methods: ? buffer chaining using linked lists ? replay mode ? contiguous address between buffers on successive buffers of a multi-buffer transfer, the dmac_ctrlax and dmac_ctrlbx regis- ters in the dmac are re-programmed using either of the following methods: ? buffer chaining using linked lists ? replay mode when buffer chaining using linked lists is the mu lti-buffer method of choice, and on successive buffers, the dmac_dscrx register in the dmac is re-programmed using the following method: ? buffer chaining using linked lists a buffer descriptor (lli) consists of foll owing registers, dmac_saddrx, dmac_daddrx, dmac_dscrx, dmac_ctrlax, dmac_ctrlb x.these registers, along with the dmac_cfgx register, are used by the dmac to set up and describe the buffer transfer. 32.4.4.1 multi-buffer transfers buffer chaining using linked lists in this case, the dmac re-programs the channel registers prior to the start of each buffer by fetching the buffer descriptor for that buffer from system memory. this is known as an lli update. dmac buffer chaining is supported by using a descriptor pointer register (dmac_dscrx) that stores the address in memory of the next buffer descriptor. each buffer descriptor contains the corresponding buffer descriptor (dma c_saddrx, dmac_daddrx, dmac_dscrx, dmac_ctrlax dmac_ctrlbx). to set up buffer chaining, a sequence of linked lists must be programmed in memory. the dmac_saddrx, dmac_daddrx, dmac _dscrx, dmac_ctrlax and dmac_ctrlbx registers are fetched from system memory on an lli update. the u pdated content of the dmac_ctrlax register is written back to memory on buffer completion. figure 32-5 on page
487 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 487 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 487 shows how to use chained linked lists in memory to define multi-buffer transfers using buffer chaining. the linked list multi-buffer transfer is init iated by programming dmac_dscrx with dscrx(0) (lli(0) base address) different from zero. other fields and registers are ignored and overwritten when the descriptor is retrieved from memory. the last transfer descriptor must be written to memory with its next descriptor address set to 0. figure 32-5. multi buffer transfer using linked list descriptor integrity check when the descriptor integrity check is enabled, a cyclic redundancy check information is attached to the descriptor. when fetched from the memory, the descriptor is verified through the use of a crc16-ccit (0x1021 polynom) by the dmac channel. if a crc error is detected, then the dicerr flag is set in the dmac_ebcisr re gister. the crc16 is computed from msb to lsb. the btsize and done fields of the dmac_ctrlax register are ignored and set to zero. system memory saddrx = dscrx(0) + 0x0 daddrx = dscrx(0) + 0x4 ctrlax = dscrx(0) + 0x8 ctrlbx = dscrx(0) + 0xc dscrx(1) = dscrx(0) + 0x10 saddrx = dscrx(1) + 0x0 daddrx = dscrx(1) + 0x4 ctrlbx = dscrx(1) + 0x8 ctrlbx = dscrx(1) + 0xc dscrx(2) = dscrx(1) + 0x10 dscrx(0) dscrx(2) (points to 0 if lli(1) is the last transfer descriptor dscrx(1) lli(0) lli(1)
488 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 488 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 32-6. linked list with crc16 attached system memory saddrx = dscrx(0) + 0x0 daddrx = dscrx(0) + 0x4 ctrlax = dscrx(0) + 0x8 ctrlbx = dscrx(0) + 0xc dscrx(1) = dscrx(0) + 0x10 saddrx = dscrx(1) + 0x0 daddrx = dscrx(1) + 0x4 ctrlbx = dscrx(1) + 0x8 ctrlbx = dscrx(1) + 0xc dscrx(2) = dscrx(1) + 0x10 dscrx(0) dscrx(2) (points to 0 if lli(1) is the last transfer descriptor dscrx(1) lli(0) lli(1) crcx(1) = dscrx(0) + 0x14 crcx(2) = dscrx(1) + 0x14
489 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 489 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 32.4.4.2 programming dmac for multiple buffer transfers notes: 1. usr means that the register field is manually programmed by the user. 2. cont means that address are contiguous. 3. rep means that the register field is updat ed with its previous value. if the transfer is the first one, then the user must ma nu- ally program the value. 4. channel stalled is true if the relevant btc interrupt is not masked. 5. lli means that the register field is updat ed with the content of the linked list item. replay mode of channel registers during automatic replay mode, the channel registers are reloaded with their initial values at the completion of each buffer and the new values used for the new buffer. depending on the row number in table 32-2 on page 489 , some or all of the dmac_saddrx, dmac_daddrx, dmac_ctrlax and dmac_ctrlbx channel register s are reloaded from their initial value at the start of a buffer transfer. contiguous address between buffers in this case, the address between successive buffers is selected to be a continuation from the end of the previous buffer. enabling the source or destination address to be contiguous between table 32-2. multiple buffers transfer management table transfer type auto src_rep dst_rep src_dscr dst_dscr btsize dscr saddr daddr other fields 1) single buffer or last buffer of a multiple buffer transfer 0 C C C C usr 0 usr usr usr 2) multi buffer transfer with contiguous daddr 0 C 0 0 1 lli usr lli cont lli 3) multi buffer transfer with contiguous saddr 0 0 C 1 0 lli usr cont lli lli 4) multi buffer transfer with lli support 0 C C 0 0 lli usr lli lli lli 5) multi buffer transfer with daddr reloaded 0 C 1 0 1 lli usr lli rep lli 6) multi buffer transfer with saddr reloaded 0 1 C 1 0 lli usr rep lli lli 7) multi buffer transfer with btsize reloaded and contiguous daddr 1 C 0 0 1 rep usr lli cont lli 8) multi buffer transfer with btsize reloaded and contiguous saddr 1 0 C 1 0 rep usr cont lli lli 9) automatic mode channel is stalling btsize is reloaded 1 0 0 1 1 rep usr cont cont rep 10) automatic mode btsize, saddr and daddr reloaded 1 1 1 1 1 rep usr rep rep rep 11) automatic mode btsize, saddr reloaded and daddr contiguous 1 1 0 1 1 rep usr rep cont rep
490 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 490 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 buffers is a function of dmac_c trlax.src_dscr, dmac_cfgx.dst_rep, dmac_cfgx.src_rep and dmac_ctrlax.dst_dscr registers. suspension of transfers between buffers at the end of every buffer transfer, an end of buffer interrupt is asserted if: ? the channel buffer interrupt is unmasked, dmac _ebcimr.btcx = 1, where x is the channel number. note: the buffer transfer completed interrupt is generated at the completion of the buffer transfer to the destination. at the end of a chain of multiple buffers, an end of linked list interrupt is asserted if: ? the channel end of the chained buffer transfer completed interrupt is unmasked, dmac_ebcimr.cbtcx = 1, when n is the channel number. 32.4.4.3 ending multi-buffer transfers all multi-buffer transfers must end as shown in row 1 of table 32-2 on page 489 . at the end of every buffer transfer, the dmac samples the row number, and if the dmac is in row 1 state, then the previous buffer transferred was the last buffer and the dmac transfer is terminated. for rows 9, 10 and 11 of table 32-2 on page 489 , (dmac_dscrx = 0 and dmac_ctrlbx.auto is set), mult i-buffer dmac transfers continue until the automatic mode is disabled by writing a 1 in dm ac_ctrlbx.auto bit. this bit should be programmed to zero in the end of buffer interrupt service routine that services the next-to-last buffer transfer. this puts the dmac into row 1 state. for rows 2, 3, 4, 5, and 6 (dmac_crtlbx.auto cleared), the user must set up the last buffer descriptor in memory so that both lli.dmac_ctrlbx.src_dscr and lli.dmac_ctrlbx.dst_dscr are one and lli.dmac_dscrx is set to 0. for rows 2, 3, 4, 5, and 6 (dmac_crtlbx.auto cleared), the user must set up the last buffer descriptor in memory so that lli.dmac_ctrlbx.src_dscr is set to 0. 32.4.5 programming a channel four registers, the dmac_dscrx, the dmac_ctrlax, the dmac_ctrlbx and dmac_cfgx, need to be programmed to set up whether single or multi-buffer transfers take place, and which type of multi-buffer transfer is used. the different transfer types are shown in table 32-2 on page 489 . the btsize, saddr and daddr columns in dicate where the values of dmac_sarx, dmac_darx, dmac_ctlx, and dmac_llpx are obtained for the next buffer transfer when multi-buffer dmac transfers are enabled. 32.4.5.1 programming examples single-buffer transfer (row 1) 1. read the channel handler status register dmac_chsr.enax field to choose a free (disabled) channel. 2. clear any pending interrupts on the channel from the previous dmac transfer by read- ing the interrupt status register, dmac_ebcisr. 3. program the following channel registers:
491 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 491 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 a. write the starting source address in the dmac_saddrx register for channel x. b. write the starting destination address in the dmac_daddrx register for channel x. c. write the next descriptor address in the dma_dscrx re gister for channel x with 0x0. d. program dmac_ctrlax, dmac_ctrlbx and dmac_cfgx according to row 1 as shown in table 32-2 on page 489 . program the dmac_ctrlbx register with both auto fields set to 0. e. write the control information for the dmac transfer in the dmac_ctrlax and dmac_ctrlbx registers for channel x. for example, in the register, you can pro- gram the following: C i. set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the fc of the dmac_ctrlbx register. C ii. set up the transfer characteristics, such as: C transfer width for the source in the src_width field. C transfer width for the desti nation in the dst_width field. C source ahb master interface layer in the sif field where source resides. C destination ahb master interface layer in the dif field where destination resides. C incrementing/decrementing or fixed address for source in src_inc field. C incrementing/decrementing or fixed address for destination in dst_inc field. f. write the channel configuration information into the dmac_cfgx register for chan- nel x. C i. designate the handshaking interface type (hardware or software) for the source and destination peripherals. this is not required for memory. this step requires programming the src_h2sel/dst_h2sel bits, respectively. writing a 1 activates the hardware handshaking interface to handle source/destination requests. writing a 0 activates the software handshaking interface to handle source/destination requests. C ii. if the hardware handshaking interface is activated for the source or destination peripheral, assign a handshaking interface to the source and destination peripheral. this requires programming the src_per and dst_per bits, respectively. g. if source picture-in-picture mode is enabled (dmac_ctrlbx.src_pip is enabled), program the dmac_spipx register for channel x. h. if destination picture-in-picture mode is enabled (dmac_ctrlbx.dst_pip is enabled), program the dmac_dpipx register for channel x. 4. after the dmac selected channel has been programmed, enable the channel by writing a 1 to the dmac_cher.enax bit, where x is the channel number. make sure that bit 0 of dmac_en.enable register is enabled. 5. source and destination request single and chunk dmac transactions to transfer the buffer of data (assuming non-memory peripherals). the dmac acknowledges at the completion of every transaction (chunk and single) in the buffer and carries out the buf- fer transfer. 6. once the transfer completes, the hardware sets the interrupts and disables the chan- nel. at this time, you can either respond to the buffer transfer completed interrupt or chained buffer transfer completed interrupt, or poll for the channel handler status
492 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 492 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 register (dmac_chsr.enax) bit until it is cleared by hardware, to detect when the transfer is complete. multi-buffer transfer with linked list for source and linked list for destination (row 4) 1. read the channel handler status register to choose a free (disabled) channel. 2. set up the chain of linked list items (otherwise known as buffer descriptors) in mem- ory. write the control information in the lli.dmac_ctrlax and lli.dmac_ctrlbx registers location of the buffer descriptor for each lli in memory (see figure 32-7 on page 494 ) for channel x. for example, in the register, you can program the following: a. set up the transfer type (memory or non-memory peripheral for source and desti- nation) and flow control device by programming the fc of the dmac_ctrlbx register. b. set up the transfer characteristics, such as: C i. transfer width for the source in the src_width field. C ii. transfer width for the dest ination in the dst_width field. C iii. source ahb master in terface layer in the sif field where source resides. C iv. destination ahb master interface layer in the dif field where destination resides. C v. incrementing/decrementing or fixed address for source in src_incr field. C vi. incrementing/decrement ing or fixed address for destination dst_incr field. 3. write the channel configuration information into the dmac_cfgx register for channel x. a. designate the handshaking interface type (hardware or software) for the source and destination peripherals. this is not required for memory. this step requires pro- gramming the src_h2sel/dst_h2sel bits, respectively. writing a 1 activates the hardware handshaking interface to ha ndle source/destination requests for the specific channel. writing a 0 activates the software handshaking interface to han- dle source/destination requests. b. if the hardware handshaking interface is activated for the source or destination peripheral, assign the handshaking interface to the source and destination periph- eral. this requires programming the src_per and dst_per bits, respectively. 4. make sure that the lli.dmac_ctrlbx register locations of all lli entries in memory (except the last) are set as shown in row 4 of table 32-2 on page 489 . the lli.dmac_ctrlbx register of the last linked list item must be set as described in row 1 of table 32-2 . figure 32-5 on page 487 shows a linked list example with two list items. 5. make sure that the lli.dmac_dscrx register locations of all lli entries in memory (except the last) are non-zero and point to the base address of the next linked list item. 6. make sure that the lli.dmac_saddrx/lli. dmac_daddrx register locations of all lli entries in memory point to the start source/destination buffer address preceding that lli fetch. 7. make sure that the lli.dmac_ctrlax.done field of the lli.dmac_ctrlax register locations of all lli entries in memory are cleared. 8. if source picture-in-picture mode is enabled (dmac_ctrlbx.src_pip is enabled), program the dmac_spipx register for channel x. 9. if destination picture-in-picture is enabled (dmac_ctrlbx.dst_pip is enabled), pro- gram the dmac_dpipx register for channel x. 10. clear any pending interrupts on the channel from the previous dmac transfer by read- ing the status register: dmac_ebcisr.
493 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 493 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 11. program the dmac_ctrlbx, dmac_cfgx registers according to row 4 as shown in table 32-2 on page 489 . 12. program the dmac_dscrx register with dmac_dscrx(0), the pointer to the first linked list item. 13. finally, enable the channel by writing a 1 to the dmac_cher.enax bit, where x is the channel number. the transfer is performed. 14. the dmac fetches the first lli from the location pointed to by dmac_dscrx(0). note: the lli.dmac_saddrx, lli. dmac_daddrx, lli.dmac_dscrx, lli.dmac_ctrlax and lli.dmac_ctrlbx registers are fetched. the dmac automatically reprograms the dmac_saddrx, dmac_daddrx, dmac_dscrx, dmac_ctrlbx and dmac_ctrlax chan- nel registers from the dmac_dscrx(0). 15. source and destination request single and chunk dmac transactions to transfer the buffer of data (assuming non-memory peripheral). the dmac acknowledges at the completion of every transaction (chunk and single) in the buffer and carries out the buf- fer transfer. 16. once the buffer of data is transferred, the dmac_ctrlax register is written out to sys- tem memory at the same location and on the same layer (dmac_dscrx.dscr_if) where it was originally fetched, that is, the location of the dmac_ctrlax register of the linked list item fetched prior to the start of the buffer transfer. only dmac_ctrlax register is written out because only the dmac_ctrlax.btsize and dmac_ctrlax.done bits have been updated by dmac hardware. additionally, the dmac_ctrlax.done bit is asserted when the buffer transfer has completed. note: do not poll the dmac_ctrlax.done bit in the dmac memory map. instead, poll the lli.dmac_ctrlax.done bit in the lli for that buffer. if the poll lli.dmac_ctrlax.done bit is asserted, then this buffer transfer has complet ed. this lli.dmac_ctrlax.done bit was cleared at the start of the transfer. 17. the dmac does not wait for the buffer interrupt to be cleared, but continues fetching the next lli from the memory location pointed to by current dmac_dscrx register and automatically reprograms the dmac_saddrx, dmac_daddrx, dmac_dscrx, dmac_ctrlax and dmac_ctrlbx channel registers. the dmac transfer continues until the dmac determines that the dmac_ctrlbx and dmac_dscrx registers at the end of a buffer transfer match described in row 1 of table 32-2 on page 489 . the dmac then knows that the previous buffer transferred was the last buffer in the dmac transfer. the dmac transfer might look like that shown in figure 32-7 on page 494 .
494 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 494 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 32-7. multi-buffer with linked list address for source and destination if the user needs to execute a dmac transfer where the source and destination address are contiguous but the amount of data to be transferred is greater than the maximum buffer size dmac_ctrlax.btsize, then this can be achieved using the type of multi-buffer transfer as shown in figure 32-8 on page 495 . saddr(2) saddr(1) saddr(0) daddr(2) daddr(1) daddr(0) buffer 2 buffer 1 buffer 0 buffer 0 buffer 1 buffer 2 address of source layer address of destination layer source buffers destination buffers
495 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 495 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 32-8. multi-buffer with linked address for source and destination buffers are contiguous the dmac transfer flow is shown in figure 32-9 on page 496 . saddr(2) saddr(1) saddr(0) daddr(2) daddr(1) daddr(0) buffer 2 buffer 1 buffer 0 buffer 0 buffer 1 buffer 2 address of source layer address of destination layer source buffers destination buffers saddr(3) buffer 2 daddr(3) buffer 2
496 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 496 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 32-9. dmac transfer flow for source and destination linked list address multi-buffer transfer with source address auto-reloaded and destination address auto-reloaded (row 10) 1. read the channel handler status register to choose an available (disabled) channel. 2. clear any pending interrupts on the channel from the previous dmac transfer by read- ing the interrupt status register. program the following channel registers: channel enabled by software lli fetch hardware reprograms saddrx, daddrx, ctrla/bx, dscrx dmac buffer transfer writeback of dmac_ctrlax register in system memory is dmac in row 1 of dmac state machine table? channel disabled by hardware chained buffer transfer completed interrupt generated here dmac chained buffer transfer completed interrupt generated here yes no
497 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 497 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 a. write the starting source address in the dmac_saddrx register for channel x. b. write the starting destination address in the dmac_daddrx register for channel x. c. program dmac_ctrlax, dmac_ctrlbx and dmac_cfgx according to row 10 as shown in table 32-2 on page 489 . program the dmac_dscrx register with 0. d. write the control information for the dmac transfer in the dmac_ctrlax and dmac_ctrlbx register for channel x. for example, in the register, you can pro- gram the following: C i. set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the fc of the dmac_ctrlbx register. C ii. set up the transfer characteristics, such as: C transfer width for the source in the src_width field. C transfer width for the desti nation in the dst_width field. C source ahb master interface layer in the sif field where source resides. C destination ahb master interface layer in the dif field where destination resides. C incrementing/decrementing or fixed address for source in src_incr field. C incrementing/decrementing or fixed address for destination in dst_incr field. e. if source picture-in-pic ture mode is enabled (dmac_ctrlbx.spip is enabled), program the dmac_spipx register for channel x. f. if destination picture-in-picture is enabled (dmac_ctrlbx.dpip), program the dmac_dpipx register for channel x. g. write the channel configuration information into the dmac_cfgx register for chan- nel x. ensure that the relo ad bits, dmac_cfgx.src_rep, dmac_cfgx.dst_rep and dmac_ctrlbx.auto are enabled. C i. designate the handshaking interface type (hardware or software) for the source and destination peripherals. this is not required for memory. this step requires programming the src_h2sel/dst_h2sel bits, respectively. writing a 1 activates the hardware handshaking interface to ha ndle source/destination requests for the specific channel. writing a 0 activates the software handshaking interface to handle source/destination requests. C ii. if the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripheral. this requires programming the src_per and dst_per bits, respectively. 3. after the dmac selected channel has been programmed, enable the channel by writing a 1 to the dmac_cher.enax bit where the channel number is. make sure that bit 0 of the dmac_en register is enabled. 4. source and destination request single and chunk dmac transactions to transfer the buffer of data (assuming non-memory peripherals). the dmac acknowledges on com- pletion of each chunk/single transaction and carries out the buffer transfer. 5. when the buffer transfer has completed, the dmac reloads the dmac_saddrx, dmac_daddrx and dmac_ctrlax registers. the hardware sets the buffer transfer completed interrupt. the dmac then samples the row number as shown in table 32-2 on page 489 . if the dmac is in row 1, then the dmac transfer has completed. the hardware sets the chained buffer transfer completed interrupt and disables the chan- nel. so you can either respond to the buffer transfer completed interrupt or chained
498 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 498 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 buffer transfer completed interrupt, or poll for the channel enable in the channel sta- tus register (dmac_chsr.enax) until it is di sabled, to detect when the transfer is complete. if the dmac is not in row 1, the next step is performed. 6. the dmac transfer proceeds as follows: a. if the buffer transfer completed interrupt is unmasked (dmac_ebcimr.btcx = 1, where x is the channel number), the hardware sets the buffer transfer com- pleted interrupt when the buffer transfer has completed. it then stalls until the stalx bit of dmac_chsr register is cleared by software, writing 1 to dmac_cher.keepx bit, where x is the channel number. if the next buffer is to be the last buffer in the dmac transfer, then the buffer complete isr (interrupt service routine) should clear the automatic mode bit in the dmac_ctrlbx.auto bit. this puts the dmac into row 1 as shown in table 32-2 on page 489 . if the next buffer is not the last buffer in the dmac transfer, then the reload bits should remain enabled to keep the dmac in row 4. b. if the buffer transfer completed interrupt is masked (dmac_ebcimr.btcx = 0, where x is the channel number), the hardware does not stall until it detects a write to the buffer transfer completed interrupt enable register dmac_ebcier register, but starts the next buffer transfer immediately. in this case, the software must clear the automatic mode bit in the dmac_ctrlb to put the dmac into row 1 of table 32-2 on page 489 before the last buffer of the dmac transfer has completed. the transfer is similar to that shown in figure 32-10 on page 498 . the dmac transfer flow is shown in figure 32-11 on page 499 . figure 32-10. multi-buffer dmac transfer with source and destination address auto-reloaded address of source layer address of destination layer source buffers destination buffers blockn block2 block1 block0 saddr daddr
499 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 499 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 32-11. dmac transfer flow for source and destination address auto-reloaded multi-buffer transfer with source address auto-reloaded and linked list destination address (row 6) 1. read the channel handler status register to choose a free (disabled) channel. 2. set up the chain of linked list items (otherwise known as buffer descriptors) in memory. write the control information in the lli.dmac_ctrlax and dmac_ctrlbx registers location of the buffer descriptor for each lli in memory for channel x. for example, in the register, you can program the following: a. set up the transfer type (memory or non-memory peripheral for source and desti- nation) and flow control peripheral by programming the fc of the dmac_ctrlbx register. b. set up the transfer characteristics, such as: C i. transfer width for the source in the src_width field. C ii. transfer width for the dest ination in the dst_width field. C iii. source ahb master in terface layer in the sif field where source resides. C iv. destination ahb master interface layer in the dif field where destination resides. C v. incrementing/decrementing or fixed address for source in src_incr field. C vi. incrementing/decrement ing or fixed address for destination dst_incr field. channel enabled by software buffer transfer replay mode for saddrx, daddrx, ctrlax, ctrlbx channel disabled by hardware buffer transfer completed interrupt generated here dmac chained buffer transfer completed interrupt generated here yes no yes stall until stallx is cleared by writing to keepx field ebcimr[x]=1? no is dmac in row 1 of dmac state machine table?
500 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 500 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 3. write the starting source address in the dmac_saddrx register for channel x. note: the values in the lli.dmac_saddrx register loca tions of each of the linked list items (llis) set up in memory, although fetched during an lli fetch, are not used. 4. write the channel configuration information into the dmac_cfgx register for channel x. a. designate the handshaking interface type (hardware or software) for the source and destination peripherals. this is not required for memory. this step requires pro- gramming the src_h2sel/dst_h2sel bits, respectively. writing a 1 activates the hardware handshaking interface to ha ndle source/destination requests for the specific channel. writing a 0 activates the software handshaking interface source/destination requests. b. if the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripheral. this requires programming the src_per and dst_per bits, respectively. 5. make sure that the lli.dmac_ctrlbx register locations of all llis in memory (except the last one) are set as shown in row 6 of table 32-2 on page 489 while the lli.dmac_ctrlbx register of the last linked list item must be set as described in row 1 of table 32-2 . figure 32-5 on page 487 shows a linked list example with two list items. 6. make sure that the lli.dmac_dscrx register locations of all llis in memory (except the last one) are non-zero and point to the next linked list item. 7. make sure that the lli.dmac_daddrx register locations of all llis in memory point to the start destination buffer address proceeding that lli fetch. 8. make sure that the lli.dmac_ctlx.done field of the lli.dmac_ctrla register locations of all llis in memory is cleared. 9. if source picture-in-picture is enabled (dmac_ctrlbx.spip is enabled), program the dmac_spipx register for channel x. 10. if destination picture-in-picture is enabled (dmac_ctrlbx.dpip is enabled), program the dmac_dpipx register for channel x. 11. clear any pending interrupts on the channel from the previous dmac transfer by read- ing to the dmac_ebcisr register. 12. program the dmac_ctlx and dmac_cfgx registers according to row 6 as shown in table 32-2 on page 489 . 13. program the dmac_dscrx register with dmac_dscrx(0), the pointer to the first linked list item. 14. finally, enable the channel by writing a 1 to the dmac_cher.enax bit, where x is the channel number. the transfer is performed. make sure that bit 0 of the dmac_en reg- ister is enabled. 15. the dmac fetches the first lli from the location pointed to by dmac_dscrx(0). note: the lli.dmac_saddrx, lli.dmac_daddrx , lli. dmac_llpx lli.dmac_ctrlax and lli.dmac_ctrlbx registers are fetched. the ll i.dmac_saddrx register, although fetched, is not used. 16. source and destination request single and chunk dmac transactions to transfer the buffer of data (assuming non-memory peripherals). dmac acknowledges at the com- pletion of every transaction (chunk and single) in the buffer and carries out the buffer transfer. 17. the dmac_ctrlax register is written out to the system memory. the dmac_ctrlax register is written out to the same location on the same layer (dmac_dscrx.dscr_if) where it was origina lly fetched, that is the location of the dmac_ctrlax register of the linked list item fetched prior to the start of the buffer
501 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 501 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 transfer. only dmac_ctrlax register is written out, because only the dmac_ctrlax.btsize and dmac_ctrlax.done fields have been updated by hardware within the dmac. the lli.dmac_ctrlax.done bit is asserted to indicate buffer completion. therefore, the software can poll the lli.dmac_ctrlax.done field of the dmac_ctrlax register in the lli to ascertain when a buffer transfer has completed. note: do not poll the dmac_ctrlax.done bit in the dmac memory map. instead, poll the lli.dmac_ctrlax.done bit in the lli for that buffer. if the polled lli.dmac_ctrlax.done bit is asserted, then this buffer transfer has completed. this lli.dmac_ctrla.done bit was cleared at the start of the transfer. 18. the dmac reloads the dmac_saddrx register from the initial value. the hardware sets the buffer transfer completed interrupt. the dmac samples the row number as shown in table 32-2 on page 489 . if the dmac is in row 1, then the dmac transfer has completed. the hardware sets the chained buffer transfer completed interrupt and disables the channel. you can either respond to the buffer transfer completed interrupt or chained buffer transfer completed interrupt, or poll for the channel enable. (dmac_chsr.enax) bit until it is cleared by hardware, to detect when the transfer is complete. if the dmac is not in row 1 as shown in table 32-2 on page 489 , the follow- ing step is performed. 19. the dmac fetches the next lli from the memory location pointed to by the current dmac_dscrx register, and automatically reprograms the dmac_daddrx, dmac_ctrlax, dmac_ctrlbx and dmac_dscrx channel registers. note that the dmac_saddrx is not re-programmed as the reloaded value is used for the next dmac buffer transfer. if the next buffer is the last buffer of the dmac transfer, then the dmac_ctrlbx and dmac_dscrx registers just fetched from the lli should match row 1 of table 32-2 on page 489 . the dmac transfer might look like that shown in fig- ure 32-12 on page 501 . figure 32-12. multi-buffer dmac transfer with source address auto-reloaded and linked list destination address the dmac transfer flow is shown in figure 32-13 on page 502 . address of source layer address of destination layer source buffers destination buffers saddr buffer0 buffer1 buffer2 buffern daddr(n) daddr(1) daddr(0) daddr(2)
502 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 502 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 32-13. dmac transfer flow for replay mode at source and linked list destination address multi-buffer transfer with source address auto-reloaded and contiguous destination address (row 11) 1. read the channel handler status register to choose a free (disabled) channel. 2. clear any pending interrupts on the channel from the previous dmac transfer by read- ing to the interrupt status register. 3. program the following channel registers: a. write the starting source address in the dmac_saddrx register for channel x. b. write the starting destination address in the dmac_daddrx register for channel x. c. program dmac_ctrlax, dmac_ctrlbx and dmac_cfgx according to row 11 as shown in table 32-2 on page 489 . program the dmac_dscrx register with 0. dmac_ctrlbx.auto field is set to 1 to enable automatic mode support. d. write the control information for the dmac transfer in the dmac_ctrlbx and dmac_ctrlax register for channel x. for example, in this register, you can pro- gram the following: C i. set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the fc of the dmac_ctrlbx register. C ii. set up the transfer characteristics, such as: channel enabled by software lli fetch yes no hardware reprograms daddrx, ctrlax, ctrlbx, dscrx dmac buffer transfer writeback of control status information in lli reload saddrx buffer transfer completed interrupt generated here dmac chained buffer transfer completed interrupt generated here channel disabled by hardware is dmac in row 1 of dmac state machine table?
503 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 503 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 C transfer width for the source in the src_width field. C transfer width for the desti nation in the dst_width field. C source ahb master interface layer in the sif field where source resides. C destination ahb master interface master layer in the dif field where destination resides. C incrementing/decrementing or fixed address for source in src_incr field. C incrementing/decrementing or fixed address for destination in dst_incr field. e. if source picture-in-picture is enable d (dmac_ctrlbx.spip is enabled), program the dmac_spipx register for channel x. f. if destination picture-in-picture is enabled (dmac_ctrlbx.dpip), program the dmac_dpipx register for channel x. g. write the channel configuration information into the dmac_cfgx register for chan- nel x. C i. designate the handshaking interface type (hardware or software) for the source and destination peripherals. this is not required for memory. this step requires programming the src_h2sel/dst_h2sel bits, respectively. writing a 1 activates the hardware handshaking interface to ha ndle source/destination requests for the specific channel. writing a 0 activates the software handshaking interface to handle source/destination requests. C ii. if the hardware handshaking interface is activated for the source or destination peripheral, assign the handshaking interface to the source and destination peripheral. this requires programming the src_per and dst_per bits, respectively. 4. after the dmac channel has been programmed, enable the channel by writing a 1 to the dmac_cher.enax bit, where x is the channel number. make sure that bit 0 of the dmac_en.enable register is enabled. 5. source and destination request single and chunk dmac transactions to transfer the buffer of data (assuming non-memory peripherals). the dmac acknowledges at the completion of every transaction (chunk and single) in the buffer and carries out the buf- fer transfer. 6. when the buffer transfer has completed, the dmac reloads the dmac_saddrx regis- ter. the dmac_daddrx register remains unchanged. the hardware sets the buffer transfer completed interrupt. the dmac then samples the row number as shown in table 32-2 on page 489 . if the dmac is in row 1, then the dmac transfer has com- pleted. the hardware sets the chained buffer transfer completed interrupt and disables the channel. so you can either respond to the buffer transfer completed inter- rupt or chained buffer transfer completed interrupt, or poll for the enable (enax) field in the channel status register (dmac_chsr.en ax bit) until it is cleared by hardware, to detect when the transfer is complete. if the dmac is not in row 1, the next step is performed. 7. the dmac transfer proceeds as follows: a. if the buffer transfer completed interrupt is unmasked (dmac_ebcimr.btcx = 1, where x is the channel number), the hardware sets the buffer transfer com- pleted interrupt when the buffer transfer has completed. it then stalls until stalx bit of dmac_chsr is cleared by writing in the keepx field of dmac_cher register, where x is the channel number. if the next buffer is to be the last buffer in the dmac transfer, then the buffer complete isr (interrupt service routine) should clear the automatic mode bit, dmac_ctrlbx.auto. this puts the dmac into row 1 as shown in table 32-2 on page 489 . if the next buffer is not the last buffer in the
504 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 504 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 dmac transfer, then the automatic transfer mode bit should remain enabled to keep the dmac in row 11 as shown in table 32-2 on page 489 . b. if the buffer transfer completed interrupt is masked (dmac_ebcimr.btcx = 0, where x is the channel number), the hardware does not stall until it detects a write to the buffer transfer completed interrupt enable register, but starts the next buffer transfer immediately. in this case, the software must clear the automatic mode bit, dmac_ctrlbx.auto, to put the device into row 1 of table 32-2 on page 489 before the last buffer of the dmac transfer has completed. the transfer is similar to that shown in figure 32-14 on page 504 . the dmac transfer flow is shown in figure 32-15 on page 505 . figure 32-14. multi-buffer transfer with source address auto-reloaded and contiguous destination address address of source layer address of destination layer source buffers destination buffers saddr buffer0 buffer1 buffer2 daddr(1) daddr(0) daddr(2)
505 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 505 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 32-15. dmac transfer replay mode is enabled for th e source and contiguous destination address multi-buffer dmac transfer with linked list for s ource and contiguous destination address (row 2) 1. read the channel handler status register to choose a free (disabled) channel. 2. set up the linked list in memory. wr ite the control information in the lli.dmac_ctrlax and lli.dmac_ctrlbx register location of the buffer descriptor for each lli in memory for channel x. for example, in the register, you can program the following: a. set up the transfer type (memory or non-memory peripheral for source and desti- nation) and flow control device by programming the fc of the dmac_ctrlbx register. b. set up the transfer characteristics, such as: C i. transfer width for the source in the src_width field. C ii. transfer width for the dest ination in the dst_width field. C iii. source ahb master in terface layer in the sif field where source resides. C iv. destination ahb master interface layer in the dif field where destination resides. channel enabled by software buffer transfer replay mode for saddrx, contiguous mode for daddrx ctrlax, ctrlbx channel disabled by hardware buffer transfer completed interrupt generated here buffer transfer completed interrupt generated here yes no no yes stall until stallx field is cleared by software writing keepx field dma_ebcimr[x]=1? is dmac in row 1 of dmac state machine table?
506 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 506 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 C v. incrementing/decrementing or fixed address for source in src_incr field. C vi. incrementing/decrement ing or fixed address for destination dst_incr field. 3. write the starting destination address in the dmac_daddrx register for channel x. note: the values in the lli.dmac_daddrx register location of each linked list item (lli) in memory, although fetched during an lli fetch, are not used. 4. write the channel configuration information into the dmac_cfgx register for channel x. a. designate the handshaking interface type (hardware or software) for the source and destination peripherals. this is not required for memory. this step requires pro- gramming the src_h2sel/dst_h2sel bits, respectively. writing a 1 activates the hardware handshaking interface to ha ndle source/destination requests for the specific channel. writing a 0 activates the software handshaking interface to han- dle source/destination requests. b. if the hardware handshaking interface is activated for the source or destination peripheral, assign the handshaking interface to the source and destination periph- erals. this requires programming the src_per and dst_per bits, respectively. 5. make sure that all lli.dmac_ctrlbx register locations of the lli (except the last) are set as shown in row 2 of table 32-2 on page 489 , while the lli.dmac_ctrlbx regis- ter of the last linked list item must be set as described in row 1 of table 32-2 . figure 32-5 on page 487 shows a linked list example with two list items. 6. make sure that the lli.dmac_dscrx register locations of all llis in memory (except the last) are non-zero and point to the next linked list item. 7. make sure that the lli.dmac_saddrx register locations of all llis in memory point to the start source buffer address proceeding that lli fetch. 8. make sure that the lli.dmac_ctrlax.done field of the lli.dmac_ctrlax register locations of all llis in memory is cleared. 9. if source picture-in-picture is enabled (dmac_ctrlbx.spip is enabled), program the dmac_spipx register for channel x. 10. if destination picture-in-picture is enabled (dmac_ctrlbx.dpip is enabled), program the dmac_dpipx register for channel x. 11. clear any pending interrupts on the channel from the previous dmac transfer by read- ing the interrupt status register. 12. program the dmac_ctrlax, dmac_ctrlbx and dmac_cfgx registers according to row 2 as shown in table 32-2 on page 489 13. program the dmac_dscrx register with dmac_dscrx(0), the pointer to the first linked list item. 14. finally, enable the channel by writing a 1 to the dmac_cher.enax bit. the transfer is performed. make sure that bit 0 of the dmac_en register is enabled. 15. the dmac fetches the first lli from the location pointed to by dmac_dscrx(0). note: the lli.dmac_saddrx, lli.dmac_daddrx, lli.dmac_dscrx and lli.dmac_ctrla/bx registers are fetched. the lli.dm ac_daddrx register location of the lli, although fetched, is not used. the dmac_daddrx register in the dmac remains unchanged. 16. source and destination requests single and chunk dmac transactions to transfer the buffer of data (assuming non-memory peripherals). the dmac acknowledges at the completion of every transaction (chunk and single) in the buffer and carries out the buf- fer transfer. 17. once the buffer of data is transferred, the dmac_ctrlax register is written out to the system memory at the same location and on the same layer (dmac_dscrx.dscr_if) where it was originally fetched, that is, the location of the
507 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 507 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 dmac_ctrlax register of the linked list item fetched prior to the start of the buffer transfer. only dmac_ctrlax register is written out because only the dmac_ctrlax.btsize and dmac_ctrlax.done fields have been updated by dmac hardware. additionally, the dmac_ctrlax.done bit is asserted when the buf- fer transfer has completed. note: do not poll the dmac_ctrlax.done bit in the dmac memory map. instead, poll the lli.dmac_ctrlax.done bit in the lli for that buffer. if the poll lli.dmac_ctrlax.done bit is asserted, then this buffer transfer has complet ed. this lli.dmac_ctrlax.done bit was cleared at the start of the transfer. 18. the dmac does not wait for the buffer interrupt to be cleared, but continues and fetches the next lli from the memory location pointed to by the current dmac_dscrx register, then automatically reprograms the dmac_saddrx, dmac_ctrlax, dmac_ctrlbx and dmac_dscrx channel registers. the dmac_daddrx register is left unchanged. the dmac transfer continues until the dmac samples the dmac_ctrlax, dmac_ctrlbx and dmac_dscrx registers at the end of a buffer transfer match that described in row 1 of table 32-2 on page 489 . the dmac then knows that the previous buffer transferred was the last buffer in the dmac transfer. the dmac transfer might look like that shown in figure 32-16 on page 507 . note that the desti- nation address is decrementing. figure 32-16. dmac transfer with linked list source address and contiguous destination address the dmac transfer flow is shown in figure 32-17 on page 508 . saddr(2) saddr(1) saddr(0) daddr(2) daddr(1) daddr(0) buffer 2 buffer 1 buffer 0 buffer 0 buffer 1 buffer 2 address of source layer address of destination layer source buffers destination buffers
508 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 508 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 32-17. dmac transfer flow for linked list source address and contiguous destination address 32.4.6 disabling a channel prior to transfer completion under normal operation, the software enables a channel by writing a 1 to the channel handler enable register, dmac_cher.enax, and the hardw are disables a channel on transfer comple- tion by clearing the dmac_chsr.enax register bit. the recommended way for software to disable a channel without losing data is to use the suspx bit in conjunction with the emptx bit in the channel handler status register. channel enabled by software lli fetch hardware reprograms saddrx, ctrlax,ctrlbx, dscrx dmac buffer transfer writeback of control information of lli is dmac in row 1 ? channel disabled by hardware buffer transfer completed interrupt generated here dmac chained buffer transfer completed interrupt generated here yes no
509 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 509 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1. if the software wishes to disable a channel n prior to the dmac transfer completion, then it can set the dmac_cher.suspx bit to tell the dmac to halt all transfers from the source peripheral. therefore, the channel fifo receives no new data. 2. the software can now poll the dmac_chsr.emptx bit until it indicates that the channel n fifo is empty, where n is the channel number. 3. the dmac_cher.enax bit can then be cleared by software once the channel n fifo is empty, where n is the channel number. when dmac_ctrlax.src_width is less than dmac_ctrlax.dst_width and the dmac_chsrx.suspx bit is high, the dmac_chs rx.emptx is asserted once the contents of the fifo does not permit a single word of dmac_ctrlax.dst_width to be formed. how- ever, there may still be data in the channel fifo but not enough to form a single transfer of dmac_ctlx.dst_width width. in th is configuration, once the channel is disabled, the remain- ing data in the channel fifo are not transferred to the destination peripheral. it is permitted to remove the channel from the suspension state by writing a 1 to the dmac_cher.resx field register. the dmac transfer completes in the normal manner. n defines the channel number. note: if a channel is disabled by software, an active single or chunk transaction is not guaranteed to receive an acknowledgement. 32.4.6.1 abnormal transfer termination a dmac transfer may be terminated abruptly by so ftware by clearing the channel enable bit, dmac_chdr.enax, where x is the channel number. this does not mean that the channel is disabled immediately after the dmac_chsr.enax bit is cleared over the apb interface. con- sider this as a request to disable the chann el. the dmac_chsr.enax must be polled and then it must be confirmed that the channel is disabled by reading back 0. the software may terminate all channels abruptly by clearing the global enable bit in the dmac configuration register (dmac_en.enable bit). again, this does not mean that all channels are disabled immediately after the dmac_en.enable is cleared over the apb slave interface. consider this as a request to disable all c hannels. the dmac_chsr.enable must be polled and then it must be confirmed that all channels are disabled by reading back 0. note: if the channel enable bit is cleared while there is data in the channel fifo, this data is not sent to the destination peripheral and is not present when the channel is re-enabled. for read sensitive source peripherals, such as a source fifo, this data is therefore lost. when the source is not a read sensitive device (i.e., memory), disabling a channel without waiting for the channel fifo to empty may be acceptable as the data is available from the source peripheral upon request and is not lost. note: if a channel is disabled by software, an active single or chunk transaction is not guaranteed to receive an acknowledgement. 32.5 dmac software requirements ? there must not be any write operation to channel registers in an active channel after the channel enable is made high. if any channel parameters must be reprogrammed, this can only be done after disabling the dmac channel. ? when the destination peripheral has been defined as the flow controller, source single transfer requests are not serviced until the destination peripheral has asserted its last transfer flag. ? when the source peripheral has been defined as the flow controller, destination single transfer requests are not serviced until the source peripheral has asserted its last transfer flag.
510 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 510 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? when the destination peripheral has been defined as the flow controller, if the destination width is smaller than the source width, then a data loss may occur, and the loss is equal to the source single transfer size in bytes- destination single transfer size in bytes. ? when a memory to peripheral transfer occurs, if the destination peripheral has been defined as the flow controller, then a prefetch operation is performed. it means that data is extracted from the memory before any request from the peripheral is generated. ? you must program the dmac_saddrx and dm ac_daddrx channel registers with a byte, half-word and word aligned address depending on the source width and destination width. ? after the software disables a channel by writing into the channel disable register, it must re- enable the channel only after it has polled a 0 in the corresponding channel enable status register. this is because the current ahb burst must terminate properly. ? if you program the btsize field in the dmac_ctrla as zero, and the dmac has been defined as the flow controller, then the channel is automatically disabled. ? when hardware handshaking interface protocol is fully implemented, a peripheral is expected to deassert any sreq or breq signals on receiv ing the ack signal irrespective of the request the ack was asserted in response to. ? multiple transfers involving the same peripheral must not be programmed and enabled on different channels, unless this peripheral integrates several hardware handshaking interfaces. ? when a peripheral has been defined as the flow controller, the targeted dmac channel must be enabled before the peripheral. if you do not ensure this and the first dmac request is also the last transfer, the dmac channel might miss a last transfer flag. ? when the auto field is set to true, then the btsize field is automatically reloaded from its previous value. btsize must be initialized to a non zero value if the first transfer is initiated with the auto field set to true, even if lli mode is enabled, because the lli fetch operation will not update this field.
511 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 511 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 32.6 write protection registers to prevent any single software error that may corrupt the dmac behavior, the dmac address space can be write-protected by setting the wpen bit in the dmac write protect mode regis- ter (dmac_wpmr). if a write access to anywhere in the dmac address space is detec ted, then the wpvs flag in the dmac write protect status register (mci_w psr) is set, and the wpvsrc field indicates in which register the write access has been attempted. the wpvs flag is reset by writ ing the dmac write protect m ode register (dmac_wpmr) with the appropriate access key, wpkey. the protected registers are: ? dmac global configuration register on page 513 ? dmac enable register on page 514 ? dmac channel x [x = 0..7] source address register on page 525 ? dmac channel x [x = 0..7] destination address register on page 526 ? dmac channel x [x = 0..7] descriptor address register on page 527 ? dmac channel x [x = 0..7] control a register on page 528 ? dmac channel x [x = 0..7] control b register on page 530 ? dmac channel x [x = 0..7] configuration register on page 532 ? dmac channel x [x = 0..7] source picture-in -picture configuration register on page 534 ? dmac channel x [x = 0..7] destination pictur e-in-picture configurat ion register on page 535
512 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 512 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 32.7 dma controller (dmac) user interface table 32-4. register mapping offset register name access reset 0x000 dmac global configuration register dmac_gcfg read-write 0x10 0x004 dmac enable register dmac_en read-write 0x0 0x008 dmac software single request register dmac_sreq read-write 0x0 0x00c dmac software chunk transfer request register dmac_creq read-write 0x0 0x010 dmac software last transfer flag register dmac_last read-write 0x0 0x014 reserved 0x018 dmac error, chained buffer transfer completed interrupt and buffer transfer completed interrupt enable register. dmac_ebcier write-only C 0x01c dmac error, chained buffer transfer completed interrupt and buffer transfer completed interrupt disable register. dmac_ebcidr write-only C 0x020 dmac error, chained buffer transfer completed interrupt and buffer transfer completed mask register. dmac_ebcimr read-only 0x0 0x024 dmac error, chained buffer transfer completed interrupt and buffer transfer completed status register. dmac_ebcisr read-only 0x0 0x028 dmac channel handler enable register dmac_cher write-only C 0x02c dmac channel handler disable register dmac_chdr write-only C 0x030 dmac channel handler status register dmac_chsr read-only 0x00ff0000 0x034 reserved C C C 0x038 reserved C C C 0x03c+ch_num*(0x28)+(0x0) dmac channel source address register dmac_saddr read-write 0x0 0x03c+ch_num*(0x28)+(0x4) dmac channel destinat ion address register dmac_daddr read-write 0x0 0x03c+ch_num*(0x28)+(0x8) dmac channel descriptor address register dmac_dscr read-write 0x0 0x03c+ch_num*(0x28)+(0xc) dmac channel control a register dmac_ctrla read-write 0x0 0x03c+ch_num*(0x28)+(0x10) dmac channel control b register dmac_ctrlb read-write 0x0 0x03c+ch_num*(0x28)+(0x14) dmac channel confi guration register dmac_cfg read-write 0x01000000 0x03c+ch_num*(0x28)+(0x18) dmac channel source picture-in-picture configuration register dmac_spip read-write 0x0 0x03c+ch_num*(0x28)+(0x1c) dmac channel destination picture-in-picture configuration register dmac_dpip read-write 0x0 0x03c+ch_num*(0x28)+(0x20) reserved C C C 0x03c+ch_num*(0x28)+(0x24) reserved C C C 0x1e4 dmac write protect mode r egister dmac_wpmr read-write 0x0 0x1e8 dmac write protect status register dmac_wpsr read-only 0x0 0x01ec- 0x1fc reserved C C C
513 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 513 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 32.7.1 dmac global configuration register name: dmac_gcfg address: 0xffffec00 access: read-write reset: 0x00000010 note: bit fields 0, 1, 2, 3, have a default value of 0. this should not be changed. this register can only be written if the wpen bit is cleared in dmac write protect mode register . ? arb_cfg: arbiter configuration 0 (fixed): fixed priority arbiter. 1 (round_robin): modified round robin arbiter. ? dicen: descriptor integrity check 0: descriptor integrity check interface is disabled. 1: descriptor integrity check interface is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCd i c e n 76543210 CCCa r b _ c f gCCCC
514 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 514 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 32.7.2 dmac enable register name: dmac_en address: 0xffffec04 access: read-write reset: 0x00000000 this register can only be written if the wpen bit is cleared in dmac write protect mode register . ? enable 0: dma controller is disabled. 1: dma controller is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCCe n a b l e
515 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 515 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 32.7.3 dmac software single request register name: dmac_sreq address: 0xffffec08 access: read-write reset: 0x00000000 ? dsreqx: destination request request a destination single transfer on channel i. ? ssreqx: source request request a source single transfer on channel i. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 dsreq7 ssreq7 dsreq6 ssreq6 dsreq5 ssreq5 dsreq4 ssreq4 76543210 dsreq3 ssreq3 dsreq2 ssreq2 dsreq1 ssreq1 dsreq0 ssreq0
516 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 516 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 32.7.4 dmac software chunk transfer request register name: dmac_creq address: 0xffffec0c access: read-write reset: 0x00000000 ? dcreqx: destination chunk request request a destination chunk transfer on channel i. ? screqx: source chunk request request a source chunk transfer on channel i. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 dcreq7 screq7 dcreq6 scre q6 dcreq5 screq5 dcreq4 screq4 76543210 dcreq3 screq3 dcreq2 scre q2 dcreq1 screq1 dcreq0 screq0
517 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 517 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 32.7.5 dmac software last transfer flag register name: dmac_last address: 0xffffec10 access: read-write reset: 0x00000000 ? dlastx: destination last writing one to dlastx prior to writing one to dsreqx or dcreqx indicates that this destination request is the last transfer of the buffer. ? slastx: source last writing one to slastx prior to writing one to ssreqx or screqx indicates that this source request is the last transfer of the buffer. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 dlast7 slast7 dlast6 slast6 d last5 slast5 dlast4 slast4 76543210 dlast3 slast3 dlast2 slast2 d last1 slast1 dlast0 slast0
518 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 518 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 32.7.6 dmac error, buffer transfer and chained buffer transfer interrupt enable register name: dmac_ebcier address: 0xffffec18 access: write-only reset: 0x00000000 ? btcx: buffer transfer completed [7:0] buffer transfer completed interrupt enable register. set the relevant bit in the btc field to enable the interrupt for channel i. ? cbtcx: chained buffer transfer completed [7:0] chained buffer transfer completed interrupt enable register. set the relevant bit in the cbtc field to enable the interrupt for channel i. ? errx: access error [7:0] access error interrupt enable register. set the relevant bi t in the err field to enable the interrupt for channel i. ? dicerrx: descriptor integrity check error [7:0] descriptor integrity check error interrupt enable register. se t the relevant bit in the dicerr field to enable the interrupt for channel i. 31 30 29 28 27 26 25 24 dicerr7 dicerr6 dicerr5 dicerr4 dicerr3 dicerr2 dicerr1 dicerr0 23 22 21 20 19 18 17 16 err7 err6 err5 err4 err3 err2 err1 err0 15 14 13 12 11 10 9 8 cbtc7 cbtc6 cbtc5 cbtc4 cbtc3 cbtc2 cbtc1 cbtc0 76543210 btc7 btc6 btc5 btc4 btc3 btc2 btc1 btc0
519 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 519 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 32.7.7 dmac error, buffer transfer and chained buffer transfer interrupt disable register name: dmac_ebcidr address: 0xffffec1c access: write-only reset: 0x00000000 ? btcx: buffer transfer completed [7:0] buffer transfer completed disable interrupt register. when set, a bit of the btc field disables the interrupt from the rele- vant dmac channel. ? cbtcx: chained buffer transfer completed [7:0] chained buffer transfer completed disable register. when set, a bit of the cbtc field disables the interrupt from the rele- vant dmac channel. ? errx: access error [7:0] access error interrupt disable register. when set, a bit of t he err field disables the interrupt from the relevant dmac channel. ? dicerrx: descriptor integrity check error [7:0] descriptor integrity check error interrupt disable register, when set, a bit of the dicerr field disables the interrupt from the relevant dmac channel. 31 30 29 28 27 26 25 24 dicerr7 dicerr6 dicerr5 dicerr4 dicerr3 dicerr2 dicerr1 dicerr0 23 22 21 20 19 18 17 16 err7 err6 err5 err4 err3 err2 err1 err0 15 14 13 12 11 10 9 8 cbtc7 cbtc6 cbtc5 cbtc4 cbtc3 cbtc2 cbtc1 cbtc0 76543210 btc7 btc6 btc5 btc4 btc3 btc2 btc1 btc0
520 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 520 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 32.7.8 dmac error, buffer transfer and chained buffer transfer interrupt mask register name: dmac_ebcimr address: 0xffffec20 access: read-only reset: 0x00000000 ? btcx: buffer transfer completed [7:0] 0: buffer transfer completed interrupt is disabled for channel i. 1: buffer transfer completed interrupt is enabled for channel i. ? cbtcx: chained buffer transfer completed [7:0] 0: chained buffer transfer interrupt is disabled for channel i. 1: chained buffer transfer interrupt is enabled for channel i. ? errx: access error [7:0] 0: transfer error interrupt is disabled for channel i. 1: transfer error interrupt is enabled for channel i. ? dicerrx: descriptor integrity check error [7:0] 0: descriptor integrity check error interrupt is disabled for channel i. 1: descriptor integrity check error interrupt is enabled for channel i. 31 30 29 28 27 26 25 24 dicerr7 dicerr6 dicerr5 dicerr4 dicerr3 dicerr2 dicerr1 dicerr0 23 22 21 20 19 18 17 16 err7 err6 err5 err4 err3 err2 err1 err0 15 14 13 12 11 10 9 8 cbtc7 cbtc6 cbtc5 cbtc4 cbtc3 cbtc2 cbtc1 cbtc0 76543210 btc7 btc6 btc5 btc4 btc3 btc2 btc1 btc0
521 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 521 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 32.7.9 dmac error, buffer transfer and chained buffer transfer status register name: dmac_ebcisr address: 0xffffec24 access: read-only reset: 0x00000000 ? btcx: buffer transfer completed [7:0] when btc[ i ] is set, channel i buffer transfer has terminated. ? cbtcx: chained buffer transfer completed [7:0] when cbtc[ i ] is set, channel i chained buffer has terminated. lli fetch operation is disabled. ? errx: access error [7:0] when err[ i ] is set, channel i has detected an ahb read or write error access. ? dicerrx: descriptor integrity check error [7:0] when dicerr[ i ] is set, channel i has detected a descriptor integrity check error. 31 30 29 28 27 26 25 24 dicerr7 dicerr6 dicerr5 dicerr4 dicerr3 dicerr2 dicerr1 dicerr0 23 22 21 20 19 18 17 16 err7 err6 err5 err4 err3 err2 err1 err0 15 14 13 12 11 10 9 8 cbtc7 cbtc6 cbtc5 cbtc4 cbtc3 cbtc2 cbtc1 cbtc0 76543210 btc7 btc6 btc5 btc4 btc3 btc2 btc1 btc0
522 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 522 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 32.7.10 dmac channel handler enable register name: dmac_cher address: 0xffffec28 access: write-only reset: 0x00000000 ? enax: enable [7:0] when set, a bit of the ena field enables the relevant channel. ? suspx: suspend [7:0] when set, a bit of the susp field freezes the relevant channel and its current context. ? keepx: keep on [7:0] when set, a bit of the keep fi eld resumes the current channel from an automatic stall state. 31 30 29 28 27 26 25 24 keep7 keep6 keep5 keep4 keep3 keep2 keep1 keep0 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 susp7 susp6 susp5 susp4 susp3 susp2 susp1 susp0 76543210 ena7 ena6 ena5 ena4 ena3 ena2 ena1 ena0
523 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 523 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 32.7.11 dmac channel handler disable register name: dmac_chdr address: 0xffffec2c access: write-only reset: 0x00000000 ? disx: disable [7:0] write one to this field to disable the relevant dmac channel. the content of the fifo is lost and the current ahb access is terminated. software must poll dis[7:0] field in the dmac_chsr register to be sure that the channel is disabled. ? resx: resume [7:0] write one to this field to resume the channel transfer restoring its context. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 res7 res6 res5 res4 res3 res2 res1 res0 76543210 dis7 dis6 dis5 dis4 dis3 dis2 dis1 dis0
524 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 524 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 32.7.12 dmac channel handler status register name: dmac_chsr address: 0xffffec30 access: read-only reset: 0x00ff0000 ? enax: enable [7:0] a one in any position of this field indicates that the relevant channel is enabled. ? suspx: suspend [7:0] a one in any position of this field indicates that the channel transfer is suspended. ? emptx: empty [7:0] a one in any position of this field indicates that the relevant channel is empty. ? stalx: stalled [7:0] a one in any position of this field indica tes that the relevant channel is stalling. 31 30 29 28 27 26 25 24 stal7 stal6 stal5 stal4 stal3 stal2 stal1 stal0 23 22 21 20 19 18 17 16 empt7 empt6 empt5 empt4 empt3 empt2 empt1 empt0 15 14 13 12 11 10 9 8 susp7 susp6 susp5 susp4 susp3 susp2 susp1 susp0 76543210 ena7 ena6 ena5 ena4 ena3 ena2 ena1 ena0
525 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 525 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 32.7.13 dmac channel x [x = 0..7] source address register name: dmac_saddrx [x = 0..7] address: 0xffffec3c [0], 0xffffec64 [1], 0xffffec8c [2], 0xffffecb4 [3], 0xffffecdc [4], 0xffffed04 [5], 0xffffed2c [6], 0xffffed54 [7] access: read-write reset: 0x00000000 this register can only be written if the wpen bit is cleared in dmac write protect mode register . ? saddr: channel x source address this register must be aligned with the source transfer width. 31 30 29 28 27 26 25 24 saddr 23 22 21 20 19 18 17 16 saddr 15 14 13 12 11 10 9 8 saddr 76543210 saddr
526 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 526 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 32.7.14 dmac channel x [x = 0..7] destination address register name: dmac_daddrx [x = 0..7] address: 0xffffec40 [0], 0xffffec68 [1], 0xffffec90 [2], 0x ffffecb8 [3], 0xffffece0 [4], 0xffffed08 [5], 0xffffed30 [6], 0xffffed58 [7] access: read-write reset: 0x00000000 this register can only be written if the wpen bit is cleared in dmac write protect mode register . ? daddr: channel x destination address this register must be aligned with the destination transfer width. 31 30 29 28 27 26 25 24 daddr 23 22 21 20 19 18 17 16 daddr 15 14 13 12 11 10 9 8 daddr 76543210 daddr
527 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 527 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 32.7.15 dmac channel x [x = 0..7] descriptor address register name: dmac_dscrx [x = 0..7] address: 0xffffec44 [0], 0xffffec6c [1], 0xffffec94 [2], 0xffffecbc [3], 0xffffece4 [4], 0xffffed0c [5], 0xffffed34 [6], 0xffffed5c [7] access: read-write reset: 0x00000000 this register can only be written if the wpen bit is cleared in dmac write protect mode register . ?dscr_if ? dscr: buffer transfer descriptor address this address is word aligned. 31 30 29 28 27 26 25 24 dscr 23 22 21 20 19 18 17 16 dscr 15 14 13 12 11 10 9 8 dscr 76543210 dscr dscr_if value name description 00 ahb_if0 the buffer transfer descriptor is fetched via ahb-lite interface 0 01 ahb_if1 the buffer transfer descriptor is fetched via ahb-lite interface 1
528 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 528 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 32.7.16 dmac channel x [x = 0..7] control a register name: dmac_ctrlax [x = 0..7] address: 0xffffec48 [0], 0xffffec70 [1], 0xffffec98 [2], 0x ffffecc0 [3], 0xffffece8 [4], 0xffffed10 [5], 0xffffed38 [6], 0xffffed60 [7] access: read-write reset: 0x00000000 this register can only be written if the wpen bit is cleared in dmac write protect mode register on page 536 ? btsize: buffer transfer size the transfer size relates to the number of transfers to be performed, that is, for writes it refers to the number of source width transfers to perform when dmac is flow controller. for reads, btsize refers to the number of transfers completed on the source interface. when this field is set to 0, the dmac module is automatically disabled when the relevant channel is enabled. ? scsize: source chunk transfer size. ? dcsize: destination chunk transfer size 31 30 29 28 27 26 25 24 done C dst_width C C src_width 23 22 21 20 19 18 17 16 C dcsize C scsize 15 14 13 12 11 10 9 8 btsize 76543210 btsize value name description 000 chk_1 1 data transferred 001 chk_4 4 data transferred 010 chk_8 8 data transferred 011 chk_16 16 data transferred 100 chk_32 32 data transferred 101 chk_64 64 data transferred 110 chk_128 128 data transferred 111 chk_256 256 data transferred value name description 000 chk_1 1 data transferred 001 chk_4 4 data transferred 010 chk_8 8 data transferred
529 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 529 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? src_width: transfer width for the source ? dst_width: transfer width for the destination ?done 0: the transfer is performed. 1: if sod field of dmac_cfg register is set to true, then the dmac is automatically disabled when an lli updates the con- tent of this register. the done field is written back to memory at the end of the transfer. 011 chk_16 16 data transferred 100 chk_32 32 data transferred 101 chk_64 64 data transferred 110 chk_128 128 data transferred 111 chk_256 256 data transferred value name description 00 byte the transfer size is set to 8-bit width 01 half_word the transfer size is set to 16-bit width 1x word the transfer size is set to 32-bit width value name description 00 byte the transfer size is set to 8-bit width 01 half_word the transfer size is set to 16-bit width 1x word the transfer size is set to 32-bit width value name description
530 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 530 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 32.7.17 dmac channel x [x = 0..7] control b register name: dmac_ctrlbx [x = 0..7] address: 0xffffec4c [0], 0xffffec74 [1], 0xffffec9c [2], 0xffffecc4 [3], 0xffffecec [4], 0xffffed14 [5], 0xffffed3c [6], 0xffffed64 [7] access: read-write reset: 0x00000000 this register can only be written if the wpen bit is cleared in dmac write protect mode register . ? sif: source interface selection field ? dif: destination interface selection field ? src_pip: source picture-in-picture mode 0 (disable): picture-in-picture mode is disabled. the sour ce data area is contiguous. 1 (enable): picture-in-picture mode is enabled. when the source pip counter reaches the programmable boundary, the address is automatically incremented by a user defined amount. ? dst_pip: destination picture-in-picture mode 0 (disable): picture-in-picture mode is disabled. the destinat ion data area is contiguous. 1 (enable): picture-in-picture mode is enabled. when the destination pip counter reaches the programmable boundary the address is automatically incremented by a user-defined amount. ? src_dscr: source address descriptor 0 (fetch_from_mem): source address is updated when the descriptor is fetched from the memory. 1 (fetch_disable): buffer de scriptor fetch operation is disabled for the source. 31 30 29 28 27 26 25 24 auto ien dst_incr C C src_incr 23 22 21 20 19 18 17 16 fc dst_dscr C C C src_dscr 15 14 13 12 11 10 9 8 CC d s t _ p i pCCCs r c _ p i p 76543210 CC d i f CC s i f value name description 00 ahb_if0 the source transfer is done via ahb-lite interface 0 01 ahb_if1 the source transfer is done via ahb-lite interface 1 value name description 00 ahb_if0 the destination transfer is done via ahb-lite interface 0 01 ahb_if1 the destination transfer is done via ahb-lite interface 1
531 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 531 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? dst_dscr: destination address descriptor 0 (fetch_from_mem): destination address is updated when the descriptor is fetched from the memory. 1 (fetch_disable): buffer descriptor fetch operation is disabled for the destination. ? fc: flow control this field defines which device controls the size of the buffer transfer, also referred to as the flow controller. ? src_incr: incrementing, decrementing or fixed address for the source ? dst_incr: incrementing, decrementing or fixed address for the destination ?ien if this bit is cleared, when the buffer transfer is completed, th e btcx flag is set in the ebcisr status register. this bit is active low. ? auto: automatic multiple buffer transfer 0 (disable): automatic multiple buffer transfer is disabled. 1 (enable): automatic multiple buffer transfer is enabled. th is bit enables replay mode or contiguous mode when several buffers are transferred. value name description 000 mem2mem_dma_fc memory-to-memory transfer dmac is flow controller 001 mem2per_dma_fc memory-to-peripheral transfer dmac is flow controller 010 per2mem_dma_fc peripheral-to-memory transfer dmac is flow controller 011 per2per_dma_fc peripheral-to-peripheral transfer dmac is flow controller value name description 00 incrementing the source address is incremented 01 decrementing the source address is decremented 10 fixed the source address remains unchanged value name description 00 incrementing the destinat ion address is incremented 01 decrementing the destinat ion address is decremented 10 fixed the destination address remains unchanged
532 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 532 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 32.7.18 dmac channel x [x = 0..7] configuration register name: dmac_cfgx [x = 0..7] address: 0xffffec50 [0], 0xffffec78 [1], 0xffffeca0 [2], 0xffffecc8 [3], 0xffffecf0 [4], 0xffffed18 [5], 0xffffed40 [6], 0xffffed68 [7] access: read-write reset: 0x0100000000 this register can only be written if the wpen bit is cleared in dmac write protect mode register on page 536 ? src_per: source with peripheral identifier channel x source request is associated with peripher al identifier coded src_per handshaking interface. ? dst_per: destination with peripheral identifier channel x destination request is associated with peripheral identifier coded dst_per handshaking interface. ? src_rep: source reloaded from previous 0 (contiguous_addr): when automatic mode is activated, source address is contiguous between two buffers. 1 (reload_addr): when automatic mode is activated, the source address and the control register are reloaded from previous transfer. ? src_h2sel: software or hard ware selection for the source 0 (sw): software handshaking interface is used to trigger a transfer request. 1 (hw): hardware handshaking interface is used to trigger a transfer request. ? src_per_msb: src_per most significant bits this field indicates the most significant bits of the src_per field. ? dst_rep: destination reloaded from previous 0 (contiguous_addr): when automatic mode is activated, destination address is contiguous between two buffers. 1 (reload_addr): when automatic mode is activated, the destination and the control register are reloaded from the pre- vious transfer. ? dst_h2sel: software or hardware selection for the destination 0 (sw): software handshaking interface is used to trigger a transfer request. 1 (hw): hardware handshaking interface is used to trigger a transfer request. 31 30 29 28 27 26 25 24 C C fifocfg C ahb_prot 23 22 21 20 19 18 17 16 C lock_if_l lock_b lock_if C C C sod 15 14 13 12 11 10 9 8 dst_per_msb dst_h2sel dst_rep src_per_msb src_h2sel src_rep 76543210 dst_per src_per
533 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 533 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? dst_per_msb: dst_per most significant bits this field indicates the most significant bits of the dst_per field. ? sod: stop on done 0 (disable): stop on done disabled, the descriptor fe tch operation ignores done field of ctrla register. 1 (enable): stop on done activated, the dmac module is automatically disabled if done field is set to 1. ? lock_if: interface lock 0 (disable): interface lo ck capability is disabled 1 (enable): interface lock capability is enabled ? lock_b: bus lock 0 (disable): ahb bus lockin g capability is disabled. 1(enable): ahb bus locking capability is enabled. ? lock_if_l: master interface arbiter lock 0 (chunk): the master in terface arbiter is locked by the channel x for a chunk transfer. 1 (buffer): the master interface arbiter is lo cked by the channel x for a buffer transfer. ? ahb_prot: ahb protection ahb_prot field provides additional information about a bus access and is primarily used to implement some level of protection. ? fifocfg: fifo configuration hprot[3] hprot[2] hprot[1] hprot[0] description 1 data access ahb_prot[0] 0: user access 1: privileged access ahb_prot[1] 0: not bufferable 1: bufferable ahb_prot[2] 0: not cacheable 1: cacheable value name description 00 alap_cfg the largest defined length ahb burst is performed on the destination ahb interface. 01 half_cfg when half fifo size is available/fill ed, a source/destination request is serviced. 10 asap_cfg when there is enough space/data available to perform a single ahb access, then the request is serviced.
534 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 534 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 32.7.19 dmac channel x [x = 0..7] source picture-in-picture configuration register name: dmac_spipx [x = 0..7] address: 0xffffec54 [0], 0xffffec7c [1], 0xfff feca4 [2], 0xffffeccc [3], 0xffffecf4 [4], 0xffffed1c [5], 0xffffed44 [6], 0xffffed6c [7] access: read-write reset: 0x00000000 this register can only be written if the wpen bit is cleared in dmac write protect mode register on page 536 ? spip_hole: source picture-in-picture hole this field indicates the value to add to the address when the programmable boundary has been reached. ? spip_boundary: source picture-in-picture boundary this field indicates the number of source transfers to perform before the automatic address increment operation. 31 30 29 28 27 26 25 24 CCCCCCs p i p _ b o u n d a r y 23 22 21 20 19 18 17 16 spip_boundary 15 14 13 12 11 10 9 8 spip_hole 76543210 spip_hole
535 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 535 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 32.7.20 dmac channel x [x = 0..7] destination picture-in-picture configuration register name: dmac_dpipx [x = 0..7] address: 0xffffec58 [0], 0xffffec80 [1], 0xffffeca8 [2], 0xffffecd0 [3], 0xffffecf8 [4], 0xffffed20 [5], 0xffffed48 [6], 0xffffed70 [7] access: read-write reset: 0x00000000 this register can only be written if the wpen bit is cleared in dmac write protect mode register on page 536 ? dpip_hole: destination picture-in-picture hole this field indicates the value to add to the address when the programmable boundary has been reached. ? dpip_boundary: destination picture-in-picture boundary this field indicates the number of source transfers to perform before the automatic address increment operation. 31 30 29 28 27 26 25 24 CCCCCCd p i p _ b o u n d a r y 23 22 21 20 19 18 17 16 dpip_boundary 15 14 13 12 11 10 9 8 dpip_hole 76543210 dpip_hole
536 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 536 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 32.7.21 dmac write protect mode register name: dmac_wpmr address: 0xffffede4 access: read-write reset: see table 32-4 ? wpen: write protect enable 0 = disables the write protec t if wpkey correspo nds to 0x444d4143 (dmac in ascii). 1 = enables the write protect if wpkey corresponds to 0x444d4143 (dmac in ascii). protects the registers: ? dmac global configuration register on page 513 ? dmac enable register on page 514 ? dmac channel x [x = 0..7] source address register on page 525 ? dmac channel x [x = 0..7] destination address register on page 526 ? dmac channel x [x = 0..7] descriptor address register on page 527 ? dmac channel x [x = 0..7] control a register on page 528 ? dmac channel x [x = 0..7] control b register on page 530 ? dmac channel x [x = 0..7] configuration register on page 532 ? dmac channel x [x = 0..7] source picture-in-picture configuration register on page 534 ? dmac channel x [x = 0..7] destination picture-in-picture configuration register on page 535 ? wpkey: write protect key should be written at value 0x50494f (dmac in ascii). writing any other value in this field aborts the write operation of the wpen bit. always reads as 0. 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 w p e n
537 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 537 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 32.7.22 dmac write protect status register name: dmac_wpsr address: 0xffffede8 access: read-only reset: see table 32-4 ? wpvs: write protect violation status 0 = no write protect violation has occurred since the last read of the dmac_wpsr register. 1 = a write protect violation has occurred since the last read of the dmac_wpsr register. if this violation is an unauthor- ized attempt to write a protected register, the associated violation is reported into field wpvsrc. ? wpvsrc: write protect violation source when wpvs is active, this field indicates the write-protected register (t hrough address offset or code) in which a write access has been attempted. note: reading dmac_wpsr automatically clears all fields. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 wpvsrc 15 14 13 12 11 10 9 8 wpvsrc 76543210 w p v s
538 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 538 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12
539 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 539 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 33. usb device port (udp) 33.1 description the usb device port (udp) is compliant with the universal serial bus (usb) v2.0 full-speed device specification. each endpoint can be configured in one of several usb transfer types. it can be associated with one or two banks of a dual-port ram used to store the current data payload. if two banks are used, one dpr bank is read or written by the proc essor, while the other is read or written by the usb device peripheral. this feature is mandator y for isochronous endpoints. thus the device maintains the maximum bandwidth (1m bytes/s) by working with endpoints with two banks of dpr. note: 1. the dual-bank function provides two banks for an endpoint. this feature is used for ping-pong mode. suspend and resume are automatically detected by the usb device, which notifies the proces- sor by raising an interrupt. depending on the product, an external signal can be used to send a wake up to the usb host controller. 33.2 embedded characteristics ? usb v2.0 full-speed complia nt, 12 mbits per second ? embedded usb v2.0 full-speed transceiver ? 6 endpoints ? embedded dual-port ram for endpoints ? suspend/resume logic ? ping-pong mode (2 memory banks) for isochronous and bulk endpoints ? compatible with embedded arm7tdmi and arm9tdmi processor ? can be directly connected to the atmel implementation of the amba peripheral bus (apb) table 33-1. usb endpoint description endpoint number mn emonic dual-bank (1) max. endpoint size endpoint type 0 ep0 no 64 control/bulk/interrupt 1 ep1 yes 64 bulk/iso/interrupt 2 ep2 yes 64 bulk/iso/interrupt 3 ep3 no 64 control/bulk/interrupt 4 ep4 yes 512 bulk/iso/interrupt 5 ep5 yes 512 bulk/iso/interrupt
540 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 540 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 33.3 block diagram figure 33-1. block diagram access to the udp is via the apb bus interface. read and write to the data fi fo are done by reading and writing 8-bit values to apb registers. the udp peripheral requires two clocks: one peripheral clock used by the master clock domain (mck) and a 48 mhz clock (udpck) used by the 12 mhz domain. a usb 2.0 full-speed pad is embedded and controlled by the serial interface engine (sie). 33.3.1 signal description 33.4 product dependencies for further details on the usb device hardware implementation, see the specific product prop- erties document. the usb physical transceiver is integrated into the product. the bidirectional differential signals ddp and ddm are available from the product boundary. atmel bridge 12 mhz suspend/resume logic w r a p p e r w r a p p e r u s e r i n t e r f a c e serial interface engine sie mck master clock domain dual port ram fifo udpck recovered 12 mhz domain udp_int usb device embedded usb transceiver ddp ddm apb to mcu bus txoen eopn txd rxdm rxd rxdp table 33-2. signal names signal name description type udpck 48 mhz clock input mck master clock input udp_int interrupt line connected to the interrupt controller input ddp usb d+ line i/o ddm usb d- line i/o
541 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 541 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 33.4.1 i/o lines ddp and ddm are not controlled by any pio controllers. the embedded usb physical trans- ceiver is controlled by the usb device peripheral. to reserve an i/o line to check vbus, the program mer must first program the pio controller to assign this i/o in input pio mode. 33.4.2 power management the usb device peripheral requires a 48 mhz cl ock. this clock must be generated by a pll with an accuracy of 0.25%. thus, the usb device receives two clocks from the power management controller (pmc): the master clock, mck, used to drive the peripheral user interface, and the udpck, used to inter- face with the bus usb signals (recovered 12 mhz domain). warning: the udp peripheral clock in the power management controller (pmc) must be enabled before any read/write operations to the udp registers including the udp_txvc register. 33.4.3 interrupt the usb device interface has an interrupt line connected to the interrupt controller. handling the usb device interrupt requires programming the interrupt controller before config- uring the udp. 33.5 typical connection figure 33-2. board schematic to interface device peripheral 33.5.1 usb device transceiver the usb device transceiver is embedded in the product. a few discrete components are required as follows: ? the application detects all device states as def ined in chapter 9 of the usb specification; Cvbus monitoring table 33-3. peripheral ids instance id udp 23 r ext r ext ddm ddp pio 27 k 47 k type b connector 1 2 34 5v bus monitoring
542 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 542 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? to reduce power consumption the host is disconnected ? for line termination. 33.5.2 vbus monitoring vbus monitoring is required to detect host connection. vbus monitoring is done using a stan- dard pio with internal pullup disabled. when the host is switched off, it should be considered as a disconnect, the pullup must be disabled in order to prevent powering the host through the pull- up resistor. when the host is disconnected and the transceiver is enabled, then ddp and ddm are floating. this may lead to over consumption. a solution is to enable the integrated pulldown by disabling the transceiver (txvdis = 1) and then remove the pullup (puon = 0). a termination serial resistor must be connected to ddp and ddm. the resistor value is defined in the electrical specification of the product (r ext ). 33.6 functional description 33.6.1 usb v2.0 full-speed introduction the usb v2.0 full-speed provides communication services between host and attached usb devices. each device is offered with a collection of communication flows (pipes) associated with each endpoint. software on the host communicates with a usb device through a set of commu- nication flows. figure 33-3. example of usb v2.0 full-speed communication control the control transfer endpoint ep0 is always used when a us b device is first configured (usb v. 2.0 specifications). ep0 usb host v2.0 software client 1 software client 2 data flow: bulk out transfer data flow: bulk in transfer data flow: control transfer data flow: control transfer ep1 ep2 usb device 2.0 block 1 usb device 2.0 block 2 ep5 ep4 ep0 data flow: isochronous in transfer data flow: isochronous out transfer usb device endpoint configuration requires that in the first instance control transfer must be ep0.
543 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 543 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 33.6.1.1 usb v2.0 full-speed transfer types a communication flow is carried over one of four transfer types defined by the usb device. 33.6.1.2 usb bus transactions each transfer results in one or more transactions over the usb bus. there are three kinds of transactions flowing acro ss the bus in packets: 1. setup transaction 2. data in transaction 3. data out transaction 33.6.1.3 usb transfer event definitions as indicated below, transfers are sequential events carried out on the usb bus. notes: 1. control transfer must use endpoints with no ping-pong attributes. 2. isochronous transfers must use endpoints with ping-pong attributes. 3. control transfers can be aborted using a stall handshake. table 33-4. usb communication flow transfer direction bandwidth supported endpoint size error detection retrying control bidirectional not guaranteed 8, 16, 32, 64 yes automatic isochronous unidirectional guaranteed 512 yes no interrupt unidirectional not guaranteed 64 yes yes bulk unidirectional not guaranteed 8, 16, 32, 64 yes yes table 33-5. usb transfer events control transfers (1) (3) ? setup transaction > data in transactions > status out transaction ? setup transaction > data out transactions > status in transaction ? setup transaction > status in transaction interrupt in transfer (device toward host) ? data in transaction > data in transaction interrupt out transfer (host toward device) ? data out transaction > data out transaction isochronous in transfer (2) (device toward host) ? data in transaction > data in transaction isochronous out transfer (2) (host toward device) ? data out transaction > data out transaction bulk in transfer (device toward host) ? data in transaction > data in transaction bulk out transfer (host toward device) ? data out transaction > data out transaction
544 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 544 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 a status transaction is a special type of host-to- device transaction used only in a control transfer. the control transfer must be performed using endpoints with no ping-pong attributes. according to the control sequence (read or write), the usb device sends or receives a status transaction. figure 33-4. control read and write sequences notes: 1. during the status in stage, the host waits for a zero length packet (data in transaction with no data) from the device using data1 pid. refer to chapter 8 of the universal serial bus specification, rev. 2.0, for more information on the protocol layer. 2. during the status out stage, the host emits a zero length packet to the device (data out transaction with no data). 33.6.2 handling transactions with usb v2.0 device peripheral 33.6.2.1 setup transaction setup is a special type of host-to-device transaction used during control transfers. control trans- fers must be performed using endpoints with no ping-pong attributes. a setup transaction needs to be handled as soon as possible by the firmware. it is used to transmit requests from the host to the device. these requests are then handled by the usb device and may require more argu- ments. the arguments are sent to the device by a data out transaction which follows the setup transaction. these requests may also return data. the data is carried out to the host by the next data in transaction which follows the setup transaction. a status transaction ends the control transfer. when a setup transfer is received by the usb endpoint: ? the usb device automatically acknowledges the setup packet ? rxsetup is set in the udp_csrx register ? an endpoint interrupt is generated while the rxsetup is not cleared. this interrupt is carried out to the microcontroller if interrupts are enabled for this endpoint. thus, firmware must det ect the rxsetup polling the udp_csrx or catching an interrupt, read the setup packet in the fifo, then clear the rxsetup. rxsetup cannot be clear ed before the control read setup tx data out tx data out tx data stage control write setup stage setup stage setup tx setup tx no data control data in tx data in tx status stage status stage status in tx status out tx status in tx data stage setup stage status stage
545 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 545 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 setup packet has been read in the fifo. otherwise, the usb device would accept the next data out transfer and overwrite the setup packet in the fifo. figure 33-5. setup transaction followed by a data out transaction 33.6.2.2 data in transaction data in transactions are used in control, is ochronous, bulk and interrupt transfers and conduct the transfer of data from the device to the host. data in transactions in isochronous transfer must be done using endpoints with ping-pong attributes. using endpoints without ping-pong attributes to perform a data in transaction using a non ping-pong endpoint: 1. the application checks if it is possible to write in the fifo by polling txpktrdy in the endpoints udp_csrx regist er (txpktrdy must be cleared). 2. the application writes the first packet of data to be sent in the endpoints fifo, writing zero or more byte values in the endpoints udp_fdrx register, 3. the application notifies the usb peripheral it has finished by setting the txpktrdy in the endpoints udp_csrx register. 4. the application is notified that the endpoints fifo has been released by the usb device when txcomp in the endpoints udp_csrx register has been set. then an interrupt for the corresponding endpoint is pending while txcomp is set. 5. the microcontroller writes the second packet of data to be sent in the endpoints fifo, writing zero or more byte values in the endpoints udp_fdrx register, 6. the microcontroller notifi es the usb peripheral it has finished by setting the txpk- trdy in the endpoints udp_csrx register. 7. the application clears the txcomp in the endpoints udp_csrx. after the last packet has been sent, the application must clear txcomp once this has been set. txcomp is set by the usb device when it has received an ack pid signal for the data in packet. an interrupt is pending while txcomp is set. warning: tx_comp must be cleared after tx_pktrdy has been set. rx_data_bko (udp_csrx) ack pid data out data out pid nak pid ack pid data setup setup pid usb bus packets rxsetup flag set by usb device cleared by firmware set by usb device peripheral fifo (dpr) content data setup data xx xx out interrupt pending setup received setup handled by firmware data out received data out data out pid
546 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 546 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 note: refer to chapter 8 of the universal serial bus specification, rev 2.0, for more information on the data in protocol layer. figure 33-6. data in transfer for non ping-pong endpoint using endpoints with ping-pong attribute the use of an endpoint with ping-pong attributes is necessary during isochronous transfer. this also allows handling the maximum bandwidth defined in the usb specification during bulk trans- fer. to be able to guarantee a constant or the maximum bandwidth, the microcontroller must prepare the next data payload to be sent while the current one is being sent by the usb device. thus two banks of memory are used. while one is available for the microcontroller, the other one is locked by the usb device. figure 33-7. bank swapping data in transfer for ping-pong endpoints usb bus packets data in 2 data in nak ack data in 1 fifo (dpr) content data in 2 load in progress data in 1 cleared by firmware dpr access by the firmware payload in fifo txcomp flag (udp_csrx) txpktrdy flag (udp_csrx) pid data in data in pid pid pid pid ack pid prevous data in tx microcontroller load data in fifo data is sent on usb bus interrupt pending interrupt pending set by the firmware set by the firmware cleared by firmware cleared by hw cleared by hw dpr access by the hardware usb device usb bus read write read and write at the same time 1 st data payload 2 nd data payload 3 rd data payload 3 rd data payload 2 nd data payload 1 st data payload data in packet data in packet data in packet microcontroller endpoint 1 bank 0 endpoint 1 bank 1 endpoint 1 bank 0 endpoint 1 bank 0 endpoint 1 bank 0 endpoint 1 bank 1
547 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 547 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 when using a ping-pong endpoint, the following procedures are required to perform data in transactions: 1. the microcontroller checks if it is possible to write in the fifo by polling txpktrdy to be cleared in the endpoints udp_csrx register. 2. the microcontroller writes the first data payload to be sent in the fifo (bank 0), writing zero or more byte values in the endpoints udp_fdrx register. 3. the microcontroller notifies the usb peripheral it has finished writing in bank 0 of the fifo by setting the txpktrdy in the endpoints udp_csrx register. 4. without waiting for txpktrdy to be cleare d, the microcontrolle r writes the second data payload to be sent in the fifo (bank 1), writing zero or more byte values in the endpoints udp_fdrx register. 5. the microcontroller is notified that the first bank has been released by the usb device when txcomp in the endpoints udp_csrx register is set. an interrupt is pending while txcomp is being set. 6. once the microcontroller has received txco mp for the first bank, it notifies the usb device that it has prepared the second bank to be sent, raising txpktrdy in the end- points udp_csrx register. 7. at this step, bank 0 is available and the microcontroller can prepare a third data pay- load to be sent . figure 33-8. data in transfer for ping-pong endpoint warning: there is software critical path due to the fact that once the second bank is filled, the driver has to wait for tx_comp to set tx_pktrdy. if the delay between receiving tx_comp is set and tx_pktrdy is set too long, some data in packets may be nacked, reducing the bandwidth. warning: tx_comp must be cleared after tx_pktrdy has been set. data in data in read by usb device read by usb device bank 1 bank 0 fifo (dpr) txcomp flag (udp_csrx) interrupt cleared by firmware set by usb device txpktrdy flag (udp_mcsrx) ack pid data in pid ack pid set by firmware, data payload written in fifo bank 1 cleared by usb device, data payload fully transmitted data in pid usb bus packets set by usb device set by firmware, data payload written in fifo bank 0 written by fifo (dpr) microcontroller written by microcontroller written by microcontroller microcontroller load data in bank 0 microcontroller load data in bank 1 usb device send bank 0 microcontroller load data in bank 0 usb device send bank 1 interrupt pending
548 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 548 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 33.6.2.3 data out transaction data out transactions are used in control, isochronous, bulk and interru pt transfers and con- duct the transfer of data from the host to the device. data out transactions in isochronous transfers must be done using endpoints with ping-pong attributes. data out transaction without ping-pong attributes to perform a data out transaction, using a non ping-pong endpoint: 1. the host generates a data out packet. 2. this packet is received by the usb device endpoint. while the fifo associated to this endpoint is being used by the microcontroller, a nak pid is returned to the host. once the fifo is available, data are written to the fifo by the usb device and an ack is automatically carried out to the host. 3. the microcontroller is notifie d that the usb device has re ceived a data payload polling rx_data_bk0 in the endpoints udp_csrx register. an interrupt is pending for this endpoint while rx_data_bk0 is set. 4. the number of bytes available in the fifo is made available by reading rxbytecnt in the endpoints udp_csrx register. 5. the microcontroller carries out data received from the endpoints memory to its mem- ory. data received is available by reading the endpoints udp_fdrx register. 6. the microcontroller notifies the usb device that it has finished the transfer by clearing rx_data_bk0 in the endpoints udp_csrx register. 7. a new data out packet can be accepted by the usb device. figure 33-9. data out transfer for non ping-pong endpoints an interrupt is pending while the flag rx_dat a_bk0 is set. memory transfer between the usb device, the fifo and microcontroller memory can not be done after rx_data_bk0 has been cleared. otherwise, the usb device would acce pt the next data out transfer and overwrite the current data out packet in the fifo. using endpoints with ping-pong attributes during isochronous transfer, using an endpoint wit h ping-pong attributes is obligatory. to be able to guarantee a constant bandwidth, the micr ocontroller must read the previous data pay- ack pid data out nak pid pid pid pid pid data out2 ack data out data out 1 usb bus packets rx_data_bk0 set by usb device cleared by firmware, data payload written in fifo fifo (dpr) content written by usb device microcontroller read data out 1 data out 1 data out 2 host resends the next data payload microcontroller transfers data host sends data payload data out2 data out2 host sends the next data payload written by usb device (udp_csrx) interrupt pending
549 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 549 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 load sent by the host, while the current data payload is received by the usb device. thus two banks of memory are used. while one is available for the microcontroller, the other one is locked by the usb device. figure 33-10. bank swapping in data out transfers for ping-pong endpoints when using a ping-pong endpoint, the following procedures are required to perform data out transactions: 1. the host generates a data out packet. 2. this packet is received by the usb device endpoint. it is written in the endpoints fifo bank 0. 3. the usb device sends an ack pid packet to the host. the host can immediately send a second data out packet. it is accepted by the device and copied to fifo bank 1. 4. the microcontroller is notifi ed that the usb device has re ceived a data payload, polling rx_data_bk0 in the endpoints udp_csrx register. an interrupt is pending for this endpoint while rx_data_bk0 is set. 5. the number of bytes available in the fifo is made available by reading rxbytecnt in the endpoints udp_csrx register. 6. the microcontroller transfers out data received from the endpoints memory to the microcontrollers memory. data received is made available by reading the endpoints udp_fdrx register. 7. the microcontroller notifies the usb peripheral device that it has finished the transfer by clearing rx_data_bk0 in the endpoints udp_csrx register. 8. a third data out packet can be accepted by the usb peripheral device and copied in the fifo bank 0. 9. if a second data out packet has been received, the microcontroller is notified by the flag rx_data_bk1 set in the endpoints udp_csrx register. an interrupt is pending for this endpoint while rx_data_bk1 is set. 10. the microcontroller transfers out data received from the endpoints memory to the microcontrollers memory. data received is available by reading the endpoints udp_fdrx register. usb device usb bus read write write and read at the same time 1 st data payload 2 nd data payload 3 rd data payload 3 rd data payload 2 nd data payload 1 st data payload data in packet data in packet data in packet microcontroller endpoint 1 bank 0 endpoint 1 bank 1 endpoint 1 bank 0 endpoint 1 bank 0 endpoint 1 bank 0 endpoint 1 bank 1
550 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 550 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 11. the microcontroller notifies the usb device it has finished the transfer by clearing rx_data_bk1 in the endpoints udp_csrx register. 12. a fourth data out packet can be accepted by the usb device and copied in the fifo bank 0. figure 33-11. data out transfer for ping-pong endpoint note: an interrupt is pending while the rx_data_bk0 or rx_data_bk1 flag is set. warning : when rx_data_bk0 and rx_data_bk1 are both set, there is no way to determine which one to clear first. thus the software must keep an internal counter to be sure to clear alter- natively rx_data_bk0 then rx_data_bk1. this situation may occur when the software application is busy elsewhere and the two banks are filled by the usb host. once the application comes back to the usb driver, the two flags are set. 33.6.2.4 stall handshake a stall handshake can be used in one of two distinct occasions. (for more information on the stall handshake, refer to chapter 8 of the universal serial bus specification, rev 2.0. ) ? a functional stall is used when the halt feature associated with the endpoint is set. (refer to chapter 9 of the universal serial bus sp ecification, rev 2.0, for more information on the halt feature.) ? to abort the current request, a protocol stall is used, but uniquely with control transfer. the following procedure generates a stall packet: 1. the microcontroller sets the forcestall flag in the udp_csrx endpoints register. 2. the host receives the stall packet. a p data out pid ack data out 3 data out data out 2 data out data out 1 pid data out 3 data out 1 data out1 data out 2 data out 2 pid pid pid ack cleared by firmware usb bus packets rx_data_bk0 flag rx_data_bk1 flag set by usb device, data payload written in fifo endpoint bank 1 fifo (dpr) bank 0 bank 1 write by usb device write in progress read by microcontroller read by microcontroller set by usb device, data payload written in fifo endpoint bank 0 host sends first data payload microcontroller reads data 1 in bank 0, host sends second data payload microcontroller reads data2 in bank 1, host sends third data payload cleared by firmware write by usb device fifo (dpr) (udp_csrx) (udp_csrx) interrupt pending interrupt pending
551 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 551 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 3. the microcontroller is notif ied that the device has sent the stall by polling the stallsent to be set. an endpoint interrup t is pending while stallsent is set. the microcontroller must clear stallsent to clear the interrupt. when a setup transaction is received after a stall handshake, stallsent must be cleared in order to prevent interrupts due to stallsent being set. figure 33-12. stall handshake (data in transfer) figure 33-13. stall handshake (data out transfer) data in stall pid pid usb bus packets cleared by firmware set by firmware forcestall stallsent set by usb device cleared by firmware interrupt pending data out pid stall pid data out usb bus packets cleared by firmware set by firmware forcestall stallsent set by usb device interrupt pending
552 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 552 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 33.6.2.5 transmit data cancellation some endpoints have dual-banks whereas some endpoints have only one bank. the procedure to cancel transmission data held in these banks is described below. to see the organization of du al-bank availability refer to table 33-1 usb endpoint description . endpoints without dual-banks there are two poss ibilities: in one case, txpktrdy fiel d in udp_csr has already been set. in the other instance, txpktrdy is not set. ? txpktrdy is not set: C reset the endpoint to clear the fifo (pointers). (see section 33.7.9 udp reset endpoint register .) ? txpktrdy has already been set: C clear txpktrdy so that no packet is ready to be sent C reset the endpoint to clear the fifo (pointers). (see section 33.7.9 udp reset endpoint register .) endpoints with dual-banks there are two poss ibilities: in one case, txpktrdy fiel d in udp_csr has already been set. in the other instance, txpktrdy is not set. ? txpktrdy is not set: C reset the endpoint to clear the fifo (pointers). (see section 33.7.9 udp reset endpoint register .) ? txpktrdy has already been set: C clear txpktrdy and read it back until actually read at 0. C set txpktrdy and read it ba ck until actually read at 1. C clear txpktrdy so that no packet is ready to be sent. C reset the endpoint to clear the fifo (pointers). (see section 33.7.9 udp reset endpoint register .)
553 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 553 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 33.6.3 controlling device states a usb device has several possible states. refer to chapter 9 of the universal serial bus speci- fication, rev 2.0 . figure 33-14. usb device state diagram movement from one state to another depends on the usb bus state or on standard requests sent through control transactions via the default endpoint (endpoint 0). after a period of bus inactivity, the us b device enters suspend mode. accepting sus- pend/resume requests from the usb host is mandatory. constraints in suspend mode are very strict for bus-powered applications; devices may not consume more than 500 a on the usb bus. while in suspend mode, the host may wake up a de vice by sending a resume signal (bus activ- ity) or a usb device may send a wake up request to the host, e.g., waking up a pc by moving a usb mouse. the wake up feature is not mandatory for all devices and must be negotiated with the host. attached suspended suspended suspended suspended hub reset or deconfigured hub configured bus inactive bus activity bus inactive bus activity bus inactive bus activity bus inactive bus activity reset reset address assigned device deconfigured device configured powered default address configured power interruption
554 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 554 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 33.6.3.1 not powered state self powered devices can detect 5v vbus using a pio as described in the typical connection section. when the device is not connected to a host, device power consumption can be reduced by disabling mck for the ud p, disabling udpck and disabl ing the transceiver. ddp and ddm lines are pulled down by 330 k resistors. 33.6.3.2 entering attached state to enable integrated pullup, the puon bit in the udp_txvc register must be set. warning : to write to the udp_txvc register, mck clock must be enabled on the udp. this is done in the power management controller. after pullup connection, the device enters the powered state. in this state, the udpck and mck must be enabled in the power management controller. the transceiver can remain disabled. 33.6.3.3 from powered state to default state after its connection to a usb host, the usb device waits for an end-of-bus reset. the unmask- able flag endbusres is set in the register udp_isr and an interrupt is triggered. once the endbusres interrupt has been triggered, the device enters default state. in this state, the udp software must: ? enable the default endpoint, setting the epeds flag in the udp_csr[0] register and, optionally, enabling the interrupt for endpoint 0 by writing 1 to the udp_ier register. the enumeration then begins by a control transfer. ? configure the interrupt mask register which has been reset by the usb reset detection ? enable the transceiver clearing the txvdis flag in the udp_txvc register. in this state udpck and mck must be enabled. warning : each time an endbusres interrupt is triggered, the interrupt mask register and udp_csr registers have been reset. 33.6.3.4 from default state to address state after a set address standard device request, the usb host peripheral enters the address state. warning : before the device enters in address state, it must achieve the status in transaction of the control transfer, i.e., the udp device sets its new address once the txcomp flag in the udp_csr[0] register has been received and cleared. to move to address state, the driver software sets the fadden flag in the udp_glb_stat register, sets its new address, and sets the fen bit in the udp_faddr register. 33.6.3.5 from address state to configured state once a valid set configuration standard request has been received and acknowledged, the device enables endpoints corresponding to the current configuration. this is done by setting the epeds and eptype fields in the udp_csrx regist ers and, optionally, en abling corr esponding interrupts in the udp_ier register. 33.6.3.6 entering in suspend state when a suspend (no bus activity on the usb bus) is detected, the rxsusp signal in the udp_isr register is set. this triggers an interrupt if the co rresponding bit is set in the udp_imr
555 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 555 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 register.this flag is cleared by writing to the udp_icr register. then the device enters suspend mode. in this state bus powered devices must drain less than 500ua from the 5v vbus. as an exam- ple, the microcontroller switches to slow clock, disables the pl l and main osc illator, and goes into idle mode. it may also switch off other devices on the board. the usb device peripheral clocks can be s witched off. resume event is asynchronously detected. mck and udpck can be switched off in the power management controller and the usb transceiver can be disabled by setting the txvdis field in the udp_txvc register. warning : read, write operations to the udp registers are allowed only if mck is enabled for the udp peripheral. switching off mck for the udp peripheral must be one of the last operations after writing to the udp_txvc and acknowledging the rxsusp. 33.6.3.7 receiving a host resume in suspend mode, a resume event on the usb bus line is detected asynchronously, transceiver and clocks are disabled (however the pullup shall not be removed). once the resume is detected on the bus, the wakeup signal in the udp_isr is set. it may gen- erate an interrupt if the corresponding bit in the udp_imr register is set. this interrupt may be used to wake up the core, enable pll and main oscillators and configure clocks. warning : read, write operations to the udp registers are allowed only if mck is enabled for the udp peripheral. mck for the udp must be enabled before clea ring the wakeup bit in the udp_icr register and clearing txvdis in the udp_txvc register. 33.6.3.8 sending a device remote wakeup in suspend state it is possible to wake up the host sending an external resume. ? the device must wait at least 5 ms after being entered in suspend before sending an external resume. ? the device has 10 ms from the moment it starts to drain current and it forces a k state to resume the host. ? the device must force a k state from 1 to 15 ms to resume the host to force a k state to the bus (ddm at 3.3v and ddp tied to gnd), it is possible to use a transis- tor to connect a pullup on ddm. the k state is obtained by disabling the pullup on ddp and enabling the pullup on ddm. this should be under the control of the application. figure 33-15. board schematic to drive a k state 3v3 pio 1.5 k 0: force wake up (k state) 1: normal mode dm
556 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 556 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 33.7 usb device port (udp) user interface warning: the udp peripheral clock in the power management controller (pmc) must be enabled before any read/write operations to the udp registers, including the udp_txvc register. notes: 1. reset values are not defined for udp_isr. 2. see warning above the register mapping on this page. table 33-6. register mapping offset register name access reset 0x000 frame number register udp_frm_num read-only 0x0000_0000 0x004 global state register udp_glb_stat read-write 0x0000_0010 0x008 function address register udp_faddr read-write 0x0000_0100 0x00c reserved C C C 0x010 interrupt enable register udp_ier write-only 0x014 interrupt disable register udp_idr write-only 0x018 interrupt mask register udp_imr read-only 0x0000_1200 0x01c interrupt status register udp_isr read-only C (1) 0x020 interrupt clear register udp_icr write-only 0x024 reserved C C C 0x028 reset endpoint register udp_rst_ep read-write 0x0000_0000 0x02c reserved C C C 0x030 endpoint control and status register 0 udp_csr0 read-write 0x0000_0000 ... ... ... ... ... 0x030 + 0x4 * 5 endpoint control and status register 5 udp_csr5 read-write 0x0000_0000 0x050 endpoint fifo data register 0 udp_fdr0 read-write 0x0000_0000 ... ... ... ... ... 0x050 + 0x4 * 5 endpoint fifo data register 5 udp_fdr5 read-write 0x0000_0000 0x070 reserved C C C 0x074 transceiver control register udp_txvc (2) read-write 0x0000_0000 0x078 - 0xfc reserved C C C
557 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 557 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 33.7.1 udp frame number register name: udp_frm_num address: 0xf803c000 access: read-only ? frm_num[10:0]: frame number as defined in the packet field formats this 11-bit value is incremented by the host on a per fr ame basis. this value is updated at each start of frame. value updated at the sof_eop (start of frame end of packet). ? frm_err: frame error this bit is set at sof_eop when the sof packet is received containing an error. this bit is reset upon receipt of sof_pid. ? frm_ok: frame ok this bit is set at sof_eop when the sof packet is received without any error. this bit is reset upon receipt of sof_pid (packet identification). in the interrupt status register, the sof interrupt is updated upon receiving sof_pid. this bit is set without waiting for eop. note: in the 8-bit register interfac e, frm_ok is bit 4 of frm_num_h and frm_err is bit 3 of frm_num_l. 31 30 29 28 27 26 25 24 --- --- --- --- --- --- --- --- 23 22 21 20 19 18 17 16 CCCCCCfrm_okfrm_err 15 14 13 12 11 10 9 8 CCCCC frm_num 76543210 frm_num
558 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 558 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 33.7.2 udp global state register name: udp_glb_stat address: 0xf803c004 access: read-write this register is used to get and set the device state as specified in chapter 9 of the usb serial bus specification, rev.2.0 . ? fadden: function address enable read: 0 = device is not in address state. 1 = device is in address state. write: 0 = no effect, only a reset can bring back a device to the default state. 1 = sets device in address state. this occurs after a successful set address request. beforehand, the udp_faddr regis- ter must have been initialized with set address parameters. set address must complete the status stage before setting fadden. refer to chapter 9 of the universal serial bus specification, rev. 2.0 for more details. ? confg: configured read: 0 = device is not in configured state. 1 = device is in configured state. write: 0 = sets device in a non configured state 1 = sets device in configured state. the device is set in configured state when it is in address st ate and receives a successful set configuration request. refer to chapter 9 of the universal serial bus specification, rev. 2.0 for more details. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCC CC 76543210 C C C rmwupe rsminpr esr confg fadden
559 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 559 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 33.7.3 udp function address register name: udp_faddr address: 0xf803c008 access: read-write ? fadd[6:0]: function address value the function address value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence. refer to the universal serial bus specification, rev. 2.0 for more information. after power up or reset, the function address value is set to 0. ? fen: function enable read: 0 = function endpoint disabled. 1 = function endpoint enabled. write: 0 = disables function endpoint. 1 = default value. the function enable bit (fen) allows the microcontroller to enable or disable the function endpoints. the microcontroller sets this bit after receipt of a reset from the host. once this bit is set, the usb device is able to accept and transfer data packets from and to the host. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCC Cf e n 76543210 Cf a d d
560 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 560 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 33.7.4 udp interrupt enable register name: udp_ier address: 0xf803c010 access: write-only ? ep0int: enable endpoint 0 interrupt ? ep1int: enable endpoint 1 interrupt ? ep2int: enable endpoint 2interrupt ? ep3int: enable endpoint 3 interrupt ? ep4int: enable endpoint 4 interrupt ? ep5int: enable endpoint 5 interrupt 0 = no effect. 1 = enables corresponding endpoint interrupt. ? rxsusp: enable udp suspend interrupt 0 = no effect. 1 = enables udp suspend interrupt. ? rxrsm: enable udp resume interrupt 0 = no effect. 1 = enables udp resume interrupt. ? sofint: enable start of frame interrupt 0 = no effect. 1 = enables start of frame interrupt. ? wakeup: enable udp bus wakeup interrupt 0 = no effect. 1 = enables usb bus interrupt. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 C C wakeup C sofint extrsm rxrsm rxsusp 76543210 ep5int ep4int ep3int ep2int ep1int ep0int
561 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 561 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 33.7.5 udp interrupt disable register name: udp_idr address: 0xf803c014 access: write-only ? ep0int: disable endpoint 0 interrupt ? ep1int: disable endpoint 1 interrupt ? ep2int: disable endpoint 2 interrupt ? ep3int: disable endpoint 3 interrupt ? ep4int: disable endpoint 4 interrupt ? ep5int: disable endpoint 5 interrupt 0 = no effect. 1 = disables corresponding endpoint interrupt. ? rxsusp: disable udp suspend interrupt 0 = no effect. 1 = disables udp suspend interrupt. ? rxrsm: disable udp resume interrupt 0 = no effect. 1 = disables udp resume interrupt. ? sofint: disable start of frame interrupt 0 = no effect. 1 = disables start of frame interrupt ? wakeup: disable usb bus interrupt 0 = no effect. 1 = disables usb bus wakeup interrupt. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 C C wakeup C sofint extrsm rxrsm rxsusp 76543210 ep5int ep4int ep3int ep2int ep1int ep0int
562 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 562 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 33.7.6 udp interrupt mask register name: udp_imr address: 0xf803c018 access: read-only ? ep0int: mask endpoint 0 interrupt ? ep1int: mask endpoint 1 interrupt ? ep2int: mask endpoint 2 interrupt ? ep3int: mask endpoint 3 interrupt ? ep4int: mask endpoint 4 interrupt ? ep5int: mask endpoint 5 interrupt 0 = corresponding endpoint interrupt is disabled. 1 = corresponding endpoint interrupt is enabled. ? rxsusp: mask udp suspend interrupt 0 = udp suspend interrupt is disabled. 1 = udp suspend interrupt is enabled. ? rxrsm: mask udp resume interrupt. 0 = udp resume interrupt is disabled. 1 = udp resume interrupt is enabled. ? sofint: mask start of frame interrupt 0 = start of frame interrupt is disabled. 1 = start of frame interrupt is enabled. ? bit12: udp_imr bit 12 bit 12 of udp_imr cannot be masked and is always read at 1. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 C C wakeup bit12 sofint extrsm rxrsm rxsusp 76543210 ep5int ep4int ep3int ep2int ep1int ep0int
563 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 563 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? wakeup: usb bus wakeup interrupt 0 = usb bus wakeup interrupt is disabled. 1 = usb bus wakeup interrupt is enabled. note: when the usb block is in suspend mode, the application may po wer down the usb logic. in this case, any usb host resume request that is made must be taken into account and, thus, the reset value of th e rxrsm bit of the register udp_imr is enabled.
564 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 564 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 33.7.7 udp interrupt status register name: udp_isr address: 0xf803c01c access: read-only ? ep0int: endpoint 0 interrupt status ? ep1int: endpoint 1 interrupt status ? ep2int: endpoint 2 interrupt status ? ep3int: endpoint 3 interrupt status ? ep4int: endpoint 4 interrupt status ? ep5int: endpoint 5 interrupt status 0 = no endpoint0 interrupt pending. 1 = endpoint0 interrupt has been raised. several signals can generate this interrupt. the reason can be found by reading udp_csr0: rxsetup set to 1 rx_data_bk0 set to 1 rx_data_bk1 set to 1 txcomp set to 1 stallsent set to 1 ep0int is a sticky bit. interrupt remains valid until ep0int is cleared by writing in the corresponding udp_csr0 bit. ? rxsusp: udp suspend interrupt status 0 = no udp suspend interrupt pending. 1 = udp suspend interrupt has been raised. the usb device sets this bit when it detects no ac tivity for 3ms. the usb device enters suspend mode. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 C C wakeup endbusres sofint extrsm rxrsm rxsusp 76543210 ep5int ep4int ep3int ep2int ep1int ep0int
565 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 565 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? rxrsm: udp resume interrupt status 0 = no udp resume interrupt pending. 1 =udp resume interrupt has been raised. the usb device sets this bit when a udp resume signal is detected at its port. after reset, the state of this bit is undefined, the application must clear this bit by setting the rxrsm flag in the udp_icr register. ? sofint: start of frame interrupt status 0 = no start of frame interrupt pending. 1 = start of frame interrupt has been raised. this interrupt is raised each time a sof token has been detected. it can be used as a synchronization signal by using isochronous endpoints. ? endbusres: end of bus reset interrupt status 0 = no end of bus reset interrupt pending. 1 = end of bus reset interrupt has been raised. this interrupt is raised at the end of a udp reset sequence. the usb device must prepare to receive requests on the end- point 0. the host starts the enumeration, then performs the configuration. ? wakeup: udp resume interrupt status 0 = no wakeup interrupt pending. 1 = a wakeup interrupt (usb host sent a resume or reset) occurred since the last clear. after reset the state of this bit is undefined, the application must clear this bit by setting the wakeup flag in the udp_icr register.
566 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 566 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 33.7.8 udp interrupt clear register name: udp_icr address: 0xf803c020 access: write-only ? rxsusp: clear udp suspend interrupt 0 = no effect. 1 = clears udp suspend interrupt. ? rxrsm: clear udp resume interrupt 0 = no effect. 1 = clears udp resume interrupt. ? sofint: clear start of frame interrupt 0 = no effect. 1 = clears start of frame interrupt. ? endbusres: clear end of bus reset interrupt 0 = no effect. 1 = clears end of bus reset interrupt. ? wakeup: clear wakeup interrupt 0 = no effect. 1 = clears wakeup interrupt. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 C C wakeup endbusres sofint extrsm rxrsm rxsusp 76543210 CCCCCCCC
567 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 567 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 33.7.9 udp reset en dpoint register name: udp_rst_ep address: 0xf803c028 access: read-write ? ep0: reset endpoint 0 ? ep1: reset endpoint 1 ? ep2: reset endpoint 2 ? ep3: reset endpoint 3 ? ep4: reset endpoint 4 ? ep5: reset endpoint 5 this flag is used to reset the fifo associated with the endpoint and the bit rxbytecount in the register udp_csrx.it also resets the data toggle to data0. it is useful after removing a halt c ondition on a bulk endpoint. refer to chapter 5.8.5 in the usb serial bus specification, rev.2.0 . warning: this flag must be cleared at the end of the reset. it does not clear udp_csrx flags. 0 = no reset. 1 = forces the corresponding endpoint fif0 pointers to 0, therefore rxbytecnt fi eld is read at 0 in udp_csrx register. resetting the endpoint is a two-step operation: 1. set the corresponding epx field. 2. clear the corresponding epx field. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCC CC 76543210 ep5 ep4 ep3 ep2 ep1 ep0
568 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 568 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 33.7.10 udp endpoint control and status register name: udp_csrx [x = 0..5] address: 0xf803c030 access: read-write warning : due to synchronization between mck and udpck, the soft ware application must wait for the end of the write operation before executing an other write by pollin g the bits which must be set/cleared. #if defined ( __iccarm__ ) #define nop() (__no_operation()) #elif defined ( __gnuc__ ) #define nop() __asm__ __volatile__ ( "nop" ) #endif /// bitmap for all status bits in csr that are not effected by a value 1. #define reg_no_effect_1_all at91c_udp_rx_data_bk0\ | at91c_udp_rx_data_bk1\ | at91c_udp_stallsent\ | at91c_udp_rxsetup\ | at91c_udp_txcomp /// sets the specified bit(s) in the udp_csr register. /// \param endpoint the endpoint number of the csr to process. /// \param flags the bitmap to set to 1. #define set_csr(endpoint, flags) \ { \ volatile unsigned int reg; \ reg = at91c_base_udp->udp_csr[endpoint] ; \ reg |= reg_no_effect_1_all; \ reg |= (flags); \ at91c_base_udp->udp_csr[endpoint] = reg; \ for( nop_count=0; nop_count<15; nop_count++ ) {\ nop();\ 31 30 29 28 27 26 25 24 CCCCC r xbytecnt 23 22 21 20 19 18 17 16 rxbytecnt 15 14 13 12 11 10 9 8 epeds C C C dtgle eptype 76543210 dir rx_data_bk1 forcestall txpktrdy stallsent/ isoerror rxsetup rx_data_ bk0 txcomp
569 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 569 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 }\ } /// clears the specified bit(s) in the udp_csr register. /// \param endpoint the endpoint number of the csr to process. /// \param flags the bitmap to clear to 0. #define clear_csr(endpoint, flags) \ { \ volatile unsigned int reg; \ reg = at91c_base_udp->udp_csr[endpoint]; \ reg |= reg_no_effect_1_all; \ reg &= ~(flags); \ at91c_base_udp->udp_csr[endpoint] = reg; \ for( nop_count=0; nop_count<15; nop_count++ ) {\ nop();\ }\ } in a preemptive environment, set or clear the flag and wait for a time of 1 udpck clock cycle and 1peripheral clock cycle. however, rx_data_bk0, txpktrdy, rx_data_bk1 require wait times of 3 udpck clock cycles and 5 peripheral clock cycles before accessing dpr. ? txcomp: generates an in packet with data previously written in the dpr this flag generates an interr upt while it is set to one. write (cleared by the firmware): 0 = clear the flag, clear the interrupt. 1 = no effect. read (set by the usb peripheral): 0 = data in transaction has not been acknowledged by the host. 1 = data in transaction is achieved, acknowledged by the host. after having issued a data in transaction setting txpktrdy, the device firmware waits for txcomp to be sure that the host has acknowledged the transaction. ? rx_data_bk0: receive data bank 0 this flag generates an interr upt while it is set to one. write (cleared by the firmware): 0 = notify usb peripheral device that data have been read in the fifo's bank 0. 1 = to leave the read value unchanged. read (set by the usb peripheral): 0 = no data packet has been received in the fifo's bank 0. 1 = a data packet has been received, it has been stored in the fifo's bank 0. when the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the fifo to the microcontroller memory. the nu mber of bytes received is av ailable in rxbytcent field. bank 0 fifo values are read
570 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 570 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 through the udp_fdrx register. once a transfer is done, the device firmware must release bank 0 to the usb peripheral device by clearing rx_data_bk0. after setting or clearing this bit, a wait time of 3 udpck clock cycles and 3 peripheral cl ock cycles is required before accessing dpr. ? rxsetup: received setup this flag generates an interr upt while it is set to one. read: 0 = no setup packet available. 1 = a setup data packet has been sent by the host and is available in the fifo. write: 0 = device firmware notifies the usb peripheral device that it has read the setup data in the fifo. 1 = no effect. this flag is used to notify the usb device firmware that a valid setup data packet has been sent by the host and success- fully received by the usb device. the usb device firmware may transfer setup data from the fifo by reading the udp_fdrx register to the microcontroller memory. once a transfer has been done, rxsetup must be cleared by the device firmware. ensuing data out transaction is not accepted while rxsetup is set. ? stallsent: stall sent (control, bulk interrupt endpoints)/isoerror (isochronous endpoints) this flag generates an interr upt while it is set to one. stallsent: this ends a stall handshake. read: 0 = the host has not acknowledged a stall. 1 = host has acknowledged the stall. write: 0 = resets the stallsent flag, clears the interrupt. 1 = no effect. this is mandatory for the device firmware to clear this flag. otherwise the interrupt remains. refer to chapters 8.4.5 and 9.4.5 of the universal serial bus s pecification, rev. 2.0 for more information on the stall handshake. isoerror: a crc error has been detected in an isochronous transfer. read: 0 = no error in the prev ious isochronous transfer. 1 = crc error has been detected, data available in the fifo are corrupted. write: 0 = resets the isoerror flag, clears the interrupt. 1 = no effect.
571 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 571 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? txpktrdy: transmit packet ready this flag is cleared by the usb device. this flag is set by the usb device firmware. read: 0 = there is no data to send. 1 = the data is waiting to be sent upon reception of token in. write: 0 = can be used in the procedure to cancel transmission data. (see, section 33.6.2.5 transmit data cancellation on page 552 ) 1 = a new data payload has been written in the fifo by the firmware and is ready to be sent. this flag is used to generate a data in transaction (device to host). device firmware checks that it can write a data payload in the fifo, checking that txpktrdy is cl eared. transfer to the fi fo is done by writing in the udp_fdrx register. once the data payload has been transferred to the fifo, the firmwar e notifies the usb device setting txpktrdy to one. usb bus transactions can start. txcomp is set once the data payload has been received by the host. after setting or clearing this bit, a wait time of 3 udpck clock cycles and 3 peripheral cl ock cycles is required before accessing dpr. ? forcestall: force stall (used by control, bulk and isochronous endpoints) read: 0 = normal state. 1 = stall state. write: 0 = return to normal state. 1 = send stall to the host. refer to chapters 8.4.5 and 9.4.5 of the universal serial bus s pecification, rev. 2.0 for more information on the stall handshake. control endpoints: during the data stage and status stage, this bit indicates that the microcontroller cannot complete the request. bulk and interrupt endpoints: this bit notifies the host that the endpoint is halted. the host acknowledges the stall, device fi rmware is notified by the stallsent flag. ? rx_data_bk1: receive data bank 1 (only used by endpoints with ping-pong attributes) this flag generates an interr upt while it is set to one. write (cleared by the firmware): 0 = notifies usb device that data have been read in the fifos bank 1. 1 = to leave the read value unchanged.
572 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 572 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 read (set by the usb peripheral): 0 = no data packet has been received in the fifo's bank 1. 1 = a data packet has been received, it has been stored in fifo's bank 1. when the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the fifo to microcontroller memory. the number of bytes received is available in rxbytecnt field. bank 1 fifo values are read through udp_fdrx register. once a transfer is done, the device firmware must release bank 1 to the usb device by clear- ing rx_data_bk1. after setting or clearing this bit, a wait time of 3 udpck clock cycles and 3 peripheral cl ock cycles is required before accessing dpr. ? dir: transfer direction (only available for control endpoints) read-write 0 = allows data out transactio ns in the control data stage. 1 = enables data in transactions in the control data stage. refer to chapter 8.5.3 of the universal serial bus specification, rev. 2.0 for more information on the control data stage. this bit must be set before udp_csrx/rxsetup is cleared at the end of the setup stage. according to the request sent in the setup data packet, the data stage is either a device to host (dir = 1) or host to device (dir = 0) data transfer. it is not necessary to check this bit to reve rse direction for the status stage. ? eptype[2:0]: endpoint type read-write ? dtgle: data toggle read-only 0 = identifies data0 packet. 1 = identifies data1 packet. refer to chapter 8 of the universal serial bus specification, rev. 2.0 for more information on data0, data1 packet definitions. value name description 000 ctrl control 001 iso_out isochronous out 101 iso_in isochronous in 010 bulk_out bulk out 110 bulk_in bulk in 011 int_out interrupt out 111 int_in interrupt in
573 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 573 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? epeds: endpoint enable disable read: 0 = endpoint disabled. 1 = endpoint enabled. write: 0 = disables endpoint. 1 = enables endpoint. control endpoints are always enabled. reading or writing this field has no effect on control endpoints. note: after reset, all endpoints are configured as control endpoints (zero). ? rxbytecnt[10:0]: number of bytes available in the fifo read-only when the host sends a data packet to the device, the usb device stores the data in the fifo and notifies the microcon- troller. the microcontr oller can load the data from the fifo by reading rxbytec ent bytes in the udp_fdrx register.
574 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 574 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 33.7.11 udp fifo data register name: udp_fdrx [x = 0..5] address: 0xf803c050 access: read-write ? fifo_data[7:0]: fifo data value the microcontroller can push or pop values in the fifo through this register. rxbytecnt in the corresponding udp_csrx re gister is the number of bytes to be read from the fifo (sent by the host). the maximum number of bytes to write is fixed by the max packet size in the standard endpoint descriptor. it can not be more than the physical memory size associated to the endpoint. refer to the universal serial bus specification, rev. 2.0 for more information. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCC CC 76543210 fifo_data
575 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 575 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 33.7.12 udp transceiver control register name: udp_txvc address: 0xf803c074 access: read-write warning: the udp peripheral clock in the power management controller (pmc) must be enabled before any read/write operations to the udp registers including the udp_txvc register. ? txvdis: transceiver disable when udp is disabled, power consumption can be reduced significantly by disab ling the embedded transceiver. this can be done by setting txvdis field. to enable the transceiver, txvdis must be cleared. ? puon: pullup on 0: the 1.5k integrated pullup on ddp is disconnected. 1: the 1.5 k integrated pullup on ddp is connected. note : if the usb pullup is not connected on ddp, the user shou ld not write in any udp register other than the udp_txvc register. this is because if ddp and ddm are floating at 0, or pulled down, then se0 is received by the device with the con- sequence of a usb reset. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCC puon txvdis 76543210 CCCCCC CC
576 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 576 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12
577 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 577 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 34. usb host port (uhp) 34.1 description the usb host port (uhp) interfaces the usb with the host application. it handles open hci protocol (open host controller interface) as well as usb v2.0 full-speed and low-speed protocols. the usb host port integrates a root hub and transceivers on downstream ports. it provides sev- eral high-speed half-duplex serial communication ports at a baud rate of 12 mbit/s. up to 127 usb devices (printer, camera, mouse, keyboard , disk, etc.) and the usb hub can be connected to the usb host in the usb tiered star topology. the usb host port controller is fully complia nt with the openhci spec ification. the usb host port user interface (registers description) can be found in the open hci rev 1.0 specification available on http://h18000.www1.hp.com/productinfo/development/openhci.html . the standard ohci usb stack driver can be easily ported to at mels architecture in the same way all exist- ing class drivers run without hardware specialization. this means that all standard class devices are automatically detected and available to the user application. as an example, integrating an hid (human interface device) class driver provides a plug & play feature for all usb keyboards and mouses. 34.2 embedded characteristics ? compliant with openhci rev 1.0 specification ? compliant with usb v2 .0 full-speed and low-speed specification ? supports both low-speed 1.5 mbps and full-speed 12 mbps usb devices ? root hub integrated with 1 downstream usb ports ? embedded usb transceivers ? supports power management
578 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 578 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 34.3 block diagram figure 34-1. block diagram access to the usb host operational registers is achieved through the ahb bus slave interface. the openhci host controller initia lizes master dma transfers th rough the asb bus master inter- face as follows: ? fetches endpoint descriptors and transfer descriptors ? access to endpoint data from system memory ? access to the hc communication area ? write status and retire transfer descriptor memory access errors (abort, misalignment) lead to an unrecoverableerror indicated by the corresponding flag in the host controller operational registers. the usb root hub is integrated in the usb host. several usb downstream ports are available. the number of downstream ports can be determined by the software driver reading the root hubs operational registers. device connection is automatically detected by the usb host port logic. usb physical transceivers are integrated in the product and driven by the root hubs ports. over current protection on ports can be activated by the usb host controller. atmels standard product does not dedicate pads to external over current protection. port s/m port s/m usb transceiver usb transceiver dp dm dp dm embedded usb v2.0 full-speed transceiver root hub and host sie list processor block fifo 64 x 8 hci slave block ohci registers ohci root hub registers ahb ed & td regsisters control hci master block data uhp_int mck uhpck ahb slave master
579 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 579 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 34.4 product dependencies 34.4.1 i/o lines dps and dms are not controlled by any pio controllers. the embedded usb physical transceiv- ers are controlled by the usb host controller. 34.4.2 power management the usb host controller requires a 48 mhz clock. this clock must be generated by a pll with a correct accuracy of 0.25%. thus the usb device peripheral receives two clocks from the power management controller (pmc): the master clock mck used to drive the peripheral user interface (mck domain) and the uhpclk 48 mhz clock used to interface with the bus usb signals (recovered 12 mhz domain). 34.4.3 interrupt the usb host interface has an interrupt line connected to the advanced interrupt controller (aic). handling usb host interrupts requires programming the aic before configuring the uhp. 34.5 functional description please refer to the open host controller interface specification for usb release 1.0.a. 34.5.1 host controller interface there are two communication channels between the host controller and the host controller driver. the first channel uses a set of operational registers located on the usb host controller. the host controller is the target for all co mmunications on this channel. the operational regis- ters contain control, status and list pointer registers. they are mapped in the memory mapped area. within the operational register set there is a pointer to a location in the processor address space named the host controller communication area (hcca). the hcca is the second com- munication channel. the host controller is the master for all communication on this channel. the hcca contains the head pointers to the interrupt endpoint descrip tor lists, the head pointer to the done queue and status information associated with start-of-frame processing. the basic building blocks for communication across the interface are endpoint descriptors (ed, 4 double words) and transfer descriptors (td, 4 or 8 double words). the host controller assigns an endpoint descriptor to each endpoint in the system. a queue of transfer descriptors is linked to the endpoint descriptor for the specific endpoint.
580 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 580 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 34-2. usb host communication channels operational registers mode hcca status event frame int ratio control bulk host controller communications area interrupt 0 interrupt 1 interrupt 2 interrupt 31 done . . . . . . open hci shared ram device register in memory space device enumeration = transfer descriptor = endpoint descriptor . . .
581 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 581 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 34.5.2 host controller driver figure 34-3. usb host drivers usb handling is done through several layers as follows: ? host controller hardware and serial engine: transmits and receives usb data on the bus. ? host controller driver: drives the host controller hardware and handles the usb protocol. ? usb bus driver and hub driver: handles usb commands and enumeration. offers a hardware independent interface. ? mini driver: handles device specific commands. ? class driver: handles standard devices. this acts as a generic driver for a class of devices, for example the hid driver. host controller hardware hub driver host controller driver usb driver mini driver class driver class driver user application kernel drivers user space hardware
582 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 582 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 34.6 typical connection figure 34-4. board schematic to interface uhp device controller a termination serial resistor must be connected to hdp and hdm. the resistor value is defined in the electrical specification of the product (r ext ). r ext hdma or hdmb hdpa or hdpb 10nf 100nf 10f 5v 0.20a type a connector r ext
583 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 583 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35. high speed multimedia card interface (hsmci) 35.1 description the high speed multimedia card interface (hsmci) supports the multimedia card (mmc) specification v4.3, the sd memo ry card specification v2.0, th e sdio v2.0 specification and ce-ata v1.1. the hsmci includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead. the hsmci supports stream, block and multi block data read and write, and is compatible with the dma controller (dmac), minimizing processor intervention for large buffer transfers. the hsmci operates at a rate of up to master clock divided by 2 and supports the interfacing of 1 slot(s). each slot may be used to interface with a high speed multimediacard bus (up to 30 cards) or with an sd memory card. only one slot can be selected at a time (slots are multi- plexed). a bit field in the sd card register performs this selection. the sd memory card communication is based on a 9-pin interface (clock, command, four data and three power lines) and the high speed multimedia card on a 7-pin interface (clock, com- mand, one data, three power lines and one reserved for future use). the sd memory card interface also supports high speed multimedia card operations. the main differences between sd and high speed multimedia cards are the initialization process and the bus topology. hsmci fully supports ce-ata revision 1.1, bui lt on the mmc system specification v4.0. the module includes dedicated hardware to issue the command completion signal and capture the host command completion signal disable. 35.2 embedded characteristics ? compatible with multimedia card specification version 4.3 ? compatible with sd memory card specification version 2.0 ? compatible with sdio specification version 2.0 ? compatible with ce-ata specification 1.1 ? cards clock rate up to master clock divided by 2 ? boot operation mode support ? high speed mode support ? embedded power management to slow down clock rate when not used ? supports 1 multiplexed slot(s) C each slot for either a high speed multimediacard bus (up to 30 cards) or an sd memory card ? support for stream, block and multi-block data read and write ? supports connection to dma controller (dmac) C minimizes processor intervention for large buffer transfers ? built in fifo (from 16 to 256 bytes) with large memory aperture supporting incremental access ? support for ce-ata completion signal disable command ? protection against unexpected modification on-the-fly of the configuration registers
584 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 584 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35.3 block diagram figure 35-1. block diagram 35.4 application block diagram figure 35-2. application block diagram hsmci interface interrupt control pio dmac apb bridge pmc mck hsmci interrupt mcck (1) mccda (1) mcda0 (1) mcda1 (1) mcda2 (1) mcda3 (1) apb 23456 17 mmc 23456 17 8 sdcard 9 physical layer hsmci interface application layer ex: file system, audio, security, etc. 9 1011 1213 8
585 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 585 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35.5 pin name list notes: 1. i: input, o: output, pp: push/pull, od: open drain. 2. when several hsmci (x hsmci) are embedded in a produc t, mcck refers to hsmcix_ck, mccda to hsmcix_cda, mcday to hsmcix_day. 35.6 product dependencies 35.6.1 i/o lines the pins used for interfacing the high speed mu ltimedia cards or sd ca rds are multiplexed with pio lines. the programmer must first program the pio controllers to assign the peripheral func- tions to hsmci pins. 35.6.2 power management the hsmci is clocked through the power management controller (pmc), so the programmer must first configure the pmc to enable the hsmci clock. 35.6.3 interrupt the hsmci interface has an interrupt line connected to the advanced interrupt controller (aic). handling the hsmci interrupt requires programming the aic before configuring the hsmci. 35.7 bus topology figure 35-3. high speed multimedia me mory card bus topology table 35-1. i/o lines description for 4-bit configuration pin name (2) pin description type (1) comments mccda command/response i/o/pp/od cm d of an mmc or sdcard/sdio mcck clock i/o clk of an mmc or sd card/sdio mcda0 - mcda3 data 0..3 of slot a i/o/pp dat[0..3] of an mmc dat[0..3] of an sd card/sdio table 35-2. peripheral ids instance id hsmci 12 23456 17 mmc 91011 12138
586 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 586 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 the high speed multimedia card communication is based on a 13-pin serial bus interface. it has three communication lines and four supply lines. notes: 1. i: input, o: output, pp : push/pull, od: open drain. 2. when several hsmci (x hsmci) are embedded in a product, mcck refers to hsmcix_ck, mccda to hsmcix_cda, mcday to hsmcix_day. figure 35-4. mmc bus connections (one slot) note: when several hsmci (x hsmci) are embedded in a product, mcck refers to hsmcix_ck, mccda to hsmcix_cda mcday to hsmcix_day. table 35-3. bus topology pin number name type (1) description hsmci pin name (2) (slot z) 1 dat[3] i/o/pp data mcdz3 2 cmd i/o/pp/od command/response mccdz 3 vss1 s supply voltage ground vss 4 vdd s supply voltage vdd 5 clk i/o clock mcck 6 vss2 s supply voltage ground vss 7 dat[0] i/o/pp data 0 mcdz0 8 dat[1] i/o/pp data 1 mcdz1 9 dat[2] i/o/pp data 2 mcdz2 10 dat[4] i/o/pp data 4 mcdz4 11 dat[5] i/o/pp data 5 mcdz5 12 dat[6] i/o/pp data 6 mcdz6 13 dat[7] i/o/pp data 7 mcdz7 mccda mcda0 mcck hsmci 23456 17 mmc1 9 1011 1213 8 23456 17 mmc2 9 1011 1213 8 23456 17 mmc3 9 1011 1213 8
587 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 587 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 35-5. sd memory card bus topology the sd memory card bus includes the signals listed in table 35-4 . notes: 1. i: input, o: output, pp: push pull, od: open drain. 2. when several hsmci (x hsmci) are embedded in a product, mcck refers to hsmcix_ck, mccda to hsmcix_cda, mcday to hsmcix_day. figure 35-6. sd card bus connections with one slot note: when several hsmci (x hsmci) are embedded in a product, mcck refers to hsmcix_ck, mccda to hsmcix_cda mcday to hsmcix_day. when the hsmci is configured to operate with sd memory cards, the width of the data bus can be selected in the hsmci_sdcr register. cleari ng the sdcbus bit in this register means that the width is one bit; setting it means that the width is four bits. in the case of high speed multi- media cards, only the data line 0 is used. the other data lines can be used as independent pios. table 35-4. sd memory card bus signals pin number name type (1) description hsmci pin name (2) (slot z) 1 cd/dat[3] i/o/pp card detect/ data line bit 3 mcdz3 2 cmd pp command/response mccdz 3 vss1 s supply voltage ground vss 4 vdd s supply voltage vdd 5 clk i/o clock mcck 6 vss2 s supply voltage ground vss 7 dat[0] i/o/pp data line bit 0 mcdz0 8 dat[1] i/o/pp data line bit 1 or interrupt mcdz1 9 dat[2] i/o/pp data line bit 2 mcdz2 23456 17 8 sd card 9 23456 17 mcda0 - mcda3 mccda mcck 8 sd card 9
588 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 588 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35.8 high speed multim ediacard operations after a power-on reset, the cards are initialized by a special message-based high speed multi- mediacard bus protocol. each message is represented by one of the following tokens: ? command: a command is a token that starts an operation. a command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). a command is transferred serially on the cmd line. ? response: a response is a token which is sent from an addressed card or (synchronously) from all connected cards to the host as an answer to a previously received command. a response is transferred serially on the cmd line. ? data: data can be transferred from the card to the host or vice versa. data is transferred via the data line. card addressing is implemented using a sess ion address assigned during the initialization phase by the bus controller to all currently connected cards. their unique cid number identifies individual cards. the structure of commands, responses and data blocks is described in the high speed multime- dia-card system specification. see also table 35-5 on page 589 . high speed multimediacard bus data transfers are composed of these tokens. there are different types of operations. addressed operations always contain a command and a response token. in addition, some operations have a data token; the others transfer their infor- mation directly within the command or response structure. in this case, no data token is present in an operation. the bits on the dat and the cmd lines are transferred synchronous to the clock hsmci clock. two types of data transfer commands are defined: ? sequential commands: these commands initiate a continuous data stream. they are terminated only when a stop command follows on the cmd line. this mode reduces the command overhead to an absolute minimum. ? block-oriented commands: th ese commands send a data block succeeded by crc bits. both read and write operations allow either single or multiple block transmission. a multiple block transmission is terminated when a stop co mmand follows on the cmd line similarly to the sequential read or when a multiple block transmission has a pre-defined block count ( see data transfer operation on page 591. ). the hsmci provides a set of registers to perform the entire range of high speed multimedia card operations. 35.8.1 command - response operation after reset, the hsmci is disabled and becomes valid after setting the mcien bit in the hsmci_cr control register. the pwsen bit saves power by dividing the hsmci clock by 2 pwsdiv + 1 when the bus is inactive. the two bits, rdproof and wrproof in the hsmci mode register (hsmci_mr) allow stopping the hsmci clock during read or write access if the internal fifo is full. this will guar- antee data integrity, not bandwidth. all the timings for high speed multimedia card are defined in the high speed multimediacard system specification.
589 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 589 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 the two bus modes (open drain and push/pull) needed to process all the operations are defined in the hsmci command register. the hsmci_cm dr allows a command to be carried out. for example, to perform an all_send_cid command: the command all_send_cid and the fields and values for the hsmci_cmdr control regis- ter are described in table 35-5 and table 35-6 . note: bcr means broadcast command with response. the hsmci_argr contains the argument field of the command. to send a command, the user must perform the following steps: ? fill the argument register (hsmci _argr) with the command argument. ? set the command register (hsmci_cmdr) (see table 35-6 ). the command is sent immediately after writing the command register. while the card maintains a busy indication (at the end of a stop_transmission command cmd12, for example), a new command shall not be sent. the notbusy flag in the status regis- ter (hsmci_sr) is asserted when the card releases the busy indication. if the command requires a response, it can be read in the hsmci response register (hsmci_rspr). the response size can be from 48 bits up to 136 bits depending on the com- mand. the hsmci embeds an error detection to prevent any corrupted data during the transfer. host command n id cycles cid cmd s t content crc e z ****** z s t content z z z table 35-5. all_send_cid command description cmd index type argument resp abbreviation command description cmd2 bcr [31:0] stuff bits r2 all_send_cid asks all cards to send their cid numbers on the cmd line table 35-6. fields and values for hsmci_cmdr command register field value cmdnb (command number) 2 (cmd2) rsptyp (response type) 2 (r2: 136 bits response) spcmd (special command) 0 (not a special command) opcmd (open drain command) 1 maxlat (max latency for command to response) 0 (nid cycles ==> 5 cycles) trcmd (transfer command) 0 (no transfer) trdir (transfer direction) x (available only in transfer command) trtyp (transfer type) x (available only in transfer command) iospcmd (sdio special command) 0 (not a special command)
590 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 590 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 the following flowchart shows how to send a command to the card and read the response if needed. in this example, the status register bits are polled but setting the appropriate bits in the interrupt enable register (hsmci_ier) allows using an interrupt method. figure 35-7. command/response functional flow diagram return ok return error (1) return ok set the command argument hsmci_argr = argument (1) set the command hsmci_cmdr = command read hsmci_sr cmdrdy status error flags? read response if required ye s w a it for command ready status flag check error bits in the status register (1) 0 1 does the comma nd involve a bus y indication? no read hsmci_sr 0 notbu sy 1
591 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 591 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 note: 1. if the command is send_op_cond, the crc error flag is always present (refer to r3 res ponse in the high speed multime- dia card specification). 35.8.2 data transfer operation the high speed multimedia card allows several r ead/write operations (single block, multiple blocks, stream, etc.). these kinds of transfer can be selected setting the transfer type (trtyp) field in the hsmci command register (hsmci_cmdr). these operations can be done using the features of the dma controller. in all cases, the block length (blklen field) must be defined either in the mode register hsmci_mr, or in the block register hsmci_blkr. this field determines the size of the data block. consequent to mmc specification 3.1, two types of multiple block read (or write) transactions are defined (the host can use either one at any time): ? open-ended/infinite multiple block read (or write): the number of blocks for the read (or write) multiple block operation is not defined. the card will continuously transfer (o r program) data blocks until a stop transmission command is received. ? multiple block read (or write) with pre-defined block count (since version 3.1 and higher): the card will transfer (or prog ram) the requested number of data blocks and terminate the transaction. the stop command is not required at the end of this type of multiple block read (or write), unless terminated with an error. in order to start a multiple block read (or write) with pre-defined block count, the host must correctly program the hsmci block register (hsmci_blkr). otherwise the ca rd will start an open-ended mu ltiple block read. the bcnt field of the block register defines the number of blocks to transfer (from 1 to 65535 blocks). programming the value 0 in the bcnt field co rresponds to an infinite block transfer. 35.8.3 read operation the following flowchart ( figure 35-8 ) shows how to read a single block with or without use of dmac facilities. in this example, a polling met hod is used to wait for the end of read. similarly, the user can configure the interrupt enable regist er (hsmci_ier) to trigger an interrupt at the end of read.
592 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 592 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 35-8. read functional flow diagram notes: 1. it is assumed that this co mmand has been correctly sent (see figure 35-7 ). 2. this field is also accessible in the hsmci block register (hsmci_blkr). read status register hsmci_sr send select/deselect_card command (1) to select the card send set_blocklen command (1) read with dmac number of words to read = 0 ? poll the bit rxrdy = 0? read data = hsmci_rdr number of words to read = number of words to read -1 send read_single_block command (1) ye s set the dmaen bit hsmci_dma |= dmaen set the block length (in bytes) hsmci_blkr |= (blocklength << 16) (2) configure the dma channel x dmac_saddrx = data address dmac_btsize = blocklength/4 dmachen[x] = true send read_single_block command (1) read status register hsmci_sr poll the bit xfrdone = 0? ye s return return ye s no no no ye s no number of words to read = blocklength/4 reset the dmaen bit hsmci_dma &= ~dmaen set the block length (in bytes) hsmci_mr l= (blocklength<<16) (2) set the block count (if neccessary) hsmci_blkr l= (blockcount<<0)
593 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 593 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35.8.4 write operation in write operation, the hsmci mode register (hsmci_mr) is used to define the padding value when writing non-multiple block size. if the bit padv is 0, then 0x00 value is used when padding data, otherwise 0xff is used. if set, the bit dmaen in the hsmci_dma register enables dma transfer. the following flowchart ( figure 35-9 ) shows how to write a single block with or without use of dma facilities. polling or interrupt method can be used to wait for the end of write according to the contents of the interrupt mask register (hsmci_imr).
594 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 594 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 35-9. write functional flow diagram note: 1. it is assumed th at this command has been correctly sent (see figure 35-7 ). 2. this field is also accessible in the hsmci block register (hsmci_blkr). send select/deselect_card command (1) to select the card send set_blocklen command (1) write using dmac send write_single_block command (1) configure the dma channel x dmac_daddrx = data address to write dmac_btsize = blocklength/4 send write_single_block command (1) read status register hsmci_sr poll the bit xfrdone = 0? ye s no ye s no read status register hsmci_sr number of words to write = 0 ? poll the bit txrdy = 0? hsmci_tdr = data to write number of words to write = number of words to write -1 ye s return no ye s no number of words to write = blocklength/4 dmac_chen[x] = true reset thedmaen bit hsmci_dma &= ~dmaen set the block length (in bytes) hsmci_mr |= (blocklength) <<16) (2) set the block count (if necessary) hsmci_blkr |= (blockcount << 0) set the dmaen bit hsmci_dma |= dmaen set the block length (in bytes) hsmci_blkr |= (blocklength << 16) (2) return
595 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 595 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 the following flowchart ( figure 35-10 ) shows how to manage read multiple block and write mul- tiple block transfers with the dma controller. polling or in terrupt method can be used to wait for the end of write according to the contents of the interrupt mask register (hsmci_imr). figure 35-10. read multiple block an d write multiple block notes: 1. it is assumed that this command has been correctly sent (see figure 35-7 ). 2. handle errors reported in hsmci_sr. send select/deselect_card command (1) to select the card send set_blocklen command (1) set the block length hsmci_mr |= (blocklength << 16) set the dmaen bit hsmci_dma |= dmaen configure the hdma channel x dmac_saddrx and dmac_daddrx dmac_btsize = blocklength/4 send write_multiple_block or read_multiple_block command (1) read status register dmac_ebcisr and poll bit cbtc[x] new buffer ? (2) no dmac_chen[x] = true poll the bit xfrdone = 1 no return ye s send stop_transmission command (1) ye s read status register hsmci_sr and poll bit fifoempty
596 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 596 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35.8.5 write_single_block operation using dma controller 1. wait until the current command execution has successfully terminated. c. check that cmdrdy and notbusy fields are asserted in hsmci_sr 2. program the block length in the card. this value defines the value block_length. 3. program the block length in the hsmci configuration register with block_length value. 4. program hsmci_dma register with the following fields: C offset field with dma_offset. C chksize is user defined and set according to dmac_dcsize. C dmaen is set to true to enable dma hardware handshaking in the hsmci. this bit was previously set to false. 5. issue a write_single_block comman d writing hsmci_arg then hsmci_cmdr. 6. program the dma controller. a. read the channel register to choose an available (disabled) channel. b. clear any pending interrupts on the channel from the previous dmac transfer by reading the dmac_ebcisr register. c. program the channel registers. d. the dmac_saddrx register for channel x must be set to the location of the source data. when the first data location is not word aligned, the two lsb bits define the temporary value called dma_offset. the two lsb bits of dmac_saddrx must be set to 0. e. the dmac_daddrx register for channel x must be set with the starting address of the hsmci_fifo address. f. program dmac_ctrlax register of channel x with the following fields values: Cdst_width is set to word. Csrc_width is set to word. Cdcsize must be set according to the value of hsmci_dma, chksize field. Cbtsize is programmed with ceiling((block_length + dma_offset) / 4), where the ceiling function is the function that re turns the smallest integer not less than x. g. program dmac_ctrlbx register for channel x with the following fields values: Cdst_incr is set to incr, the block_length value must not be larger than the hsmci_fifo aperture. Csrc_incr is set to incr. Cfc field is programmed with memory to peripheral flow control mode. Cboth dst_dscr and src_dscr are set to 1 (descriptor fetch is disabled). Cdif and sif are set with their respective layer id. if sif is different from dif, the dma controller is able to prefetch data and write hsmci simultaneously. h. program dmac_cfgx register for channel x with the following fields values: Cfifocfg defines the watermark of the dmac channel fifo. Cdst_h2sel is set to true to enable hardware handshaking on the destination. Cdst_per is programmed with the hardware handshaking id of the targeted hsmci host controller.
597 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 597 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 i. enable channel x, writing one to dmac_cher[x]. the dmac is ready and waiting for request. 7. wait for xfrdone in hsmci_sr register. 35.8.6 read_single_block operation using dma controller 35.8.6.1 block length is multiple of 4 1. wait until the current command execution has successfully completed. a. check that cmdrdy and notbusy are asserted in hsmci_sr. 2. program the block length in the card. this value defines the value block_length. 3. program the block length in the hsmci configuration register with block_length value. 4. set rdproof bit in hsmci_mr to avoid overflow. 5. program hsmci_dma register with the following fields: C ropt field is set to 0. C offset field is set to 0. C chksize is user defined. C dmaen is set to true to enable dmac hardware handshaking in the hsmci. this bit was previously set to false. 6. issue a read_single_block command. 7. program the dma controller. a. read the channel register to choose an available (disabled) channel. b. clear any pending interrupts on the channel from the previous dma transfer by reading the dmac_ebcisr register. c. program the channel registers. d. the dmac_saddrx register for channel x must be set with the starting address of the hsmci_fifo address. e. the dmac_daddrx register for channel x must be word aligned. f. program dmac_ctrlax register of channel x with the following fields values: Cdst_width is set to word. Csrc_width is set to word. Cscsize must be set according to the value of hsmci_dma, chksize field. Cbtsize is programmed with block_length/4. g. program dmac_ctrlbx register for channel x with the following fields values: C dst_incr is set to incr. C src_incr is set to incr. C fc field is programmed with periphera l to memory flow control mode. C both dst_dscr and src_dscr are set to 1 (descriptor fetch is disabled). C dif and sif are set with their respective layer id. if sif is different from dif, the dma controller is able to prefetch data and write hsmci simultaneously. h. program dmac_cfgx register for channel x with the following fields values: Cfifocfg defines the watermark of the dma channel fifo. Csrc_h2sel is set to true to enable hardware handshaking on the destination. Csrc_per is programmed with the hardware handshaking id of the targeted hsmci host controller.
598 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 598 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 Cenable channel x, writing one to dmac_cher[x]. the dmac is ready and waiting for request. 8. wait for xfrdone in hsmci_sr register. 35.8.6.2 block length is not multiple of 4 and padding not used (ropt field in hsmci_dma register set to 0) in the previous dma transfer flow (block length multiple of 4), the dma controller is configured to use only word ahb access. when the block length is no longer a multiple of 4 this is no longer true. the dma controller is programmed to copy exactly the block length number of bytes using 2 transfer descriptors. 1. use the previous step until read_single_block then 2. program the dma controller to use a two descriptors linked list. a. read the channel register to choose an available (disabled) channel. b. clear any pending interrupts on the channel from the previous dma transfer by reading the dmac_ebcisr register. c. program the channel registers in the memory for the first descriptor. this descriptor will be word oriented. this descriptor is refe rred to as lli_w, st anding for lli word oriented transfer. d. the lli_w.dmac_saddrx field in memory must be set with the starting address of the hsmci_fifo address. e. the lli_w.dmac_daddrx field in th e memory must be word aligned. f. program lli_w.dmac_ctrlax with the following fields values: Cdst_width is set to word. Csrc_width is set to word. Cscsize must be set according to the value of hsmci_dma, chksize field. Cbtsize is programmed with block_length/4. if btsize is zero, this descriptor is skipped later. g. program lli_w.dmac_ctrlbx with the following fields values: Cdst_incr is set to incr Csrc_incr is set to incr Cfc field is programmed with peripheral to memory flow control mode. Csrc_dscr is set to zero. (descriptor fetch is enabled for the src) Cdst_dscr is set to one. (descriptor fetch is disabled for the dst) Cdif and sif are set with their respective layer id. if sif is different from dif, dma controller is able to prefetch data and write hsmci simultaneously. h. program lli_w.dmac_cfgx register for channel x with the following fields values: Cfifocfg defines the watermark of the dma channel fifo. Cdst_rep is set to zero meaning that address are contiguous. Csrc_h2sel is set to true to enable hardware handshaking on the destination. Csrc_per is programmed with the hardware handshaking id of the targeted hsmci host controller. i. program lli_w.dmac_dscrx with the address of lli_b descriptor. and set dscrx_if to the ahb layer id. this operation actually links the word oriented
599 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 599 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 descriptor on the second byte oriented descriptor. when block_length[1:0] is equal to 0 (multiple of 4) lli_w.dmac_dscrx points to 0, only lli_w is relevant. j. program the channel registers in the memory for the second descriptor. this descriptor will be byte oriented . this descriptor is referred to as lli_b, standing for lli byte oriented. k. the lli_b.dmac_saddrx field in memory must be set with the starting address of the hsmci_fifo address. l. the lli_b.dmac_daddrx is not relevant if previous word aligned descriptor was enabled. if 1, 2 or 3 bytes are transferred that address is user defined and not word aligned. m. program lli_b.dmac_ctrlax with the following fields values: Cdst_width is set to byte. Csrc_width is set to byte. Cscsize must be set according to the value of hsmci_dma, chksize field. Cbtsize is programmed with block_length[1:0]. (last 1, 2, or 3 bytes of the buffer). n. program lli_b.dmac_ctrlbx with the following fields values: Cdst_incr is set to incr Csrc_incr is set to incr Cfc field is programmed with peripheral to memory flow control mode. Cboth src_dscr and dst_dscr are set to 1 (descriptor fetch is disabled) or next descriptor location points to 0. Cdif and sif are set with their respective layer id. if sif is different from dif, dma controller is able to prefetch da ta and write hsmci simultaneously. o. program lli_b.dmac_cfgx memory location for channel x with the following fields values: C fifocfg defines the watermark of the dma channel fifo. C src_h2sel is set to true to enable hardware handshaking on the destination. C src_per is programmed with the hardware handshaking id of the targeted hsmci host controller. p. program lli_b.dmac_dscr with 0. q. program dmac_ctrlbx register for channel x with 0. its content is updated with the lli fetch operation. r. program dmac_dscrx with the address of lli_w if block_length greater than 4 else with address of lli_b. s. enable channel x writing one to dmac_c her[x]. the dmac is ready and waiting for request. 3. wait for xfrdone in hsmci_sr register. 35.8.6.3 block length is not multiple of 4, with padding value (ropt field in hsmci_dma register set to 1) when the ropt field is set to one, the dma controller performs only word access on the bus to transfer a non-multiple of 4 block length. unlik e previous flow, in which the transfer size is rounded to the nearest multiple of 4. 1. program the hsmci interface, see previous flow. C ropt field is set to 1. 2. program the dma controller
600 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 600 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 a. read the channel register to choose an available (disabled) channel. b. clear any pending interrupts on the channel from the previous dma transfer by reading the dmac_ebcisr register. c. program the channel registers. d. the dmac_saddrx register for channel x must be set with the starting address of the hsmci_fifo address. e. the dmac_daddrx register for channel x must be word aligned. f. program dmac_ctrlax register of channel x with the following fields values: Cdst_width is set to word Csrc_width is set to word Cscsize must be set according to the value of hsmci_dma.chksize field. Cbtsize is programmed with ceiling(block_length/4). g. program dmac_ctrlbx register for channel x with the following fields values: Cdst_incr is set to incr Csrc_incr is set to incr Cfc field is programmed with peripheral to memory flow control mode. Cboth dst_dscr and src_dscr are set to 1. (descriptor fetch is disabled) Cdif and sif are set with their respective layer id. if sif is different from dif, the dma controller is able to prefetch data and write hsmci simultaneously. h. program dmac_cfgx register for channel x with the following fields values: Cfifocfg defines the watermark of the dma channel fifo. Csrc_h2sel is set to true to enable hardware handshaking on the destination. Csrc_per is programmed with the hardware handshaking id of the targeted hsmci host controller. Cenable channel x writing one to dmac_cher[x]. the dmac is ready and waiting for request. 3. wait for xfrdone in hsmci_sr register. 35.8.7 write_multiple_block 35.8.7.1 one block per descriptor 1. wait until the current command execution has successfully terminated. a. check that cmdrdy and notbusy are asserted in hsmci_sr. 2. program the block length in the card. this value defines the value block_length. 3. program the block length in the hsmci configuration register with block_length value. 4. program hsmci_dma register with the following fields: C offset field with dma_offset. C chksize is user defined. C dmaen is set to true to enable dmac hardware handshaking in the hsmci. this bit was previously set to false. 5. issue a write_multiple_block command. 6. program the dma controller to use a list of descriptors. each descriptor transfers one block of data. block n of data is transferred with descriptor lli(n).
601 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 601 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 a. read the channel register to choose an available (disabled) channel. b. clear any pending interrupts on the channel from the previous dmac transfer by reading the dmac_ebcisr register. c. program a list of descriptors. d. the lli(n).dmac_saddrx memory location for channel x must be set to the loca- tion of the source data. when the first data location is not word aligned, the two lsb bits define the temporary value called dma_offset. the two lsb bits of lli(n).dmac_saddrx must be set to 0. e. the lli(n).dmac_daddrx register for ch annel x must be set with the starting address of the hsmci_fifo address. f. program lli(n).dmac_ctrlax register of channel x with the following fields values: Cdst_width is set to word. Csrc_width is set to word. Cdcsize must be set according to the value of hsmci_dma, chksize field. Cbtsize is programmed with ceiling((block_length + dma_offset)/4). g. program lli(n).dmac_ctrlbx register for channel x with the following fields values: Cdst_incr is set to incr. Csrc_incr is set to incr. Cdst_dscr is set to 0 (fetch operation is enabled for the destination). Csrc_dscr is set to 1 (sou rce address is contiguous). Cfc field is programmed with memory to peripheral flow control mode. Cboth dst_dscr and src_dscr are set to 1 (descriptor fetch is disabled). Cdif and sif are set with their respective layer id. if sif is different from dif, dma controller is able to prefetch da ta and write hsmci simultaneously. h. program lli(n).dmac_cfgx register for channel x with the following fields values: Cfifocfg defines the watermark of the dma channel fifo. Cdst_h2sel is set to true to enable hardware handshaking on the destination. Csrc_rep is set to 0. (contiguous memory access at block boundary) Cdst_per is programmed with the hardware handshaking id of the targeted hsmci host controller. i. if lli(n) is the last descriptor, then lli(n).dscr points to 0 else lli(n) points to the start address of lli(n+1). j. program dmac_ctrlbx for channel register x with 0. its content is updated with the lli fetch operation. k. program dmac_dscrx for channel register x with the address of the first descrip- tor lli(0). l. enable channel x writing one to dmac _cher[x]. the dma is ready and waiting for request. 7. poll cbtc[x] bit in the dmac_ebcisr register. 8. if a new list of buffers shall be transferred, repeat step 6. check and handle hsmci errors. 9. poll fifoempty field in the hsmci_sr.
602 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 602 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 10. send the stop_transmission co mmand writing hsmci_arg then hsmci_cmdr. 11. wait for xfrdone in hsmci_sr register. 35.8.8 read_multiple_block 35.8.8.1 block length is a multiple of 4 1. wait until the current command execution has successfully terminated. a. check that cmdrdy and notbusy are asserted in hsmci_sr. 2. program the block length in the card. this value defines the value block_length. 3. program the block length in the hsmci configuration register with block_length value. 4. set rdproof bit in hsmci_mr to avoid overflow. 5. program hsmci_dma register with the following fields: C ropt field is set to 0. C offset field is set to 0. C chksize is user defined. C dmaen is set to true to enable dmac hardware handshaking in the hsmci. this bit was previously set to false. 6. issue a read_multiple_block command. 7. program the dma controller to use a list of descriptors: a. read the channel register to choose an available (disabled) channel. b. clear any pending interrupts on the channel from the previous dma transfer by reading the dmac_ebcisr register. c. program the channel registers in the memory with the first descriptor. this descrip- tor will be word oriented. this descriptor is referred to as lli_w(n ), standing for lli word oriented transfer for block n . d. the lli_w(n).dmac_saddrx field in memory must be set with the starting address of the hsmci_fifo address. e. the lli_w(n).dmac_daddrx field in the memory must be word aligned. f. program lli_w(n).dmac_ctrlax with the following fields values: Cdst_width is set to word Csrc_width is set to word Cscsize must be set according to the value of hsmci_dma, chksize field. Cbtsize is programmed with block_length/4. g. program lli_w(n).dmac_ctrlbx with the following fields values: Cdst_incr is set to incr. Csrc_incr is set to incr. Cfc field is programmed with peripheral to memory flow control mode. Csrc_dscr is set to 0 (descripto r fetch is enabled for the src). Cdst_dscr is set to true (descriptor fetch is disabled for the dst). Cdif and sif are set with their respective layer id. if sif is different from dif, the dma controller is able to prefetch data and write hsmci simultaneously. h. program lli_w(n).dmac_cfgx register for channel x with the following fields values: Cfifocfg defines the watermark of the dma channel fifo.
603 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 603 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 Cdst_rep is set to zero. addresses are contiguous. Csrc_h2sel is set to true to enable hardware handshaking on the destination. Csrc_per is programmed with the hardware handshaking id of the targeted hsmci host controller. i. program lli_w(n).dmac_dscrx with the address of lli_w(n+1) descriptor. and set the dscrx_if to the ahb layer id. this operation actually links descriptors together. if lli_w(n) is the last descriptor then lli_w(n).dmac_dscrx points to 0. j. program dmac_ctrlbx register for channel x with 0. its content is updated with the lli fetch operation. k. program dmac_dscrx register for channel x with the address of lli_w(0). l. enable channel x writing one to dmac _cher[x]. the dma is ready and waiting for request. 8. poll cbtc[x] bit in the dmac_ebcisr register. 9. if a new list of buffer shall be transferred repeat step 6. check and handle hsmci errors. 10. poll fifoempty field in the hsmci_sr. 11. send the stop_transmission command writing the hsmci_arg then the hsmci_cmdr. 12. wait for xfrdone in hsmci_sr register. 35.8.8.2 block length is not multiple of 4. (ropt field in hsmci_dma register set to 0) two dma transfer descriptors are used to perform the hsmci block transfer. 1. use the previous step to configure the hsmci to perform a read_multiple_block command. 2. issue a read_multiple_block command. 3. program the dma controller to use a list of descriptors. a. read the channel register to choose an available (disabled) channel. b. clear any pending interrupts on the channel from the previous dmac transfer by reading the dmac_ebcisr register. c. for every block of data repeat the following procedure: d. program the channel registers in the memory for the first descriptor. this descriptor will be word oriented. this descriptor is referred to as lli_w(n ) standing for lli word oriented transfer for block n . e. the lli_w(n).dmac_saddrx field in memory must be set with the starting address of the hsmci_fifo address. f. the lli_w(n).dmac_daddrx field in the memory must be word aligned. g. program lli_w(n).dmac_ctrlax with the following fields values: Cdst_width is set to word. Csrc_width is set to word. Cscsize must be set according to the value of hsmci_dma, chksize field. Cbtsize is programmed with block_length/4. if btsize is zero, this descriptor is skipped later. h. program lli_w(n).dmac_ctrlbx with the following fields values: Cdst_incr is set to incr.
604 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 604 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 Csrc_incr is set to incr. Cfc field is programmed with peripheral to memory flow control mode. Csrc_dscr is set to 0 (descripto r fetch is enabled for the src). Cdst_dscr is set to true (descriptor fetch is disabled for the dst). Cdif and sif are set with their respective layer id. if sif is different from dif, the dma controller is able to prefetch data and write hsmci simultaneously. i. program lli_w(n).dmac_cfgx register for channel x with the following fields values: Cfifocfg defines the watermark of the dma channel fifo. Cdst_rep is set to zero. address are contiguous. Csrc_h2sel is set to true to enable hardware handshaking on the destination. Csrc_per is programmed with the hardware handshaking id of the targeted hsmci host controller. j. program lli_w(n).dmac_dscrx with the address of lli_b(n) descriptor. and set the dscrx_if to the ahb layer id. this operation actually links the word oriented descriptor on the second byte oriented descriptor. when block_length[1:0] is equal to 0 (multiple of 4) lli_w(n).dmac_dscrx points to 0, only lli_w(n) is relevant. k. program the channel registers in the memory for the second descriptor. this descriptor will be byte oriented . this descriptor is referred to as lli_b(n), standing for lli byte oriented. l. the lli_b(n).dmac_saddrx field in memory must be set with the starting address of the hsmci_fifo address. m. the lli_b(n).dmac_daddrx is not relevant if previous word aligned descriptor was enabled. if 1, 2 or 3 bytes are transferred, that address is user defined and not word aligned. n. program lli_b(n).dmac_ctrlax with the following fields values: Cdst_width is set to byte. Csrc_width is set to byte. Cscsize must be set according to the value of hsmci_dma, chksize field. Cbtsize is programmed with block_length[1:0]. (last 1, 2, or 3 bytes of the buffer). o. program lli_b(n).dmac_ctrlbx with the following fields values: C dst_incr is set to incr. C src_incr is set to incr. C fc field is programmed with periphera l to memory flow control mode. C both src_dscr and dst_dscr are set to 1 (descriptor fetch is disabled) or next descriptor location points to 0. C dif and sif are set with their respective layer id. if sif is different from dif, the dma controller is able to prefetch data and write hsmci simultaneously. p. program lli_b(n).dmac_cfgx memory lo cation for channel x with the following fields values: C fifocfg defines the watermark of the dmac channel fifo. C src_h2sel is set to true to enable hardware handshaking on the destination. C src_per is programmed with the hardware handshaking id of the targeted hsmci host controller
605 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 605 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 q. program lli_b(n).dmac_dscr with address of descriptor lli_w(n+1). if lli_b(n) is the last descriptor, then program lli_b(n).dmac_dscr with 0. r. program dmac_ctrlbx register for channel x with 0, its content is updated with the lli fetch operation. s. program dmac_dscrx with the address of lli_w(0) if block_length is greater than 4 else with address of lli_b(0). t. enable channel x writing one to dmac_c her[x]. the dmac is ready and waiting for request. 4. enable dmadone interrupt in the hsmci_ier register. 5. poll cbtc[x] bit in the dmac_ebcisr register. 6. if a new list of buffers shall be transferred, repeat step 7. check and handle hsmci errors. 7. poll fifoempty field in the hsmci_sr. 8. send the stop_transmission co mmand writing hsmci_arg then hsmci_cmdr. 9. wait for xfrdone in hsmci_sr register. 35.8.8.3 block length is not a multiple of 4. (ropt field in hsmci_dma register set to 1) one dma transfer descriptor is used to perform the hsmci block transfer, the dma writes a rounded up value to the nearest multiple of 4. 1. use the previous step to configure the hsmci to perform a read_multiple_block. 2. set the ropt field to 1 in the hsmci_dma register. 3. issue a read_multiple_block command. 4. program the dma controller to use a list of descriptors: a. read the channel register to choose an available (disabled) channel. b. clear any pending interrupts on the channel from the previous dmac transfer by reading the dmac_ebcisr register. c. program the channel registers in the memory with the first descriptor. this descrip- tor will be word oriented. this descriptor is referred to as lli_w(n ), standing for lli word oriented transfer for block n . d. the lli_w(n).dmac_saddrx field in memory must be set with the starting address of the hsmci_fifo address. e. the lli_w(n).dmac_daddrx field in the memory must be word aligned. f. program lli_w(n).dmac_ctrlax with the following fields values: Cdst_width is set to word. Csrc_width is set to word. Cscsize must be set according to the value of hsmci_dma, chksize field. Cbtsize is programmed with ceiling(block_length/4). g. program lli_w(n).dmac_ctrlbx with the following fields values: Cdst_incr is set to incr Csrc_incr is set to incr Cfc field is programmed with peripheral to memory flow control mode. Csrc_dscr is set to 0. (descrip tor fetch is enabled for the src) Cdst_dscr is set to true. (descriptor fetch is disabled for the dst)
606 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 606 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 Cdif and sif are set with their respective layer id. if sif is different from dif, the dma controller is able to prefetch data and write hsmci simultaneously. h. program lli_w(n).dmac_cfgx register for channel x with the following fields values: Cfifocfg defines the watermark of the dma channel fifo. Cdst_rep is set to zero. address are contiguous. Csrc_h2sel is set to true to enable hardware handshaking on the destination. Csrc_per is programmed with the hardware handshaking id of the targeted hsmci host controller. i. program lli_w(n).dmac_dscrx with the address of lli_w(n+1) descriptor. and set the dscrx_if to the ahb layer id. this operation actually links descriptors together. if lli_w(n) is the last descriptor then lli_w(n).dmac_dscrx points to 0. j. program dmac_ctrlbx register for channel x with 0. its content is updated with the lli fetch operation. k. program dmac_dscrx register for channel x with the address of lli_w(0). l. enable channel x writing one to dmac_c her[x]. the dmac is ready and waiting for request. 5. poll cbtc[x] bit in the dmac_ebcisr register. 6. if a new list of buffers shall be transferred repeat step 7. check and handle hsmci errors. 7. poll fifoempty field in the hsmci_sr. 8. send the stop_transmission command writing the hsmci_arg then the hsmci_cmdr. 9. wait for xfrdone in hsmci_sr register. 35.9 sd/sdio card operation the high speed multimedia card interface allows processing of sd memory (secure digital memory card) and sdio (sd input output) card commands. sd/sdio cards are based on the multi media card (mmc) format, but are physically slightly thicker and feature higher data transfer rates, a lock switch on the side to prevent accidental overwriting and security featur es. the physical form factor, pin assignment and data transfer protocol are forward-compatible with the high speed multimedia card with some additions. sd slots can actually be used for more than flash memory cards. devices that support sdio can use small devices designed for the sd form fact or, such as gps receivers, wi-fi or bluetooth adapters, modems, barcode readers, irda adapters, fm radio tuners, rfid readers, digital cam- eras and more. sd/sdio is covered by numerous patents and trademarks, and licensing is only available through the secure digital card association. the sd/sdio card communication is based on a 9-pin interface (clock, command, 4 x data and 3 x power lines). the communication protocol is defined as a part of this specification. the main difference between the sd/sdio card and t he high speed multimedia card is the initial- ization process. the sd/sdio card register (hsmci_sdcr) allows selection of the card slot and the data bus width.
607 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 607 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 the sd/sdio card bus allows dynamic configur ation of the number of data lines. after power up, by default, the sd/sdio card uses only dat0 for data transfer. after initialization, the host can change the bus width (number of active data lines). 35.9.1 sdio data transfer type sdio cards may transfer data in either a multi-byte (1 to 512 bytes) or an optional block format (1 to 511 blocks), while the sd memory cards are fixed in the block transfer mode. the trtyp field in the hsmci command register (hsmci_c mdr) allows to choose between sdio byte or sdio block transfer. the number of bytes/blocks to transfer is set through the bcnt field in the hsmci block regis- ter (hsmci_blkr). in sdio block mode, the field blklen must be set to the data block size while this field is not used in sdio byte mode. an sdio card can have multiple i/o or combined i/o and memo ry (called combo card). within a multi-function sdio or a combo card, there are multiple devices (i/o and memory) that share access to the sd bus. in order to allow the sharing of access to the host among multiple devices, sdio and combo cards can implement the optional concept of suspend/resume (refer to the sdio specification for more details). to send a suspend or a resume command, the host must set the sdio special command field (iospcmd) in the hsmci command register. 35.9.2 sdio interrupts each function within an sdio or combo card may implement interrupts (refer to the sdio specification for more details). in order to allow the sdio card to interrupt the host, an interrupt function is added to a pin on the dat[1] line to signal the cards interrupt to the host. an sdio interrupt on each slot can be enabled through the hsmci interrupt enable register. the sdio interrupt is sampled regardless of the currently selected slot. 35.10 ce-ata operation ce-ata maps the streamlined ata command set onto the mmc interface. the ata task file is mapped onto mmc register space. ce-ata utilizes five mmc commands: ? go_idle_state (cmd0): used for hard reset. ? stop_transmission (cmd12): causes the ata command currently executing to be aborted. ? fast_io (cmd39): used for single register access to the ata taskfile registers, 8 bit access only. ? rw_multiple_registers (cmd60): used to issue an ata command or to access the control/status registers. ? rw_multiple_block (cmd61): used to transfer data for an ata command. ce-ata utilizes the same mmc command s equences for initialization as traditional mmc devices. 35.10.1 executing an ata polling command 1. issue read_dma_ext with rw_multiple_ register (cmd60) for 8kb of data. 2. read the ata status register until drq is set. 3. issue rw_multiple_block (cmd61) to transfer data. 4. read the ata status register until drq && bsy are set to 0.
608 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 608 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35.10.2 executing an ata interrupt command 1. issue read_dma_ext with rw_multiple_ register (cmd60) for 8kb of data with nien field set to zero to enable the command completion signal in the device. 2. issue rw_multiple_block (cmd61) to transfer data. 3. wait for completion signal received interrupt. 35.10.3 aborting an ata command if the host needs to abort an ata command prior to the completion signal it must send a special command to avoid potential collision on t he command line. the spcmd field of the hsmci_cmdr must be set to 3 to issue the ce-ata completion signal disable command. 35.10.4 ce-ata error recovery several methods of ata command failure may occur, including: ? no response to an mmc command, such as rw_multiple_register (cmd60). ? crc is invalid for an mmc command or response. ? crc16 is invalid for an mmc data packet. ? ata status register reflects an error by setting the err bit to one. ? the command completion signal does not arrive within a host specified time out period. error conditions are expected to happen infreq uently. thus, a robust error recovery mechanism may be used for each error event. the recommended error recovery procedure after a timeout is: ? issue the command completion signal disable if nien was cleared to zero and the rw_multiple_block (cmd61) response has been received. ? issue stop_transmission (cmd12) and successfully receive the r1 response. ? issue a software reset to the ce-ata device using fast_io (cmd39). if stop_tranmission (cmd12) is successful , then the device is again ready for ata com- mands. however, if the error recovery procedure does not work as expected or there is another timeout, the next step is to issue go_idle_state (cmd0) to the device. go_idle_state (cmd0) is a hard reset to the device and completely resets all device states. note that after issuing go_idle_state (cmd0), a ll device initialization needs to be completed again. if the ce-ata device completes all mmc commands corr ectly but fails the ata command with the err bit set in the ata status register , no error recovery action is required. the ata command itself failed implying that the device could not complete the action requested, how- ever, there was no communication or protocol failu re. after the device signals an error by setting the err bit to one in the ata status register, the host may attempt to retry the command. 35.11 hsmci boot operation mode in boot operation mode, the processor can read boot data from the slave (mmc device) by keep- ing the cmd line low after power-on before issuing cmd1. the data can be read from either the boot area or user area, depending on register setting. boot procedure, processor mode 1. configure the hsmci data bus width programming sdcbus field in the hsmci_sdcr register. the boot_bus_width field located in the device extended csd register must be set accordingly. 2. set the byte count to 512 bytes and the block count to the desired number of blocks, writing blklen and bcnt fields of the hsmci_blkr register.
609 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 609 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 3. issue the boot operation request command by writing to the hsmci_cmdr register with spcmd field set to bootreq, trdir set to read and trcmd set to start data transfer. 4. the boot_ack field located in the hsmci_cmdr register must be set to one, if the boot_ack field of the mmc device located in the extended csd register is set to one. 5. host processor can copy boot data sequentially as soon as the rxrdy flag is asserted. 6. when data transfer is completed, host processor shall terminate the boot stream by writing the hsmci_cmdr register with spcmd field set to bootend. 35.11.1 boot procedure dma mode 1. configure the hsmci data bus width by programming sdcbus field in the hsmci_sdcr register. the boot_bus_width field in the device extended csd register must be set accordingly. 2. set the byte count to 512 bytes and the block count to the desired number of blocks by writing blklen and bcnt fields of the hsmci_blkr register. 3. enable dma transfer in the hsmci_dma register. 4. configure dma controller, program the total amount of data to be transferred and enable the relevant channel. 5. issue the boot operation request command by writing to the hsmci_cmdr register with spcnd set to bootreq, trdir set to read and trcmd set to start data transfer. 6. dma controller copies the boot partition to the memory. 7. when dma transfer is completed, host processor shall terminate the boot stream by writing the hsmci_cmdr register with spcmd field set to bootend.
610 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 610 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35.12 hsmci transfer done timings 35.12.1 definition the xfrdone flag in the hsmci_sr indicate s exactly when the read or write sequence is finished. 35.12.2 read access during a read access, the xfrdone flag behaves as shown in figure 35-11 . figure 35-11. xfrdone during a read access 35.12.3 write access during a write access, the xfrdone flag behaves as shown in figure 35-12 . figure 35-12. xfrdone during a write access cmd line hsmci read cmd card response cmdrdy flag data 1st block last block not busy flag xfrdone flag the cmdrdy flag is released 8 tbit after the end of the card response. cmd line card response cmdrdy flag data bus - d0 1st block not busy flag xfrdone flag the cmdrdy flag is released 8 tbit after the end of the card response. last block d0 1st block last block d0 is tied by the card d0 is released hsmci write cmd
611 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 611 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35.13 write protection registers to prevent any single software error that may corrupt hsmci behavior, the entire hsmci address space from address offset 0x000 to 0x00fc can be write-protected by setting the wpen bit in the hsmci write protect mode register (hsmci_wpmr). if a write access to anywhere in the hsmci add ress space from address offset 0x000 to 0x00fc is detected, then the wpvs flag in the hsmci write protect status register (hsmci_wpsr) is set and the field wpvsrc indicates in which register the write access has been attempted. the wpvs flag is reset by writing the hsmci write protect mode register (hsmci_wpmr) with the appropriate access key, wpkey. the protected registers are: ? hsmci mode register on page 614 ? hsmci data timeout register on page 616 ? hsmci sdcard/sdio register on page 617 ? hsmci completion signal timeout register on page 623 ? hsmci dma configuration register on page 636 ? hsmci configuration register on page 637
612 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 612 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35.14 high speed multimediacard in terface (hsmci) user interface note: 1. the response register can be read by n accesses at the same hsmci_rspr or at consecut ive addresses (0x20 to 0x2c). n depends on the size of the response. table 35-7. register mapping offset register name access reset 0x00 control register hsmci_cr write C 0x04 mode register hsmci_mr read-write 0x0 0x08 data timeout register hsmci_dtor read-write 0x0 0x0c sd/sdio card register hsmci_sdcr read-write 0x0 0x10 argument register hsmci_argr read-write 0x0 0x14 command register hsmci_cmdr write C 0x18 block register hsmci_blkr read-write 0x0 0x1c completion signal timeout register hsmci_cstor read-write 0x0 0x20 response register (1) hsmci_rspr read 0x0 0x24 response register (1) hsmci_rspr read 0x0 0x28 response register (1) hsmci_rspr read 0x0 0x2c response register (1) hsmci_rspr read 0x0 0x30 receive data register hsmci_rdr read 0x0 0x34 transmit data register hsmci_tdr write C 0x38 - 0x3c reserved C C C 0x40 status register hsmci_sr read 0xc0e5 0x44 interrupt enable register hsmci_ier write C 0x48 interrupt disable register hsmci_idr write C 0x4c interrupt mask register hsmci_imr read 0x0 0x50 dma configuration register hsmci_dma read-write 0x00 0x54 configuration register hsmci_cfg read-write 0x00 0x58-0xe0 reserved C C C 0xe4 write protection mode register hsmci_wpmr read-write C 0xe8 write protection status register hsmci_wpsr read-only C 0xec - 0xfc reserved C C C 0x100-0x1fc reserved C C C 0x200 fifo memory aperture0 hsmci_fifo0 read-write 0x0 ... ... ... ... ... 0x5fc fifo memory aperture255 hsmci_fifo255 read-write 0x0
613 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 613 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35.14.1 hsmci control register name: hsmci_cr address: 0xf0008000 access: write-only ? mcien: multi-media interface enable 0 = no effect. 1 = enables the multi-media interface if mcdis is 0. ? mcidis: multi-media interface disable 0 = no effect. 1 = disables the multi-media interface. ? pwsen: power save mode enable 0 = no effect. 1 = enables the power saving mode if pwsdis is 0. warning: before enabling this mode, the user must set a value different from 0 in the pwsdiv field (mode register, hsmci_mr). ? pwsdis: power save mode disable 0 = no effect. 1 = disables the power saving mode. ? swrst: software reset 0 = no effect. 1 = resets the hsmci. a software triggered hardwa re reset of the hsmci interface is performed. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 swrst C C C pwsdis pwsen mcidis mcien
614 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 614 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35.14.2 hsmci mode register name: hsmci_mr address: 0xf0008004 access: read-write this register can only be written if the wpen bit is cleared in hsmci write protect mode register on page 638 . ? clkdiv: clock divider high speed multimedia card inte rface clock (mcck or hsmci_ck) is master clock (mck) divider by ({clkdiv,clkodd}+2). ? pwsdiv: power saving divider high speed multimedia card interface clock is divided by 2 (pwsdiv) + 1 when entering power saving mode. warning: this value must be different from 0 before enabling the power save mode in the hsmci_cr (hsmci_pwsen bit). ? rdproof read proof enable enabling read proof allows to stop the hs mci clock during read access if the internal fifo is full. this will guarantee data integrity, no t bandwidth. 0 = disables read proof. 1 = enables read proof. ? wrproof write proof enable enabling write proof allows to st op the hsmci clock during write access if the internal fifo is full. this will guarantee data integrity, no t bandwidth. 0 = disables write proof. 1 = enables write proof. ? fbyte: force byte transfer enabling force byte transfer allow byte transfers, so that transfer of blocks with a size different from modulo 4 can be supported. warning: blklen value depends on fbyte. 0 = disables force byte transfer. 1 = enables force byte transfer. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCc l k o d d 15 14 13 12 11 10 9 8 C padv fbyte wrproof rdproof pwsdiv 76543210 clkdiv
615 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 615 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? padv: padding value 0 = 0x00 value is used when padding data in write transfer. 1 = 0xff value is used when padding data in write transfer. padv may be only in manual transfer. ? clkodd: clock divider is odd this field is the least significant bit of the clock divider and indicates the clock divider parity.
616 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 616 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35.14.3 hsmci data timeout register name: hsmci_dtor address: 0xf0008008 access: read-write this register can only be written if the wpen bit is cleared in hsmci write protect mode register on page 638 . ? dtocyc: data timeout cycle number these fields determine the maximum numb er of master clock cycles that the hsmci waits between two data block trans- fers. it equals (dtocyc x multiplier). ? dtomul: data timeout multiplier multiplier is defined by dtomul as shown in the following table: if the data time-out set by dtocyc and dtomul has been exceeded, the data time-out error flag (dtoe) in the hsmci status register (hsmci_sr) rises. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 C dtomul dtocyc value name description 01 d t o c y c 1 16 dtocyc x 16 2 128 dtocyc x 128 3 256 dtocyc x 256 4 1024 dtocyc x 1024 5 4096 dtocyc x 4096 6 65536 dtocyc x 65536 7 1048576 dtocyc x 1048576
617 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 617 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35.14.4 hsmci sdcard/sdio register name: hsmci_sdcr address: 0xf000800c access: read-write this register can only be written if the wpen bit is cleared in hsmci write protect mode register on page 638 . ? sdcsel: sdcard/sdio slot ? sdcbus: sdcard/sdio bus width 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 s d c b u s CCCC s d c s e l value name description 0s l o t a slot a is selected . 1slotbC 2slotcC 3slotdC value name description 01 1 bit 1C reserved 244 b i t 388 b i t
618 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 618 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35.14.5 hsmci argument register name: hsmci_argr address: 0xf0008010 access: read-write ? arg: command argument 31 30 29 28 27 26 25 24 arg 23 22 21 20 19 18 17 16 arg 15 14 13 12 11 10 9 8 arg 76543210 arg
619 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 619 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35.14.6 hsmci command register name: hsmci_cmdr address: 0xf0008014 access: write-only this register is write-protected while cm drdy is 0 in hsmci_sr. if an interrupt command is sent, this register is only writeable by an interrupt response (field spcmd). this means that the current command execution cannot be interrupted or modified. ? cmdnb: command number this is the command index. ? rsptyp: response type ? spcmd: special command 31 30 29 28 27 26 25 24 CCCCb o o t _ a c ka t a c s i o s p c m d 23 22 21 20 19 18 17 16 C C trtyp trdir trcmd 15 14 13 12 11 10 9 8 C C C maxlat opdcmd spcmd 76543210 rsptyp cmdnb value name description 0 noresp no response. 1 48_bit 48-bit response. 2 136_bit 136-bit response. 3 r1b r1b response type value name description 0 std not a special cmd. 1i n i t initialization cmd: 74 clock cycles for initialization sequence. 2 sync synchronized cmd: wait for the end of the current data block transfer before sending the pending command. 3c e _ a t a ce-ata completion signal disable command. the host cancels the ability for the device to return a command completion signal on the command line. 4i t _ c m d interrupt command: corresponds to the interrupt mode (cmd40).
620 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 620 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? opdcmd: open drain command 0 (pushpull) = push pull command. 1 (opendrain) = open drain command. ? maxlat: max latency for command to response 0 (5) = 5-cycle max latency. 1 (64) = 64-cycle max latency. ? trcmd: transfer command ? trdir: transfer direction 0 (write) = write. 1 (read) = read. ? trtyp: transfer type ? iospcmd: sdio special command 5 it_resp interrupt response: corresponds to the interrupt mode (cmd40). 6b o r boot operation request. start a boot operation mode, the host processor can re ad boot data from the mmc device directly. 7e b o end boot operation. this command allows the host processor to terminate the boot operation mode. value name description 0 no_data no data transfer 1 start_data start data transfer 2 stop_data stop data transfer 3Cr e s e r v e d value name description 0 single mmc/sdcard single block 1 multiple mmc/sdcard multiple block 2 stream mmc stream 4 byte sdio byte 5 block sdio block value name description 0 std not an sdio special command 1 suspend sdio suspend command 2 resume sdio resume command value name description
621 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 621 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? atacs: ata with command completion signal 0 (normal) = normal operation mode. 1 (completion) = this bit indicates that a completion signal is expected within a programmed amount of time (hsmci_cstor). ? boot_ack: boot operation acknowledge. the master can choose to receive the boot acknowledge fr om the slave when a boot request command is issued. when set to one this field indicates that a boot acknowledge is expected within a programmabl e amount of time defined with dtomul and dtocyc fields located in the hsmci_dtor r egister. if the acknowledge pattern is not received then an acknowledge timeout error is raised. if the acknowledge patt ern is corrupted then an acknowledge pattern error is set.
622 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 622 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35.14.7 hsmci block register name: hsmci_blkr address: 0xf0008018 access: read-write ? bcnt: mmc/sdio block count - sdio byte count this field determines the number of data byte(s) or block(s) to transfer. the transfer data type and the authorized values for bcnt field are determined by the tr typ field in the hsmci com- mand register (hsmci_cmdr): warning: in sdio byte and block modes, writing to the 7 last bits of bcnt field is forbidden and may lead to unpredictable results. ? blklen: data block length this field determines the size of the data block. this field is also accessible in the hsmci mode register (hsmci_mr). bits 16 and 17 must be set to 0 if fbyte is disabled. note: in sdio byte mode, blklen field is not used. 31 30 29 28 27 26 25 24 blklen 23 22 21 20 19 18 17 16 blklen 15 14 13 12 11 10 9 8 bcnt 76543210 bcnt value name description 0multiple mmc/sdcard multiple block from 1 to 65635: value 0 corresponds to an infinite block transfer. 4 byte sdio byte from 1 to 512 bytes: value 0 corresponds to a 512-byte transfer. values from 0x200 to 0xffff are forbidden. 5block sdio block from 1 to 511 blocks: value 0 corresponds to an infinite block transfer. values from 0x200 to 0xffff are forbidden.
623 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 623 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35.14.8 hsmci completion signal timeout register name: hsmci_cstor address: 0xf000801c access: read-write this register can only be written if the wpen bit is cleared in hsmci write protect mode register on page 638 . ? cstocyc: completion signal timeout cycle number these fields determine the maximum numb er of master clock cycles that the hsmci waits between two data block trans- fers. its value is calculated by (cstocyc x multiplier). ? cstomul: completion signal timeout multiplier these fields determine the maximum numb er of master clock cycles that the hsmci waits between two data block trans- fers. its value is calculated by (cstocyc x multiplier). these fields determine the maximum number of master clock cycles that the hsmci waits between the end of the data transfer and the assertion of the completion signal. the data transfer comprises data phase and the optional busy phase. if a non-data ata command is issued, the hsmci starts waiting immediately after the end of the response until the comple- tion signal. multiplier is defined by cstomul as shown in the following table: if the data time-out set by cstocyc and cstomul has b een exceeded, the completion signal time-out error flag (cstoe) in the hsmci status register (hsmci_sr) rises. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 C cstomul cstocyc value name description 0 1 cstocyc x 1 1 16 cstocyc x 16 2 128 cstocyc x 128 3 256 cstocyc x 256 4 1024 cstocyc x 1024 5 4096 cstocyc x 4096 6 65536 cstocyc x 65536 7 1048576 cstocyc x 1048576
624 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 624 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35.14.9 hsmci response register name: hsmci_rspr address: 0xf0008020 access: read-only ? rsp: response note: 1. the response register can be read by n accesses at the same hsmci_rspr or at consecut ive addresses (0x20 to 0x2c). n depends on the size of the response. 35.14.10 hsmci receive data register name: hsmci_rdr address: 0xf0008030 access: read-only ? data: data to read 31 30 29 28 27 26 25 24 rsp 23 22 21 20 19 18 17 16 rsp 15 14 13 12 11 10 9 8 rsp 76543210 rsp 31 30 29 28 27 26 25 24 data 23 22 21 20 19 18 17 16 data 15 14 13 12 11 10 9 8 data 76543210 data
625 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 625 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35.14.11 hsmci transmit data register name: hsmci_tdr address: 0xf0008034 access: write-only ? data: data to write 31 30 29 28 27 26 25 24 data 23 22 21 20 19 18 17 16 data 15 14 13 12 11 10 9 8 data 76543210 data
626 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 626 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35.14.12 hsmci status register name: hsmci_sr address: 0xf0008040 access: read-only ? cmdrdy: command ready 0 = a command is in progress. 1 = the last command has been sent. cleared when writing in the hsmci_cmdr. ? rxrdy: receiver ready 0 = data has not yet been received since the last read of hsmci_rdr. 1 = data has been received since the last read of hsmci_rdr. ? txrdy: transmit ready 0= the last data written in hsmci_tdr has not yet been transferred in the shift register. 1= the last data written in hsmci_tdr has been transferred in the shift register. ? blke: data block ended this flag must be used only for write operations. 0 = a data block transfer is not yet finished. cleared when reading the hsmci_sr. 1 = a data block transfer has ended, including the crc16 status transmission. the flag is set for each transmitted crc status. refer to the mmc or sd sp ecification for more details concerning the crc status. ? dtip: data transfer in progress 0 = no data transfer in progress. 1 = the current data tran sfer is still in progress, including crc16 calculatio n. cleared at the end of the crc16 calculation. ? notbusy: hsmci not busy a block write operation uses a simple busy signalling of the write operat ion duration on the data (dat0) line: during a data transfer block, if the card does not have a free data receive buffer, the card indicates this condition by pulling down the dat a line (dat0) to low. the card stops pulling down the data line as soon as at least one receive buffer for the defined data transfer block length becomes free. the notbusy flag allows to deal with these different states. 0 = the hsmci is not ready for new data transfer. cleared at the end of the card response. 31 30 29 28 27 26 25 24 unre ovre ackrcve ackrcv xfrdone fifoempty dmadone blkovre 23 22 21 20 19 18 17 16 cstoe dtoe dcrce rtoe rende rcrce rdire rinde 15 14 13 12 11 10 9 8 C C csrcv sdiowait C C C sdioirqa 76543210 C C notbusy dtip blke txrdy rxrdy cmdrdy
627 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 627 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1 = the hsmci is ready for new data transfer. set when the busy state on the data line has ended. this corresponds to a free internal data receive buffer of the card. refer to the mmc or sd specification for more details concerning the busy behavior. for all the read operations, the notbusy flag is cleared at the end of the host command. for the infinite read multiple blocks, the notbusy flag is set at the end of the st op_transmission host command (cmd12). for the single block reads, the notbusy flag is set at the end of the data read block. for the multiple block reads with pre-defined block count, the notbusy flag is set at the end of the last received data block. ? sdioirqa: sdio interrupt for slot a 0 = no interrupt detected on sdio slot a. 1 = an sdio interrupt on slot a occurred. cleared when reading the hsmci_sr. ? sdiowait: sdio read wait operation status 0 = normal bus operation. 1 = the data bus has entered io wait state. ? csrcv: ce-ata comple tion signal received 0 = no completion signal received since last status read operation. 1 = the device has issued a command completion signal on the command line. cleared by reading in the hsmci_sr register. ? rinde: response index error 0 = no error. 1 = a mismatch is detected between the command index sent and the response index received. cleared when writing in the hsmci_cmdr. ? rdire: response direction error 0 = no error. 1 = the direction bit from card to host in the response has not been detected. ? rcrce: response crc error 0 = no error. 1 = a crc7 error has been detected in the response. cleared when writing in the hsmci_cmdr. ? rende: response end bit error 0 = no error. 1 = the end bit of the response has not been detected. cleared when writing in the hsmci_cmdr. ? rtoe: response time-out error 0 = no error. 1 = the response time-out set by maxlat in the hs mci_cmdr has been exceeded. cleared when writing in the hsmci_cmdr.
628 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 628 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? dcrce: data crc error 0 = no error. 1 = a crc16 error has been detected in the last data block. cleared by reading in the hsmci_sr register. ? dtoe: data time-out error 0 = no error. 1 = the data time-out set by dtocyc and dtomul in hsmci_dtor has been exceeded. cleared by reading in the hsmci_sr register. ? cstoe: completion signal time-out error 0 = no error. 1 = the completion signal time-out set by cstocyc an d cstomul in hsmci_cstor has been exceeded. cleared by reading in the hsmci_sr register. cleared by reading in the hsmci_sr register. ? blkovre: dma block overrun error 0 = no error. 1 = a new block of data is received and the dma controller has not started to move the current pending block, a block over- run is raised. cleared by read ing in the hsmci_sr register. ? dmadone: dma transfer done 0 = dma buffer transfer has not completed since the last read of hsmci_sr register. 1 = dma buffer transfer has completed. ? fifoempty: fifo empty flag 0 = fifo contains at least one byte. 1 = fifo is empty. ? xfrdone: transfer done flag 0 = a transfer is in progress. 1 = command register is ready to operate and the data bus is in the idle state. ? ackrcv: boot operatio n acknowledge received 0 = no boot acknowledge received since the last read of the status register. 1 = a boot acknowledge signal has been received. cleared by reading the hsmci_sr register. ? ackrcve: boot operation acknowledge error 0 = no error 1 = corrupted boot acknowledge signal received. ? ovre: overrun 0 = no error. 1 = at least one 8-bit received data has been lost (not read). cleared when sending a new data transfer command. when ferrctrl in hsmci_cfg is set to 1, ovre becomes reset after read.
629 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 629 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? unre: underrun 0 = no error. 1 = at least one 8-bit data has been sent without valid information (not written). cleared when sending a new data transfer command or when setting ferrctrl in hsmci_cfg to 1 . when ferrctrl in hsmci_cfg is set to 1, unre becomes reset after read.
630 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 630 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35.14.13 hsmci interrupt enable register name: hsmci_ier address: 0xf0008044 access: write-only ? cmdrdy: command ready interrupt enable ? rxrdy: receiver ready interrupt enable ? txrdy: transmit ready interrupt enable ? blke: data block ended interrupt enable ? dtip: data transfer in progress interrupt enable ? notbusy: data not busy interrupt enable ? sdioirqa: sdio interrupt for slot a interrupt enable ? sdioirqd: sdio interrupt for slot d interrupt enable ? sdiowait: sdio read wait operation status interrupt enable ? csrcv: completion signal received interrupt enable ? rinde: response index error interrupt enable ? rdire: response direction error interrupt enable ? rcrce: response crc error interrupt enable ? rende: response end bit error interrupt enable ? rtoe: response time-out error interrupt enable ? dcrce: data crc error interrupt enable ? dtoe: data time-out error interrupt enable ? cstoe: completion signal timeout error interrupt enable ? blkovre: dma block overrun error interrupt enable 31 30 29 28 27 26 25 24 unre ovre ackrcve ackrcv xfrdone fifoempty dmadone blkovre 23 22 21 20 19 18 17 16 cstoe dtoe dcrce rtoe rende rcrce rdire rinde 15 14 13 12 11 10 9 8 C C csrcv sdiowait C C C sdioirqa 76543210 C C notbusy dtip blke txrdy rxrdy cmdrdy
631 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 631 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? dmadone: dma transfer completed interrupt enable ? fifoempty: fifo empty interrupt enable ? xfrdone: transfer done interrupt enable ? ackrcv: boot acknowle dge interrupt enable ? ackrcve: boot acknowledge error interrupt enable ? ovre: overrun interrupt enable ? unre: underrun interrupt enable 0 = no effect. 1 = enables the corresponding interrupt.
632 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 632 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35.14.14 hsmci interrupt disable register name: hsmci_idr address: 0xf0008048 access: write-only ? cmdrdy: command ready interrupt disable ? rxrdy: receiver ready interrupt disable ? txrdy: transmit ready interrupt disable ? blke: data block ended interrupt disable ? dtip: data transfer in progress interrupt disable ? notbusy: data not busy interrupt disable ? sdioirqa: sdio interrupt for slot a interrupt disable ? sdiowait: sdio read wait operation status interrupt disable ? csrcv: completion signal received interrupt disable ? rinde: response index error interrupt disable ? rdire: response direction error interrupt disable ? rcrce: response crc error interrupt disable ? rende: response end bit error interrupt disable ? rtoe: response time-out error interrupt disable ? dcrce: data crc error interrupt disable ? dtoe: data time-out error interrupt disable ? cstoe: completion signal time out error interrupt disable ? blkovre: dma block overrun error interrupt disable ? dmadone: dma transfer co mpleted interrupt disable 31 30 29 28 27 26 25 24 unre ovre ackrcve ackrcv xfrdone fifoempty dmadone blkovre 23 22 21 20 19 18 17 16 cstoe dtoe dcrce rtoe rende rcrce rdire rinde 15 14 13 12 11 10 9 8 C C csrcv sdiowait C C C sdioirqa 76543210 C C notbusy dtip blke txrdy rxrdy cmdrdy
633 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 633 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? fifoempty: fifo empty interrupt disable ? xfrdone: transfer done interrupt disable ? ackrcv: boot acknowle dge interrupt disable ? ackrcve: boot acknowledge error interrupt disable ? ovre: overrun interrupt disable ? unre: underrun in terrupt disable 0 = no effect. 1 = disables the corresponding interrupt.
634 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 634 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35.14.15 hsmci interrupt mask register name: hsmci_imr address: 0xf000804c access: read-only ? cmdrdy: command ready interrupt mask ? rxrdy: receiver ready interrupt mask ? txrdy: transmit ready interrupt mask ? blke: data block ended interrupt mask ? dtip: data transfer in progress interrupt mask ? notbusy: data not busy interrupt mask ? sdioirqa: sdio interrupt for slot a interrupt mask ? sdiowait: sdio read wait operation status interrupt mask ? csrcv: completion signal received interrupt mask ? rinde: response index error interrupt mask ? rdire: response direction error interrupt mask ? rcrce: response crc error interrupt mask ? rende: response end bit error interrupt mask ? rtoe: response time-out error interrupt mask ? dcrce: data crc error interrupt mask ? dtoe: data time-out error interrupt mask ? cstoe: completion signal time-out error interrupt mask ? blkovre: dma block overrun error interrupt mask ? dmadone: dma transfer completed interrupt mask 31 30 29 28 27 26 25 24 unre ovre ackrcve ackrcv xfrdone fifoempty dmadone blkovre 23 22 21 20 19 18 17 16 cstoe dtoe dcrce rtoe rende rcrce rdire rinde 15 14 13 12 11 10 9 8 C C csrcv sdiowait C C C sdioirqa 76543210 C C notbusy dtip blke txrdy rxrdy cmdrdy
635 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 635 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? fifoempty: fifo empty interrupt mask ? xfrdone: transfer done interrupt mask ? ackrcv: boot operation acknow ledge received interrupt mask ? ackrcve: boot operation acknowledge error interrupt mask ? ovre: overrun interrupt mask ? unre: underrun interrupt mask 0 = the corresponding interrupt is not enabled. 1 = the corresponding interrupt is enabled.
636 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 636 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35.14.16 hsmci dma co nfiguration register name: hsmci_dma address: 0xf0008050 access: read-write this register can only be written if the wpen bit is cleared in hsmci write protect mode register on page 638 . ? offset: dma write buffer offset this field indicates the number of discarded bytes when the dma writes the first word of the transfer. ? chksize: dma channel read and write chunk size the chksize field indicates the number of data available when the dma chunk transfer request is asserted. ? dmaen: dma hardware handshaking enable 0 = dma interface is disabled. 1 = dma interface is enabled. note: to avoid unpredictable behavior, dma hardware handshak ing must be disabled when cpu transfers are performed. ? ropt: read optimization with padding 0: blklen bytes are moved from the memory card to the system memory, two dma descriptors are used when the trans- fer size is not a multiple of 4. 1: ceiling(blklen/4) * 4 bytes are moved from the memory card to the system me mory, only one dma descriptor is used. 31 30 29 28 27 26 25 24 CCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCr o p tCCCd m a e n 76543210 C C chksize C C offset value name description 00 1 1 data available 01 4 4 data available 10 8 8 data available 11 16 16 data available
637 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 637 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35.14.17 hsmci configuration register name: hsmci_cfg address: 0xf0008054 access: read-write this register can only be written if the wpen bit is cleared in hsmci write protect mode register on page 638 . ? fifomode: hsmci internal fifo control mode 0 = a write transfer starts when a sufficient amount of data is written into the fifo. when the block length is greater than or equal to 3/4 of the hsmci internal fifo size, then the write transfer starts as soon as half the fifo is filled. when the block length is greater than or equal to half the internal fifo size, then the write trans fer starts as soon as one quarter of the fifo is filled. in other cases, th e transfer starts as soon as the total amount of data is written in the internal fifo. 1 = a write transfer starts as soon as one data is written into the fifo. ? ferrctrl: flow error flag reset control mode 0= when an underflow/overflow condition flag is set, a new write/read command is needed to reset the flag. 1= when an underflow/overflow condition fl ag is set, a read status resets the flag. ? hsmode: high speed mode 0= default bus timing mode. 1= if set to one, the host controller outputs command line and data lines on the rising edge of the card clock. the host driver shall check the high speed support in the card registers. ? lsync: synchronize on the last block 0= the pending command is sent at the end of the current data block. 1= the pending command is sent at the end of the block transf er when the transfer length is not infinite. (block count shall be different from zero) 31 30 29 28 27 26 25 24 CCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCl s y n cCCCh s m o d e 76543210 C C C ferrctrl C C C fifomode
638 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 638 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35.14.18 hsmci write protect mode register name: hsmci_wpmr address: 0xf00080e4 access: read-write ? wp_en: write protection enable 0 = disables the write protection if wp_key corresponds to 0x4d4349 (mci in ascii). 1 = enables the write protection if wp_key corresponds to 0x4d4349 (mci in ascii). ? wp_key: write protection key password should be written at value 0x4d4349 (ascii code for mci). writing any other value in this field has no effect. protects the registers: ? hsmci mode register on page 614 ? hsmci data timeout register on page 616 ? hsmci sdcard/sdio re gister on page 617 ? hsmci completion signal timeout register on page 623 ? hsmci dma configuration register on page 636 ? hsmci configuration register on page 637 31 30 29 28 27 26 25 24 wp_key (0x4d => m) 23 22 21 20 19 18 17 16 wp_key (0x43 => c) 15 14 13 12 11 10 9 8 wp_key (0x49 => i) 76543210 wp_en
639 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 639 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35.14.19 hsmci write protect status register name: hsmci_wpsr address: 0xf00080e8 access: read-only ? wp_vs: write protect ion violation status ? wp_vsrc: write protection violation source when wpvs is active, this field indicates the write-protected register (t hrough address offset or code) in which a write access has been attempted. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 wp_vsrc 15 14 13 12 11 10 9 8 wp_vsrc 76543210 CCCC w p _ v s value name description 0n o n e no write protection violation occu rred since the last read of this register (wp_sr) 1w r i t e write protection detected unauthorized attempt to write a control register had occurred (since the last read.) 2 reset software reset had been performed while write protection was enabled (since the last read). 3b o t h both write protection violation and software reset with write protection enabled have occu rred since the last read.
640 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 640 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35.14.20 hsmci fifox memory aperture name: hsmci_fifox[x=0..255] address: 0xf0008200 access: read-write ? data: data to read or data to write 31 30 29 28 27 26 25 24 data 23 22 21 20 19 18 17 16 data 15 14 13 12 11 10 9 8 data 76543210 data
641 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 641 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 36. serial peripheral interface (spi) 36.1 description the serial peripheral interface (spi) circuit is a synchronous serial data link that provides com- munication with external devices in master or slave mode. it also enables communication between processors if an external processor is connected to the system. the serial peripheral interface is essentially a shift register that serially transmits data bits to other spis. during a data transfer, one spi syste m acts as the master' which controls the data flow, while the other devices act as slaves'' whic h have data shifted into and out by the master. different cpus can take turn being masters (multiple master protocol opposite to single master protocol where one cpu is always the master while all of the others are always slaves) and one master may simultaneously shift da ta into multiple slaves. howeve r, only one slave may drive its output to write data back to the master at any given time. a slave device is selected when the master asse rts its nss signal. if multiple slave devices exist, the master generates a separate slav e select signal for each slave (npcs). the spi system consists of two data lines and two control lines: ? master out slave in (mosi): this data line supplies the output data from the master shifted into the input(s) of the slave(s). ? master in slave out (miso): this data line supplies the output data from a slave to the input of the master. there may be no more than one slave transmitting data during any particular transfer. ? serial clock (spck): this control line is driven by the master and regulates the flow of the data bits. the master may transmit data at a variety of baud rates; the spck line cycles once for each bit that is transmitted. ? slave select (nss): this control line allows slaves to be turned on and off by hardware. 36.2 embedded characteristics ? compatible with an embedded 32-bit microcontroller ? supports communication with serial external devices C four chip selects with external decoder support allow communication with up to 15 peripherals C serial memories, such as dataflash and 3-wire eeproms C serial peripherals, such as adcs, da cs, lcd controllers, can controllers and sensors C external co-processors ? master or slave serial peripheral bus interface C 8- to 16-bit programmable da ta length per chip select C programmable phase and polarity per chip select C programmable transfer delays between consecutive transfers and between clock and data per chip select C programmable delay between consecutive transfers C selectable mode fault detection ? connection to dma channel capab ilities optimizes data transfers C one channel for the receiver, one channel for the transmitter
642 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 642 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 36.3 block diagram figure 36-1. block diagram spi interface interrupt control pio peripher a l bridge dma ch. ahb ma trix pmc mck spi interrupt spck miso mosi npcs0/nss npcs1 npcs2 npcs3 apb
643 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 643 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 36.4 application block diagram figure 36-2. application block diagram: single master/multiple slave implementation 36.5 signal description table 36-1. signal description pin name pin description type master slave miso master in slave out input output mosi master out slave in output input spck serial clock output input npcs1-npcs3 peripheral chip selects output unused npcs0/nss peripheral chip select/slave select output input spi master spck miso mosi npcs0 npcs1 npcs2 spck miso mosi nss slave 0 spck miso mosi nss slave 1 spck miso mosi nss slave 2 nc npcs3
644 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 644 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 36.6 product dependencies 36.6.1 i/o lines the pins used for interfacing the compliant ex ternal devices may be multiplexed with pio lines. the programmer must first program the pio controllers to assign the spi pins to their peripheral functions. 36.6.2 power management the spi may be clocked through the power management controller (pmc), thus the program- mer must first configure the pmc to enable the spi clock. 36.6.3 interrupt the spi interface has an interrupt line connected to the interrupt controller. handling the spi interrupt requires programming the interrupt controller before configuring the spi. table 36-2. i/o lines instance signal i/o line peripheral spi0 spi0_miso pa11 a spi0 spi0_mosi pa12 a spi0 spi0_npcs0 pa14 a spi0 spi0_npcs1 pa7 b spi0 spi0_npcs2 pa1 b spi0 spi0_npcs3 pb3 b spi0 spi0_spck pa13 a spi1 spi1_miso pa21 b spi1 spi1_mosi pa22 b spi1 spi1_npcs0 pa8 b spi1 spi1_npcs1 pa0 b spi1 spi1_npcs2 pa31 b spi1 spi1_npcs3 pa30 b spi1 spi1_spck pa23 b table 36-3. peripheral ids instance id spi0 13 spi1 14
645 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 645 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 36.7 functional description 36.7.1 modes of operation the spi operates in master mode or in slave mode. operation in master mode is programmed by writing at 1 the mstr bit in the mode register. the pins npcs0 to npcs3 are all configured as outputs, the spck pin is driven, the miso line is wired on the receiver input and the mosi line driven as an output by the transmitter. if the mstr bit is written at 0, the spi operates in slave mode. the miso line is driven by the transmitter output, the mosi line is wired on the re ceiver input, the spck pin is driven by the transmitter to synchronize the receiver. the npcs0 pin becomes an input, and is used as a slave select signal (nss). the pins npcs1 to npcs3 are not driven and can be used for other purposes. the data transfers are identically programmable for both modes of operations. the baud rate generator is activated only in master mode. 36.7.2 data transfer four combinations of polarity and phase are available for data transfers. the clock polarity is programmed with the cpol bit in the chip select register. the clock phase is programmed with the ncpha bit. these two parameters determine the edges of the clock signal on which data is driven and sampled. each of the two parameters has two possible states, resulting in four possi- ble combinations that are incompatible with one another. thus, a master/slave pair must use the same parameter pair values to communicate. if multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a dif- ferent slave. table 36-4 shows the four modes and corresponding parameter settings. figure 36-3 and figure 36-4 show examples of data transfers. table 36-4. spi bus protocol mode spi mode cpol ncpha shift spck edge capt ure spck edge spck inactive level 0 0 1 falling rising low 1 0 0 rising falling low 2 1 1 rising falling high 3 1 0 falling rising high
646 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 646 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 36-3. spi transfer format (ncpha = 1, 8 bits per transfer) figure 36-4. spi transfer format (ncpha = 0, 8 bits per transfer) 6 * spck (cpol = 0) spck (cpol = 1) mosi (from master) miso (from slave) nss (to slave) spck cycle (for reference) msb msb lsb lsb 6 6 5 5 4 4 3 3 2 2 1 1 * not defined, but normally msb of previous character received. 1 2345 78 6 * spck (cpol = 0) spck (cpol = 1) 1 2345 7 mosi (from master) miso (from slave) nss (to slave) spck cycle (for reference) 8 msb msb lsb lsb 6 6 5 5 4 4 3 3 1 1 * not defined but normally lsb of previous character transmitted. 2 2 6
647 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 647 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 36.7.3 master mode operations when configured in master mode, the spi operates on the clock generated by the internal pro- grammable baud rate generator. it fully controls the data transfers to and from the slave(s) connected to the spi bus. the spi drives the chip select line to the slave and the serial clock signal (spck). the spi features two holding registers, the transmit data register and the receive data regis- ter, and a single shift register. the holding registers maintain the data flow at a constant rate. after enabling the spi, a data transfer begins when the processor writes to the spi_tdr (trans- mit data register). the written data is immediat ely transferred in the shift register and transfer on the spi bus starts. while the data in the shift register is shifted on the mosi line, the miso line is sampled and shifted in the shift register. receiving data cannot occur without transmit- ting data. if receiving mode is not needed, for example when communicating with a slave receiver only (such as an lcd), the receive status flags in the status register can be discarded. before writing the tdr, the pcs field in the spi_mr register must be set in order to select a slave. after enabling the spi, a data transfer begins when the processor writes to the spi_tdr (trans- mit data register). the written data is immediat ely transferred in the shift register and transfer on the spi bus starts. while the data in the shift register is shifted on the mosi line, the miso line is sampled and shifted in the shift register. transmission cannot occur without reception. before writing the tdr, the pcs field must be set in order to select a slave. if new data is written in spi_tdr during the transfer, it stays in it until the current transfer is completed. then, the received data is transferred from the shift register to spi_rdr, the data in spi_tdr is loaded in the shift register and a new transfer starts. the transfer of a data written in spi_tdr in t he shift register is indicated by the tdre bit (transmit data register empty) in the status register (spi_sr). when new data is written in spi_tdr, this bit is cleared. the tdre bit is used to trigger the transmit dma channel. the end of transfer is indicated by the txempty flag in the spi_sr register. if a transfer delay (dlybct) is greater than 0 for the last transfer, txempty is set after the completion of said delay. the master clock (mck) can be switched off at this time. the transfer of received data from the shift register in spi_rdr is indicated by the rdrf bit (receive data register full) in the status register (spi_sr). when the received data is read, the rdrf bit is cleared. if the spi_rdr (receive data register) has not been read before new data is received, the overrun error bit (ovres) in spi_sr is set. as long as this flag is set, data is loaded in spi_rdr. the user has to read the status register to clear the ovres bit. figure 36-5 , shows a block diagram of the spi when operating in master mode. figure 36-6 on page 649 shows a flow chart describing how transfers are handled.
648 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 648 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 36.7.3.1 master mode block diagram figure 36-5. master mode block diagram shift register spck mosi lsb msb miso spi_rdr rd spi clock tdre spi_tdr td rdrf ovres spi_csr0..3 cpol ncpha bits mck baud rate generator spi_csr0..3 scbr npcs3 npcs0 npcs2 npcs1 npcs0 0 1 ps spi_mr pcs spi_tdr pcs modf current peripheral spi_rdr pcs spi_csr0..3 csaat pcsdec modfdis mstr
649 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 649 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 36.7.3.2 master mode flow diagram figure 36-6. master mode flow diagram spi enable csaat ? ps ? 1 0 0 1 1 npcs = spi_tdr(pcs) npcs = spi_mr(pcs) delay dlybs serializer = spi_tdr(td) tdre = 1 data transfer spi_rdr(rd) = serializer rdrf = 1 tdre ? npcs = 0xf delay dlybcs fixed peripheral variable peripheral delay dlybct 0 1 csaat ? 0 tdre ? 1 0 ps ? 0 1 spi_tdr(pcs) = npcs ? no yes spi_mr(pcs) = npcs ? no npcs = 0xf delay dlybcs npcs = spi_tdr(pcs) npcs = 0xf delay dlybcs npcs = spi_mr(pcs), spi_tdr(pcs) fixed peripheral variable peripheral - npcs defines the current chip select - csaat, dlybs, dlybct refer to the fields of the chip select register corresponding to the current chip select - when npcs is 0xf, csaat is 0.
650 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 650 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 36-7 shows transmit data register empty (tdre), receive data register (rdrf) and transmission register empty (txempty) status flags behavior within the spi_sr (status reg- ister) during an 8-bit data transfer in fixed mode and no peripheral data controller involved. figure 36-7. status register flags behavior 36.7.3.3 clock generation the spi baud rate clock is generated by dividing the master clock (mck), by a value between 1 and 255. this allows a maximum operating baud rate at up to master clock and a minimum operating baud rate of mck divided by 255. programming the scbr field at 0 is forbidden. tr iggering a transfer while scbr is at 0 can lead to unpredictable results. at reset, scbr is 0 and the user has to program it at a valid value before performing the first transfer. the divisor can be defined independently for each chip select, as it has to be programmed in the scbr field of the chip select registers. this allows the spi to automatically adapt the baud rate for each interfaced peripheral without reprogramming. 36.7.3.4 transfer delays figure 36-8 shows a chip select transfer change and consecutive transfers on the same chip select. three delays can be programmed to modify the transfer waveforms: ? the delay between chip selects, programmable only once for all the ch ip selects by writing the dlybcs field in the mode register. allows insertion of a delay between release of one chip select and before assertion of a new one. 6 spck mosi (from master) miso (from slave) npcs0 msb msb lsb lsb 6 6 5 5 4 4 3 3 2 2 1 1 1 2345 78 6 rdrf tdre txempty write in spi_tdr rdr read shift register empty
651 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 651 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? the delay before spck, independently programmable for each chip select by writing the field dlybs. allows the start of spck to be delayed after the chip select has been asserted. ? the delay between consecutive transfers, independently programmable for each chip select by writing the dlybct field. allows insertion of a delay between two transfers occurring on the same chip select these delays allow the spi to be adapted to the interfaced peripherals and their speed and bus release time. figure 36-8. programmable delays 36.7.3.5 peripheral selection the serial peripherals are selected through the assertion of the npcs0 to npcs3 signals. by default, all the npcs signals are high before and after each transfer. ? fixed peripheral select: spi exchanges data with only one peripheral fixed peripheral select is activated by writing the ps bit to zero in spi_mr (mode register). in this case, the current peripheral is defined by the pcs field in spi_mr and the pcs field in the spi_tdr has no effect. ? variable peripheral select: data can be exchanged with more than one peripheral without having to reprogram the npcs field in the spi_mr register. variable peripheral select is activated by se tting ps bit to one. the pcs field in spi_tdr is used to select the current peripheral. this means that the peripheral selection can be defined for each new data. the value to write in the spi_tdr register as the following format. [xxxxxxx(7-bit) + lastxfer(1-bit) (1) + xxxx(4-bit) + pcs (4-bit) + data (8 to 16-bit)] with pcs equals to the chip select to assert as defined in section 36.8.4 (spi transmit data register) and lastxfer bit at 0 or 1 depending on csaat bit. note: 1. optional. csaat, lastxfer and csnaat bits are discussed in section 36.7.3.9 peripheral deselec- tion with dmac . if lastxfer is used, the command must be issued before writing the last character. instead of lastxfer, the user can use the spidis command. after the end of the dma transfer, wait for the txempty flag, then write spidis into the spi _cr register (this will no t change the configu- ration register values); the np cs will be deactivated after the last character transfer. then, another dma transfer can be started if the spien was previously written in the spi_cr register. dlybcs dlybs dlybct dlybct chip select 1 chip select 2 spck
652 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 652 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 36.7.3.6 spi direct access memory controller (dmac) in both fixed and variable mode the direct memory access controller (dmac) can be used to reduce processor overhead. the fixed peripheral selection allows buffer tran sfers with a single perip heral. using the dmac is an optimal means, as the size of the data tr ansfer between the memory and the spi is either 8 bits or 16 bits. however, changing the peripheral selection requires the mode register to be reprogrammed. the variable peripheral selection allows buffer transfers with multiple peripherals without repro- gramming the mode register. data written in spi_tdr is 32 bits wide and defines the real data to be transmitted and the peripheral it is destined to. using the dmac in this mode requires 32- bit wide buffers, with the data in the lsbs and the pcs and lastxfer fields in the msbs, how- ever the spi still controls the number of bits (8 to16) to be transferre d through miso and mosi lines with the chip select configuration registers. this is not the optimal means in term of mem- ory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor. 36.7.3.7 peripheral chip select decoding the user can program the spi to operate with up to 15 peripherals by decoding the four chip select lines, npcs0 to npcs3 with 1 of up to 16 decoder/demultiplexer. this can be enabled by writing the pcsdec bit at 1 in the mode register (spi_mr). when operating without decoding, the spi makes sure that in any case only one chip select line is activated, i.e., one npcs line driven low at a time. if two bits are defined low in a pcs field, only the lowest numbered ch ip select is driven low. when operating with decoding, the spi directly outputs the value defined by the pcs field on npcs lines of either the mode register or the transmit data register (depending on ps). as the spi sets a default value of 0xf on the chip select lines (i.e. all chip select lines at 1) when not processing any transfer, only 15 peripherals can be decoded. the spi has only four chip select registers, not 15. as a result, when decoding is activated, each chip select defines the characteristics of up to four peripherals. as an example, spi_crs0 defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the pcs values 0x0 to 0x3. thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. figure 36-9 below shows such an implementation. if the csaat bit is used, with or without the dmac, the mode fault detection for npcs0 line must be disabled. this is not needed for all other chip select lines since mode fault detection is only on npcs0.
653 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 653 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 36-9. chip select decoding applicati on block diagram: single master/multiple slave implementation 36.7.3.8 peripheral deselection without dmac during a transfer of more than one data on a chip select without the dmac, the spi_tdr is loaded by the processor, the flag tdre rises as soon as the content of the spi_tdr is trans- ferred into the internal shift register. when this flag is detected high, the spi_tdr can be reloaded. if this reload by the processor occurs before the end of the current transfer and if the next transfer is performed on the same chip select as the current transfer, the chip select is not de-asserted between the two transfers. but depending on the application software handling the spi status register flags (by interrupt or polli ng method) or servicing other interrupts or other tasks, the processor may not reload the spi_tdr in time to keep the chip select active (low). a null delay between consecutive transfer (dlybc t) value in the spi_csr register, will give even less time for the processor to reload t he spi_tdr. with some spi slave peripherals, requiring the chip select line to remain active (low) during a full set of transfers might lead to communication errors. to facilitate interfacing with such devices, the chip select register [csr0...csr3] can be pro- grammed with the csaat bit (chip select active af ter transfer) at 1. this allows the chip select lines to remain in their current state (low = active) until transfer to another chip select is required. even if the spi_tdr is not reloa ded the chip select will remain active. to have the chip select line to raise at the end of the transfer the last transfer bit (lastxfer) in the spi_mr register must be set at 1 before writing the last data to transmit into the spi_tdr. 36.7.3.9 peripheral deselection with dmac when the direct memory access controller is used, the chip select line will remain low during the whole transfer since the tdre flag is managed by the dmac itself. the reloading of the spi_tdr by the dmac is done as soon as tdre flag is set to one. in this case the use of csaat bit might not be needed. however, it may happen that when other dmac channels con- spi master spck miso mosi npcs0 npcs1 npcs2 spck 1-of-n decoder/demultiplexer miso mosi nss slave 0 spck miso mosi nss slave 1 spck miso mosi nss slave 14 npcs3
654 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 654 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 nected to other peripherals are in use as well, the spi dmac might be delayed by another (dmac with a higher priority on the bus). having dmac buffers in slower memories like flash memory or sdram compared to fast internal sram, may lengthen the reload time of the spi_tdr by the dmac as well. this means that the spi_tdr might not be reloaded in time to keep the chip select line low. in this case the chip select line may toggle between data transfer and according to some spi slave devices, the communication might get lost. the use of the csaat bit might be needed. when the csaat bit is set at 0, the npcs does not rise in all cases between two transfers on the same peripheral. during a transfer on a chip select, the flag tdre rises as soon as the con- tent of the spi_tdr is transferred into the internal shifter. when this flag is detected the spi_tdr can be reloaded. if this reload occurs before the end of the current transfer and if the next transfer is performed on the same chip select as the current transfer, the chip select is not de-asserted between the two transfers. this migh t lead to difficulties fo r interfacing with some serial peripherals requiring the chip select to be de-asserted after each transfer. to facilitate interfacing with such de vices, the chip select register ca n be programmed with the csnaat bit (chip select not active after tr ansfer) at 1. this allows to de-assert systematically the chip select lines during a time dlybcs. (the value of the csnaat bit is taken into account only if the csaat bit is set at 0 for the same chip select). figure 36-10 shows different peripheral deselection cases and the effect of the csaat and csnaat bits.
655 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 655 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 36-10. peripheral deselection 36.7.3.10 mode fault detection a mode fault is detected when the spi is programmed in master mode and a low level is driven by an external master on the npcs0/nss signal. in this case, multi-master configuration, npcs0, mosi, miso and spck pins must be configured in open drain (through the pio control- ler). when a mode fault is detected, the modf bit in the spi_sr is set until the spi_sr is read a npcs[0..3] write spi_tdr tdre npcs[0..3] write spi_tdr tdre npcs[0..3] write spi_tdr tdre dlybcs pcs = a dlybcs dlybct a pcs = b b dlybcs pcs = a dlybcs dlybct a pcs = b b dlybcs dlybct pcs=a a dlybcs dlybct a pcs = a a a dlybct aa csaat = 0 and csnaat = 0 dlybct aa csaat = 1 and csnaat= 0 / 1 a dlybcs pcs = a dlybct aa csaat = 0 and csnaat = 1 npcs[0..3] write spi_tdr tdre pcs = a dlybct aa csaat = 0 and csnaat = 0
656 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 656 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 and the spi is automatically disabled until re-enabled by writing the spien bit in the spi_cr (control register) at 1. by default, the mode fault detection circuitr y is enabled. the user can disable mode fault detection by setting the modfdis bit in the spi mode register (spi_mr). 36.7.4 spi slave mode when operating in slave mode, the spi processes data bits on the clock provided on the spi clock pin (spck). the spi waits for nss to go active before receiving the serial clock from an external master. when nss falls, the clock is validated on the serializer, which processes the number of bits defined by the bits field of the chip select register 0 (spi_csr0). these bits are processed following a phase and a polarity defined respectively by the ncpha and cpol bits of the spi_csr0. note that bits, cpol and ncpha of the other chip select registers have no effect when the spi is programmed in slave mode. the bits are shifted out on the miso line and sampled on the mosi line. (for more information on bits field, see also, the (note:) below the register table; section 36.8.9 spi chip select register on page 669 .) when all the bits are processed, the received data is transferred in the receive data register and the rdrf bit rises. if the spi_rdr (receive data register) has no t been read be fore new data is received, the overrun error bit (ovres) in spi_sr is set. as long as this flag is set, data is loaded in spi_rdr. the user has to read the status register to clear the ovres bit. when a transfer starts, the data shifted out is the data present in the shift register. if no data has been written in the transmit data register (spi_tdr), the la st data received is transferred. if no data has been received since the last reset, all bits are transmitted low, as the shift regis- ter resets at 0. when a first data is written in sp i_tdr, it is transferred immediat ely in the shift register and the tdre bit rises. if new data is wr itten, it remains in spi_tdr unt il a transfer occurs, i.e. nss falls and there is a valid clock on the spck pin. w hen the transfer occurs, the last data written in spi_tdr is transferred in the shift register and the tdre bit rises. this enables frequent updates of critical variables with single transfers. then, a new data is loaded in the shift register from the transmit data register. in case no character is ready to be transmitted, i.e. no character has been written in spi_tdr since the last load from spi_tdr to the shift register, the shift register is not modified and the last received character is retransmitted. figure 36-11 shows a block diagram of the spi when operating in slave mode.
657 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 657 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 36-11. slave mode functional bloc diagram shift register spck spiens lsb msb nss mosi spi_rdr rd spi clock tdre spi_tdr td rdrf ovres spi_csr0 cpol ncpha bits spien spidis miso
658 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 658 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 36.7.5 write protected registers to prevent any single software error that may corrupt spi behavior, the registers listed below can be write-protected by setting the spiwpen bit in the spi write protection mode register (spi_wpmr). if a write access in a write-pr otected register is detected, then the spiwpvs flag in the spi write protection status register (spi_wpsr) is set and the field spiwpvsrc indicates in which register the write access has been attempted. the spiwpvs flag is automatically reset after reading the spi wr ite protection status register (spi_wpsr). list of the write-protected registers: section 36.8.2 spi mode register section 36.8.9 spi ch ip select register
659 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 659 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 36.8 serial peripheral inte rface (spi) user interface table 36-5. register mapping offset register name access reset 0x00 control register spi_cr write-only --- 0x04 mode register spi_mr read-write 0x0 0x08 receive data register spi_rdr read-only 0x0 0x0c transmit data register spi_tdr write-only --- 0x10 status register spi_sr read-only 0x000000f0 0x14 interrupt enable register spi_ier write-only --- 0x18 interrupt disable register spi_idr write-only --- 0x1c interrupt mask register spi_imr read-only 0x0 0x20 - 0x2c reserved 0x30 chip select register 0 spi_csr0 read-write 0x0 0x34 chip select register 1 spi_csr1 read-write 0x0 0x38 chip select register 2 spi_csr2 read-write 0x0 0x3c chip select register 3 spi_csr3 read-write 0x0 0x4c - 0xe0 reserved C C C 0xe4 write protection control register spi_wpmr read-write 0x0 0xe8 write protection status register spi_wpsr read-only 0x0 0x00e8 - 0x00f8 reserved C C C 0x00fc reserved C C C
660 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 660 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 36.8.1 spi control register name: spi_cr address: 0xf0000000 (0), 0xf0004000 (1) access: write-only ? spien: spi enable 0 = no effect. 1 = enables the spi to transfer and receive data. ? spidis: spi disable 0 = no effect. 1 = disables the spi. as soon as spidis is set, spi finishes its transfer. all pins are set in input mode and no data is received or transmitted. if a transfer is in progress, the transfer is finished before the spi is disabled. if both spien and spidis are equal to one when the control register is written, the spi is disabled. ? swrst: spi software reset 0 = no effect. 1 = reset the spi. a software-triggered hardware reset of the spi interface is performed. the spi is in slave mode after software reset. dmac channels are not affected by software reset. ? lastxfer: last transfer 0 = no effect. 1 = the current npcs will be deasserted afte r the character written in td has been transferred. when csaat is set, this allows to close the communication with the current serial peri pheral by raising the correspo nding npcs line as soon as td transfer has completed. refer to section 36.7.3.5 per ipheral selection for more details. 31 30 29 28 27 26 25 24 CCCCCCCl a s t x f e r 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 s w r s tCCCCCs p i d i ss p i e n
661 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 661 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 36.8.2 spi mode register name: spi_mr address: 0xf0000004 (0), 0xf0004004 (1) access: read-write ? mstr: master/slave mode 0 = spi is in slave mode. 1 = spi is in master mode. ? ps: peripheral select 0 = fixed peripheral select. 1 = variable peripheral select. ? pcsdec: chip select decode 0 = the chip selects are directly connected to a peripheral device. 1 = the four chip select lines are connected to a 4- to 16-bit decoder. when pcsdec equals one, up to 15 chip select signals can be generated with the four lines using an external 4- to 16-bit decoder. the chip select registers define the characteristics of the 15 chip selects according to the following rules: spi_csr0 defines peripheral chip select signals 0 to 3. spi_csr1 defines peripheral chip select signals 4 to 7. spi_csr2 defines peripheral chip select signals 8 to 11. spi_csr3 defines peripheral chip select signals 12 to 14. ? modfdis: mode fault detection 0 = mode fault detection is enabled. 1 = mode fault detection is disabled. ? wdrbt: wait data read before transfer 0 = no effect. in master mode, a transfer can be initiated whatever the state of the receive data register is. 1 = in master mode, a transfer can start only if the receive data register is empty, i.e. does not contain any unread data. this mode prevents overrun error in reception. 31 30 29 28 27 26 25 24 dlybcs 23 22 21 20 19 18 17 16 CCCC p c s 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 llb C wdrbt modfdis C pcsdec ps mstr
662 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 662 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? llb: local loopback enable 0 = local loopback path disabled. 1 = local loopback path enabled llb controls the local loopback on the data serializer for te sting in master mode only. (miso is internally connected on mosi.) ? pcs: peripheral chip select this field is only used if fixed peripheral select is active (ps = 0). if pcsdec = 0: pcs = xxx0 npcs[3:0] = 1110 pcs = xx01 npcs[3:0] = 1101 pcs = x011 npcs[3:0] = 1011 pcs = 0111 npcs[3:0] = 0111 pcs = 1111 forbidden (no peripheral is selected) (x = dont care) if pcsdec = 1: npcs[3:0] output signals = pcs. ? dlybcs: delay between chip selects this field defines the delay from npcs inactive to the ac tivation of another npcs. the dlybcs time guarantees non-over- lapping chip selects and solves bus contentions in case of peripherals having long data float times. if dlybcs is less than or eq ual to six, six mck periods will be inserted by default. otherwise, the following equat ion determines the delay: delay between chip selects dlybcs mck ---------------------- - =
663 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 663 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 36.8.3 spi receive data register name: spi_rdr address: 0xf0000008 (0), 0xf0004008 (1) access: read-only ? rd: receive data data received by the spi interface is stored in this register right-justified. unused bits read zero. ? pcs: peripheral chip select in master mode only, these bits indicate the value on the npcs pins at the end of a transfer. otherwise, these bits read zero. note: when using variable peripheral select mode (ps = 1 in spi_m r) it is mandatory to also set the wdrbt field to 1 if the spi_rdr pcs field is to be processed. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCC p c s 15 14 13 12 11 10 9 8 rd 76543210 rd
664 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 664 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 36.8.4 spi transmit data register name: spi_tdr address: 0xf000000c (0), 0xf000400c (1) access: write-only ? td: transmit data data to be transmitted by the spi interface is stored in this register. information to be transmitted must be written to the transmit data register in a right-justified format. ? pcs: peripheral chip select this field is only used if variable peripheral select is active (ps = 1). if pcsdec = 0: pcs = xxx0 npcs[3:0] = 1110 pcs = xx01 npcs[3:0] = 1101 pcs = x011 npcs[3:0] = 1011 pcs = 0111 npcs[3:0] = 0111 pcs = 1111 forbidden (no peripheral is selected) (x = dont care) if pcsdec = 1: npcs[3:0] output signals = pcs ? lastxfer: last transfer 0 = no effect. 1 = the current npcs will be deasserted afte r the character written in td has been transferred. when csaat is set, this allows to close the communication with the current serial peri pheral by raising the correspo nding npcs line as soon as td transfer has completed. this field is only used if variable peripheral select is active (ps = 1). 31 30 29 28 27 26 25 24 CCCCCCCl a s t x f e r 23 22 21 20 19 18 17 16 CCCC p c s 15 14 13 12 11 10 9 8 td 76543210 td
665 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 665 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 36.8.5 spi status register name: spi_sr address: 0xf0000010 (0), 0xf0004010 (1) access: read-only ? rdrf: receive data register full 0 = no data has been received since the last read of spi_rdr 1 = data has been received and the received data has been transferred from the serializer to spi_rdr since the last read of spi_rdr. ? tdre: transmit data register empty 0 = data has been written to spi_tdr and not yet transferred to the serializer. 1 = the last data written in the transmit data register has been transferred to the serializer. tdre equals zero when the spi is disabled or at reset. the spi enable command sets this bit to one. ? modf: mode fault error 0 = no mode fault has been detected since the last read of spi_sr. 1 = a mode fault occurred since the last read of the spi_sr. ? ovres: overrun error status 0 = no overrun has been detected since the last read of spi_sr. 1 = an overrun has occurred since the last read of spi_sr. an overrun occurs when spi_r dr is loaded at least twice from the serializer since the last read of the spi_rdr. ? nssr: nss rising 0 = no rising edge detected on nss pin since last read. 1 = a rising edge occurred on nss pin since last read. ? txempty: transmission registers empty 0 = as soon as data is written in spi_tdr. 1 = spi_tdr and internal shifter are empty. if a transfer delay has been defined, txempty is set after the completion of such delay. ? spiens: spi enable status 0 = spi is disabled. 1 = spi is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCs p i e n s 15 14 13 12 11 10 9 8 CCCCCCt x e m p t yn s s r 76543210 CCCCo v r e sm o d ft d r e rdrf
666 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 666 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 36.8.6 spi interrupt enable register name: spi_ier address: 0xf0000014 (0), 0xf0004014 (1) access: write-only 0 = no effect. 1 = enables the corresponding interrupt. ? rdrf: receive data register full interrupt enable ? tdre: spi transmit data regi ster empty interrupt enable ? modf: mode fault error interrupt enable ? ovres: overrun error interrupt enable ? nssr: nss rising interrupt enable ? txempty: transmission registers empty enable 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCt x e m p t yn s s r 76543210 CCCCo v r e sm o d ft d r e rdrf
667 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 667 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 36.8.7 spi interrupt disable register name: spi_idr address: 0xf0000018 (0), 0xf0004018 (1) access: write-only 0 = no effect. 1 = disables the corresponding interrupt. ? rdrf: receive data register full interrupt disable ? tdre: spi transmit data register empty interrupt disable ? modf: mode fault error interrupt disable ? ovres: overrun error interrupt disable ? nssr: nss rising interrupt disable ? txempty: transmission registers empty disable 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCt x e m p t yn s s r 76543210 CCCCo v r e sm o d ft d r e rdrf
668 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 668 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 36.8.8 spi interrupt mask register name: spi_imr address: 0xf000001c (0), 0xf000401c (1) access: read-only 0 = the corresponding interrupt is not enabled. 1 = the corresponding interrupt is enabled. ? rdrf: receive data register full interrupt mask ? tdre: spi transmit data register empty interrupt mask ? modf: mode fault error interrupt mask ? ovres: overrun error interrupt mask ? nssr: nss rising interrupt mask ? txempty: transmission registers empty mask 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCt x e m p t yn s s r 76543210 CCCCo v r e sm o d ft d r e rdrf
669 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 669 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 36.8.9 spi chip select register name: spi_csrx[x=0..3] address: 0xf0000030 (0), 0xf0004030 (1) access: read/write note: spi_csrx registers must be written even if the user wants to use the defaults. the bits field will not be updated with the trans- lated value unless the register is written. ? cpol: clock polarity 0 = the inactive state value of spck is logic level zero. 1 = the inactive state value of spck is logic level one. cpol is used to determine the inactive state value of the serial clock (spck). it is used with ncpha to produce the required clock/data relationship between master and slave devices. ? ncpha: clock phase 0 = data is changed on the leading edge of spck and captured on the following edge of spck. 1 = data is captured on the leading edge of spck and changed on the following edge of spck. ncpha determines which edge of spck causes data to change and which edge causes data to be captured. ncpha is used with cpol to produce the required clock/da ta relationship between master and slave devices. ? csnaat: chip select not active af ter transfer (ignored if csaat = 1) 0 = the peripheral chip select does not rise between two transfers if the spi_tdr is reloaded before the end of the first transfer and if the two transfers occur on the same chip select. 1 = the peripheral chip select rises systematically after each transfer performed on the same slave. it remains active after the end of transfer for a minimal duration of: C (if dlybct field is different from 0) C (if dlybct field equals 0) ? csaat: chip select active after transfer 0 = the peripheral chip select line rises as soon as the last transfer is achieved. 1 = the peripheral chip select does not rise after the last transfer is achieved. it remains active until a new transfer is requested on a different chip select. 31 30 29 28 27 26 25 24 dlybct 23 22 21 20 19 18 17 16 dlybs 15 14 13 12 11 10 9 8 scbr 76543210 bits csaat csnaat ncpha cpol dlybct mck ----------------------- dlybct 1 + mck ---------------------------------
670 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 670 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? bits: bits per transfer (see the (note:) below the register table; section 36.8.9 spi chip select register on page 669 .) the bits field determines the number of data bits transferred. reserved values should not be used. ? scbr: serial clock baud rate in master mode, the spi interface uses a modulus counter to derive the spck baud rate from the master clock mck. the baud rate is selected by writing a value from 1 to 255 in the scbr field. the following equations determine the spck baud rate: programming the scbr field at 0 is forbidden. triggering a trans fer while scbr is at 0 can le ad to unpredictable results. at reset, scbr is 0 and the user has to program it at a valid value before performing the first transfer. note: if one of the scbr fields inspi_csrx is set to 1, the other scbr fields in spi_csrx must be set to 1 as well, if they are required to process transfers. if they are not used to transfer data, they can be set at any value. ? dlybs: delay before spck this field defines the delay from npcs valid to the first valid spck transition. when dlybs equals zero, the npcs valid to spck transition is 1/2 the spck clock period. otherwise, the following equations determine the delay: value name description 0 8_bit 8 bits for transfer 1 9_bit 9 bits for transfer 2 10_bit 10 bits for transfer 3 11_bit 11 bits for transfer 4 12_bit 12 bits for transfer 5 13_bit 13 bits for transfer 6 14_bit 14 bits for transfer 7 15_bit 15 bits for transfer 8 16_bit 16 bits for transfer 9C reserved 10 C reserved 11 C reserved 12 C reserved 13 C reserved 14 C reserved 15 C reserved spck baudrate mck scbr -------------- -= delay before spck dlybs mck ------------------ -=
671 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 671 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? dlybct: delay between consecutive transfers this field defines the delay between two consecutive transfers with the same perip heral without removing the chip select. the delay is always inserted after each transfer and before removing the chip select if needed. when dlybct equals zero, no delay between consecutive transf ers is inserted and the clock keeps its duty cycle over the character transfers. otherwise, the following equat ion determines the delay: delay between consecutive transfers 32 dlybct mck ------------------------------------- =
672 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 672 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 36.8.10 spi write protection mode register name: spi_wpmr address: 0xf00000e4 (0), 0xf00040e4 (1) access: read-write ? spiwpen: spi write protection enable 0: the write protection is disabled 1: the write protection is enabled ? spiwpkey: spi write protection key password if a value is written in spiwpen, the value is taken into ac count only if spiwpkey is wri tten with spi (spi written in ascii code, ie 0x535049 in hexadecimal). 31 30 29 28 27 26 25 24 spiwpkey 23 22 21 20 19 18 17 16 spiwpkey 15 14 13 12 11 10 9 8 spiwpkey 76543210 -------s p i w p e n
673 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 673 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 36.8.11 spi write protection status register name: spi_wpsr address: 0xf00000e8 (0), 0xf00040e8 (1) access: read-only ? spiwpvs: spi write prot ection violation status ? spiwpvsrc: spi write prot ection violation source this field indicates the apb offset of the register concerned by the violation (spi _mr or spi_csrx) 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 spiwpvsrc 76543210 CCCCC spiwpvs spiwpvs value violation type 0x1 the write protection has blocked a write access to a protected register (since the last read). 0x2 software reset has been performed while write protection was enabled (since the last read or since the last write access on spi_m r, spi_ier, spi_i dr or spi_csrx). 0x3 both write protection violation and software re set with write protection enabled have occurred since the last read. 0x4 write accesses have been detected on spi_mr (while a chip select was active) or on spi_csri (while the chip select i was active) since the last read. 0x5 the write protection has blocked a write access to a protected register and write accesses have been detected on spi_mr (while a chip select was active) or on spi_csri (while the chip select i was active) since the last read. 0x6 software reset has been performed while write protection was enabled (since the last read or since the last write access on spi_mr, spi_i er, spi_idr or spi_csrx) and some write accesses have been detected on spi_mr (while a ch ip select was active) or on spi_csri (while the chip select i was active) since the last read. 0x7 - the write protection has blocked a write access to a protected register. and - software reset has been performed while write protection was enabled. and - write accesses have been detected on spi_mr (while a chip select was active) or on spi_csri (while the chip select i was active) since the last read.
674 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 674 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12
675 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 675 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 37. timer counter (tc) 37.1 description the timer counter (tc) includes 6 iden tical 32-bit timer counter channels. each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. each channel has three external clock inputs, fi ve internal clock inputs and two multi-purpose input/output signals which can be configured by the user. each channel drives an internal inter- rupt signal which can be programmed to generate processor interrupts. the timer counter block has two global registers which act upon all tc channels. the block control register allows the channels to be started simultaneously with the same instruction. the block mode register defines the external clock inputs for each channel, allowing them to be chained. table 37-1 gives the assignment of the device timer counter clock inputs common to timer counter 0 to 2. note: 1. when slow clock is selected for master clock (css = 0 in pmc master clock register), timer_clock5 input is master clock, i.e., slow clock modified by pres and mdiv fields. 37.2 embedded characteristics ? provides 6 32-bit timer counter channels ? wide range of functions including: C frequency measurement C event counting C interval measurement C pulse generation C delay timing C pulse width modulation C up/down capabilities C ? each channel is user-configurable and contains: C three external clock inputs C five internal clock inputs table 37-1. timer counter clock assignment name definition timer_clock1 mck/2 timer_clock2 mck/8 timer_clock3 mck/32 timer_clock4 mck/128 timer_clock5 (1) slck
676 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 676 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 C two multi-purpose input/output signals ? internal interrupt signal ? two global registers that act on all tc channels ? read of the capture registers by the dmac 37.3 block diagram figure 37-1. timer counter block diagram timer/counter channel 0 timer/counter channel 1 timer/counter channel 2 syn c parallel i/o controller tc1xc1s tc0xc0s tc2xc2s int0 int1 int2 tioa0 tioa1 tioa2 tiob0 tiob1 tiob2 xc0 xc1 xc2 xc0 xc1 xc2 xc0 xc1 xc2 tclk0 tclk1 tclk2 tclk0 tclk1 tclk2 tclk0 tclk1 tclk2 tioa1 tioa2 tioa0 tioa2 tioa0 tioa1 interrupt controller tclk0 tclk1 tclk2 tioa0 tiob0 tioa1 tiob1 tioa2 tiob2 timer counter tioa tiob tioa tiob tioa tiob syn c syn c timer_clock2 timer_clock3 timer_clock4 timer_clock5 timer_clock1 table 37-2. signal name description block/channel signal name description channel signal xc0, xc1, xc2 external clock inputs tioa capture mode: timer counter input waveform mode: timer counter output tiob capture mode: timer counter input waveform mode: timer counter input/output int interrupt signal output sync synchronization input signal
677 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 677 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 37.4 pin name list 37.5 product dependencies 37.5.1 i/o lines the pins used for interfacing the compliant ex ternal devices may be multiplexed with pio lines. the programmer must first program the pio controllers to assign the tc pins to their peripheral functions. 37.5.2 power management the tc is clocked through the power management controller (pmc), thus the programmer must first configure the pmc to enable the timer counter clock. table 37-3. tc pin list pin name description type tclk0-tclk2 external clock input input tioa0-tioa2 i/o line a i/o tiob0-tiob2 i/o line b i/o table 37-4. i/o lines instance signal i/o line peripheral tc0 tclk0 pa24 a tc0 tclk1 pa25 a tc0 tclk2 pa26 a tc0 tioa0 pa21 a tc0 tioa1 pa22 a tc0 tioa2 pa23 a tc0 tiob0 pa27 a tc0 tiob1 pa28 a tc0 tiob2 pa29 a tc1 tclk3 pc4 c tc1 tclk4 pc7 c tc1 tclk5 pc14 c tc1 tioa3 pc2 c tc1 tioa4 pc5 c tc1 tioa5 pc12 c tc1 tiob3 pc3 c tc1 tiob4 pc6 c tc1 tiob5 pc13 c
678 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 678 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 37.5.3 interrupt the tc has an interrupt line connected to the interrupt controller (ic). handling the tc interrupt requires programming the ic before configuring the tc. 37.6 functional description 37.6.1 tc description the 6 channels of the timer counter are independent and identical in operation. the registers for channel programming are listed in table 37-5 on page 691 . 37.6.2 32-bit counter each channel is organized around a 32-bit counter. the value of the counter is incremented at each positive edge of the selected clock. when the counter has reached the value 0xffff and passes to 0x0000, an overflow occurs and the covfs bit in tc_sr (status register) is set. the current value of the counter is accessible in real time by reading the counter value regis- ter, tc_cv. the counter can be reset by a trigger. in this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. 37.6.3 clock selection at block level, input clock signals of each channel can either be connected to the external inputs tclk0, tclk1 or tclk2, or be connected to t he internal i/o signals tioa0, tioa1 or tioa2 for chaining by programming the tc_bmr (block mode). see figure 37-2 clock chaining selection . each channel can independently select an internal or external clock source for its counter: ? internal clock signals: timer_cl ock1, timer_clock2, timer_clock3, timer_clock4, timer_clock5 ? external clock signals: xc0, xc1 or xc2 this selection is made by the tcclks bits in the tc channel mode register. the selected clock can be inverted with the clki bit in tc_cmr. this allows counting on the opposite edges of the clock. the burst function allows the clock to be validat ed when an external signal is high. the burst parameter in the mode register defines this signal (none, xc0, xc1, xc2). see figure 37-3 clock selection note: in all cases, if an external clock is used, the du ration of each of its leve ls must be longer than the master clock period. the external clock frequen cy must be at least 2.5 times lower than the mas- ter clock
679 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 679 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 37-2. clock chaining selection figure 37-3. clock selection timer/counter channel 0 sync tc0xc0s tioa0 tiob0 xc0 xc1 = tclk1 xc2 = tclk2 tclk0 tioa1 tioa2 timer/counter channel 1 sync tc1xc1s tioa1 tiob1 xc0 = tclk0 xc1 xc2 = tclk2 tclk1 tioa0 tioa2 timer/counter channel 2 sync tc2xc2s tioa2 tiob2 xc0 = tclk0 xc1 = tclk1 xc2 tclk2 tioa0 tioa1 timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 tcclks clki synchronous edge detection burst mck 1 selected clock
680 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 680 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 37.6.4 clock control the clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. see figure 37-4 . ? the clock can be enabled or disabled by the user with the clken and the clkdis commands in the control register. in capture mode it can be disabled by an rb load event if ldbdis is set to 1 in tc_cmr. in waveform mode, it can be disabled by an rc compare event if cpcdis is set to 1 in tc_cmr. when disabled, the start or the stop actions have no effect: only a clken command in the control register can re-enable the clock. when the clock is enabled, the clksta bit is set in the status register. ? the clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. the clock can be stopped by an rb load event in capture mode (ldbstop = 1 in tc_cmr) or a rc compare event in waveform mode (cpcstop = 1 in tc_cmr). the start and the stop commands have effect only if the clock is enabled. figure 37-4. clock control 37.6.5 tc operating modes each channel can independently operate in two different modes: ? capture mode provides measurement on signals. ? waveform mode provides wave generation. the tc operating mode is prog rammed with the wave bit in th e tc channel mode register. in capture mode, tioa and tiob are configured as inputs. in waveform mode, tioa is always configured to be an output and tiob is an output if it is not selected to be the external trigger. 37.6.6 trigger a trigger resets the counter and starts the counter clock. three types of triggers are common to both modes, and a fourth external trigger is available to each mode. qs r s r q clksta clken clkdis stop event disable event counter clock selected clock trigger
681 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 681 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. this means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. the following triggers are common to both modes: ? software trigger: each channel has a software trigger, available by setting swtrg in tc_ccr. ? sync: each channel has a synchronization signal sync. when asserted, this signal has the same effect as a software trigger. the sync signals of all channels are asserted simultaneously by writing tc_bcr (block control) with sync set. ? compare rc trigger: rc is implemented in each channel and can provide a trigger when the counter value matches the rc val ue if cpctrg is set in tc_cmr. the channel can also be configured to have an external trigger. in capture mode, the external trigger signal can be selected between tioa and tiob. in waveform mode, an external event can be programmed on one of the following signals: tiob, xc0, xc1 or xc2. this external event can then be programmed to perform a trigger by setting enetrg in tc_cmr. if an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected. 37.6.7 capture operating mode this mode is entered by clearing the wave parameter in tc_cmr (channel mode register). capture mode allows the tc channel to perform measurements such as pulse timing, fre- quency, period, duty cycle and phase on tioa and tiob sig nals which are considered as inputs. figure 37-5 shows the configuration of the tc channel when programmed in capture mode. 37.6.8 capture registers a and b registers a and b (ra and rb) are used as capture registers. this means that they can be loaded with the counter value when a progr ammable event occurs on the signal tioa. the ldra parameter in tc_cmr defines the tioa selected edge for the loading of register a, and the ldrb parameter defines the tioa selected edge for the loading of register b. ra is loaded only if it has not been loaded since the last trigger or if rb has been loaded since the last loading of ra. rb is loaded only if ra has been loaded sinc e the last trigger or t he last loading of rb. the rab register provides the next unread value from register a and register b. it may be read by the dmac after a request has been triggered upon loading register a or register b. loading ra or rb before the read of the last value loaded sets the overrun error flag (lovrs) in tc_sr (status register). in this case, the old value is overwritten. 37.6.9 trigger conditions in addition to the sync signal, the software trigger and the rc compare trigger, an external trig- ger can be defined. the abetrg bit in tc_cmr selects tioa or tiob input signal as an external trigger. the etrgedg parameter defines the edge (rising, falling or both) det ected to genera te an external trigger. if etrgedg = 0 (none), the external trigger is disabled.
682 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 682 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 37-5. capture mode timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 tcclks clki qs r s r q clksta clken clkdis burst tiob register c capture register a capture register b compare rc = counter abetrg swtrg etrgedg cpctrg tc1_imr trig ldrbs ldras etrgs tc1_sr lovrs covfs sync 1 mtiob tioa mtioa ldra ldbstop if ra is not loaded or rb is loaded if ra is loaded ldbdis cpcs int edge detector edge detector ldrb edge detector clk ovf reset timer/counter channel mck synchronous edge detection
683 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 683 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 37.6.10 waveform operating mode waveform operating mode is entered by setting the wave parameter in tc_cmr (channel mode register). in waveform operating mode the tc channel generates 1 or 2 pwm signals with the same fre- quency and independently programmable duty cycles , or generates differe nt types of one-shot or repetitive pulses. in this mode, tioa is configured as an output and tiob is defined as an output if it is not used as an external event ( eevt parameter in tc_cmr). figure 37-6 shows the configuration of the tc channel when programmed in waveform operat- ing mode. 37.6.11 waveform selection depending on the wavsel parameter in tc_c mr (channel mode register), the behavior of tc_cv varies. with any selection, ra, rb and rc can all be used as compare registers. ra compare is used to control the tioa output, rb compare is used to control the tiob output (if correctly configured) and rc compare is used to control tioa and/or tiob outputs.
684 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 684 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 37-6. waveform mode tcclks clki qs r s r q clksta clken clkdis cpcdis burst tiob register a register b register c compare ra = compare rb = compare rc = cpcstop counter eevt eevtedg sync swtrg enetrg wavsel tc1_imr trig acpc acpa aeevt aswtrg bcpc bcpb beevt bswtrg tioa mtioa tiob mtiob cpas covfs etrgs tc1_sr cpcs cpbs clk ovf reset output controller output controller int 1 edge detector timer/counter channel timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 wavsel mck synchronous edge detection
685 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 685 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 37.6.11.1 wavsel = 00 when wavsel = 00, the value of tc_cv is incr emented from 0 to 0x ffff. once 0xffff has been reached, the value of tc_cv is reset. incrementation of tc_cv starts again and the cycle continues. see figure 37-7 . an external event trigger or a software trigger can reset the value of tc_cv. it is important to note that the trigger may occur at any time. see figure 37-8 . rc compare cannot be programmed to generate a trigger in this configuration. at the same time, rc compare can stop the counter clock (cpcstop = 1 in tc_cmr) and/or disable the counter clock (cpcdis = 1 in tc_cmr). figure 37-7. wavsel= 00 without trigger time counter value r c r b r a tiob tioa counter cleared by compare match with 0xffff 0xffff waveform examples
686 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 686 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 37-8. wavsel= 00 with trigger 37.6.11.2 wavsel = 10 when wavsel = 10, the value of tc_cv is incremented from 0 to the value of rc, then auto- matically reset on a rc compare. once the value of tc_cv has been reset, it is then incremented and so on. see figure 37-9 . it is important to note that tc_cv can be reset at any time by an external event or a software trigger if both are programmed correctly. see figure 37-10 . in addition, rc compare can stop the counter clock (cpcstop = 1 in tc_cmr) and/or disable the counter clock (cpcdis = 1 in tc_cmr). figure 37-9. wavsel = 10 without trigger time counter value r c r b r a tiob tioa counter cleared by compare match with 0xffff 0xffff waveform examples counter cleared by trigger time counter value r c r b r a tiob tioa counter cleared by compare match with rc 0xffff waveform examples
687 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 687 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 37-10. wavsel = 10 with trigger 37.6.11.3 wavsel = 01 when wavsel = 01, the value of tc_cv is incremented from 0 to 0xffff. once 0xffff is reached, the value of tc_cv is decremented to 0, then re-incremented to 0xffff and so on. see figure 37-11 . a trigger such as an external event or a software trigger can modify tc_cv at any time. if a trig- ger occurs while tc_cv is incrementing, tc_cv then decrements. if a trigger is received while tc_cv is decrementing, tc_cv then increments. see figure 37-12 . rc compare cannot be programmed to generate a trigger in this configuration. at the same time, rc compare can stop the counter clock (cpcstop = 1) and/or disable the counter clock (cpcdis = 1). time counter value r c r b r a tiob tioa counter cleared by compare match with rc 0xffff waveform examples counter cleared by trigger
688 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 688 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 37-11. wavsel = 01 without trigger figure 37-12. wavsel = 01 with trigger 37.6.11.4 wavsel = 11 when wavsel = 11, the value of tc_cv is incremented from 0 to rc. once rc is reached, the value of tc_cv is decremented to 0, then re-incremented to rc and so on. see figure 37-13 . a trigger such as an external event or a software trigger can modify tc_cv at any time. if a trig- ger occurs while tc_cv is incrementing, tc_cv then decrements. if a trigger is received while tc_cv is decrementing, tc_cv then increments. see figure 37-14 . rc compare can stop the counter clock (cpcstop = 1) and/or disable the counter clock (cpcdis = 1). time counter value r c r b r a tiob tioa counter decremented by compare match with 0xffff 0xffff waveform examples time counter value tiob tioa counter decremented by compare match with 0xffff 0xffff waveform examples counter decremented by trigger counter incremented by trigger r c r b r a
689 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 689 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 37-13. wavsel = 11 without trigger figure 37-14. wavsel = 11 with trigger time counter value r c r b r a tiob tioa counter decremented by compare match with rc 0xffff waveform examples time counter value tiob tioa counter decremented by compare match with rc 0xffff waveform examples counter decremented by trigger counter incremented by trigger r c r b r a
690 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 690 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 37.6.12 external event/trigger conditions an external event can be programmed to be detected on one of the clock sources (xc0, xc1, xc2) or tiob. the external event selected can then be used as a trigger. the eevt parameter in tc_cmr selects the external tr igger. the eevtedg parameter defines the trigger edge for each of the possible external triggers (ris ing, falling or both). if eevtedg is cleared (none), no external event is defined. if tiob is defined as an external event signal (eevt = 0), tiob is no longer used as an output and the compare register b is not used to generate waveforms and subsequently no irqs. in this case the tc channel can only generate a waveform on tioa. when an external event is defined, it can be used as a trigger by setting bit enetrg in tc_cmr. as in capture mode, the sync signal and the softw are trigger are also available as triggers. rc compare can also be used as a trigger depending on the parameter wavsel. 37.6.13 output controller the output controller defines the output level changes on tioa and tiob following an event. tiob control is used only if tiob is defin ed as output (not as an external event). the following events control tioa and tiob: software trigger, external event and rc compare. ra compare controls tioa and rb compare controls tiob. each of these events can be pro- grammed to set, clear or toggle the output as defined in the corresponding parameter in tc_cmr.
691 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 691 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 37.7 timer counter (tc) user interface notes: 1. channel index ranges from 0 to 2. 2. read-only if wave = 0 table 37-5. register mapping offset (1) register name access reset 0x00 + channel * 0x40 + 0x00 channel control register tc_ccr write-only C 0x00 + channel * 0x40 + 0x04 channel mode register tc_cmr read-write 0 0x00 + channel * 0x40 + 0x08 reserved 0x00 + channel * 0x40 + 0x0c register ab tc_rab read-only 0 0x00 + channel * 0x40 + 0x10 counter value tc_cv read-only 0 0x00 + channel * 0x40 + 0x14 register a tc_ra read-write (2) 0 0x00 + channel * 0x40 + 0x18 register b tc_rb read-write (2) 0 0x00 + channel * 0x40 + 0x1c register c tc_rc read-write 0 0x00 + channel * 0x40 + 0x20 status register tc_sr read-only 0 0x00 + channel * 0x40 + 0x24 interrupt enable register tc_ier write-only C 0x00 + channel * 0x40 + 0x28 interrupt disable register tc_idr write-only C 0x00 + channel * 0x40 + 0x2c interrupt mask register tc_imr read-only 0 0xc0 block control register tc_bcr write-only C 0xc4 block mode register tc_bmr read-write 0 0xd8 reserved 0xe4 reserved 0xfc reserved C C C
692 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 692 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 37.7.1 tc block control register name: tc_bcr address: 0xf80080c0 (0), 0xf800c0c0 (1) access: write-only ? sync: synchro command 0 = no effect. 1 = asserts the sync signal which generates a software trigger simultaneously for each of the channels. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCCs y n c
693 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 693 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 37.7.2 tc block mode register name: tc_bmr address: 0xf80080c4 (0), 0xf800c0c4 (1) access: read-write ? tc0xc0s: external clock signal 0 selection ? tc1xc1s: external clock signal 1 selection ? tc2xc2s: external clock signal 2 selection 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 C C tc2xc2s tc1xc1s tc0xc0s value name description 0 tclk0 signal connected to xc0: tclk0 1C reserved 2 tioa1 signal connected to xc0: tioa1 3 tioa2 signal connected to xc0: tioa2 value name description 0 tclk1 signal connected to xc1: tclk1 1C reserved 2 tioa0 signal connected to xc1: tioa0 3 tioa2 signal connected to xc1: tioa2 value name description 0 tclk2 signal connected to xc2: tclk2 1C reserved 2 tioa1 signal connected to xc2: tioa1 3 tioa2 signal connected to xc2: tioa2
694 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 694 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 37.7.3 tc channel control register name: tc_ccrx [x=0..2] address: 0xf8008000 (0)[0], 0xf8008040 (0)[1], 0xf8008080 (0)[2], 0xf800c000 (1)[0], 0xf800c040 (1)[1], 0xf800c080 (1)[2] access: write-only ? clken: counter clock enable command 0 = no effect. 1 = enables the clock if clkdis is not 1. ? clkdis: counter clock disable command 0 = no effect. 1 = disables the clock. ? swtrg: software trigger command 0 = no effect. 1 = a software trigger is performed: the counter is reset and the clock is started. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCs w t r gc l k d i sc l k e n
695 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 695 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 37.7.4 tc channel mode register: capture mode name: tc_cmrx [x=0..2] (wave = 0) address: 0xf8008004 (0)[0], 0xf8008044 (0)[1], 0xf8008084 (0)[2], 0xf800c004 (1)[0], 0xf800c044 (1)[1], 0xf800c084 (1)[2] access: read-write ? tcclks: clock selection ? clki: clock invert 0 = counter is incremented on rising edge of the clock. 1 = counter is incremented on falling edge of the clock. ? burst: burst signal selection ? ldbstop: counter clock stopped with rb loading 0 = counter clock is not stopped when rb loading occurs. 1 = counter clock is stopped when rb loading occurs. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 C C C C ldrb ldra 15 14 13 12 11 10 9 8 wave cpctrg C C C abetrg etrgedg 76543210 ldbdis ldbstop burst clki tcclks value name description 0 timer_clock1 clock selected: tclk1 1 timer_clock2 clock selected: tclk2 2 timer_clock3 clock selected: tclk3 3 timer_clock4 clock selected: tclk4 4 timer_clock5 clock selected: tclk5 5 xc0 clock selected: xc0 6 xc1 clock selected: xc1 7 xc2 clock selected: xc2 value name description 0 none the clock is not gated by an external signal. 1 xc0 xc0 is anded with the selected clock. 2 xc1 xc1 is anded with the selected clock. 3 xc2 xc2 is anded with the selected clock.
696 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 696 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? ldbdis: counter clock disable with rb loading 0 = counter clock is not disabled when rb loading occurs. 1 = counter clock is disabled when rb loading occurs. ? etrgedg: external trigger edge selection ? abetrg: tioa or tiob external trigger selection 0 = tiob is used as an external trigger. 1 = tioa is used as an external trigger. ? cpctrg: rc compare trigger enable 0 = rc compare has no effect on the counter and its clock. 1 = rc compare resets the counter and starts the counter clock. ? wave: waveform mode 0 = capture mode is enabled. 1 = capture mode is disabled (waveform mode is enabled). ? ldra: ra loading edge selection ? ldrb: rb loading edge selection value name description 0 none the clock is not gated by an external signal. 1 rising rising edge 2 falling falling edge 3 edge each edge value name description 0none none 1 rising rising edge of tioa 2 falling falling edge of tioa 3 edge each edge of tioa value name description 0none none 1 rising rising edge of tioa 2 falling falling edge of tioa 3 edge each edge of tioa
697 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 697 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 37.7.5 tc channel mode register: waveform mode name: tc_cmrx [x=0..2] (wave = 1) access: read-write ? tcclks: clock selection ? clki: clock invert 0 = counter is incremented on rising edge of the clock. 1 = counter is incremented on falling edge of the clock. ? burst: burst signal selection ? cpcstop: counter clock stopped with rc compare 0 = counter clock is not stopped when counter reaches rc. 1 = counter clock is stopped when counter reaches rc. ? cpcdis: counter clock disable with rc compare 0 = counter clock is not disabl ed when counter reaches rc. 1 = counter clock is disabled when counter reaches rc. 31 30 29 28 27 26 25 24 bswtrg beevt bcpc bcpb 23 22 21 20 19 18 17 16 aswtrg aeevt acpc acpa 15 14 13 12 11 10 9 8 wave wavsel enetrg eevt eevtedg 76543210 cpcdis cpcstop burst clki tcclks value name description 0 timer_clock1 clock selected: tclk1 1 timer_clock2 clock selected: tclk2 2 timer_clock3 clock selected: tclk3 3 timer_clock4 clock selected: tclk4 4 timer_clock5 clock selected: tclk5 5 xc0 clock selected: xc0 6 xc1 clock selected: xc1 7 xc2 clock selected: xc2 value name description 0 none the clock is not gated by an external signal. 1 xc0 xc0 is anded with the selected clock. 2 xc1 xc1 is anded with the selected clock. 3 xc2 xc2 is anded with the selected clock.
698 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 698 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? eevtedg: external ev ent edge selection ? eevt: external event selection signal selected as external event. note: 1. if tiob is chosen as the external event signal, it is conf igured as an input and no longer generates waveforms and subse- quently no irqs . ? enetrg: external event trigger enable 0 = the external event has no effect on the counter and its clock. in this case, the selected external event only controls the tioa output. 1 = the external event resets the counter and starts the counter clock. ? wavsel: waveform selection ? wave: waveform mode 0 = waveform mode is disabled (capture mode is enabled). 1 = waveform mode is enabled. ? acpa: ra compare effect on tioa value name description 0none none 1 rising rising edge 2 falling falling edge 3 edge each edge value name description tiob direction 0 tiob tiob (1) input 1 xc0 xc0 output 2 xc1 xc1 output 3 xc2 xc2 output value name description 0 up up mode without automatic trigger on rc compare 1 updown updown mode without automatic trigger on rc compare 2 up_rc up mode with automatic trigger on rc compare 3 updown_rc updown mode with autom atic trigger on rc compare value name description 0none none 1 set set 2 clear clear 3 toggle toggle
699 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 699 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? acpc: rc compare effect on tioa ? aeevt: external event effect on tioa ? aswtrg: software trigger effect on tioa ? bcpb: rb compare effect on tiob ? bcpc: rc compare effect on tiob value name description 0none none 1 set set 2 clear clear 3 toggle toggle value name description 0none none 1 set set 2 clear clear 3 toggle toggle value name description 0none none 1 set set 2 clear clear 3 toggle toggle value name description 0none none 1 set set 2 clear clear 3 toggle toggle value name description 0none none 1 set set 2 clear clear 3 toggle toggle
700 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 700 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? beevt: external event effect on tiob ? bswtrg: software trigger effect on tiob value name description 0none none 1 set set 2 clear clear 3 toggle toggle value name description 0none none 1 set set 2 clear clear 3 toggle toggle
701 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 701 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 37.7.6 tc register ab name: tc_rabx [x=0..2] address: 0xf800800c (0)[0], 0xf800804c (0)[1], 0xf800808c (0)[2], 0xf800c00c (1)[0], 0xf800c04c (1)[1], 0xf800c08c (1)[2] access: read-only ? rab: register a or register b rab contains the next unread capture register a or regist er b value in real time. it is usually read by the dmac after a request due to a valid load edge on tioa. 37.7.7 tc counter value register name: tc_cvx [x=0..2] address: 0xf8008010 (0)[0], 0xf8008050 (0)[1], 0xf8008090 (0)[2], 0xf800c010 (1)[0], 0xf800c050 (1)[1], 0xf800c090 (1)[2] access: read-only ? cv: counter value cv contains the counter value in real time. 31 30 29 28 27 26 25 24 rab 23 22 21 20 19 18 17 16 rab 15 14 13 12 11 10 9 8 rab 76543210 rab 31 30 29 28 27 26 25 24 cv 23 22 21 20 19 18 17 16 cv 15 14 13 12 11 10 9 8 cv 76543210 cv
702 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 702 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 37.7.8 tc register a name: tc_rax [x=0..2] address: 0xf8008014 (0)[0], 0xf8008054 (0)[1], 0xf8008094 (0)[2], 0xf800c014 (1)[0], 0xf800c054 (1)[1], 0xf800c094 (1)[2] access: read-only if wave = 0, read-write if wave = 1 ? ra: register a ra contains the register a value in real time. 31 30 29 28 27 26 25 24 ra 23 22 21 20 19 18 17 16 ra 15 14 13 12 11 10 9 8 ra 76543210 ra
703 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 703 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 37.7.9 tc register b name: tc_rbx [x=0..2] address: 0xf8008018 (0)[0], 0xf8008058 (0)[1], 0xf8008098 (0)[2], 0xf800c018 (1)[0], 0xf800c058 (1)[1], 0xf800c098 (1)[2] access: read-only if wave = 0, read-write if wave = 1 ? rb: register b rb contains the register b value in real time. 37.7.10 tc register c name: tc_rcx [x=0..2] address: 0xf800801c (0)[0], 0xf800805c (0)[1], 0xf800809c (0)[2], 0xf800c01c (1)[0], 0xf800c05c (1)[1], 0xf800c09c (1)[2] access: read-write ? rc: register c rc contains the register c value in real time. 31 30 29 28 27 26 25 24 rb 23 22 21 20 19 18 17 16 rb 15 14 13 12 11 10 9 8 rb 76543210 rb 31 30 29 28 27 26 25 24 rc 23 22 21 20 19 18 17 16 rc 15 14 13 12 11 10 9 8 rc 76543210 rc
704 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 704 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 37.7.11 tc status register name: tc_srx [x=0..2] address: 0xf8008020 (0)[0], 0xf8008060 (0)[1], 0xf80080a0 (0)[2], 0xf800c020 (1)[0], 0xf800c060 (1)[1], 0xf800c0a0 (1)[2] access: read-only ? covfs: counter overflow status 0 = no counter overflow has occurred since the last read of the status register. 1 = a counter overflow has occurred since the last read of the status register. ? lovrs: load overrun status 0 = load overrun has not occurred since the last read of the status register or wave = 1. 1 = ra or rb have been loaded at least twice without any read of the corresponding register since the last read of the sta- tus register, if wave = 0. ? cpas: ra compare status 0 = ra compare has not occurred since the last read of the status register or wave = 0. 1 = ra compare has occurred since the last read of the status register, if wave = 1. ? cpbs: rb compare status 0 = rb compare has not occurred since the last read of the status register or wave = 0. 1 = rb compare has occurred since the last read of the status register, if wave = 1. ? cpcs: rc compare status 0 = rc compare has not occurred since the last read of the status register. 1 = rc compare has occurred since the last read of the status register. ? ldras: ra loading status 0 = ra load has not occurred si nce the last read of the status register or wave = 1. 1 = ra load has occurred since the last re ad of the status register, if wave = 0. ? ldrbs: rb loading status 0 = rb load has not occurred si nce the last read of the status register or wave = 1. 1 = rb load has occurred since the last re ad of the status register, if wave = 0. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCm t i o bm t i o ac l k s t a 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
705 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 705 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? etrgs: external trigger status 0 = external trigger has not occurred sinc e the last read of the status register. 1 = external trigger has occurred since the last read of the status register. ? clksta: clock enabling status 0 = clock is disabled. 1 = clock is enabled. ? mtioa: tioa mirror 0 = tioa is low. if wave = 0, this means that tioa pin is low. if wave = 1, this means that tioa is driven low. 1 = tioa is high. if wave = 0, this mean s that tioa pin is high. if wave = 1, this means that ti oa is driven high. ? mtiob: tiob mirror 0 = tiob is low. if wave = 0, this means that tiob pin is low. if wave = 1, this means that tiob is driven low. 1 = tiob is high. if wave = 0, this mean s that tiob pin is high. if wave = 1, this means that ti ob is driven high.
706 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 706 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 37.7.12 tc interrupt enable register name: tc_ierx [x=0..2] address: 0xf8008024 (0)[0], 0xf8008064 (0)[1], 0xf80080a4 (0)[2], 0xf800c024 (1)[0], 0xf800c064 (1)[1], 0xf800c0a4 (1)[2] access: write-only ? covfs: counter overflow 0 = no effect. 1 = enables the counter overflow interrupt. ? lovrs: load overrun 0 = no effect. 1 = enables the load overrun interrupt. ? cpas: ra compare 0 = no effect. 1 = enables the ra compare interrupt. ? cpbs: rb compare 0 = no effect. 1 = enables the rb compare interrupt. ? cpcs: rc compare 0 = no effect. 1 = enables the rc compare interrupt. ? ldras: ra loading 0 = no effect. 1 = enables the ra load interrupt. ? ldrbs: rb loading 0 = no effect. 1 = enables the rb load interrupt. ? etrgs: external trigger 0 = no effect. 1 = enables the external trigger interrupt. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
707 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 707 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 37.7.13 tc interrupt disable register name: tc_idrx [x=0..2] address: 0xf8008028 (0)[0], 0xf8008068 (0)[1], 0xf80080a8 (0)[2], 0xf800c028 (1)[0], 0xf800c068 (1)[1], 0xf800c0a8 (1)[2] access: write-only ? covfs: counter overflow 0 = no effect. 1 = disables the counter overflow interrupt. ? lovrs: load overrun 0 = no effect. 1 = disables the load overrun interrupt (if wave = 0). ? cpas: ra compare 0 = no effect. 1 = disables the ra compare interrupt (if wave = 1). ? cpbs: rb compare 0 = no effect. 1 = disables the rb compare interrupt (if wave = 1). ? cpcs: rc compare 0 = no effect. 1 = disables the rc compare interrupt. ? ldras: ra loading 0 = no effect. 1 = disables the ra load interrupt (if wave = 0). ? ldrbs: rb loading 0 = no effect. 1 = disables the rb load interrupt (if wave = 0). ? etrgs: external trigger 0 = no effect. 1 = disables the external trigger interrupt. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
708 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 708 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 37.7.14 tc interrupt mask register name: tc_imrx [x=0..2] address: 0xf800802c (0)[0], 0xf800806c (0)[1], 0xf80080ac (0)[2], 0xf800c02c (1)[0], 0xf800c06c (1)[1], 0xf800c0ac (1)[2] access: read-only ? covfs: counter overflow 0 = the counter overflow interrupt is disabled. 1 = the counter overflow interrupt is enabled. ? lovrs: load overrun 0 = the load overrun interrupt is disabled. 1 = the load overrun interrupt is enabled. ? cpas: ra compare 0 = the ra compare interrupt is disabled. 1 = the ra compare interrupt is enabled. ? cpbs: rb compare 0 = the rb compare interrupt is disabled. 1 = the rb compare interrupt is enabled. ? cpcs: rc compare 0 = the rc compare interrupt is disabled. 1 = the rc compare interrupt is enabled. ? ldras: ra loading 0 = the load ra interrupt is disabled. 1 = the load ra interrupt is enabled. ? ldrbs: rb loading 0 = the load rb interrupt is disabled. 1 = the load rb interrupt is enabled. ? etrgs: external trigger 0 = the external trigger interrupt is disabled. 1 = the external trigger interrupt is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
709 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 38. pulse width modulation controller (pwm) 38.1 description the pwm macrocell controls several cha nnels independently. each channel controls one square output waveform. characteristics of the output waveform such as period, duty-cycle and polarity are configurable through the user interface. each channel selects and uses one of the clocks provided by the clock generator. the cloc k generator provides several clocks resulting from the division of the pwm macrocell master clock. all pwm macrocell accesses are made through apb mapped registers. channels can be synchronized, to generate non overlapped waveforms. all channels integrate a double buffering system in order to prevent an unexpected output waveform while modifying the period or the duty-cycle. 38.2 embedded characteristics ? 4 channels, one 32-bit counter per channel ? common clock generator, providing thirteen different clocks C a modulo n counter providing eleven clocks C two independent linear dividers working on modulo n counter outputs ? independent channel programming C independent enable disable commands C independent clock selection C independent period and duty cycle, with double bufferization C programmable selection of the output waveform polarity C programmable center or left aligned output waveform
710 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 38.3 block diagram figure 38-1. pulse width modulation controller block diagram 38.4 i/o lines description each channel outputs one waveform on one external i/o line. 38.5 product dependencies 38.5.1 i/o lines the pins used for interfacing the pwm may be multiplexed with pio lines. the programmer must first program the pio controller to assign the desire d pwm pins to their peripheral function. if i/o lines of the pwm are not used by the applicati on, they can be used for other purposes by the pio controller. pwm controller apb pwmx pwmx pwmx channel update duty cycle counter pwm0 channel pio interrupt controller pmc mck clock generator apb interface interrupt generator clock selector period update duty cycle counter clock selector period pwm0 pwm0 comparator comparator table 38-1. i/o line description name description type pwmx pwm waveform output for channel x output
711 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 all of the pwm outputs may or may not be enabled. if an application requires only four channels, then only four pio lines will be assigned to pwm outputs. 38.5.2 power management the pwm is not continuously clocked. the programmer must first enable the pwm clock in the power management controller (pmc) before using the pwm. however, if the application does not require pwm operations, the pwm clock can be stopped when not needed and be restarted later. in this case, th e pwm will resume its operat ions where it left off. configuring the pwm does not require the pwm clock to be enabled. 38.5.3 interrupt sources the pwm interrupt line is connected on one of the internal sources of the interrupt controller. using the pwm interrupt requires the interrupt controller to be programmed first. note that it is not recommended to use the pwm interrupt line in edge sensitive mode. 38.6 functional description the pwm macrocell is primarily composed of a clock generator module and 4 channels. C clocked by the system clock, mck, the clock generator module provides 13 clocks. C each channel can independently choose one of the clock generator outputs. C each channel generates an output waveform with attributes that can be defined independently for each channel through the user interface registers. table 38-2. i/o lines instance signal i/o line peripheral pwm pwm0 pb11 b pwm pwm0 pc10 c pwm pwm0 pc18 c pwm pwm1 pb12 b pwm pwm1 pc11 c pwm pwm1 pc19 c pwm pwm2 pb13 b pwm pwm2 pc20 c pwm pwm3 pb14 b pwm pwm3 pc21 c table 38-3. peripheral ids instance id pwm 18
712 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 38.6.1 pwm clock generator figure 38-2. functional view of the clock generator block diagram caution: before using the pwm macrocell, the pr ogrammer must first enable the pwm clock in the power management controller (pmc). the pwm macrocell master clock, mck, is divide d in the clock generator module to provide dif- ferent clocks available for all channels. each channel can independently select one of the divided clocks. the clock generator is divided in three blocks: C a modulo n counter which provides 11 clocks: f mck , f mck /2, f mck /4, f mck /8, f mck /16, f mck /32, f mck /64, f mck /128, f mck /256, f mck /512, f mck /1024 C two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clka and clkb each linear divider can independently divide one of the clocks of the modulo n counter. the selection of the clock to be divided is made ac cording to the prea (preb) field of the pwm mode register (pwm_mr). the resulting clock clka (clkb) is the clock selected divided by diva (divb) field value in the pwm mode register (pwm_mr). after a reset of the pwm controller, diva (divb) and prea (preb) in the pwm mode register are set to 0. this implies that after reset clka (clkb) are turned off. modulo n counter mck mck/2 mck/4 mck/16 mck/32 mck/64 mck/8 divider a clka diva pwm_mr mck mck/128 mck/256 mck/512 mck/1024 prea divider b clkb divb pwm_mr preb
713 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 at reset, all clocks provided by the modulo n counter are turned off except clock clk. this situa- tion is also true when the pwm master cl ock is turned off through the power management controller. 38.6.2 pwm channel 38.6.2.1 block diagram figure 38-3. functional view of the channel block diagram each of the 4 channels is composed of three blocks: ? a clock selector which selects one of the clocks provided by the clock generator described in section 38.6.1 pwm clock generator on page 712 . ? an internal counter clocked by the output of the clock selector. this internal counter is incremented or decremented according to the channel configuration and comparators events. the size of the internal counter is 32 bits. ? a comparator used to generate events according to the internal counter value. it also computes the pwmx output waveform according to the configuration. 38.6.2.2 waveform properties the different properties of output waveforms are: ? the internal clock selection . the internal channel counter is clocked by one of the clocks provided by the clock generator described in the previous section. this channel parameter is defined in the cpre field of the pwm_cmrx register. this field is reset at 0. ? the waveform period . this channel parameter is defined in the cprd field of the pwm_cprdx register. - if the waveform is left aligned, then the output waveform period depends on the counter source clock and can be calculated: by using the master clock (mck) divided by an x given prescaler value (with x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be: by using a master clock divided by one of both diva or divb divider, the formula becomes, respectively: or if the waveform is center aligned then the output waveform period depends on the counter compar ator pwmx output w a veform intern al counter clock selector inputs from clock gener ator inputs from apb bus channel xcprd () mck -------------------------------- x * cprd * diva () mck --------------------------------------------- - x * cprd * divb () mck --------------------------------------------- -
714 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 source clock and can be calculated: by using the master clock (mck) divided by an x given prescaler value (with x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024 ). the resulting period formula will be: by using a master clock divided by one of both diva or divb divider, the formula becomes, respectively: or ? the waveform duty cycle . this channel parameter is defined in the cdty field of the pwm_cdtyx register. if the waveform is left aligned then: if the waveform is center aligned, then: ? the waveform polarity. at the beginning of the period, the signal can be at high or low level. this property is defined in the cpol field of the pwm_cmrx register. by default the signal starts by a low level. ? the waveform alignment . the output waveform can be left or center aligned. center aligned waveforms can be used to generate non overlapped waveforms. this property is defined in the calg field of the pwm_cmrx register. the default mode is left aligned. figure 38-4. non overlapped center aligned waveforms note: 1. see figure 38-5 on page 716 for a detailed description of center aligned waveforms. when center aligned, the internal channel counter increases up to cprd and.decreases down to 0. this ends the period. when left aligned, the internal channel counter increases up to cprd and is reset. this ends the period. thus, for the same cprd value, the period for a ce nter aligned channel is twice the period for a left aligned channel. 2 xcprd () mck ------------------------------------------ - 2*x * cprd * diva () mck --------------------------------------------------- - 2*x * cprd * divb () mck --------------------------------------------------- - duty cycle period 1 fchannel_x_clock cdty ? ? () period ----------------------------------------------------------------------------------------------------------- - = duty cycle period 2 ? () 1 fchannel_x_clock cdty ? ? () ) period 2 ? () ------------------------------------------------------------------------------------------------------------------------------ = pwm0 pwm1 period no overlap
715 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 waveforms are fixed at 0 when: ? cdty = cprd and cpol = 0 ? cdty = 0 and cpol = 1 waveforms are fixed at 1 (once the channel is enabled) when: ? cdty = 0 and cpol = 0 ? cdty = cprd and cpol = 1 the waveform polarity must be set before enabling the channel. this immediately affects the channel output level. changes on channel polari ty are not taken into account while the channel is enabled.
716 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 38-5. waveform properties pwm_mckx chidx(pwm_sr) center aligned cprd(pwm_cprdx) cdty(pwm_cdtyx) pwm_ccntx output waveform pwmx cpol(pwm_cmrx) = 0 output waveform pwmx cpol(pwm_cmrx) = 1 chidx(pwm_isr) left aligned cprd(pwm_cprdx) cdty(pwm_cdtyx) pwm_ccntx output waveform pwmx cpol(pwm_cmrx) = 0 output waveform pwmx cpol(pwm_cmrx) = 1 chidx(pwm_isr) calg(pwm_cmrx) = 0 calg(pwm_cmrx) = 1 period period chidx(pwm_ena) chidx(pwm_dis)
717 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 38.6.3 pwm controller operations 38.6.3.1 initialization before enabling the output channel, this chann el must have been configured by the software application: ? configuration of the clock generator if diva and divb are required ? selection of the clock for each channel (cpre field in the pwm_cmrx register) ? configuration of the waveform alignment for each channel (calg field in the pwm_cmrx register) ? configuration of the period for each channel (cprd in the pwm_cprdx register). writing in pwm_cprdx register is possible while the channel is disabled. after validation of the channel, the user must use pwm_cupdx register to update pwm_cprdx as explained below. ? configuration of the duty cycl e for each channel (cdty in the pwm_cdtyx register). writing in pwm_cdtyx register is possible while the channel is disabled. after validation of the channel, the user must use pwm_cupdx register to update pwm_cdtyx as explained below. ? configuration of the output waveform polarity for each channel (cpol in the pwm_cmrx register) ? enable interrupts (writing chidx in the pwm_ier register) ? enable the pwm channel (writing chidx in the pwm_ena register) it is possible to synchronize different channels by enabling them at the same time by means of writing simultaneously several chidx bits in the pwm_ena register. ? in such a situation, all channels may have the same clock selector configuration and the same period specified. 38.6.3.2 source clock selection criteria the large number of source clocks can make selection difficult. the relationship between the value in the period register (pwm_cprdx) and the duty cycle register (pwm_cdtyx) can help the user in choosing. the event number written in the period register gives the pwm accu- racy. the duty cycle quantum cannot be lower than 1/pwm_cprdx value. the higher the value of pwm_cprdx, the greater the pwm accuracy. for example, if the user sets 15 (in decimal) in pwm_cprdx, the user is able to set a value between 1 up to 14 in pwm_cdtyx register. the resulting duty cycle quantum cannot be lower than 1/15 of the pwm period. 38.6.3.3 changing the duty cycle or the period it is possible to modulate the output waveform duty cycle or period. to prevent unexpected output waveform, the user must use the update register (pwm_cupdx) to change waveform parameters while the channel is still enabled. the user can write a new period value or duty cycle value in the update re gister (pwm_cupdx). this register holds the new value until the end of the current cycle and updates the value for the next cycle. depending on the cpd field in the pwm_cmrx regist er, pwm_cupdx either updates pwm_cprdx or pwm_cdtyx. note that even if the update register is used, the period must not be smaller than the duty cycle.
718 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 38-6. synchronized period or duty cycle update to prevent overwriting the pwm_cupdx by software , the user can use status events in order to synchronize his software. two methods are possibl e. in both, the user must enable the dedi- cated interrupt in pwm_ier at pwm controller level. the first method ( polling method) consists of reading the relevant status bit in pwm_isr regis- ter according to the enabled channel(s). see figure 38-7 . the second method uses an interrupt service routine associated with the pwm channel. note: reading the pwm_isr register automatically clears chidx flags. figure 38-7. polling method note: polarity and alignment can be modified only when the channel is disabled. pwm_cupdx value pwm_cprdx pwm_cdtyx end of cycle pwm_cmrx. cpd user's writing 1 0 writing in pwm_cupdx the last write has been taken into account chidx = 1 writing in cpd field update of the period or duty cycle pwm_isr read acknowledgement and clear previous register state yes
719 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 38.6.3.4 interrupts depending on the interrupt mask in the pwm_imr register, an interrupt is generated at the end of the corresponding channel period. the interrupt remains active until a read operation in the pwm_isr register occurs. a channel interrupt is enabled by setting the corresponding bit in the pwm_ier register. a chan- nel interrupt is disabled by setting the corresponding bit in the pwm_idr register.
720 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 38.7 pulse width modulation controller (pwm) user interface 2. some registers are indexed with ch_num index ranging from 0 to 3. table 38-4. register mapping (2) offset register name access reset 0x00 pwm mode register pwm_mr read-write 0 0x04 pwm enable register pwm_ena write-only - 0x08 pwm disable register pwm_dis write-only - 0x0c pwm status register pwm_sr read-only 0 0x10 pwm interrupt enable register pwm_ier write-only - 0x14 pwm interrupt disable register pwm_idr write-only - 0x18 pwm interrupt mask register pwm_imr read-only 0 0x1c pwm interrupt status register pwm_isr read-only 0 0x20 - 0xfc reserved C C C 0x100 - 0x1fc reserved 0x200 + ch_num * 0x20 + 0x00 pwm channel mode register pwm_cmr read-write 0x0 0x200 + ch_num * 0x20 + 0x04 pwm channel duty cycle register pwm_cdty read-write 0x0 0x200 + ch_num * 0x20 + 0x08 pwm channel period register pwm_cprd read-write 0x0 0x200 + ch_num * 0x20 + 0x0c pwm channel counter register pwm_ccnt read-only 0x0 0x200 + ch_num * 0x20 + 0x10 pwm channel update register pwm_cupd write-only -
721 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 38.7.1 pwm mode register name: pwm_mr address: 0xf8034000 access: read/write ? diva, divb: clka, clkb divide factor ? prea, preb values which are not listed in the table must be considered as reserved. 31 30 29 28 27 26 25 24 CCCC p r e b 23 22 21 20 19 18 17 16 divb 15 14 13 12 11 10 9 8 CCCC p r e a 76543210 diva value name description 0 clk_off clka, clkb clock is turned off 1 clk_div1 clka, clkb clock is clock selected by prea, preb 2-255 C clka, clkb clock is clock selected by prea, preb divided by diva, divb factor. value name description 0000 mck master clock 0001 mckdiv2 master clock divided by 2 0010 mckdiv4 master clock divided by 4 0011 mckdiv8 master clock divided by 8 0100 mckdiv16 master clock divided by 16 0101 mckdiv32 master clock divided by 32 0110 mckdiv64 master clock divided by 64 0111 mckdiv128 master clock divided by 128 1000 mckdiv256 master clock divided by 256 1001 mckdiv512 master clock divided by 512 1010 mckdiv1024 master clock divided by 1024
722 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 38.7.2 pwm enable register name: pwm_ena address: 0xf8034004 access: write-only ? chidx: channel id 0 = no effect. 1 = enable pwm output for channel x. 38.7.3 pwm disable register name: pwm_dis address: 0xf8034008 access: write-only ? chidx: channel id 0 = no effect. 1 = disable pwm output for channel x. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCc h i d 3c h i d 2c h i d 1c h i d 0 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCc h i d 3c h i d 2c h i d 1c h i d 0
723 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 38.7.4 pwm status register name: pwm_sr address: 0xf803400c access: read-only ? chidx: channel id 0 = pwm output for channel x is disabled. 1 = pwm output for channel x is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCc h i d 3c h i d 2c h i d 1c h i d 0
724 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 38.7.5 pwm interrupt enable register name: pwm_ier address: 0xf8034010 access: write-only ? chidx: channel id. 0 = no effect. 1 = enable interrupt for pwm channel x. 38.7.6 pwm interrupt disable register name: pwm_idr address: 0xf8034014 access: write-only ? chidx: channel id. 0 = no effect. 1 = disable interrupt for pwm channel x. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCc h i d 3c h i d 2c h i d 1c h i d 0 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCc h i d 3c h i d 2c h i d 1c h i d 0
725 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 38.7.7 pwm interrupt mask register name: pwm_imr address: 0xf8034018 access: read-only ? chidx: channel id. 0 = interrupt for pwm channel x is disabled. 1 = interrupt for pwm channel x is enabled. 38.7.8 pwm interrupt status register name: pwm_isr address: 0xf803401c access: read-only ? chidx: channel id 0 = no new channel period has been achieved si nce the last read of the pwm_isr register. 1 = at least one new channel period has been achiev ed since the last read of the pwm_isr register. note: reading pwm_isr automa tically clears chidx flags. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCc h i d 3c h i d 2c h i d 1c h i d 0 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCc h i d 3c h i d 2c h i d 1c h i d 0
726 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 38.7.9 pwm channel mode register name: pwm_cmr[0..3] addresses: 0xf8034200 [0], 0xf8034220 [1], 0xf8034240 [2], 0xf8034260 [3] access: read/write ? cpre: channel pre-scaler values which are not listed in the table must be considered as reserved. ? calg: channel alignment 0 = the period is left aligned. 1 = the period is center aligned. ? cpol: channel polarity 0 = the output waveform starts at a low level. 1 = the output waveform starts at a high level. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCc p dc p o lc a l g 76543210 CCCC c p r e value name description 0000 mck master clock 0001 mckdiv2 master clock divided by 2 0010 mckdiv4 master clock divided by 4 0011 mckdiv8 master clock divided by 8 0100 mckdiv16 master clock divided by 16 0101 mckdiv32 master clock divided by 32 0110 mckdiv64 master clock divided by 64 0111 mckdiv128 master clock divided by 128 1000 mckdiv256 master clock divided by 256 1001 mckdiv512 master clock divided by 512 1010 mckdiv1024 master clock divided by 1024 1011 clka clock a 1100 clkb clock b
727 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? cpd: channel update period 0 = writing to the pwm_cupdx will modify the duty cycle at the next period start event. 1 = writing to the pwm_cupdx will modify th e period at the next period start event.
728 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 38.7.10 pwm channel duty cycle register name: pwm_cdty[0..3] addresses: 0xf8034204 [0], 0xf8034224 [1], 0xf8034244 [2], 0xf8034264 [3] access: read/write only the first 32 bits (internal ch annel counter size) are significant. ? cdty: channel duty cycle defines the waveform duty cycle. this value must be defined between 0 and cprd (pwm_cprx). 31 30 29 28 27 26 25 24 cdty 23 22 21 20 19 18 17 16 cdty 15 14 13 12 11 10 9 8 cdty 76543210 cdty
729 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 38.7.11 pwm channel period register name: pwm_cprd[0..3] addresses: 0xf8034208 [0], 0xf8034228 [1], 0xf8034248 [2], 0xf8034268 [3] access: read/write only the first 32 bits (internal ch annel counter size) are significant. ? cprd: channel period if the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be calculated: C by using the master clock (mck) divided by an x given prescaler value (with x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). the resu lting period formula will be: C by using a master clock divided by one of both diva or divb divider, the formula becomes, respectively: or if the waveform is center-aligned, then the output waveform period depends on the counter source clock and can be calculated: C by using the master clock (mck) divided by an x given prescaler value (with x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024) . the resulting pe riod formula will be: C by using a master clock divided by one of both diva or divb divider, the formula becomes, respectively: or 31 30 29 28 27 26 25 24 cprd 23 22 21 20 19 18 17 16 cprd 15 14 13 12 11 10 9 8 cprd 76543210 cprd xcprd () mck -------------------------------- crpd diva () mck ------------------------------------------- crpd divab () mck ----------------------------------------------- 2 xcprd () mck ------------------------------------------ - 2 cprd diva () mck ----------------------------------------------------- - 2 cprd divb () mck ----------------------------------------------------- -
730 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 38.7.12 pwm channel counter register name: pwm_ccnt[0..3] addresses: 0xf803420c [0], 0xf803422c [1], 0xf803424c [2], 0xf803426c [3] access: read-only ? cnt: channel counter register internal counter value. this register is reset when: ? the channel is enabled (writing chidx in the pwm_ena register). ? the counter reaches cprd value defined in the pwm_ cprdx register if the waveform is left aligned. 31 30 29 28 27 26 25 24 cnt 23 22 21 20 19 18 17 16 cnt 15 14 13 12 11 10 9 8 cnt 76543210 cnt
731 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 38.7.13 pwm channel update register name: pwm_cupd[0..3] addresses: 0xf8034210 [0], 0xf8034230 [1], 0xf8034250 [2], 0xf8034270 [3] access: write-only ? cupd: channel update register this register acts as a double buffer for the period or the duty cycle. this prevents an unexpected waveform when modify- ing the waveform period or duty-cycle. only the first 32 bits (internal ch annel counter size) are significant. when cpd field of pwm_cmrx register = 0, the duty-cycle (cdty of pwm_cdtyx register) is updated with the cupd value at the beginning of the next period. when cpd field of pwm_cmrx register = 1, the period (cpr d of pwm_cprdx register) is updated with the cupd value at the beginning of the next period. 31 30 29 28 27 26 25 24 cupd 23 22 21 20 19 18 17 16 cupd 15 14 13 12 11 10 9 8 cupd 76543210 cupd
732 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12
733 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 733 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 39. two-wire interface (twi) 39.1 description the atmel two-wire interface (twi) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 kbits per second, based on a byte-oriented transfer format. it can be used with any atmel two-wire interface bus serial eeprom and i2c compatible device such as real time clock (rtc), dot matrix/graphic lcd controllers and temperature sensor, to name but a few. the twi is programmable as a master or a slave with sequential or single-byte acce ss. multiple master capability is supported. 20 arbitration of the bus is performed internally and puts the twi in slave mode automatically if the bus arbitration is lost. a configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies. below, table 39-1 lists the compatibility level of the atme l two-wire interface in master mode and a full i 2 c compatible device. note: 1. start + b000000001 + ack + sr 39.2 embedded characteristics ? two twis ? compatible with atmel two-wire interface serial memory and i2c compatible devices (1) ? one, two or three bytes for slave address ? sequential read-write operations ? master, multi-master and slave mode operation ? bit rate: up to 400 kbits ? general call supported in slave mode ? smbus quick command supported in master mode ? connection to dma controller (d mac) channel capabilities optimizes data transfers in master mode only note: 1. see table 39-1 for details on compatibility with i2c standard. table 39-1. atmel twi compatibility with i 2 c standard i 2 c standard atmel twi standard mode speed (100 khz) supported fast mode speed (400 khz) supported 7 or 10 bits slave addressing supported start byte (1) not supported repeated start (sr) condition supported ack and nack management supported slope control and input filtering (fast mode) not supported clock stretching supported multi master capability supported
734 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 734 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 39.3 list of abbreviations 39.4 block diagram figure 39-1. block diagram table 39-2. abbreviations abbreviation description twi two-wire interface a acknowledge na non acknowledge ps t o p ss t a r t sr repeated start sadr slave address adr any address except sadr r read ww r i t e apb bridge pmc mck two-wire interface pio interrupt controller twi interrupt twck twd
735 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 735 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 39.5 application block diagram figure 39-2. application block diagram 39.5.1 i/o lines description 39.6 product dependencies 39.6.1 i/o lines both twd and twck are bidirectional lines, connect ed to a positive supply voltage via a current source or pull-up resistor (see figure 39-2 on page 735 ). when the bus is free, both lines are high. the output stages of devices connected to the bus must have an open-drain or open-col- lector to perform the wired-and function. twd and twck pins may be multiplexed with pi o lines. to enable the twi, the programmer must perform the following step: ? program the pio controller to dedicate twd and twck as peripheral lines. the user must not program twd and twck as open-drain. it is already done by the hardware. host with twi interface twd twck atmel twi serial eeprom i2c rtc i2c lcd controller slave 1 slave 2 slave 3 vdd i2c temp. sensor slave 4 rp: pull up value as given by the i2c standard rp rp table 39-3. i/o lines description pin name pin description type twd two-wire serial data input/output twck two-wire serial clock input/output table 39-4. i/o lines instance signal i/o line peripheral twi0 twck0 pa31 a twi0 twd0 pa30 a twi1 twck1 pc1 c twi1 twd1 pc0 c
736 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 736 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 39.6.2 power management ? enable the peripheral clock. the twi interface may be clocked through the power management controller (pmc), thus the programmer must first configure the pmc to enable the twi clock. 39.6.3 interrupt the twi interface has an interrupt line connected to the interrupt controller. in order to handle interrupts, the interrupt controller must be programmed before configuring the twi. 39.7 functional description 39.7.1 transfer format the data put on the twd line must be 8 bits long. data is transferred msb first; each byte must be followed by an acknowledgement. the number of bytes per transfer is unlimited (see figure 39-4 ). each transfer begins with a start condition and terminates with a stop condition (see figure 39-3 ). ? a high-to-low transition on the twd line while twck is high defines the start condition. ? a low-to-high transition on the twd line while twck is high defines a stop condition. figure 39-3. start and stop conditions figure 39-4. transfer format 39.7.2 modes of operation the twi has different modes of operations: ? master transmitter mode ? master receiver mode table 39-5. peripheral ids instance id twi0 9 twi1 10 twd twck start stop twd twck start address r/w ack data ack data ack stop
737 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 737 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? multi-master transmitter mode ? multi-master receiver mode ? slave transmitter mode ? slave receiver mode these modes are described in the following chapters. 39.8 master mode 39.8.1 definition the master is the device that starts a transfer, generates a clock and stops it. 39.8.2 application block diagram figure 39-5. master mode typical application block diagram 39.8.3 programming master mode the following registers have to be programmed before entering master mode: 1. dadr (+ iadrsz + iadr if a 10 bit device is addressed): the device address is used to access slave devices in read or write mode. 2. ckdiv + chdiv + cldiv: clock waveform. 3. svdis: disable the slave mode. 4. msen: enable the master mode. 39.8.4 master transmitter mode after the master initiates a start condition when writing into the tran smit holding register, twi_thr, it sends a 7-bit slave address, configured in the master mode register (dadr in twi_mmr), to notify the slave device. the bit following the slave address indicates the transfer direction, 0 in this case (mread = 0 in twi_mmr). the twi transfers require the slave to acknowledge each received byte. during the acknowl- edge clock pulse (9th pulse), the master releases the data line (high), enabling the slave to pull it down in order to generate the acknowledge. the master polls the data line during this clock pulse and sets the not acknowledge bit ( nack) in the status register if the slave does not host with twi interface twd twck atmel twi serial eeprom i2c rtc i2c lcd controller slave 1 slave 2 slave 3 vdd i2c temp. sensor slave 4 rp: pull up value as given by the i2c standard rp rp
738 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 738 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 acknowledge the byte. as with the other status bits, an interrupt can be generated if enabled in the interrupt enable register (twi_ier). if the slave acknowledges the byte, the data written in the twi_thr, is then shifted in the internal shifter and transferred. when an acknowledge is detected, the txrdy bit is set until a new write in the twi_thr. while no new data is writ ten in the twi_thr, the serial clock line is tied low. when new data is written in the twi_thr, the scl is released and the data is sent. to generate a stop event, the stop command must be performed by writing in the stop field of twi_cr. after a master write transfer, the serial clock line is stretched (tied low) while no new data is written in the twi_thr or until a stop command is performed. see figure 39-6 , figure 39-7 , and figure 39-8 . figure 39-6. master write with one data byte figure 39-7. master write with mu ltiple data bytes txcomp txrdy write thr (data) stop command sent (write in twi_cr) twd a data a s dadr w p a data n a s dadr w data n+1 a p data n+2 a txcomp txrdy write thr (data n) write thr (data n+1) write thr (data n+2) last data sent stop command performed (by writing in the twi_cr) twd twck
739 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 739 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 39-8. master write with one byte internal address and multiple data bytes 39.8.5 master receiver mode the read sequence begins by setting the start bit. after the start condition has been sent, the master sends a 7-bit slave address to notify th e slave device. the bit following the slave address indicates the transfer direction, 1 in this ca se (mread = 1 in twi_mmr). during the acknowl- edge clock pulse (9th pulse), the master releases the data line (high), enabling the slave to pull it down in order to generate the acknowledge. the master polls the data line during this clock pulse and sets the nack bit in the status register if the slave does not acknowledge the byte. if an acknowledge is received, the master is then ready to receive data from the slave. after data has been received, the master sends an acknowle dge condition to notify the slave that the data has been received except for the last data, after the stop condition. see figure 39-9 . when the rxrdy bit is set in the status register, a character has been received in the receive-holding reg- ister (twi_rhr). the rxrdy bit is reset when reading the twi_rhr. when a single data byte read is performed, with or without internal address (iadr ), the start and stop bits must be set at the same time. see figure 39-9 . when a multiple data byte read is performed, with or without internal address (iadr ), the stop bit must be set after the next-to- last data received. see figure 39-10 . for internal address usage see section 39.8.6 . figure 39-9. master read with one data byte a data n a s dadr w data n+1 a p data n+2 a txcomp txrdy write thr (data n) write thr (data n+1) write thr (data n+2) last data sent stop command performed (by writing in the twi_cr) twd iadr a twck a s dadr r data n p txcomp write start & stop bit rxrdy read rhr twd
740 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 740 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 39-10. master read with mu ltiple data bytes 39.8.6 internal address the twi interface can perform various transfe r formats: transfers with 7-bit slave address devices and 10-bit slave address devices. 39.8.6.1 7-bit slave addressing when addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write) accesses to reach one or more data bytes, within a memory page loca- tion in a serial memory, for example. when performing read operations with an internal address, the twi performs a write operation to set the internal address into the slave device, and then switch to master receiver mode. note that the second start condition (after sending the iadr) is sometimes called repeat ed start (sr) in i 2 c fully-compatible devices. see figure 39-12 . see figure 39-11 and figure 39-13 for master write operation with internal address. the three internal address bytes are configurable through the master mode register (twi_mmr). if the slave device supports only a 7-bit address, i.e. no internal address, iadrsz must be set to 0. in the figures below the following abbreviations are used: n a s dadr r data n a a data (n+1) a data (n+m) data (n+m)-1 p twd txcomp write start bit rxrdy write stop bit after next-to-last data read read rhr data n read rhr data (n+1) read rhr data (n+m)-1 read rhr data (n+m) ?s start ?sr repeated start ?p stop ?w write ?r read ?a acknowledge ?n not acknowledge ?dadr device address ?iadr internal address
741 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 741 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 39-11. master write with one, two or three bytes internal address and one data byte figure 39-12. master read with one, two or three bytes internal address and one data byte 39.8.6.2 10-bit slave addressing for a slave address higher than 7 bits, the user must configure the address size (iadrsz ) and set the other slave address bits in the internal address register (twi_iadr). the two remaining internal address bytes, iadr[15:8] and iadr[23:16] can be used the same as in 7-bit slave addressing. example: address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10) 1. program iadrsz = 1, 2. program dadr with 1 1 1 1 0 b1 b2 (b1 is the msb of the 10-bit address, b2, etc.) 3. program twi_iadr with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the lsb of the 10-bit address) figure 39-13 below shows a byte write to an atmel at24lc512 eeprom. this demonstrates the use of internal addresses to access the device. figure 39-13. internal address usage s dadr w a iadr(23:16) a iadr(15:8) a iadr(7:0) a data a p s dadr w a iadr(15:8) a iadr(7:0) a p data a a iadr(7:0) a p data a s dadr w twd three bytes internal address two bytes internal address one byte internal address twd twd s dadr w a iadr(23:16) a iadr(15:8) a iadr(7:0) a s dadr w a iadr(15:8) a iadr(7:0) a a iadr(7:0) a s dadr w data n p sr dadr r a sr dadr r a data n p sr dadr ra data np twd twd twd three bytes internal address two bytes internal address one byte internal address s t a r t m s b device address 0 l s b r / w a c k m s b w r i t e a c k a c k l s b a c k first word address second word address data s t o p
742 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 742 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 39.8.7 using the dma controller (dmac) the use of the dmac significantly reduces the cpu load. to assure correct implementation, respect the following programming sequence. 1. initialize the dmac (channels, memory pointers, size, etc.); 2. configure the master mode (dadr, ckdiv, etc.). 3. enable the dmac. 4. wait for the dmac flag. 5. disable the dmac. 39.8.8 smbus quick command (master mode only) the twi interface can perform a quick command: 1. configure the master mode (dadr, ckdiv, etc.). 2. write the mread bit in the twi_mmr register at the value of the one-bit command to be sent. 3. start the transfer by setting the quick bit in the twi_cr. figure 39-14. smbus quick command 39.8.9 read-write flowcharts the following flowcharts shown in figure 39-16 on page 744 , figure 39-17 on page 745 , figure 39-18 on page 746 , figure 39-19 on page 747 and figure 39-20 on page 748 give examples for read and write operations. a polling or interrupt method can be used to check the status bits. the interrupt method requires that the interrupt enable register (twi_ier) be configured first. txcomp txrdy write quick command in twi_cr twd a s dadr r/w p
743 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 743 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 39-15. twi write operation with single data byte without internal address set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once) set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address (dadr) - transfer direction bit write ==> bit mread = 0 load transmit register twi_thr = data to send read status register txrdy = 1? read status register txcomp = 1? transfer finished ye s ye s begin no no write stop command twi_cr = stop
744 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 744 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 39-16. twi write operation with single data byte and internal address begin set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once) set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address (dadr) - internal address size (iadrsz) - transfer direction bit write ==> bit mread = 0 load transmit register twi_thr = data to send read status register txrdy = 1? read status register txcomp = 1? transfer finished set the internal address twi_iadr = address yes yes no no write stop command twi_cr = stop
745 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 745 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 39-17. twi write operation with multiple data bytes with or without internal address set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address - internal address size (if iadr used) - transfer direction bit write ==> bit mread = 0 internal address size = 0? load transmit register twi_thr = data to send read status register txrdy = 1? data to send? read status register txcomp = 1? end begin set the internal address twi_iadr = address ye s twi_thr = data to send ye s ye s ye s no no no write stop command twi_cr = stop set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once)
746 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 746 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 39-18. twi read operation with single data byte without internal address set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address - transfer direction bit read ==> bit mread = 1 start the transfer twi_cr = start | stop read status register rxrdy = 1? read status register txcomp = 1? end begin ye s ye s set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once) read receive holding register no no
747 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 747 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 39-19. twi read operation with single data byte and internal address set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address - internal address size (iadrsz) - transfer direction bit read ==> bit mread = 1 read status register txcomp = 1? end begin ye s set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once) ye s set the internal address twi_iadr = address start the transfer twi_cr = start | stop read status register rxrdy = 1? read receive holding register no no
748 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 748 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 39-20. twi read operation with multiple data bytes with or without internal address internal address size = 0? start the transfer twi_cr = start stop the transfer twi_cr = stop read status register rxrdy = 1? last data to read but one? read status register txcomp = 1? end set the internal address twi_iadr = address ye s ye s ye s no ye s read receive holding register (twi_rhr) no set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address - internal address size (if iadr used) - transfer direction bit read ==> bit mread = 1 begin set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once) no read status register rxrdy = 1? ye s read receive holding register (twi_rhr) no
749 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 749 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 39.9 multi-master mode 39.9.1 definition more than one master may handle the bus at the same time without data corruption by using arbitration. arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. as soon as arbitration is lost by a master, it st ops sending data and listens to the bus in order to detect a stop. when the stop is detected, the master who has lost arbitration may put its data on the bus by respecting arbitration. arbitration is illustrated in figure 39-22 on page 750 . 39.9.2 different multi-master modes two multi-master modes may be distinguished: 1. twi is considered as a master only and will never be addressed. 2. twi may be either a master or a slave and may be addressed. note: in both multi-master modes arbitration is supported. 39.9.2.1 twi as master only in this mode, twi is considered as a master only (msen is always at one) and must be driven like a master with the arblst (arbitration lost) flag in addition. if arbitration is lost (arblst = 1), the programmer must reinitiate the data transfer. if the user starts a transfer (ex.: dadr + start + w + write in thr) and if the bus is busy, the twi automatically waits for a stop conditi on on the bus to initiate the transfer (see figure 39- 21 on page 750 ). note: the state of the bus (busy or free) is not indicated in the user interface. 39.9.2.2 twi as master or slave the automatic reversal from master to slave is not supported in case of a lost arbitration. then, in the case where twi may be either a master or a slave, the programmer must manage the pseudo multi-master mode described in the steps below. 1. program twi in slave mode (sadr + ms dis + sven) and perform slave access (if twi is addressed). 2. if twi has to be set in master mode, wait until txcomp flag is at 1. 3. program master mode (dadr + svdis + msen ) and start the transfer (ex: start + write in thr). 4. as soon as the master mode is enabled, twi scans the bus in order to detect if it is busy or free. when the bus is considered as free, twi initiates the transfer. 5. as soon as the transfer is initiated and until a stop condition is sent, the arbitration becomes relevant and the user must monitor the arblst flag. 6. if the arbitration is lost (arblst is set to 1), the user must program the twi in slave mode in the case where the master that won the arbitration wanted to access the twi. 7. if twi has to be set in slave mode, wait until txcomp flag is at 1 and then program the slave mode.
750 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 750 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 note: in the case where the arbitration is lost and tw i is addressed, twi will not acknowledge even if it is programmed in slave mode as soon as arblst is set to 1. then, the master must repeat sadr. figure 39-21. programmer sends data while the bus is busy figure 39-22. arbitration cases the flowchart shown in figure 39-23 on page 751 gives an example of read and write operations in multi-master mode. twck twd data sent by a master stop sent by the master start sent by the twi data sent by the twi bus is busy bus is free a transfer is programmed (dadr + w + start + write thr) transfer is initiated twi data transfer transfer is kept bus is considered as free twck bus is busy bus is free a transfer is programmed (dadr + w + start + write thr) transfer is initiated twi data transfer transfer is kept bus is considered as free data from a master data from twi s 0 s 0 0 1 1 1 arblst s 0 s 0 0 1 1 1 twd s 0 0 1 1 1 1 1 arbitration is lost twi stops sending data p s 0 1 p 0 1 1 1 1 data from the master data from the twi arbitration is lost the master stops sending data transfer is stopped transfer is programmed again (dadr + w + start + write thr) twck twd
751 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 751 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 39-23. multi-master flowchart programm the slave mode: sadr + msdis + sven svacc = 1 ? txcomp = 1 ? gacc = 1 ? decoding of the programming sequence prog seq ok ? change sadr svread = 1 ? read status register rxrdy= 1 ? read twi_rhr txrdy= 1 ? eosacc = 1 ? write in twi_thr need to perform a master access ? program the master mode dadr + svdis + msen + clk + r / w read status register arblst = 1 ? mread = 1 ? txrdy= 0 ? write in twi_thr data to send ? rxrdy= 0 ? read twi_rhr data to read? read status register txcomp = 0 ? general call treatment ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s stop transfer twi_cr = stop no no no no no no no no no no no no no no no no start
752 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 752 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 39.10 slave mode 39.10.1 definition the slave mode is defined as a mode where the device receives the clock and the address from another device called the master. in this mode, the device never initiates and never completes the transmission (start, repeated_start and stop conditions are always provided by the master). 39.10.2 application block diagram figure 39-24. slave mode typical application block diagram 39.10.3 programming slave mode the following fields must be programmed before entering slave mode: 1. sadr (twi_smr): the slave device address is used in order to be accessed by mas- ter devices in read or write mode. 2. msdis (twi_cr): disable the master mode. 3. sven (twi_cr): enable the slave mode. as the device receives the clock, values written in twi_cwgr are not taken into account. 39.10.4 receiving data after a start or repeated start condition is detected and if the address sent by the master matches with the slave addre ss programmed in the sadr (slave address) field, svacc (slave access) flag is set and svread (slave read) indicates the direction of the transfer. svacc remains high until a stop condition or a repeated start is detected. when such a condition is detected, eosacc (end of slave access) flag is set. 39.10.4.1 read sequence in the case of a read sequence (svread is high), twi transfers data written in the twi_thr (twi transmit holding register) until a stop condition or a repeated _start + an address different from sadr is detected. note that at the end of the read sequence txcomp (transmis- sion complete) flag is set and svacc reset. as soon as data is written in the twi_thr, txrdy (transmit holding register ready) flag is reset, and it is set when the shift register is empty and the sent data acknowledged or not. if the data is not acknowledged, the nack flag is set. host with twi interface twd twck lcd controller slave 1 slave 2 slave 3 rr vdd host with twi interface host with twi interface master
753 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 753 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 note that a stop or a repeated start always follows a nack. see figure 39-25 on page 754 . 39.10.4.2 write sequence in the case of a write sequence (svread is low), the rxrdy (receive holding register ready) flag is set as soon as a character has been received in the twi_rhr (twi receive holding register). rxrdy is re set when reading the twi_rhr. twi continues receiving data until a stop co ndition or a repeated_start + an address dif- ferent from sadr is detected. note that at the end of the write sequence txcomp flag is set and svacc reset. see figure 39-26 on page 754 . 39.10.4.3 clock synchronization sequence in the case where twi_thr or twi_rhr is not written/read in time, twi performs a clock synchronization. clock stretching information is given by the sclws (clock wait state) bit. see figure 39-28 on page 756 and figure 39-29 on page 757 . 39.10.4.4 general call in the case where a general call is perfor med, gacc (general call access) flag is set. after gacc is set, it is up to the programmer to interpret the meaning of the general call and to decode the new address programming sequence. see figure 39-27 on page 755 . 39.10.5 data transfer 39.10.5.1 read operation the read mode is defined as a data requirement from the master. after a start or a repeated start condition is detected, the decoding of the address starts. if the slave address (sadr) is decoded, svacc is set and svread indicates the direc- tion of the transfer. until a stop or repeated start condition is detected, twi continues sending data loaded in the twi_thr register. if a stop condition or a repeated start + an address different from sadr is detected, svacc is reset. figure 39-25 on page 754 describes the write operation.
754 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 754 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 39-25. read access ordered by a master notes: 1. when svacc is low, the state of svread becomes irrelevant. 2. txrdy is reset when data has been transmitted from twi_thr to the shift register and set when this data has been acknowledged or non acknowledged. 39.10.5.2 write operation the write mode is defined as a data transmission from the master. after a start or a repeated start, the decoding of the address starts . if the slave address is decoded, svacc is set and svread indicates the direction of the transfer (svread is low in this case). until a stop or repeated start condition is detected, twi stores the received data in the twi_rhr register. if a stop condition or a repeated start + an address different from sadr is detected, svacc is reset. figure 39-26 on page 754 describes the write operation. figure 39-26. write access ordered by a master notes: 1. when svacc is low, the state of svread becomes irrelevant. 2. rxrdy is set when data has been transmitted from the shift register to the twi_rhr and reset when this data is read. write thr read rhr svread has to be taken into account only while svacc is active twd txrdy nack svacc svread eosvacc sadr s adr r na r a data a a data na s/sr data na p/s/sr sadr matches, twi answers with an ack sadr does not match, twi answers with a nack ack/nack from the master rxrdy read rhr svread has to be taken into account only while svacc is active twd svacc svread eosvacc sadr does not match, twi answers with a nack sadr s adr w na w a data a a data na s/sr data na p/s/sr sadr matches, twi answers with an ack
755 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 755 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 39.10.5.3 general call the general call is performed in order to change the address of the slave. if a general call is detected, gacc is set. after the detection of general call, it is up to the programmer to decode the commands which come afterwards. in case of a write command, the programmer has to decode the programming sequence and program a new sadr if the programming sequence matches. figure 39-27 on page 755 describes the general call access. figure 39-27. master performs a general call note: this method allows the user to create an own programming sequence by choosing the program- ming bytes and the number of them. the programming sequence has to be provided to the master. 0000000 + w general call p s a general call reset or write dadd a new sadr data 1 a data 2 a a new sadr programming sequence txd gcacc svacc reset command = 00000110x write command = 00000100x reset after read
756 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 756 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 39.10.5.4 clock synchronization in both read and write modes, it may happen that twi_thr/tw i_rhr buffer is not filled /emp- tied before the emission/reception of a new charac ter. in this case, to avoid sending/receiving undesired data, a clock stretching mechanism is implemented. clock synchronization in read mode the clock is tied low if the shif t register is empty and if a stop or repeated start condition was not detected. it is tied low until the shift register is loaded. figure 39-28 on page 756 describes the clock synchronization in read mode. figure 39-28. clock synchronization in read mode notes: 1. txrdy is reset when data has been written in the twi_ thr to the shift register and set when this data has been acknowl- edged or non acknowledged. 2. at the end of the read sequence, txcomp is set after a stop or after a repeated_start + an address different from sadr. 3. sclws is automatically set when the cl ock synchronization mechanism is started. data 1 the clock is stretched after the ack, the state of twd is undefined during clock stretching sclws svacc svread txrdy twck twi_thr txcomp the data is memorized in twi_thr until a new value is written twi_thr is transmitted to the shift register ack or nack from the master data 0data 0 data 2 1 2 1 clock is tied low by the twi as long as thr is empty s sadr s r data 0 a a data 1 a data 2 na s xxxxxxx 2 write thr as soon as a start is detected
757 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 757 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 clock synchronization in write mode the clock is tied low if the shift regi ster and the twi_rhr is full. if a stop or repeated_start condition was not detected , it is tied low until twi_rhr is read. figure 39-29 on page 757 describes the clock synchronization in read mode. figure 39-29. clock synchronization in write mode notes: 1. at the end of the read sequence, txcomp is set after a stop or after a repeated_start + an address different from sadr. 2. sclws is automatically set when the cl ock synchronization mechanism is started and automatically reset when the mecha- nism is finished. 39.10.5.5 reversal after a repeated start reversal of read to write the master initiates the communication by a read command and finishes it by a write command. figure 39-30 on page 757 describes the repeated start + reversal from read to write mode. figure 39-30. repeated start + reversal from read to write mode 1. txcomp is only set at the end of the transmission because after the repeated start, sadr is detected again. rd data0 rd data1 rd data2 svacc svread rxrdy sclws txcomp data 1 data 2 scl is stretched on the last bit of data1 as soon as a start is detected twck twd twi_rhr clock is tied low by the twi as long as rhr is full data0 is not read in the rhr adr s sadr w a data 0 a a data 2 data 1 s na s sadr r a data 0 a data 1 sadr sr na w a data 2 a data 3 a p cleared after read data 0 data 1 data 2 data 3 svacc svread twd twi_thr twi_rhr eosacc txrdy rxrdy txcomp as soon as a start is detected
758 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 758 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 reversal of write to read the master initiates the communication by a write command and finishes it by a read command. figure 39-31 on page 758 describes the repeated start + reversal from write to read mode. figure 39-31. repeated start + reversal from write to read mode notes: 1. in this case, if twi_thr has not bee n written at the end of the read command, the clock is automatically stretched befo re the ack. 2. txcomp is only set at the end of the transmission because after the repeated st art, sadr is detected again. 39.10.6 read write flowcharts the flowchart shown in figure 39-32 on page 759 gives an example of read and write operations in slave mode. a polling or interrupt method can be used to check the status bits. the interrupt method requires that the interrupt enable register (twi_ier) be configured first. s sadr w a data 0 a data 1 sadr sr a r a data 2 a data 3 n a p cleared after read data 0 data 2 data 3 data 1 txcomp txrdy rxrdy as soon as a start is detected read twi_rhr svacc svread twd twi_rhr twi_thr eosacc
759 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 759 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 39-32. read write flowchart in slave mode set the slave mode: sadr + msdis + sven svacc = 1 ? txcomp = 1 ? gacc = 1 ? decoding of the programming sequence prog seq ok ? change sadr svread = 0 ? read status register rxrdy= 0 ? read twi_rhr txrdy= 1 ? eosacc = 1 ? write in twi_thr end general call treatment no no no no no no no no
760 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 760 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 39.11 two-wire interface (twi) user interface note: 1. all unlisted offset values are considered as reserved. table 39-6. register mapping offset register name access reset 0x00 control register twi_cr write-only n / a 0x04 master mode register twi_mmr read-write 0x00000000 0x08 slave mode register twi_smr read-write 0x00000000 0x0c internal address register twi_iadr read-write 0x00000000 0x10 clock waveform generator register twi_cwgr read-write 0x00000000 0x14 - 0x1c reserved C C C 0x20 status register twi_sr read-only 0x0000f009 0x24 interrupt enable regist er twi_ier write-only n / a 0x28 interrupt disable regist er twi_idr write-only n / a 0x2c interrupt mask register twi_imr read-only 0x00000000 0x30 receive holding register twi_rhr read-only 0x00000000 0x34 transmit holding register twi_thr write-only 0x00000000 0xec - 0xfc (1) reserved C C C
761 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 761 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 39.11.1 twi control register name: twi_cr address: 0xf8010000 (0), 0xf8014000 (1) access: write-only reset: 0x00000000 ? start: send a start condition 0 = no effect. 1 = a frame beginning with a start bit is transmitted according to the features defined in the mode register. this action is necessary when the twi peripheral wants to read data from a slave. when configured in master mode with a write operation, a frame is sent as soon as the user writes a character in the transmit holding register (twi_thr). ? stop: send a stop condition 0 = no effect. 1 = stop condition is sent just after completing the current byte transmission in master read mode. C in single data byte master read, the start and stop must both be set. C in multiple data bytes master read, the stop must be set after the last data received but one. C in master read mode, if a nack bit is received, the stop is automatically performed. C in master data write operation, a st op condition will be sent after the tr ansmission of the current data is finished. ? msen: twi master mode enabled 0 = no effect. 1 = if msdis = 0, the master mode is enabled. note: switching from slave to master mo de is only permitted when txcomp = 1. ? msdis: twi master mode disabled 0 = no effect. 1 = the master mode is disabled, all pending data is transmitted. the shifter and holding characters (if it contains data) are transmitted in case of write operation. in read operation, the character being transferred must be completely received before disabling. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 swrst quick svdis sven msdis msen stop start
762 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 762 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? sven: twi slave mode enabled 0 = no effect. 1 = if svdis = 0, the slave mode is enabled. note: switching from master to slave mode is only permitted when txcomp = 1. ? svdis: twi slave mode disabled 0 = no effect. 1 = the slave mode is disabled. the shifter and holding characte rs (if it contains data) are transmitted in case of read oper- ation. in write operation, the character being transferred must be completely received before disabling. ? quick: smbus quick command 0 = no effect. 1 = if master mode is enabled, a smbus quick command is sent. ? swrst: software reset 0 = no effect. 1 = equivalent to a system reset.
763 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 763 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 39.11.2 twi master mode register name: twi_mmr address: 0xf8010004 (0), 0xf8014004 (1) access: read-write reset: 0x00000000 ? iadrsz: internal device address size ? mread: master read direction 0 = master write direction. 1 = master read direction. ? dadr: device address the device address is used to access slave devices in read or write mode. those bits are only used in master mode. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 Cd a d r 15 14 13 12 11 10 9 8 CCCm r e a dCC i a d r s z 76543210 CCCCCCCC value name description 0 none no internal device address 1 1_byte one-byte internal device address 2 2_byte two-byte internal device address 3 3_byte three-byte internal device address
764 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 764 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 39.11.3 twi slave mode register name: twi_smr address: 0xf8010008 (0), 0xf8014008 (1) access: read-write reset: 0x00000000 ? sadr: slave address the slave device address is used in slav e mode in order to be accessed by master devices in read or write mode. sadr must be programmed before enabling the slave mode or after a general call. writes at other times have no effect. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 Cs a d r 15 14 13 12 11 10 9 8 CCCCCC 76543210 CCCCCCCC
765 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 765 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 39.11.4 twi internal address register name: twi_iadr address: 0xf801000c (0), 0xf801400c (1) access: read-write reset: 0x00000000 ? iadr: internal address 0, 1, 2 or 3 bytes depending on iadrsz. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 iadr 15 14 13 12 11 10 9 8 iadr 76543210 iadr
766 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 766 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 39.11.5 twi clock waveform generator register name: twi_cwgr address: 0xf8010010 (0), 0xf8014010 (1) access: read-write reset: 0x00000000 twi_cwgr is only used in master mode. ? cldiv: clock low divider the scl low period is defined as follows: ? chdiv: clock high divider the scl high period is defined as follows: ? ckdiv: clock divider the ckdiv is used to increase both scl high and low periods. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 ckdiv 15 14 13 12 11 10 9 8 chdiv 76543210 cldiv t low cldiv ( 2 ckdiv () 4 ) + t mck = t high chdiv ( 2 ckdiv () 4 ) + t mck =
767 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 767 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 39.11.6 twi status register name: twi_sr address: 0xf8010020 (0), 0xf8014020 (1) access: read-only reset: 0x0000f009 ? txcomp: transmission completed (automatically set / reset) txcomp used in master mode : 0 = during the length of the current frame. 1 = when both holding and shifter registers are empty and stop condition has been sent. txcomp behavior in master mode can be seen in figure 39-8 on page 739 and in figure 39-10 on page 740 . txcomp used in slave mode : 0 = as soon as a start is detected. 1 = after a stop or a repeated start + an address different from sadr is detected. txcomp behavior in slave mode can be seen in figure 39-28 on page 756 , figure 39-29 on page 757 , figure 39-30 on page 757 and figure 39-31 on page 758 . ? rxrdy: receive holding register ready (automatically set / reset) 0 = no character has been received since the last twi_rhr read operation. 1 = a byte has been received in the twi_rhr since the last read. rxrdy behavior in master mode can be seen in figure 39-10 on page 740 . rxrdy behavior in slave mode can be seen in figure 39-26 on page 754 , figure 39-29 on page 757 , figure 39-30 on page 757 and figure 39-31 on page 758 . ? txrdy: transmit holding register ready (automatically set / reset) txrdy used in master mode : 0 = the transmit holding register has not been transferred into shift register. set to 0 when writing into twi_thr register. 1 = as soon as a data byte is transferred from twi_thr to inte rnal shifter or if a nack erro r is detected, txrdy is set at the same time as txcomp and nack. txrdy is also set when msen is set (enable twi). txrdy behavior in master mode can be seen in figure 39-8 on page 739 . 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 eosacc sclws arblst nack 76543210 C ovre gacc svacc svread txrdy rxrdy txcomp
768 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 768 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 txrdy used in slave mode : 0 = as soon as data is written in the twi_thr, until this data has been transmitted and acknowledged (ack or nack). 1 = it indicates that the twi_thr is empty and that data has been transmitted and acknowledged. if txrdy is high and if a nack has been detected, the tr ansmission will be stopped. thus when trdy = nack = 1, the programmer must not fill tw i_thr to avoid losing it. txrdy behavior in slave mode can be seen in figure 39-25 on page 754 , figure 39-28 on page 756 , figure 39-30 on page 757 and figure 39-31 on page 758 . ? svread: slave read (automatically set / reset) this bit is only used in slave mode. when svacc is low (no slave access has been detected) svread is irrelevant. 0 = indicates that a write access is performed by a master. 1 = indicates that a read access is performed by a master. svread behavior can be seen in figure 39-25 on page 754 , figure 39-26 on page 754 , figure 39-30 on page 757 and figure 39-31 on page 758 . ? svacc: slave access (automatically set / reset) this bit is only used in slave mode. 0 = twi is not addressed. svacc is automatically cleared af ter a nack or a stop condition is detected. 1 = indicates that the address decoding sequence has matched (a master has sent sadr). svacc remains high until a nack or a stop condition is detected. svacc behavior can be seen in figure 39-25 on page 754 , figure 39-26 on page 754 , figure 39-30 on page 757 and fig- ure 39-31 on page 758 . ? gacc: general call access (clear on read) this bit is only used in slave mode. 0 = no general call has been detected. 1 = a general call has been detected. after the detection of general call, if need be, the programmer may acknowledge this access and decode the following bytes and respond according to the value of the bytes. gacc behavior can be seen in figure 39-27 on page 755 . ? ovre: overrun error (clear on read) this bit is only used in master mode. 0 = twi_rhr has not been loaded while rxrdy was set 1 = twi_rhr has been loaded while rxrdy was set. reset by read in twi_sr when txcomp is set. ? nack: not acknowledged (clear on read) nack used in master mode : 0 = each data byte has been correctly received by the far-end side twi slave component. 1 = a data byte has not been acknowledged by the sl ave component. set at the same time as txcomp.
769 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 769 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 nack used in slave read mode : 0 = each data byte has been correctly received by the master. 1 = in read mode, a data byte has not been acknowledged by the master. when nack is set the programmer must not fill twi_thr even if txrdy is set, because it means that the master will stop the data transfer or re initiate it. note that in slave write mode all data are acknowledged by the twi. ? arblst: arbitration lost (clear on read) this bit is only used in master mode. 0: arbitration won. 1: arbitration lost. another master of the twi bus has won the multi-master arbitration. txcomp is set at the same time. ? sclws: clock wait state (automatically set / reset) this bit is only used in slave mode. 0 = the clock is not stretched. 1 = the clock is stretched. twi_thr / twi_rhr buffer is not filled / emptied bef ore the emission / reception of a new character. sclws behavior can be seen in figure 39-28 on page 756 and figure 39-29 on page 757 . ? eosacc: end of slave access (clear on read) this bit is only used in slave mode. 0 = a slave access is being performing. 1 = the slave access is finished. end of slave access is automatically set as soon as svacc is reset. eosacc behavior can be seen in figure 39-30 on page 757 and figure 39-31 on page 758
770 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 770 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 39.11.7 twi interrupt enable register name: twi_ier address: 0xf8010024 (0), 0xf8014024 (1) access: write-only reset: 0x00000000 ? txcomp: transmission completed interrupt enable ? rxrdy: receive holding register ready interrupt enable ? txrdy: transmit holding register ready interrupt enable ? svacc: slave access interrupt enable ? gacc: general call access interrupt enable ? ovre: overrun error interrupt enable ? nack: not acknowledge interrupt enable ? arblst: arbitration lost interrupt enable ? scl_ws: clock wait state interrupt enable ? eosacc: end of slave access interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 eosacc scl_ws arblst nack 76543210 C ovre gacc svacc C txrdy rxrdy txcomp
771 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 771 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 39.11.8 twi interrupt disable register name: twi_idr address: 0xf8010028 (0), 0xf8014028 (1) access: write-only reset: 0x00000000 ? txcomp: transmission completed interrupt disable ? rxrdy: receive holding regi ster ready interrupt disable ? txrdy: transmit holding register ready interrupt disable ? svacc: slave access interrupt disable ? gacc: general call access interrupt disable ? ovre: overrun error interrupt disable ? nack: not acknowledge interrupt disable ? arblst: arbitration lost interrupt disable ? scl_ws: clock wait state interrupt disable ? eosacc: end of slave access interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 eosacc scl_ws arblst nack 76543210 C ovre gacc svacc C txrdy rxrdy txcomp
772 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 772 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 39.11.9 twi interrupt mask register name: twi_imr address: 0xf801002c (0), 0xf801402c (1) access: read-only reset: 0x00000000 ? txcomp: transmission completed interrupt mask ? rxrdy: receive holding regi ster ready interrupt mask ? txrdy: transmit holding register ready interrupt mask ? svacc: slave access interrupt mask ? gacc: general call access interrupt mask ? ovre: overrun error interrupt mask ? nack: not acknowledge interrupt mask ? arblst: arbitration lost interrupt mask ? scl_ws: clock wait state interrupt mask ? eosacc: end of slave access interrupt mask 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 eosacc scl_ws arblst nack 76543210 C ovre gacc svacc C txrdy rxrdy txcomp
773 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 773 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 39.11.10 twi receive holding register name: twi_rhr address: 0xf8010030 (0), 0xf8014030 (1) access: read-only reset: 0x00000000 ? rxdata: master or slave receive holding data 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 rxdata
774 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 774 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 39.11.11 twi transmit holding register name: twi_thr address: 0xf8010034 (0), 0xf8014034 (1) access: read-write reset: 0x00000000 ? txdata: master or slave transmit holding data 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 txdata
775 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 775 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40. universal synchronous asynchrono us receiver transmitter (usart) 40.1 description the universal synchronous asynchronous rece iver transceiver (usart) provides one full duplex universal synchronous asynchronous serial link. data frame format is widely programma- ble (data length, parity, number of stop bits) to support a maximum of standards. the receiver implements parity error, framing error and overrun error detection. the receiver time-out enables handling variable-length frames and the transmitter timeguard facilitates communications with slow remote devices. multidrop communications are also supported through address bit han- dling in reception and transmission. the usart features three test modes: remote loopback, local loopback and automatic echo. the usart supports specific operating modes providing interfaces on rs485, lin, and spi buses, with iso7816 t = 0 or t = 1 smart card slots and infrared transceivers. the hardware handshaking feature enables an out-of-band flow control by automatic management of the pins rts and cts. the usart supports the connection to the dm a controller, which enables data transfers to the transmitter and from the receiver. the dmac provides chained buffer management without any intervention of the processor. 40.2 embedded characteristics ? programmable baud rate generator ? 5- to 9-bit full-duplex synchronous or asynchronous serial communications C 1, 1.5 or 2 stop bits in asynchronous mode or 1 or 2 stop bits in synchronous mode C parity generation and error detection C framing error detection, overrun error detection C msb- or lsb-first C optional break generation and detection C by 8 or by 16 over-sampling receiver frequency C optional hardware handshaking rts-cts C receiver time-out and transmitter timeguard C optional multidrop mode with address generation and detection ? rs485 with driver control signal ? iso7816, t = 0 or t = 1 protocols for interfacing with smart cards C nack handling, error counter with repetition and iteration limit ? irda modulation and demodulation C communication at up to 115.2 kbps ? spi mode Cmaster or slave C serial clock programmab le phase and polarity C spi serial clock (sck) frequency up to internal clock frequency mck/6 ? lin mode C compliant with lin 1.3 and lin 2.0 specifications
776 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 776 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 Cmaster or slave C processing of frames with up to 256 data bytes C response data length can be configurable or defined automatically by the identifier C self synchronization in slave node configuration C automatic processing and verification of the synch break and the synch field C the synch break is detected even if it is partially superimposed with a data byte C automatic identifier parity calculation/sending and verification C parity sending and verification can be disabled C automatic checksum calculation/sending and verification C checksum sending and verification can be disabled C support both classic and enhanced checksum types C full lin error checking and reporting C frame slot mode: the master allocates slots to the scheduled frames automatically. C generation of the wakeup signal ? test modes C remote loopback, local loopback, automatic echo ? supports connection of: C two dma controller channels (dmac) ? offers buffer transfer without processor intervention
777 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 777 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.3 block diagram figure 40-1. usart block diagram table 40-1. spi operating mode pin usart spi slave spi master rxd rxd mosi miso txd txd miso mosi rts rts C cs cts cts cs C (peripheral) dma controller channel channel interrupt controller receiver usart interrupt rxd txd sck usart pio controller cts rts transmitter baud rate generator user interface pmc mck slck div mck/div apb
778 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 778 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.4 application block diagram figure 40-2. application block diagram 40.5 i/o lines description smart card slot usart rs485 drivers differential bus irda transceivers field bus driver emv driver irda driver irlap rs232 drivers serial port serial driver ppp lin driver lin transceiver spi driver spi bus table 40-2. i/o line description name description type active level sck serial clock i/o txd transmit serial data or master out slave in (mosi) in spi master mode or master in slave out (miso) in spi slave mode i/o rxd receive serial data or master in slave out (miso) in spi master mode or master out slave in (mosi) in spi slave mode input cts clear to send or slave select (nss) in spi slave mode input low rts request to send or slave select (nss) in spi master mode output low
779 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 779 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.6 product dependencies 40.6.1 i/o lines the pins used for interfacing the usart may be multiplexed with the pio lines. the program- mer must first program the pio controller to assign the desired usart pins to their peripheral function. if i/o lines of the usart are not used by the application, they can be used for other purposes by the pio controller. to prevent the txd line from falling when the usart is di sabled, the use of an internal pull up is mandatory. if the hardware handshaking feature is used, the internal pull up on txd must also be enabled. 40.6.2 power management the usart is not continuously clocked. the pr ogrammer must first enable the usart clock in the power management controller (pmc) before using the usart. however, if the application does not require usart operations, the usart clock can be stopped when not needed and be restarted later. in this case, the usart will resume its operations where it left off. configuring the usart does not require the usart clock to be enabled. table 40-3. i/o lines instance signal i/o line peripheral usart0 cts0 pa3 a usart0 rts0 pa2 a usart0 rxd0 pa1 a usart0 sck0 pa4 a usart0 txd0 pa0 a usart1 cts1 pc28 c usart1 rts1 pc27 c usart1 rxd1 pa6 a usart1 sck1 pc29 c usart1 txd1 pa5 a usart2 cts2 pb1 b usart2 rts2 pb0 b usart2 rxd2 pa8 a usart2 sck2 pb2 b usart2 txd2 pa7 a usart3 cts3 pc25 b usart3 rts3 pc24 b usart3 rxd3 pc23 b usart3 sck3 pc26 b usart3 txd3 pc22 b
780 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 780 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.6.3 interrupt the usart interrupt line is connected on one of the internal sources of the interrupt controller using the usart interrupt requires the interrupt controller to be programmed first. note that it is not recommended to use the usart interrupt line in edge sensitive mode. 40.7 functional description the usart is capable of managing several ty pes of serial synchronous or asynchronous communications. it supports the following communication modes: ? 5- to 9-bit full-duplex asynchronous serial communication C msb- or lsb-first C 1, 1.5 or 2 stop bits C parity even, odd, marked, space or none C by 8 or by 16 over-sampling receiver frequency C optional hardware handshaking C optional break management C optional multidrop serial communication ? high-speed 5- to 9-bit full-duplex synchronous serial communication C msb- or lsb-first C 1 or 2 stop bits C parity even, odd, marked, space or none C by 8 or by 16 over-sampling frequency C optional hardware handshaking C optional break management C optional multidrop serial communication ? rs485 with driver control signal ? iso7816, t0 or t1 protocols for interfacing with smart cards C nack handling, error counter with repetition and iteration limit, inverted data. ? infrared irda modulation and demodulation ? spi mode Cmaster or slave C serial clock programmab le phase and polarity C spi serial clock (sck) frequency up to internal clock frequency mck/6 ? lin mode table 40-4. peripheral ids instance id usart0 5 usart1 6 usart2 7 usart3 8
781 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 781 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 C compliant with lin 1.3 and lin 2.0 specifications Cmaster or slave C processing of frames with up to 256 data bytes C response data length can be configurable or defined automatically by the identifier C self synchronization in slave node configuration C automatic processing and verification of the synch break and the synch field C the synch break is detected even if it is partially superimposed with a data byte C automatic identifier parity calculation/sending and verification C parity sending and verification can be disabled C automatic checksum calculation/sending and verification C checksum sending and verification can be disabled C support both classic and enhanced checksum types C full lin error checking and reporting C frame slot mode: the master allocates slots to the scheduled frames automatically. C generation of the wakeup signal ? test modes C remote loopback, local loopback, automatic echo 40.7.1 baud rate generator the baud rate generator provides the bit period clock named the baud rate clock to both the receiver and the transmitter. the baud rate generator clock source can be selected by setting the usclks field in the mode register (us_mr) between: ? the master clock mck ? a division of the master clock, the divider being product dependent, but generally set to 8 ? the external clock, available on the sck pin the baud rate generator is based upon a 16-bit divider, which is programmed with the cd field of the baud rate generator register (us_brgr). if cd is programmed to 0, the baud rate generator does not generate any clock. if cd is programmed to 1, the divider is bypassed and becomes inactive. if the external sck clock is selected, the duration of the low and high levels of the signal pro- vided on the sck pin must be longer than a master clock (mck) period. the frequency of the signal provided on sck must be at least 3 times lower than mck in usart mode, or 6 in spi mode.
782 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 782 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 40-3. baud rate generator 40.7.1.1 baud rate in asynchronous mode if the usart is programmed to operate in as ynchronous mode, the selected clock is first divided by cd, which is field programmed in the baud rate generator register (us_brgr). the resulting clock is provided to the receiv er as a sampling clock and then divided by 16 or 8, depending on the programming of the over bit in us_mr. if over is set to 1, the receiver sampling is 8 times higher than the baud rate clock. if over is cleared, the sampling is performed at 16 times the baud rate clock. the following formula performs the calculation of the baud rate. this gives a maximum baud rate of mck divided by 8, assuming that mck is the highest possi- ble clock and that over is programmed to 1. baud rate calculation example table 40-5 shows calculations of cd to obtain a baud rate at 38400 bauds for different source clock frequencies. this table also shows the actual resulting baud rate and the error. mck/div 16-bit counter 0 baud rate clock cd cd sampling divider 0 1 >1 sampling clock reserved mck sck usclks over sck sync sync usclks = 3 1 0 2 3 0 1 0 1 fidi baudrate selectedclock 82 over ? () cd () = table 40-5. baud rate example (over = 0) source clock expected baud rate calculation result cd actual baud rate error mhz bit/s bit/s 3 686 400 38 400 6.00 6 38 400.00 0.00% 4 915 200 38 400 8.00 8 38 400.00 0.00% 5 000 000 38 400 8.14 8 39 062.50 1.70% 7 372 800 38 400 12.00 12 38 400.00 0.00% 8 000 000 38 400 13.02 13 38 461.54 0.16%
783 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 783 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 the baud rate is calculated with the following formula: the baud rate error is calculated with the following formula. it is not recommended to work with an error higher than 5%. 40.7.1.2 fractional baud rate in asynchronous mode the baud rate generator previously defined is su bject to the following limitation: the output fre- quency changes by only integer multiples of the reference frequency. an approach to this problem is to integrate a fractional n clock generator that has a high resolution. the generator architecture is modified to obtain baud rate c hanges by a fraction of the reference source clock. this fractional part is programmed with the fp field in the baud rate generator register (us_brgr). if fp is not 0, the fractional part is activated. the resolution is one eighth of the clock divider. this feature is only available when using usart normal mode. the fractional baud rate is calculated using the following formula: the modified architecture is presented below: 12 000 000 38 400 19.53 20 37 500.00 2.40% 12 288 000 38 400 20.00 20 38 400.00 0.00% 14 318 180 38 400 23.30 23 38 908.10 1.31% 14 745 600 38 400 24.00 24 38 400.00 0.00% 18 432 000 38 400 30.00 30 38 400.00 0.00% 24 000 000 38 400 39.06 39 38 461.54 0.16% 24 576 000 38 400 40.00 40 38 400.00 0.00% 25 000 000 38 400 40.69 40 38 109.76 0.76% 32 000 000 38 400 52.08 52 38 461.54 0.16% 32 768 000 38 400 53.33 53 38 641.51 0.63% 33 000 000 38 400 53.71 54 38 194.44 0.54% 40 000 000 38 400 65.10 65 38 461.54 0.16% 50 000 000 38 400 81.38 81 38 580.25 0.47% table 40-5. baud rate example (over = 0) (continued) source clock expected baud rate calculation result cd actual baud rate error baudrate mck cd 16 ? = error 1 expectedbaudrate actualbaudrate -------------------------------------------------- - ?? ?? ?= baudrate selectedclock 82 over ? () cd fp 8 ------- + ?? ?? ?? ?? =
784 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 784 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 40-4. fractional baud rate generator 40.7.1.3 baud rate in synchronous mode or spi mode if the usart is programmed to operate in synchronous mode, the selected clock is simply divided by the field cd in us_brgr. in synchronous mode, if the external clock is selected (usclks = 3), the clock is provided directly by the signal on the usart sck pin. no division is active. the value written in us_brgr has no effect. the external clock frequency must be at least 3 times lower than the system clock. in synchronous mode master (usclks = 0 or 1, clk0 set to 1), the receive part limits the sck maximum frequency to mck/3 in usart mode, or mck/6 in spi mode. when either the external clock sck or the inte rnal clock divided (mck/div) is selected, the value programmed in cd must be even if the user has to ensure a 50:50 mark/space ratio on the sck pin. if the internal clock mck is selected, the baud rate generator ensures a 50:50 duty cycle on the sck pin, even if the value programmed in cd is odd. 40.7.1.4 baud rate in iso 7816 mode the iso7816 specification defines the bit rate with the following formula: where: ? b is the bit rate ? di is the bit-rate adjustment factor ? fi is the clock frequency division factor ? f is the iso7816 clock frequency (hz) mck/div 16-bit counter 0 baud rate clock cd cd sampling divider 0 1 >1 sampling clock reserved mck sck usclks over sck sync sync usclks = 3 1 0 2 3 0 1 0 1 fidi glitch-free logic modulus control fp fp baudrate selectedclock cd ------------------------------------- - = b di fi ----- - f =
785 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 785 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 di is a binary value encoded on a 4-bit field, named di, as represented in table 40-6 . fi is a binary value encoded on a 4-bit field, named fi, as represented in table 40-7 . table 40-8 shows the resulting fi/di ratio, which is the ratio between the iso7816 clock and the baud rate clock. if the usart is configured in iso7816 mode, th e clock selected by the usclks field in the mode register (us_mr) is first divided by the value programmed in the field cd in the baud rate generator register (us_brgr). the resulting clock can be provided to the sck pin to feed the smart card clock inputs. this means that the clko bit can be set in us_mr. this clock is then divided by the value progra mmed in the fi_di_ratio field in the fi_di_ratio register (us_fidi). this is performed by the sampling divider, which performs a division by up to 2047 in iso7816 mode. the non-integer values of the fi/di ratio are not supported and the user must program the fi_di_ratio field to a va lue as close as possible to the expected value. the fi_di_ratio field resets to the value 0x174 (372 in decimal) and is the most common divider between the iso7816 clock and the bit rate (fi = 372, di = 1). figure 40-5 shows the relation between the elementary time unit, corresponding to a bit time, and the iso 7816 clock. table 40-6. binary and decimal values for di di field 0001 0010 0011 0100 0101 0110 1000 1001 d i ( d e c i m a l )1 2 4 8 1 63 21 2 2 0 table 40-7. binary and decimal values for fi fi field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101 fi (decimal) 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048 table 40-8. possible values for the fi/di ratio fi/di 372 558 774 1116 1488 1806 512 768 1024 1536 2048 1 372 558 744 1116 1488 1860 512 768 1024 1536 2048 2 186 279 372 558 744 930 256 384 512 768 1024 4 93 139.5 186 279 372 465 128 192 256 384 512 8 46.5 69.75 93 139.5 186 232.5 64 96 128 192 256 16 23.25 34.87 46.5 69.75 93 116.2 32 48 64 96 128 32 11.62 17.43 23.25 34.87 46.5 58.13 16 24 32 48 64 12 31 46.5 62 93 124 155 42.66 64 85.33 128 170.6 20 18.6 27.9 37.2 55.8 74.4 93 25.6 38.4 51.2 76.8 102.4
786 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 786 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 40-5. elementary time unit (etu) 40.7.2 receiver and transmitter control after reset, the receiver is disabled. the user must enable the receiver by setting the rxen bit in the control register (us_cr). however, the receiver registers can be programmed before the receiver clock is enabled. after reset, the transmitter is disabled. the user must enable it by setting the txen bit in the control register (us_cr). however, the transmitter registers can be programmed before being enabled. the receiver and the transmitter can be enabled together or independently. at any time, the software can perform a reset on the receiver or the transmitter of the usart by setting the corresponding bit, rstrx and rsttx respectively, in the control register (us_cr). the software resets clear the status flag and reset internal state machines but the user interface configuration registers hold the value configured prior to software reset. regard- less of what the receiver or the transmitter is performing, the communi cation is immediately stopped. the user can also independently disable the receiv er or the transmitter by setting rxdis and txdis respectively in us_cr. if the receiver is disabled during a character reception, the usart waits until the end of reception of the current character, then the reception is stopped. if the transmitter is disabled while it is operating, the usart waits the end of transmission of both the current character and character being stored in the transmit holding register (us_thr). if a timeguard is programmed, it is handled normally. 40.7.3 synchronous and asynchronous modes 40.7.3.1 transmitter operations the transmitter performs the same in both synchronous and asynchronous operating modes (sync = 0 or sync = 1). one start bit, up to 9 da ta bits, one optional parity bit and up to two stop bits are successively shifted out on the txd pin at each falling edge of the programmed serial clock. the number of data bits is selected by the chrl field and the mode 9 bit in the mode register (us_mr). nine bits are selected by setting the mode 9 bit regardless of the chrl field. the parity bit is set according to the par field in us_mr. the even, odd, space, marked or none parity bit can be configured. the msbf field in us _mr configures which data bit is sent first. if written to 1, the most significant bit is sent first. if written to 0, the less significant bit is sent first. the number of stop bits is selected by the nbst op field in us_mr. the 1.5 stop bit is sup- ported in asynchronous mode only. 1 etu iso7816 clock on sck iso7816 i/o line on txd fi_di_ratio iso7816 clock cycles
787 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 787 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 40-6. character transmit the characters are sent by writing in the tran smit holding register (us_thr). the transmitter reports two status bits in the channel status register (us_csr): txrdy (transmitter ready), which indicates that us_thr is empty and txempty, which indicates that all the characters written in us_thr have been processed. when the current character processing is completed, the last character written in us_thr is transferred into the shift register of the transmitter and us_thr becomes empty, thus txrdy rises. both txrdy and txempty bits are low when the transmitter is disabled. writing a character in us_thr while txrdy is low has no effect and the written character is lost. figure 40-7. transmitter status 40.7.3.2 manchester encoder when the manchester encoder is in use, c haracters transmitted through the usart are encoded based on biphase manchester ii format. to enable this mode, set the man field in the us_mr register to 1. depending on polarity configur ation, a logic level (zero or one), is transmit- ted as a coded signal one-to-zero or zero-to-one. thus, a transition always occurs at the midpoint of each bit time. it consumes more bandwidth than the original nrz signal (2x) but the receiver has more error control since the expected input must show a change at the center of a bit cell. an example of manchester encoded sequence is: the byte 0xb1 or 10110001 encodes to 10 01 10 10 01 01 01 10, assuming the default polarity of the encoder. figure 40-8 illustrates this coding scheme. d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit example: 8-bit, parity enabled one stop baud rate clock d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock start bit write us_thr d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit txrdy txempty
788 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 788 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 40-8. nrz to manchester encoding the manchester encoded character can also be enc apsulated by adding both a configurable preamble and a start frame delimiter pattern. depending on the configuration, the preamble is a training sequence, composed of a pre-defined pattern with a programmable length from 1 to 15 bit times. if the preamble length is set to 0, the preamble waveform is not generated prior to any character. the preamble pattern is chosen among the following sequences: all_one, all_zero, one_zero or zero_one, writing th e field tx_pp in the us_man register, the field tx_pl is used to configure the preamble length. figure 40-9 illustrates and defines the valid patterns. to improve flexibility, the encoding scheme can be configured using the tx_mpol field in the us_man register. if the tx _mpol field is set to zero (default), a logic zero is encoded with a zero-to-one transition and a logic one is encoded with a one-to-zero tran- sition. if the tx_mpol field is set to one, a logic one is encoded with a one-to-zero transition and a logic zero is encoded with a zero-to-one transition. figure 40-9. preamble patterns, default polarity assumed a start frame delimiter is to be configured using the onebit field in the us_mr register. it con- sists of a user-defined pattern that indicates the beginning of a valid data. figure 40-10 illustrates these pattern s. if the start frame delimiter, also kn own as start bit, is one bit, (onebit to 1), a logic zero is manchester encoded and indicates that a new character is being sent seri- ally on the line. if the start frame delimiter is a synchronization pattern also referred to as sync (onebit to 0), a sequence of 3 bit times is sent serially on the line to indicate the start of a new nrz encoded data manchester encoded data 10110001 txd manchester encoded data txd sfd data 8 bit width "all_one" preamble manchester encoded data txd sfd data 8 bit width "all_zero" preamble manchester encoded data txd sfd data 8 bit width "zero_one" preamble manchester encoded data txd sfd data 8 bit width "one_zero" preamble
789 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 789 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 character. the sync waveform is in itself an invalid manchester waveform as the transition occurs at the middle of the second bit time. tw o distinct sync patterns are used: the command sync and the data sync. the command sync has a logic one level for one and a half bit times, then a transition to logic zero for the second one and a half bit times. if the modsync field in the us_mr register is set to 1, the next character is a command. if it is set to 0, the next charac- ter is a data. when direct memory access is used, the modsync field can be immediately updated with a modified character located in memory. to enable this mode, var_sync field in us_mr register must be set to 1. in this ca se, the modsync field in us_mr is bypassed and the sync configuration is held in the txsynh in the us_thr register. the usart character for- mat is modified and includes sync information. figure 40-10. start frame delimiter drift compensation drift compensation is available only in 16x oversampling mode. an hardware recovery system allows a larger clock drift. to enable the ha rdware system, the bit in the usart_man register must be set. if the rxd edge is one 16x clock c ycle from the expected edge, this is considered as normal jitter and no corrective actions is taken. if the rxd event is between 4 and 2 clock cycles before the expected edge, then the current per iod is shortened by one clock cycle. if the rxd event is between 2 and 3 clock cycles after the expected edge, then the current period is lengthened by one clock cycle. these intervals are considered to be drift and so corrective actions are automatically taken. manchester encoded data txd sfd data one bit start frame delimiter preamble length is set to 0 manchester encoded data txd sfd data command sync start frame delimiter manchester encoded data txd sfd data data sync start frame delimiter
790 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 790 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 40-11. bit resynchronization 40.7.3.3 asynchronous receiver if the usart is programmed in asynchronous operating mode (sync = 0), the receiver over- samples the rxd input line. the oversampling is either 16 or 8 times the baud rate clock, depending on the over bit in the mode register (us_mr). the receiver samples the rxd line. if the line is sampled during one half of a bit time to 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. if the oversampling is 16, (over to 0), a start is detected at the eighth sample to 0. then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. if the oversampling is 8 (over to 1), a start bit is detected at the fourth sample to 0. then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle. the number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively chrl , mode9, msbf and par. for the synchronization mechanism only, the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field nbstop, so that resynchronization between the receiver and the transmitter can occur. moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. figure 40-12 and figure 40-13 illustrate start detection and character reception when usart operates in asynchronous mode. rxd oversampling 16x clock sampling point expected edge tolerance synchro. jump sync jump synchro. error synchro. error
791 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 791 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 40-12. asynchronous start detection figure 40-13. asynchronous character reception 40.7.3.4 manchester decoder when the man field in us_mr register is set to 1, the manchester decoder is enabled. the decoder performs both preamble and start frame delimiter detection. one input line is dedicated to manchester encoded input data. an optional preamble sequence can be defined, it s length is user-defined and totally indepen- dent of the emitter side. use rx_pl in us_man register to configure the length of the preamble sequence. if the length is set to 0, no preamble is detected and the function is disabled. in addi- tion, the polarity of the input stream is programmable with rx_mpol field in us_man register. depending on the desired application the preamble pattern matching is to be defined via the rx_pp field in us_man. see figure 40-9 for available preamble patterns. unlike preamble, the start frame delimiter is shared between manchester encoder and decoder. so, if onebit field is set to 1, only a zero encoded manchester can be detected as a valid start frame delimiter. if onebit is set to 0, only a sync pattern is detected as a valid start frame delimiter. decoder operates by detecting transition on incoming stream. if rxd is sampled dur- ing one quarter of a bit time to zero, a start bit is detected. see figure 40-14 . the sample pulse rejection mechanism applies. sampling clock (x16) rxd start detection sampling baud rate clock rxd start rejection sampling 12345678 12345670 1234 12345678 9 10111213141516 d0 sampling d0 d1 d2 d3 d4 d5 d6 d7 rxd parity bit stop bit example: 8-bit, parity enabled baud rate clock start detection 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples
792 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 792 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 in order to increase the compatibility the rxidlv bi t in the us_man register allows to inform the usart block of the rx line idle state value (rx line undriven), it can be either level one (pull-up) or level zero (pull-down). by default this bit is set to one (rx line is at level 1 if undriven). figure 40-14. asynchronous star t bit detection the receiver is activated and starts preamble and frame delimiter detection, sampling the data at one quarter and then three quarters. if a valid preamble pattern or start frame delimiter is detected, the receiver continues decoding with the same synchronization. if the stream does not match a valid pattern or a valid start frame delimiter, the receiver re-synchronizes on the next valid edge.the minimum time threshold to estimate the bit value is three quarters of a bit time. if a valid preamble (if used) followed with a valid start frame delimiter is detected, the incoming stream is decoded into nrz data and passed to usart for processing. figure 40-15 illustrates manchester pattern mismatch. when incoming data stream is passed to the usart, the receiver is also able to detect manchester code vi olation. a code violation is a lack of transition in the middle of a bit cell. in this case, mane flag in us_csr register is raised. it is cleared by writing the control register (us_cr) with the rststa bit to 1. see figure 40-16 for an exam- ple of manchester error detection during data phase. figure 40-15. preamble pattern mismatch manchester encoded data txd 1234 sampling clock (16 x) start detection manchester encoded data txd sfd data preamble length is set to 8 preamble mismatch invalid pattern preamble mismatch manchester coding error
793 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 793 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 40-16. manchester error flag when the start frame delimiter is a sync pattern (onebit field to 0), both command and data delimiter are supported. if a valid sync is detected, the received character is written as rxchr field in the us_rhr register and the rxsynh is updated. rxchr is set to 1 when the received character is a command, and it is set to 0 if the received character is a data. this mechanism alleviates and simplifies the direct memory access as the character contains its own sync field in the same register. as the decoder is setup to be used in unipolar mode, the first bit of the frame has to be a zero-to- one transition. 40.7.3.5 radio interface: manchester encoded usart application this section describes low data rate rf transmission systems and their integration with a man- chester encoded usart. these systems are based on transmitter and receiver ics that support ask and fsk modulation schemes. the goal is to perform full duplex radio transmissi on of characters using two different frequency carriers. see the configuration in figure 40-17 . manchester encoded data txd sfd preamble length is set to 4 elementary character bit time manchester coding error detected sampling points preamble subpacket and start frame delimiter were successfully decoded entering usart character area
794 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 794 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 40-17. manchester encoded characters rf transmission the usart module is configured as a manchester encoder/decoder. looking at the down- stream communication channel, manchester encoded characters are serially sent to the rf emitter. this may also include a user defined preamble and a start frame delimiter. mostly, pre- amble is used in the rf receiver to distinguish between a valid data from a transmitter and signals due to noise. the manchester stream is then modulated. see figure 40-18 for an exam- ple of ask modulation scheme. when a logic one is sent to the ask modulator, the power amplifier, referred to as pa, is enabled and transmits an rf signal at downstream frequency. when a logic zero is transmitted, the rf signal is turned off. if the fsk modulator is activated, two different frequencies are used to transmit dat a. when a logic 1 is sent, the modulator out- puts an rf signal at frequency f0 and switches to f1 if the data sent is a 0. see figure 40-19 . from the receiver side, another carrier frequency is used. the rf receiver performs a bit check operation examining demodulated data stream. if a valid pattern is detected, the receiver switches to receiving mode. the demodulated stream is sent to the manchester decoder. because of bit checking inside rf ic, the data transferred to the microcontroller is reduced by a user-defined number of bits. the manchester preamble length is to be defined in accordance with the rf ic configuration. figure 40-18. ask modulator output lna vco rf filter demod control bi-dir line pa rf filter mod vco control manchester decoder manchester encoder usart receiver usart emitter ask/fsk upstream receiver ask/fsk downstream transmitter upstream emitter downstream receiver serial configuration interface fup frequency carrier fdown frequency carrier manchester encoded data default polarity unipolar output txd ask modulator output uptstream frequency f0 nrz stream 10 0 1
795 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 795 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 40-19. fsk modulator output 40.7.3.6 synchronous receiver in synchronous mode (sync = 1), the receiver samples the rxd signal on each rising edge of the baud rate clock. if a low level is detected, it is considered as a start. all data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit. synchronous mode operations provide a high speed transfer capability. configuration fields and bits are the same as in asynchronous mode. figure 40-20 illustrates a character reception in synchronous mode. figure 40-20. synchronous mode character reception 40.7.3.7 receiver operations when a character reception is completed, it is transferred to the receive holding register (us_rhr) and the rxrdy bit in the status register (us_csr) rises. if a character is com- pleted while the rxrdy is set, the ovre (ove rrun error) bit is set. the last character is transferred into us_rhr and overwrites the previous one. the ovre bit is cleared by writing the control register (us_cr) with the rststa (reset status) bit to 1. manchester encoded data default polarity unipolar output txd fsk modulator output uptstream frequencies [f0, f0+offset] nrz stream 10 0 1 d0 d1 d2 d3 d4 d5 d6 d7 rxd start sampling parity bit stop bit example: 8-bit, parity enabled 1 stop baud rate clock
796 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 796 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 40-21. receiver status 40.7.3.8 parity the usart supports five parity modes selected by programming the par field in the mode register (us_mr). the par field also enables the multidrop mode, see multidrop mode on page 797 . even and odd parity bit generation and error detection are supported. if even parity is selected, the parity generator of the transmitter drives the parity bit to 0 if a num- ber of 1s in the character data bit is even, and to 1 if the number of 1s is odd. accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sam- pled parity bit does not correspond. if odd parity is selected, the parity generator of the transmitter drives the parity bit to 1 if a number of 1s in the character data bit is even, and to 0 if the number of 1s is odd. accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. if the mark parity is used, the parity generator of the transmitter drives the parity bit to 1 for all characters. the receiver parity checker reports an error if the parity bit is sampled to 0. if the space parity is used, the parity generator of the transmitter drives the parity bit to 0 for all characters. the receiver parity checker reports an error if the parity bit is sampled to 1. if parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. table 40-9 shows an example of the parity bit for the character 0x41 (character ascii a) depending on the configuration of the usart. because there are two bits to 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit parity bit stop bit baud rate clock write us_cr rxrdy ovre d0 d1 d2 d3 d4 d5 d6 d7 start bit parity bit stop bit rststa = 1 read us_rhr table 40-9. parity bit examples character hexa binary parity bit parity mode a 0x41 0100 0001 1 odd a 0x41 0100 0001 0 even a 0x41 0100 0001 1 mark a 0x41 0100 0001 0 space a 0x41 0100 0001 none none
797 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 797 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 when the receiver detects a parity error, it sets the pare (parity error) bit in the channel status register (us_csr). the pare bit can be cleared by writing the control register (us_cr) with the rststa bit to 1. figure 40-22 illustrates the parity bit status setting and clearing. figure 40-22. parity error 40.7.3.9 multidrop mode if the par field in the mode register (us_mr) is programmed to the value 0x6 or 0x07, the usart runs in multidrop mode. this mode differentiates the data characters and the address characters. data is transmitted with the parity bit to 0 and addresses are transmitted with the parity bit to 1. if the usart is configured in multidrop mode, the receiver sets the pare parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the control register is written with the senda bit to 1. to handle parity error, the pare bit is cleared when the control register is written with the bit rststa to 1. the transmitter sends an address byte (parity bit set) when senda is written to us_cr. in this case, the next byte written to us_thr is trans mitted as an address. any character written in us_thr without having written the command senda is transmitted normally with the parity to 0. 40.7.3.10 transmitter timeguard the timeguard feature enables the usar t interface with slow remote devices. the timeguard function enables the transmitter to insert an idle state on the txd line between two characters. this idle state actually acts as a long stop bit. the duration of the idle state is programmed in the tg field of the transmitter timeguard regis- ter (us_ttgr). when this field is programmed to zero no timeguard is generated. otherwise, the transmitter holds a high level on txd after each transmitted byte during the number of bit periods programmed in tg in addition to the number of stop bits. as illustrated in figure 40-23 , the behavior of txrdy and txempty status bits is modified by the programming of a timeguard. txrdy rises only when the start bit of the next character is sent, and thus remains to 0 during the timeguard transmission if a character has been written in d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit bad parity bit stop bit baud rate clock write us_cr pare rxrdy rststa = 1
798 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 798 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 us_thr. txempty remains low until the timeguard transmission is completed as the time- guard is part of the current character being transmitted. figure 40-23. timeguard operations table 40-10 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the baud rate. 40.7.3.11 receiver time-out the receiver time-out provides support in handling variable-length frames. this feature detects an idle condition on the rxd line. when a time-out is detected, the bit timeout in the channel status register (us_csr) rises and can generate an interrupt, thus indicating to the driver an end of frame. the time-out delay period (during which the receiver waits for a new character) is programmed in the to field of the receiver time-out regist er (us_rtor). if the to field is programmed to 0, the receiver time-out is disabled and no time-out is detected. the timeout bit in us_csr remains to 0. otherwise, the receiver loads a 16-bit counter with the value programmed in to. this counter is decremented at each bit per iod and reloaded each time a new character is received. if the counter reaches 0, the timeout bit in the status register rises. then, the user can either: d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock start bit tg = 4 write us_thr d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit txrdy txempty tg = 4 table 40-10. maximum timeguard length depending on baud rate baud rate bit time timeguard bit/sec s ms 1 200 833 212.50 9 600 104 26.56 14400 69.4 17.71 19200 52.1 13.28 28800 34.7 8.85 33400 29.9 7.63 56000 17.9 4.55 57600 17.4 4.43 115200 8.7 2.21
799 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 799 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? stop the counter clock until a new character is received. this is performed by writing the control register (us_cr) with the sttto (start time-out) bit to 1. in this case, the idle state on rxd before a new character is received will not provide a time-out. this prevents having to handle an interrupt before a character is received and allows waiting for the next idle state on rxd after a frame is received. ? obtain an interrupt while no character is rece ived. this is performed by writing us_cr with the retto (reload and start time-out) bit to 1. if retto is performed, the counter starts counting down immediately from the value to. this enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. if sttto is performed, the counter clock is stopped until a first character is received. the idle state on rxd before the start of the frame does not provide a time-out. this prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on rxd is detected. if retto is performed, the counter starts counting down immediately from the value to. this enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. figure 40-24 shows the block diagram of the receiver time-out feature. figure 40-24. receiver time-out block diagram table 40-11 gives the maximum time-out period for some standard baud rates. table 40-11. maximum time-out period baud rate bit time time-out bit/sec s ms 600 1 667 109 225 1 200 833 54 613 2 400 417 27 306 4 800 208 13 653 9 600 104 6 827 14400 69 4 551 19200 52 3 413 28800 35 2 276 33400 30 1 962 16-bit time-out counter 0 to timeout baud rate clock = character received retto load clock 16-bit value sttto dq 1 clear
800 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 800 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.7.3.12 framing error the receiver is capable of detecting framing errors. a framing error happens when the stop bit of a received character is detected at level 0. this can occur if the receiver and the transmitter are fully desynchronized. a framing error is reported on the frame bit of the channel status register (us_csr). the frame bit is asserted in the middle of the stop bit as soon as the framing error is detected. it is cleared by writing the control register (us_cr) with the rststa bit to 1. figure 40-25. framing error status 40.7.3.13 transmit break the user can request the transmitter to generate a break condition on the txd line. a break con- dition drives the txd line low during at least one complete character. it appears the same as a 0x00 character sent with the parity and the stop bits to 0. however, the transmitter holds the txd line at least during one character until the user requests the break condition to be removed. a break is transmitted by writing the control register (us_cr) with the sttbrk bit to 1. this can be performed at any time, either while the transmitter is empty (no character in either the shift register or in us_thr) or when a character is being transmitted. if a break is requested while a character is being shifted out, the charac ter is first completed before the txd line is held low. once sttbrk command is requested further sttbrk commands are ignored until the end of the break is completed. the break condition is removed by writing us_cr with the stpbrk bit to 1. if the stpbrk is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. 56000 18 1 170 57600 17 1 138 200000 5 328 table 40-11. maximum time-out period (continued) baud rate bit time time-out d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit parity bit stop bit baud rate clock write us_cr frame rxrdy rststa = 1
801 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 801 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 the transmitter considers the break as though it is a character, i.e. the sttbrk and stpbrk commands are taken into account only if the txrdy bit in us_csr is to 1 and the start of the break condition clears the txrdy and txempty bits as if a character is processed. writing us_cr with both sttbrk and stpbrk bits to 1 can lead to an unpredictable result. all stpbrk commands requested without a previous sttbrk command are ignored. a byte writ- ten into the transmit holding re gister while a break is pending, but not started, is ignored. after the break condition, the transmitter returns the txd line to 1 for a minimum of 12 bit times. thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. if the timeguard is programmed with a value higher than 12, the txd line is held high for the timeguard period. after holding the txd line for this period, the transmitter resumes normal operations. figure 40-26 illustrates the effect of both the start break (sttbrk) and stop break (stpbrk) commands on the txd line. figure 40-26. break transmission 40.7.3.14 receive break the receiver detects a break condition when all data, parity and stop bits are low. this corre- sponds to detecting a framing error with data to 0x00, but frame remains low. when the low stop bit is detected, the receiver asserts the rxbrk bit in us_csr. this bit may be cleared by writing the control regi ster (us_cr) with the bit rststa to 1. an end of receive break is detected by a high leve l for at least 2/16 of a bit period in asynchro- nous operating mode or one sample at high level in synchronous operating mode. the end of break detection also asserts the rxbrk bit. 40.7.3.15 hardware handshaking the usart features a hardware handshaking out-of-band flow control. the rts and cts pins are used to connect with the remote device, as shown in figure 40-27 . d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock write us_cr txrdy txempty stpbrk = 1 sttbrk = 1 break transmission end of break
802 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 802 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 40-27. connection with a remote device for hardware handshaking setting the usart to operate with hardware handshaking is performed by writing the usart_mode field in the mode register (us_mr) to the value 0x2. the usart behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the rts pin as described below and the level on the cts pin modifies the behavior of the transmitter as described below. using this mode requires using the dmac channel for reception. the transmit- ter can handle hardware handshaking in any case. figure 40-28 shows how the transmitter operates if hardware handshaking is enabled. the cts pin disables the transmitt er. if a character is being processi ng, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin cts falls. figure 40-28. transmitter behavior when operating with hardware handshaking 40.7.4 iso7816 mode the usart features an iso7816-compatible operating mode. this mode permits interfacing with smart cards and security access modules (sam) communicating through an iso7816 link. both t = 0 and t = 1 protocols defined by the iso7816 specification are supported. setting the usart in iso7816 mode is performed by writing the usart_mode field in the mode register (us_mr) to the value 0x4 for protoc ol t = 0 and to the value 0x5 for protocol t = 1. 40.7.4.1 iso7816 mode overview the iso7816 is a half duplex communication on only one bidirectional line. the baud rate is determined by a division of the clo ck provided to the remote device (see baud rate generator on page 782 ). the usart connects to a smart card as shown in figure 40-29 . the txd line becomes bidirec- tional and the baud rate generator feeds the iso7816 clock on the sck pin. as the txd pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is direct ed to the input of the receiver. the usart is con- sidered as the master of the communication as it generates the clock. usart txd cts remote device rxd txd rxd rts rts cts cts txd
803 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 803 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 40-29. connection of a smart card to the usart when operating in iso7816, either in t = 0 or t = 1 modes, the character format is fixed. the configuration is 8 data bits, ev en parity and 1 or 2 stop bits, regardless of the values pro- grammed in the chrl, mode9, par and chmode fields. msbf can be used to transmit lsb or msb first. parity bit (par) can be used to transmit in normal or inverse mode. refer to usart mode register on page 836 and par: parity type on page 837 . the usart cannot operate concurrently in both receiver and transmitter modes as the commu- nication is unidirectional at a time. it has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. enabling both the receiver and the transmitter at the same time in iso7816 mode may lead to unpredictable results. the iso7816 specification defines an inverse transmission format. data bits of the character must be transmitted on the i/o line at their negative value. 40.7.4.2 protocol t = 0 in t = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. the transmitter shifts out the bits and does not drive the i/o line during the guard time. if no parity error is detected, the i/o line remains to 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in figure 40-30 . if a parity error is detected by the receiver, it drives the i/o line to 0 during the guard time, as shown in figure 40-31 . this error bit is also named nack, for non acknowledge. in this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. when the usart is the receiver and it detects an error, it does not load the erroneous character in the receive holding register (us_rhr). it appropriately sets the pare bit in the status reg- ister (us_sr) so that the software can handle the error. figure 40-30. t = 0 protocol without parity error smart card sck clk txd i/o usart d0 d1 d2 d3 d4 d5 d6 d7 rxd parity bit baud rate clock start bit guard time 1 next start bit guard time 2
804 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 804 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 40-31. t = 0 protocol with parity error receive error counter the usart receiver also records the total number of errors. this can be read in the number of error (us_ner) register. the nb_errors field can record up to 255 errors. reading us_ner automatically clears the nb_errors field. receive nack inhibit the usart can also be configured to inhibit an error. this can be achieved by setting the inack bit in the mode register (us_mr). if inack is to 1, no error signal is driven on the i/o line even if a parity bit is detected. moreover, if inack is set, the erroneous receiv ed character is stored in the receive holding register, as if no error occurred and the rxrdy bit does rise. transmit character repetition when the usart is transmitting a character and gets a nack, it can automatically repeat the character before moving on to the next one. repetition is enabled by writing the max_iteration field in the mode register (us_mr) at a value higher than 0. each character can be transmitted up to eight times; the first transmission plus seven repetitions. if max_iteration does not equal zero, the u sart repeats the character as many times as the value loaded in max_iteration. when the usart repetition number reaches max_iteration, the iteration bit is set in the channel status register (us_csr). if the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. the iteration bit in us_csr can be cleared by writing the control register with the rsit bit to 1. disable successive receive nack the receiver can limit the number of successive nacks sent back to the remote transmitter. this is programmed by setting the bit dsnack in the mode register (us_mr). the maximum number of nack transmitted is programmed in the max_iteration field. as soon as max_iteration is reached, the character is cons idered as correct, an acknowledge is sent on the line and the iteration bit in the channel status register is set. 40.7.4.3 protocol t = 1 when operating in iso7816 protocol t = 1, the transmission is similar to an asynchronous for- mat with only one stop bit. the parity is generated when transmitting and checked when receiving. parity error detection sets the pare bit in the channel status register (us_csr). d0 d1 d2 d3 d4 d5 d6 d7 i/o parity bit baud rate clock start bit guard time 1 start bit guard time 2 d0 d1 error repetition
805 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 805 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.7.5 irda mode the usart features an irda mode supplying half-duplex point-to-point wireless communica- tion. it embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in figure 40-32 . the modulator and demodulator are compliant with the irda specification version 1.1 and support data transfer speeds ranging from 2.4 kb/s to 115.2 kb/s. the usart irda mode is enabled by setting t he usart_mode field in the mode register (us_mr) to the value 0x8. the irda filter register (us_if) allows configuring the demodulator filter. the usart transmitter and receiver operate in a normal asynchronous mode and all parameters are accessible. note that the modulator and the demodulator are activated. figure 40-32. connection to irda transceivers the receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed. to receive irda signals, the following needs to be done: ? disable tx and enable rx ? configure the txd pin as pio and set it as an output to 0 (to avoid led emission). disable the internal pull-up (better for power consumption). ? receive data 40.7.5.1 irda modulation for baud rates up to and including 115.2 kbits/sec, the rzi modulation scheme is used. 0 is represented by a light pulse of 3/16th of a bit time. some examples of signal pulse duration are shown in table 40-12 . irda transceivers rxd rx txd tx usart demodulator modulator receiver transmitter table 40-12. irda pulse duration baud rate pulse duration (3/16) 2.4 kb/s 78.13 s 9.6 kb/s 19.53 s 19.2 kb/s 9.77 s 38.4 kb/s 4.88 s 57.6 kb/s 3.26 s 115.2 kb/s 1.63 s
806 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 806 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 40-33 shows an example of character transmission. figure 40-33. irda modulation 40.7.5.2 irda baud rate table 40-13 gives some examples of cd values, baud rate error and pulse duration. note that the requirement on the maximum acceptable error of 1.87% must be met. bit period bit period 3 16 start bit data bits stop bit 0 0 0 0 0 1 11 1 1 transmitter output txd table 40-13. irda baud rate error peripheral clock baud rate cd baud rate error pulse time 3 686 400 115 200 2 0.00% 1.63 20 000 000 115 200 11 1.38% 1.63 32 768 000 115 200 18 1.25% 1.63 40 000 000 115 200 22 1.38% 1.63 3 686 400 57 600 4 0.00% 3.26 20 000 000 57 600 22 1.38% 3.26 32 768 000 57 600 36 1.25% 3.26 40 000 000 57 600 43 0.93% 3.26 3 686 400 38 400 6 0.00% 4.88 20 000 000 38 400 33 1.38% 4.88 32 768 000 38 400 53 0.63% 4.88 40 000 000 38 400 65 0.16% 4.88 3 686 400 19 200 12 0.00% 9.77 20 000 000 19 200 65 0.16% 9.77 32 768 000 19 200 107 0.31% 9.77 40 000 000 19 200 130 0.16% 9.77 3 686 400 9 600 24 0.00% 19.53 20 000 000 9 600 130 0.16% 19.53 32 768 000 9 600 213 0.16% 19.53 40 000 000 9 600 260 0.16% 19.53
807 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 807 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.7.5.3 irda demodulator the demodulator is based on the irda receive filter co mprised of an 8-bit down counter which is loaded with the value programmed in us_if. when a falling edge is detected on the rxd pin, the filter counter starts counting down at the master clock (mck) speed. if a rising edge is detected on the rxd pin, the counter stops and is reloaded with us_if. if no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time. figure 40-34 illustrates the operations of the irda demodulator. figure 40-34. irda demodulator operations as the irda mode uses the same logic as the iso7816, note that the fi_di_ratio field in us_fidi must be set to a value higher than 0 in order to assure irda communications operate correctly. 40.7.6 rs485 mode the usart features the rs485 mode to enable li ne driver control. while operating in rs485 mode, the usart behaves as though in asynch ronous or synchronous mode and configuration of all the parameters is possible. the difference is that the rts pin is driven high when the transmitter is operating. the behavior of the rts pin is controlled by the txempty bit. a typical connection of the usart to a rs485 bus is shown in figure 40-35 . figure 40-35. typical connection to a rs485 bus 3 686 400 2 400 96 0.00% 78.13 20 000 000 2 400 521 0.03% 78.13 32 768 000 2 400 853 0.04% 78.13 table 40-13. irda baud rate error (continued) peripheral clock baud rate cd baud rate error pulse time mck rxd receiver input pulse rejected 65432 6 1 65432 0 pulse accepted counter value usart rts txd rxd differential bus
808 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 808 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 the usart is set in rs485 mode by programming the usart_mode field in the mode regis- ter (us_mr) to the value 0x1. the rts pin is at a level inverse to the txempt y bit. significantly, the rts pin remains high when a timeguard is programmed so that the line can remain driven after the last character com- pletion. figure 40-36 gives an example of the rts waveform during a character transmission when the timeguard is enabled. figure 40-36. example of rts drive with timeguard 40.7.7 spi mode the serial peripheral interface (spi) mode is a synchronous serial data link that provides com- munication with external devices in master or slave mode. it also enables communication between processors if an external processor is connected to the system. the serial peripheral interface is essentially a shift register that serially transmits data bits to other spis. during a data transfer, one spi system acts as the master which controls the data flow, while the other devices act as slaves'' whic h have data shifted into and out by the master. different cpus can take turns being masters and one master may simultaneously shift data into multiple slaves. (multiple master protocol is the opposite of single master protocol, where one cpu is always the master while all of the others are always slaves.) however, only one slave may drive its output to write data back to the master at any given time. a slave device is selected when its nss signal is asserted by the master. the usart in spi master mode can address only one spi slave because it can generate only one nss signal. the spi system consists of two data lines and two control lines: ? master out slave in (mosi): this data line supplies the output data from the master shifted into the input of the slave. ? master in slave out (miso): this data line supplies the output data from a slave to the input of the master. ? serial clock (sck): this control line is driven by the master and regulates the flow of the data bits. the master may transmit data at a variety of baud rates. the sck line cycles once for each bit that is transmitted. ? slave select (nss): this control line allows the master to select or deselect the slave. d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock tg = 4 write us_thr txrdy txempty rts
809 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 809 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.7.7.1 modes of operation the usart can operate in spi master mode or in spi slave mode. operation in spi master mode is programmed by writing to 0xe the usart_mode field in the mode register. in this case the spi lines must be connected as described below: ? the mosi line is driven by the output pin txd ? the miso line drives the input pin rxd ? the sck line is driven by the output pin sck ? the nss line is driven by the output pin rts operation in spi slave mode is programmed by writing to 0xf the usart_mode field in the mode register. in this case the spi lines must be connected as described below: ? the mosi line drives the input pin rxd ? the miso line is driven by the output pin txd ? the sck line drives the input pin sck ? the nss line drives the input pin cts in order to avoid unpredicted behavior, any change of the spi mode must be followed by a soft- ware reset of the transmitter and of the receiver (except the initial configuration after a hardware reset). (see section 40.7.8.3 ). 40.7.7.2 baud rate in spi mode, the baudrate generator operates in the same way as in usart synchronous mode: see baud rate in synchronous mode or spi mode on page 784. however, there are some restrictions: in spi master mode: ? the external clock sck must not be selected (usclks 0x3), and the bit clko must be set to 1 in the mode register (us_mr), in order to generate correctly the serial clock on the sck pin. ? to obtain correct behavior of the receiver and the transmitter, the value programmed in cd must be superior or equal to 6. ? if the internal clock divided (mck/div) is selected, the value programmed in cd must be even to ensure a 50:50 mark/space ratio on the sck pin, this value can be odd if the internal clock is selected (mck). in spi slave mode: ? the external clock (sck) selection is forced regardless of the value of the usclks field in the mode register (us_mr). likewise, the value written in us_brgr has no effect, because the clock is provided directly by the signal on the usart sck pin. ? to obtain correct behavior of the receiver and the transmitter, the external clock (sck) frequency must be at least 6 times lower than the system clock.
810 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 810 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.7.7.3 data transfer up to 9 data bits are successively shifted out on the txd pin at each rising or falling edge (depending of cpol and cpha) of the programmed serial clock. there is no start bit, no parity bit and no stop bit. the number of data bits is selected by the chrl field and the mode 9 bit in the mode register (us_mr). the 9 bits are selected by setting the mode 9 bit regardless of the chrl field. the msb data bit is always sent first in spi mode (master or slave). four combinations of polarity and phase are available for data transfers. the clock polarity is programmed with the cpol bit in the mode regi ster. the clock phase is programmed with the cpha bit. these two parameters determine the edges of the clock signal upon which data is driven and sampled. each of the two parameters has two possible states, resulting in four possi- ble combinations that are incompatible with one another. thus, a master/slave pair must use the same parameter pair values to communicate. if multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a dif- ferent slave. figure 40-37. spi transfer format (cpha=1, 8 bits per transfer) table 40-14. spi bus protocol mode spi bus protocol mode cpol cpha 001 100 211 310 6 sck (cpol = 0) sck (cpol = 1) mosi spi master ->txd spi slave -> rxd nss spi master -> rts spi slave -> cts sck cycle (for reference) msb msb lsb lsb 6 6 5 5 4 4 3 3 2 2 1 1 1 2345 78 6 miso spi master ->rxd spi slave -> txd
811 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 811 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 40-38. spi transfer format (cpha=0, 8 bits per transfer) 40.7.7.4 receiver and transmitter control see receiver and transmitter control on page 786. 40.7.7.5 character transmission the characters are sent by writing in the tran smit holding register (us_thr). an additional condition for transmitting a character can be ad ded when the usart is configured in spi mas- ter mode. in the usart_mr register, the va lue configured on inack field can prevent any character transmission (even if us_thr has been written) while the receiver side is not ready (character not read). when wrdbt equals 0, the character is transmitted whatever the receiver status. if wrdbt is set to 1, the transmitter waits for the receiver holding register to be read before transmitting the character (rxrdy flag cl eared), thus preventing any overflow (character loss) on the receiver side. the transmitter reports two status bits in the channel status register (us_csr): txrdy (transmitter ready), which indicates that us_thr is empty and txempty, which indicates that all the characters written in us_thr have been processed. when the current character pro- cessing is completed, the last ch aracter written in us_thr is transferred into the shift register of the transmitter and us_thr becomes empty, thus txrdy rises. both txrdy and txempty bits are low when the transmitter is disabled. writing a character in us_thr while txrdy is low has no effect and the written character is lost. if the usart is in spi slave mode and if a character must be sent while the transmit holding register (us_thr) is empty, the unre (underru n error) bit is set. the txd transmission line stays at high level during all th is time. the unre bit is cleared by writing the control register (us_cr) with the rststa (reset status) bit to 1. in spi master mode, the slave select line (nss) is asserted at low level 1 tbit (time bit) before the transmission of the msb bit and released at high level 1 tbit after the transmission of the lsb bit. so, the slave select line (nss) is always released between each character transmission sck (cpol = 0) sck (cpol = 1) 1 2345 7 mosi spi master -> txd spi slave -> rxd miso spi master -> rxd spi slave -> txd nss spi master -> rts spi slave -> cts sck cycle (for reference) 8 msb msb lsb lsb 6 6 5 5 4 4 3 3 1 1 2 2 6
812 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 812 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 and a minimum delay of 3 tbits always inserted . however, in order to address slave devices supporting the csaat mode (chip select active after transfer), the slave select line (nss) can be forced at low level by writing the control register (us_cr) with the rtsen bit to 1. the slave select line (nss) can be released at high level only by writing the control register (us_cr) with the rtsdis bit to 1 (for example, when all data have been transferred to the slave device). in spi slave mode, the transmitter does not require a falling edge of the slave select line (nss) to initiate a character transmission but only a low level. however, this lo w level must be present on the slave select line (nss) at least 1 tbit before the first serial clock cycle corresponding to the msb bit. 40.7.7.6 character reception when a character reception is completed, it is transferred to the receive holding register (us_rhr) and the rxrdy bit in the status register (us_csr) rises. if a character is com- pleted while rxrdy is set, the ovre (overrun erro r) bit is set. the last character is transferred into us_rhr and overwrites the pr evious one. the ovre bit is cleared by writing the control register (us_cr) with the rststa (reset status) bit to 1. to ensure correct behavior of the receiver in spi slave mode, the master device sending the frame must ensure a minimum delay of 1 tb it between each character transmission. the receiver does not require a falling edge of the slave select line (nss) to initiate a character reception but only a low level. however, this low level must be present on the slave select line (nss) at least 1 tbit before the first serial clock cycle corresponding to the msb bit. 40.7.7.7 receiver timeout because the receiver baudrate clock is active only during data transfers in spi mode, a receiver timeout is impossible in this mode, whatever the time-out value is (field to) in the time-out register (us_rtor). 40.7.8 lin mode the lin mode provides master node and slave node connectivity on a lin bus. the lin (local interconnect network) is a serial communication protocol which efficiently sup- ports the control of mechatronic nodes in distributed automotive applications. the main properties of the lin bus are: ? single master/multiple slaves concept ? low cost silicon implementation based on common uart/sci interface hardware, an equivalent in software, or as a pure state machine. ? self synchronization without quartz or ceramic resonator in the slave nodes ? deterministic signal transmission ? low cost single-wire implementation ? speed up to 20 kbit/s lin provides cost efficient bu s communication where the bandwid th and versatility of can are not required. the lin mode enables processing lin frames with a minimum of action from the microprocessor.
813 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 813 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.7.8.1 modes of operation the usart can act either as a lin master node or as a lin slave node. the node configuration is chosen by setting the usart_mode field in the usart mode regis- ter (us_mr): ? lin master node (usart_mode=0xa) ? lin slave node (usart_mode=0xb) in order to avoid unpredicted behavior, any change of the lin node configuration must be fol- lowed by a software reset of the transmitter and of the receiver (except the initial node configuration after a hardware reset). (see section 40.7.8.3 ) 40.7.8.2 baud rate configuration see baud rate in asynchronous mode on page 782. the baud rate is configured in the baud rate generator register (us_brgr). 40.7.8.3 receiver and transmitter control see receiver and transmitter control on page 786. 40.7.8.4 character transmission see transmitter operations on page 786. 40.7.8.5 character reception see receiver operations on page 795. 40.7.8.6 header transmission (master node configuration) all the lin frames start with a header which is sent by the master node and consists of a synch break field, synch field and identifier field. so in master node configuration, the frame handling starts with the sending of the header. the header is transmitted as soon as the identifier is written in the lin identifier register (us_linir). at this moment the flag txrdy falls. the break field, the synch field and the identifier field are sent automatically one after the other. the break field consists of 13 dominant bits and 1 recessive bit, the synch field is the charac- ter 0x55 and the identifier corresponds to the character written in the lin identifier register (us_linir). the identifier parity bits can be automatically computed and sent (see section 40.7.8.9 ). the flag txrdy rises when the identifier character is transferred into the shift register of the transmitter. as soon as the synch break field is transmitted, the flag linbk in the channel status register (us_csr) is set to 1. likewise, as soon as the id entifier field is sent, the flag linid in the chan- nel status register (us_csr) is set to 1. these flags are reset by writing the bit rststa to 1 in the control register (us_cr).
814 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 814 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 40-39. header transmission 40.7.8.7 header reception (slave node configuration) all the lin frames start with a header which is sent by the master node and consists of a synch break field, synch field and identifier field. in slave node configuration, the frame handling starts with the reception of the header. the usart uses a break detection threshold of 11 nominal bit times at the actual baud rate. at any time, if 11 consecutive rece ssive bits are detected on the bus, the usart detects a break field. as long as a break field has not been detected, the usart stays idle and the received data are not taken in account. when a break field has been detected, the flag linbk in the channel status register (us_csr) is set to 1 and the usart expects the synch field character to be 0x55. this field is used to update the actual baud rate in order to stay synchronized (see section 40.7.8.8 ). if the received synch character is not 0x55, an inc onsistent synch field error is generated (see sec- tion 40.7.8.14 ). after receiving the synch field, the usart expects to receive the identifier field. when the identifier field has been received, the flag linid in the channel status register (us_csr) is set to 1. at this moment the field idchr in the lin identifier register (us_linir) is updated with the received character. the identifier parity bits can be automatically computed and checked (see section 40.7.8.9 ). the flags linid and linbk are reset by writing the bit rststa to 1 in the control register (us_cr). txd baud rate clock start bit write us_linir 10101010 txrdy stop bit start bit id0 id1 id2 id3 id4 id5 id6 id7 break field 13 dominant bits (at 0) stop bit break delimiter 1 recessive bit (at 1) synch byte = 0x55 us_linir id linid in us_csr linbk in us_csr write rststa=1 in us_cr
815 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 815 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 40-40. header reception 40.7.8.8 slave node synchronization the synchronization is done only in slave node configuration. the procedure is based on time measurement between falling edges of the synch field. the falling edges are available in dis- tances of 2, 4, 6 and 8 bit times. figure 40-41. synch field the time measurement is made by a 19-bit counter clocked by the sampling clock (see section 40.7.1 ). when the start bit of the synch field is detect ed, the counter is reset. then during the next 8 tbits of the synch field, the counter is incremen ted. at the end of these 8 tbits, the counter is stopped. at this moment, the 16 most significant bi ts of the counter (value divided by 8) give the new clock divider (lincd) and the 3 least significant bits of this value (the remainder) give the new fractional part (linfp). when the synch field has been re ceived, the clock divider (cd) and the fractional part (fp) are updated in the baud rate generator register (us_brgr). if it appears that the sampled synch character is not equal to 0x55, then the error flag linisfe in the channel status register (us_csr) is set to 1. it is reset by writin g bit rststa to 1 in the control register (us_cr). rxd baud rate clock write rststa=1 in us_cr linid us_linir linbk start bit 10101010 stop bit start bit id0 id1 id2 id3 id4 id5 id6 id7 break field 13 dominant bits (at 0) stop bit break delimiter 1 recessive bit (at 1) synch byte = 0x55 start bit stop bit synch field 8 tbit 2 tbit 2 tbit 2 tbit 2 tbit
816 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 816 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 40-42. slave node synchronization the accuracy of the synchronization depends on several parameters: ? the nominal clock frequency (f nom ) (the theoretical slave node clock frequency) ? the baud rate ? the oversampling (over=0 => 16x or over=0 => 8x) the following formula is used to compute the deviation of the slave bit rate relative to the master bit rate after synchronization (f slave is the real slave node clock frequency). f tol_unsynch is the deviation of the real slave node clock from the nominal clock frequency. the lin standard imposes that it must not exceed 15%. the lin standard imposes also that for communication between two nodes, their bit rate must not differ by more than 2%. this means that the baudrate_deviation must not exceed 1%. it follows from that, a minimum value for the nominal clock frequency: rxd baud rate clock linidrx synchro counter 000_0011_0001_0110_1101 us_brgr clcok divider (cd) us_brgr fractional part (fp) initial cd initial fp reset us_linbrr clcok divider (cd) 0000_0110_0010_1101 us_linbrr fractional part (fp) 101 initial cd initial fp start bit 10101010 stop bit start bit id0 id1 id2 id3 id4 id5 id6 id7 break field 13 dominant bits (at 0) stop bit break delimiter 1 recessive bit (at 1) synch byte = 0x55 baudrate_deviation 100 [ 82over ? () + ] baudrate 8f slave ---------------------------------------------------------------------------------------------- - ?? ?? % = baudrate_deviation 100 [ 82over ? () + ] baudrate 8 f tol_unsynch 100 --------------------------------------- ?? ?? xf nom ---------------------------------------------------------------------------------------------- - ?? ?? ?? ?? ?? % = 0.5 ? +0.5 -1 +1 << ? f nom min () 100 0.5 8 2 over ? () 1 + [] baudrate 8 15 ? 100 --------- - 1 + ?? ?? 1% --------------------------------------------------------------------------------------------------- ?? ?? ?? ?? ?? hz =
817 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 817 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 examples: ? baudrate = 20 kbit/s, over=0 (oversampling 16x) => f nom (min) = 2.64 mhz ? baudrate = 20 kbit/s, over=1 (oversampling 8x) => f nom (min) = 1.47 mhz ? baudrate = 1 kbit/s, over=0 (oversampling 16x) => f nom (min) = 132 khz ? baudrate = 1 kbit/s, over=1 (oversampling 8x) => f nom (min) = 74 khz 40.7.8.9 identifier parity a protected identifier consists of two sub-fields; the identifier and the identifier parity. bits 0 to 5 are assigned to the identifier and bits 6 and 7 are assigned to the parity. the usart interface can generate/check these parity bits, but this feature can also be disabled. the user can choose between two modes by the pardis bit of the lin mode register (us_linmr): ? pardis = 0: during header transmission, the parity bits are computed and sent with the 6 least significant bits of the idchr field of the lin identifier register (us_linir). the bits 6 and 7 of this register are discarded. during header reception, the parity bits of the identifier are checked. if the parity bits are wrong, an identifier parity error occurs (see section 40.7.3.8 ). only the 6 least significant bits of the idchr field are updated with the received identifier. the bits 6 and 7 are stuck to 0. ? pardis = 1: during header transmission, all the bits of the idchr field of the lin identifier register (us_linir) are sent on the bus. during header reception, all the bits of the idchr field are updated with the received identifier. 40.7.8.10 node action in function of the identifier, the node is concerned, or not, by the lin response. consequently, after sending or receiving the identifier, the us art must be configured. there are three possi- ble configurations: ? publish: the node sends the response. ? subscribe: the node receives the response. ? ignore: the node is not concerned by the response, it does not send and does not receive the response. this configuration is made by the field, node action (nact), in the us_linmr register (see section 40.8.26 ). example: a lin cluster that contains a master and two slaves: ? data transfer from the master to the slave 1 and to the slave 2: nact(master)=publish nact(slave1)=subscribe nact(slave2)=subscribe ? data transfer from the master to the slave 1 only: nact(master)=publish
818 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 818 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 nact(slave1)=subscribe nact(slave2)=ignore ? data transfer from the slave 1 to the master: nact(master)=subscribe nact(slave1)=publish nact(slave2)=ignore ? data transfer from the slave1 to the slave2: nact(master)=ignore nact(slave1)=publish nact(slave2)=subscribe ? data transfer from the slave2 to the master and to the slave1: nact(master)=subscribe nact(slave1)=subscribe nact(slave2)=publish 40.7.8.11 response data length the lin response data length is the number of data fields (bytes) of the response excluding the checksum. the response data length can either be configur ed by the user or be defined automatically by bits 4 and 5 of the identifier (compatibility to lin specification 1.1). the user can choose between these two modes by the dlm bit of the lin mode register (us_linmr): ? dlm = 0: the response data length is configured by the user via the dlc field of the lin mode register (us_linmr). the response data length is equal to (dlc + 1) bytes. dlc can be programmed from 0 to 255, so the response can contain from 1 data byte up to 256 data bytes. ? dlm = 1: the response data length is de fined by the identifier (idchr in us_linir) according to the table below. the dlc field of the lin mode register (us_linmr) is discarded. the response can contain 2 or 4 or 8 data bytes. table 40-15. response data length if dlm = 1 idchr[5] idchr[4] response data length [bytes] 00 2 01 2 10 4 11 8
819 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 819 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 40-43. response data length 40.7.8.12 checksum the last field of a frame is the checksum. the checksum contains the inverted 8- bit sum with carry, over all data bytes or all data bytes and the protected identifier. checksum calculation over the data bytes only is called classic checks um and it is used for communication with lin 1.3 slaves. checksum calculation over the data by tes and the protected identifier byte is called enhanced checksum and it is used for communication with lin 2.0 slaves. the usart can be configured to: ? send/check an enhanced checksum automatically (chkdis = 0 & chktyp = 0) ? send/check a classic checksum automatically (chkdis = 0 & chktyp = 1) ? not send/check a checksum (chkdis = 1) this configuration is made by the checksum type (chktyp) and ch ecksum disable (chkdis) fields of the lin mode register (us_linmr). if the checksum feature is disabled, the user can send it manually all the same, by considering the checksum as a normal data byte and by adding 1 to the response data length (see section 40.7.8.11 ). 40.7.8.13 frame slot mode this mode is useful only for master nodes. it respects the following rule: each frame slot shall be longer than or equal to tframe_maximum. if the frame slot mode is enabled (fsdis = 0) and a frame transfer has been completed, the txrdy flag is set again only after tframe_maximum delay, from the start of frame. so the mas- ter node cannot send a new header if the frame slot duration of the previous frame is inferior to tframe_maximum. if the frame slot mode is disabled (fsdis = 1) and a frame transfer has been completed, the txrdy flag is set again immediately. the tframe_maximum is calculated as below: if the checksum is sent (chkdis = 0): ? theader_nominal = 34 x tbit ? tresponse_nominal = 10 x (ndata + 1) x tbit ? tframe_maximum = 1.4 x (theader_nominal + tresponse_nominal + 1) (note:) ? tframe_maximum = 1.4 x (34 + 10 x (dlc + 1 + 1) + 1) x tbit ? tframe_maximum = (77 + 14 x dlc) x tbit if the checksum is not sent (chkdis = 1): user configuration: 1 - 256 data fields (dlc+1) identifier configuration: 2/4/8 data fields sync break sync field identifier field checksum field data field data field data field data field
820 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 820 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? theader_nominal = 34 x tbit ? tresponse_nominal = 10 x ndata x tbit ? tframe_maximum = 1.4 x (theader_nominal + tresponse_nominal + 1 (note:) ) ? tframe_maximum = 1.4 x (34 + 10 x (dlc + 1) + 1) x tbit ? tframe_maximum = (63 + 14 x dlc) x tbit note: the term +1 leads to an integer re sult for tframe_max (lin specification 1.3) figure 40-44. frame slot mode 40.7.8.14 lin errors bit error this error is generated in master of slave node configuration, when the usart is transmitting and if the transmitted value on the tx line is different from the value sampled on the rx line. if a bit error is detected, the transmission is aborted at the next byte border. this error is reported by flag linbe in the channel status register (us_csr). inconsistent synch field error this error is generated in slave node configuration, if the synch field character received is other than 0x55. this error is reported by flag linisfe in the channel status register (us_csr). identifier parity error this error is generated in slave node configuration, if the parity of the identifier is wrong. this error can be generated only if the parity feature is enabled (pardis = 0). this error is reported by flag linipe in the channel status register (us_csr). checksum error this error is generated in master of slave node configuration, if the received checksum is wrong. this flag can be set to 1 only if the checksum feature is enabled (chkdis = 0). this error is reported by flag lince in the channel status register (us_csr). break synch protected identifier data n checksum header inter- frame space response space frame frame slot = tframe_maximum response txrdy write us_thr write us_linid data 1 data 2 data 3 data3 data n-1 data n frame slot mode disabled frame slot mode enabled lintc data 1
821 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 821 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 slave not responding error this error is generated in master of slave node configuration, when the usart expects a response from another node (nact = subscribe) but no valid message appears on the bus within the time given by the maximum length of the message frame, tframe_maximum (see section 40.7.8.13 ). this error is disabled if the us art does not expect any message (nact = publish or nact = ignore). this error is reported by flag linsnre in the channel status register (us_csr). 40.7.8.15 lin frame handling master node configuration ? write txen and rxen in us_cr to enable both the transmitter and the receiver. ? write usart_mode in us_mr to select the lin mode and the master node configuration. ? write cd and fp in us_brgr to configure the baud rate. ? write nact, pardis, chkdis, chktype, dlcm, fsdis and dlc in us_linmr to configure the frame transfer. ? check that txrdy in us_csr is set to 1 ? write idchr in us_linir to send the header what comes next depends on the nact configuration: ? case 1: nact = publish, the usart sends the response C wait until txrdy in us_csr rises C write tchr in us_thr to send a byte C if all the data have not been written, redo the two previous steps C wait until lintc in us_csr rises C check the lin errors ? case 2: nact = subscribe, the usart receives the response C wait until rxrdy in us_csr rises C read rchr in us_rhr C if all the data have not been read, redo the two previous steps C wait until lintc in us_csr rises C check the lin errors ? case 3: nact = ignore, the usart is not concerned by the response C wait until lintc in us_csr rises C check the lin errors
822 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 822 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 40-45. master node configuration, nact = publish figure 40-46. master node configur ation, nact=subscribe frame break synch protected identifier data 1 data n checksum txrdy write us_thr write us_linir data 1 data 2 data 3 data n-1 data n rxrdy header inter- frame space response space frame slot = tframe_maximum response data3 lintc fsdis=1 fsdis=0 break synch protected identifier data 1 data n checksum txrdy read us_rhr write us_linir data 1 data n-1 data n-1 rxrdy data n data n-2 header inter- frame space response space frame frame slot = tframe_maximum response data3 lintc fsdis=0 fsdis=1
823 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 823 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 40-47. master node configuration, nact=ignore slave node configuration ? write txen and rxen in us_cr to enable both the transmitter and the receiver. ? write usart_mode in us_mr to select the lin mode and the slave node configuration. ? write cd and fp in us_brgr to configure the baud rate. ? wait until linid in us_csr rises ? check linisfe and linpe errors ? read idchr in us_rhr ? write nact, pardis, chkdis, chktype, dlcm and dlc in us_linmr to configure the frame transfer. important : if the nact configuration for this frame is publish, the us_linmr register, must be write with nact = publish even if this field is already correctly configured, in order to set the txready flag and the corresponding write transfer request. what comes next depends on the nact configuration: ? case 1: nact = publish, the lin controller sends the response C wait until txrdy in us_csr rises C write tchr in us_thr to send a byte C if all the data have not been written, redo the two previous steps C wait until lintc in us_csr rises C check the lin errors ? case 2: nact = subscribe, the usart receives the response C wait until rxrdy in us_csr rises C read rchr in us_rhr C if all the data have not been read, redo the two previous steps C wait until lintc in us_csr rises C check the lin errors ? case 3: nact = ignore, the usart is not concerned by the response C wait until lintc in us_csr rises txrdy write us_linir rxrdy lintc break synch protected identifier data 1 data n checksum data n-1 header inter- frame space response space frame frame slot = tframe_maximum response data3 fsdis=1 fsdis=0
824 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 824 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 C check the lin errors figure 40-48. slave node configuration, nact = publish figure 40-49. slave node configuration, nact = subscribe figure 40-50. slave node configurat ion, nact = ignore break synch protected identifier data 1 data n checksum txrdy write us_thr read us_linid data 1 data 3 data n-1 data n rxrdy linidrx data 2 lintc txrdy read us_rhr read us_linid rxrdy linidrx lintc break synch protected identifier data 1 data n checksum data 1 data n-1 data n-1 data n data n-2 txrdy read us_rhr read us_linid rxrdy linidrx lintc break synch protected identifier data 1 data n checksum data n-1
825 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 825 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.7.8.16 lin frame handling with the dmac the usart can be dmacused in association with the dmac in order to transfer data directly into/from the on- and off-chip memories without any processor intervention. the dmac uses the trigger flags, txrdy and rxrdy, to write or read into the usart. the dmac always writes in the transmit holding register (us_thr) and it always reads in the receive holding register (us_rhr). the size of th e data written or read by the dmac in the usart is always a byte. master node configuration the user can choose between two dmac modes by the pdcm bit in the lin mode register (us_linmr): ? pdcm = 1: the lin configuration is stored in th e write buffer and it is written by the dmac in the transmit holding register us_thr (ins tead of the lin mode register us_linmr). because the dmac transfer size is limited to a byte, the transfer is split into two accesses. during the first access the bits, nact, pardis, chkdis, chktyp, dlm and fsdis are written. during the second access the 8-bit dlc field is written. ? pdcm = 0: the lin configuration is not stored in the write buffer and it must be written by the user in the lin mode register (us_linmr). the write buffer also contains the identifier and the data, if the usart sends the response (nact = publish). the read buffer contains the data if the usart receives the response (nact = subscribe). figure 40-51. master node with dmac (pdcm = 1) | | | | | | | | nact pardis chkdis chktyp dlm fsdis dlc identifier data 0 data n write buffer (peripheral) dma controller (peripheral) dma controller usart3 lin controller apb bus nact pardis chkdis chktyp dlm fsdis dlc identifier data 0 data n write buffer rxrdy txrdy txrdy usart3 lin controller apb bus read buffer node action = publish node action = subscribe
826 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 826 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 40-52. master node with dmac (pdcm = 0) slave node configuration in this configuration, the dmac transfers only th e data. the identifier must be read by the user in the lin identifier register (us_linir). the lin mode must be written by the user in the lin mode register (us_linmr). the write buffer contains the data if the usart sends the response (nact=publish). the read buffer contains the data if the usart receives the response (nact=subscribe). figure 40-53. slave node with dmac | | | | rxrdy txrdy txrdy apb bus usart3 lin controller data 0 data n | | | | write buffer usart3 lin controller read buffer node action = publish node action = subscribe apb bus identifier data 0 data n write buffer identifier (peripheral) dma controller (peripheral) dma controller | | | | | | | | data 0 data n rxrdy usart3 lin controller apb bus read buffer nact = subscribe data 0 data n txrdy usart3 lin controller apb bus write buffer (peripheral) dma controller (peripheral) dma controller
827 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 827 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.7.8.17 wake-up request any node in a sleeping lin cluster may request a wake-up. in the lin 2.0 specification, the wakeup reques t is issued by forcing the bus to the dominant state from 250 s to 5 ms. for this, it is necessa ry to send the character 0xf0 in order to impose 5 successive dominant bits. whatever the baud rate is, this character respects the specified timings. ? baud rate min = 1 kbit/s -> tbit = 1ms -> 5 tbits = 5 ms ? baud rate max = 20 kbit/s -> tbi t= 50 s -> 5 tbits = 250 s in the lin 1.3 specification, the wakeup request should be generated with the character 0x80 in order to impose 8 successive dominant bits. the user can choose by the wkuptyp bit in the lin mode register (us_linmr) either to send a lin 2.0 wakeup request (wkuptyp=0) or to send a lin 1.3 wakeup request (wkuptyp=1). a wake-up request is transmitte d by writing the control regist er (us_cr) with the linwkup bit to 1. once the transfer is completed, the lintc flag is asserted in the status register (us_sr). it is cleared by writing the control re gister (us_cr) with the rststa bit to 1. 40.7.8.18 bus idle time-out if the lin bus is inactive for a certain duration, the slave nodes shall automatically enter in sleep mode. in the lin 2.0 specification, this time-out is fixed at 4 seconds. in the lin 1.3 specifica- tion, it is fixed at 25000 tbits. in slave node configuration, the receiver time-out detects an idle condition on the rxd line. when a time-out is detected, the bit timeout in the channel status register (us_csr) rises and can generate an interrupt, thus indicating to the driver to go into sleep mode. the time-out delay period (during which the receiver waits for a new character) is programmed in the to field of the receiver time-out regist er (us_rtor). if the to field is programmed to 0, the receiver time-out is disabled and no time-out is detected. the timeout bit in us_csr remains to 0. otherwise, the receiver loads a 17-bit counter with the value programmed in to. this counter is decremented at each bit per iod and reloaded each time a new character is received. if the counter reaches 0, the timeout bit in the status register rises. if sttto is performed, the counter clock is stopped until a first character is received. if retto is performed, the counter starts counting down immediately from the value to. receiver time-out programming lin specification baud rate time-out period to 2.0 1 000 bit/s 4s 4 000 2 400 bit/s 9 600 9 600 bit/s 38 400 19 200 bit/s 76 800 20 000 bit/s 80 000 1.3 - 25 000 tbits 25 000
828 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 828 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.7.9 test modes the usart can be programmed to operate in three different test modes. the internal loopback capability allows on-boar d diagnostics. in the loopback mode the usart interface pins are dis- connected or not and reconfigured for loopback internally or externally. 40.7.9.1 normal mode normal mode connects the rxd pin on the receiver input and the transmitter output on the txd pin. figure 40-54. normal mode configuration 40.7.9.2 automatic echo mode automatic echo mode allows bit-by-bit retransmission. when a bit is received on the rxd pin, it is sent to the txd pin, as shown in figure 40-55 . programming the transmitter has no effect on the txd pin. the rxd pin is still connected to the receiver input, thus the receiver remains active. figure 40-55. automatic echo mode configuration 40.7.9.3 local loopback mode local loopback mode c onnects the output of the transmitter directly to the input of the receiver, as shown in figure 40-56 . the txd and rxd pins are not used. the rxd pin has no effect on the receiver and the txd pin is continuously driven high, as in idle state. figure 40-56. local loopback mode configuration receiver transmitter rxd txd receiver transmitter rxd txd receiver transmitter rxd txd 1
829 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 829 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.7.9.4 remote loopback mode remote loopback mode directly connects the rxd pin to the txd pin, as shown in figure 40-57 . the transmitter and the receiver are disabled an d have no effect. this mode allows bit-by-bit retransmission. figure 40-57. remote loopback mode configuration 40.7.10 write protection registers to prevent any single software error that may corrupt usart behavior, certain address spaces can be write-protected by setting the wpen bit in the usart write protect mode register (us_wpmr). if a write access to the protected registers is detected, then the wpvs flag in the usart write protect status register (us_wpsr) is set and the field wpvsr c indicates in which r egister the write access has been attempted. the wpvs flag is automatically reset by reading the usart write protect mode register (us_wpmr) with the appropri- ate access key, wpkey. the protected registers are: ? usart mode register ? usart baud rate generator register ? usart receiver time-out register ? usart transmitter timeguard register ? usart fi di ratio register ? usart irda filter register ? usart manchester configuration register receiver transmitter rxd txd 1
830 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 830 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8 universal synchronous async hronous receiver transmitter (usart) user interface notes: 1. write is possible only in lin master node configuration. table 40-16. register mapping offset register name access reset 0x0000 control register us_cr write-only C 0x0004 mode register us_mr read-write C 0x0008 interrupt enable register us_ier write-only C 0x000c interrupt disable register us_idr write-only C 0x0010 interrupt mask register us_imr read-only 0x0 0x0014 channel status register us_csr read-only C 0x0018 receiver holding register us_rhr read-only 0x0 0x001c transmitter holding register us_thr write-only C 0x0020 baud rate generator register us_brgr read-write 0x0 0x0024 receiver time-out register us_rtor read-write 0x0 0x0028 transmitter timeguard register us_ttgr read-write 0x0 0x2c - 0x3c reserved C C C 0x0040 fi di ratio regist er us_fidi read-write 0x174 0x0044 number of errors register us_ner read-only C 0x0048 reserved C C C 0x004c irda filter regi ster us_if read-write 0x0 0x0050 manchester encoder decoder register us_man read-write 0xb0011004 0x0054 lin mode register us_linmr read-write 0x0 0x0058 lin identifier register us_linir read-write (1) 0x0 0xe4 write protect mode register us_wpmr read-write 0x0 0xe8 write protect status register us_wpsr read-only 0x0 0x5c - 0xfc reserved C C C
831 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 831 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8.1 usart control register name: us_cr address: 0xf801c000 (0), 0xf8020000 (1), 0xf8024000 (2), 0xf8028000 (3) access: write-only for spi control, see usart control register (spi_mode) on page 834 . ? rstrx: reset receiver 0: no effect. 1: resets the receiver. ? rsttx: reset transmitter 0: no effect. 1: resets the transmitter. ? rxen: receiver enable 0: no effect. 1: enables the receiver, if rxdis is 0. ? rxdis: receiver disable 0: no effect. 1: disables the receiver. ? txen: transmitter enable 0: no effect. 1: enables the transmitter if txdis is 0. ? txdis: transmitter disable 0: no effect. 1: disables the transmitter. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 C C linwkup linabt rtsdis rtsen C C 15 14 13 12 11 10 9 8 retto rstnack rstit senda sttto stpbrk sttbrk rststa 76543210 txdis txen rxdis rxen rsttx rstrx C C
832 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 832 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? rststa: reset status bits 0: no effect. 1: resets the status bits pare, frame, ovre, manerr, linbe, linisfe, linipe, lince, linsnre, linid, lintc, linbk and rxbrk in us_csr. ? sttbrk: start break 0: no effect. 1: starts transmission of a break after the characters present in us_thr and the transmit shi ft register have been trans- mitted. no effect if a break is already being transmitted. ? stpbrk: stop break 0: no effect. 1: stops transmission of the break after a minimum of one char acter length and transmits a high level during 12-bit periods. no effect if no break is being transmitted. ? sttto: start time-out 0: no effect. 1: starts waiting for a character before clocking the time-out counter. resets the status bit timeout in us_csr. ? senda: send address 0: no effect. 1: in multidrop mode only, the next character written to the us_thr is sent with the address bit set. ? rstit: reset iterations 0: no effect. 1: resets iteration in us_csr. no e ffect if the iso7816 is not enabled. ? rstnack: reset non acknowledge 0: no effect 1: resets nack in us_csr. ? retto: rearm time-out 0: no effect 1: restart time-out ? rtsen: request to send enable 0: no effect. 1: drives the pin rts to 0. ? rtsdis: request to send disable 0: no effect. 1: drives the pin rts to 1.
833 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 833 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? linabt: abort lin transmission 0: no effect. 1: abort the current lin transmission. ? linwkup: send lin wakeup signal 0: no effect: 1: sends a wakeup signal on the lin bus.
834 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 834 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8.2 usart control register (spi_mode) name: us_cr (spi_mode) address: 0xf801c000 (0), 0xf8020000 (1), 0xf8024000 (2), 0xf8028000 (3) access: write-only this configuration is relevant only if usart_mode=0xe or 0xf in usart mode register on page 836 . ? rstrx: reset receiver 0: no effect. 1: resets the receiver. ? rsttx: reset transmitter 0: no effect. 1: resets the transmitter. ? rxen: receiver enable 0: no effect. 1: enables the receiver, if rxdis is 0. ? rxdis: receiver disable 0: no effect. 1: disables the receiver. ? txen: transmitter enable 0: no effect. 1: enables the transmitter if txdis is 0. ? txdis: transmitter disable 0: no effect. 1: disables the transmitter. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCr c sf c sCC 15 14 13 12 11 10 9 8 CCCCCCCr s t s t a 76543210 txdis txen rxdis rxen rsttx rstrx C C
835 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 835 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? rststa: reset status bits 0: no effect. 1: resets the status bits ovre, unre in us_csr. ? fcs: force spi chip select C applicable if usart operates in spi master mode (usart_mode = 0xe): fcs = 0: no effect. fcs = 1: forces the slave select line nss (rts pin) to 0, ev en if usart is no transmitting, in order to address spi slave devices supporting the csaat mode (chip select active after transfer). ? rcs: release spi chip select C applicable if usart operates in spi master mode (usart_mode = 0xe): rcs = 0: no effect. rcs = 1: releases the slave select line nss (rts pin).
836 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 836 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8.3 usart mode register name: us_mr address: 0xf801c004 (0), 0xf8020004 (1), 0xf8024004 (2), 0xf8028004 (3) access: read-write this register can only be written if the wpen bit is cleared in usart write protect mode register on page 870 . for spi configuration, see usart mode register (spi_mode) on page 840 . ? usart_mode: usart mode of operation ? usclks: clock selection 31 30 29 28 27 26 25 24 onebit modsync man filter C max_iteration 23 22 21 20 19 18 17 16 invdata var_sync dsnack inack over clko mode9 msbf 15 14 13 12 11 10 9 8 chmode nbstop par sync 76543210 chrl usclks usart_mode value name description 0x0 normal normal mode 0x1 rs485 rs485 0x2 hw_handshaking hardware handshaking 0x4 is07816_t_0 is07816 protocol: t = 0 0x6 is07816_t_1 is07816 protocol: t = 1 0x8 irda irda 0xa lin_master lin master 0xb lin_slave lin slave 0xe spi_master spi master 0xf spi_slave spi slave value name description 0 mck master clock mck is selected 1 div internal clock divided mck/div (div=8) is selected 3 sck serial clock slk is selected
837 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 837 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? chrl: character length. ? sync: synchronous mode select 0: usart operates in asynchronous mode. 1: usart operates in synchronous mode. ? par: parity type ? nbstop: number of stop bits ? chmode: channel mode ? msbf: bit order 0: least significant bit is sent/received first. 1: most significant bit is sent/received first. value name description 0 5_bit character length is 5 bits 1 6_bit character length is 6 bits 2 7_bit character length is 7 bits 3 8_bit character length is 8 bits value name description 0 even even parity 1 odd odd parity 2 space parity forced to 0 (space) 3 mark parity forced to 1 (mark) 4 no no parity 6 multidrop multidrop mode value name description 0 1_bit 1 stop bit 1 1_5_bit 1.5 stop bit (sync = 0) or reserved (sync = 1) 2 2_bit 2 stop bits value name description 0 normal normal mode 1 automatic automatic echo. receiver input is connected to the txd pin. 2 local_loopback local loopback. transmitter outp ut is connected to the receiver input. 3 remote_loopback remote loopback. rxd pin is internally connected to the txd pin.
838 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 838 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? mode9: 9-bit character length 0: chrl defines character length. 1: 9-bit character length. ? clko: clock output select 0: the usart does not drive the sck pin. 1: the usart drives the sck pin if usclks does not select the external clock sck. ? over: oversampling mode 0: 16x oversampling. 1: 8x oversampling. ? inack: inhibit non acknowledge 0: the nack is generated. 1: the nack is not generated. ? dsnack: disable successive nack 0: nack is sent on the iso line as soon as a parity erro r occurs in the received character (unless inack is set). 1: successive parity errors are counted up to the value spec ified in the max_iteration field. these parity errors gener- ate a nack on the iso line. as soon as this value is reached, no additional nack is sent on the iso line. the flag iteration is asserted. ?invdata: inverted data 0: the data field transmitted on txd line is the same as the one written in us_thr register or the content read in us_rhr is the same as rxd line. normal mode of operation. 1: the data field transmitted on txd line is inverted (voltage polarity only) compared to the value written on us_thr regis- ter or the content read in us_rhr is inverted compared to what is received on rxd line (or iso7816 io line). inverted mode of operation, useful for contactless card application. to be used with configuration bit msbf. ? var_sync: variable synchronization of command/data sync start frame delimiter 0: user defined configuration of command or data sync field depending on modsync value. 1: the sync field is updated when a char acter is written into us_thr register. ? max_iteration: maximum number of automatic iteration 0 - 7: defines the maximum number of iterations in mode iso7816, protocol t= 0. ? filter: infrared receive line filter 0: the usart does not filter the receive line. 1: the usart filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority). ? man: manchester encoder/decoder enable 0: manchester encoder/decoder are disabled. 1: manchester encoder/decoder are enabled.
839 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 839 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? modsync: manchester synchronization mode 0:the manchester start bit is a 0 to 1 transition 1: the manchester start bit is a 1 to 0 transition. ? onebit: start frame delimiter selector 0: start frame delimiter is command or data sync. 1: start frame delimiter is one bit.
840 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 840 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8.4 usart mode register (spi_mode) name: us_mr (spi_mode) address: 0xf801c004 (0), 0xf8020004 (1), 0xf8024004 (2), 0xf8028004 (3) access: read-write this configuration is relevant only if usart_mode=0xe or 0xf in usart mode register on page 836 . this register can only be written if the wpen bit is cleared in usart write protect mode register on page 870 . ? usart_mode: usart mode of operation ? usclks: clock selection ? chrl: character length. ? cpha: spi clock phase C applicable if usart operates in spi mode (usart_mode = 0xe or 0xf): cpha = 0: data is changed on the leading edge of spck and captured on the following edge of spck. cpha = 1: data is captured on the leading edge of spck and changed on the following edge of spck. cpha determines which edge of spck causes data to change and which edge causes data to be captured. cpha is used with cpol to produce the required clock/data relationship between master and slave devices. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 C C C wrdbt C cpol 15 14 13 12 11 10 9 8 CCCCCCCc p h a 76543210 chrl usclks usart_mode value name description 0xe spi_master spi master 0xf spi_slave spi slave value name description 0 mck master clock mck is selected 1 div internal clock divided mck/div (div= 8 ) is selected 3 sck serial clock slk is selected value name description 3 8_bit character length is 8 bits
841 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 841 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? chmode: channel mode ? cpol: spi clock polarity C applicable if usart operates in spi mode (s lave or master, usart_mode = 0xe or 0xf): cpol = 0: the inactive state va lue of spck is logic level zero. cpol = 1: the inactive state value of spck is logic level one. cpol is used to determine the inactive state value of the se rial clock (spck). it is used with cpha to produce the required clock/data relationship between master and slave devices. ? wrdbt: wait read data before transfer 0: the character transmission starts as soon as a character is written into us_thr register (assuming txrdy was set). 1: the character transmission starts when a character is wr itten and only if rxrdy flag is cleared (receiver holding reg- ister has been read). value name description 0 normal normal mode 1 automatic automatic echo. receiver input is connected to the txd pin. 2 local_loopback local loopback. transmitter outp ut is connected to the receiver input. 3 remote_loopback remote loopback. rxd pin is internally connected to the txd pin.
842 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 842 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8.5 usart interrupt enable register name: us_ier address: 0xf801c008 (0), 0xf8020008 (1), 0xf8024008 (2), 0xf8028008 (3) access: write-only for spi specific configuration, see usart interrupt enable register (spi_mode) on page 843 . for lin specific configuration, see usart interrupt enable register (lin_mode) on page 844 . ? rxrdy: rxrdy interrupt enable ? txrdy: txrdy interrupt enable ? rxbrk: receiver break interrupt enable ? ovre: overrun error interrupt enable ? frame: framing error interrupt enable ? pare: parity error interrupt enable ? timeout: time-out interrupt enable ? txempty: txempty interrupt enable ? iter: max number of repetitions reached interrupt enable ? nack: non acknowledge interrupt enable ? ctsic: clear to send input change interrupt enable ? mane: manchester error interrupt enable 0: no effect 1: enables the corresponding interrupt. 31 30 29 28 27 26 25 24 CCCCCCCm a n e 23 22 21 20 19 18 17 16 CCCCc t s i cC C C 15 14 13 12 11 10 9 8 C C nack C C iter txempty timeout 76543210 pare frame ovre C C rxbrk txrdy rxrdy
843 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 843 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8.6 usart interrupt enable register (spi_mode) name: us_ier (spi_mode) address: 0xf801c008 (0), 0xf8020008 (1), 0xf8024008 (2), 0xf8028008 (3) access: write-only this configuration is relevant only if usart_mode=0xe or 0xf in usart mode register on page 836 . ? rxrdy: rxrdy interrupt enable ? txrdy: txrdy interrupt enable ? ovre: overrun error interrupt enable ? txempty: txempty interrupt enable ? unre: spi underrun error interrupt enable 0: no effect 1: enables the corresponding interrupt. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCu n r et x e m p t yC 76543210 CCo v r eCCCt x r d yr x r d y
844 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 844 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8.7 usart interrupt enable register (lin_mode) name: us_ier (lin_mode) address: 0xf801c008 (0), 0xf8020008 (1), 0xf8024008 (2), 0xf8028008 (3) access: write-only this configuration is relevant only if usart_mode=0xa or 0xb in usart mode register on page 836 . ? rxrdy: rxrdy interrupt enable ? txrdy: txrdy interrupt enable ? ovre: overrun error interrupt enable ? frame: framing error interrupt enable ? pare: parity error interrupt enable ? timeout: time-out interrupt enable ? txempty: txempty interrupt enable ? linbk: lin break sent or lin break received interrupt enable ? linid: lin identifier sent or lin identifier received interrupt enable ? lintc: lin transfer completed interrupt enable ? linbe: lin bus error interrupt enable ? linisfe: lin inconsistent synch field error interrupt enable ? linipe: lin identifier parity interrupt enable ? lince: lin checksum error interrupt enable ? linsnre: lin slave not responding error interrupt enable 0: no effect 1: enables the corresponding interrupt. 31 30 29 28 27 26 25 24 C C linsnre lince linipe linisfe linbe C 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 lintc linid linbk C C C txempty timeout 76543210 pare frame ovre C C C txrdy rxrdy
845 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 845 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8.8 usart interrupt disable register name: us_idr address: 0xf801c00c (0), 0xf802000c (1), 0xf802400c (2), 0xf802800c (3) access: write-only for spi specific configuration, see usart interrupt disable register (spi_mode) on page 846 . for lin specific configuration, see usart interrupt disable register (lin_mode) on page 847 . ? rxrdy: rxrdy interrupt disable ? txrdy: txrdy interrupt disable ? rxbrk: receiver bre ak interrupt disable ? ovre: overrun error interrupt enable ? frame: framing error interrupt disable ? pare: parity error interrupt disable ? timeout: time-out interrupt disable ? txempty: txempty interrupt disable ? iter: max number of repetitions reached interrupt disable ? nack: non acknowledge interrupt disable ? ctsic: clear to send input change interrupt disable ? mane: manchester error interrupt disable 0: no effect 1: disables the corresponding interrupt. 31 30 29 28 27 26 25 24 CCCCCCCm a n e 23 22 21 20 19 18 17 16 CCCCc t s i cC C C 15 14 13 12 11 10 9 8 C C nack C C iter txempty timeout 76543210 pare frame ovre C C rxbrk txrdy rxrdy
846 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 846 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8.9 usart interrupt disable register (spi_mode) name: us_idr (spi_mode) address: 0xf801c00c (0), 0xf802000c (1), 0xf802400c (2), 0xf802800c (3) access: write-only this configuration is relevant only if usart_mode=0xe or 0xf in usart mode register on page 836 . ? rxrdy: rxrdy interrupt disable ? txrdy: txrdy interrupt disable ? ovre: overrun error interrupt disable ? txempty: txempty interrupt disable ? unre: spi underrun error interrupt disable 0: no effect 1: disables the corresponding interrupt. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCu n r et x e m p t yC 76543210 CCo v r eCCCt x r d yr x r d y
847 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 847 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8.10 usart interrupt disable register (lin_mode) name: us_idr (lin_mode) address: 0xf801c00c (0), 0xf802000c (1), 0xf802400c (2), 0xf802800c (3) access: write-only this configuration is relevant only if usart_mode=0xa or 0xb in usart mode register on page 836 . ? rxrdy: rxrdy interrupt disable ? txrdy: txrdy interrupt disable ? ovre: overrun error interrupt disable ? frame: framing error interrupt disable ? pare: parity error interrupt disable ? timeout: time-out interrupt disable ? txempty: txempty interrupt disable ? linbk: lin break sent or lin br eak received interrupt disable ? linid: lin identifier sent or lin identifier received interrupt disable ? lintc: lin transfer completed interrupt disable ? linbe: lin bus error interrupt disable ? linisfe: lin inconsistent synch field error interrupt disable ? linipe: lin identifier parity interrupt disable ? lince: lin checksum error interrupt disable ? linsnre: lin slave not responding error interrupt disable 0: no effect 1: disables the corresponding interrupt. 31 30 29 28 27 26 25 24 C C linsnre lince linipe linisfe linbe C 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 lintc linid linbk C C C txempty timeout 76543210 pare frame ovre C C C txrdy rxrdy
848 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 848 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8.11 usart interrupt mask register name: us_imr address: 0xf801c010 (0), 0xf8020010 (1), 0xf8024010 (2), 0xf8028010 (3) access: read-only for spi specific configuration, see usart interrupt mask register (spi_mode) on page 849 . for lin specific configuration, see usart interrupt mask register (lin_mode) on page 850 . ? rxrdy: rxrdy interrupt mask ? txrdy: txrdy interrupt mask ? rxbrk: receiver break interrupt mask ? ovre: overrun error interrupt mask ? frame: framing error interrupt mask ? pare: parity error interrupt mask ? timeout: time-out interrupt mask ? txempty: txempty interrupt mask ? iter: max number of repetitions reached interrupt mask ? nack: non acknowledge interrupt mask ? ctsic: clear to send input change interrupt mask ? mane: manchester error interrupt mask 0: the corresponding interrupt is not enabled. 1: the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 CCCCCCCm a n e 23 22 21 20 19 18 17 16 CCCCc t s i cC C C 15 14 13 12 11 10 9 8 C C nack C C iter txempty timeout 76543210 pare frame ovre C C rxbrk txrdy rxrdy
849 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 849 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8.12 usart interrupt mask register (spi_mode) name: us_imr (spi_mode) address: 0xf801c010 (0), 0xf8020010 (1), 0xf8024010 (2), 0xf8028010 (3) access: read-only this configuration is relevant only if usart_mode=0xe or 0xf in usart mode register on page 836 . ? rxrdy: rxrdy interrupt mask ? txrdy: txrdy interrupt mask ? ovre: overrun error interrupt mask ? txempty: txempty interrupt mask ? unre: spi underrun error interrupt mask 0: the corresponding interrupt is not enabled. 1: the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCu n r et x e m p t yC 76543210 CCo v r eCCCt x r d yr x r d y
850 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 850 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8.13 usart interrupt mask register (lin_mode) name: us_imr (lin_mode) address: 0xf801c010 (0), 0xf8020010 (1), 0xf8024010 (2), 0xf8028010 (3) access: read-only this configuration is relevant only if usart_mode=0xa or 0xb in usart mode register on page 836 . ? rxrdy: rxrdy interrupt mask ? txrdy: txrdy interrupt mask ? ovre: overrun error interrupt mask ? frame: framing error interrupt mask ? pare: parity error interrupt mask ? timeout: time-out interrupt mask ? txempty: txempty interrupt mask ? linbk: lin break sent or lin break received interrupt mask ? linid: lin identifier sent or lin identifier received interrupt mask ? lintc: lin transfer completed interrupt mask ? linbe: lin bus error interrupt mask ? linisfe: lin inconsistent synch field error interrupt mask ? linipe: lin identifier parity interrupt mask ? lince: lin checksum error interrupt mask ? linsnre: lin slave not responding error interrupt mask 0: the corresponding interrupt is not enabled. 1: the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 C C linsnre lince linipe linisfe linbe C 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 lintc linid linbk C C C txempty timeout 76543210 pare frame ovre C C C txrdy rxrdy
851 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 851 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8.14 usart channel status register name: us_csr address: 0xf801c014 (0), 0xf8020014 (1), 0xf8024014 (2), 0xf8028014 (3) access: read-only for spi specific configuration, see usart channel status register (spi_mode) on page 853 . for lin specific configuration, see usart channel status register (lin_mode) on page 854 . ? rxrdy: receiver ready 0: no complete character has been received since the last read of us_rhr or the receiver is disabled. if characters were being received when the receiver was disabled, rx rdy changes to 1 when the receiver is enabled. 1: at least one complete char acter has been rece ived and us_rhr has not yet been read. ? txrdy: transmitter ready 0: a character is in the us_thr waiting to be transferred to the transmit shift register, or an sttbrk command has been requested, or the transmitter is disabled. as soon as the transmitter is enabled, txrdy becomes 1. 1: there is no char acter in the us_thr. ? rxbrk: break received/end of break 0: no break received or end of break detected since the last rststa. 1: break received or end of break detected since the last rststa. ? ovre: overrun error 0: no overrun error has occurred since the last rststa. 1: at least one overrun error has occurred since the last rststa. ? frame: framing error 0: no stop bit has been detected low since the last rststa. 1: at least one stop bit has been detected low since the last rststa. ? pare: parity error 0: no parity error has been detected since the last rststa. 1: at least one parity error has been detected since the last rststa. 31 30 29 28 27 26 25 24 CCCCCCCm a n e r r 23 22 21 20 19 18 17 16 cts C C C ctsic C C C 15 14 13 12 11 10 9 8 C C nack C C iter txempty timeout 76543210 pare frame ovre C C rxbrk txrdy rxrdy
852 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 852 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? timeout: receiver time-out 0: there has not been a time-out since t he last start time-out command (sttto in us_cr) or the time-out register is 0. 1: there has been a time-out since the last start time-out command (sttto in us_cr). ? txempty: transmitter empty 0: there are characters in either us_thr or the tr ansmit shift register, or the transmitter is disabled. 1: there are no characters in us_thr, nor in the transmit shift register. ? iter: max number of repetitions reached 0: maximum number of repetitions has not been reached since the last rststa. 1: maximum number of repetitions has been reached since the last rststa. ? nack: non acknowledge interrupt 0: non acknowledge has not been detected since the last rstnack. 1: at least one non acknowledge has been detected since the last rstnack. ? ctsic: clear to send input change flag 0: no input change has been detected on the cts pin since the last read of us_csr. 1: at least one input change has been detected on the cts pin since the last read of us_csr. ? cts: image of cts input 0: cts is set to 0. 1: cts is set to 1. ? manerr: manchester error 0: no manchester error has been detected since the last rststa. 1: at least one manchester error has been detected since the last rststa.
853 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 853 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8.15 usart channel status register (spi_mode) name: us_csr (spi_mode) address: 0xf801c014 (0), 0xf8020014 (1), 0xf8024014 (2), 0xf8028014 (3) access: read-only this configuration is relevant only if usart_mode=0xe or 0xf in usart mode register on page 836 . ? rxrdy: receiver ready 0: no complete character has been received since the last read of us_rhr or the receiver is disabled. if characters were being received when the receiver was disabled, rx rdy changes to 1 when the receiver is enabled. 1: at least one complete char acter has been rece ived and us_rhr has not yet been read. ? txrdy: transmitter ready 0: a character is in the us_thr waiting to be transferred to the transmit shift register or the transmitter is disabled. as soon as the transmitter is enabled, txrdy becomes 1. 1: there is no char acter in the us_thr. ? ovre: overrun error 0: no overrun error has occurred since the last rststa. 1: at least one overrun error has occurred since the last rststa. ? txempty: transmitter empty 0: there are characters in either us_thr or the tr ansmit shift register, or the transmitter is disabled. 1: there are no characters in us_thr, nor in the transmit shift register. ? unre: underrun error 0: no spi underrun error has occurred since the last rststa. 1: at least one spi underrun error has occurred since the last rststa. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCu n r et x e m p t yC 76543210 CCo v r eCCCt x r d yr x r d y
854 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 854 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8.16 usart channel status register (lin_mode) name: us_csr (lin_mode) address: 0xf801c014 (0), 0xf8020014 (1), 0xf8024014 (2), 0xf8028014 (3) access: read-only this configuration is relevant only if usart_mode=0xa or 0xb in usart mode register on page 836 . ? rxrdy: receiver ready 0: no complete character has been received since the last read of us_rhr or the receiver is disabled. if characters were being received when the receiver was disabled, rx rdy changes to 1 when the receiver is enabled. 1: at least one complete char acter has been rece ived and us_rhr has not yet been read. ? txrdy: transmitter ready 0: a character is in the us_thr waiting to be transferred to the transmit shift register or the transmitter is disabled. as soon as the transmitter is enabled, txrdy becomes 1. 1: there is no char acter in the us_thr. ? ovre: overrun error 0: no overrun error has occurred since the last rststa. 1: at least one overrun error has occurred since the last rststa. ? frame: framing error 0: no stop bit has been detected low since the last rststa. 1: at least one stop bit has been detected low since the last rststa. ? pare: parity error 0: no parity error has been detected since the last rststa. 1: at least one parity error has been detected since the last rststa. ? timeout: receiver time-out 0: there has not been a time-out since t he last start time-out command (sttto in us_cr) or the time-out register is 0. 1: there has been a time-out since the last start time-out command (sttto in us_cr). 31 30 29 28 27 26 25 24 C C linsnre lince linipe linisfe linbe C 23 22 21 20 19 18 17 16 l i n b l sCCCCCCC 15 14 13 12 11 10 9 8 lintc linid linbk C C C txempty timeout 76543210 pare frame ovre C C C txrdy rxrdy
855 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 855 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? txempty: transmitter empty 0: there are characters in either us_thr or the tr ansmit shift register, or the transmitter is disabled. 1: there are no characters in us_thr, nor in the transmit shift register. ? linbk: lin break sent or lin break received C applicable if usart operates in lin master mode (usart_mode = 0xa): 0: no lin break has been sent since the last rststa. 1:at least one lin break has been sent since the last rststa C if usart operates in lin slave mode (usart_mode = 0xb): 0: no lin break has received sent since the last rststa. 1:at least one lin break has been received since the last rststa. ? linid: lin identifier sent or lin identifier received C if usart operates in lin master mode (usart_mode = 0xa): 0: no lin identifier has been sent since the last rststa. 1:at least one lin identifier has been sent since the last rststa. C if usart operates in lin slave mode (usart_mode = 0xb): 0: no lin identifier has been received since the last rststa. 1:at least one lin identifier has been received since the last rststa ? lintc: lin transfer completed 0: the usart is idle or a lin transfer is ongoing. 1: a lin transfer has been completed since the last rststa. ? linbls: lin bus line status 0: lin bus line is set to 0. 1: lin bus line is set to 1. ? linbe: lin bit error 0: no bit error has been detected since the last rststa. 1: a bit error has been detected since the last rststa. ? linisfe: lin inconsistent synch field error 0: no lin inconsistent synch field erro r has been detected since the last rststa 1: the usart is configured as a slave node and a lin in consistent synch field error has been detected since the last rststa. ? linipe: lin identifier parity error 0: no lin identifier parity error has been detected since the last rststa. 1: a lin identifier parity error has been detected since the last rststa.
856 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 856 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? lince: lin checksum error 0: no lin checksum error has been detected since the last rststa. 1: a lin checksum error has been de tected since the last rststa. ? linsnre: lin slave not responding error 0: no lin slave not responding error ha s been detected since the last rststa. 1: a lin slave not responding error has been detected since the last rststa.
857 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 857 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8.17 usart receive holding register name: us_rhr address: 0xf801c018 (0), 0xf8020018 (1), 0xf8024018 (2), 0xf8028018 (3) access: read-only ? rxchr: received character last character received if rxrdy is set. ? rxsynh: received sync 0: last character received is a data. 1: last character received is a command. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 rxsynh CCCCCCr x c h r 76543210 rxchr
858 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 858 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8.18 usart transmit holding register name: us_thr address: 0xf801c01c (0), 0xf802001c (1), 0xf802401c (2), 0xf802801c (3) access: write-only ? txchr: character to be transmitted next character to be transmitted after the current character if txrdy is not set. ? txsynh: sync field to be transmitted 0: the next character sent is encoded as a data. start frame delimiter is data sync. 1: the next character sent is encoded as a command. start frame delimiter is command sync. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 txsynh CCCCCCt x c h r 76543210 txchr
859 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 859 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8.19 usart baud rate generator register name: us_brgr address: 0xf801c020 (0), 0xf8020020 (1), 0xf8024020 (2), 0xf8028020 (3) access: read-write this register can only be written if the wpen bit is cleared in usart write protect mode register on page 870 . ? cd: clock divider ? fp: fractional part 0: fractional divider is disabled. 1 - 7: baudrate resolution, defined by fp x 1/8. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCC f p 15 14 13 12 11 10 9 8 cd 76543210 cd cd usart_mode iso7816 usart_mode = iso7816 sync = 0 sync = 1 or usart_mode = spi (master or slave) over = 0 over = 1 0 baud rate clock disabled 1 to 65535 baud rate = selected clock/(16*cd) baud rate = selected clock/(8*cd) baud rate = selected clock /cd baud rate = selected clock/(fi_di_ratio*cd)
860 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 860 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8.20 usart receiver time-out register name: us_rtor address: 0xf801c024 (0), 0xf8020024 (1), 0xf8024024 (2), 0xf8028024 (3) access: read-write this register can only be written if the wpen bit is cleared in usart write protect mode register on page 870 . ? to: time-out value 0: the receiver time-out is disabled. 1 - 131071: the receiver time-out is enabled and the time-out delay is to x bit period. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCt o 15 14 13 12 11 10 9 8 to 76543210 to
861 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 861 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8.21 usart transmitter timeguard register name: us_ttgr address: 0xf801c028 (0), 0xf8020028 (1), 0xf8024028 (2), 0xf8028028 (3) access: read-write this register can only be written if the wpen bit is cleared in usart write protect mode register on page 870 . ? tg: timeguard value 0: the transmitter timeguard is disabled. 1 - 255: the transmitter timeguard is enabled and the timeguard delay is tg x bit period. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 tg
862 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 862 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8.22 usart fi di ratio register name: us_fidi address: 0xf801c040 (0), 0xf8020040 (1), 0xf8024040 (2), 0xf8028040 (3) access: read-write reset value: 0x174 this register can only be written if the wpen bit is cleared in usart write protect mode register on page 870 . ? fi_di_ratio: fi over di ratio value 0: if iso7816 mode is selected, the baud rate generator generates no signal. 1 - 2047: if iso7816 mode is selected, the baud rate is the clock provided on sck divided by fi_di_ratio. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCC f i _ d i _ r a t i o 76543210 fi_di_ratio
863 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 863 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8.23 usart number of errors register name: us_ner address: 0xf801c044 (0), 0xf8020044 (1), 0xf8024044 (2), 0xf8028044 (3) access: read-only this register is relevant only if usart_mode=0x4 or 0x6 in usart mode register on page 836 . ? nb_errors: number of errors total number of errors that occurred during an iso7816 transfer. this register automatically clears when read. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 nb_errors
864 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 864 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8.24 usart irda filter register name: us_if address: 0xf801c04c (0), 0xf802004c (1), 0xf802404c (2), 0xf802804c (3) access: read-write this register is relevant only if usart_mode=0x8 in usart mode register on page 836 . this register can only be written if the wpen bit is cleared in usart write protect mode register on page 870 . ? irda_filter: irda filter sets the filter of the irda demodulator. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 irda_filter
865 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 865 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8.25 usart manchester configuration register name: us_man address: 0xf801c050 (0), 0xf8020050 (1), 0xf8024050 (2), 0xf8028050 (3) access: read-write this register can only be written if the wpen bit is cleared in usart write protect mode register on page 870 . ? tx_pl: transmitter preamble length 0: the transmitter preamble pattern generation is disabled 1 - 15: the preamble length is tx_pl x bit period ? tx_pp: transmitter preamble pattern the following values assume that tx_mpol field is not set: ? tx_mpol: transmitter manchester polarity 0: logic zero is coded as a zero-to-one transition , logic one is coded as a one-to-zero transition. 1: logic zero is coded as a one-to-zero transition , logic one is coded as a zero-to-one transition. ? rx_pl: receiver preamble length 0: the receiver preamble pattern detection is disabled 1 - 15: the detected preamble length is rx_pl x bit period 31 30 29 28 27 26 25 24 C drift one rx_mpol C C rx_pp 23 22 21 20 19 18 17 16 CCCC r x _ p l 15 14 13 12 11 10 9 8 C C C tx_mpol C C tx_pp 76543210 CCCC tx_pl value name description 00 all_one the preamble is composed of 1s 01 all_zero the preamble is composed of 0s 10 zero_one the preamble is composed of 01s 11 one_zero the preamble is composed of 10s
866 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 866 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? rx_pp: receiver preamble pattern detected the following values assume that rx_mpol field is not set: ? rx_mpol: receiver manchester polarity 0: logic zero is coded as a zero-to-one transition , logic one is coded as a one-to-zero transition. 1: logic zero is coded as a one-to-zero transition , logic one is coded as a zero-to-one transition. ? one: must be set to 1 bit 29 must always be set to 1 when programming the us_man register. ? drift: drift compensation 0: the usart can not recover from an important clock drift 1: the usart can recover from clock drift. the 16x clock mode must be enabled. value name description 00 all_one the preamble is composed of 1s 01 all_zero the preamble is composed of 0s 10 zero_one the preamble is composed of 01s 11 one_zero the preamble is composed of 10s
867 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 867 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8.26 usart lin mode register name: us_linmr address: 0xf801c054 (0), 0xf8020054 (1), 0xf8024054 (2), 0xf8028054 (3) access: read-write this register is relevant only if usart_mode=0xa or 0xb in usart mode register on page 836 . this register can only be written if the wpen bit is cleared in usart write protect mode register on page 870 . ? nact: lin node action values which are not listed in the table must be considered as reserved. ? pardis: parity disable 0: in master node configuration, the identifier parity is computed and sent automatically. in master node and slave node configuration, the parity is checked automatically. 1:whatever the node configuration is, the identifier parity is not computed/sent and it is not checked. ? chkdis: checksum disable 0: in master node configuration, the checksum is computed and sent automatically. in slave node configuration, the check- sum is checked automatically. 1: whatever the node configuration is, the checksum is not computed/sent and it is not checked. ? chktyp: checksum type 0: lin 2.0 enhanced checksum 1: lin 1.3 classic checksum ? dlm: data length mode 0: the response data length is defined by the field dlc of this register. 1: the response data length is defined by the bits 5 and 6 of the identifier (idchr in us_linir). 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCp d c m 15 14 13 12 11 10 9 8 dlc 76543210 wkuptyp fsdis dlm chktyp chkdis pardis nact value name description 00 publish the usart transmits the response. 01 subscribe the usart receives the response. 10 ignore the usart does not transmit and does not receive the response.
868 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 868 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? fsdis: frame slot mode disable 0: the frame slot mode is enabled. 1: the frame slot mode is disabled. ? wkuptyp: wakeup signal type 0: setting the bit linwkup in the control register sends a lin 2.0 wakeup signal. 1: setting the bit linwkup in the control register sends a lin 1.3 wakeup signal. ? dlc: data length control 0 - 255: defines the response data length if dlm=0,in that case the response data length is equal to dlc+1 bytes. ? pdcm: dmac mode 0: the lin mode register us_linmr is not written by the dmac. 1: the lin mode register us_linmr (excepting that flag) is written by the dmac.
869 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 869 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8.27 usart lin identifier register name: us_linir address: 0xf801c058 (0), 0xf8020058 (1), 0xf8024058 (2), 0xf8028058 (3) access: read-write or read-only this register is relevant only if usart_mode=0xa or 0xb in usart mode register on page 836 . ? idchr: identifier character if usart_mode=0xa (master node configuration): idchr is read-write and its value is the identifier character to be transmitted. if usart_mode=0xb (slave node configuration): idchr is read-only and its value is the last identifier character that has been received. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 idchr
870 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 870 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8.28 usart write protect mode register name: us_wpmr address: 0xf801c0e4 (0), 0xf80200e4 (1), 0xf80240e4 (2), 0xf80280e4 (3) access: read-write reset: see table 40-16 ? wpen: write protect enable 0 = disables the write protect if wpkey corresponds to 0x5553 41 (usa in ascii). 1 = enables the write protect if wpkey corresponds to 0x555341 (usa in ascii). protects the registers: ? usart mode register on page 836 ? usart baud rate generator register on page 859 ? usart receiver time-out register on page 860 ? usart transmitter timeguard register on page 861 ? usart fi di ratio register on page 862 ? usart irda filter register on page 864 ? usart manchester configuration register on page 865 ? wpkey: write protect key should be written at value 0x555341 (usa in ascii). writing any other value in this field aborts the write operation of the wpen bit. always reads as 0. 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 w p e n
871 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 871 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 40.8.29 usart write protect status register name: us_wpsr address: 0xf801c0e8 (0), 0xf80200e8 (1), 0xf80240e8 (2), 0xf80280e8 (3) access: read-only reset: see table 40-16 ? wpvs: write protect violation status 0 = no write protect violation has occurred since the last read of the us_wpsr register. 1 = a write protect violation has occurred since the last read of the us_wpsr register. if this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field wpvsrc. ? wpvsrc: write protect violation source when wpvs is active, this field indicates the write-protected register (t hrough address offset or code) in which a write access has been attempted. note: reading us_wpsr automatically clears all fields. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 wpvsrc 15 14 13 12 11 10 9 8 wpvsrc 76543210 w p v s
872 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 872 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12
873 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 873 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 41. universal asynchronous receiver transceiver (uart) 41.1 description the universal asynchronous receiver transmitter features a two-pin uart that can be used for communication and trace purposes and offers an ideal medium for in-situ programming solu- tions. moreover, the association with two dma controller channels permits packet handling for these tasks with processor time reduced to a minimum. 41.2 embedded characteristics ?two-pin uart C implemented features are usart compatible C independent receiver and transmitter with a common programmable baud rate generator C even, odd, mark or space parity generation C parity, framing and overrun error detection C automatic echo, local loopback and remote loopback channel modes C interrupt generation C support for two dma channels with connection to receiver and transmitter
874 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 874 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 41.3 block diagram figure 41-1. uart functional block diagram 41.4 product dependencies 41.4.1 i/o lines the uart pins are multiplexed with pio lines. the programmer must first configure the corre- sponding pio controller to enable i/o line operations of the uart. 41.4.2 power management the uart clock is controllable through the power management controller. in this case, the pro- grammer must first configure the pmc to enable the uart clock. usually, the peripheral identifier used for this purpose is 1. 41.4.3 interrupt source the uart interrupt line is connected to one of the interrupt sources of the nested vectored interrupt controller (nvic). interrupt handling requires programming of the nvic before config- uring the uart. dma controller baud rate gener ator tr ansmit receive interr upt control peripher al bridge p ar allel input/ output utxd urxd power management controller mck ua rt_irq apb uart table 41-1. uart pin description pin name description type urxd uart receive data input utxd uart transmit data output
875 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 875 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 41.5 uart operations the uart operates in asynchronous mode only and supports only 8-bit character handling (with parity). it has no clock pin. the uart is made up of a receiver and a transmitter that operate independently, and a common baud rate generator. receiver timeout and transmitter time guard are not implemented. how- ever, all the implemented features are compatible with those of a standard usart. 41.5.1 baud rate generator the baud rate generator provides the bit period clock named baud rate clock to both the receiver and the transmitter. the baud rate clock is the master clock divided by 16 times the value (cd) written in uart_brgr (baud rate generator register). if ua rt_brgr is set to 0, the baud rate clock is disabled and the uart remains inactive. the maximum allowable baud rate is master clock divided by 16. the minimum allowable baud rate is master clock divided by (16 x 65536). figure 41-2. baud rate generator 41.5.2 receiver 41.5.2.1 receiver rese t, enable and disable after device reset, the uart receiver is disabled and must be enabled before being used. the receiver can be enabled by writing the control re gister uart_cr with the bit rxen at 1. at this command, the receiver starts looking for a start bit. the programmer can disable the receiver by writing uart_cr with the bit rxdis at 1. if the receiver is waiting for a start bit, it is immedi ately stopped. however, if the receiver has already detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its operation. the programmer can also put the receiver in it s reset state by writing uart_cr with the bit rstrx at 1. in doing so, the receiver immediat ely stops its current operations and is disabled, whatever its current state. if rstrx is applied wh en data is being processed, this data is lost. 41.5.2.2 start detection and data sampling the uart only supports asynchronous operations, and this affects only its receiver. the uart receiver detects the start of a received character by sampling th e urxd signal until it detects a baud rate mck 16 cd ----------------------- - = mck 16-bit counter 0 baud rate clock cd cd out divide by 16 0 1 >1 receiver sampling clock
876 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 876 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 valid start bit. a low level (space) on urxd is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. a space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. when a valid start bit has been detected, the receiver samples the urxd at the theoretical mid- point of each bit. it is assumed that each bit last s 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. the first sampling point is therefore 24 cycles (1.5 -bit periods) after t he falling edge of the st art bit was detected. each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. figure 41-3. start bit detection figure 41-4. character reception 41.5.2.3 receiver ready when a complete character is re ceived, it is transferred to the uart_rhr and the rxrdy sta- tus bit in uart_sr (status register) is set. the bit rxrdy is automatically cleared when the receive holding regist er uart_rhr is read. figure 41-5. receiver ready sampling clock urxd true start detection d0 baud rate clock d0 d1 d2 d3 d4 d5 d6 d7 urxd true start detection sampling parity bit stop bit example: 8-bit, parity enabled 1 stop 1 bit period 0.5 bit period d0 d1 d2 d3 d4 d5 d6 d7 p s s d0 d1 d2 d3 d4 d5 d6 d7 p urxd read uart_rhr rxrdy
877 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 877 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 41.5.2.4 receiver overrun if uart_rhr has not been read by the software (or the peripheral data controller or dma controller) since the last transf er, the rxrdy bit is still set and a new character is received, the ovre status bit in uart_sr is set. ovre is cl eared when the software writes the control regis- ter uart_cr with the bit rststa (reset status) at 1. figure 41-6. receiver overrun 41.5.2.5 parity error each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field par in uart_mr. it then compares the result with the received parity bit. if different, the parity error bit pare in uart_sr is set at the same time the rxrdy is set. the parity bit is cleared when the control regist er uart_cr is written with the bit rststa (reset status) at 1. if a new character is received before the reset status command is written, the pare bit remains at 1. figure 41-7. parity error 41.5.2.6 receiver framing error when a start bit is detected, it generates a character reception when all the data bits have been sampled. the stop bit is also sampled and when it is detected at 0, the frame (framing error) bit in uart_sr is set at the same time the rx rdy bit is set. the frame bit remains high until the control register uart_cr is wr itten with the bit rststa at 1. figure 41-8. receiver framing error d0 d1 d2 d3 d4 d5 d6 d7 p s s d0 d1 d2 d3 d4 d5 d6 d7 p urxd rststa rxrdy ovre stop stop stop d0 d1 d2 d3 d4 d5 d6 d7 p s urxd rststa rxrdy pare wrong parity bit d0 d1 d2 d3 d4 d5 d6 d7 p s urxd rststa rxrdy frame stop bit detected at 0 stop
878 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 878 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 41.5.3 transmitter 41.5.3.1 transmitter reset, enable and disable after device reset, the uart transmitter is disabled and it must be enabled before being used. the transmitter is enabled by writing the control register uart_cr with the bit txen at 1. from this command, the transmitter waits for a character to be written in the transmit holding register (uart_thr) before actually starting the transmission. the programmer can disable the transmitter by writing uart_cr with the bit txdis at 1. if the transmitter is not operating, it is immediately stopped. however, if a character is being pro- cessed into the shift register and/or a character has been written in the transmit holding register, the characters are completed before the transmitter is actually stopped. the programmer can also put the transmitter in its reset state by writing the uart_cr with the bit rsttx at 1. this immediately stops the transmitter, whether or not it is processing characters. 41.5.3.2 transmit format the uart transmitter drives the pin utxd at the baud rate clock speed. the line is driven depending on the format defined in the mode register and the data stored in the shift register. one start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown in the following figure. the field pare in the mode register uart_mr defines whether or not a parity bit is shifted out. when a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit. figure 41-9. character transmission 41.5.3.3 transmitter control when the transmitter is enabled, the bit txrdy (transmitter ready) is set in the status register uart_sr. the transmission starts when the prog rammer writes in the tr ansmit holding regis- ter (uart_thr), and after the written character is transferred from uart_thr to the shift register. the txrdy bit remains high until a se cond character is written in uart_thr. as soon as the first character is completed, the last character written in uart_thr is transferred into the shift register and txrdy rises again, showing that the holding register is empty. when both the shift register and uart_thr are empty, i.e., all the characters written in uart_thr have been processed, the txempty bit rises after the last stop bit has been completed. d0 d1 d2 d3 d4 d5 d6 d7 utxd start bit parity bit stop bit example: parity enabled baud rate clock
879 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 879 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 41-10. transmitter control 41.5.4 dma support both the receiver and the transmitter of the uart are connected to a dma controller (dmac) channel. the dma controller channels are programmed via registers that are mapped within the dmac user interface. 41.5.5 test modes the uart supports three test modes. these modes of operation are programmed by using the field chmode (channel mode) in the mode register (uart_mr). the automatic echo mode allows bit-by-bit retr ansmission. when a bit is received on the urxd line, it is sent to the utxd line. the transm itter operates normally, but has no effect on the utxd line. the local loopback mode allows the transmitted characters to be received. utxd and urxd pins are not used and the output of the transmitter is internally connected to the input of the receiver. the urxd pin level has no effect and th e utxd line is held high , as in idle state. the remote loopback mode directly connects the urxd pin to the utxd line. the transmitter and the receiver are disabled and have no effec t. this mode allows a bit-by-bit retransmission. uart_thr shift register utxd txrdy txempty data 0 data 1 data 0 data 0 data 1 data 1 s s p p write data 0 in uart_thr write data 1 in uart_thr stop stop
880 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 880 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 41-11. test modes receiver transmitter disabled rxd txd receiver transmitter disabled rxd txd v dd disabled receiver transmitter disabled rxd txd disabled automatic echo local loopback remote loopback v dd
881 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 881 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 41.6 universal asynchronous r eceiver transmitter (uar t) user interface table 41-2. register mapping offset register name access reset 0x0000 control register uart_cr write-only C 0x0004 mode register uart_mr read-write 0x0 0x0008 interrupt enable register uart_ier write-only C 0x000c interrupt disable register uart_idr write-only C 0x0010 interrupt mask register uart_imr read-only 0x0 0x0014 status register uart_sr read-only C 0x0018 receive holding register uart_rhr read-only 0x0 0x001c transmit holding register uart_thr write-only C 0x0020 baud rate generator register uart_brgr read-write 0x0 0x0024 - 0x003c reserved C C C 0x004c - 0x00fc reserved C C C
882 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 882 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 41.6.1 uart control register name: uart_cr address: 0xf8040000 (0), 0xf8044000 (1) access: write-only ? rstrx: reset receiver 0 = no effect. 1 = the receiver logic is reset and disabled. if a ch aracter is being received, the reception is aborted. ? rsttx: reset transmitter 0 = no effect. 1 = the transmitter logic is reset and disabled. if a character is being transmitted, the transmission is aborted. ? rxen: receiver enable 0 = no effect. 1 = the receiver is enabled if rxdis is 0. ? rxdis: receiver disable 0 = no effect. 1 = the receiver is disabled. if a character is being processe d and rstrx is not set, the character is completed before the receiver is stopped. ? txen: transmitter enable 0 = no effect. 1 = the transmitter is ena bled if txdis is 0. ? txdis: transmitter disable 0 = no effect. 1 = the transmitter is disabled. if a character is being processed and a character has been written in the uart_thr and rsttx is not set, both characters are completed before the transmitter is stopped. ? rststa: reset status bits 0 = no effect. 1 = resets the status bits pare, frame and ovre in the uart_sr. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCC rststa 76543210 txdis txen rxdis rxen rsttx rstrx CC
883 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 883 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 41.6.2 uart mode register name: uart_mr address: 0xf8040004 (0), 0xf8044004 (1) access: read-write ? par: parity type ? chmode: channel mode 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 chmode CC pa r C 76543210 CCCCCCCC value name description 0 even even parity 1 odd odd parity 2 space space: parity forced to 0 3 mark mark: parity forced to 1 4 no no parity value name description 0 normal normal mode 1 automatic automatic echo 2 local_loopback local loopback 3 remote_loopback remote loopback
884 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 884 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 41.6.3 uart interrupt enable register name: uart_ier address: 0xf8040008 (0), 0xf8044008 (1) access: write-only ? rxrdy: enable rxrdy interrupt ? txrdy: enable txrdy interrupt ? ovre: enable overrun error interrupt ? frame: enable framing error interrupt ? pare: enable parity error interrupt ? txempty: enable txempty interrupt 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCC CC C txempty C 76543210 pare frame ovre CC C txrdy rxrdy
885 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 885 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 41.6.4 uart interrupt disable register name: uart_idr address: 0xf804000c (0), 0xf804400c (1) access: write-only ? rxrdy: disable rxrdy interrupt ? txrdy: disable txrdy interrupt ? ovre: disable overrun error interrupt ? frame: disable framing error interrupt ? pare: disable parity error interrupt ? txempty: disable txempty interrupt 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCC CC C txempty C 76543210 pare frame ovre CC C txrdy rxrdy
886 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 886 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 41.6.5 uart interrupt mask register name: uart_imr address: 0xf8040010 (0), 0xf8044010 (1) access: read-only ? rxrdy: mask rxrdy interrupt ? txrdy: disable txrdy interrupt ? ovre: mask overrun error interrupt ? frame: mask framing error interrupt ? pare: mask parity error interrupt ? txempty: mask txempty interrupt 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCC CC C txempty C 76543210 pare frame ovre CC C txrdy rxrdy
887 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 887 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 41.6.6 uart status register name: uart_sr address: 0xf8040014 (0), 0xf8044014 (1) access: read-only ? rxrdy: receiver ready 0 = no character has been received since the last re ad of the uart_rhr or the receiver is disabled. 1 = at least one complete character has been received, transferred to uart_rhr and not yet read. ? txrdy: transmitter ready 0 = a character has been written to uart_thr and not yet transferred to the shift register, or the transmitter is disabled. 1 = there is no character written to uart_thr not yet transferred to the shift register. ? ovre: overrun error 0 = no overrun error has occurred since the last rststa. 1 = at least one overrun error has occurred since the last rststa. ? frame: framing error 0 = no framing error has occurred since the last rststa. 1 = at least one framing error has occurred since the last rststa. ? pare: parity error 0 = no parity error has occurred since the last rststa. 1 = at least one parity error has occurred since the last rststa. ? txempty: transmitter empty 0 = there are characters in uart_thr, or characters being processed by the transmitter, or the transmitter is disabled. 1 = there are no characters in uart_thr and there ar e no characters being processed by the transmitter. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCC CC C txempty C 76543210 pare frame ovre CC C txrdy rxrdy
888 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 888 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 41.6.7 uart receiver holding register name: uart_rhr address: 0xf8040018 (0), 0xf8044018 (1) access: read-only ? rxchr: received character last received character if rxrdy is set. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 rxchr
889 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 889 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 41.6.8 uart transmit holding register name: uart_thr address: 0xf804001c (0), 0xf804401c (1) access: write-only ? txchr: character to be transmitted next character to be transmitted after the current character if txrdy is not set. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 txchr
890 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 890 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 41.6.9 uart baud rate generator register name: uart_brgr address: 0xf8040020 (0), 0xf8044020 (1) access: read-write ? cd: clock divisor 0 = baud rate clock is disabled 1 to 65,535 = mck / (cd x 16) 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 cd 76543210 cd
891 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 891 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42. analog-to-digital converter (adc) 42.1 description the adc is based on a 10-bit analog-to-digita l converter (adc) managed by an adc control- ler. refer to the block diagram: figure 42-1 . it also integrates a 12-to-1 analog multiplexer, making possible the analog-to-digital conversions of 12 analog lines. the conversions extend from 0v to advref. the adc supports an 8-bit or 10-bit resolution mode, and conversion results are reported in a common register for all channels, as well as in a channel-dedicated reg- ister. software trigger, external trigger on rising edge of the adtrg pin or internal triggers from timer counter output(s) are configurable. the comparison circuitry allows automatic detection of values below a threshold, higher than a threshold, in a given range or outside the range, thresholds and ranges being fully configurable. the adc also integrates a sleep mode and a c onversion sequencer and connects with a dma channel. these features reduce both power consumption and processor intervention. a whole set of reference voltages is generated internally from a single external reference volt- age node that may be equal to the analog supply voltage. an external decoupling capacitance is required for noise filtering. finally, the user can configure adc timings, such as startup time and tracking time. this adc controller includes a resistive touchs creen controller. it supports 4-wire and 5-wire technologies. 42.2 embedded characteristics ? 10-bit resolution ? 300khz conversion rate ? wide range power supply operation ? resistive 4-wire and 5-wire touchscreen controller C position and pressure measurement for 4-wire screens C position measurement for 5-wire screens C average of up to 8 measures for noise filtering ? programmable pen detection sensitivity ? integrated multiplexer offering up to 12 independent analog inputs ? individual enable and disable of each channel ? hardware or software trigger C external trigger pin C internal trigger counter C trigger on pen contact detection ? dma support ? possibility of adc timings configuration ? two sleep modes and conversion sequencer C automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels C possibility of custom ized channel sequence
892 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 892 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? standby mode for fast wakeup time response C power down capability ? automatic window comparison of converted values ? write protect registers 42.3 block diagram figure 42-1. analog-to-digital converter block diagram with touchscreen mode 42.4 signal description table 42-1. adc pin description pin name description vddana analog power supply advref reference voltage ad0 - ad 11 analog input channels adtrg external trigger adc interrupt adtrg vddana advref gnd trigger selection control logic successive approximation register analog-to-digital converter user interface interrupt controller peripheral bridge apb dma system bus touch screen analog inputs ad0/xp/ul ad1/xm/ur ad3/ym/sense ad- ad- ad- adc controller pmc mck adc cell ad2/yp/ll ad4/lr pio other analog inputs 0 1 2 3 4 chx timer counter channels touch screen switches
893 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 893 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.5 product dependencies 42.5.1 power management the adc controller is not continuously clock ed. the programmer must first enable the adc controller mck in the power management cont roller (pmc) before using the adc controller. however, if the application doe s not require adc operations, the adc controller clock can be stopped when not needed and restarted when necessary. configuring the adc controller does not require the adc controller clock to be enabled. 42.5.2 interrupt sources the adc interrupt line is connected on one of the internal sources of the interrupt controller. using the adc interrupt requires the interrupt controller to be programmed first. 42.5.3 analog inputs the analog input pins can be multiplexed with pio lines. in this case, the assignment of the adc input is automatically done as soon as the corresponding channel is enabled by writing the reg- ister adc_cher. by default, after reset, the pio line is configured as input with its pull-up enabled and the adc input is connected to the gnd. 42.5.4 i/o lines the pin adtrg may be shared with other peripheral functions through the pio controller. in this case, the pio controller should be set acco rdingly to assign the pin adtrg to the adc function. table 42-2. peripheral ids instance id adc 19 table 42-3. i/o lines instance signal i/o line peripheral adc adtrg pb18 b adc ad0 pb11 x1 adc ad1 pb12 x1 adc ad2 pb13 x1 adc ad3 pb14 x1 adc ad4 pb15 x1 adc ad5 pb16 x1 adc ad6 pb17 x1 adc ad7 pb6 x1 adc ad8 pb7 x1 adc ad9 pb8 x1 adc ad10 pb9 x1 adc ad11 pb10 x1
894 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 894 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.5.5 timer triggers timer counters may or may not be used as hardware triggers depending on user requirements. thus, some or all of the timer counters may be unconnected. 42.5.6 conversion performances for performance and electrical characteristics of the adc, see the product dc characteristics section. 42.6 functional description 42.6.1 analog-to-digital conversion the adc uses the adc clock to perform conver sions. converting a single analog value to a 10 - bit digital data requires tracki ng clock cycles as defined in the field tracktim of the adc mode register on page 916 and transfer clock cycles as defined in the field transfer of the same register. the adc clock frequency is selected in the prescal field of the mode register (adc_mr). the tracking phase starts during the conversion of the previous channel. if the track- ing time is longer than the conversion time, the tracking phase is extended to the end of the previous conversion. the adc clock range is between mck/2, if presc al is 0, and mck/512, if prescal is set to 255 (0xff). prescal must be programmed in order to provide an adc clock frequency according to the parameters given in the product electrical characteristics section. figure 42-2. sequence of adc conversions 42.6.2 conversion reference the conversion is performed on a full range be tween 0v and the reference voltage pin advref. analog inputs between these voltages convert to values based on a linear conversion. adcclock lcdr adc_on adc_sel drdy adc_start ch0 ch1 ch0 ch2 ch1 sta rt up time (and tr a cking of ch0) conver sion of ch0 conver sion of ch1 tr a cking of ch1 tr a cking of ch2 adc_eoc trigger event (hard or soft) analog cell ios
895 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 895 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.6.3 conversion resolution the adc supports 8-bit or 10-bit resolutions. the 8-bit selection is performed by setting the lowres bit in the adc mode r egister (adc_mr). by default, after a reset, the resolution is the highest and the data field in the data registers is fully used. by setting the lowres bit, the adc switches to the lowest resolution and the c onversion results can be read in the lowest sig- nificant bits of the data registers. the two highest bits of the data field in the corresponding adc_cdr register and of the ldata field in the adc_lcdr register read 0. 42.6.4 conversion results when a conversion is completed, the resulting 10-bit digital value is stored in the channel data register (adc_cdrx) of the current channel and in the adc last converted data register (adc_lcdr). by setting the tag option in the adc_emr, the adc_lcdr presents the chan- nel number associated to the last converted data in the chnb field. the channel eoc bit in the status register (adc_sr) is set and the drdy is set. in the case of a connected dma channel, drdy ri sing triggers a data transfer request. in any case, either eoc and drdy can trigger an interrupt. reading one of the adc_cdr registers clears the corresponding eoc bit. reading adc_lcdr clears the drdy bit and eoc bit corresponding to the last converted channel. figure 42-3. eocx and drdy flag behavior if the adc_cdr is not read befo re further incoming data is converted, the corresponding over- run error (ovrex) flag is set in the overrun status register (adc_over). likewise, new data converted when drdy is hi gh sets the govre bit (general overrun error) in adc_sr. the ovrex flag is automatically cleared when adc_over is read, and govre flag is auto- matically cleared when adc_sr is read. read the adc_cdrx eocx drdy read the adc_lcdr chx (adc_chsr) (adc_sr) (adc_sr) write the adc_cr with start = 1 write the adc_cr with start = 1
896 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 896 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 42-4. govre and ovrex flag behavior warning: if the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during a conversion, its associated data and its corresponding eoc and ovre flags in adc_sr are unpredictable. eoc0 govre ch0 (adc_chsr) (adc_sr) (adc_sr) trigger event eoc1 ch1 (adc_chsr) (adc_sr) ovre0 (adc_over) undefined data data a data b adc_lcdr undefined data data a adc_cdr0 undefined data data b adc_cdr1 data c data c conversion c conversion a drdy (adc_sr) read adc_cdr1 read adc_cdr0 conversion b read adc_over read adc_sr ovre1 (adc_over)
897 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 897 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.6.5 conversion triggers conversions of the active analog channels are start ed with a software or hardware trigger. the software trigger is provided by writing the control register (adc_ cr) with the start bit at 1. the hardware trigger can be selected by the trgmod field in the adc trigger register between: ? any edge, either rising or fa lling or both, detected on the external trigger pin, tsadtrg. the pen detect, depending on how the pendet bit is set in the adc touchscreen mode register. ? a continuous trigger, meaning the adc controller restarts the next sequence as soon as it finishes the current one ? a periodic trigger, which is defined by programming the trgper field in the adc trigger register. the minimum time between 2 consecutive trigger events must be strictly greater than the dura- tion time of the longest conversion sequence according to configuration of registers adc_mr, adc_chsr, adc_seqr1, adc_seqr2, adc_tsmr. if a hardware trigger is selected, the start of a conversion is triggered after a delay starting at each rising edge of the selected signal. due to asynchronous handling, the delay may vary in a range of 2 mck clock periods to 1 adc clock period. only one start command is necessary to initiate a conversion sequence on all the channels. the adc hardware logic automatically performs the conversions on the active channels, then waits for a new request. the channel enable (adc_cher) and channel disable (adc_chdr) reg- isters permit the analog channels to be enabled or disabled independently. if the adc is used with a dma, only the transf ers of converted data from enabled channels are performed and the resulting data buffers should be interpreted accordingly. 42.6.6 sleep mode and conversion sequencer the adc sleep mode maximizes power saving by automatically deactivating the adc when it is not being used for conversions. sleep mode is selected by setting the sleep bit in the mode register adc_mr. the sleep mode is automatically managed by a conversion sequencer, which can automatically process the conversions of all channels at lowest power consumption. this mode can be used when the minimum period of time between 2 successive trigger events is greater than the startup period of analog-digit al converter (see the product adc characteris- tics section). when a start conversion request occurs, the adc is automatically activated. as the analog cell requires a start-up time, the logic waits during this time and starts the conversion on the enabled channels. when all conversions are complete, the adc is deactivated until the next trigger. trig- gers occurring during the sequence are not taken into account. the conversion sequencer allows automatic processing with minimum processor intervention and optimized power consumption. conversion sequences can be performed periodically using trigger start delay
898 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 898 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 the internal timer (adc_trgr register). the periodic acquisition of several samples can be pro- cessed automatically without any intervention of the processor thanks to the dma. the sequence can be customized by programming the sequence channel registers, adc_seqr1 and adc_seqr2 and setting to 1 the useq bit of the mode register (adc_mr). the user can choose a specific order of channels and can program up to 12 conversions by sequence. the user is totally free to create a personal sequence, by writing channel numbers in adc_seqr1 and adc_seqr2. not only can channel numbers be written in any sequence, channel numbers can be repeated several times. only enabled sequence bitfields are con- verted, consequently to program a 15-conversion sequence, the user can simply put a disable in adc_chsr[15], thus disabling the 16thch field of adc_seqr2. note: the reference voltage pins always remain connected in normal mode as in sleep mode. 42.6.7 comparison window the adc controller features automatic comparison functions. it compares converted values to a low threshold or a high threshold or both, according to the cmpmode function chosen in the extended mode register (adc_emr). the comparison can be done on all channels or only on the channel specified in cmpsel field of adc_emr. to compare all channels the cmp_all parameter of adc_emr should be set. the flag can be read on the compe bit of the interrupt status register (adc_isr) and can trig- ger an interrupt. the high threshold and the low threshold can be read/write in the comparison window regis- ter (adc_cwr). if the comparison window is to be used with lowres bit in adc_mr set to 1, the thresholds do not need to be adjusted as adju stment will be done inte rnally. whether or not the lowres bit is set, thresholds must always be configured in consideration of the maximum adc resolution. 42.6.8 adc timings each adc has its own minimal startup time that is programmed through the field startup in the mode register, adc_mr. a minimal tracking time is necessary for the adc to guarantee the best converted final value between two channel selections. this time has to be programmed through the tracktim bit field in the mode register, adc_mr. warning: no input buffer amplifier to isolate the source is included in the adc. this must be taken into consideration to program a precise value in the tracktim field. see the product adc characteristics section. 42.7 touchscreen 42.7.1 touchscreen mode the tsmode parameter of adc touchscreen mode register is used to enable/disable the touchscreen functionality, to select the type of screen (4-wire or 5-wire) and, in the case of a 4- wire screen, to activate (or not) the pressure measurement. in 4-wire mode, channel 0, 1, 2 and 3 must no t be used for classic adc conversions. likewise, in 5-wire mode, channel 0, 1, 2, 3, and 4 must not be used for classic adc conversions.
899 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 899 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.7.2 4-wire resistive touchscreen principles a resistive touchscreen is based on two resistive f ilms, each one being fitted with a pair of elec- trodes, placed at the top and bottom on one film, and on the right and left on the other. in between, there is a layer acting as an insulator, but also enables contact when you press the screen. this is illustrated in figure 42-5 . the tsadc controller has the ability to perform without exte rnal components: ? position measurement ? pressure measurement ? pen detection figure 42-5. touchscreen position measurement 42.7.3 4-wire position measurement method as shown in figure 42-5 , to detect the position of a contact, a supply is first applied from top to bottom. due to the linear resistance of the film, there is a voltage gradient from top to bottom. when a contact is performed on the screen, the voltage propagates at the point the two surfaces come into contact with the second film. if the input impedance on the right and left electrodes sense is high enough, the film does not affect this voltage, despite its resistive nature. for the horizontal direction, the same method is used, but by applying supply from left to right. the range depends on the supply voltage and on the loss in the switches that connect to the top and bottom electrodes. in an ideal world (linear, with no loss through switches), the horizontal position is equal to: vy m / vdd or vy p / vdd. the implementation with on-chip power switches is shown in figure 42-6 . the voltage measure- ment at the output of the switch compensates for the switches loss. x m x p y m y p x p x m y p vdd gnd volt horizontal position detection y p y m x p vdd gnd volt vertical position detection pen contact
900 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 900 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 it is possible to correct for switch loss by performing the operation: [vy p - vx m ] / [vx p - vx m ]. this requires additional measurements, as shown in figure 42-6 . figure 42-6. touchscreen switches implementation 42.7.4 4-wire pressure measurement method the method to measure the pressure (rp) applied to the touchscreen is based on the known resistance of the x-panel resistance (rxp). three conversions (xpos,z1,z2) are necessary to determine the value of rp (zaxis resistance). rp = rxp*(xpos/1024)*[(z2/z1)-1] x p x m y m vddana y p vddana gnd gnd to the adc x p x m y p vddana gnd switch resistor switch resistor y p y m x p vddana gnd switch resistor switch resistor horizontal position detection vertical position detection 0 1 2 3
901 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 901 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 42-7. pressure measurement 42.7.5 5-wire resistive touchscreen principles to make a 5-wire touchscreen, a resistive layer with a contact point at each corner and a con- ductive layer are used. the 5-wire touchscreen differs from the 4-wire type mainly in that the voltage gradient is applied only to one layer, the resistive layer, while the other layer is the sense layer for both measurements. the measurement of the x position is obtained by biasing the upper left corner and lower left corner to v ddana and the upper right corner and lower right to ground. to measure along the y axis, bias the upper left corner and upper right corner to v ddana and bias the lower left corner and lower right corner to ground. x p x m vddana gnd switch resistor switch resistor xpos measure(yp) y p y m open circuit rp x p x m vddana gnd switch resistor switch resistor z1 measure(xp) y p y m open circuit rp x p x m vddana gnd switch resistor switch resistor z2 measure(xp) y p y m open circuit rp
902 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 902 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 42-8. 5-wire principle 42.7.6 5-wire position measurement method in an application only monitoring clicks, 100 points per second is typically needed. for handwrit- ing or motion detection, the number of measurements to consider is approximately 200 points per second. this must take into account that multiple measurements are included (over sam- pling, filtering) to co mpute the correct point. the 5-wire touchscreen panel works by applying a voltage at the corners of the resistive layer and measuring the vertical or horizontal resi stive network with the s ense input. the adc con- verts the voltage measured at the point the panel is touched. a measurement of the y position of the pointing device is made by: ? connecting upper left (ul) and upper right (ur) corners to vddana ? connecting lower left (ll) and lower right (lr) corners to ground. ? the voltage measured is determined by the voltage divider developed at the point of touch (yposition) and the sense input is converted by adc. a measurement of the x position of the pointing device is made by: ? connecting the upper left (ul) and lower left (ll) corners to ground ? connecting the upper right and lower right corners to vddana. ? the voltage measured is determined by the voltage divider developed at the point of touch (xposition) and the sense input is converted by adc. pen contact u l u r l l l r sense resistive layer conductive layer u l u r l l l r vddana gnd vddana for yp gnd for xp vddana for xp gnd for yp sense
903 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 903 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 42-9. touchscreen switches implementation 42.7.7 sequence and noise filtering the adc controller can manage adc conversions and touchscreen measurement. on each trigger event the sequence of adc conversions is performed as described in section 42.6.6 sleep mode and conversion sequencer . the touchscreen measure frequency can be speci- fied in number of trigger events by writing the tsfreq parameter in the adc touchscreen mode register. an internal counter counts triggers up to tsfreq, and every time it rolls out, a touchscreen sequence is appended to the classic adc conversion sequence (see figure 42- 10 ). additionally the user can average multiple to uchscreen measures by writing the tsav parame- ter in the adc touchscreen mode register. this can be 1, 2, 4 or 8 measures performed on consecutive triggers as illustrated in figure 42-10 bellow. consequently, the tsfreq parame- ter must be grea ter or equal to the tsav parameter. u l u r l r vddana l l vddana gnd to the adc vddana gnd sen se u l u r l l l r vddana gnd vddana for ypos gnd for xpos vddana for xpos gnd for ypos sense gnd 0 1 2 3 4
904 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 904 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 42-10. insertion of touchscreen sequences (tsfreq = 2; tsav = 1) 42.7.8 measured values, registers and flags as soon as the controller finishes the touchscreen sequence, xrdy, yrdy and prdy are set and can generate an interrupt. these flags can be read in the adc interrupt status register. they are reset independently by reading in adc_xposr, adc_yposr and adc_pressr. for classic adc conversions. the adc touchscreen x position register presents xpos (v x - v xmin ) on its lsb and xscale (v xmax - v xmin ) aligned on the 16th bit. the adc touchscreen y position register presents ypos (v y - v ymin ) on its lsb and yscale (v ymax - v ymin ) aligned on the 16th bit. to improve the quality of the measure, the user must calculate: xpos/xscale and ypos/yscale. v xmax, v xmin, v ymax, and v ymin are measured at the first start up of the controller. these values can change during use, so it can be necessary to refresh them. refresh can be done by writing 1 in the calib field of the control register (adc_cr). the adc touchscreen pressure register pr esents z1 on its lsb and z2 aligned on the 16th bit. see section 42.7.4 to know how use them. 42.7.9 pen detect method when there is no contact, it is not necessary to perform a conversion. however, it is important to detect a contact by keeping the powe r consumption as low as possible. the implementation polarizes one panel by closing the switch on (x p /u l ) and ties the horizontal panel by an embedded resistor connected to y m / sense. this resistor is enabled by a fifth switch. since there is no contact, no current is flowing and there is no related power consump- tion. as soon as a contact occurs, a current is flowing in the touchscreen and a schmitt trigger detects the voltage in the resistor. the touchscreen interrupt configuration is entered by programming the pendet bit in the adc touchscreen mode register. if this bit is written at 1, the controller samples the pen con- tact state when it is not converting and waiting for a trigger. trigger event adc_sel xrdy read the adc_xposr read the adc_xposr c t c t c c t c t c c c: classic adc conversion sequence - t: touch screen sequence yrdy read the adc_yposr read the adc_yposr
905 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 905 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 to complete the circuit, a programmable debouncer is placed at the output of the schmitt trig- ger. this debouncer is programmable up to 2 15 adc clock periods. the debouncer length can be selected by programming the field pendbc in adc touchscreen mode register. due to the analog switchs structure, the debounce r circuitry is only active when no conversion (touchscreen or classic adc channels) is in prog ress. thus, if the time between the end of a conversion sequence and the arrival of the next trigger event is lower than the debouncing time configured on pendbc, the debouncer will not detect any contact. figure 42-11. touchscreen pen detect the touchscreen pen detect can be used to generate an adc interrupt to wake up the system. the pen detect generates two types of status, reported in the adc interrupt status register: ? the pen bit is set as soon as a contact exceeds the debouncing time as defined by pendbc and remains set until adc_sr is read. ? the nopen bit is set as soon as no current flows for a time over the debouncing time as defined by pendbc and remains set until adc_sr is read. both bits are automatically cleared as soon as the status register (adc_sr) is read, and can generate an interrupt by writing the adc interrupt enable register. moreover, the rising of either one of them clears the other, they cannot be set at the same time. the pens bit of the adc_sr indicates the current status of the pen contact. 42.7.10 buffer structure the dma read channel is triggered each time a new data is stored in adc_lcdr register. the same structure of data is repeatedly stored in adc_lcdr register each time a trigger event occurs. depending on user mode of operation (adc_mr, adc_chsr, adc_seqr1, adc_seqr2, adc_tsmr) the structure differs. each data transferred to dma buffer, carried x+/u l x-/u r l r vddana y+/l l vddana gnd gnd to the adc vddana gnd y-/sense gnd gnd pen interrupt debouncer pendbc 0 1 2 3 4
906 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 906 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 on a half-word (16-bit), consists of last converted data right aligned and when tag is set in adc_emr register, the 4 most significant bits ar e carrying the channel number thus allowing an easier post-processing in the dma buffer or better checking the dma buffer integrity. as soon as touchscreen conversions are required , the pen detection function may help the post- processing of the buffer. to get more details refer to section 42.7.10.4 pen detection status . 42.7.10.1 classical adc channels only when no touchscreen conversion is required (i.e. tsmode = 0 in adc_tsmr register), the structure of data within the buffer is de fined by the adc_mr, adc_chsr, adc_seqr1, adc_seqr2 registers. if the user sequence is not used (i.e. useq is cleared in adc_mr register) then only the value of adc_chsr register defines the data structure. for each trigger event, enabled channels will be consecutively stored in adc_lcdr register and automatically transferred to the buffer. when the user sequence is configured (i.e. useq is set in adc_mr register) not only does adc_chsr register modify the data structur e of the buffer, but adc_seqr1, adc_seqr2 registers may modify the data structure of the buffer as well. figure 42-12. buffer structure when tsmode = 0 42.7.10.2 touchscreen channels only when only touchscreen conversions are required (i.e. tsmode differs from 0 in adc_tsmr register and adc_chsr equals 0), the structure of data within the buffer is defined by the adc_tsmr register. when tsmode = 1 or 3, each trigger event adds 2 half-words in the buffer (assuming tsav = 0), first half-word being xpos of adc_xposr register then ypos of adc_yposr register. if tsav/tsfreq differs from 0, t he data structure remains unchang ed. not all trigger events add data to the buffer. base address (ba) ba + 0x02 adc_cdr6 6 adc_cdr5 5 adc_cdr8 8 ba + 0x04 adc_cdr6 6 adc_cdr5 5 adc_cdr8 8 ba + 0x06 ba + 0x08 ba + 0x0a adc_cdr6 6 adc_cdr5 5 adc_cdr8 8 ba + [(n-1) * 6] ba + [(n-1) * 6]+ 0x02 ba + [(n-1) * 6]+ 0x04 assuming adc_chsr = 0x000_01600 adc_emr(tag) = 1 trig.event1 adc_cdr6 0 adc_cdr5 0 adc_cdr8 0 adc_cdr6 0 adc_cdr5 0 adc_cdr8 0 adc_cdr6 0 adc_cdr5 0 adc_cdr8 0 assuming adc_chsr = 0x000_01600 adc_emr(tag) = 0 dma bu ffer str ucture dma bu ffer str ucture trig.event2 trig.event1 trig.event2 trig.eventn trig.eventn dma transfer
907 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 907 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 when tsmode = 2, each trigger event adds 4 half-words to the buffer (assumin g tsav=0), first half-word being xpos of adc_xposr register followed by ypos of adc_yposr register and finally z1 followed by z2, both located in adc_pressr register. when tag is set (adc_emr), the chnb field (4 most significant bit of the adc_lcdr) register is set to 0 when xpos is transmitted and set to 1 when ypos is transm itted, allowing an easier post-processing of the buffer or better checking buffer integrity. in case 4-wire with pressure mode is selected, z1 value is transmitted to the buffer along with tag set to 2 and z2 is tagged with value 3. xscale and yscale (calibration values) are not transmitted to the buffer because they are supposed to be constant and moreover only measured at the very first start up of the controller or upon user request. there is no change in buffer structure whatever the value of pendet bit configuration in adc_tsmr register but it is recommended to use the pen detection function for buffer post-pro- cessing (refer to pen detection status on page 911 ).
908 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 908 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 42-13. buffer structure when only touchscreen channels are enabled 42.7.10.3 interleaved channels when both classic adc channe ls (ch4/ch5 up to ch12 are set in adc_chsr) and touch- screen conversions are required (tsmode differs from 0 in adc_tsmr register) the structure of the buffer differs according to tsav and tsfreq values. if tsfreq differs from 0, not all events generate touchscreen conversions, therefore buffer structure is based on 2 tsfreq trigger events. given a tsfreq value, the location of touch- screen conversion results depends on tsav value. base address (ba) ba + 0x02 adc_yposr 1 adc_xposr 0 0 ba + 0x04 1 ba + 0x06 adc_yposr 1 adc_xposr 0 ba + [(n-1) * 4] ba + [(n-1) * 4]+ 0x02 assuming adc_tsmr(tsmod) = 1 or 3 adc_tsmr(tsav) = 0 adc_chsr = 0x000_00000 , adc_emr(tag) = 1 trig.event1 dma buffer structure trig.event2 trig.eventn dma transfer assuming adc_tsmr(tsmod) =1 or 3 adc_tsmr(tsav) = 0 adc_chsr = 0x000_00000 , adc_emr(tag) = 0 adc_yposr adc_xposr adc_yposr 0 adc_xposr 0 0 0 adc_yposr 0 adc_xposr 0 trig.event1 dma buffer structure trig.event2 trig.eventn adc_yposr adc_xposr base address (ba) ba + 0x02 adc_yposr 1 adc_xposr 0 2 ba + 0x04 3 ba + 0x06 ba + [(n-1) * 8] ba + [(n-1) * 8]+ 0x02 assuming adc_tsmr(tsmod) = 2 adc_tsmr(tsav) = 0 adc_chsr = 0x000_00000 , adc_emr(tag) = 1 trig.event1 dma buffer structure trig.event2 trig.eventn dma transfer assuming adc_tsmr(tsmod) = 2 adc_tsmr(tsav) = 0 adc_chsr = 0x000_00000 , adc_emr(tag) = 0 adc_pressr(z2) adc_pressr(z1) adc_yposr 1 adc_xposr 0 2 3 adc_pressr(z2) adc_pressr(z1) adc_yposr 1 adc_xposr 0 2 3 adc_pressr(z2) adc_pressr(z1) ba + 0x08 ba + 0x0a ba + 0x0c ba + 0x0e adc_yposr 0 adc_xposr 0 0 0 trig.event1 dma buffer structure trig.event2 trig.eventn adc_pressr(z2) adc_pressr(z1) adc_yposr 0 adc_xposr 0 0 0 adc_pressr(z2) adc_pressr(z1) adc_yposr 0 adc_xposr 0 0 0 adc_pressr(z2) adc_pressr(z1) ba + [(n-1) * 8]+ 0x04 ba + [(n-1) * 8]+ 0x06
909 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 909 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 when tsfreq = 0, tsav must equal 0. there is no change in buffer structure whatever the value of pendet bit configuration in adc_tsmr register but it is recommended to use the pen detection function for buffer post-pro- cessing (refer to pen detection status on page 911 ).
910 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 910 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 42-14. buffer structure when classic adc and touchscreen channels are interleaved base address (ba) ba + 0x02 adc_xposr 0 adc_cdr8 8 1 ba + 0x04 8 ba + 0x06 adc_yposr 1 adc_xposr 0 ba + [(n-1) * 6] ba + [(n-1) * 6]+ 0x02 assuming adc_tsmr(tsmod) = 1 adc_tsmr(ts av) = adc_tsmr(tsfreq) = 0 adc_chs r = 0x000_0100 , adc_emr(tag) =1 trig.event1 dma bu ffer str ucture trig.event2 trig.eventn dma transfer adc_cdr8 adc_yposr assuming adc_tsmr(tsmod) = 1 adc_tsmr(ts av) = adc_tsmr(tsfreq) = adc_chs r = 0x000_0100 , adc_emr(tag) ba + 0x08 ba + 0x0a 8 adc_yposr 1 adc_xposr 0 adc_cdr8 ba + [(n-1) * 6]+ 0x04 adc_xposr 0 adc_cdr8 0 0 0 adc_yposr 0 adc_xposr 0 trig.event1 dma bu ffer str ucture trig.event2 trig.eventn adc_cdr8 adc_yposr 0 adc_yposr 0 adc_xposr 0 adc_cdr8 base address (ba) ba + 0x02 adc_xposr 0 adc_cdr8 8 1 ba + 0x04 8 ba + 0x06 ba + [(n-1) * 8] ba + [(n-1) * 8]+ 0x02 assuming adc_tsmr(tsmod) = 1 adc_tsmr(ts av) = 0 adc_tsmr(tsfreq) = 1 adc_chs r = 0x000_0100 , adc_emr(tag) = 1 trig.event1 dma bu ffer str ucture trig.event2 trig.eventn dma transfer adc_cdr8 adc_yposr ba + 0x08 ba + 0x0a 8 adc_yposr 1 adc_xposr 0 adc_cdr8 ba + [(n-1) * 8]+ 0x04 8 adc_cdr8 adc_xposr 0 1 adc_yposr trig.event3 trig.event4 ba + 0x0c trig.eventn+1 8 adc_cdr8 8 adc_cdr8 ba + [(n-1) * 8]+ 0x06 ba + 0x0e assuming adc_tsmr(tsmod) = 1 adc_tsmr(ts av) = 1 adc_tsmr(tsfreq adc_chs r = 0x000_0100 , adc_emr(tag) adc_xposr 0 adc_cdr8 8 1 8 trig.event1 dma bu ffer str ucture trig.event2 trig.eventn adc_cdr8 adc_yposr trig.event3 trig.event4 trig.eventn+1 adc_xposr 0 adc_cdr8 8 1 8 adc_cdr8 adc_yposr adc_xposr 0 adc_cdr8 8 1 8 adc_cdr8 adc_yposr
911 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 911 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.7.10.4 pen detection status if the pen detection measure is enabled (pende t is set in adc_tsmr register), the xpos, ypos, z1, z2 values transmitted to the buffer through adc_lcdr register are cleared (includ- ing the chnb field), if the pens flag of adc_ isr register is 0. when the pens flag is set, xpos, ypos, z1, z2 ar e normally transmitted. therefore, using pen detection together with tag function eases the post-processing of the buf- fer, especially to determine which touchscreen converted values correspond to a period of time when the pen was in contact with the screen. when the pen detection is disabled or the tag function is disabled, xpos, ypos, z1, z2 are nor- mally transmitted without tag and no relationship can be found with pen status, thus post- processing may not be easy. figure 42-15. buffer structure with and without pen detection enabled base address (ba) ba + 0x02 adc_xposr 0 adc_cdr8 8 1 ba + 0x04 8 ba + 0x06 adc_yposr 1 adc_xposr 0 ba + [(n-1) * 6] ba + [(n-1) * 6]+ 0x02 assuming adc_tsmr(tsmod) = 1, pendet = 1 adc_tsmr(tsav) = adc_tsmr(tsfreq) = 0 adc_chsr = 0x000_0100 , adc_emr(tag) = 1 trig.event1 dma buffer structure trig.event2 trig.eventn dma transfer adc_cdr8 adc_yposr assuming adc_tsmr(tsmod) = 1, pendet = 1 adc_tsmr(tsav) = adc_tsmr(tsfreq) = 0 adc_chsr = 0x000_0100 , adc_emr(tag) =0 ba + 0x08 ba + 0x0a 8 00 00 adc_cdr8 ba + [(n-1) * 6]+ 0x04 adc_xposr 0 adc_cdr8 0 0 0 adc_yposr 0 adc_xposr 0 trig.event1 dma buffer structure trig.event2 trig.eventn adc_cdr8 adc_yposr 8 00 00 adc_cdr8 trig.eventn+1 pens = 1 pens = 0 pens = 1 pens = 0 0 0 0 adc_cdr8 0 0 0 adc_cdr8 adc_xposr* adc_yposr* adc_xposr* adc_yposr* 2 successive tags cleared => pens = 0 adc_xposr*, adc_yposr* can b a ny v alue when pens = 0
912 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 912 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.7.11 write protection registers to prevent any single software error that ma y corrupt adc behavior, certain address spaces can be write-protected by setting the wpen bit in the adc write protect mode register (adc_wpmr). if a write access to the protecte d registers is detected, then th e wpvs flag in the adc write pro- tect status register (adc_wpsr) is set and t he field wpvsrc indicates in which register the write access has been attempted. the wpvs flag is reset by writing the adc wr ite protect mode register (adc_wpmr) with the appropriate access key, wpkey. the protected registers are: ? adc mode register on page 916 ? adc channel sequence 1 register on page 918 ? adc channel sequence 2 register on page 919 ? adc channel enable register on page 920 ? adc channel disable register on page 921 ? adc extended mode register on page 930 ? adc compare window register on page 931 ? adc touchscreen mode register on page 934 ? adc trigger register on page 939
913 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 913 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.8 analog-to-digital conv erter (adc) user interface any offset not listed in table 42-4 must be considered as reserved. table 42-4. register mapping offset register name access reset 0x00 control register adc_cr write-only C 0x04 mode register adc_mr read-write 0x00000000 0x08 channel sequence register 1 adc_seqr1 read-write 0x00000000 0x0c channel sequence register 2 adc_seqr2 read-write 0x00000000 0x10 channel enable register adc_cher write-only C 0x14 channel disable register adc_chdr write-only C 0x18 channel status register adc_chsr read-only 0x00000000 0x1c reserved C C C 0x20 last converted data register adc_lcdr read-only 0x00000000 0x24 interrupt enable register adc_ier write-only C 0x28 interrupt disable register adc_idr write-only C 0x2c interrupt mask register adc_imr read-only 0x00000000 0x30 interrupt status regist er adc_isr read-only 0x00000000 0x34 reserved C C C 0x38 reserved C C C 0x3c overrun status register adc_over read-only 0x00000000 0x40 extended mode register adc_emr read-write 0x00000000 0x44 compare window register adc_cwr read-write 0x00000000 0x50 channel data register 0 adc_cdr0 read-only 0x00000000 0x54 channel data register 1 adc_cdr1 read-only 0x00000000 ... ... ... ... ... 0x7c channel data register 11 adc_cdr11 read-only 0x00000000 0x80 - 0x90 reserved C C C 0x94 analog control register adc_acr read-write 0x00000100 0x98 - 0xac reserved C C C 0xb0 touchscreen mode register adc_tsmr read-write 0x00000000 0xb4 touchscreen x position register adc_xposr read-only 0x00000000 0xb8 touchscreen y position register adc_yposr read-only 0x00000000 0xbc touchscreen pressure register adc_pressr read-only 0x00000000 0xc0 trigger register adc_trgr read-write 0x00000000 0xc4 - 0xe0 reserved C C C 0xe4 write protect mode register adc_wpmr read-write 0x00000000
914 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 914 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 2. if an offset is not listed in the table it must be considered as reserved. 0xe8 write protect status regi ster adc_wpsr read-only 0x00000000 0xec - 0xf8 reserved C C C 0xfc reserved C C C table 42-4. register mapping (continued) offset register name access reset
915 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 915 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.8.1 adc control register name: adc_cr address: 0xf804c000 access: write-only ? swrst: software reset 0 = no effect. 1 = resets the adc simulating a hardware reset. ? start: start conversion 0 = no effect. 1 = begins analog-to-digital conversion. ? tscalib: touchscreen calibration 0 = no effect. 1 = programs screen calibration (vdd/gnd measurement) the calibration sequence is performed during the next s equence when command is launched during an already started conversion sequence, or at the start of the second conversion sequence located after the tscalib command, if it is launched when no conversion is in progress (sleep mode, waiting a trigger event). tscalib measurement sequ ence does not affect the last da ta converted regi ster (adc_ldcr). 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCt s c a l i bs t a r ts w r s t
916 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 916 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.8.2 adc mode register name: adc_mr address: 0xf804c004 access: read-write this register can only be written if the wpen bit is cleared in adc write protect mode register on page 940 . ? lowres: resolution ? sleep: sleep mode ?fwup: fast wake up ? prescal: prescaler rate selection adcclock = mck / ( (prescal+1) * 2 ) ? startup: start up time 31 30 29 28 27 26 25 24 useq C C C tracktim 23 22 21 20 19 18 17 16 CCCC s t a r t u p 15 14 13 12 11 10 9 8 prescal 76543210 C fwup sleep lowres C C value name description 0 bits_10 10-bit resolution 1 bits_8 8-bit resolution value name description 0 normal normal mode: the adc core and reference vo ltage circuitry are kept on between conversions 1 sleep sleep mode: the adc core and reference voltage circuitry are off between conversions value name description 0 off normal sleep mode: the sleep mode is defined by the sleep bit 1 on fast wake up sleep mode: the voltage referenc e is on between conversions and adc core is off value name description 0 sut0 0 periods of adcclock 1 sut8 8 periods of adcclock 2 sut16 16 periods of adcclock 3 sut24 24 periods of adcclock
917 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 917 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? tracktim: tracking time tracking time = (tracktim + 1) * adcclock periods. ? useq: use sequence enable 4 sut64 64 periods of adcclock 5 sut80 80 periods of adcclock 6 sut96 96 periods of adcclock 7 sut112 112 periods of adcclock 8 sut512 512 periods of adcclock 9 sut576 576 periods of adcclock 10 sut640 640 periods of adcclock 11 sut704 704 periods of adcclock 12 sut768 768 periods of adcclock 13 sut832 832 periods of adcclock 14 sut896 896 periods of adcclock 15 sut960 960 periods of adcclock value name description 0 num_order normal mode: the controller converts channels in a simple numeric order. 1 reg_order user sequence mode: the sequence respects wh at is defined in adc_seqr1 and adc_seqr2 registers. value name description
918 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 918 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.8.3 adc channel sequence 1 register name: adc_seqr1 address: 0xf804c008 access: read-write this register can only be written if the wpen bit is cleared in adc write protect mode register on page 940 . ? uschx: user sequence number x the sequence number x (uschx) can be programmed by the channel number chy where y is the value written in this field. the allowed range is 0 up to 11. so it is only possible to use the sequencer from ch0 to ch11. this register activates only if adc_mr(useq) field is set to 1. any uschx field is taken into account only if adc_chsr(chx) register field reads logical 1 else any value written in uschx does not add the corresponding channel in the conversion sequence. configuring the same value in different fields leads to multiple samples of the same channel during the conversion sequence. this can be done consecutively, or not, according to user needs. 31 30 29 28 27 26 25 24 usch8 usch7 23 22 21 20 19 18 17 16 usch6 usch5 15 14 13 12 11 10 9 8 usch4 usch3 76543210 usch2 usch1
919 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 919 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.8.4 adc channel sequence 2 register name: adc_seqr2 address: 0xf804c00c access: read-write this register can only be written if the wpen bit is cleared in adc write protect mode register on page 940 . ? uschx: user sequence number x the sequence number x (uschx) can be programmed by the channel number chy where y is the value written in this field. the allowed range is 0 up to 11. so it is only possible to use the sequencer from ch0 to ch11. this register activates only if adc_mr(useq) field is set to 1. any uschx field is taken into account only if adc_chsr(chx) register field reads logical 1 else any value written in uschx does not add the corresponding channel in the conversion sequence. configuring the same value in different fields leads to multiple samples of the same channel during the conversion sequence. this can be done consecutively, or not, according to user needs. 31 30 29 28 27 26 25 24 usch16 usch15 23 22 21 20 19 18 17 16 usch14 usch13 15 14 13 12 11 10 9 8 usch12 usch11 76543210 usch10 usch9
920 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 920 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.8.5 adc channel enable register name: adc_cher address: 0xf804c010 access: write-only this register can only be written if the wpen bit is cleared in adc write protect mode register on page 940 . ? chx: channel x enable 0 = no effect. 1 = enables the corresponding channel. note: if useq = 1 in adc_mr register, chx corresponds to the xth channel of the sequence described in adc_seqr1 and adc_seqr2. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCc h 1 1c h 1 0c h 9c h 8 76543210 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0
921 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 921 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.8.6 adc channel disable register name: adc_chdr address: 0xf804c014 access: write-only this register can only be written if the wpen bit is cleared in adc write protect mode register on page 940 . ? chx: channel x disable 0 = no effect. 1 = disables the corresponding channel. warning: if the corresponding channel is disabled during a conversion or if it is disabled then reenabled during a conver- sion, its associated data and its corresponding eoc and ovre flags in adc_sr are unpredictable. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCc h 1 1c h 1 0c h 9c h 8 76543210 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0
922 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 922 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.8.7 adc channel status register name: adc_chsr address: 0xf804c018 access: read-only ? chx: channel x status 0 = corresponding c hannel is disabled. 1 = corresponding channel is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCc h 1 1c h 1 0c h 9c h 8 76543210 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0
923 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 923 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.8.8 adc last conv erted data register name: adc_lcdr address: 0xf804c020 access: read-only ? ldata: last data converted the analog-to-digital conversion data is pl aced into this register at the end of a conversion and remains until a new conver- sion is completed. ? chnb: channel number indicates the last converted channel when the tag option is set to 1 in adc_emr register. if tag option is not set, chnb = 0. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 chnb ldata 76543210 ldata
924 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 924 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.8.9 adc interrupt enable register name: adc_ier address: 0xf804c024 access: write-only ? eocx: end of conversion interrupt enable x ? xrdy: touchscreen measure xpos ready interrupt enable ? yrdy: touchscreen measure ypos ready interrupt enable ? prdy: touchscreen measure pressure ready interrupt enable ? drdy: data ready interrupt enable ? govre: general overrun error interrupt enable ? compe: comparison event interrupt enable ? pen: pen contact interrupt enable ? nopen: no pen contact interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 C nopen pen C C compe govre drdy 23 22 21 20 19 18 17 16 Cp r d yy r d yx r d yCCCC 15 14 13 12 11 10 9 8 CCCCe o c 1 1e o c 1 0e o c 9e o c 8 76543210 eoc7 eoc6 eoc5 eoc4 eoc3 eoc2 eoc1 eoc0
925 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 925 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.8.10 adc interrupt disable register name: adc_idr address: 0xf804c028 access: write-only ? eocx: end of conversion interrupt disable x ? xrdy: touchscreen measure xpos ready interrupt disable ? yrdy: touchscreen measure ypos ready interrupt disable ? prdy: touchscreen measure pressure ready interrupt disable ? drdy: data ready interrupt disable ? govre: general overrun error interrupt disable ? compe: comparison event interrupt disable ? pen: pen contact interrupt disable ? nopen: no pen contact interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 C nopen pen C C compe govre drdy 23 22 21 20 19 18 17 16 Cp r d yy r d yx r d yCCCC 15 14 13 12 11 10 9 8 CCCCe o c 1 1e o c 1 0e o c 9e o c 8 76543210 eoc7 eoc6 eoc5 eoc4 eoc3 eoc2 eoc1 eoc0
926 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 926 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.8.11 adc interrupt mask register name: adc_imr address: 0xf804c02c access: read-only ? eocx: end of conversion interrupt mask x ? xrdy: touchscreen measure xpos ready interrupt mask ? yrdy: touchscreen measure ypos ready interrupt mask ? prdy: touchscreen measure pressure ready interrupt mask ? drdy: data ready interrupt mask ? govre: general overrun error interrupt mask ? compe: comparison event interrupt mask ? pen: pen contact interrupt mask ? nopen: no pen contact interrupt mask 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 C nopen pen C C compe govre drdy 23 22 21 20 19 18 17 16 Cp r d yy r d yx r d yCCCC 15 14 13 12 11 10 9 8 CCCCe o c 1 1e o c 1 0e o c 9e o c 8 76543210 eoc7 eoc6 eoc5 eoc4 eoc3 eoc2 eoc1 eoc0
927 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 927 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.8.12 adc interrupt status register name: adc_isr address: 0xf804c030 access: read-only ? eocx: end of conversion x 0 = corresponding analog channel is disabled , or the conversion is not finished. this flag is cleared when reading the cor- responding adc_cdrx registers. 1 = corresponding analog channel is enabled and conversion is complete. ? xrdy: touchscreen xpos measure ready 0 = no measure has been performed since the last read of adc_xposr. 1 = at least one measure has been performed since the last read of adc_isr. ? yrdy: touchscreen ypos measure ready 0 = no measure has been performed since the last read of adc_yposr. 1 = at least one measure has been performed since the last read of adc_isr. ? prdy: touchscreen pressure measure ready 0 = no measure has been performed since the last read of adc_pressr. 1 = at least one measure has been performed since the last read of adc_isr. ? drdy: data ready 0 = no data has been converted since the last read of adc_lcdr. 1 = at least one data has been conv erted and is ava ilable in adc_lcdr. ? govre: general overrun error 0 = no general overrun error occurred since the last read of adc_isr. 1 = at least one general overrun error has occurred since the last read of adc_isr. ? compe: comparison error 0 = no comparison error since the last read of adc_isr. 1 = at least one comparison error has occurred since the last read of adc_isr. ? pen: pen contact 0 = no pen contact since the last read of adc_isr. 31 30 29 28 27 26 25 24 pens nopen pen C C compe govre drdy 23 22 21 20 19 18 17 16 Cp r d yy r d yx r d yCCCC 15 14 13 12 11 10 9 8 CCCCe o c 1 1e o c 1 0e o c 9e o c 8 76543210 eoc7 eoc6 eoc5 eoc4 eoc3 eoc2 eoc1 eoc0
928 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 928 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1 = at least one pen contact since the last read of adc_isr. ? nopen: no pen contact 0 = no loss of pen contact since the last read of adc_isr. 1 = at least one loss of pen contact since the last read of adc_isr. ? pens: pen detect status 0 = the pen does not press the screen. 1 = the pen presses the screen. note: pens is not a source of interruption.
929 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 929 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.8.13 adc overrun status register name: adc_over address: 0xf804c03c access: read-only ? ovrex: overrun error x 0 = no overrun error on the corresponding channel since the last read of adc_over. 1 = there has been an overrun error on the corres ponding channel since the last read of adc_over. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCo v r e 1 1o v r e 1 0o v r e 9o v r e 8 76543210 ovre7 ovre6 ovre5 ovre4 ovre3 ovre2 ovre1 ovre0
930 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 930 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.8.14 adc extended mode register name: adc_emr address: 0xf804c040 access: read-write this register can only be written if the wpen bit is cleared in adc write protect mode register on page 940 . ? cmpmode: comparison mode ? cmpsel: comparison selected channel if cmpall = 0: cmpsel indicates wh ich channel has to be compared. if cmpall = 1: no effect. ? cmpall: compare all channels 0 = only channel indicated in cmpsel field is compared. 1 = all channels are compared. ? tag: tag of adc_ldcr register 0 = set chnb to zero in adc_ldcr. 1 = append the channel number to the conversion result in adc_ldcr register. 31 30 29 28 27 26 25 24 CCCCCCCt a g 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCc m p a l lC 76543210 cmpsel C C cmpmode value name description 0 low generates an event when the converted data is lower than the low threshold of the window. 1 high generates an event when the converted data is higher than the high threshold of the window. 2 in generates an event when the conver ted data is in the comparison window. 3 out generates an event when the converted data is out of the comparison window.
931 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 931 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.8.15 adc compare window register name: adc_cwr address: 0xf804c044 access: read-write this register can only be written if the wpen bit is cleared in adc write protect mode register on page 940 . ? lowthres: low threshold low threshold associated to compare settings of adc_emr register. ? highthres: high threshold high threshold associated to compare settings of adc_emr register. 31 30 29 28 27 26 25 24 CCCC h i g h t h r e s 23 22 21 20 19 18 17 16 highthres 15 14 13 12 11 10 9 8 CCCC l o w t h r e s 76543210 lowthres
932 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 932 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.8.16 adc channel data register name: adc_cdrx [x=0..11] address: 0xf804c050 access: read-write ? data: converted data the analog-to-digital conversion data is pl aced into this register at the end of a conversion and remains until a new conver- sion is completed. the convert data re gister (cdr) is only loaded if the corr esponding analog channel is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCC d a t a 76543210 data
933 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 933 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.8.17 adc analog control register name: adc_acr address: 0xf804c094 access: read-write this register can only be written if the wpen bit is cleared in adc write protect mode register on page 940 . ? pendetsens: pen de tection sensitivity allows to modify the pen detection input pull-up resistor valu e. (see the product electrical characteristics for further detail s). 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCC C 76543210 CCCCCC p e n d e t s e n s
934 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 934 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.8.18 adc touchscreen mode register name: adc_tsmr address: 0xf804c0b0 access: read-write this register can only be written if the wpen bit is cleared in adc write protect mode register on page 940 . ? tsmode: touchscreen mode when tsmod equals 01 or 10 (i.e. 4-wire mode), channel 0, 1, 2 and 3 must not be used for classic adc conversions. when tsmod equals 11 (i.e. 5-wire mode), channel 0, 1, 2, 3, and 4 must not be used. ? tsav: touchscreen average ? tsfreq: touchscreen frequency defines the touchscreen frequency compared to the trigger frequency. tsfreq must be greater or equal to tsav. the touchscreen frequency is: touchscreen frequency = trigger frequency / 2 tsfreq ? tssctim: touchscreen switches closure time defines closure time of analog switches necessa ry to establish the measurement conditions. 31 30 29 28 27 26 25 24 pendbc C C C pendet 23 22 21 20 19 18 17 16 C notsdma C C tssctim 15 14 13 12 11 10 9 8 CCCC t s f r e q 76543210 CC t s a v CC t s m o d e value name description 0 none no touchscreen 1 4_wire_no_pm 4-wire touchscre en without pressure measurement 2 4_wire 4-wire touchscreen with pressure measurement 3 5_wire 5-wire touchscreen value name description 0 no_filter no filtering. only one adc conversion per measure 1 avg2conv averages 2 adc conversions 2 avg4conv averages 4 adc conversions 3 avg8conv averages 8 adc conversions
935 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 935 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 the closure time is: switch closure time = (tssctim * 4) adcclock periods. ? pendet: pen contact detection enable 0: pen contact detection disable. 1: pen contact detection enable. when pendet = 1, xpos, ypos, z1, z2 values of adc_xposr, adc_yposr, adc_pressr registers are automati- cally cleared when pens = 0 in adc_isr. ? notsdma: no touchscreen dma 0: xpos, ypos, z1, z2 are transmitted in adc_lcdr. 1: xpos, ypos, z1, z2 are never transm itted in adc_lcdr, therefore the buffer does not contains touchscreen values. ? pendbc: pen detect debouncing period debouncing period = 2 pendbc adcclock periods.
936 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 936 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.8.19 adc touchscreen x position register name: adc_xposr address: 0xf804c0b4 access: read-only ? xpos: x position the position measured is stored here. if xpos = 0 or xpos = xsize, the pen is on the border. when pen detection is enabled (pendet set to 1 in adc_tsmr register), xpos is tied to 0 while there is no detection of contact on the touchscreen (i.e. when pens bitfield is cleared in adc_isr register). ? xscale: scale of xpos indicates the max value that xpos can reach. this value should be close to 2 10 . 31 30 29 28 27 26 25 24 CCCCCC x s c a l e 23 22 21 20 19 18 17 16 xscale 15 14 13 12 11 10 9 8 CCCCCC x p o s 76543210 xpos
937 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 937 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.8.20 adc touchscreen y position register name: adc_yposr address: 0xf804c0b8 access: read-only ? ypos: y position the position measured is stored here. if ypos = 0 or ypos = ysize, the pen is on the border. when pen detection is enabled (pendet set to 1 in adc_tsmr register), ypos is tied to 0 while there is no detection of contact on the touchscreen (i.e. when pens bitfield is cleared in adc_isr register). ? yscale: scale of ypos indicates the max value that ypos can reach. this value should be close to 2 10 31 30 29 28 27 26 25 24 CCCCCC y s c a l e 23 22 21 20 19 18 17 16 yscale 15 14 13 12 11 10 9 8 CCCCCC y p o s 76543210 ypos
938 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 938 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.8.21 adc touchscreen pressure register name: adc_pressr address: 0xf804c0bc access: read-only ? z1: data of z1 measurement data z1 necessary to calculate pen pressure. when pen detection is enabled (pendet set to 1 in adc_tsmr register), z1 is tied to 0 while there is no detection of contact on the touchscreen (i.e. when pens bitfield is cleared in adc_isr register). ? z2: data of z2 measurement data z2 necessary to calculate pen pressure. when pen detection is enabled (pendet set to 1 in adc_tsmr register), z2 is tied to 0 while there is no detection of contact on the touchscreen (i.e. when pens bitfield is cleared in adc_isr register). note: these two values are unavailable if tsmo de is not set to 2 in adc_tsmr register. 31 30 29 28 27 26 25 24 CCCCCC z 2 23 22 21 20 19 18 17 16 z2 15 14 13 12 11 10 9 8 CCCCCC z 1 76543210 z1
939 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 939 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.8.22 adc trigger register name: adc_trgr address: 0xf804c0c0 access: read-write ? trgmod: trigger mode ? trgper: trigger period effective only if trgmod defines a periodic trigger. defines the periodic trigger period, with the following equation: trigger period = (trgper+1) /adcclk the minimum time between 2 consecutive trigger events must be strictly greater than the duration time of the longest con- version sequence according to configuration of r egisters adc_mr, adc_chsr, adc_seqr1, adc_seqr2, adc_tsmr. when trgmod is set to pen de tect trigger (i.e. 100) and averaging is used (i.e. bitfi eld tsav differs from 0 in adc_tsmr register) only 1 measure is performed. thus, xrdy, yrdy, prdy, drdy will not rise on pen contact trigger. to achieve measurement, several triggers must be provided either by software or by setting the trgmod on continuous trigger (i.e. 110) until flags rise. 31 30 29 28 27 26 25 24 trgper 23 22 21 20 19 18 17 16 trgper 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCC trgmod value name description 0 no_trigger no trigger, only software trigger can start conversions 1 ext_trig_rise external trigger rising edge 2 ext_trig_fall external trigger falling edge 3 ext_trig_any external trigger any edge 4 pen_trig pen detect trigger (shall be selected only if pendet is set and tsamod = touchscreen only mode) 5 period_trig periodic trigger (trgper shall be initiated appropriately) 6 continuous continuous mode 7Cr e s e r v e d
940 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 940 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.8.23 adc write protect mode register name: adc_wpmr address: 0xf804c0e4 access: read-write ? wpen: write protect enable 0 = disables the write protect if wpkey corresponds to 0x4144 43 (adc in ascii). 1 = enables the write protect if wpkey corresponds to 0x414443 (adc in ascii). protects the registers: adc mode register on page 916 adc channel sequence 1 register on page 918 adc channel sequence 2 register on page 919 adc channel enable register on page 920 adc channel disable register on page 921 adc extended mode register on page 930 adc compare window register on page 931 adc touchscreen mode register on page 934 adc trigger register on page 939 ? wpkey: write protect key should be written at value 0x414443 (adc in ascii). writing any other value in this field aborts the write operation of the wpen bit. always reads as 0. 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 CCCCCCCw p e n
941 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 941 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 42.8.24 adc write protect status register name: adc_wpsr address: 0xf804c0e8 access: read-only ? wpvs: write protect violation status 0 = no write protect violation has occurred since the last read of the adc_wpsr register. 1 = a write protect violation has occurred since the last read of the adc_wpsr register. if this violation is an unauthor- ized attempt to write a protected register, the associated violation is reported into field wpvsrc. ? wpvsrc: write protect violation source when wpvs is active, this field indicates the write-protected register (t hrough address offset or code) in which a write access has been attempted. reading adc_wpsr automatically clears all fields. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 wpvsrc 15 14 13 12 11 10 9 8 wpvsrc 76543210 CCCCCCCw p v s
942 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 942 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12
943 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 943 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 43. synchronous serial controller (ssc) 43.1 description the synchronous serial controller (ssc) provides a synchronous communication link with external devices. it supports many serial sy nchronous communication protocols generally used in audio and telecom applications such as i2s, short frame sync, long frame sync, etc. the ssc contains an independent receiver and transmitter and a common clock divider. the receiver and the transmitter each interface with three signals: the td/rd signal for data, the tk/rk signal for the clock and the tf/rf signal for the frame sync. the transfers can be pro- grammed to start automatically or on different events detected on the frame sync signal. the ssc high-level of pr ogrammability and its use of dma perm it a continuous high bit rate data transfer without processor intervention. featuring connection to the dma, the ssc permits interfacing with low processor overhead to the following: ? codecs in master or slave mode ? dac through dedicated serial interface, particularly i2s ? magnetic card reader 43.2 embedded characteristics ? provides serial synchronous communication links used in audio and telecom applications ? contains an independent receiver and transmitter and a common clock divider ? interfaced with the dma controller (dmac) to reduce processor overhead ? offers a configurable frame sync and data length ? receiver and transmitter can be programmed to start automatically or on detection of different events on the frame sync signal ? receiver and transmitter include a data signal, a clock signal and a frame synchronization signal
944 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 944 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 43.3 block diagram figure 43-1. block diagram 43.4 application block diagram figure 43-2. application block diagram ssc interface pio dma apb bridge mck system bus peripheral bus tf tk td rf rk rd interrupt control ssc interrupt pmc interrupt management power management test management ssc serial audio os or rtos driver codec frame management line interface time slot management
945 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 945 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 43.5 pin name list 43.6 product dependencies 43.6.1 i/o lines the pins used for interfacing the compliant external devices may be multiplexed with pio lines. before using the ssc receiver, the pio contro ller must be configured to dedicate the ssc receiver i/o lines to the ssc peripheral mode. before using the ssc transmitter, the pio controller must be configured to dedicate the ssc transmitter i/o lines to the ssc peripheral mode. 43.6.2 power management the ssc is not continuously clocked. the ssc interface may be clocked through the power management controller (pmc), therefore the programmer must first configure the pmc to enable the ssc clock. 43.6.3 interrupt the ssc interface has an interrupt line connected to the interrupt controller. handling interrupts requires programming the interrupt controller before configuring the ssc. all ssc interrupts can be enabled/disabled configur ing the ssc interrupt mask register. each pending and unmasked ssc interrupt will assert the ssc interrupt line. the ssc interrupt ser- vice routine can get the interrupt origin by reading the ssc interrupt status register. table 43-1. i/o lines description pin name pin description type rf receiver frame synchro input/output rk receiver clock input/output rd receiver data input tf transmitter frame synchro input/output tk transmitter clock input/output td transmitter data output table 43-2. i/o lines instance signal i/o line peripheral ssc rd pa27 b ssc rf pa29 b ssc rk pa28 b ssc td pa26 b ssc tf pa25 b ssc tk pa24 b table 43-3. peripheral ids instance id ssc 28
946 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 946 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 43.7 functional description this chapter contains the functional description of the following: ssc functional block, clock management, data format, start, transmitter, receiver and frame sync. the receiver and transmitter operate separately. however, they can work synchronously by pro- gramming the receiver to use the transmit clock and/or to start a data transfer when transmission starts. alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. the transmitter and the receiver can be pro- grammed to operate with the clock signals provided on either the tk or rk pins. this allows the ssc to support many slave-mode data transfer s. the maximum clock speed allowed on the tk and rk pins is the master clock divided by 2. figure 43-3. ssc functional block diagram 43.7.1 clock management the transmitter clock can be generated by: ? an external clock received on the tk i/o pad ? the receiver clock ? the internal clock divider user interface apb mck re c e i v e cl o c k controller tx cl ock rk inpu t clock o utpu t c ontroller frame s ync controller transmit clock controller transmit shif t register st a r t se l e c t o r st a r t se l e c t o r transmit s ync holding r egist er transmit holding re g i st e r rx c l o c k tx c l ock tk input rd rf rk clock output controller frame s ync controller receive shift register re c e i v e sy n c holding r egist er receive holding r egist er td tf tk rx cl o c k re c e i v e r transmitter dat a controller txen dat a controller rf tf rx st a r t rxen rc0 r tx st ar t interrupt control to interrupt controller clock divider rx st a r t tx st ar t
947 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 947 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 the receiver clock can be generated by: ? an external clock received on the rk i/o pad ? the transmitter clock ? the internal clock divider furthermore, the transmitter block can generate an external clock on the tk i/o pad, and the receiver block can generate an external clock on the rk i/o pad. this allows the ssc to support many master and slave mode data transfers. 43.7.1.1 clock divider figure 43-4. divided clock block diagram the master clock divider is determined by the 12-bit field div counter and comparator (so its maximal value is 4095) in the clock mode register ssc_cmr, allowing a master clock division by up to 8190. the divided clock is provided to both the receiver and transmitter. when this field is programmed to 0, the clock divider is not used and remains inactive. when div is set to a value equal to or greater than 1, the divided clock has a frequency of mas- ter clock divided by 2 times div. each level of the divided clock has a duration of the master clock multiplied by div. this ensures a 50% duty cycle for the divided clock regardless of whether the div value is even or odd. figure 43-5. divided clock generation mck divided clock clock divider / 2 12-bit counter ssc_cmr master clock divided clock div = 1 master clock divided clock div = 3 divided clock frequency = mck/2 divided clock frequency = mck/6
948 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 948 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 43.7.1.2 transmitter clock management the transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the tk i/o pad. the transm itter clock is selected by the cks field in ssc_tcmr (transmit clock mode register). transmit clock can be inverted independently by the cki bits in ssc_tcmr. the transmitter can also drive the tk i/o pad cont inuously or be limited to the actual data trans- fer. the clock output is configured by the ssc_tcmr register. the transmit clock inversion (cki) bits have no effect on the clock outputs. programming the tcmr register to select tk pin (cks field) and at the same time continuous transmit clock (cko field) might lead to unpredict- able results. figure 43-6. transmitter clock management 43.7.1.3 receiver clock management the receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the rk i/o pad. the receive clock is selected by the cks field in ssc_rcmr (receive clock mode register). receive clocks can be inverted independently by the cki bits in ssc_rcmr. the receiver can also drive the rk i/o pad continuo usly or be limited to the actual data transfer. the clock output is configured by the ssc_rcmr register. the receive clock inversion (cki) bits have no effect on the clock outputs. programming the rcmr register to select rk pin (cks field) and at the same time continuous receive clock (cko field) can lead to unpredictable results. tk (pin) receiver clock divider clock cks cko data transfer cki ckg transmitter clock clock output mux tri_state controller tri-state controller inv mux
949 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 949 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 43-7. receiver clock management 43.7.1.4 serial clock ratio considerations the transmitter and the receiver can be programmed to operate with the clock signals provided on either the tk or rk pins. this allows the ssc to support many slave-mode data transfers. in this case, the maximum clock speed allowed on the rk pin is: C master clock divided by 2 if receiver frame synchro is input C master clock divided by 3 if receiver frame synchro is output in addition, the maximum clock speed allowed on the tk pin is: C master clock divided by 6 if transmit frame synchro is input C master clock divided by 2 if transmit frame synchro is output 43.7.2 transmitter operations a transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. the start event is configured by setting the transmit clock mode register (ssc_tcmr). see start on page 951. the frame synchronization is configured setting the transmit frame mode register (ssc_tfmr). see frame sync on page 953. to transmit data, the transmitter uses a shift re gister clocked by the transmitter clock signal and the start mode selected in the ssc_tcmr. data is written by the application to the ssc_thr register then transferred to the shift register according to the data format selected. when both the ssc_thr and the transmit shift register are empty, the status flag txempty is set in ssc_sr. when the transmit holding register is transferred in the transmit shift register, the status flag txrdy is set in ssc_sr and additional data can be loaded in the holding register. rk (pin) transmitter clock divider clock cks cko data transfer cki ckg receiver clock clock output mux tri-state controller tri-state controller inv mux
950 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 950 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 43-8. transmitter block diagram 43.7.3 receiver operations a received frame is triggered by a start event and can be followed by synchronization data before data transmission. the start event is configured setting the receive clock mode register (ssc_rcmr). see start on page 951. the frame synchronization is configured setting the receive frame mode register (ssc_rfmr). see frame sync on page 953. the receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the ssc_rcmr. the data is transferred from the shift register depending on the data format selected. when the receiver shift register is full, the ssc transfers this data in the holding register, the sta- tus flag rxrdy is set in ssc_sr and the data c an be read in the receiver holding register. if another transfer occurs before read of the rhr register, the status flag overun is set in ssc_sr and the receiver shift register is transferred in the rhr register. transmit shift register td ssc_tfmr.fslen ssc_tfmr.datlen ssc_tcmr.sttdly ssc_tfmr.fsden ssc_tfmr.datnb ssc_tfmr.datdef ssc_tfmr.msbf ssc_tcmr.sttdly != 0 ssc_tfmr.fsden 10 tx controller ssc_tcmr.start rf start selector txen rx start txen rf start selector rxen rc0r tx start tx start transmitter clock tx controller counter reached sttdly ssc_rcmr.start ssc_thr ssc_tshr ssc_crtxen ssc_srtxen ssc_crtxdis
951 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 951 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 43-9. receiver block diagram 43.7.4 start the transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the transmit start sele ction (start) field of ssc_tcmr and in the receive start selection (start) field of ssc_rcmr. under the following conditions the start event is independently programmable: ? continuous. in this case, the transmission st arts as soon as a word is written in ssc_thr and the reception starts as soon as the receiver is enabled. ? synchronously with the transmitter/receiver ? on detection of a falling/rising edge on tf/rf ? on detection of a low level/high level on tf/rf ? on detection of a level change or an edge on tf/rf a start can be programmed in the same manner on either side of the transmit/receive clock register (rcmr/tcmr). thus, the start coul d be on tf (transmit) or rf (receive). moreover, the receiver can start when data is detected in the bit stream with the compare functions. detection on tf/rf input/output is done by the field fsos of the transmit/receive frame mode register (tfmr/rfmr). ssc_rfmr.msbf ssc_rfmr.datnb ssc_tcmr.start ssc_rcmr.start ssc_rhr ssc_rshr ssc_rfmr.fslen ssc_rfmr.datlen rx controller counter reached sttdly rx controller rd ssc_cr.rxen ssc_cr.rxdis ssc_sr.rxen receiver clock rf txen rx start rf rxen rc0r ssc_rcmr.sttdly != 0 receive shift register start selector start selector rx start load load
952 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 952 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 43-10. transmit start mode figure 43-11. receive pulse/ed ge start modes x tk tf (input) td (output) td (output) td (output) td (output) td (output) td (output) xb ob 1 x bo b1 bo b1 bo b1 bo b1 bo b1 bo b1 b1 bo x x x sttdly sttdly sttdly sttdly sttdly sttdly start = falling edge on tf start = rising edge on tf start = low level on tf start = high level on tf start = any edge on tf start = level change on tf x rk rf (input) rd (input) rd (input) rd (input) rd (input) rd (input) rd (input) xb ob 1 x bo b1 bo b1 bo b1 bo b1 bo b1 bo b1 b1 bo x x x sttdly sttdly sttdly sttdly sttdly sttdly start = falling edge on rf start = rising edge on rf start = low level on rf start = high level on rf start = any edge on rf start = level change on rf
953 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 953 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 43.7.5 frame sync the transmitter and receiver frame sync pins, tf and rf, can be programmed to generate different kinds of frame synchron ization signals. the frame sync output selection (fsos) field in the receive frame mode register (ssc_rfmr) and in the transmit frame mode register (ssc_tfmr) are used to select the required waveform. ? programmable low or high levels during data transfer are supported. ? programmable high levels before the start of data transfers or toggling are also supported. if a pulse waveform is selected, the frame sync length (fslen) field in ssc_rfmr and ssc_tfmr programs the length of the pulse, from 1 bit time up to 256 bit time. the periodicity of the receive and transmit frame sync pulse output can be programmed through the period divider selection ( period) field in ssc_rcmr and ssc_tcmr. 43.7.5.1 frame sync data frame sync data transmits or receives a specific tag during the frame sync signal. during the frame sync signal, the receiver can sample the rd line and store the data in the receive sync holding register and the transmitter can transfer transmit sync holding register in the shifter register. the data length to be sampled/shifted out during the frame sync signal is programmed by the fslen field in ssc_rfmr/ssc_tfmr and has a maximum value of 16. concerning the receive frame sync data operation, if the frame sync length is equal to or lower than the delay between the start event and the actual data reception, the data sampling operation is performed in the re ceive sync holding register thr ough the receive shift register. the transmit frame sync operation is performed by the transmitter only if the bit frame sync data enable (fsden) in ssc_tfmr is set. if the frame sync length is equal to or lower than the delay between the start event and the actual data transmission, the normal transmission has priority and the data contained in the transmit sync holding register is transferred in the trans- mit register, then shifted out. 43.7.5.2 frame sync edge detection the frame sync edge detection is programmed by the fsedge field in ssc_rfmr/ssc_tfmr. this sets the corres ponding flags rxsyn/txsyn in the ssc status register (ssc_sr) on frame synchro edge detection (signals rf/tf). 43.7.6 receive compare modes figure 43-12. receive compare modes cmp0 cmp3 cmp2 cmp1 ignored b0 b2 b1 start rk rd (input) fslen up to 16 bits (4 in this example) stdly datlen
954 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 954 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 43.7.6.1 compare functions length of the comparison patterns (compare 0, compare 1) and thus the number of bits they are compared to is defined by fslen, but with a maximum value of 16 bits. comparison is always done by comparing the last bits received with the comparison pattern. compare 0 can be one start event of the receiver. in this case, the receiver compares at each new sample the last bits received at the compare 0 pattern contained in the compare 0 register (ssc_rc0r). when this start event is selected, the user can program the receiver to start a new data transfer either by writing a new compare 0, or by receiving continuously until compare 1 occurs. this selection is done with the bit (stop) in ssc_rcmr. 43.7.7 data format the data framing format of both the transmitter and the receiver are programmable through the transmitter frame mode register (ssc_tfmr) and the receiver frame mode register (ssc_rfmr). in either case, the user can independently select: ? the event that starts the data transfer (start) ? the delay in number of bit periods between the start event and the first data bit (sttdly) ? the length of the data (datlen) ? the number of data to be transferred for each start event (datnb). ? the length of synchronization transferred for each start event (fslen) ? the bit sense: most or lowest significant bit first (msbf) additionally, the transmitter can be used to tr ansfer synchronization and select the level driven on the td pin while not in data transfer operation. this is done respectively by the frame sync data enable (fsden) and by the data default value (datdef) bits in ssc_tfmr.
955 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 955 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 43-13. transmit and receive frame format in edge/pulse start modes note: 1. example of input on falling edge of tf/rf. figure 43-14. transmit frame format in continuous mode table 43-4. data frame registers transmitter receiver field length comment ssc_tfmr ssc_rfmr datlen up to 32 size of word ssc_tfmr ssc_rfmr datnb up to 16 number of words transmitted in frame ssc_tfmr ssc_rfmr msbf most significant bit first ssc_tfmr ssc_rfmr fslen up to 16 size of synchro data register ssc_tfmr datdef 0 or 1 data default value ended ssc_tfmr fsden enable send ssc_tshr ssc_tcmr ssc_rcmr period up to 512 frame size ssc_tcmr ssc_rcmr sttdly up to 255 size of transmit start delay sync data default sttdly sync data ignored rd default data datlen data data data datlen data data default default ignored sync data sync data fslen tf/rf (1) start start from ssc_tshr from ssc_thr from ssc_thr from ssc_thr from ssc_thr to ssc_rhr to ssc_rhr to ssc_rshr td (if fsden = 0) td (if fsden = 1) datnb period fromdatdef fromdatdef from datdef from datdef datlen data datlen data default start from ssc_thr from ssc_thr td start: 1. txempty set to 1 2. write into the ssc_thr
956 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 956 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 note: 1. sttdly is set to 0. in this example, ssc_thr is loaded twice. fsden value has no effect on the transmission. syncdata cannot be output in continuous mode. figure 43-15. receive frame format in continuous mode note: 1. sttdly is set to 0. 43.7.8 loop mode the receiver can be programmed to receive transmissions from the transmitter. this is done by setting the loop mode (loop) bit in ssc_rfmr. in this case, rd is connected to td, rf is connected to tf and rk is connected to tk. 43.7.9 interrupt most bits in ssc_sr have a corresponding bit in interrupt management registers. the ssc can be programmed to generate an interrupt when it detects an event. the interrupt is controlled by writing ssc_ier (interrupt enable register) and ssc_idr (interrupt disable reg- ister) these registers enable and disable, respectively, the corresponding interrupt by setting and clearing the corresponding bit in ssc_imr (interrupt mask register), which controls the generation of interrupts by asserting the ssc interrupt line connected to the interrupt controller. figure 43-16. interrupt block diagram data datlen data datlen start = enable receiver to ssc_rhr to ssc_rhr rd ssc_imr interrupt control ssc interrupt set rxrdy ovrun rxsync receiver transmitter txrdy txempty txsync clear ssc_ier ssc_idr
957 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 957 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 43.8 ssc application examples the ssc can support several serial communica tion modes used in audio or high speed serial links. some standard applications are shown in t he following figures. all se rial link applications supported by the ssc are not listed here. figure 43-17. audio application block diagram figure 43-18. codec application block diagram ssc rk rf rd td tf tk clock sck word select ws data sd i2s receiver clock sck word select ws data sd right channel left channel msb msb lsb ssc rk rf rd td tf tk serial data clock (sclk) frame sync (fsync) serial data out serial data in codec serial data clock (sclk) frame sync (fsync) serial data out serial data in first time slot dstart dend
958 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 958 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 43-19. time slot application block diagram ssc rk rf rd td tf tk sclk fsync data out data in codec first time slot serial data clock (sclk) frame sync (fsync) serial data out serial data in codec second time slot first time slot second time slot dstart dend
959 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 959 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 43.8.1 write protection registers to prevent any single software error that may co rrupt ssc behavior, certain address spaces can be write-protected by setting the wpen bit in the ssc write protect mode register (ssc_wpmr). if a write access to the protecte d registers is detected, then th e wpvs flag in the ssc write pro- tect status register (us_wpsr) is set and the field wpvsrc indicates in which register the write access has been attempted. the wpvs flag is reset by writing the ssc write protect mode register (ssc_wpmr) with the appropriate access key, wpkey. the protected registers are: ? ssc clock mode register on page 962 ? ssc receive clock mode register on page 963 ? ssc receive frame mode register on page 965 ? ssc transmit clock mode register on page 967 ? ssc transmit frame mode register on page 969 ? ssc receive compare 0 register on page 975 ? ssc receive compare 1 register on page 976
960 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 960 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 43.9 synchronous serial contro ller (ssc) user interface table 43-5. register mapping offset register name access reset 0x0 control register ssc_cr write-only C 0x4 clock mode register ssc_cmr read-write 0x0 0x8 reserved C C C 0xc reserved C C C 0x10 receive clock mode register ssc_rcmr read-write 0x0 0x14 receive frame mode register ssc_rfmr read-write 0x0 0x18 transmit clock mode register ssc_tcmr read-write 0x0 0x1c transmit frame mode register ssc_tfmr read-write 0x0 0x20 receive holding register ssc_rhr read-only 0x0 0x24 transmit holding register ssc_thr write-only C 0x28 reserved C C C 0x2c reserved C C C 0x30 receive sync. holding register ssc_rshr read-only 0x0 0x34 transmit sync. holding register ssc_tshr read-write 0x0 0x38 receive compare 0 register ssc_rc0r read-write 0x0 0x3c receive compare 1 register ssc_rc1r read-write 0x0 0x40 status register ssc_sr read-only 0x000000cc 0x44 interrupt enable register ssc_ier write-only C 0x48 interrupt disable register ssc_idr write-only C 0x4c interrupt mask register ssc_imr read-only 0x0 0xe4 write protect mode register ssc_wpmr read-write 0x0 0xe8 write protect status register ssc_wpsr read-only 0x0 0x50-0xfc reserved C C C 0x100-0x124 reserved C C C
961 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 961 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 43.9.1 ssc control register name: ssc_cr: address: 0xf0010000 access: write-only ? rxen: receive enable 0 = no effect. 1 = enables receive if rxdis is not set. ? rxdis: receive disable 0 = no effect. 1 = disables receive. if a character is currently being re ceived, disables at end of current character reception. ? txen: transmit enable 0 = no effect. 1 = enables transmit if txdis is not set. ? txdis: transmit disable 0 = no effect. 1 = disables transmit. if a character is currently being trans mitted, disables at end of current character transmission. ? swrst: software reset 0 = no effect. 1 = performs a software reset. has priority on any other bit in ssc_cr. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 s w r s tCCCCCt x d i st x e n 76543210 CCCCCCr x d i sr x e n
962 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 962 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 43.9.2 ssc clock mode register name: ssc_cmr address: 0xf0010004 access: read-write this register can only be written if the wpen bit is cleared in ssc write protect mode register . ? div: clock divider 0 = the clock divider is not active. any other value: the divided clock equals the master clock divided by 2 times div. the maximum bit rate is mck/2. the minimum bit rate is mck/2 x 4095 = mck/8190. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCC d i v 76543210 div
963 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 963 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 43.9.3 ssc receive clock mode register name: ssc_rcmr address: 0xf0010010 access: read-write this register can only be written if the wpen bit is cleared in ssc write protect mode register . ? cks: receive clock selection ? cko: receive clock output mode selection ? cki: receive clock inversion 0 = the data inputs (data and frame sync signals) are sampled on receive clock falling edge. the frame sync signal output is shifted out on receive clock rising edge. 1 = the data inputs (data and frame sync signals) are samp led on receive clock rising edge. the frame sync signal out- put is shifted out on receive clock falling edge. cki affects only the receive clock and not the output clock signal. 31 30 29 28 27 26 25 24 period 23 22 21 20 19 18 17 16 sttdly 15 14 13 12 11 10 9 8 C C C stop start 76543210 ckg cki cko cks value name description 0 mck divided clock 1tk tk clock signal 2rk rk pin value name description 0 none none, rk pin is an input 1 continuous continuous receive clock, rk pin is an output 2 transfer receive clock only during data transfers, rk pin is an output
964 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 964 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? ckg: receive clock gating selection ? start: receive start selection ? stop: receive stop selection 0 = after completion of a data transfer when starting with a compare 0, the receiver stops the data transfer and waits for a new compare 0. 1 = after starting a receive with a compare 0, the receiver operates in a continuous mode until a compare 1 is detected. ? sttdly: receive start delay if sttdly is not 0, a delay of sttdly clock cycles is inserted between the start event and the actual start of reception. when the receiver is programmed to start synchronously with the transmitter, the delay is also applied. note: it is very important that sttdly be set carefully. if sttdly must be set, it should be done in relation to tag (receive sync data) reception. ? period: receive period divider selection this field selects the divider to apply to the selected receive clock in order to generate a new frame sync signal. if 0, no period signal is generated. if not 0, a period sig nal is generated each 2 x (period+1) receive clock. value name description 0 continuous none 1 en_rf_low receive clock enabled only if rf pin is low 2 en_rf_high receive clock enabled only if rf pin is high value name description 0 continuous continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. 1transmit transmit start 2 rf_low detection of a low level on rf signal 3rf_high detection of a high level on rf signal 4rf_falling detection of a falling edge on rf signal 5 rf_rising detection of a rising edge on rf signal 6 rf_level detection of any level change on rf signal 7rf_edge detection of any edge on rf signal 8cmp_0 compare 0
965 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 965 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 43.9.4 ssc receive frame mode register name: ssc_rfmr address: 0xf0010014 access: read-write this register can only be written if the wpen bit is cleared in ssc write protect mode register . ? datlen: data length 0 = forbidden value (1-bit data length not supported). any other value: the bit stream contains datlen + 1 data bits. ? loop: loop mode 0 = normal operating mode. 1 = rd is driven by td, rf is driven by tf and tk drives rk. ? msbf: most significant bit first 0 = the lowest significant bit of the data register is sampled first in the bit stream. 1 = the most significant bit of the data register is sampled first in the bit stream. ? datnb: data number per frame this field defines the number of data words to be received after each transfer start, which is equal to (datnb + 1). ? fslen: receive frame sync length this field defines the number of bits sampled and stored in the receive sync data register. when this mode is selected by the start field in the receive clock mode register, it also determines the length of the sampled data to be compared to the compare 0 or compare 1 register. this field is used with fslen_ext to determine the pulse length of the receive frame sync signal. pulse length is equal to fslen + (fslen_ext * 16) + 1 receive clock periods. 31 30 29 28 27 26 25 24 fslen_ext C C C fsedge 23 22 21 20 19 18 17 16 C fsos fslen 15 14 13 12 11 10 9 8 CCC C d a t n b 765 4 3210 msbf C loop datlen
966 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 966 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? fsos: receive frame sync output selection ? fsedge: frame sync edge detection determines which edge on frame sy nc will generate the in terrupt rxsyn in the ssc status register. ? fslen_ext: fslen field extension extends fslen field. for details, refer to fslen bit description on page 965 . value name description 0 none none, rf pin is an input 1negative negative pulse, rf pin is an output 2 positive positive pulse, rf pin is an output 3low driven low during data transfer, rf pin is an output 4high driven high during data transfer, rf pin is an output 5 toggling toggling at each start of data transfer, rf pin is an output value name description 0 positive positive edge detection 1 negative negative edge detection
967 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 967 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 43.9.5 ssc transmit clock mode register name: ssc_tcmr address: 0xf0010018 access: read-write this register can only be written if the wpen bit is cleared in ssc write protect mode register . ? cks: transmit clock selection ? cko: transmit clock output mode selection ? cki: transmit clock inversion 0 = the data outputs (data and frame sync signals) are shi fted out on transmit clock falling edge. the frame sync signal input is sampled on transmit clock rising edge. 1 = the data outputs (data and frame sync signals) are shifte d out on transmit clock rising edge. the frame sync signal input is sampled on tran smit clock falling edge. cki affects only the transmit clock and not the output clock signal. 31 30 29 28 27 26 25 24 period 23 22 21 20 19 18 17 16 sttdly 15 14 13 12 11 10 9 8 CCCC s t a r t 76543210 ckg cki cko cks value name description 0 mck divided clock 1rk rk clock signal 2tk tk pin value name description 0 none none, tk pin is an input 1 continuous continuous transmit clock, tk pin is an output 2 transfer transmit clock only during data transfers, tk pin is an output
968 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 968 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? ckg: transmit clock gating selection ? start: transmit start selection ? sttdly: transmit start delay if sttdly is not 0, a delay of sttdly clock cycles is inse rted between the start event and the actual start of transmission of data. when the transmitter is programmed to start sync hronously with the receiver, the delay is also applied. note: sttdly must be set carefully. if sttdly is too short in respect to tag (transmit sync data) emission, data is emit- ted instead of the end of tag. ? period: transmit period divider selection this field selects the divider to apply to the selected transmi t clock to generate a new frame sync signal. if 0, no period signal is generated. if not 0, a period signal is generated at each 2 x (period+1) transmit clock. value name description 0 continuous none 1 en_tf_low transmit clock enabled only if tf pin is low 2en_tf_high transmit clock enabled only if tf pin is high value name description 0 continuous continuous, as soon as a word is written in the ssc_thr register (if transmit is enabled), and immediately after the end of transfer of the previous data. 1 receive receive start 2tf_low detection of a low level on tf signal 3 tf_high detection of a high level on tf signal 4 tf_falling detection of a falling edge on tf signal 5 tf_rising detection of a rising edge on tf signal 6 tf_level detection of any level change on tf signal 7tf_edge detection of any edge on tf signal
969 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 969 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 43.9.6 ssc transmit frame mode register name: ssc_tfmr address: 0xf001001c access: read-write this register can only be written if the wpen bit is cleared in ssc write protect mode register . ? datlen: data length 0 = forbidden value (1-bit data length not supported). any other value: the bit stream contains datlen + 1 data bits. . ? datdef: data default value this bit defines the level driven on the td pin while out of tran smission. note that if the pin is defined as multi-drive by th e pio controller, the pin is enabled only if the scc td output is 1. ? msbf: most significant bit first 0 = the lowest significant bit of the data register is shifted out first in the bit stream. 1 = the most significant bit of the data register is shifted out first in the bit stream. ? datnb: data number per frame this field defines the number of data words to be transferred after each transfer start, which is equal to (datnb +1). ? fslen: transmit frame sync length this field defines the length of the transmit frame sync sig nal and the number of bits shifted out from the transmit sync data register if fsden is 1. this field is used with fslen_ext to determine the pulse length of the transmit frame sync signal. pulse length is equal to fslen + (fslen_ext * 16) + 1 transmit clock period. 31 30 29 28 27 26 25 24 fslen_ext C C C fsedge 23 22 21 20 19 18 17 16 fsden fsos fslen 15 14 13 12 11 10 9 8 CCC C d a t n b 765 4 3210 m s b f C dat d e f dat l e n
970 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 970 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? fsos: transmit frame sync output selection ? fsden: frame sync data enable 0 = the td line is driven with the default value during the transmit frame sync signal. 1 = ssc_tshr value is shifted out during the transmission of the transmit frame sync signal. ? fsedge: frame sync edge detection determines which edge on frame sync will gene rate the interrupt tx syn (status register). ? fslen_ext: fslen field extension extends fslen field. for details, refer to fslen bit description on page 969 . value name description 0 none none, tf pin is an input 1negative negative pulse, tf pin is an output 2 positive positive pulse,tf pin is an output 3low tf pin driven low during data transfer 4high tf pin driven high during data transfer 5 toggling tf pin toggles at each start of data transfer value name description 0 positive positive edge detection 1 negative negative edge detection
971 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 971 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 43.9.7 ssc receive holding register name: ssc_rhr address: 0xf0010020 access: read-only ? rdat: receive data right aligned regardless of the number of data bits defined by datlen in ssc_rfmr. 31 30 29 28 27 26 25 24 rdat 23 22 21 20 19 18 17 16 rdat 15 14 13 12 11 10 9 8 rdat 76543210 rdat
972 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 972 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 43.9.8 ssc transmit holding register name: ssc_thr address: 0xf0010024 access: write-only ? tdat: transmit data right aligned regardless of the number of data bits defined by datlen in ssc_tfmr. 31 30 29 28 27 26 25 24 tdat 23 22 21 20 19 18 17 16 tdat 15 14 13 12 11 10 9 8 tdat 76543210 tdat
973 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 973 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 43.9.9 ssc receive synchronization holding register name: ssc_rshr address: 0xf0010030 access: read-only ? rsdat: receive synchronization data 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 rsdat 76543210 rsdat
974 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 974 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 43.9.10 ssc transmit synchronization holding register name: ssc_tshr address: 0xf0010034 access: read-write ? tsdat: transmit synchronization data 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 tsdat 76543210 tsdat
975 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 975 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 43.9.11 ssc receive compare 0 register name: ssc_rc0r address: 0xf0010038 access: read-write this register can only be written if the wpen bit is cleared in ssc write protect mode register . ? cp0: receive compare data 0 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 cp0 76543210 cp0
976 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 976 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 43.9.12 ssc receive compare 1 register name: ssc_rc1r address: 0xf001003c access: read-write this register can only be written if the wpen bit is cleared in ssc write protect mode register . ? cp1: receive compare data 1 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 cp1 76543210 cp1
977 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 977 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 43.9.13 ssc status register name: ssc_sr address: 0xf0010040 access: read-only ? txrdy: transmit ready 0 = data has been loaded in ssc_thr and is waiting to be loaded in the transmit shift register (tsr). 1 = ssc_thr is empty. ? txempty: transmit empty 0 = data remains in ssc_thr or is currently transmitted from tsr. 1 = last data written in ssc_thr has been loaded in tsr and last data loaded in tsr has been transmitted. ? rxrdy: receive ready 0 = ssc_rhr is empty. 1 = data has been received and loaded in ssc_rhr. ? ovrun: receive overrun 0 = no data has been loaded in ssc_rhr while previous data has not been read since the last read of the status register. 1 = data has been loaded in ssc_rhr while previous data has not yet been read since the last read of the status register. ?cp0: compare 0 0 = a compare 0 has not occurred since the last read of the status register. 1 = a compare 0 has occurred since the last read of the status register. ?cp1: compare 1 0 = a compare 1 has not occurred since the last read of the status register. 1 = a compare 1 has occurred since the last read of the status register. ? txsyn: transmit sync 0 = a tx sync has not occurred since the last read of the status register. 1 = a tx sync has occurred since the last read of the status register. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCr x e nt x e n 15 14 13 12 11 10 9 8 CCCCr x s y nt xsyn cp1 cp0 76543210 C C ovrun rxrdy C C txempty txrdy
978 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 978 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? rxsyn: receive sync 0 = an rx sync has not occurred since the last read of the status register. 1 = an rx sync has occurred since the last read of the status register. ? txen: transmit enable 0 = transmit is disabled. 1 = transmit is enabled. ? rxen: receive enable 0 = receive is disabled. 1 = receive is enabled.
979 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 979 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 43.9.14 ssc interrupt enable register name: ssc_ier address: 0xf0010044 access: write-only ? txrdy: transmit ready interrupt enable 0 = 0 = no effect. 1 = enables the transmit ready interrupt. ? txempty: transmit empty interrupt enable 0 = no effect. 1 = enables the transmit empty interrupt. ? rxrdy: receive ready interrupt enable 0 = no effect. 1 = enables the receive ready interrupt. ? ovrun: receive overrun interrupt enable 0 = no effect. 1 = enables the receive overrun interrupt. ? cp0: compare 0 interrupt enable 0 = no effect. 1 = enables the compare 0 interrupt. ? cp1: compare 1 interrupt enable 0 = no effect. 1 = enables the compare 1 interrupt. ? txsyn: tx sync interrupt enable 0 = no effect. 1 = enables the tx sync interrupt. ? rxsyn: rx sync interrupt enable 0 = no effect. 1 = enables the rx sync interrupt. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCr x s y nt xsyn cp1 cp0 76543210 C C ovrun rxrdy C C txempty txrdy
980 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 980 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 43.9.15 ssc interrupt disable register name: ssc_idr address: 0xf0010048 access: write-only ? txrdy: transmit ready interrupt disable 0 = no effect. 1 = disables the transmit ready interrupt. ? txempty: transmit empty interrupt disable 0 = no effect. 1 = disables the transmit empty interrupt. ? rxrdy: receive ready interrupt disable 0 = no effect. 1 = disables the receive ready interrupt. ? ovrun: receive overrun interrupt disable 0 = no effect. 1 = disables the receive overrun interrupt. ? cp0: compare 0 interrupt disable 0 = no effect. 1 = disables the compare 0 interrupt. ? cp1: compare 1 interrupt disable 0 = no effect. 1 = disables the compare 1 interrupt. ? txsyn: tx sync interrupt enable 0 = no effect. 1 = disables the tx sync interrupt. ? rxsyn: rx sync interrupt enable 0 = no effect. 1 = disables the rx sync interrupt. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCr x s y nt xsyn cp1 cp0 76543210 C C ovrun rxrdy C C txempty txrdy
981 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 981 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 43.9.16 ssc interrupt mask register name: ssc_imr address: 0xf001004c access: read-only ? txrdy: transmit ready interrupt mask 0 = the transmit ready interrupt is disabled. 1 = the transmit ready interrupt is enabled. ? txempty: transmit empty interrupt mask 0 = the transmit empty interrupt is disabled. 1 = the transmit empty interrupt is enabled. ? rxrdy: receive ready interrupt mask 0 = the receive ready interrupt is disabled. 1 = the receive ready interrupt is enabled. ? ovrun: receive overrun interrupt mask 0 = the receive overrun interrupt is disabled. 1 = the receive overrun interrupt is enabled. ? cp0: compare 0 interrupt mask 0 = the compare 0 interrupt is disabled. 1 = the compare 0 interrupt is enabled. ? cp1: compare 1 interrupt mask 0 = the compare 1 interrupt is disabled. 1 = the compare 1 interrupt is enabled. ? txsyn: tx sync interrupt mask 0 = the tx sync interrupt is disabled. 1 = the tx sync interrupt is enabled. ? rxsyn: rx sync interrupt mask 0 = the rx sync interrupt is disabled. 1 = the rx sync interrupt is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCr x s y nt xsyn cp1 cp0 76543210 C C ovrun rxrdy C C txempty txrdy
982 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 982 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 43.9.17 ssc write protect mode register name: ssc_wpmr address: 0xf00100e4 access: read-write reset: see table 43-5 ? wpen: write protect enable 0 = disables the write protect if wpkey corresponds to 0x535343 (ssc in ascii). 1 = enables the write protect if wpkey corresponds to 0x535343 (ssc in ascii). protects the registers: ? ssc clock mode register on page 962 ? ssc receive clock mode register on page 963 ? ssc receive frame mode register on page 965 ? ssc transmit clock mode register on page 967 ? ssc transmit frame mode register on page 969 ? ssc receive compare 0 register on page 975 ? ssc receive compare 1 register on page 976 ? wpkey: write protect key should be written at value 0x535343 (ssc in ascii). writing any other value in this field aborts the write operation of the wpen bit. always reads as 0. 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 w p e n
983 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 983 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 43.9.18 ssc write protect status register name: ssc_wpsr address: 0xf00100e8 access: read-only reset: see table 43-5 ? wpvs: write protect violation status 0 = no write protect violation has occurred since the last read of the ssc_wpsr register. 1 = a write protect violation has occurred since the last read of the ssc_wpsr register. if this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field wpvsrc. ? wpvsrc: write protect violation source when wpvs is active, this field indicates the write-protected register (t hrough address offset or code) in which a write access has been attempted. note: reading ssc_wpsr automatically clears all fields. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 wpvsrc 15 14 13 12 11 10 9 8 wpvsrc 76543210 w p v s
984 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 984 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12
985 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 985 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44. lcd controller (lcdc) 44.1 description the lcd controller consists of logic for transferring lcd image data from an external display buffer to an lcd module. the lcd has one display input buffer that fetches pixels through the ab master interface and a lookup table to allow palletized display configurations. the lcd con- troller is programmable on a per overlay basis, and supports different lcd resolution, window size, image format and pixel depth. the lcd is connected to the arm advanced high performance bus (ahb) as a master for reading pixel data. it also integrates an apb interface to configure its registers. 44.2 embedded characteristics ? one ahb master interface ? supports single scan active tft display ? supports 12-, 16-, 18- and 24-bit output mode through the spatial dithering unit ? asynchronous output mode supported ? 1, 2, 4, 8 bits per pixel (palletized) ? 12, 16, 18, 19, 24, 25 and 32 bits per pixel (non palletized) ? supports one base layer (background) ? little endian memory organization ? programmable timing engine, with integer clock divider ? programmable polarity for data, line synchro and frame synchro ? display size up to 1280 x 860 ? color lookup table with up to 256 entries ? programmable negative and positive row striding ? dma user interface uses linked list structure and add-to-queue structure
986 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 986 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.3 block diagram figure 44-1. block diagram 32-bit ahb master interf ace deag unit sysctrl unit 32-bit apb interf ace configur ation registers base la yer clut lt e unit lcd_dat[2 3:0] lcd_vsync lcd_hsync lcd_pclk lcd_den lcd_pwm lcd_disp deag: dma engine addre ss gener ation lte: lcd timing engine ahb bus
987 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 987 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.4 i/o lines description 44.5 product dependencies 44.5.1 i/o lines the pins used for interfacing the lcd controller may be multiplexed with pio lines. the pro- grammer must first program the pio controller to assign the pins to their peripheral function. if i/o lines of the lcd controller are not used by the application, they can be used for other pur- poses by the pio controller. table 44-1. i/o lines description name description type lcd_pwm contrast control signal, using pulse width modulation output lcd_hsync horizontal synchronization pulse output lcd_vsync vertical sync hronization pulse output lcd_dat[23:0] lcd 24-bit data bus output lcd_den data enable output lcd_disp display enable signal output lcd_pclk pixel clock output table 44-2. i/o lines instance signal i/o line peripheral lcdc lcddat0 pc0 a lcdc lcddat1 pc1 a lcdc lcddat2 pc2 a lcdc lcddat3 pc3 a lcdc lcddat4 pc4 a lcdc lcddat5 pc5 a lcdc lcddat6 pc6 a lcdc lcddat7 pc7 a lcdc lcddat8 pc8 a lcdc lcddat9 pc9 a lcdc lcddat10 pc10 a lcdc lcddat11 pc11 a lcdc lcddat12 pc12 a lcdc lcddat13 pc13 a lcdc lcddat14 pc14 a lcdc lcddat15 pc15 a lcdc lcddat16 pc16 a lcdc lcddat17 pc17 a
988 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 988 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.5.2 power management the lcd controller is not continuously clocked. the user must first enable the lcd controller clock in the power management contro ller before using it (pmc_pcer). 44.5.3 interrupt sources the lcd controller interrupt line is connected to one of the internal sources of the advanced interrupt controller. using the lcd controller interrupt requires prior programming of the aic. lcdc lcddat18 pc18 a lcdc lcddat19 pc19 a lcdc lcddat20 pc20 a lcdc lcddat21 pc21 a lcdc lcddat22 pc22 a lcdc lcddat23 pc23 a lcdc lcdden pc29 a lcdc lcddisp pc24 a lcdc lcdhsync pc28 a lcdc lcdpck pc30 a lcdc lcdpwm pc26 a lcdc lcdvsync pc27 a table 44-2. i/o lines table 44-3. peripheral ids instance id lcdc 25
989 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 989 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.6 functional description the lcd module integrates the following digital blocks: ? dma engine address generation (deag). this block performs data prefetch and requests access to the ahb interface. ? input fifo, stores the stream of pixels. ? color lookup table (clut). these 256 ram-based lookup table entries are selected when the color depth is set to 1, 2, 4 or 8 bpp. ? output fifo, stores the pixel prior to display. ? lcd timing engine, provides a fully programmable hsync-vsync interface. the dma controller reads the image through the ahb master interface. the lcd controller engine formats the display data and writes the final pixel into the output fifo. the programma- ble timing engine drives a valid pixel onto the lcd_dat[23:0] display bus. 44.6.1 timing engine configuration 44.6.1.1 pixel clock period configuration the pixel clock (pclk) generated by the timing engine is the source clock (sclk) divided by the field clkdiv in the lcdc_lcdcfg0 register. t he source clock can be selected between the system clock and the 2x system clock with the field clksel locate d in the lcdc_lcdcfg0 register. the pixel clock period formula is given below: the pixel clock polarity is also programmable. 44.6.1.2 horizontal and vertical synchronization configuration the following fields are used to configure the timing engine: ? hspw field ? vspw field ?vfpw field ? vbpw field ?hfpw field ? hbpw field ? ppl field ?rpf field the polarity of output signals is also programmable. 44.6.1.3 timing engine power up software operation the following sequence is used to enable the display: 1. configure lcd timing parameters, signal polarity and clock period. 2. enable the pixel clock by writing one to the clken field of the lcdc_lcden register. 3. poll clksts field of the lcdc_lcdsr register to check that the clock is running. 4. enable horizontal and vertical synchronization by writing one to the syncen field of the lcdc_lcden register. pclk sclk clkdiv 2 + -------------------------------- =
990 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 990 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 5. poll lcdsts field of the lcdc_lcdsr register to check that the synchronization is up. 6. enable the display power signal writing one to the dispen field of the lcdc_lcden register. 7. poll dispsts field of the lcdc_lcdsr register to check that the power signal is activated. the guardtime field of the lcdc_lcdcfg5 regi ster is used to configure the number of frames before the assertion of the disp signal. 44.6.1.4 timing engine power down software operation the following sequence is used to disable the display: 1. disable the disp signal writing dispdis field of the lcdc_lcddis register. 2. poll dispsts field of the lcdc_lcdsr register to verify that the disp is no longer activated. 3. disable the hsync and vsync signals by writing one to syncdis field of the lcdc_lcddis register. 4. poll lcdsts field of the lcdc_lcdsr register to check that the synchronization is off. 5. disable the pixel clock by writing one in the clkdis field of the lcdc_lcddis register.
991 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 991 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.6.2 dma software operations 44.6.2.1 dma channel descriptor (dscr) alignment and structure the dma channel descriptor (dscr) must be word aligned. the dma channel descriptor structure contains three fields: ? dscr.chxaddr: frame buffer base address register ? dscr.chxctrl: transfer control register ? dscr.chxnext: next descriptor address register 44.6.2.2 programming a dma channel 1. check the status of the channel reading the chxchsr register. 2. write the channel descriptor (dscr) structure in the system memory by writing dscr.chxaddr frame base address, dscr.chxctrl cha nnel control and dscr.chxnext next descriptor location. 3. if more than one descriptor is expected, the dfetch field of dscr.chxctrl is set to one to enable the descriptor fetch operation. 4. write the dscr.chxnext register with the address location of the descriptor struc- ture and set dfetch field of the dscr.chxctrl register to one. 5. enable the relevant channel by writing one to the chen field of the chxcher register. 6. an interrupt may be raised if unmasked when the descriptor has been loaded. 44.6.2.3 disabling a dma channel 1. clear the dfetch bit in the dscr.chxctrl field of the dscr structure will disable the channel at the end of the frame. 2. set the dscr.chxnext field of the dscr structure will disable the channel at the end of the frame. 3. writing one to the chdis field of the chx chdr register will disable the channel at the end of the frame. 4. writing one to the chrst field of the chxchdr regist er will disable the channel immediately. this may occur in the middle of the image. 5. poll chsr field in the chxchsr register un til the channel is successfully disabled. 44.6.2.4 dma dynamic linking of a new transfer descriptor 1. write the new descriptor structure in the system memory. 2. write the address of the new structure in the chxhead register. 3. add the new structure to the queue of descriptors by writing one to the a2qen field of the chxcher register. 4. the new descriptor will be added to the queue on the next frame. 5. an interrupt will be raised if unmasked, when the head descriptor structure has been loaded by the dma channel. table 44-4. dma channel descriptor structure system memory structure field for channel chx dscr + 0x0 addr dscr + 0x4 ctrl dscr + 0x8 next
992 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 992 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.6.2.5 dma interrupt generation the dma controller operation sets the following interrupt flags in the interrupt status register chxisr: ? dma field indicates that the dma transfer is completed. ? dscr field indicates that the descriptor structure is loaded in the dma controller. ? add field indicates that a descriptor has been added to the descriptor queue. ? done field indicates that the channel transfer has terminated and the channel is automatically disabled. 44.6.2.6 dma address alignment requirements when programming the dscr.chxaddr field of the dscr structure the following requirement must be met. table 44-5. dma address alignment when clut mode is selected clut mode dma address alignment 1 bpp 8 bit 2 bpp 8 bit 4 bpp 8 bit 8 bpp 8 bit table 44-6. dma address alignment when rgb mode is selected rgb mode dma address alignment 12 bpp rgb 444 16 bit 16 bpp argb 4444 16 bit 16 bpp rgba 4444 16 bit 16 bpp rgb 565 16 bit 16 bpp trgb 1555 16 bit 18 bpp rgb 666 32 bit 18 bpp rgb 666 packed 8 bit 19 bpp trgb 1666 32 bit 19 bpp trgb 1666 8 bit 24 bpp rgb 888 32 bit 24 bpp rgb 888 packed 8 bit 25 bpp trgb 1888 32 bit 32 bpp argb 8888 32 bit 32 bpp rgba 8888 32 bit
993 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 993 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.6.3 display software configuration 44.6.3.1 system bus access attributes these attributes are defined to improve bandwidth of the pixel stream. ? dlbo field: when set to one only defined burst lengths are performed when the dma channel retrieves the data from the memory. ? blen field: defines the maximum burst length of the dma channel. 44.6.3.2 color attributes ? clutmode field: selects the color lookup table mode ? rgbmode field: selects the rgb mode. 44.6.3.3 window attributes software operation 1. when required, write the overlay attributes configuration registers. 2. set updateen field of the chxcher register. 3. poll updatesr field in the chxchsr, the update applies when that field is reset. 44.6.4 rgb frame buffer memory bitmap 44.6.4.1 1 bpp through color lookup table 44.6.4.2 2 bpp through color lookup table 44.6.4.3 4 bpp through color lookup table table 44-7. 1 bpp memory mapping, little endian organization mem addr 0x3 0x2 0x1 0x0 bit 313029282726252423222120191817161514131211109876543210 pixel 1 bpp p3 1 p3 0 p2 9 p2 8 p2 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 p1 9 p1 8 p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 table 44-8. 2 bpp memory mapping, little endian organization mem addr 0x3 0x2 0x1 0x0 bit 313029282726252423222120191817161514131211109876543210 pixel 2 bpp p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 table 44-9. 4 bpp memory mapping, little endian organization mem addr 0x3 0x2 0x1 0x0 bit 313029282726252423222120191817161514131211109876543210 pixel 4 bpp p7 p6 p5 p4 p3 p2 p1 p0
994 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 994 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.6.4.4 8 bpp through color lookup table 44.6.4.5 12 bpp memory mapping, rgb 4:4:4 44.6.4.6 16 bpp memory mapping with alpha channel, argb 4:4:4:4 44.6.4.7 16 bpp memory mapping with alpha channel, rgba 4:4:4:4 44.6.4.8 16 bpp memory mapping with alpha channel, rgb 5:6:5 44.6.4.9 16 bpp memory mapping with transparency bit, argb 1:5:5:5 table 44-10. 8 bpp memory mapping, little endian organization mem addr 0x3 0x2 0x1 0x0 bit 313029282726252423222120191817161514131211109876543210 pixel 8 bpp p3 p2 p1 p0 table 44-11. 12 bpp memory mapping, little endian organization mem addr 0x3 0x2 0x1 0x0 bit 313029282726252423222120191817161514131211109 8 7 6 5 4 3 2 1 0 pixel 12 bpp C r1[3:0] g1[3:0] b1[3:0] C r0[3:0] g0[3:0] b0[3:0] table 44-12. 16 bpp memory mapping, little endian organization mem addr 0x3 0x2 0x1 0x0 bit 313029282726252423222120191817161514131211109 8 7 6 5 4 3 2 1 0 pixel 16 bpp a1[3:0] r1[3:0] g1[3:0] b1[3:0] a0[3:0] r0[3:0] g0[3:0] b0[3:0] table 44-13. 16 bpp memory mapping, little endian organization mem addr 0x3 0x2 0x1 0x0 bit 313029282726252423222120191817161514131211109 8 7 6 5 4 3 2 1 0 pixel 16 bpp r1[3:0] g13:0] b1[3:0] a1[3:0] r0[3:0] g0[3:0] b0[3:0] a0[3:0] table 44-14. 16 bpp memory mapping, little endian organization mem addr 0x3 0x2 0x1 0x0 bit 313029282726252423222120191817161514131211109876543210 pixel 16bpp r1[4:0] g1[5:0] b1[4:0] r0[4:0] g0[5:0] b0[4:0] table 44-15. 16 bpp memory mapping, little endian organization mem addr 0x3 0x2 0x1 0x0 bit 313029282726252423222120191817161514131211109 8 7 6 5 4 3 2 1 0 pixel 4 bpp a1 r1[4:0] g1[4:0] b1[4:0] a0 r0[4:0] g0[4:0] b0[4:0]
995 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 995 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.6.4.10 18 bpp unpacked memory mapping with transparency bit, rgb 6:6:6 44.6.4.11 18 bpp packed memory mapping with transparency bit, rgb 6:6:6 44.6.4.12 19 bpp unpacked memory mapping with transparency bit, rgb 1:6:6:6 44.6.4.13 19 bpp packed memory mapping with transparency bit, argb 1:6:6:6 table 44-16. 18 bpp unpacked memory mapping, little endian organization mem addr 0x3 0x2 0x1 0x0 bit 313029282726252423222120191817161514131211109876543210 pixel 18 bpp r0[5:0] g0[5:0] b0[5:0] table 44-17. 18 bpp packed memory mapping, little endian organization at address 0x0, 0x1, 0x2, 0x3 mem addr 0x3 0x2 0x1 0x0 bit 313029282726252423222120191817161514131211109876543210 pixel 18 bpp g1[1:0] b1[5:0] r0[5:0] g0[5:0] b0[5:0] table 44-18. 18 bpp packed memory mapping, little endian organization at address 0x4, 0x5, 0x6, 0x7 mem addr 0x7 0x6 0x5 0x4 bit 313029282726252423222120191817161514131211109876543210 pixel 18 bpp r2[3:0] g2[5:0] b2[5:0] r1[5:2] g1[5:2] table 44-19. 18 bpp packed memory mapping, little endian organization at address 0x8, 0x9, 0xa, 0xb mem addr 0xb 0xa 0x9 0x8 bit 313029282726252423222120191817161514131211109 8 7 6 5 4 3 2 1 0 pixel 18 bpp g4[1:0] b4[5:0] r3[5:0] g3[5:0] b3[3:0] r2[5:4] table 44-20. 19 bpp unpacked memory mapping, little endian organization mem addr 0x3 0x2 0x1 0x0 bit 313029282726252423222120191817161514131211109876543210 pixel 19 bpp a0 r0[5:0] g0[5:0] b0[5:0] table 44-21. 19 bpp packed memory mapping, little endian organization at address 0x0, 0x1, 0x2, 0x3 mem addr 0x3 0x2 0x1 0x0 bit 313029282726252423222120191817161514131211109876543210 pixel 19 bpp g1[1:0] b1[5:0] a0 r0[5:0] g0[5:0] b0[5:0]
996 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 996 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.6.4.14 24 bpp unpacked memory mapping, rgb 8:8:8 44.6.4.15 24 bpp packed memory mapping, rgb 8:8:8 44.6.4.16 25 bpp memory mapping, argb 1:8:8:8 table 44-22. 19 bpp packed memory mapping, little endian organization at address 0x4, 0x5, 0x6, 0x7 mem addr 0x7 0x6 0x5 0x4 bit 313029282726252423222120191817161514131211109876543210 pixel 19 bpp r2[3:0] g2[5:0] b2[5:0] a1 r1[5:2] g1[5:2] table 44-23. 19 bpp packed memory mapping, little endian organization at address 0x8, 0x9, 0xa, 0xb mem addr 0xb 0xa 0x9 0x8 bit 313029282726252423222120191817161514131211109876543210 pixel 19 bpp g4[1:0] b4[5:0] a3 r3[5:0] g3[5:0] b3[3:0] r2[5:4] table 44-24. 24 bpp memory mapping, little endian organization mem addr 0x3 0x2 0x1 0x0 bit 313029282726252423222120191817161514131211109876543210 pixel 24 bpp r0[7:0] g0[7:0] b0[7:0] table 44-25. 24 bpp packed memory mapping, little endian organization at address 0x0, 0x1, 0x2, 0x3 mem addr 0x3 0x2 0x1 0x0 bit 313029282726252423222120191817161514131211109876543210 pixel 24 bpp b1[7:0] r0[7:0] g0[7:0] b0[7:0] table 44-26. 24 bpp packed memory mapping, little endian organization at address 0x4, 0x5, 0x6, 0x7 mem addr 0x7 0x6 0x5 0x4 bit 313029282726252423222120191817161514131211109876543210 pixel 24 bpp g2[7:0] b2[7:0] r1[7:0] g1[7:0] table 44-27. 25 bpp memory mapping, little endian organization mem addr 0x3 0x2 0x1 0x0 bit 313029282726252423222120191817161514131211109876543210 pixel 25 bpp a0 r0[7:0] g0[7:0] b0[7:0]
997 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 997 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.6.4.17 32 bpp memory mapping, argb 8:8:8:8 44.6.4.18 32 bpp memory mapping, rgba 8:8:8:8 table 44-28. 32 bpp memory mapping, little endian organization mem addr 0x3 0x2 0x1 0x0 bit 313029282726252423222120191817161514131211109 8 7 6 5 4 3 2 1 0 pixel 32 bpp a0[7:0] r0[7:0] g0[7:0] b0[7:0] table 44-29. 32 bpp memory mapping, little endian organization mem addr 0x3 0x2 0x1 0x0 bit 313029282726252423222120191817161514131211109876543210 pixel 32 bpp r0[7:0] g0[7:0] b0[7:0] a0[7:0]
998 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 998 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.6.5 output timing generation 44.6.5.1 active display timing mode figure 44-2. active display timing lcd_vsync lcd_hsync lcd_pclk lcd_bias_den lcd_dat[23:0] hsw vsw hbp vbp lcd_vsync lcd_hsync lcd_pclk lcd_bias_den lcd_dat[23:0] hsw hbp hfp ppl lcd_vsync lcd_hsync lcd_pclk lcd_bias_den lcd_dat[23:0] hfp ppl hsw vfp hbp hsw
999 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 999 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 44-3. vertical synchronization timing (part 1) lcd_vsync lcd_hsync lcd_pclk hswv sw hbp vbp vs pdlys = 0 vs pdlye = 0 vsps u = 0 vspho = 0 lcd_vsync lcd_hsync lcd_pclk hswv sw hbp vbp vs pdlys = 1 vs pdlye = 0 vsps u = 0 vspho = 0 lcd_vsync lcd_hsync lcd_pclk hswv sw hbp vbp vs pdlys = 0 vs pdlye = 1 vsps u = 0 vspho = 0 lcd_vsync lcd_hsync lcd_pclk hswv sw hbp vbp vs pdlys = 1 vs pdlye = 1 vsps u = 0 vspho = 0 lcd_vsync lcd_hsync lcd_pclk hswv sw hbp vbp vs pdlys = 1 vs pdlye = 0 vsps u = 1 vspho = 0
1000 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1000 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 44-4. vertical synchronization timing (part 2) lcd_vsync lcd_hsync lcd_pclk hswv sw hbp vbp vs pdlys = 1 vs pdlye = 0 vsps u = 0 vspho = 1 lcd_vsync lcd_hsync lcd_pclk hswv sw hbp vbp vs pdlys = 1 vs pdlye = 0 vsps u = 1 vspho = 1
1001 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1001 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 44-5. disp signal timing diagram lcd_vsync lcd_disp lcd_pclk lcd_hsync vspdlye = 0 vspho = 0 disppol = 0 dispdly = 0 lcd_vsync lcd_disp lcd_pclk lcd_hsync vspdlye = 0 vspho = 0 disppol = 0 dispdly = 0 lcd display off lcd display on lcd display on lcd display off lcd_vsync lcd_disp lcd_pclk lcd_hsync vspdlye = 0 vspho = 0 disppol = 0 dispdly = 1 lcd_vsync lcd_disp lcd_pclk lcd_hsync vspdlye = 0 vspho = 0 disppol = 0 dispdly = 1 lcd display off lcd display on lcd display on lcd display off
1002 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1002 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.6.6 output format 44.6.6.1 active mode output pin assignment table 44-30. active mode output with 24-bit bus interface configuration pin id tft 24 bit tft 18 bit tft 16 bit tft 12 bit lcd_dat[23] r[7] C C C lcd_dat[22] r[6] C C C lcd_dat[21] r[5] C C C lcd_dat[20] r[4] C C C lcd_dat[19] r[3] C C C lcd_dat[18] r[2] C C C lcd_dat[17] r[1] r[5] C C lcd_dat[16] r[0] r[4] C C lcd_dat[15] g[7] r[3] r[4] C lcd_dat[14] g[6] r[2] r[3] C lcd_dat[13] g[5] r[1] r[2] C lcd_dat[12] g[4] r[0] r[1] C lcd_dat[11] g[3] g[5] r[0] r[3] lcd_dat[10] g[2] g[4] g[5] r[2] lcd_dat[9] g[1] g[3] g[4] r[1] lcd_dat[8] g[0] g[2] g[3] r[0] lcd_dat[7] b[7] g[1] g[2] g[3] lcd_dat[6] b[6] g[0] g[1] g[2] lcd_dat[5] b[5] b[5] g[0] g[1] lcd_dat[4] b[4] b[4] b[4] g[0] lcd_dat[3] b[3] b[3] b[3] b[3] lcd_dat[2] b[2] b[2] b[2] b[2] lcd_dat[1] b[1] b[1] b[1] b[1] lcd_dat[0] b[0] b[0] b[0] b[0]
1003 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1003 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7 lcd controller (lcdc) user interface table 44-32. register mapping offset register name access reset 0x00000000 lcd controller configuration re gister 0 lcdc_lcdcfg0 read-write 0x00000000 0x00000004 lcd controller configuration re gister 1 lcdc_lcdcfg1 read-write 0x00000000 0x00000008 lcd controller configuration re gister 2 lcdc_lcdcfg2 read-write 0x00000000 0x0000000c lcd controller configuration re gister 3 lcdc_lcdcfg3 read-write 0x00000000 0x00000010 lcd controller configuration re gister 4 lcdc_lcdcfg4 read-write 0x00000000 0x00000014 lcd controller configuration re gister 5 lcdc_lcdcfg5 read-write 0x00000000 0x00000018 lcd controller configuration re gister 6 lcdc_lcdcfg6 read-write 0x00000000 0x0000001c reserved C C C 0x00000020 lcd controller enable register lcdc_lcden write-only C 0x00000024 lcd controller disable register lcdc_lcddis write-only C 0x00000028 lcd controller status r egister lcdc_lcdsr read-only 0x00000000 0x0000002c lcd controller interrupt enable register lcdc_lcdier write-only - 0x00000030 lcd controller interrupt disab le register lcdc_lcdidr write-only - 0x00000034 lcd controller interrupt mask register lcdc_lcdimr read-only 0x00000000 0x00000038 lcd controller interrupt status register lcdc_lcdisr read-only 0x00000000 0x0000003c reserved C C C 0x00000040 base layer channel enable register lcdc_basecher write-only 0x00000000 0x00000044 base layer channel disable register lcdc_basechdr write-only 0x00000000 0x00000048 base layer channel status register lcdc_basechsr read-only 0x00000000 0x0000004c base layer interrupt enable register lcdc_baseier write-only 0x00000000 0x00000050 base layer interrupt disabled register lcdc_baseidr write-only 0x00000000 0x00000054 base layer interrupt mask register lcdc_baseimr read-only 0x00000000 0x00000058 base layer interrupt status register lcdc_baseisr read-only 0x00000000 0x0000005c base layer dma head register lcdc_basehead read-write 0x00000000 0x00000060 base layer dma address register lcdc_baseaddr read-write 0x00000000 0x00000064 base layer dma control register lcdc_basectrl read-write 0x00000000 0x00000068 base layer dma next register lcdc_basenext read-write 0x00000000 0x0000006c base layer configuration register 0 lcdc_basecfg0 read-write 0x00000000 0x00000070 base layer configuration register 1 lcdc_basecfg1 read-write 0x00000000 0x00000074 base layer configuration register 2 lcdc_basecfg2 read-write 0x00000000 0x00000078 base layer configuration register 3 lcdc_basecfg3 read-write 0x00000000 0x0000007c base layer configuration register 4 lcdc_basecfg4 read-write 0x00000000 0x80-0x3fc reserved C C C 0x400 base clut register 0 (1) lcdc_baseclut0 read-write 0x00000000 ... ... ... ... ... 0x7fc base clut register 255 (1) lcdc_baseclut255
1004 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1004 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 note: 1. the clut registers are located in ram. 0x800-0x1fe4 reserved C C C 0x1fec address size register lcdc_addrsize read-only 0x 0x1ff0 ip name1 register lcdc_ipname1 read-only 0x 0x1ff4 ip name2 register lcdc_ipname2 read-only 0x 0x1ff8 features register lcdc_features read-only 0x 0x1ffc version register lcdc_version read-only 0x table 44-32. register mapping (continued) offset register name access reset
1005 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1005 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.1 lcd controller configuration register 0 name: lcdc_lcdcfg0 address: 0xf8038000 access: read-write reset: 0x00000000 ? clkpol: lcd controller clock polarity 0: data/control signals are launched on the rising edge of the pixel clock. 1: data/control signals are launched on the falling edge of the pixel clock. ? clksel: lcd controller clock source selection 0: the asynchronous output stage of the lcd controller is fed by mck. 1: the asynchronous output state of the lcd controller is fed by 2x mck. ? clkpwmsel: lcd controller pwm clock source selection 0: the slow clock is selected and feeds the pwm module. 1: the system clock is selected and feeds the pwm module. ? cgdisbase: clock gating disable control for the base layer 0: automatic clock gating is enabled for the base layer. 1: clock is running continuously. ? clkdiv: lcd controller clock divider 8 bit width clock divider for pixel clock lcd_pclk. pixel_clock = select ed_clock/(clkdiv+2) where selected_clock is equal to syst em_clock when clksel field is set to 0 and system_clock2x when clksel is set to one. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 clkdiv 15 14 13 12 11 10 9 8 CCCCCCCc g d i sbase 76543210 C C C C clkpwmsel clksel C clkpol
1006 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1006 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.2 lcd controller configuration register 1 name: lcdc_lcdcfg1 address: 0xf8038004 access: read-write reset: 0x00000000 ? hspw: horizontal synchronization pulse width width of the lcd_hsync pulse, given in pixel cl ock cycles. width is (hspw+1) lcd_pclk cycles. ? vspw: vertical synchr onization pulse width width of the lcd_vsync pulse, given in number of lines. width is (vspw+1) lines. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 C C vspw 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 C C hspw
1007 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1007 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.3 lcd controller configuration register 2 name: lcdc_lcdcfg2 address: 0xf8038008 access: read-write reset: 0x00000000 ? vfpw: vertical front porch width this field indicates the number of lines at the end of th e frame. the blanking interval is equal to (vfpw+1) lines. ? vbpw: vertical back porch width this field indicates the number of lines at the beginning of the fr ame. the blanking interval is equal to vbpw lines. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 C C vbpw 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 C C vfpw
1008 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1008 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.4 lcd controller configuration register 3 name: lcdc_lcdcfg3 address: 0xf803800c access: read-write reset: 0x00000000 ? hfpw: horizontal front porch width number of pixel clock cycles inserted at the end of the active line. the interval is equal to (hfpw+1) lcd_pclk cycles. ? hbpw: horizontal back porch width number of pixel clock cycles inserted at the beginning of th e line. the interval is equal to (hbpw+1) lcd_pclk cycles. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 hbpw 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 hfpw
1009 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1009 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.5 lcd controller configuration register 4 name: lcdc_lcdcfg4 address: 0xf8038010 access: read-write reset: 0x00000000 ? rpf: number of active rows per frame number of active lines in the frame. the frame height is equal to (rpf+1) lines. ? ppl: number of pixels per line number of pixels in the frame. the number of active pixels in the frame is equal to (ppl+1) pixels. 31 30 29 28 27 26 25 24 CCCCC r p f 23 22 21 20 19 18 17 16 rpf 15 14 13 12 11 10 9 8 CCCCC p p l 76543210 ppl
1010 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1010 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.6 lcd controller configuration register 5 name: lcdc_lcdcfg5 address: 0xf8038014 access: read-write reset: 0x00000000 ? hspol: horizontal synchronization pulse polarity 0: active high 1: active low ? vspol: vertical synchr onization pulse polarity 0: active high 1: active low ? vspdlys: vertical synchronization pulse start 0: the first active edge of the vertical synchronization puls e is synchronous with the second edge of the horizontal pulse. 1: the first active edge of the vertical synchronization pu lse is synchronous with the fi rst edge of the horizontal pulse. ? vspdlye: vertical synchronization pulse end 0: the second active edge of the vertic al synchronization pulse is synchronous with the second edge of the horizontal pulse. 1: the second active edge of the vertical synchronization pulse is synchronous with the first edge of the horizontal pulse. ? disppol: display signal polarity 0: active high 1: active low ? dither: lcd controller dithering 0: dithering logical unit is disabled. 1: dithering logical unit is activated. ? dispdly: lcd controller displa y power signal synchronization 0: the lcd_disp signal is asserted synchronously with the second active edge of the horizontal pulse. 1: the lcd_disp signal is asserted asynchronously with both edges of the horizontal pulse. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 C C C guardtime 15 14 13 12 11 10 9 8 C C vspho vspsu C C mode 76543210 dispdly dither C disppol vspdlye vspdlys vspol hspol
1011 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1011 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? mode: lcd controller output mode ? vspsu: lcd controller vertical synchr onization pulse setup configuration 0: the vertical synchronization pulse is asse rted synchronously with horizontal pulse edge. 1: the vertical synchronization pulse is asserted one pixel clock cycle before the horizontal pulse. ? vspho: lcd controller vertical sync hronization pulse ho ld configuration 0: the vertical synchronization pulse is asse rted synchronously with horizontal pulse edge. 1: the vertical synchronization pulse is held active one pixel clock cycle after the horizontal pulse. ? guardtime: lcd display guard time number of frames inserted during start up before lcd_disp assertion. number of frames inserted after lcd_disp reset. value name description 0 output_12bpp lcd output mode is set to 12 bits per pixel 1 output_16bpp lcd output mode is set to 16 bits per pixel 2 output_18bpp lcd output mode is set to 18 bits per pixel 3 output_24bpp lcd output mode is set to 24 bits per pixel
1012 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1012 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.7 lcd controller configuration register 6 name: lcdc_lcdcfg6 address: 0xf8038018 access: read-write reset: 0x00000000 ? pwmps: pwm clock prescaler 3-bit value. selects the configuration of the counter prescaler module. the pwmps field decoding is listed below. ? pwmpol: lcd controller pwm signal polarity this bit defines the polarity of the pwm output signal. if set to one, the output pulses are high level (the output will be hig h whenever the value in the counter is less than the value cval) if set to zero, the output pulses are low level. ? pwmcval: lcd controller pwm compare value pwm compare value. used to adjust the analog value obtained after an external filter to control the contrast of the display. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 pwmcval 76543210 C C C pwmpol C pwmps value name description 0 0 0 div_1 the counter advances at a rate of fcounter = fpwm_selected_clock 0 0 1 div_2 the counter advances at a rate of fcounter = fpwm_selected_clock/2 0 1 0 div_4 the counter advances at a rate of fcounter = fpwm_selected_clock/4 0 1 1 div_8 the counter advances at a rate of fcounter = fpwm_selected_clock/8 1 0 0 div_16 the counter advances at a rate of fcounter = fpwm_selected_clock/16 1 0 1 div_32 the counter advances at a of rate fcounter = fpwm_selected_clock/32 1 1 0 div_64 the counter advances at a of rate fcounter = fpwm_selected_clock/64
1013 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1013 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.8 lcd controller enable register name: lcdc_lcden address: 0xf8038020 access: write reset: 0x00000000 ? clken: lcd controller pixel clock enable 0: writing this field to zero has no effect. 1: when set to one the pixel clock logical unit is activated. ? syncen: lcd controller horizontal and vertical synchronization enable 0: writing this field to zero has no effect. 1: when set to one, both horizontal and vertical synchr onization (lcd_vsync and lcd_hsync) signals are generated. ? dispen: lcd controller disp signal enable 0: writing this field to zero has no effect. 1: when set to one, lcd_disp signals is generated. ? pwmen: lcd controller pu lse width modulation enable 0: writing this field to zero has no effect. 1: when set to one, the pwm is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 C C C C pwmen dispen syncen clken
1014 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1014 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.9 lcd controller disable register name: lcdc_lcddis address: 0xf8038024 access: write reset: 0x00000000 ? clkdis: lcd controller pixel clock disable 0: no effect. 1: disable the pixel clock. ? syncdis: lcd controller horizontal and vertical synchronization disable 0: no effect. 1: disable the synchronization signals after the end of the frame. ? dispdis: lcd controller disp signal disable 0: no effect. 1: disable the disp signal. ? pwmdis: lcd controller pulse width modulation disable 0: no effect. 1: disable the pulse width modulation signal. ? clkrst: lcd controller clock reset 0: no effect. 1: reset the pixel clock generator module. the pixel clock duty cycle may be violated. ? syncrst: lcd controller horizontal and vertical synchronization reset 0: no effect. 1: reset the timing engine. both horizontal and vertical pulse width are violated. ? disprst: lcd controller disp signal reset 0: no effect. 1: reset the disp signal. ? pwmrst: lcd controller pwm reset 0: no effect. 1: reset the pwm module, the duty cycle may be violated. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 C C C C pwmrst disprst syncrst clkrst 76543210 C C C C pwmdis dispdis syncdis clkdis
1015 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1015 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.10 lcd controller status register name: lcdc_lcdsr address: 0xf8038028 access: read-only reset: 0x00000000 ? clksts: clock status 0: pixel clock is disabled. 1: pixel clock is running. ? lcdsts: lcd controller synchronization status 0: timing engine is disabled. 1: timing engine is running. ? dispsts: lcd controller disp signal status 0: disp is disabled. 1: disp signal is activated. ? pwmsts: lcd controll er pwm signal status 0: pwm is disabled. 1: pwm signal is activated. ? sipsts: synchronization in progress 0: clock domain synchronization is terminated. 1: a double domain synchronization is in progress, acce ss to the lcdc_lcden and lcdc_lcddis registers has no effect. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 C C C sipsts pwmsts dispsts lcdsts clksts
1016 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1016 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.11 lcd controller interrupt enable register name: lcdc_lcdier address: 0xf803802c access: write-only reset: 0x00000000 ? sofie: start of frame interrupt enable register 0: no effect. 1: enable the interrupt. ? disie: lcd disable interrupt enable register 0: no effect. 1: enable the interrupt. ? dispie: power up/down sequence terminated interrupt enable register 0: no effect. 1: enable the interrupt. ? fifoerrie: output fifo error interrupt enable register 0: no effect. 1: enable the interrupt. ? baseie: base layer interrupt enable register 0: no effect. 1: enable the interrupt. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCC baseie 76543210 C C C fifoerrie C dispie disie sofie
1017 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1017 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.12 lcd controller in terrupt disable register name: lcdc_lcdidr address: 0xf8038030 access: write-only reset: 0x00000000 ? sofid: start of frame interrupt disable register 0: no effect. 1: disable the interrupt. ? disid: lcd disable interrupt disable register 0: no effect. 1: disable the interrupt. ? dispid: power up/down sequence terminated interrupt disable register 0: no effect. 1: disable the interrupt. ? fifoerrid: output fifo error interrupt disable register 0: no effect. 1: disable the interrupt. ? baseid: base layer in terrupt disable register 0: no effect. 1: disable the interrupt. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCb a s e i d 76543210 C C C fifoerrid C dispid disid sofid
1018 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1018 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.13 lcd controller interrupt mask register name: lcdc_lcdimr address: 0xf8038034 access: read-only reset: 0x00000000 ? sofim: start of frame interrupt mask register 0: interrupt source is disabled. 1: interrupt source is enabled. ? disim: lcd disable interrupt mask register 0: interrupt source is disabled. 1: interrupt source is enabled. ? dispim: power up/down sequence terminated interrupt mask register 0: interrupt source is disabled. 1: interrupt source is enabled. ? fifoerrim: output fifo error interrupt mask register 0: interrupt source is disabled. 1: interrupt source is enabled. ? baseim: base layer interrupt mask register 0: interrupt source is disabled. 1: interrupt source is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCC baseim 76543210 C C C fifoerrim C dispim disim sofim
1019 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1019 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.14 lcd controller interrupt status register name: lcdc_lcdisr address: 0xf8038038 access: read-only reset: 0x00000000 ? sof: start of frame interrupt status register when set to one this flag indicates that a start of frame event has been detected. this flag is reset after a read operation. ? dis: lcd disable interrupt status register when set to one this flag indicates that the horizontal and vertical timing generator has been successfully disabled. this flag is reset after a read operation. ? disp: power-up/power-down sequence terminated interrupt status register when set to one this flag indicates whether the power-up sequence or power-down sequence has terminated. this flag is reset after a read operation. ? fifoerr: output fifo error when set to one this flag indicates that an underflow occurs in the output fifo. this flag is reset after a read operation. ? base: base layer raw interrupt status register when set to one this flag indi cates that a ba se layer interrupt is pending. this flag is reset as soon as the baseisr register is read. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCb a s e 76543210 C C C fifoerr C disp dis sof
1020 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1020 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.15 base layer channel enable register name: lcdc_basecher address: 0xf8038040 access: write-only reset: 0x00000000 ? chen: channel enable register 0: no effect. 1: enable the dma channel. ? updateen: update overlay attributes enable register 0: no effect. 1: update windows attributes on the next start of frame. ? a2qen: add head pointer enable register write this field to one to add the head pointer to the descriptor list. this field is reset by hardware as soon as the head reg - ister is added to the list. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCa 2 q e nu p d a t e e nc h e n
1021 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1021 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.16 base layer channel disable register name: lcdc_basechdr address: 0xf8038044 access: write-only reset: 0x00000000 ? chdis: channel disable register when set to one this field disables the layer at the end of the current frame. the frame is completed. ? chrst: channel reset register when set to one this field resets the layer immediately. the frame is aborted. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCc h r s t 76543210 CCCCCCCc h d i s
1022 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1022 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.17 base layer channel status register name: lcdc_basechsr address: 0xf8038048 access: read-only reset: 0x00000000 ? chsr: channel status register when set to one this field disables the layer at the end of the current frame. ? updatesr: update overlay attributes in progress when set to one this bit indicate s that the overlay attributes w ill be updated on the next frame. ? a2qsr: add to queue pending register when set to one this bit indicates th at the head pointer is still pending. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCa 2 q s ru p d a t e s rc h s r
1023 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1023 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.18 base layer interrupt enable register name: lcdc_baseier address: 0xf803804c access: write-only reset: 0x00000000 ? dma: end of dma transfer interrupt enable register 0: no effect. 1: interrupt source is enabled. ? dscr: descriptor loaded interrupt enable register 0: no effect. 1: interrupt source is enabled. ? add: head descriptor loaded interrupt enable register 0: no effect. 1: interrupt source is enabled. ? done: end of list interrupt enable register 0: no effect. 1: interrupt source is enabled. ? ovr: overflow interrupt enable register 0: no effect. 1: interrupt source is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 C ovr done add dscr dma C C
1024 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1024 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.19 base layer interrupt disable register name: lcdc_baseidr address: 0xf8038050 access: write-only reset: 0x00000000 ? dma: end of dma transfer interrupt disable register 0: no effect. 1: interrupt source is disabled. ? dscr: descriptor loaded interrupt disable register 0: no effect. 1: interrupt source is disabled. ? add: head descriptor loaded interrupt disable register 0: no effect. 1: interrupt source is disabled. ? done: end of list interrupt disable register 0: no effect. 1: interrupt source is disabled. ? ovr: overflow interrupt disable register 0: no effect. 1: interrupt source is disabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 C ovr done add dscr dma C C
1025 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1025 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.20 base layer interrupt mask register name: lcdc_baseimr address: 0xf8038054 access: read-only reset: 0x00000000 ? dma: end of dma transfer interrupt mask register 0: interrupt source is disabled. 1: interrupt source is enabled. ? dscr: descriptor loaded interrupt mask register 0: interrupt source is disabled. 1: interrupt source is enabled. ? add: head descriptor loaded interrupt mask register 0: interrupt source is disabled. 1: interrupt source is enabled. ? done: end of list interrupt mask register 0: interrupt source is disabled. 1: interrupt source is enabled. ? ovr: overflow interrupt mask register 0: interrupt source is disabled. 1: interrupt source is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 C ovr done add dscr dma C C
1026 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1026 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.21 base layer interrupt status register name: lcdc_baseisr address: 0xf8038058 access: read-only reset: 0x00000000 ? dma: end of dma transfer when set to one this flag indicates that an end of transfer has been detected. this flag is reset after a read operation. ? dscr: dma descriptor loaded when set to one this flag indicates that a descriptor has been loaded successfully. this flag is reset after a read operation. ? add: head descriptor loaded when set to one this flag indicates that the descriptor pointed to by the head register has been loaded successfully. this flag is reset after a read operation. ? done: end of list detected when set to one this flag indicates that an end of list condi tion has occurred. this flag is reset after a read operation. ? ovr: overflow detected when set to one this flag indicates that an overflow occurred. this flag is reset after a read operation. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 C ovr done add dscr dma C C
1027 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1027 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.22 base layer head register name: lcdc_basehead address: 0xf803805c access: read-write reset: 0x00000000 ? head: dma head pointer the head pointer points to a new descriptor. 31 30 29 28 27 26 25 24 head 23 22 21 20 19 18 17 16 head 15 14 13 12 11 10 9 8 head 76543210 head C C
1028 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1028 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.23 base layer address register name: lcdc_baseaddr address: 0xf8038060 access: read-write reset: 0x00000000 ? addr: dma transfer start address frame buffer base address. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr
1029 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1029 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.24 base layer control register name: lcdc_basectrl address: 0xf8038064 access: read-write reset: 0x00000000 ? dfetch: transfer descriptor fetch enable 0: transfer descriptor fetch is disabled. 1: transfer descriptor fetch is enabled. ? lfetch: lookup table fetch enable 0: lookup table dma fetch is disabled. 1: lookup tabled dma fetch is enabled. ? dmaien: end of dma transfer interrupt enable 0: dma transfer completed interrupt is enabled. 1: dma transfer completed interrupt is disabled. ? dscrien: descriptor loaded interrupt enable 0: transfer descriptor loaded interrupt is enabled. 1: transfer descriptor loaded interrupt is disabled. ? addien: add head descriptor to queue interrupt enable 0: transfer descriptor added to queue interrupt is enabled. 1: transfer descriptor added to queue interrupt is disabled. ? doneien: end of list interrupt enable 0: end of list interrupt is disabled. 1: end of list interrupt is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 C C doneien addien dscrien dmaien lfetch dfetch
1030 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1030 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.25 base layer next register name: lcdc_basenext address: 0xf8038068 access: read-write reset: 0x00000000 ? next: dma descriptor next address dma descriptor next address, this address must be word aligned. 31 30 29 28 27 26 25 24 next 23 22 21 20 19 18 17 16 next 15 14 13 12 11 10 9 8 next 76543210 next
1031 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1031 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.26 base layer configuration 0 register name: lcdc_basecfg0 address: 0xf803806c access: read-write reset: 0x00000000 ? blen: ahb burst length ? dlbo: defined length burst only for channel bus transaction. 0: undefined length incr burst is used for a burst of 2 and 3 beats. 1: only defined length burst is used (single, incr4, incr8 and incr16). 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCd l b o 76543210 CC b l e n CCCC value name description 0 ahb_single ahb access is started as soon as there is en ough space in the fifo to store one 32-bit data. single, incr, incr4, incr8 and incr16 bursts can be used. incr is used for a burst of 2 and 3 beats. 1 ahb_incr4 ahb access is started as soon as there is enough space in the fifo to store a total amount of four 32-bit data. an ahb incr4 burst is preferred. single, incr and incr4 bursts can be used. incr is used for a burst of 2 and 3 beats. 2 ahb_incr8 ahb access is started as soon as there is enough space in the fifo to stor e a total amount of eight 32-bit data. an ahb incr8 burst is preferred. si ngle, incr, incr4 and incr8 bursts can be used. incr is used for a burst of 2 and 3 beats. 3 ahb_incr16 ahb access is started as soon as there is enoug h space in the fifo to store a total amount of sixteen 32-bit data. an ahb incr16 burst is pref erred. single, incr, in cr4, incr8 and incr16 bursts can be used. incr is used for a burst of 2 and 3 beats.
1032 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1032 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.27 base layer configuration 1 register name: lcdc_basecfg1 address: 0xf8038070 access: read-write reset: 0x00000000 ? cluten: color lookup table enable 0: rgb mode is selected. 1: color lookup table is selected. ? rgbmode: rgb input mode selection ? clutmode: color lookup table input mode selection 31 30 29 28 27 26 25 24 CCC - CCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CC C c l u t m o d e 76543210 rgbmode C C C cluten value name description 0 12bpp_rgb_444 12 bpp rgb 444 1 16bpp_argb_4444 16 bpp argb 4444 2 16bpp_rgba_4444 16 bpp rgba 4444 3 16bpp_rgb_565 16 bpp rgb 565 4 16bpp_trgb_1555 16 bpp trgb 1555 5 18bpp_rgb_666 18 bpp rgb 666 6 18bpp_rgb_666_packed 18 bpp rgb 666 packed 7 19bpp_trgb_1666 19 bpp trgb 1666 8 19bpp_trgb_packed 19 bpp trgb 1666 packed 9 24bpp_rgb_888 24 bpp rgb 888 10 24bpp_rgb_888_packed 24 bpp rgb 888 packed 11 25bpp_trgb_1888 25 bpp trgb 1888 12 32bpp_argb_8888 32 bpp argb 8888 13 32bpp_rgba_8888 32 bpp rgba 8888 value name description 0 1bpp color lookup table mode set to 1 bit per pixel 1 2bpp color lookup table mode set to 2 bits per pixel 2 4bpp color lookup table mode set to 4 bits per pixel 3 8bpp color lookup table mode set to 8 bits per pixel
1033 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1033 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.28 base layer configuration 2 register name: lcdc_basecfg2 address: 0xf8038074 access: read-write reset: 0x00000000 ? xstride: horizontal stride xstride represents the memory offset, in bytes, between two rows of the image memory. 31 30 29 28 27 26 25 24 xstride 23 22 21 20 19 18 17 16 xstride 15 14 13 12 11 10 9 8 xstride 76543210 xstride
1034 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1034 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.29 base layer configuration 3 register name: lcdc_basecfg3 address: 0xf8038078 access: read-write reset: 0x00000000 ? rdef: red default default red color when the base dma channel is disabled. ? gdef: green default default green color when the base dma channel is disabled. ? bdef: blue default default blue color when the base dma channel is disabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 rdef 15 14 13 12 11 10 9 8 gdef 76543210 bdef
1035 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1035 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.30 base layer configuration 4 register name: lcdc_basecfg4 address: 0xf803807c access: read-write reset: 0x00000000 ? dma: use dma data path 0: the default color is used on the base layer. 1: the dma channel retrieves the pixels stream from the memory. ? rep: use replication logic to expand rgb color to 24 bits 0: when the selected pixel depth is less than 24 bpp th e pixel is shifted and least significant bits are set to 0. 1: when the selected pixel depth is less than 24 bpp the pi xel is shifted and the least significant bit replicates the msb. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCr e pd m a 76543210 CCCCCCCC
1036 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1036 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 44.7.31 base clut register x register name: lcdc_baseclutx [x=0..255] address: 0xf8038400 access: read-write reset: 0x00000000 ? bclut: blue color entry this field indicates the 8 bit width blue color of the color lookup table. ? gclut: green color entry this field indicates the 8 bit width green color of the color lookup table. ? rclut: red color entry this field indicates the 8 bit width red color of the color lookup table. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 rclut 15 14 13 12 11 10 9 8 gclut 76543210 bclut
1037 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1037 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 45. advanced encryption standard (aes) 45.1 description the advanced encryption standard (aes) is compliant with the american fips (federal infor- mation processing standard) publication 197 specification. the aes supports all five confidentiality modes of operation for symmetrical key block cipher algorithms (ecb, cbc, ofb, cfb and ctr), as specified in the nist special publication 800- 38a recommendation. it is compatible with all these modes via peripheral dma controller chan- nels, minimizing processor intervention for large buffer transfers. the 128-bit/192-bit/256-bit key is stored in four/six/eight 32-bit registers (aes_keywrx) which are all write-only. the 128-bit input data and initialization vector (for some modes) are each stored in four 32-bit registers (aes_idatar x and aes_ivrx) which are all write-only. as soon as the initialization vector, the input data and the key are configured, the encryp- tion/decryption process may be started. then the encrypted/decrypted data are ready to be read out on the four 32-bit output data registers (aes_odatarx) or through the dma channels. 45.2 embedded characteristics ? compliant with fips publication 197, advanced encryption standard (aes) ? 128-bit/192-bit/256-b it cryptographic key ? 12/14/16 clock cycles encryption/decryption processing time with a 128-bit/192-bit/256-bit cryptographic key ? double input buffer optimizes runtime ? support of the five standard modes of operation specified in the nist special publication 800-38a, recommendation for block cipher modes of operation - methods and techniques: C electronic code book (ecb) C cipher block chaining (cbc) including cbc-mac C cipher feedback (cfb) C output feedback (ofb) C counter (ctr) ? 8-, 16-, 32-, 64- and 128-bit data sizes possible in cfb mode ? last output data mode allows optimized message authentication code (mac) generation ? hardware countermeasures ? connection to dma optimizes data transfers for all operating modes 45.3 product dependencies 45.3.1 power management the aes may be clocked through the power manage ment controller (pmc), so the programmer must first to configure the pmc to enable the aes clock.
1038 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1038 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 45.3.2 interrupt the aes interface has an interrupt line connected to the interrupt controller. handling the aes interrupt requires programming the interrupt controller before configuring the aes. 45.4 functional description the advanced encryption standard (aes) specif ies a fips-approved cryptographic algorithm that can be used to protect electronic data. the aes algorithm is a symmetric block cipher that can encrypt (encipher) and decrypt (decipher) information. encryption converts data to an unintelligible form called ciphertext. decrypting the ciphertext converts the data back into its original form, called plaintext. the cipher bit in the aes mode register (aes_mr) allows sele ction between the encryption and the decryption processes. the aes is capable of usin g cryptographic keys of 128/192/256 bits to encr ypt and decrypt data in blocks of 128 bits. this 128-bit/192-bit/256-bit key is defined in the key registers (aes_keywrx). the input to the encryption processes of the cbc, cfb, and ofb modes includes, in addition to the plaintext, a 128-bit data block called the initialization vector (iv), which must be set in the ini- tialization vector registers (aes_ivrx). the initia lization vector is used in an initial step in the encryption of a message and in the corresponding decryption of the message. the initialization vector registers are also used by the ctr mode to set the counter value. 45.4.1 operation modes the aes supports the following modes of operation: ? ecb: electronic code book ? cbc: cipher block chaining ? ofb: output feedback ? cfb: cipher feedback C cfb8 (cfb where the length of the data segment is 8 bits) C cfb16 (cfb where the length of the data segment is 16 bits) C cfb32 (cfb where the length of the data segment is 32 bits) C cfb64 (cfb where the length of the data segment is 64 bits) C cfb128 (cfb where the length of the data segment is 128 bits) ?ctr: counter the data pre-processing, post-processing and data chaining for the concerned modes are auto- matically performed. refer to the nist special publication 800-38a recommendation for more complete information. these modes are selected by setting the opmod field in the aes mode register (aes_mr). in cfb mode, five data sizes are possible (8, 16, 32, 64 or 128 bits), configurable by means of the cfbs field in the mode register. ( see aes mode register on page 1047. ). table 45-1. peripheral ids instance id aes 29
1039 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1039 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 in ctr mode, the size of the block counter embedded in the module is 16 bits. therefore, there is a rollover after processing 1 megabyte of data. 45.4.2 double input buffer the input data register can be double-buffered to reduce the runtime of large files. this mode allows writing a new message block when the previous message block is being pro- cessed. this is only possible when dma accesses are performed (smod = 0x2). the dualbuff field in aes_mr register must be set to 1 to get a ccess to double buffer. 45.4.3 start modes the smod field in the aes mode register (aes_ mr) allows selection of the encryption (or decryption) start mode. 45.4.3.1 manual mode the sequence is as follows: ? write the 128-bit /192-bit/256-bit key in th e key registers (aes_keywrx). ? write the initialization vector (or counter) in the initialization vector registers (aes_ivrx). note: the initialization vector registers concern all modes except ecb. ? set the bit datrdy (data ready) in the aes interrupt enable register (aes_ier), depending on whether an interrupt is required or not at the end of processing. ? write the data to be encrypted/decrypted in the authorized input data registers (see table 45-2 ). note: in 64-bit cfb mode, writing to aes_idatar2 and aes_idatar3 registers is not allowed and may lead to errors in processing. note: in 32-, 16- and 8-bit cf b modes, writing to aes_idatar1, aes_idatar2 and aes_idatar3 registers is not allowed and may lead to errors in processing. ? set the start bit in the aes control regist er aes_cr to begin th e encryption or the decryption process. table 45-2. authorized input data registers operation mode input data registers to write ecb all cbc all ofb all 128-bit cfb all 64-bit cfb aes_idatar0 and aes_idatar1 32-bit cfb aes_idatar0 16-bit cfb aes_idatar0 8-bit cfb aes_idatar0 ctr all
1040 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1040 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? when processing completes, the bit datr dy in the aes interrupt status register (aes_isr) raises. if an interrupt has been en abled by setting the bit datrdy in aes_ier, the interrupt line of the aes is activated. ? when the software reads one of the output data registers (aes_odatarx), the datrdy bit is automatically cleared. 45.4.3.2 auto mode the auto mode is similar to the manual one, except that in this mode, as soon as the correct number of input data registers is written, processing is automatically started without any action in the control register. 45.4.4 dma mode the dma controller can be used in association with the aes to perform an encryption/decryp- tion of a buffer without any action by the software during processing. the smod field of the aes_mr must be set to 0x2 and the dma must be configured with non incremental addresses. the start address of any tr ansfer descriptor must be se t to aes_idatar0 register. the dma chunk size configuration depends on the aes mode of operation and is listed in table 45-3 "dma data transfer type for the different operation modes" . when writing data to aes with a first dma channel, data are first fetched from a memory buffer (source data). it is recommended to configure the size of source data to words even for cfb modes. on the contrary, the destination data size depends on the mode of operation. when reading data from the aes with th e second dma channel, the sour ce data is the data read from aes and data destination is the me mory buffer. in this case, so urce data size depends on the aes mode of operation and is listed in table 45-3 . . 45.4.5 last output data mode this mode is used to generate cryptographi c checksums on data (mac ) by means of cipher block chaining encryption algorithm (cbc-mac algorithm for example). table 45-3. dma data transfer type for the different operation modes operation mode chunk size destinat ion/source data transfer type ecb 4 words word cbc 4 words word ofb 4 words word cfb 128-bit 4 words word cfb 64-bit 1 word word cfb 32-bit 1 word word cfb 16-bit 1 word half-word cfb 8-bit 1 word byte ctr 4 words word
1041 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1041 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 after each end of encryption/decryption, the output data are available either on the output data registers for manual and auto mode or at the address specified in the receive buffer pointer for dma mode (see table 45-4 "last output data mode behavior versus start modes" ). the last output data bit (lod) in the aes mode register (aes_mr) allows retrieva l of only the last data of several encryption/decryption processes. therefore, there is no need to define a read buffer in dma mode. this data are only availa ble on the output data registers (aes_odatarx). 45.4.6 manual and auto modes 45.4.6.1 if lod = 0 the datrdy flag is cleared when at least one of the output data registers is read (see figure 45-1 ). figure 45-1. manual and auto modes with lod = 0 if the user does not want to read the output data registers between each encryption/decryption, the datrdy flag will not be clear ed. if the datrdy flag is not cleared, the user cannot know the end of the following encryptions/decryptions. 45.4.6.2 if lod = 1 the datrdy flag is cleared when at least one inpu t data register is written, so before the start of a new transfer (see figure 45-2 ). no more output data register reads are necessary between consecutive encryptions/decryptions. figure 45-2. manual and auto modes with lod = 1 encryption or decryption process read the aes_odatarx write start bit in aes_cr (manual mode) datrdy write aes_idatarx register(s) (auto mode) or write aes_idatarx register(s) write start bit in aes_cr (manual mode) write aes_idatarx register(s) (auto mode) or encryption or decryption process datrdy
1042 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1042 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 45.4.7 dma mode 45.4.7.1 if lod = 0 this mode may be used for all aes operating modes except cbc-mac where lod=1 mode is recommended. the end of the encryption/decryption is notif ied by the end of dma transfer associated to aes_odatarx registers (see figure 45-3 ). 2 channels dma are required, 1 for writing mes- sage blocks to aes_idatarx registers and t he other one to get back the processed from aes_odatarx registers. figure 45-3. dma transfer with lod = 0 45.4.7.2 if lod = 1 this mode is recommen ded to process aes cbc-mac operating mode. enable pdc channels (receive and transmit channels) multiple encryption or decryption processes endrx (or rxbuff) endtx (or txbufel) message fully processed (cipher or decipher) last block can be read write accesses into aes_idatarx read accesses into aes_odatarx datrdy enable pdc channels (receive and transmit channels) multiple encryption or decryption processes endtx (or txbufe) message fully processed (cipher or decipher) mac result can be read write accesses into aes_idatarx message fully transferred enable dma channels associated to aes_idatarx and aes_odatarx multiple encryption or decryption processes btc /channel 1 btc /channel 0 message fully processed (cipher or decipher) last block can be read write accesses into aes_idatarx read accesses into aes_odatarx
1043 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1043 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 the user must first wait for the dma flag (btc = buffer transfer complete) to rise, then for datrdy to ensure that the encryption/decryption is completed (see figure 45-4 ). in this case, no receive buffers are required. the output data are only available on th e output data registers (aes_odatarx). figure 45-4. dma transfer with lod = 1 table 45-4 summarizes the different cases. note: 1. depending on the mode, there are other ways of clearing the datrdy flag. see: section 45.6.6 aes interrupt status register . warning: in dma mode, reading to the output data registers before the last data transfer may lead to unpredictable results. datrdy enable dma channels associated with tdes_idatarx and tdes_odatarx registers multiple encryption or decryption processes btc / channel 0 message fully processed (cipher or decipher) mac result can be read write accesses into aes_idatarx message fully transferred table 45-4. last output data mode behavior versus start modes manual and auto modes dma transfer lod = 0 lod = 1 lod = 0 lod = 1 datrdy flag clearing condition (1) at least one output data register must be read at least one input data register must be written not used managed by the dma encrypted/decrypted data result location in the output data registers in the output data registers not available in the output data registers end of encryption/decryption datrdy datrdy 2 dma flags (btc[n/m]) dma flag (btc[n]) then aes datrdy
1044 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1044 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 45.5 security features 45.5.1 countermeasures the aes also features hardware countermeasures that can be used to make more difficult the unexpected data recovery. these countermeasures can be enabled through the cmtypx field in the aes mode register. this field is write-only, and all changes to it are taken into account if, at the same time, the coun- termeasure key (ckey field) is correc tly written (see aes mode register on page 1047 ). note: enabling countermeasures has an impact on the aes encryption/decryption throughput. by default, all the countermeasures are enabled. the best throughput is achieved with all the countermeasures disabled except cmtyp6 which can be kept enabled. on the other hand, the best protection is achieved with all of them enabled. the loadseed bit in the aes control register (aes_cr) restarts the countermeasures gen- erator to an internal pre-defined value. 45.5.2 unspecified register access detection when an unspecified register ac cess occurs, the urad bit in the interrupt status register (aes_isr) raises. its source is then reported in th e unspecified register access type field (urat). only the last unspecified register access is available through the urat field. several kinds of unspecified register accesses can occur: ? input data register written during the data processing when smod=idatar0_start ? output data register read during data processing ? mode register written during data processing ? output data register read during sub-keys generation ? mode register written during sub-keys generation ? write-only register read access the urad bit and the urat field can only be reset by the swrst bi t in the aes_cr control register.
1045 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1045 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 45.6 advanced encryption standar d (aes) user interface table 45-5. register mapping offset register name access reset 0x00 control register aes_cr write-only C 0x04 mode register aes_mr read-write 0x0 0x08-0x0c reserved CCC 0x10 interrupt enable register aes_ier write-only C 0x14 interrupt disable r egister aes_idr write-only C 0x18 interrupt mask register aes_imr read-only 0x0 0x1c interrupt status register aes_isr read-only 0x0 0x20 key word register 0 aes_keywr0 write-only C 0x24 key word register 1 aes_keywr1 write-only C 0x28 key word register 2 aes_keywr2 write-only C 0x2c key word register 3 aes_keywr3 write-only C 0x30 key word register 4 aes_keywr4 write-only C 0x34 key word register 5 aes_keywr5 write-only C 0x38 key word register 6 aes_keywr6 write-only C 0x3c key word register 7 aes_keywr7 write-only C 0x40 input data register 0 aes_idatar0 write-only C 0x44 input data register 1 aes_idatar1 write-only C 0x48 input data register 2 aes_idatar2 write-only C 0x4c input data register 3 aes_idatar3 write-only C 0x50 output data register 0 aes_odatar0 read-only 0x0 0x54 output data register 1 aes_odatar1 read-only 0x0 0x58 output data register 2 aes_odatar2 read-only 0x0 0x5c output data register 3 aes_odatar3 read-only 0x0 0x60 initialization vector r egister 0 aes_ivr0 write-only C 0x64 initialization vector r egister 1 aes_ivr1 write-only C 0x68 initialization vector r egister 2 aes_ivr2 write-only C 0x6c initialization vector r egister 3 aes_ivr3 write-only C 0x70 - 0xfc reserved CCC
1046 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1046 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 45.6.1 aes control register name: aes_cr address: 0xf000c000 access: write-only ? start: start processing 0: no effect 1: starts manual encryption/decryption process. ? swrst: software reset 0: no effect. 1: resets the aes. a so ftware triggered hardwa re reset of the aes in terface is performed. ? loadseed: random number generator seed loading 0: no effect. 1: restarts the countermeasures generator to an internal pre-defined value. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCl o a d seed 15 14 13 12 11 10 9 8 CCCCCCCs w r s t 76543210 CCCCCCCs t a r t
1047 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1047 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 45.6.2 aes mode register name: aes_mr address: 0xf000c004 access: read-write ? cipher: processing mode 0: decrypts data. 1: encrypts data. ? dualbuff: dual input buffer ? procdly: processing delay the processing time repr esents the number of clock cycle s that the aes needs in order to perform one en cryption/decryp- tion with no countermeasures activated. note: the best performance is achieved with procdly equal to 0. ? smod: start mode values which are not listed in the table must be considered as reserved. if a dma transfer is used, 0x2 must be configured. refer to section 45.4.4 dma mode for more details. 31 30 29 28 27 26 25 24 C C cmtyp6 cmtyp5 cmtyp4 cmtyp3 cmtyp2 cmtyp1 23 22 21 20 19 18 17 16 ckey C cfbs 15 14 13 12 11 10 9 8 lod opmod keysize smod 76543210 procdly dualbuff C C cipher value name description 0x0 inactive aes_idatarx cannot be writt en during processing of previous block. 0x1 active aes_idatarx can be written during processing of previous block when smod = 0x2. it speeds up the overall runtime of large files. value name description 0x0 manual_start manual mode 0x1 auto_start auto mode 0x2 idatar0_start aes_idatar0 access only auto mode processing time 12 procdly 1 + () =
1048 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1048 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? keysize: key size values which are not listed in the table must be considered as reserved. ? opmod: operation mode values which are not listed in the table must be considered as reserved. for cbc-mac operating mode, please set opmod to cbc and lod to 1. ? lod: last output data mode 0: no effect. after each end of encryption/decr yption, the output data will be available eith er on the output data registers (manual and auto modes). in manual and auto modes, the datrdy flag is cleared when at least one of the output data registers is read. 1: the datrdy flag is cleared when at least one of the input data registers is written. no more output data register reads is necessary between consecutive encry ptions/decryptions (see last output data mode on page 1040 ). warning : in dma mode, reading to the output data registers before the last data encryption/decryption process may lead to unpredictable results. ? cfbs: cipher feedback data size values which are not listed in table must be considered as reserved. value name description 0x0 aes128 aes key size is 128 bits 0x1 aes192 aes key size is 192 bits 0x2 aes256 aes key size is 256 bits value name description 0x0 ecb ecb: electronic code book mode 0x1 cbc cbc: cipher block chaining mode 0x2 ofb ofb: output feedback mode 0x3 cfb cfb: cipher feedback mode 0x4 ctr ctr: counter mode (16-bit internal counter) value name description 0x0 size_128bit 128-bit 0x1 size_64bit 64-bit 0x2 size_32bit 32-bit 0x3 size_16bit 16-bit 0x4 size_8bit 8-bit
1049 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1049 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? ckey: countermeasure key this field should be written with the value 0xe to allow cmtypx field changes. if the field is written with a different value, changes ma de through the cmtypx field will not be taken into account. note: ckey field is write-only. ? cmtyp1: countermeasure type 1 0 (noprot_extxkey): counter-me asure type 1 is disabled 1 (prot_extkey): counter-meas ure type 1 is enabled ? cmtyp2: countermeasure type 2 0 (no_pause): counter-measure type 2 is disabled 1 (pause): counter-measure type 2 is enabled ? cmtyp3: countermeasure type 3 0 (no_dummy): counter-measure type 3 is disabled 1 (dummy): counter-measure type 3 is enabled ? cmtyp4: countermeasure type 4 0 (no_restart): counter-measure type 4 is disabled 1 (restart): counter-measure type 4 is enabled ? cmtyp5: countermeasure type 5 0 (no_addaccess): counter-measure type 5 is disabled 1 (addaccess): counter-meas ure type 5 is enabled ? cmtyp6: countermeasure type 6 0 (no_idlecurrent): counter-measure type 6 is disabled 1 (idlecurrent): counter-me asure type 6 is enabled note: all the countermeasures are enabled by default. note: cmtypx fields are write-only and can only be modified if ckey is correctly set.
1050 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1050 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 45.6.3 aes interrupt enable register name: aes_ier address: 0xf000c010 access: write-only ? datrdy: data ready interrupt enable ? urad: unspecified register access detection interrupt enable 0: no effect. 1: enables the corresponding interrupt. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCu r a d 76543210 CCCCCCCd a t r d y
1051 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1051 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 45.6.4 aes interrupt disable register name: aes_idr address: 0xf000c014 access: write-only ? datrdy: data ready interrupt disable ? urad: unspecified register acce ss detection interrupt disable 0: no effect. 1: disables the corresponding interrupt. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCu r a d 76543210 CCCCCCCd a t r d y
1052 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1052 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 45.6.5 aes interrupt mask register name: aes_imr address: 0xf000c018 access: read-only ? datrdy: data ready interrupt mask ? urad: unspecified register access detection interrupt mask 0: the corresponding interrupt is not enabled. 1: the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCu r a d 76543210 CCCCCCCd a t r d y
1053 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1053 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 45.6.6 aes interrupt status register name: aes_isr address: 0xf000c01c access: read-only ? datrdy: data ready 0: output data not valid. 1: encryption or decryption process is completed. datrdy is cleared when a manual encryption/decryption occu rs (start bit in aes_cr) or when a software triggered hardware reset of the aes interface is performed (swrst bit in aes_cr). lod = 0 (aes_mr): in manual and auto mode, the datrdy flag can also be cleared when at least one of the output data registers is read. in dma mode, datrdy is se t and cleared automatically. lod = 1 (aes_mr): in manual and auto mode, the datrdy flag can also be cleared when at least one of the input data registers is written. in dma mode, datrdy is se t and cleared automatically. ? urad: unspecified register access detection status 0: no unspecified register access has been detected since the last swrst. 1: at least one unspecified register access has been detected since the last swrst. urad bit is reset only by the swrst bit in the aes_cr control register. ? urat: unspecified register access: only the last unspecified re gister access type is available through the urat field. urat field is reset only by the swrst bit in the aes_cr control register. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 urat C C C urad 76543210 CCCCCCCd a t r d y value name description 0x0 idr_wr_processing input data re gister written during the data processing w hen smod=0x2 mode. 0x1 odr_rd_processing output data register read during the data processing. 0x2 mr_wr_processing mode register written during the data processing. 0x3 odr_rd_subkgen output data register read during the sub-keys generation. 0x4 mr_wr_subkgen mode register written during the sub-keys generation. 0x5 wor_rd_access write-only register read access.
1054 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1054 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 45.6.7 aes key word register x name: aes_keywrx address: 0xf000c020 access: write-only ? keyw: key word the four/six/eight 32-bit key word registers set the 128-bit/192-bit/256-bit cryptographic key used for encryption/decryption. aes_keywr0 corresponds to the first word of the key and respectively aes_keywr3/aes_keywr5/aes_keywr7 to the last one. these registers are write-only to prevent the key from being read by another application. 31 30 29 28 27 26 25 24 keyw 23 22 21 20 19 18 17 16 keyw 15 14 13 12 11 10 9 8 keyw 76543210 keyw
1055 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1055 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 45.6.8 aes input data register x name: aes_idatarx address: 0xf000c040 access: write-only ? idata: input data word the four 32-bit input data registers set the 128-bit data block used for encryption/decryption. aes_idatar0 corresponds to the first word of the data to be encr ypted/decrypted, and aes_idatar3 to the last one. these registers are write-only to prevent the input data from being read by another application. 31 30 29 28 27 26 25 24 idata 23 22 21 20 19 18 17 16 idata 15 14 13 12 11 10 9 8 idata 76543210 idata
1056 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1056 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 45.6.9 aes output data register x name: aes_odatarx address: 0xf000c050 access: read-only ? odata: output data the four 32-bit output data registers contain the 128-bit data block that has been encrypted/decrypted. aes_odatar0 corresponds to the first word, aes_odatar3 to the last one. 31 30 29 28 27 26 25 24 odata 23 22 21 20 19 18 17 16 odata 15 14 13 12 11 10 9 8 odata 76543210 odata
1057 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1057 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 45.6.10 aes initialization vector register x name: aes_ivrx address: 0xf000c060 access: write-only ? iv: initialization vector the four 32-bit initialization vector registers set the 128-bit in itialization vector data block that is used by some modes of operation as an addit ional initial input. aes_ivr0 corresponds to the first word of the initializati on vector, aes_ivr3 to the last one. these registers are write-only to prevent the initialization vector from being read by another application. for cbc, ofb and cfb modes, the initialization vector corresponds to the initialization vector. for ctr mode, it corresponds to the counter value. note: these registers are not used in ecb mode and must not be written. 31 30 29 28 27 26 25 24 iv 23 22 21 20 19 18 17 16 iv 15 14 13 12 11 10 9 8 iv 76543210 iv
1058 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1058 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12
1059 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 46. secure hash algorithm (sha) 46.1 description the secure hash algorithm (sha) is compliant with the american fips (federal information processing standard) publication 180-2 specification. the 512-bit block of message is respectively stored in 16 x 32-bit registers (sha_idatarx/sha_odatarx) which are all write-only. as soon as the input data is written, the hash processing may be started. the registers compris- ing the block of a padded message must be enter ed consecutively. then the message digest is ready to be read out on the 5 up to 8 x 32-bit output data registers (sha_odatarx) or through the dma channels. 46.2 embedded characteristics ? supports secure hash algorithm (sha1, sha224, sha256) ? compliant with fips publication 180-2 ? configurable processing period: C 85 clock cycles to get a fast sha1 runtime or 209 clock cycles for maximizing bandwidth of other applications C 72 clock cycles to get a fast sha224, sha256 runtime or 194 clock cycles for maximizing bandwidth of other applications ? connection to dma channel capab ilities optimizes data transfers ? double input buffer optimizes runtime 46.3 product dependencies 46.3.1 power management the sha may be clocked through the power management controller (pmc), so the programmer must first configure the pmc to enable the sha clock. 46.3.2 interrupt the sha interface has an interrupt line connected to the interrupt controller. handling the sha interrupt requires programming the interrupt controller before configuring the sha. table 46-1. peripheral ids instance id sha 27
1060 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 46.4 functional description the secure hash algorithm (sha) module requires a padded message according to fips180-2 specification. the first block of the message must be indicated to the module by a specific com- mand. the sha module produces a n-bit mess age digest each time a block is written and processing period ends. n is 160 for sha1, 224 for sha224, 256 for sha256. 46.4.1 sha algorithm the module can process sha1, sha224, sha256 by means of a configuration field in the sha_mr register. 46.4.2 processing period the processing period can be configured. the short processing period allows to allocate bandwidth to the sha module whereas the long processing period allocates more bandwidth on the system bus to other applications (example: dma channels not associated with sha). in sha1 mode, the shortest processing period is 85 clock cycles + 2 clock cycles for start com- mand synchronization. the longest period is 209 clock cycles + 2 clock cycles. in sha256 and sha224 mode, the shortest proc essing period is 72 clock cycles + 2 clock cycles for start command synchronization. the l ongest period is 194 clock cycles + 2 clock cycles. 46.4.3 double input buffer the input data register can be double-buffered to reduce the runtime of large files. this mode allows to write a new message block while the previous message block is being pro- cessed. this is only possible when dma accesses are performed (smod=0x2). the dualbuff field in sha_mr register must be set to 1 to get access to double buffer. 46.4.4 start modes the smod field in the sha mode register (sha_mr) is used to select the hash processing start mode. 46.4.4.1 manual mode the sequence is as follows: ? set the bit datrdy (data ready) in the sha interrupt enable register (sha_ier), depending on whether an interrupt is required or not at the end of processing. ? for the first block of a message, the first command must be set by writing a 1 into the corresponding bit of the control register (sha_cr). for the other blocks, there is nothing to write in this control register. ? write the block to be processed in the input data registers. ? set the start bit in the sha control register sha_cr to begin the processing. ? when the processing completes, the bit datr dy in the sha interrupt status register (sha_isr) raises. if an interrupt has been enabled by setting the bit datrdy in sha_ier, the interrupt line of the sha is activated.
1061 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 ? repeat the write procedure for each block, start procedure and wait for the interrupt procedure up to the last block of the entire message. each time the start procedure is complete, the datrdy flag is cleared. ? after the last block is processed (datrdy flag is set, if an interrupt has been enabled by setting the bit datrdy in sha_ier, the interrupt line of the sha is activated), read the message digest in the output data registers. the datrdy flag is automatically cleared when reading the sha_odatarx registers. 46.4.4.2 auto mode auto mode is similar to manual mode, except that in this mode, as soon as the correct number of input data registers is written, processing is automatically started without any action in the con- trol register. 46.4.4.3 dma mode the dma can be used in association with the sha to perform the algorithm on a complete mes- sage without any action by th e software during processing. the smod field of the sha_mr must be set to 0x2. the dma must be configured with non incremental addresses. the start address of any transfer descriptor must be set to point to the sha_idatar0 register. the dma chunk size must be set to transfer, for each trigger request, 16 words of 32 bits when processing sha1/sha256 algorithms or 32 words of 32 bits when sha384/sha512 are being used. figure 46-1. enable dma channels 46.4.4.4 sha register endianism in arm processor based products, the ahb bus an d processors manipulate data in little endian form. however, following the protocol of fips 180-2 specification, data is collected, processed and stored by the sha module in a big endian form. the data presented to the sha module (written to sha_idataxr) must be in little endian form. the data read from the sha module (read from sha_odataxr) will be in little endian form. the sha interface automatically converts into big endian format words that are presented into little endian. likewise, the sha interface returns hash results into little endian format even if the internal processing is big endian. datrdy enable dma channels associated with sha_idatarx registers message processing (multiple block) btc/ channel 0 message fully processed sha result can be read write accesses into sha_idatarx message fully transferred
1062 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 managing how data is presented to the sha registers should be managed by software. as a clarification of this process consider the following example. if the first 64 bits of a message (according to fips180-2, i.e. big endian format) to be processed is 0xcafe_dede_0123_4567 then the sha_idata0r and sha_idata1r registers should be written with the following pattern: ? sha_idata0r = 0xefac ? sha_idata1r = 0xeded in a little endian system, the message starting with pattern 0xcafe_dede_0123_4567 will be stored into memories as follows: C 0xca stored at initial offset (for example 0x00), C then 0xfe stored at initial offset + 1 (i.e. 0x01), C 0xde stored at initial offset + 2 (i.e. 0x02), C 0xde stored at initial offset +3 (i.e. 0x03). lets assume the message is received through a serial to parallel communication channel, the first received character is 0xca and stored at first memory location (initial offset), second octet being 0xfe is stored at initial offset + 1. when reading on a 32-bit little endian system bus, the first word read back from system mem- ory is 0x_dede_feca. when the sha_odataxr registers are read, the hash result is organized in little endian for- mat, allowing system memory storage in the same format as the message. taking an example from the fips 180-2 specification appendix b.1, the endianism conversion can be observed. for this example, the 512-bit message is: 0x6162638000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000018 and the expected sha-256 result is: 0xba7816bf_8f01cfea_414140de_5dae2223_b00361a3_96177a9c_b410ff61_f20015ad if the message has not already been stored in the system memory, the first step is to convert the input message to little endian before writing to the sha_idataxr registers. this would result in a write of: sha_idata0r = 0x80636261...... sha_idata15r = 0x18000000 the data in the output message digest registers, sha_odataxr, contain sha_odataxr = 0xbf1678ba... sha_odata7r = 0xad1500f2 which is the little endian format of 0xba7816bf,..., 0xf20015ad. reading sha_odata0r to sha_odata1r and stor ing into a little endian memory system forces hash results to be stored in the same format as the message. when the output message is read, the user can convert back to big endian for a resulting mes- sage value of: 0xba7816bf_8f01cfea_414140de_5dae2223_b00361a3_96177a9c_b410ff61_f20015ad
1063 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 46.4.5 security features when an unspecified register ac cess occurs, the urad bit in the interrupt status register (sha_isr) raises. its source is then reported in the unspecified register access type field (urat). only the last unspecified register access is available through the urat field. several kinds of unspecified register accesses can occur: ? input data register written during the data processing in dma mode ? output data register read during the data processing ? mode register written during the data processing ? write-only register read access the urad bit and the urat field can only be reset by the swrst bit in the sha_cr control register.
1064 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 46.5 secure hash algorithm (sha) user interface table 46-2. register mapping offset register name access reset 0x00 control register sha_cr write-only C 0x04 mode register sha_mr read-write 0x1 0x08-0x0c reserved CCC 0x10 interrupt enable register sha_ier write-only C 0x14 interrupt disable register sha_idr write-only C 0x18 interrupt mask register sha_imr read-only 0x0 0x1c interrupt status register sha_isr read-only 0x0 0x20-0x3c reserved C 0x40 input data 0 register sha_idatar0 write-only C ... ... ... ... ... 0x7c input data 15 register sha_idatar15 write-only C 0x80 output data 0 register sha_odatar0 read-only 0x0 ... ... ... ... ... 0x9c output data 7 register sha_odatar7 read-only 0x0 0x94-0xfc reserved CCC
1065 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 46.5.1 sha control register name: sha_cr address: 0xf0014000 access: write-only ? start: start processing 0: no effect 1: starts manual hash algorithm process ? first: first block of a message 0: no effect 1: indicates that the next block to process is the first one of a message. ? swrst: software reset 0: no effect. 1: resets the sha. a software triggered hardware reset of the sha interface is performed. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCs w r s t 76543210 CCCf i r s tCCCs t a r t
1066 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 46.5.2 sha mode register name: sha_mr address: 0xf0014004 access: read-write ? smod: start mode values which are not listed in table must be considered as reserved. if a dma transfer is used, either 0x1 or 0x2 must be configured. refer to dma mode on page 1061 for more details. ? procdly: processing delay when sha1 algorithm is processed, runtime period is either 85 or 209 clock cycles. when sha256 or sha224 algorithm is processed, runtime period is either 72 or 194 clock cycles. ? algo: sha algorithm. values which are not listed in table must be considered as reserved. ? dualbuff: dual input buffer 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCd u a l b u f f 15 14 13 12 11 10 9 8 CC Ca l g o 76543210 C procdly C C smod value name description 0x0 manual_start manual mode 0x1 auto_start auto mode 0x2 idatar0_start sha_idatar0 access only auto mode value name description 0x0 shortest sha processing runtime is the shortest one 0x1 longest sha processing runtime is the longest one value name description 0x0 sha1 sha1 algorithm processed 0x1 sha256 sha256 algorithm processed 0x4 sha224 sha224 algorithm processed value name description 0x0 inactive sha_idatarx and sha_iodatarx cannot be written during processing of previous block. 0x1 active sha_idatarx and sha_iodatarx can be written during processing of previous block when smod=0x2. it speeds up the overall runtime of large files.
1067 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 46.5.3 sha interrupt enable register name: sha_ier address: 0xf0014010 access: write-only ? datrdy: data ready interrupt enable ? urad: unspecified register access detection interrupt enable 0: no effect. 1: enables the corresponding interrupt. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCu r a d 76543210 CCCCCCCd a t r d y
1068 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 46.5.4 sha interrupt disable register name: sha_idr address: 0xf0014014 access: write-only ? datrdy: data ready interrupt disable ? urad: unspecified register acce ss detection interrupt disable 0: no effect. 1: disables the corresponding interrupt. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCu r a d 76543210 CCCCCCCd a t r d y
1069 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 46.5.5 sha interrupt mask register name: sha_imr address: 0xf0014018 access: read-only ? datrdy: data ready interrupt mask ? urad: unspecified register access detection interrupt mask 0: the corresponding interrupt is not enabled. 1: the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCu r a d 76543210 CCCCCCCd a t r d y
1070 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 46.5.6 sha interrupt status register name: sha_isr address: 0xf001401c access: read-only ? datrdy: data ready 0: output data is not valid. 1: 512-bit block process is completed. datrdy is cleared when a manual process occurs (start bi t in sha_cr) or when a software triggered hardware reset of the sha interface is performed (swrst bit in sha_cr). ? urad: unspecified register access detection status 0: no unspecified register access has been detected since the last swrst. 1: at least one unspecified register access has been detected since the last swrst. urad bit is reset only by the swrst bit in the sha_cr control register. urat field indicates the unspecified access type. ? urat: unspecified re gister access type only the last unspecified re gister access type is available through the urat field. urat field is reset only by the swrst bit in the sha_cr control register. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 urat C C C urad 76543210 CCCCCCCd a t r d y value description 0x0 input data register 0 to 15 written during the data processing in dma mode. (urad=0x1 and urat=0x0 can occur only if dualbuff is cleared in sha_mr) 0x1 output data register read during the data processing. 0x2 mode register written during the data processing. 0x3 write-only register read access.
1071 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 46.5.7 sha input data x register name: sha_idatarx [x=0..15] address: 0xf0014040 access: write-only ? idata: input data the 32-bit input data registers allow to load the data block used for hash processing. these registers are write-only to prevent the input data from being read by another application. sha_idatar0 corresponds to the first word of the block, sha_ idatar15 to the last word of the last block in case sha algorithm is set to sha1,sha224,sha256. 31 30 29 28 27 26 25 24 idata 23 22 21 20 19 18 17 16 idata 15 14 13 12 11 10 9 8 idata 76543210 idata
1072 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 46.5.8 sha output data x register name: sha_odatarx [x=0..15] address: 0xf0014080 access: read only ? odata: output data these registers can be used to read the resulting message digest. when sha processing is in progress, these registers return 0x0000. sha_odata0r corresponds to the first word of message digest; sha_odata5r to the last one in sha1 mode, sha_odata6r in sha224, sha_odata7r in sha256. when sha224 is selected, the content of sha_odata7r must not be taken into account. 31 30 29 28 27 26 25 24 odata 23 22 21 20 19 18 17 16 odata 15 14 13 12 11 10 9 8 odata 76543210 odata
1073 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1073 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 47. true random numb er generator (trng) 47.1 description the true random number generator (trng) passes the american nist special publication 800-22 and diehard random tests suites. as soon as the trng is enabled (trng_ctrl register), the generator provides one 32-bit value every 84 clock cycles. interrupt trng_int can be enabled through the trng_ier register (respectively disabled in trng_idr). this interrupt is set when a new random value is available and is cleared when the status register is read (trng_sr register). the flag datrdy of the status register (trng_isr) is set when the random data is ready to be read out on the 32-bit output data register (trng_odata). the normal mode of operation checks that the status register flag equals 1 before reading the output data register when a 32-bit random value is required by the software application. 47.2 embedded characteristics ? passed nist special publication 800-22 tests suite ? passed diehard random tests suite ? provides a 32-bit random number every 84 clock cycles figure 47-1. trng data generation sequence 84 clock cycles 84 clock cycles 84 clock cycles read trng_isr read trng_odata read trng_isr read trng_odata clock trng_int trng_cr enable
1074 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1074 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 47.3 true random number genera tor (trng) user interface table 47-1. register mapping offset register name access reset 0x00 control register trng_cr write-only C 0x10 interrupt enable register trng_ier write-only C 0x14 interrupt disable register trng_idr write-only C 0x18 interrupt mask register trng_imr read-only 0x0000_0000 0x1c interrupt status r egister trng_isr read-only 0x0000_0000 0x50 output data register trng_odata read-only 0x0000_0000
1075 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1075 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 47.3.1 trng control register name: trng_cr address: 0xf8048000 access: write-only ? enable: enables the trng to provide random values 0 = disables the trng. 1 = enables the trng. ? key: security key key = 0x524e47 (rng in ascii) this key is to be written when the enable bit is set or cleared. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 key 15 14 13 12 11 10 9 8 key 76543210 CCCCCCCe n a b l e
1076 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1076 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 47.3.2 trng interrupt enable register name: trng_ier address: 0xf8048010 access: write-only ? datrdy: data ready interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCCd a t r d y
1077 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1077 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 47.3.3 trng interrupt disable register name: trng_idr address: 0xf8048014 access: write-only ? datrdy: data ready interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCCd a t r d y
1078 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1078 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 47.3.4 trng interrupt mask register name: trng_imr address: 0xf8048018 reset: 0x0000_0000 access: read-only ? datrdy: data ready interrupt mask 0 = the corresponding interrupt is not enabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCCd a t r d y
1079 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1079 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 47.3.5 trng interrupt status register name: trng_isr address: 0xf804801c reset: 0x0000_0000 access: read-only ? datrdy: data ready 0 = output data is not valid or trng is disabled. 1 = new random value is completed. datrdy is cleared when this register is read. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCC 76543210 CCCCCCCd a t r d y
1080 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 1080 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 47.3.6 trng output data register name: trng_odata address: 0xf8048050 reset: 0x0000_0000 access: read-only ? odata: output data the 32-bit output data register contains the 32-bit random data. 31 30 29 28 27 26 25 24 odata 23 22 21 20 19 18 17 16 odata 15 14 13 12 11 10 9 8 odata 76543210 odata
1081 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 48. electrical characteristics 48.1 absolute maximum ratings 48.2 dc characteristics the following characteristics are applicable to the operating temperature range: t a = -40c to +85c, unless otherwise specified. table 48-1. absolute maximum ratings* operating temperature (industrial)................-40 c to + 85 c *notice: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational se ctions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reli- ability. junction temperature...................................................125c storage temperature...................................-60c to + 150c voltage on input pins with respect to ground......-0.3v to vddio+0.3v(+ 4v max) maximum operating voltage (vddcore and vddpll) .............. ............................ ...1.2v (vddiom, vddiopx, vddosc, vddana, vddnf, vddusb, vddfuse, and vddbu) ....... ..........4.0v total dc output current on all i/o lines.....................350 ma table 48-2. dc characteristics symbol parameter conditions min typ max units v vddcore dc supply core 0.9 1.0 1.1 v v vddcorerip vddcore ripple 50 mvrms v vddbu dc supply backup 1.8 3.6 v v vddburip vddbu ripple 100 mvrms v vddpll dc supply pll 0.9 1.0 1.1 v v vddpllrip vddpll ripple 30 mvrms v vddosc dc supply oscillator 1.65 3.6 v v vddoscrip vddosc ripple 30 mvrms v vddiom dc supply ebi i/os 1.65/3.0 1.8/3.3 1.95/3.6 v v vddnf dc supply nand flash i/os 1.65/3.0 1.8/3.3 1.95/3.6 v v vddiop0 dc supply peripheral i/os 1.65 3.6 v v vddiop1 dc supply peripheral i/os 1.65 3.6 v v vddana dc supply analog 3.0 3.3 3.6 v v vddusb dc supply usb 3.0 3.3 3.6 v v vddfuse dc supply fuse box 3.0 3.6 v
1082 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 v il input low-level voltage v vddio from 3.0v to 3.6v -0.3 0.8 v v vddio from 1.65v to 1.95v -0.3 0.3 x v vddio v v ih input high-level voltage v vddio from 3.0v to 3.6v 2 v vddio + 0.3 v v vddio from 1.65v to 1.95v 0.7 x v vddio v vddio + 0.3 v v ol output low-level voltage i o max, v vddio from 3.0v to 3.6v 0.4 v cmos (i o <0.3 ma), v vddio from 1.65v to 1.95v 0.1 v ttl (i o max), v vddio from 1.65v to 1.95v 0.4 v v oh output high-level voltage i o max, v vddio from 3.0v to 3.6v v vddio - 0.4 v cmos (i o <0.3 ma), v vddio from 1.65v to 1.95v v vddio - 0.1 v ttl (i o max), v vddio from 1.65v to 1.95v v vddio - 0.4 v v t- schmitt trigger negative going threshold voltage i o max, v vddio from 3.0v to 3.6v 0.8 1.1 v ttl (i o max), v vddio from 1.65v to 1.95v 0.3 x v vddio v v t+ schmitt trigger positive going threshold voltage i o max, v vddio from 3.0v to 3.6v 1.6 2.0 v ttl (i o max), v vddio from 1.65v to 1.95v 0.3 x v vddio v v hys schmitt trigger hysteresis v vddio from 3.0v to 3.6v 0.5 0.75 v v vddio from 1.65v to 1.95v 0.28 0.6 v r pullup pull-up resistance pa0-pa31 pb0-pb31 pd0-pd31 pe0-pe31 ntrst and nrst 40 75 190 kohms pc0-pc31 v vddiom1 in 1.8v range 240 1000 pc0-pc31 v vddiom1 in 3.3v range 120 350 i o output current pa0-pa31 pb0-pb31 pd0-pd31 pe0-pe31 8 ma pc0-pc31 v vddiom1 in 1.8v range 2 pc0-pc31 v vddiom1 in 3.3v range 4 i sc static current on v vddcore = 1.0v, mck = 0 hz, excluding por t a = 25c 11 ma all inputs driven tms, tdi, tck, nrst = 1 t a = 85c 25 on v vddbu = 3.3v, logic cells consumption, excluding por t a = 25c 8 a all inputs driven wkup = 0 t a = 85c 15 table 48-2. dc characteristics (continued)
1083 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 48.3 power consumption ? typical power consumption of plls , slow clock and main oscillator. ? power consumption of power supply in four different modes: active, idle, ultra low-power and backup. ? power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock. 48.3.1 power consumption versus modes the values in table 48-3 and table 48-4 on page 1084 are estimated values of the power con- sumption with operating conditions as follows: ?v ddiom = 1.8v ?v ddiop0 and 1 = 3.3v ?v ddpll = 1.0v ?v ddcore = 1.0v ?v ddbu = 3.3v ?t a = 25 c ? there is no consumption on the i/os of the device figure 48-1. measures schematics these figures represent the power consumption estimated on the power supplies. table 48-3. power consumption for different modes mode conditions consumption unit active arm core clock is 400 mhz. mck is 133 mhz. all peripheral clocks activated. onto amp2 103 ma idle idle state, waiting an interrupt. all peripheral clocks de-activated. onto amp2 33 ma ultra low power arm core clock is 500 hz. all peripheral clocks de-activated. onto amp2 7m a backup device only v ddbu powered onto amp1 8 a vddcore vddbu amp2 amp1
1084 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 table 48-4. power consumption by peripheral in active mode peripheral consumption unit pio controller 6 a/mhz usart 6 adc 5 twi 2 spi 3 uart 3 uhp 5 udp 5 lcdc 3 pwm 6 hsmci 3 ssc 5 timer counter channels 12 dma 1 aes 4 sha 3 trng 1
1085 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 48.4 clock characteristics 48.4.1 processor clock 48.4.2 system clock the system clock is the maximum clock at which the system is able to run. it is given by the smallest value of the internal bus clock and ebi clock. note: 1. with ddr2 usage. there is no limitations for lpddr, sdram and mobile sdram. table 48-5. processor clock wave form parameters symbol parameter conditions min max units 1/(t cppck ) processor clock frequency v vddcore min 250 (1) 400 mhz table 48-6. system clock waveform parameters symbol parameter conditions min max units 1/(t cpmck ) system clock frequency v vddcore min 125 (1) 133 mhz
1086 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 48.4.3 main oscillator characteristics note: 1. the c crystal value is specified by the crys tal manufacturer. in our case, c crystal must be between 12.5 pf and 17.5 pf. all parasitic capacitance, package and board, must be calculated in order to reach 12.5 pf (minimum targeted load for the oscillator) by taking into account the internal load c int . so, to target the minimum oscillator load of 12.5 pf, external capaci- tance must be: 12.5 pf - 2.1 pf = 10.4 pf which means that 20.8 pf is the target value (20.8 pf from xin to gnd and 20.8 pf from xout to gnd) if 17.5 pf load is targeted, the sum of pad, package, boar d and external capacitances must be 17.5 pf - 2.1 pf = 15.4 pf which means 30.8 pf (30.8 pf from xin to gnd and 30.8 pf from xout to gnd). table 48-7. main oscillator characteristics symbol parameter conditions min typ max unit 1/(t cpmain ) crystal oscillator frequency 8 16 20 mhz c crystal (1) crystal load capacitance 12.5 17.5 pf c int (1) internal load capacitance 1.85 2.1 2.35 pf c lext external load capacitance c crystal = 12.5 pf (1) 20.8 pf c crystal = 17.5 pf (1) 30.8 pf duty cycle % t st startup time @3mhz @8mhz @16mhz @20mhz 20 4 2 2 ms i ddst standby current consumption standby mode 1 a p on drive level @3mhz @8mhz @16mhz @20mhz 15 30 50 50 w i dd on current dissipation @3mhz @8mhz @16mhz @20mhz 280 380 500 580 380 510 630 750 a 1k xin xout gndpll c lext c lext c crystal
1087 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 48.4.4 crystal oscillator characteristics the following characteristics are applicabl e to the operating temperature range: t a = -40c to 85c and worst case of power supply, unless otherwise specified. 48.4.5 xin clock characteristics notes: 1. these characteristics apply only when the main oscillato r is in bypass mode (i.e. when moscen = 0 and oscbypass = 1) in the ckgr_mor register. see pmc clock generator main oscillator register in the pmc section. 2. do not exceed 3.6v table 48-8. crystal characteristics symbol parameter conditions min typ max unit esr equivalent series resistor rs fundamental @3mhz fundamental @8mhz fundamental @16mhz fundamental @20mhz 200 100 80 50 c m motional capacitance 8ff c s shunt capacitance 7pf table 48-9. xin clock electrical characteristics symbol parameter conditions min max units 1/(t cpxin ) xin clock frequency 50 mhz t cpxin xin clock period 20 ns t chxin xin clock high half-period 0.4 x t cpxin 0.6 x t cpxin ns t clxin xin clock low half-period 0.4 x t cpxin 0.6 x t cpxin ns c in xin input capacitance (1) 25 pf r in xin pull-down resistor (1) 500 k v xinlow xin low voltage (1) -0.3v 0.3 x vddosc (2) v v xinhigh xin high voltage (1) 0.7 x vddosc vddosc+0.3 (2) v
1088 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 48.5 12 mhz rc oscillat or characteristics 48.6 32 khz oscillator characteristics notes: 1. r s is the equivalent series resistance. 2. c lext32 is determined by taking into account inte rnal, parasitic and package load capacitance. table 48-10. 12 mhz rc oscillator characteristics symbol parameter conditions min typ max units f0 nominal frequency 8.4 12 15.6 mhz duty duty cycle 45 50 55 % i dd on power consumption oscillation 86 86 140 125 a t on startup time 6 10 s i dd stdby standby consumption 22 a table 48-11. 32 khz oscillator characteristics symbol parameter conditions min typ max unit 1/(t cp32khz ) crystal oscillator frequency 32 768 khz c crystal32 load capacitance crystal @ 32.768 khz 6 12.5 pf c lext32 (2) external load capacitance c crystal32 = 6 pf 6 pf c crystal32 = 12.5 pf 19 pf duty cycle 40 50 60 % t st startup time r s = 50 k (1) c crystal32 = 6 pf 400 ms c crystal32 = 12.5 pf 900 ms r s = 100 k (1) c crystal32 = 6 pf 600 ms c crystal32 = 12.5 pf 1200 ms xin32 xout3 2 gndbu c lext32 c lext32 c crystal32
1089 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 48.6.1 32 khz crystal characteristics 48.6.2 xin32 clock characteristics note: 1. these characteristics apply only when the 32.768khz osci llator is in bypass mode (i.e. when rcen = 0, osc32en = 0, oscsel = 1 and osc32byp = 1) in the sckcr regi ster. see slow clock select ion in the pmc section. table 48-12. 32 khz crystal characteristics symbol parameter conditions min typ max unit esr equivalent series resistor rs crystal @ 32.768 khz 50 100 k c m motional capacitance crystal @ 32.768 khz 0.6 3 ff c s shunt capacitance crystal @ 32.768 khz 0.6 2 pf i dd on current dissipation r s = 50 k (1) c crystal32 = 6 pf 0.55 1.3 a r s = 50 k (1) c crystal32 = 12.5pf 0.85 1.6 a r s = 100 k (1) c crystal32 = 6 pf 0.7 2.0 a r s = 100 k (1) c crystal32 = 12.5 pf 1.1 2.2 a i dd stdby standby consumption 0.3 a table 48-13. xin32 clock electrical characteristics symbol parameter conditions min max units 1/(t cpxin32 ) xin32 clock frequency 44 khz t cpxin32 xin32 clock period 22 s t chxin32 xin32 clock high half-period 11 s t clxin32 xin32 clock low half-period 11 s t clch32 xin32 clock rise time 400 ns t clcl32 xin32 clock fall time 400 ns c in32 xin32 input capacitance (1) 6p f r in32 xin32 pull-down resistor (1) 4m v in32 xin32 voltage (1) vddbu vddbu v v inil32 xin32 input low level voltage (1) -0.3 0.3 x v vddbu v v inih32 xin32 input high level voltage (1) 0.7 x v vddbu v vddbu + 0.3 v
1090 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 48.7 32 khz rc oscillator characteristics table 48-14. rc oscillator characteristics symbol parameter conditions min typ max unit 1/(t cprcz ) crystal oscillator frequency 20 32 44 khz duty cycle 45 55 % t st startup time 75 s i dd on power consumption oscillation after startup time 1.1 2.1 a i dd stdby standby consumption 0.4 a
1091 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 48.8 pll characteristics the following configuration of icplla and outa must be done for each plla frequency range. 48.9 i/os criteria used to define the maximum frequency of the i/os: ? output duty cycle (40%-60%) ? minimum output swing: 100 mv to vddio - 100 mv ? addition of rising and falling time inferior to 75% of the period notes: 1. 3.3v domain: v vddiop from 3.0v to 3.6v, maximum external capacitor = 40 pf 2. 1.8v domain: v vddiop from 1.65v to 1.95v, maximum external capacitor = 20 pf table 48-15. plla characteristics symbol parameter conditions min typ max unit f out output frequency refer to following table 400 800 mhz f in input frequency 2 32 mhz i pll current consumption active mode 3.6 4.5 ma standby mode 1 a t startup time 50 s table 48-16. plla frequency regarding icplla and outa pll frequency range (mhz) icplla outa 745 - 800 0 0 0 695 - 750 0 0 1 645 - 700 0 1 0 595 - 650 0 1 1 545 - 600 1 0 0 495 - 550 1 0 1 445 - 500 1 1 0 400 - 450 1 1 1 table 48-17. i/o characteristics symbol parameter conditions min max units freqmax vddiop powered pins frequency 3.3v domain (1) 66 mhz 1.8v domain (2) 66 mhz
1092 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 48.10 analog-to-digital converter (adc) note: 1. the track-and-hold acquisition time is given by: the adc internal clock is divided by 2 in order to generate a clock with a duty cycle of 75%. so the maximum conversion time is give by: the full speed is obtained for an input source impedance of < 50 ohms maximum, or tth = 500 ns. in order to make the tsadc work properly, the shtim field in tsadcc mode register is to be calculated according to this track and hold acquisition time, also called sampled and hold time. table 48-18. channel conversion time and adc clock parameter conditions min typ max units adc clock frequency 10-bit resolution mode 13.2 mhz startup time return from idle mode 40 s track and hold acquisition time (tth) adc clock = 13.2 mhz (1) 0.5 s conversion time (tct) adc clock = 13.2 mhz (1) adc clock = 5 mhz (1) 1.74 4.6 s throughput rate adc clock = 13.2 mhz (1) adc clock = 5 mhz (1) 440 192 ksps tth (ns) 500 0.12 z in () () += tct s () 23 fclk ---------- - mhz () = table 48-19. external voltage reference input parameter conditions min typ max units advref input voltage range 2.4 vddana v advref average current 600 a current consumption on vddana 600 a table 48-20. analog inputs parameter min typ max units input voltage range 0 advref v input peak current 2.5 ma input capacitance 710pf input impedance 50 ohms
1093 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 48.11 core power supply por characteristics 48.12 smc timings 48.12.1 timing conditions timings are given assuming a capacitance load on data, control and address pads: in the following tables, t cpmck is mck period. table 48-21. transfer characteristics parameter min typ max units resolution 10 bit integral non-linearity 2 lsb differential non-linearity - adc clock = 13.2 mhz - adc clock = 5 mhz 2 0.9 lsb offset error 10 mv gain error - adc clock = 13.2 mhz - adc clock = 5 mhz 3 2 lsb table 48-22. power-on-reset characteristics symbol parameter conditions min typ max units v th+ threshold voltage rising minimum slope of +2.0v/30ms 0.5 0.7 0.89 v v th- threshold voltage falling 0.4 0.6 0.85 v t res reset time 30 70 130 s idd current consumption after t res 37 a table 48-23. capacitance load corner supply max min 3.3v 50pf 5 pf 1.8v 30 pf 5 pf
1094 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 48.12.2 timing extraction 48.12.2.1 zero hold mode restrictions 48.12.2.2 read timings table 48-24. zero hold mode use maximum system clock frequency (mck) symbol parameter min units vddiom supply 1.8v 3.3v zero hold mode use fmax mck frequency 66 66 mhz table 48-25. smc read signals - nrd controlled (read_mode= 1) symbol parameter min units vddiom supply 1.8v 3.3v no hold settings (nrd hold = 0) smc 1 data setup before nrd high 13.7 11.8 ns smc 2 data hold after nrd high 0 0 ns hold settings (nrd hold 0) smc 3 data setup before nrd high 10.7 8.8 ns smc 4 data hold after nrd high 0 0 ns hold or no hold settings (nrd hold 0, nrd hold =0) smc 5 nbs0/a0, nbs1, nbs2/a1, nbs3, a2 - a25 valid before nrd high (nrd setup + nrd pulse)* t cpmck - 5.3 (nrd setup + nrd pulse)* t cpmck - 5.1 ns smc 6 ncs low before nrd high (nrd setup + nrd pulse - ncs rd setup) * t cpmck -4.8 (nrd setup + nrd pulse - ncs rd setup) * t cpmck - 4.9 ns smc 7 nrd pulse width nrd pulse * t cpmck - 3.4 nrd pulse * t cpmck - 3.5 ns table 48-26. smc read signals - ncs controlled (read_mode= 0) symbol parameter min units vddiom supply 1.8v 3.3v no hold settings (ncs rd hold = 0) smc 8 data setup before ncs high 26.7 24.7 ns smc 9 data hold after ncs high 0 0 ns hold settings (ncs rd hold 0) smc 10 data setup before ncs high 12.4 10.4 ns smc 11 data hold after ncs high 0 0 ns hold or no hold settings (ncs rd hold 0, ncs rd hold = 0)
1095 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 48.12.2.3 write timings notes: 1. hold length = total cycle duration - setup duration - pulse duration. hold length is for ncs wr hold length or nwe hold length. ) smc 12 nbs0/a0, nbs1, nbs2 /a1, nbs3, a2 - a25 valid before ncs high (ncs rd setup + ncs rd pulse)* t cpmck - 18.1 (ncs rd setup + ncs rd pulse)* t cpmck - 18.2 ns smc 13 nrd low before ncs high (ncs rd setup + ncs rd pulse - nrd setup)* t cpmck - 2.8 (ncs rd setup + ncs rd pulse - nrd setup)* t cpmck - 2.9 ns smc 14 ncs pulse width ncs rd pulse length * t cpmck - 4.0 ncs rd pulse length * t cpmck - 4.0 ns table 48-26. smc read signals - ncs controlled (read_mode= 0) table 48-27. smc write signals - nwe controlled (write_mode = 1) symbol parameter min units 1.8v supply 3.3v supply hold or no hold settings (nwe hold 0, nwe hold = 0) smc 15 data out valid before nwe high nwe pulse * t cpmck - 4.1 nwe pulse * t cpmck - 4.0 ns smc 16 nwe pulse width nwe pulse * t cpmck - 3.0 nwe pulse * t cpmck - 3.1 ns smc 17 nbs0/a0 nbs1, nbs2/a1, nbs3, a2 - a25 valid before nwe low nwe setup * t cpmck - 4.2 nwe setup * t cpmck - 4.1 ns smc 18 ncs low before nwe high (nwe setup - ncs rd setup + nwe pulse) * t cpmck - 3.8 (nwe setup - ncs rd setup + nwe pulse) * t cpmck - 3.7 ns hold settings (nwe hold 0) smc 19 nwe high to data out, nbs0/a0 nbs1, nbs2/a1, nbs3, a2 - a25 change nwe hold * t cpmck - 4.0 nwe hold * t cpmck - 3.1 ns smc 20 nwe high to ncs inactive (1) (nwe hold - ncs wr hold)* t cpmck - 2.8 (nwe hold - ncs wr hold)* t cpmck - 2.0 ns no hold settings (nwe hold = 0) smc 21 nwe high to data out, nbs0/a0 nbs1, nbs2/a1, nbs3, a2 - a25, ncs change (1) 1.6 1.4 ns table 48-28. smc write ncs controlled (write_mode = 0) symbol parameter min units 1.8v supply 3.3v supply smc 22 data out valid before ncs high ncs wr pulse * t cpmck - 4.3 ncs wr pulse * t cpmck - 4.5 ns smc 23 ncs pulse width ncs wr pulse * t cpmck - 4.0 ncs wr pulse * t cpmck - 4.0 ns smc 24 nbs0/a0 nbs1, nbs2/a1, nbs3, a2 - a25 valid before ncs low ncs wr setup * t cpmck - 3.6 ncs wr setup * t cpmck - 3.5 ns
1096 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 48-2. smc timings - ncs controlled read and write smc 25 nwe low before ncs high (ncs wr setup - nwe setup + ncs pulse)* t cpmck - 3.9 (ncs wr setup - nwe setup + ncs pulse)* t cpmck - 3.9 ns smc 26 ncs high to data out, nbs0/a0, nbs1, nbs2/a1, nbs3, a2 - a25, change ncs wr hold * t cpmck - 6.1 ncs wr hold * t cpmck - 5.2 ns smc 27 ncs high to nwe inactive (ncs wr hold - nwe hold)* t cpmck - 4.8 (ncs wr hold - nwe hold)* t cpmck - 4.4 ns table 48-28. smc write ncs controlled (write_mode = 0) symbol parameter min units 1.8v supply 3.3v supply nrd ncs d0 - d15 nwe ncs controlled read with no hold ncs controlled read with hold ncs controlled write smc22 smc26 smc10 smc11 smc12 smc9 smc8 smc14 smc14 smc23 smc27 smc26 a0/a1/nbs[3:0] /a2-a25 smc24 smc25 smc12 smc13 smc13
1097 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 48-3. smc timings - nrd controlled r ead and nwe controlled write nrd ncs d0 - d31 nwe a0/a1/nbs[3:0] /a2-a25 nrd controlled read with no hold nwe controlled write with no hold nrd controlled read with hold nwe controlled write with hold smc1 smc2 smc15 smc21 smc3 smc4 smc15 smc19 smc20 smc7 smc21 smc16 smc7 smc16 smc19 smc21 smc17 smc18 smc5 smc5 smc6 smc6 smc17 smc18
1098 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 48.13 ddrsdrc timings the ddrsdrc controller satisfies the timings of standard ddr2, lp-ddr, sdr and lp-sdr modules. ddr2, lp-ddr and sdr timings are specified by the jedec standard. supported speed grade limitations: ? ddr2-400 limited at 133 mhz clock frequency (1.8v, 30pf on data/control, 10pf on ck/ck#) ? lp-ddr (1.8v, 30pf on data/control, 10pf on ck) tcyc = 5.0 ns, fmax = 125 mhz tcyc = 6.0 ns, fmax = 110 mhz tcyc = 7.5 ns, fmax = 95 mhz ? sdr-100 (3.3v, 50 pf on data/control, 10 pf on ck) ? sdr-133 (3.3v, 50 pf on data/control, 10 pf on ck) ? lp-sdr-133 (1.8v, 30 pf on data/control, 10 pf on ck) 48.14 peripheral timings 48.14.1 spi 48.14.1.1 maximum spi frequency the following formulas give maximum spi frequency in master read and write modes and in slave read and write modes. master write mode the spi only sends data to a slave device such as an lcd, for example. the limit is given by spi 2 (or spi 5 ) timing. since it gives a maximum frequency above the maximum pad speed (see section 48.9 i/os ), the max spi frequency is the one from the pad. master read mode t valid is the slave time response to output data after deleting an spck edge. for atmel spi dataflash (at45db642d), t valid (ort v ) is 12 ns max. this gives, f spck max = 47.1 mhz @ vddio = 3.3v. slave read mode in slave mode, spck is the input clock fo r the spi. the max spck frequency is given by setup and hold timings spi 7 /spi 8 (or spi 10 /spi 11 ). since this gives a frequency well above the pad limit, the limit in slave read mode is given by spck pad. slave write mode t setup is the setup time from the master before sampling data (12ns). this gives, f spck max = 44.6 mhz @ vddio = 3.3v. f spck max 1 spi 0 orspi 3 () t valid + -------------------------------------------------------- = f spck max 1 spi 6 orspi 9 () t setup + -------------------------------------------------------- - =
1099 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 48.14.1.2 timing conditions timings are given assuming a capacitance load on miso, spck and mosi : 48.14.1.3 timing extraction figure 48-4. spi master mode 1 and 2 figure 48-5. spi master mode 0 and 3 table 48-29. capacitance load for miso, spck and mosi (product dependent) corner supply max min 3.3v 40 pf 5 pf 1.8v 20 pf 5 pf spck miso mosi spi 2 spi 0 spi 1 spck miso mosi spi 5 spi 3 spi 4
1100 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 48-6. spi slave mode 0 and 3 figure 48-7. spi slave mode 1 and 2 spck miso mosi spi 6 spi 7 spi 8 npcs0 spi 12 spi 13 spck miso mosi spi 9 spi 10 spi 11 npcs0 spi 12 spi 13
1101 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 48-8. spi slave mode - npcs timings spck (cpol = 0) miso spi 14 spi 16 spi 12 spi 15 spi 13 spck (cpol = 1) spi 6 spi 9 table 48-30. spi timings with 3.3v peripheral supply symbol parameter cond min max units master mode spi spck spi clock 66 mhz spi 0 miso setup time before spck rises 13.7 ns spi 1 miso hold time after spck rises 0 ns spi 2 spck rising to mosi 0 7.6 ns spi 3 miso setup time before spck falls 13.2 ns spi 4 miso hold time after spck falls 0 ns spi 5 spck falling to mosi 0 7.7 ns slave mode spi 6 spck falling to miso 2.7 14.1 ns spi 7 mosi setup time before spck rises 2.7 ns spi 8 mosi hold time af ter spck rises 0.2 ns spi 9 spck rising to miso 2.5 13.8 ns spi 10 mosi setup time before spck falls 2.2 ns spi 11 mosi hold time after spck falls 0.6 ns spi 12 npcs0 setup to spck rising 4.3 ns spi 13 npcs0 hold after spck falling 0 ns spi 14 npcs0 setup to spck falling 3.8 ns spi 15 npcs0 hold after spck rising 0 ns spi 16 npcs0 falling to miso valid 14.5 ns
1102 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 48-9. min and max access time for spi output signal table 48-31. spi timings with 1.8v peripheral supply symbol parameter cond min max units master mode spi spck spi clock 66 mhz spi 0 miso setup time before spck rises 16.3 ns spi 1 miso hold time after spck rises 0 ns spi 2 spck rising to mosi 0 6.9 ns spi 3 miso setup time before spck falls 15.1 ns spi 4 miso hold time after spck falls 0 ns spi 5 spck falling to mosi 0 7.0 ns slave mode spi 6 spck falling to miso 3.5 16.8 ns spi 7 mosi setup time before spck rises 2.9 ns spi 8 mosi hold time af ter spck rises 0.3 ns spi 9 spck rising to miso 3.3 16.4 ns spi 10 mosi setup time before spck falls 2.4 ns spi 11 mosi hold time after spck falls 0.7 ns spi 12 npcs0 setup to spck rising 4.5 ns spi 13 npcs0 hold after spck falling 0 ns spi 14 npcs0 setup to spck falling 3.9 ns spi 15 npcs0 hold after spck rising 0 ns spi 16 npcs0 falling to miso valid 17.3 ns spck miso mosi spi 2max spi 0 spi 1 spi 2min
1103 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 48.14.2 ssc 48.14.2.1 timing conditions timings are given assuming a capacitance load on table 48-32 . these values may be product dependant and should be confirmed by the specification. 48.14.2.2 timing extraction figure 48-10. ssc transmitter, tk and tf in output figure 48-11. ssc transmitter, tk in input and tf in output table 48-32. capacitance load corner supply max min 3.3v 30pf 5 pf 1.8v 20pf 5 pf tk (cki =1) tf/td ssc 0 tk (cki =0) tk (cki =1) tf/td ssc 1 tk (cki =0)
1104 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 48-12. ssc transmitter, tk in output and tf in input figure 48-13. ssc transmitter, tk and tf in input figure 48-14. ssc receiver rk and rf in input tk (cki=1) tf ssc 2 ssc 3 tk (cki=0) td ssc 4 tk (cki=0) tf ssc 5 ssc 6 tk (cki=1) td ssc 7 rk (cki=1) rf/rd ssc 8 ssc 9 rk (cki=0)
1105 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 48-15. ssc receiver, rk in input and rf in output figure 48-16. ssc receiver, rk and rf in output figure 48-17. ssc receiver, rk in ou tput and rf in input rk (cki=0) rd ssc 8 ssc 9 rk (cki=1) rf ssc 10 rk (cki=0) rd ssc 11 ssc 12 rk (cki=1) rf ssc 13 rk (cki=1) rf/rd ssc 11 ssc 12 rk (cki=0)
1106 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 notes: 1. ssc4 and ssc7 timings depend on the start condition. when sttdly = 0 (receive start delay) and start = 4, or 5 or 7 (receive start selection), two periods of the mck must be added to timings. 2. for output signals (tf, td, rf), min and max access times are defined. the min access time is the time between the tk (or rk) edge and the signal change. the max access time is t he time between the tk edge and the signal stabilization. figure 48-18 illustrates min and max accesses for ssc0. the sa me applies to ssc1, ssc4, and ssc7, ssc10 and ssc13. 3. 1.8v domain: v vddio from 1.65v to 1.95v, maximum external capacitor = 20pf. 4. 3.3v domain: v vddio from 3.0v to 3.6v, maximum external capacitor = 30pf. table 48-33. ssc timings symbol parameter conditions min max units transmitter ssc 0 (2) tk edge to tf/td (t k output, tf output) 1.8v domain (3) 3.3v domain (4) 2.1 2.1 13.5 13.2 ns ssc 1 (2) tk edge to tf/td (tk input, tf output) 1.8v domain (3) 3.3v domain (4) 2.8 2.1 15.4 11.1 ns ssc 2 tf setup time before tk edge (tk output) 1.8v domain (3) 3.3v domain (4) 14.6 - t cpmck 10.6 - t cpmck ns ssc 3 tf hold time after tk edge (tk output) 1.8v domain (3) 3.3v domain (4) t cpmck - 2.7 t cpmck - 2.0 ns ssc 4 (1)(2) tk edge to tf/td (tk output, tf input) 1.8v domain (3) 3.3v domain (4) 2.1 (+2*t cpmck ) 2.0 (+2*t cpmck ) 13.5 +2*t cpmck ) 13.2 +2*t cpmck ) ns ssc 5 tf setup time before tk edge (tk input) 1.8v domain (3) 3.3v domain (4) 0n s ssc 6 tf hold time after tk edge (tk input) 1.8v domain (3) 3.3v domain (4) t cpmck ns ssc 7 (1)(2) tk edge to tf/td (tk input, tf input) 1.8v domain (3) 3.3v domain (4) 2.8 (+3*t cpmck ) 2.1 (+3*t cpmck ) 15.4(+3*t cpmck ) 11.1 (+3*t cpmck ) ns receiver ssc 8 rf/rd setup time before rk edge (rk input) 1.8v domain (3) 3.3v domain (4) 0n s ssc 9 rf/rd hold time after rk edge (rk input) 1.8v domain (3) 3.3v domain (4) t cpmck ns ssc 10 (2) rk edge to rf (rk input) 1.8v domain (3) 3.3v domain (4) 2.8 2.1 15.1 10.8 ns ssc 11 rf/rd setup time before rk edge (rk output) 1.8v domain (3) 3.3v domain (4) 14.5 - t cpmck 10.4 - t cpmck ns ssc 12 rf/rd hold time after rk edge (rk output) 1.8v domain (3) 3.3v domain (4) t cpmck - 2.7 t cpmck - 1.9 ns ssc 13 (2) rk edge to rf (rk output) 1.8v domain (3) 3.3v domain (4) 2.1 2.0 13.5 13.2 ns
1107 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 48-18. min and max access time of output signals 48.14.3 hsmci the high speed multimedia card interface (hsmci) supports the multimedia card (mmc) specification v4.3, the sd memo ry card specification v2.0, th e sdio v2.0 specification and ce-ata v1.1. 48.14.4 usart in spi mode timings 48.14.4.1 timing conditions timings are given assuming a capacitance load on table 48-32 . 48.14.4.2 timing extraction figure 48-19. usart spi master mode tk (cki =0) tf/td ssc 0min tk (cki =1) ssc 0max table 48-34. capacitance load corner supply max min 3.3v 40pf 5 pf 1.8v 20pf 5 pf nss spi 0 msb lsb spi 1 cpol=1 cpol=0 miso mosi sck spi 5 spi 2 spi 3 spi 4 spi 4
1108 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 figure 48-20. usart spi slave mode: (mode 1 or 2) figure 48-21. usart spi slave mode: (mode 0 or 3) sck miso mosi spi 6 spi 7 spi 8 nss spi 12 spi 13 sck miso mosi spi 9 spi 10 spi 11 nss spi 14 spi 15
1109 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 notes: 1. 1.8v domain: vddio from 1.65v to 1.95v, maximum external capacitor = 20pf 2. 3.3v domain: vddio from 3.0v to 3.6v, maximum external capacitor = 40pf. table 48-35. usart spi timings symbol parameter conditions min max units master mode spi 0 sck period 1.8v domain (1) 3.3v domain (2) mck/6 ns spi 1 input data setup time 1.8v domain (1) 3.3v domain (2) 0.5 * mck + 3.5 0.5 * mck + 3.3 ns spi 2 input data hold time 1.8v domain (1) 3.3v domain (2) 1.5 * mck + 1.1 1.5 * mck + 0.8 ns spi 3 chip select active to serial clock 1.8v domain (1) 3.3v domain (2) 1.5 * sck - 1.9 1.5 * sck - 2.5 ns spi 4 output data setup time 1.8v domain (1) 3.3v domain (2) 0 0 7.6 8.4 ns spi 5 serial clock to chip select inactive 1.8v domain (1) 3.3v domain (2) 1 *sck - 7.1 1 *sck - 7.8 ns slave mode spi 6 sck falling to miso 1.8v domain (1) 3.3v domain (2) 3.8 3.0 19.5 16.6 ns spi 7 mosi setup time before sck rises 1.8v domain (1) 3.3v domain (2) 2 * mck + 3.0 2 * mck + 2.7 ns spi 8 mosi hold time after sck rises 1.8v domain (1) 3.3v domain (2) 1.5 1.3 ns spi 9 sck rising to miso 1.8v domain (1) 3.3v domain (2) 3.6 2.9 19.1 16.6 ns spi 10 mosi setup time before sck falls 1.8v domain (1) 3.3v domain (2) 2 * mck + 2.6 2 * mck + 2.4 ns spi 11 mosi hold time after sck falls 1.8v domain (1) 3.3v domain (2) 1.5 1.2 ns spi 12 npcs0 setup to sck rising 1.8v domain (1) 3.3v domain (2) 2.5 * mck + 1.4 2.5 * mck + 1.1 ns spi 13 npcs0 hold after sck falling 1.8v domain (1) 3.3v domain (2) 1.5 * mck + 2.4 1.5 * mck + 2.1 ns spi 14 npcs0 setup to sck falling 1.8v domain (1) 3.3v domain (2) 2.5 * mck + 1.1 2.5 * mck + 1.0 ns spi 15 npcs0 hold after sck rising 1.8v domain (1) 3.3v domain (2) 1.5 * mck + 1.8 1.5 * mck + 1.6 ns
1110 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 49. mechanical overview of the 21 7-ball and 247-ball bga packages 49.1 217-ball bga package figure 49-1. 217-ball bga package drawing
1111 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 table 49-1. ball information ball pitch 0.8 mm +/- 0.05 ball diameter 0.4 mm +/- 0.05 table 49-2. soldering information ball land 0.43 mm +/- 0.05 solder mask opening 0.30 mm +/- 0.05 table 49-3. device and 217-ball bga package maximum weight 450 mg table 49-4. 217-ball bga package characteristics moisture sensitivity level 3 table 49-5. package reference jedec drawing reference mo-205 jesd97 classification e1
1112 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 49.2 247-ball bga package figure 49-2. 247-ball bga package drawing
1113 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 table 49-6. ball information ball pitch 0.5 mm +/- 0.05 ball diameter 0.3 mm +/- 0.05 table 49-7. soldering information ball land 0.35 mm +/- 0.05 solder mask opening 0.27 mm +/- 0.05 table 49-8. device and 247-ball bga package maximum weight 177 mg table 49-9. 247-ball bga package characteristics moisture sensitivity level 3 table 49-10. package reference jedec drawing reference none jesd97 classification e1
1114 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12
1115 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 50. sam9n12/SAM9CN11 /sam9cn12 ordering information table 50-1. sam9n12/cn11/cn12 ordering information ordering code package package type temperature operating range at91sam9cn12-cu bga217 green industrial -40c to 85c at91SAM9CN11-cu bga217 green industrial -40c to 85c at91sam9n12-cu bga217 green industrial -40c to 85c
1116 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12
1117 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 51. at91sam9cn12 series errata 51.1 marking all devices are marked with the atmel logo and the ordering code. additional marking is as follows: where ?yy: manufactory year ? ww: manufactory week ? v: revision ? xxxxxxxxx: lot number 51.2 at91sam9n12/c n11/cn12 errata 51.2.1 reset controller (rstc) 51.2.1.1 rstc: reset during sdram accesses when a reset (user reset, watchdog, software reset) occurs during sdram read access, the sdram clock is turned off while data is ready to be read on the data bus. the sdram main- tains the data until the clock restarts. this leads to a data bus conflict and adversely affects the boot memories connected on the ebi: ? nand flash boot functionality, if the system boots out of internal rom. ? nor flash boot, if the system boots on an external memory connected on the ebi cs0. problem fix/workaround 1. boot from serial flash or data flash on spi 2. connect the nand flash on d16-d23 and set nfd0_on_d16 to 1 in ccfg_ebicsa register. warning! this prohibits connecting another device on the ebi. yyww v xxxxxxxxx arm
1118 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12
1119 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 revision history in the tables that follow, the most recent ve rsion appears first. rfo denotes expert input during the update process. doc. rev 11063g comments change request ref. overview: added write protected registers in section features . product name updated to sam9n12/SAM9CN11/sam9cn12. section 1. description updated with the various devices configurations: table 1-1, devices added. bullets for SAM9CN11 and sam9n12 added in section 7.3 chip identification . 8213 8244 boot strategies: boot strategy from sam9cn12 removed to create the separate secure boot document, and replaced by the previous boot strategies from sam9n12. table 12-1, external clock and crystal frequencies allowed for boot sequence (in mhz) added in section 12.2.3 chip setup . 8202 8270 rstc: rstc conditions improved. 8083 hsmci: sentence "this flag must be used only for write operations removed in notbusy: hsmci not busy on page 626 . 8394 usart: whole chapter updated. rfo ssc: reworked tables and bitfield descriptions in section 43.9.3 ssc rece ive clock mode register , section 43.9.4 ssc receive frame mode register , section 43.9.5 ssc transmit clock mode register , section 43.9.6 ssc transmit fr ame mode register . replaced aic/nvic wording with interrupt controller. 8466 aes: hardware counter measures updated in section 45.2 embedded characteristics on page 1037 and in section 45.5.1 counter measures on page 1044 . rfo sha: mode register reset value updated to 0x1 in table 46-2, register mapping .r f o ordering information: ordering codes added for sam9n12 and SAM9CN11. 8244 errata errata created. section 49.3 marking moved to section 51.1 marking on page 1117 .r f o back page: date updated. rfo
1120 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 doc. rev 11063f comments change request ref. description: section 1. description , 125 mhz --> 133 mhz fips pub 46-3 compliant tdes removed from 3rd paragraph 7928 rfo signal description: table 3-1, signal description list , nfd0-nfd16 --> nfd0-nfd15 rfo power considerations: section 5.2 programmable i/o lines power supplies and current drive removed from section 5. power considerations , as the same contents already exists in section 27.7.4 power supplies rfo system controller: section 7.3 chip identification , chip id: 0x819a_07a0 --> 0x819a_07a1 rfo peripherals: table 8-1, sam9n12/cn11/cn12 peripheral identifiers :replaced keyword reserved on 4th row with fuse 8039 ebi: section 27.7.4 power supplies , following sentences added before the 2nd figure: this can be used if the smc connects to the nand flash only. using this func tion with another device on the smc will lead to an unpredictable behavior of that device. in th at case, a default value must be selected. 8008 fuse: section 25. umc fuse controller added. 7928 matrix: section 26.10.5.1 ebi chip select assignment register , nfd0_on_d16 bitfield description updated 8008 pmc: section 21.2 embedded characteristics , 266 mhz ddr --> 133 mhz ddr section 22.8 peripheral clock controller , pmc_pcr, 0x10030102 --> pmc_pcr,0x10031002 7975 7920 electrical characteristics: table 48-5, processor clo ck waveform parameters and table 48-6, system clock waveform parameters , corner max changed to vvddcore min and second row removed. in the note below, ldddr changed to lpddr table 48-9, xin clock electrical characteristics , vin row split into 2 rows: v xinlow and v xinhigh section 48.12 smc timings , smc timings are given for max corners removed table 48-18, channel conversion time and adc clock : adc clock = 5 mhz row added to conversion time (tct) and to throughput rate table 48-21, transfer characteristics , 2 rows added: adc clock = 13.2 mhz and adc clock = 5 mhz rfo 8009 rfo 7947
1121 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 doc. rev 11063e comments change request ref. overview: description , updated...processor running up to 400 mhz... updated...system running up to 133 mhz... 7847 ddrsdrc: former section 29.7 programmable io delays removed from datasheet. 7891 pio: section 23.5.12 programmable i/o delays , only pads pa[15:11] and pa[20:18] can be configured. section 23.5.13 programmable i/o drive , it is possible to configure the i/o drive for pads pa[31:0], pb[18:0] and pc[31:0]. 7886 pmc: section 21.2 embedded characteristics , updated, 266 mhz ddr system clock. section 22.12.8 pmc clock generator main clock frequency register , added rcmeas bit to register. 7874 7726 electrical characteristics: table 48-3, power consumption for different modes , ? updated, active mode power consumption, 103 ma ? updated, idle mode power consumption, 33 ma table 48-5, processor clo ck waveform parameters ? updated, max = 400 mhz table 48-6, system clock waveform parameters updated, max = 133 mhz 7847 section 46.14.5 two-wire serial interface characteristics removed. footnotes updated in table 48-33, ssc timings 7863 back page: updated point of contact information. marcom doc. rev 11063d comments change request ref. overview: section 6. memories , ...internal rom... bootstrap routine, revised. section 8.5 fuse box features , removed table 8.3 rfo debug and test: section 10.6.3 debug unit , removed unnecessary line on chip id section 10.6.5 jtag id code register , fixed typo in title, revised part number and jtag id code value. rfo dmac: section 32.2 embedded characteristics , missing elements recovered. 7271 trng: section 47. true random number generator (trng) , faulty section number corrected. subsequent section numbering and toc affected. rfo:
1122 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 doc. rev 11063c comments change request ref. overview: description slc nand flash is supported. section 1. description , 1st paragraph, the 2nd sentence was removed. table 4-1, bga217 pin description , table updated with values in ball column. table 5-1, sam9n12/cn11/cn12 power supplies , vddfuse voltage range updated, 3.0v-3.6v. section 6.3.3 ddr-sdram controller , revised. section 7.3 chip identification , removed two lines. section 8.4 peripheral signal multiplexing on i/o lines , removed irrelevant text. elsewhere, minor grammar revisions. advance information status moved to preliminary. rfo 7395 rfo 7269 rfo arm processor: section 9. arm926ej-s processor overview , removed tightly-coupled memory interface chapter. rfo: debug and test: figure 10-1, debug and test block diagram , removed pdc. rfo boot program: figure 12-1, rom code algorithm flow diagram , updated. section the system always boots at address 0x0. to ensure maximum boot possib ilities, the memory layout can be changed thanks to the bms pin. this allows the user to layout the rom or an external memory to 0x0. the sampling of the bms pin is done at reset. , and forward, grammar and format edits. 7304 rfo adc: section 42.8.12 adc inte rrupt status register , fixed adc_sr typos to adc_isr. section 42.8.14 adc extended mode register , values 2 and 3 swapped in cmpmode bitfield table. section 42.8.16 adc channel data register , data bitfield extended to fields 11 and 10. section 42.6.5 conversion triggers , trgmod bitfield refers to section 42.8.22 adc trigger register . 7249-7250 7313 rfo aes: section 45.5.1 countermeasures , updated. 7357 aic: section 11.9 write protection registers added to datasheet. srctype: interrupt source type on page 74 bitfield description table updated. prior: priority level on page 74 , bitfield described in a table. 7045 7144 7191 ddrsdrc: section 31.2 embedded characteristics ,removed... eight internal banks not supported. section 31.5.4.1 self refresh mode udp_en replaced by upd_mr. in section 31.7.7 ddrsdrc low- power register udp_mr typo corrected. twtr: internal write to read delay on page 468 , bitfield table updated. 7396 7210 rfo dmac: fc: flow control on page 531 , removed last four lines from bitfield table. section 32.4.1 basic definitions , added programmable arbitration policy. 7353 7366 external memories: section 27.8.7 8-bit nand flash with nfd0_on_d16 = 1 section 27.8.7.2 sof tware configuration , added the line: configure the piod controller to assign... rfo
1123 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 hsmci: table 35-7, register mapping and section 35.14.20 hsmci fifox memory aperture , hsmci_fifox offset updated. 7253 matrix: section 26-5 chip configuration user interface , ccfg_ebicsa offset values revised. rfo pio: figure 23-3, i/o line control logic , table 23-2, register mapping , pio input filter slow clock disable register , pio input filter slow clock enable register , pio input filter slow clock status register ,updated ifsxx register acronyms. table 23-2, register mapping , pio i/o drive register 1 and pio i/o drive register 2 added to datasheet. 6787 6876, 7255 pmc: section 22.12 power management controller (pmc) user interface , pllb is usable as input clock. section 22-3 register mapping , offset 0x0038 updated with usb clock register (pmc_usb). section 22.5 processor clock controller , revised. section 22.12.10 pmc clock generator pllb register , removed usbdiv bitfields. section 22.12.12 usb clock register , added to datasheet. 7304 rfo 7369 rfo pmeec: errie, errid, errim bitfields are 1 bit wide. see: section 28.6.8 pmecc inte rrupt enable register , section 28.6.9 pmecc interrupt disable register and section 28.6.10 pmecc interrupt mask register . 7202 pmerrloc: table 29-3, register mapping pmecc sigma 24 is located at 0x088. section 29.5.10 error location sigmax register , updated. 7203 sckc: section 20. slow clock controller (sckc) , added to datasheet. rfo smc: table 30-1, i/o line description , replaced ncs[7:0] by ncs[5:0] rfo spi: section 36.8.9 spi chip select register , scbr: serial clock baud rate , data transfer note added. section 36.8.3 spi receive data register added requirements to bitfield pcs: peripheral chip select . section 36.8.9 spi chip select register , bits: bits per transfer , bitfield table; descr iption column revised. section 36.7.3.5 peripheral selection , added paragraph at end of the section. 7247 7319 7267 tc: section 37.7.5 tc channel mode register: waveform mode , updated wavsel bitfield table. tc counter value register , tc register a , tc register b , tc register c all bitfields are filled. figure 37-5, capture mode and fi gure 37-6, waveform mode , revise the counter component. 7190 7318 trng: section 47.2 embedded characteristics , removed 133 mhz clock frequency. section 47.3.1 trng control register , added key bitfield. rfo 5914 twi: section 39.8.7 using the dma controller (dmac) , added to the datasheet. 7306 doc. rev 11063c comments (continued) change request ref.
1124 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 udp: section 33.4 product dependencies , second paragraph removed. section 33.5 typical connection , revised schematic and vbus monitoring. section 33.6.3.2 enter ing attached state , revised, replaced paragraphs before warning . section 33.7.12 udp transceiver control register , bit field 9 is dedicated to puon. 7322 uhp: section 34-1 block diagram , removed warning . section 34.6 typical connection , revised schematic and text. 7322 usart: melange of references to pdc/dma remove d in favor of dma implementation. 7284 uart: section 41-1 uart functional block diagram , revised. 7285 electrical characteristics: table 48-7, main oscillator characteristics , revised schematic in note below table. table 48-11, 32 khz oscillator characteristics , revised schematic in note below table. 7304 table 48-5, processor clo ck waveform parameters , updated. table 48-6, system clock waveform parameters , replaces master clock waveform parameters. section 48.12 smc timings , added to datasheet. section 48.13 ddrsdrc timings , added to datasheet. section 48.14 peripheral timings , added to datasheet. 7334 table 48-2, dc characteristics table 48-3, power consumption for different modes table 48-4, power consumption by peripheral in active mode table 48-17, i/o characteristics former tbds assigned values rfo doc. rev 11063b comments change request ref. table 4-2, bga247 pin description updated. 7271 doc. rev 11063a comments change request ref. first issue doc. rev 11063c comments (continued) change request ref.
i 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 table of contents features ................ ................ .............. ............... ............................ ............ 1 1 description ............ ............................ ............... ............................ ............ 2 2 block diagram ............ ................ ................. ................ ................. ............ 3 3 signal description .............. .............. ............... ............................ ............ 4 4 package and pinout ................. ................ ................. ................ ............... 8 4.1 mechanical overview of the 217-ball bga package .........................................8 4.2 mechanical overview of the 247-ball bga package .........................................8 4.3 217-ball bga package pinout ...........................................................................9 4.4 247-ball bga package pinout .........................................................................15 5 power considerations ........ .............. ............... ............................ .......... 21 5.1 power supplies ................................................................................................21 6 memories ............... ............................ ............... ............................ .......... 22 6.1 memory mapping .............................................................................................23 6.2 embedded memories ......................................................................................23 6.3 external memories overview ...........................................................................24 7 system controller ............. ................ ............... ............................ .......... 26 7.1 system controller mapping .............................................................................26 7.2 system controller block diagram ...................................................................27 7.3 chip identification ............................................................................................28 7.4 backup section ................................................................................................28 8 peripherals ............ ............................ ............... ............................ .......... 29 8.1 peripheral mapping .........................................................................................29 8.2 peripheral identifiers ........................................................................................29 8.3 peripheral interrupts and clock control ..........................................................30 8.4 peripheral signal multiplexing on i/o lines .....................................................30 8.5 fuse box features ..........................................................................................32 9 arm926ej-s processor overview .............. ............................... .......... 33 9.1 description .......................................................................................................33 9.2 embedded characteristics ..............................................................................33 9.3 block diagram .................................................................................................35 9.4 arm9ej-s processor ......................................................................................36
ii 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 9.5 cp15 coprocessor ..........................................................................................44 9.6 memory management unit (mmu) ..................................................................46 9.7 caches and write buffer .................................................................................47 9.8 bus interface unit ............................................................................................50 10 debug and test ............... ................ ............................................. .......... 51 10.1 description .......................................................................................................51 10.2 embedded characteristics ..............................................................................51 10.3 block diagram .................................................................................................52 10.4 application examples ......................................................................................53 10.5 debug and test pin description ......................................................................54 10.6 functional description .....................................................................................55 11 advanced interrupt controller (aic) .............. ............................ .......... 59 11.1 description .......................................................................................................59 11.2 embedded characteristics ..............................................................................59 11.3 block diagram .................................................................................................60 11.4 application block diagram ...............................................................................60 11.5 aic detailed block diagram ............................................................................61 11.6 i/o line description .........................................................................................61 11.7 product dependencies ....................................................................................61 11.8 functional description .....................................................................................62 11.9 write protection registers ...............................................................................72 11.10 advanced interrupt controller (aic) user interface .........................................73 12 boot strategies ............... ................ ............................................. .......... 95 12.1 12.1 sam9cn12 only ......................................................................................95 12.2 12.2 SAM9CN11 and sam9n12 only ..............................................................95 13 boot sequence controller (bsc) .......... ................. ................ ............. 113 13.1 description .....................................................................................................113 13.2 embedded characteristics ............................................................................113 13.3 product dependencies ..................................................................................113 13.4 boot sequence controller (bsc) user interface ..........................................113 14 reset controller (rstc) .... ............. .......................................... ........... 115 14.1 description .....................................................................................................115 14.2 embedded characteristics ............................................................................115 14.3 block diagram ...............................................................................................115
iii 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 14.4 functional description ...................................................................................116 14.5 reset controller (rstc) user interface ........................................................124 15 real time clock (rtc) ....... .............. ............... ............................ ........ 129 15.1 description .....................................................................................................129 15.2 embedded characteristics ............................................................................129 15.3 block diagram ...............................................................................................129 15.4 product dependencies ..................................................................................129 15.5 functional description ...................................................................................130 15.6 real time clock (rtc) user interface ........................................................133 16 periodic interval time r (pit) ............... ............................ ............ ........ 147 16.1 description .....................................................................................................147 16.2 embedded characteristics ............................................................................147 16.3 block diagram ...............................................................................................147 16.4 functional description ...................................................................................148 16.5 periodic interval timer (pit) user interface ..................................................150 17 watchdog timer (wdt) ......... ................ ................. ................ ............. 155 17.1 description .....................................................................................................155 17.2 embedded characteristics ............................................................................155 17.3 block diagram ...............................................................................................155 17.4 functional description ...................................................................................156 17.5 watchdog timer (wdt) user interface .........................................................158 18 shutdown controller (shdwc ) .............. ................. ................ ........... 163 18.1 description .....................................................................................................163 18.2 embedded characteristics ............................................................................163 18.3 block diagram ...............................................................................................163 18.4 i/o lines description .....................................................................................163 18.5 product dependencies ..................................................................................164 18.6 functional description ...................................................................................164 18.7 shutdown controller (shdwc) user interface .............................................165 19 general purpose backup regi sters (gpbr) ............ .............. ........... 169 19.1 description .....................................................................................................169 19.2 embedded characteristics ............................................................................169 19.3 general purpose backup registers (gpbr) user interface ........................169 20 slow clock controller (sckc ) .............. ................. ................ ............. 171
iv 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 20.1 description .....................................................................................................171 20.2 embedded characteristics ............................................................................171 20.3 block diagram ...............................................................................................172 20.4 slow clock configuration (sckc) user interface ........................................173 21 clock generator ................ ........................................................ ........... 175 21.1 description .....................................................................................................175 21.2 embedded characteristics ............................................................................175 21.3 block diagram ...............................................................................................176 21.4 slow clock selection .....................................................................................177 21.5 main clock .....................................................................................................180 21.6 divider and pll block ...................................................................................182 22 power management controller (pmc) .... ................. ................ ........... 184 22.1 description .....................................................................................................184 22.2 embedded characteristics ............................................................................184 22.3 block diagram ...............................................................................................185 22.4 master clock controller .................................................................................185 22.5 processor clock controller ............................................................................185 22.6 usb device and host clocks ........................................................................186 22.7 lp-ddr/ddr2 clock ....................................................................................186 22.8 peripheral clock controller ............................................................................186 22.9 programmable clock output controller .........................................................187 22.10 programming sequence ................................................................................187 22.11 clock switching details .................................................................................192 22.12 power management controller (pmc) user interface ...................................195 23 parallel input/output contro ller (pio) ......... ............................ ........... 219 23.1 description .....................................................................................................219 23.2 embedded characteristics ............................................................................219 23.3 block diagram ...............................................................................................220 23.4 product dependencies ..................................................................................221 23.5 functional description ...................................................................................222 23.6 i/o lines programming example ...................................................................233 23.7 parallel input/output controller (pio) user interface ....................................234 24 debug unit (dbgu) .. ................................ ................. ................ ........... 269 24.1 description .....................................................................................................269 24.2 embedded characteristics ............................................................................269
v 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 24.3 block diagram ...............................................................................................271 24.4 product dependencies ..................................................................................272 24.5 uart operations ..........................................................................................272 24.6 debug unit (dbgu) user interface ...............................................................279 25 umc fuse controller .......... .............. ............... ............................ ........ 295 25.1 description .....................................................................................................295 25.2 embedded characteristics ............................................................................295 25.3 block diagram ...............................................................................................295 25.4 functional description ...................................................................................296 25.5 fuse controller (fuse) user interface .........................................................298 26 bus matrix (matrix) ........ ........................................................ ........... 305 26.1 description .....................................................................................................305 26.2 embedded characteristics ............................................................................305 26.3 matrix masters ...............................................................................................306 26.4 matrix slaves .................................................................................................306 26.5 master to slave access .................................................................................306 26.6 memory mapping ...........................................................................................307 26.7 special bus granting mechanism .................................................................307 26.8 arbitration ......................................................................................................308 26.9 write protect registers ..................................................................................311 26.10 bus matrix (matrix) user interface .............................................................312 27 external memories ............ ........................................................ ........... 323 27.1 description .....................................................................................................323 27.2 embedded characteristics ............................................................................323 27.3 ebi block diagram ........................................................................................324 27.4 i/o lines description .....................................................................................325 27.5 application example ......................................................................................326 27.6 product dependencies ..................................................................................329 27.7 functional description ...................................................................................329 27.8 implementation examples .............................................................................332 28 programmable multibit ecc cont roller (pmecc) for mlc devices 341 28.1 description .....................................................................................................341 28.2 embedded characteristics ............................................................................341 28.3 block diagram ...............................................................................................342 28.4 functional description ...................................................................................342
vi 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 28.5 software implementation ...............................................................................349 28.6 programmable multibit ecc controller (pmecc) user interface .................354 29 programmable multibit ecc error location controller (pmerrloc) .............. ................ ................. ................ .............. ........... 371 29.1 description .....................................................................................................371 29.2 embedded characteristics ............................................................................371 29.3 block diagram ...............................................................................................371 29.4 functional description ...................................................................................372 29.5 programmable multibit ecc error location (pmerrloc) user interface ...373 30 static memory controller (smc) ........... ................. ................ ............. 385 30.1 description .....................................................................................................385 30.2 embedded characteristics ............................................................................385 30.3 i/o lines description .....................................................................................386 30.4 multiplexed signals ........................................................................................386 30.5 application example ......................................................................................387 30.6 product dependencies ..................................................................................387 30.7 external memory mapping .............................................................................388 30.8 connection to external devices ....................................................................388 30.9 standard read and write protocols ..............................................................393 30.10 automatic wait states ...................................................................................401 30.11 data float wait states ...................................................................................405 30.12 external wait .................................................................................................409 30.13 slow clock mode ...........................................................................................415 30.14 asynchronous page mode ............................................................................418 30.15 programmable io delays ..............................................................................421 30.16 static memory controller (smc) user interface ............................................422 31 ddr sdr sdram controll er (ddrsdrc) ............... .............. ........... 431 31.1 description .....................................................................................................431 31.2 embedded characteristics ............................................................................431 31.3 ddrsdrc module diagram .........................................................................433 31.4 initialization sequence ...................................................................................434 31.5 functional description ...................................................................................439 31.6 software interface/sdram organization, address mapping ........................457 31.7 ddr sdr sdram controller (ddrsdrc) user interface ...........................461 32 dma controller (dmac) ................. .......................................... ........... 479
vii 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 32.1 description .....................................................................................................479 32.2 embedded characteristics ............................................................................479 32.3 block diagram ...............................................................................................481 32.4 functional description ...................................................................................482 32.5 dmac software requirements .....................................................................509 32.6 write protection registers .............................................................................511 32.7 dma controller (dmac) user interface ........................................................512 33 usb device port (udp) ....... .............. ............... ............................ ........ 539 33.1 description .....................................................................................................539 33.2 embedded characteristics ............................................................................539 33.3 block diagram ...............................................................................................540 33.4 product dependencies ..................................................................................540 33.5 typical connection ........................................................................................541 33.6 functional description ...................................................................................542 33.7 usb device port (udp) user interface .........................................................556 34 usb host port (uhp) ....... ........................................................ ........... 577 34.1 description .....................................................................................................577 34.2 embedded characteristics ............................................................................577 34.3 block diagram ...............................................................................................578 34.4 product dependencies ..................................................................................579 34.5 functional description ...................................................................................579 34.6 typical connection ........................................................................................582 35 high speed multimedia card interface (hsmci) ....... .............. ........... 583 35.1 description .....................................................................................................583 35.2 embedded characteristics ............................................................................583 35.3 block diagram ...............................................................................................584 35.4 application block diagram .............................................................................584 35.5 pin name list ................................................................................................585 35.6 product dependencies ..................................................................................585 35.7 bus topology .................................................................................................585 35.8 high speed multimediacard operations .......................................................588 35.9 sd/sdio card operation ..............................................................................606 35.10 ce-ata operation .........................................................................................607 35.11 hsmci boot operation mode ........................................................................608 35.12 hsmci transfer done timings .....................................................................610
viii 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 35.13 write protection registers .............................................................................611 35.14 high speed multimediacard interface (hsmci) user interface ....................612 36 serial peripheral interface (spi) ................ ................ .............. ........... 641 36.1 description .....................................................................................................641 36.2 embedded characteristics ............................................................................641 36.3 block diagram ...............................................................................................642 36.4 application block diagram .............................................................................643 36.5 signal description .........................................................................................643 36.6 product dependencies ..................................................................................644 36.7 functional description ...................................................................................645 36.8 serial peripheral interface (spi) user interface ............................................659 37 timer counter (tc) ........... ........................................................ ........... 675 37.1 description .....................................................................................................675 37.2 embedded characteristics ............................................................................675 37.3 block diagram ...............................................................................................676 37.4 pin name list ................................................................................................677 37.5 product dependencies ..................................................................................677 37.6 functional description ...................................................................................678 37.7 timer counter (tc) user interface ................................................................691 38 pulse width modulation c ontroller (pwm) . ............................ ........... 709 38.1 description .....................................................................................................709 38.2 embedded characteristics ............................................................................709 38.3 block diagram ...............................................................................................710 38.4 i/o lines description .....................................................................................710 38.5 product dependencies ..................................................................................710 38.6 functional description ...................................................................................711 38.7 pulse width modulation controller (pwm) user interface ............................720 39 two-wire interface (twi) .... .............. ............... ............................ ........ 733 39.1 description .....................................................................................................733 39.2 embedded characteristics ............................................................................733 39.3 list of abbreviations ......................................................................................734 39.4 block diagram ...............................................................................................734 39.5 application block diagram .............................................................................735 39.6 product dependencies ..................................................................................735 39.7 functional description ...................................................................................736
ix 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 39.8 master mode ..................................................................................................737 39.9 multi-master mode .........................................................................................749 39.10 slave mode ....................................................................................................752 39.11 two-wire interface (twi) user interface .......................................................760 40 universal synchronous asynchr onous receiver transmitter (usart) ................. ................. ................ ................. ................ ............. 775 40.1 description .....................................................................................................775 40.2 embedded characteristics ............................................................................775 40.3 block diagram ...............................................................................................777 40.4 application block diagram .............................................................................778 40.5 i/o lines description ....................................................................................778 40.6 product dependencies ..................................................................................779 40.7 functional description ...................................................................................780 40.8 universal synchronous asynch ronous receiver transmitter (usart) user interface ...............................................................................................830 41 universal asynchronous receiver tra nsceiver (uart) ... ............... 873 41.1 description .....................................................................................................873 41.2 embedded characteristics ............................................................................873 41.3 block diagram ...............................................................................................874 41.4 product dependencies ..................................................................................874 41.5 uart operations ..........................................................................................875 41.6 universal asynchronous receiver transmitter (uart) user interface ........881 42 analog-to-digital converte r (adc) ....... ................. ................ ............. 891 42.1 description .....................................................................................................891 42.2 embedded characteristics ............................................................................891 42.3 block diagram ...............................................................................................892 42.4 signal description ..........................................................................................892 42.5 product dependencies ..................................................................................893 42.6 functional description ...................................................................................894 42.7 touchscreen ..................................................................................................898 42.8 analog-to-digital converter (adc) user interface .........................................913 43 synchronous serial controller (ssc) .... ................. ................ ........... 943 43.1 description .....................................................................................................943 43.2 embedded characteristics ............................................................................943 43.3 block diagram ...............................................................................................944
x 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 43.4 application block diagram .............................................................................944 43.5 pin name list ................................................................................................945 43.6 product dependencies ..................................................................................945 43.7 functional description ...................................................................................946 43.8 ssc application examples ............................................................................957 43.9 synchronous serial controller (ssc) user interface ....................................960 44 lcd controller (lcdc) .......... ................ ................. ................ ............. 985 44.1 description .....................................................................................................985 44.2 embedded characteristics ............................................................................985 44.3 block diagram ...............................................................................................986 44.4 i/o lines description .....................................................................................987 44.5 product dependencies ..................................................................................987 44.6 functional description ...................................................................................989 44.7 lcd controller (lcdc) user interface ........................................................1003 45 advanced encryption standard (aes) ........... ......................... ......... 1037 45.1 description ...................................................................................................1037 45.2 embedded characteristics ..........................................................................1037 45.3 product dependencies ................................................................................1037 45.4 functional description .................................................................................1038 45.5 security features ........................................................................................1044 45.6 advanced encryption st andard (aes) user interfac e ........... ................ ......1045 46 secure hash algorithm (sha ) .............. ................. ................ ........... 1059 46.1 description ...................................................................................................1059 46.2 embedded characteristics ..........................................................................1059 46.3 product dependencies ................................................................................1059 46.4 functional description .................................................................................1060 46.5 secure hash algorithm (sha) user interface .............................................1064 47 true random number generator (trng) ............... .............. ........... 1073 47.1 description ...................................................................................................1073 47.2 embedded characteristics ..........................................................................1073 47.3 true random number generator (trng) user interface ..........................1074 48 electrical characteristics ... ................. ................ ................. ............. 1081 48.1 absolute maximum ratings .........................................................................1081 48.2 dc characteristics .......................................................................................1081
xi 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12 48.3 power consumption ....................................................................................1083 48.4 clock characteristics ...................................................................................1085 48.5 12 mhz rc oscillator characteristics .........................................................1088 48.6 32 khz oscillator characteristics .................................................................1088 48.7 32 khz rc oscillator characteristics ..........................................................1090 48.8 pll characteristics .....................................................................................1091 48.9 i/os ..............................................................................................................1091 48.10 analog-to-digital converter (adc) ..............................................................1092 48.11 core power supply por characteristics ....................................................1093 48.12 smc timings ...............................................................................................1093 48.13 ddrsdrc timings .....................................................................................1098 48.14 peripheral timings .......................................................................................1098 49 mechanical overview of the 217-ball and 247-ball bga packages 1110 49.1 217-ball bga package ................................................................................1110 49.2 247-ball bga package ................................................................................1112 50 sam9n12/SAM9CN11/sam9cn12 orde ring information ............... 1115 51 at91sam9cn12 series errata .............. ................. ................ ........... 1117 51.1 marking ........................................................................................................1117 51.2 at91sam9n12/cn11/cn12 errata ............................................................1117 revision history........ ................................ ............................... ........... 1119 table of contents.......... ................. ................ ................. ................ ........... i
xii 11063gCatarmC09-oct-12 sam9n12/SAM9CN11/sam9cn12
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