1
2
3
4
5
6
7
8
9
10
11
12
13
14 28
27
26
25
24
23
22
21
20
19
18
17
16
15 ainl + in
ainl _ in
v ref in
tst1 in/out
sel18 in
pd in
tst2 in
cmode in
smode in
l/ r in/out ainr + in
ainr _ in
v ref out
tst4 in
tst3 in/out
clk in
fsync in/out
sdata out
sclk in/out av dd
26
16
15
17
14 1
2
28
27
3
9
10
20
12
13
8
11
21
22 ainl +
ainl _
ainr +
ainr _
v ref in
sel18
pd
clk
cmode
smode
tst1
tst2
tst3
tst4
v ref
sdata
sclk
fsync
l/r av dd , agnd
dv dd , dgnd : for analog block
: for digital block agnd
nc
nc nc nc
dgnd dv dd dv dd AK5340-VS ( 1/3 )
il08 c-mos 18-bit 2 channel a/d converter
?op view
AK5340-VS ( 2/3 ) input
ainl +
ainl _
ainr +
ainr _
clk
cmode
pd
sel 18
smode
tst 2, 4
v ref in
output
sdata
v ref
input/output
fsync
l/ r
sclk
tst 1, 3
; l-ch analog positive input
; l-ch analog negative input
; r-ch analog positive input
; r-ch analog negative input
; master clock
( cmode = h : 384 fs )
( cmode = l : 256 fs )
; master clock select
( l : clk = 256 fs, 12.288 mhz @fs = 48 khz )
( h : clk = 384 fs, 18.432 mhz @fs = 48 khz )
; power down for digital section
; 18/16 bit select ( l : 16-bit, h : 18-bit )
; interface clock select
( l : sub mode )
( h : master mode )
; test
; reference voltage
; serial data
; reference voltage ( _ 2.5v )
; frame sync clock
( sub mode : fsync input )
( master mode : fsync output )
; input channel select
( sub mode : fs clk input )
( master mode : fs clk output )
; serial data clock
( sub mode : sclk input )
( master mode : sclk output )
; test
voltage reference controller calibration
s-ram decimation filter decimation filter analog block digital block dac serial
output
i/f low pass
filter + _ 1
2 26 vref 28
27 ainl +
ainl _ + _ dac ainr +
ainr _ 9
10
20
8
11
21
22
12
13 15 sclk 14 l/r 17 fsync 16 sdata sel 18
pd
clk
tst 1
tst 2
tst 3
tst 4
cmode
smode AK5340-VS ( 3/3 ) 3 vref in low pass
filter + _ + _ + _ + _
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