View MAX5981AETE_5350482.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5981a/max5981b _______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. general description the max5981 provides a com plete interface for a pow - ered device (pd) to comply with the ieee ? 802.3af/at standard in a power-over-ethernet (poe) system. the max5981 provides the pd with a detection signature, classifica tion signature, and an integrated isolation power switch with inrush current control. during the inrush period, the max5981 limits the current to less than 180ma before switching to the higher cur rent limit (720ma to 880ma) when the isolation power mosfet is fully enhanced. the device features an input uvlo with wide hysteresis and long deglitch time to compensate for twisted-pair cable resistive drop and to assure glitch-free transition during power-on/-off condi tions. the max5981 can with stand up to 100v at the input. the max5981 supports a 2-event classification method as specified in the ieee 802.3at standard and provides a signal to indicate when probed by a type 2 power sourc - ing equipment (pse). the device detects the presence of a wall adapter power source connection and allows a smooth switch over from the poe power source to the wall power adapter. the max5981 also provides a power-good (pg) signal, two-step current limit and fold back, overtemperature protection, and di/dt limit. a sleep mode feature in the max5981 provides low power consumption while supporting maintain power signature (mps). an ultra- low-power sleep mode feature in the max5981 further reduces power consump tion while still supporting mps. the max5981 also features an led driver that is auto - matically activated during sleep mode. during sleep mode, the led driver sources a peri odic current (i led ) at 250hz (max5981a) or 15.625khz (max5981b). the max5981 is available in a 16-pin, 5mm x 5mm tqfn power package. the device is rated over the -40c to +85c extended temperature range. features s sleep mode and ultra-low power s ieee 802.3af/at compliant s 2-event classification or an external wall adapter indicator output s simplified wall adapter interface s poe classification 0C5 s 100v input absolute maximum rating s inrush current limit of 180ma maximum s current limit during normal operation between 720ma and 880ma s current limit and foldback s legacy uvlo at 36v s led driver with programmable led current s overtemperature protection s thermally enhanced, 5mm x 5mm, 16-pin tqfn applications ieee 802.3af/at powered devices ip phones, wireless access nodes, ip security cameras wimax k base stations 19-5732; rev 2; 8/11 + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. ordering information wimax is a trademark of wimax forum. ieee is a registered service mark of the institute of electrical and electronics engineers, inc. part temp range pin- package sleep mode max5981a ete+ -40 n c to +85 n c 16 tqfn-ep* yes max5981b ete+ -40 n c to +85 n c 16 tqfn-ep* yes
ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5981a/max5981b 2 ______________________________________________________________________________________ stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to v ss .......................................................... -0.3v to +100v det, rtn, wad, pg, 2ec to v ss ....................... -0.3v to +100v cls, sl , wk , ulp, led to v ss ............................... -0.3v to +6v maximum current on cls (100ms maximum) ................. 100ma continuous power dissipation (t a = +70 n c) (note 1) tqfn (derate 28.6mw/ n c above +70 n c) multilayer board ..................................................... 2285.7mw package thermal resistance (note 2) b ja ............................................................................... 35 n c/w b jc ............................................................................. 2.7 n c/w operating temperature range .......................... -40 n c to +85 n c maximum junction temperature ..................................... +150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) .............................. +300 n c soldering temperature ................................................. +260 n c electrical characteristics (v in = (v dd - v ss ) = 48v, r det = 24.9k, r cls = 615, and r sl = 60.4k. rtn, wad, pg, 2ec , wk , and ulp unconnected, all voltages are referenced to v ss, unless otherwise noted. t a = t j = -40 n c to +85 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 3) absolute maximum ratings note 1: maximum power dissipation is obtained using jedec jesd51-5 and jesd51-7 specifications. note 2: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . parameter symbol conditions min typ max units detection mode input offset current i offset v in = 1.4v to 10.1v (note 4) 10 f a effective differential input resistance dr v in = 1.4v up to 10.1v with 1v step, v dd = rtn = wad = pg = 2ec (note 5) 23.95 25.00 25.50 k i classification mode classification disable threshold v th,cls v in rising (note 6) 22.0 22.8 23.6 v classification stability time 0.2 ms classification current i class v in = 12.5v to 20.5v, v dd = rtn = wad = pg = 2ec class 0, r cls = 619 i 0 3.96 ma class 1, r cls = 117 i 9.12 11.88 class 2, r cls = 66.5 i 17.2 19.8 class 3, r cls = 43.7 i 26.3 29.7 class 4, r cls = 30.9 i 36.4 43.6 class 5, r cls = 21.3 i 52.7 63.3 type 2 (802.3at) classification mode mark event threshold v thm v in falling 10.1 10.7 11.6 v hysteresis on mark event threshold 0.84 v mark event current i mark v in falling to enter mark event, 5.2v p v in p 10.1v 0.25 0.85 ma reset event threshold v thr v in falling 2.8 4 5.2 v power mode v in supply voltage range 60 v v in supply current i q 0.27 0.55 ma
ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5981a/max5981b _______________________________________________________________________________________ 3 electrical characteristics (continued) (v in = (v dd - v ss ) = 48v, r det = 24.9k, r cls = 615, and r sl = 60.4k. rtn, wad, pg, 2ec , wk , and ulp unconnected, all voltages are referenced to v ss, unless otherwise noted. t a = t j = -40 n c to +85 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 3) parameter symbol conditions min typ max units v in turn-on voltage v on v in rising 34.3 35.4 36.6 v v in turn-off voltage v off v in falling 30 v v in turn-on/-off hysteresis v hyst_ uvlo (note 7) 4.2 v v in deglitch time t off_dly v in falling from 40v to 20v (note 8) 30 120 f s inrush to operating mode delay t delay t delay = minimum pg current pulse width after entering into power mode 87 96 105 ms isolation power mosfet on-resistance r on_iso i rtn = 600ma t j = +25 n c 0.5 0.7 i t j = +85 n c 0.65 1 t j = +125 n c 0.8 rtn leakage current i rtn_lkg v rtn = 12.5v to 30v 10 f a current limit inrush current limit i inrush during initial turn-on period, v rtn = 1.5v 90 135 180 ma current limit during normal operation i lim after inrush completed, v rtn = 1v 720 800 880 ma foldback threshold v rtn (note 9) 13 16.5 v logic wad detection threshold v wad-ref v wad rising, v in = 14v to 48v (referenced to rtn) 8 9 10 v wad detection threshold hysteresis v wad falling, v rtn = 0v, v ss unconnected 0.725 v wad input current i wad-lkg v wad = 10v (referenced to rtn) 3.5 f a 2ec sink current v 2ec = 3.5v (referenced to rtn), v ss disconnected 1 1.5 2.25 ma 2ec off-leakage current v 2ec = 48v 1 f a pg sink current v rtn = 1.5v, v pg = 0.8v, during inrush period 125 230 375 f a pg off-leakage current v pg = 60v 1 f a sleep mode wk and ulp logic threshold v th v wk falling and v ulp rising and falling 1.5 3 v sl logic threshold falling 0.75 0.8 0.85 v sl current r sl = 0 i 140 f a led current amplitude i led r sl = 60.4k i , v led = 3.5v 10 10.5 11.5 ma r sl = 30.2k i , v led = 3.75v 19.5 20.9 22.5 r sl = 30.2k i , v led = 4v 19
ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5981a/max5981b 4 ______________________________________________________________________________________ electrical characteristics (continued) (v in = (v dd - v ss ) = 48v, r det = 24.9k, r cls = 615, and r sl = 60.4k. rtn, wad, pg, 2ec , wk , and ulp unconnected, all voltages are referenced to v ss, unless otherwise noted. t a = t j = -40 n c to +85 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 3) note 3: all devices are 100% production tested at t a = +25 n c. limits over temperature are guaranteed by design. note 4: the input offset current is illustrated in figure 1. note 5: effective differential input resistance is defined as the differential resistance between v dd and v ss . see figure 1. note 6: classification current is turned off whenever the device is in power mode. note 7: uvlo hysteresis is guaranteed by design, not production tested. note 8: a 20v glitch on input voltage, which takes v dd below v on shorter than or equal to t off_dly does not cause the max5981a/max5981b to exit power-on mode. note 9: in power mode, current-limit foldback is used to reduce the power dissipation in the isolation mosfet during an overload condition across v dd and rtn. figure 1. effective differential input resistance/offset current parameter symbol conditions min typ max units led current programmable range 10 20 ma led current with grounded sl v sl = 0v 20.5 24.5 28.5 ma led current frequency f iled normal and ulp sleep mode max5981a 250 hz max5981b 15.625 khz led current duty cycle d iled normal and ulp sleep mode 25 % v dd current amplitude i vdd normal sleep mode, v led = 3.5v 10 11 12 ma internal current duty cycle d ivdd normal and ulp sleep modes 75 % internal current enable time t mps ulp sleep mode 76 84 92 ms internal current disable time t mpdo ulp sleep mode 205 228 250 ms thermal shutdown thermal-shutdown threshold t sd t j rising +140 n c thermal-shutdown hysteresis t j falling 28 n c i in i ini + 1 i ini i offset dr i 1v v ini v ini + 1 i offset = i ini - v ini dr i dr i = (v ini + 1 - v ini ) = 1v (i ini + 1 - i ini ) (i ini + 1 - i ini ) v in
ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5981a/max5981b _______________________________________________________________________________________ 5 typical operating characteristics (v in = (v dd - v ss ) = 54v, r det = 24.9k, r cls = 615, and r sl = 60.4k. rtn, wad, pg, 2ec , wk , and ulp unconnected; all voltages are referenced to v ss. ) detection current vs. input voltage max5981 toc01 v in (v) i in (ma) 8 6 4 2 0.1 0.2 0.3 0.4 0.5 0 0 10 i in = i vdd + i det r det = 25.4ki rtn = 2ec = pg = wad = v dd -40c p t a p +85nc signature resistance vs. input voltage r signature (ki) 8 6 4 2 24.5 25.0 25.5 26.0 24.0 0 10 max5981 toc02 v in (v) i in = i vdd + i det r det = 24.9ki rtn = 2ec = pg = wad = v dd t a = -40nc t a = +85nc t a = +25nc input offset current vs. input voltage input offset current (fa) 8 6 4 2 -2 0 2 4 -4 0 10 max5981 toc03 v in (v) t a = +85nc t a = -40nc t a = +25nc classification current vs. input voltage max5981 toc04 v in (v) i in (ma) 25 20 15 10 5 10 20 30 40 50 60 70 0 0 30 class 5 class 4 class 3 class 2 class 1 class 0 classification settling time max5981 toc05 v in 10v/div i in 200ma/div v cls 1v/div 100fs/div r cls = 30.9 i 2ec sink current vs. 2ec voltage v 2ec (v) i 2ec (ma) 50 40 30 20 10 0.4 0.8 1.2 1.6 2.0 0 0 60 max5981 toc06 v ss floating v 2ec referenced to rtn v wad = 14v t a = -40 n c t a = +85 n c t a = +25 n c pg sink current vs. pg voltage v pg (v) i pg (fa) 50 40 30 20 10 100 150 200 250 300 50 0 60 max5981 toc07 t a = -40nc t a = +85nc t a = +25nc inrush current limit vs. rtn voltage max5981 toc08 v rtn (v) inrush current limit (ma) 50 40 30 20 10 70 90 110 130 150 50 0 60
ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5981a/max5981b 6 ______________________________________________________________________________________ typical operating characteristics (continued) (v in = (v dd - v ss ) = 54v, r det = 24.9k, r cls = 615, and r sl = 60.4k. rtn, wad, pg, 2ec , wk , and ulp unconnected; all voltages are referenced to v ss. ) inrush control waveform with type 2 classification max5981 toc10 0v 0v 0v 0a 0v v rtn 50v/div i rtn 100ma/div v dd 50v/div v pg 10v/div v 2ec 40v/div 20ms/div using typical application circuit 2ec pulled up to v dd with 10ki inrush control waveform with type 2 classification max5981 toc11 v pg 10v/div 0v 0v 0v 0a 0v v rtn 50v/div i rtn 200ma/div v dd 50v/div 20ms/div v 2ec 40v/div using typical application circuit 2ec pulled up to v dd with 10ki led current vs. r sl r sl (ki) i led (ma) 60 55 50 45 40 35 30 25 20 15 10 5 13 16 19 22 25 10 0 65 max5981 toc12 -40nc < t a < +85nc led current vs. led voltage i led (ma) 4 3 2 1 10 15 20 25 5 0 5 max5981 toc13 v led (v) r sl = 60.4ki r sl = 30.2ki normal operation current limit vs. rtn voltage max5981 toc09 v rtn (v) current limit (ma) 50 40 10 20 30 200 300 400 500 600 700 800 900 100 0 60
ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5981a/max5981b _______________________________________________________________________________________ 7 pin description pin name function 1 n.c. no connection. not internally connected. 2 v dd positive supply input. connect a 68nf (min) bypass capacitor between v dd and v ss . 3 det detection resistor input. connect a signature resistor (r det = 24.9k i ) from det to v dd . 4 i.c. internally connected. leave unconnected. 5, 6 v ss negative supply input. v ss connects to the source of the integrated isolation n-channel power mosfet. 7, 8 rtn drain of isolation mosfet. rtn connects to the drain of the integrated isolation n-channel power mosfet. connect rtn to the downstream dc-dc converter ground as shown in the typical application circuit . 9 wad wall power adapter detector input. wall adapter detection is enabled the moment v dd - v ss crosses the mark event threshold. detection occurs when the voltage from wad to rtn is greater than 9v. when a wall power adapter is present, the isolation n-channel power mosfet turns off, 2ec current sink turns on. connect wad directly to rtn when the wall power adapter or other auxiliary power source is not used. 10 pg open-drain power-good indicator output. pg sinks 230 f a to disable the downstream dc-dc converter while turning on the hot-swap mosfet switch. pg current sink is disabled during detection, classifica - tion, and in the steady-state power mode. the pg current sink is turned on to disable the downstream dc-dc converter when the device is in sleep mode. pin configuration 3 4 2 1 10 9 11 v ss rtn v ss ep* led 5 6 v dd 8 16 15 13 det i.c. cls 2ec pg wad max5981a max5981b rtn 7 14 n.c. tqfn 12 ulp wk sl connect to v ss . + top view
ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5981a/max5981b 8 ______________________________________________________________________________________ pin description (continued) pin name function 11 2ec 2-event classification detect or wall adapter detect output. a 1.5ma current sink is enabled at 2ec when a type 2 pse or a wall adapter is detected. when powered by a type 2 pse, the 2ec current sink is enabled after the isolation mosfet is fully on until v in drops below the uvlo threshold. 2ec is latched when powered by a type 2 pse until v in drops below the reset threshold. 2ec also asserts when a wall adapter supply, typically greater than 9v, is applied between wad and rtn. 2ec is not latched if asserted by wad. the 2ec current sink is turned off when the device is in sleep mode. 12 cls classification resistor input. connect a resistor (r cls ) from cls to v ss to set the desired classification current. see the classification current specifications in the electrical characteristics table to find the resistor value for a particular pd classification. 13 led led driver output. during sleep mode, led sources a periodic current (i led ). the amplitude of i led is set by r sl according to the formula i led (in a) = 645.75/(r sl + 1200). 14 sl sleep mode enable input. a falling edge on sl brings the device into sleep mode (v sl must drop below 0.75v). an external resistor (r sl ) connected between sl and v ss sets the led current (i led ). 15 wk wake mode enable input. wk has an internal 2.5k i pullup resistor to the internal 5v bias rail. a falling edge on wk brings the device out of sleep mode and into the normal operating mode (wake mode). 16 ulp ultra-low-power enable input (in sleep mode). ulp has an internal 50k i pullup resistor to the internal 5v bias rail. a falling edge on sl while ulp is asserted low enables ultra-low-power mode. when ultra- low-power mode is enabled, the power consumption of the device is reduced even lower than normal sleep while still supporting mps. CC ep exposed pad. do not use ep as an electrical connection to v ss . ep is internally connected to v ss through a resistive path and must be connected to v ss externally. to optimize power dissipation, solder the exposed pad to a large copper power plane.
ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5981a/max5981b _______________________________________________________________________________________ 9 simplified block diagram 1.5ma 46a v dd en cls 2ec v dd 5v d q q set clr det v ss 5v regulato r thermal shutdown q r s v dd v dd v dd wad rtn led v on /v off v dd d q q set clr 9v 230a pg classification i sw it ch logic k x i sw it ch isolation switch s mux i0 i1 1/k max5981a max5981b sl wk ulp 5v 50ki 5v 2.5ki t delay
ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5981a/max5981b 10 _____________________________________________________________________________________ typical operating circuit 2-event classification detection -54v max5981a max5981b 1ki v dd rtn wad pg 2ec/wad 2ec 24v/48v battery 1.5ma wk sl ulp led -54v -54v -54v isolated sleep mode input isolated ulp mode input 68nf rj-4 5 and bridge rectifier gnd smaj58a r det 24.9ki r cls v ss det cls enable dc-dc converter in+ in- gnd
ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5981a/max5981b ______________________________________________________________________________________ 11 detailed description operating modes depending on the input voltage (v in = v dd - v ss ), the max5981 operates in four differ ent modes: pd detec - tion, pd classification, mark event, and pd power. the devices enter pd detection mode when the input voltage is between 1.4v and 10.1v. the device enters pd clas - sification mode when the input voltage is between 12.6v and 20v. the device enters pd power mode once the input voltage exceeds v on . detection mode (1.4v p v in p 10.1v) in detection mode, the power source equipment (pse) applies two voltages on v in in the 1.4v to 10.1v range (1v step minimum) and then records the current measure ments at the two points. the pse then computes dv/di to ensure the presence of the 24.9k i signature resistor. connect the signature resistor (r det ) from v dd to det for proper signature detection. the max5981 pulls det low in detection mode. det goes high imped - ance when the input voltage exceeds 12.5v. in detection mode, most of the max5981 internal circuitry is off and the offset current is less than 10a. if the voltage applied to the pd is reversed, install pro - tection diodes at the input terminal to prevent internal damage to the max5981 (see the typical application circuit ). since the pse uses a slope technique (dv/di) to calculate the signature resistance, the dc offset due to the protection diodes is subtracted and does not affect the detection process. classification mode (12.6v p v in p 20v) in the classification mode, the pse classifies the pd based on the power consumption required by the pd. this allows the pse to efficiently manage power distribu - tion. class 0C5 is defined as shown in table 1. (the ieee 802.3af/at standard defines only class 0C4 and class 5 for any spe cial requirement.) an external resistor (r cls ) connected from cls to v ss sets the classification current. the pse determines the class of a pd by applying a volt - age at the pd input and measuring the current sourced out of the pse. when the pse applies a voltage between 12.6v and 20v, the max5981a/max5981b exhibit a cur - rent characteristic with a value shown in table 1. the pse uses the classification current informa tion to classify the power requirement of the pd. the classification cur - rent includes the current drawn by r cls and the supply current of the max5981a/max5981b so the total current drawn by the pd is within the ieee 802.3af/at standard figures. the classification current is turned off whenever the device is in power mode. 2-event classification and detection during 2-event classification, a type 2 pse probes pd for classification twice. in the first classification event, the pse presents an input voltage between 12.6v and 20.5v and the max5981a/max5981b pres ent the pro - grammed load i class . the pse then drops the probing voltage below the mark event threshold of 10.1v and the max5981a/max5981b pres ent the mark current (i mark ). this sequence is repeated one more time. when the max5981a/max5981b are pow ered by a type 2 pse, the 2-event identification output 2ec asserts low after the internal isolation n-channel mosfet is fully turned on. 2ec current sink is turned off when v dd goes below the uvlo threshold (v off ) and turns on when v dd goes above the uvlo threshold (v on ), unless v dd goes below vthr to reset the latched output of the table 1. setting classification current * v in is measured across the max5981a/max5981b input v dd to v ss . class maximum power used by pd (w) r cls ( i ) v in * (v) class current seen at v in (ma) ieee 802.3at pd classification current specification (ma) min max min max 0 0.44 to 12.95 615 12.6 to 20 0 4 0 5 1 0.44 to 3.84 117 12.6 to 20 9 12 8 13 2 3.84 to 6.49 66.5 12.6 to 20 17 20 16 21 3 6.49 to 12.95 43.7 12.6 to 20 26 30 25 31 4 12.95 to 25.5 30.9 12.6 to 20 36 44 35 45 5 > 25.5 21.3 12.6 to 20 54 64 51 68
ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5981a/max5981b 12 _____________________________________________________________________________________ type 2 pse detection flag. alternatively, the 2ec output also serves as a wall adapt er detection output when the max5981a/max5981b are powered by an external wall power adapter. see the wall power adapter detection and operation section for more information. power mode (wake mode) the max5981a/max5981b enter power mode when v in rises above the undervoltage lock out threshold (v on ). when v in rises above v on , the max5981a/max5981b turn on the internal n-channel isolation mosfet to con - nect v ss to rtn with inrush current limit internally set to 135ma (typ). the iso lation mosfet is fully turned on when the voltage at rtn is near v ss and the inrush cur - rent is reduced below the inrush limit. once the isolation mosfet is fully turned on, the max5981a/max5981b change the cur rent limit to 800ma. the open-drain power-good output (pg) remains low for a minimum of t delay until the power mosfet fully turns on to keep the downstream dc-dc converter disabled during inrush. undervoltage lockout the max5981a/max5981b operate up to a 60v supply voltage with a turn-on uvlo threshold (v on ) at 35.4v and a turn-off uvlo threshold (v off ) at 31v. when the input voltage is above v on , the max5981a/max5981b enter power mode and the inter nal mosfet is turned on. when the input voltage goes below v off for more than t off_dly , the mosfet turns off. sleep and ultra-low-power sleep modes the max5981a/max5981b feature a sleep mode, which pulls pg low while keeping the internal n-channel isola - tion mosfet turned on. the pg output is used to dis - able downstream dc-dc converters reducing the power consumption of the overall pd system in sleep mode. in sleep mode, the led driver output (led) sources peri - odic current pulses. the led current i led is set by an external resistor r sl , see the applications information section for more information. an ultra-low-power sleep mode allows the max5981a/ max5981b to further reduce power consumption while maintaining the power signature of the standard. the ultra-low-power enable input ulp is internally held high with a 50k i pullup resistor to the internal 5v bias of the max5981a/max5981b. set ulp to logic-low and apply a falling edge to sl to enable ultra-low-power sleep mode. apply a falling edge on the wake-mode enable input ( wk ) to disable sleep or ultra-low-power sleep mode and resume normal operation. led driver the max5981a/max5981b drive an led connected from the output led to v ss . during sleep mode/ultra-low- power sleep mode, the led is driven by current pulses with the amplitude set by the resistor connected from sl to v ss . the led driver current ampli tude is program - mable from 10ma to 20ma using r sl according to the following formula: led 645.75 i (in amperes) r 1200 = + sl power-good output an open-drain output (pg) is used to allow disabling downstream dc-dc converter until the n-channel isola - tion mosfet is fully turned on. pg is pulled low to v ss for a period of t delay and until the internal isolation mosfet is fully turned on. the pg is also pulled low during sleep mode and coming out of thermal shutdown. thermal-shutdown protection the max5981a/max5981b include thermal protection from excessive heating. if the junction tempera ture exceeds the thermal-shutdown threshold of +140 n c, the max5981a/max5981b turn off the internal power mosfet, led driver, and 2ec current sink. when the junction temperature falls below +112 n c, the device enters inrush mode and then return to power mode. inrush mode ensures the downstream dc-dc converter is turned off as the internal power mosfet is turned on. wall power adapter detection and operation for applications where an auxiliary power source such as a wall power adapter is used to power the pd, the max5981a/max5981b feature wall power adapter detection. the max5981a/max5981b give highest prior - ity to the wad and smooth ly switch the power supply to wad when it is detected. once the input voltage (v dd - v ss ) exceeds the mark event threshold, the max5981a/ max5981b enable wall adapter detection. the wall power adapt er is connected from wad to rtn. the max5981a/max5981b detect the wall power adapter when the voltage from wad to rtn is greater than 9v. when a wall power adapter is detected, the internal n-channel isolation mosfet turns off, 2ec current sink turns on, and classification current is disabled if v in is in the classification range.
ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5981a/max5981b ______________________________________________________________________________________ 13 applications information operation with 12v adapter layout procedure careful pcb layout is critical to achieve high efficiency and low emi. follow these layout guidelines for optimum performance: 1) place the input capacitor, classification resistor, and transient voltage suppressor as close as possible to the max5981a/max5981b. 2) use large smt component pads for power dissipat - ing devices such as the max5981a/max5981b and the external diodes. 3) use short and wide traces for high-power paths. 4) use the max5981a/max5981b evaluation kit layout as a reference. 5) place enough vias in the pad for the ep of the max5981a/max5981b so that heat generated inside can be effectively dissipated by the pcb copper. the recommended spacing for the vias is 1mm to 1.2mm pitch. the thermal vias should be plated (1oz copper) and have a small barrel diameter (0.3mm to 0.33mm). figure 2. typical configuration when using a 12v wall power adapter 68nf 2-event classi fication (asserted on ) enable dc-dc converter in+ in- rj-4 5 and bridge rectifier gnd gnd -54v smaj58a max5981a max5981b r det 24.9ki r cls v dd v ss rtn wad pg det cls 2ec/wad 2ec 12v battery 1.5ma this circuit achieves pro per 2e c logi c wh en battery is < 12.5v
ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5981a/max5981b 14 _____________________________________________________________________________________ typical application circuit 68nf isolated 2-event classification output gnd v ac v ac gnd -54v smaj58a walk mode input max5981a max5981b 24.9ki 43.7i 60.4ki 1ki v dd v ss rtn wad pg pg det cls 2ec/wad 2ec 24/48v battery 1.4ma wk sl ulp led -54v rtn -54v -54v isolated sleep mode input isolated ulp mode input max15000 ulvo/en in v cc uflg fb comp cs pg cs v cc v cc cs rtn isolated +5.3v/2a isolated rtn isolated rtn gnd rtn gnd 33ki 10ki 249i 22.1i 0.75i 1ki 619i 8.2nf 330pf 649i 4.99ki 1ki 100pf 33nf 8.06ki 2.49ki 1ki 18.1ki rtn 4.99ki ndrv gnd rt 51.5ki 1.37mi 0.1f 0.1f 0.1f 0.1f 22f 4.7f 2.2nf 8.06ki
ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5981a/max5981b ______________________________________________________________________________________ 15 package information for the latest package outline information and land patterns, (footprints) go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: bicmos package type package code outline no. land pattern no. 16 tqfn-ep t1655+4 21-0140 90-0121
ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5981a/max5981b maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 16 maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 1/11 initial release 1 8/11 revised general description , absolute maximum ratings , electrical characteristics , pin description , typical operating circuit , led driver section, and typical application circuit . 1C8, 10, 11, 12, 14 2 8/11 revised general description , electrical characteristics , typical operating characteristics , and pin description . 1, 4, 6, 8

▲Up To Search▲

Price & Availability of MAX5981AETE

	To Download MAX5981AETE Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .