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? integrated circuits group lr s1329 s ta cke d chi p 1 6 m fla sh and 2m s ram (model no.: LRS1329 ) spec no.: mf m 2 - j 11 60 1 issue date: jun e 1 0 , 19 99 p reliminary p roduct s pecifications
sharp LRS1329 l handle this document carefully for it contains material protected by international copyright law. any reproduction, full or in part,. of this material is prohibited without the express written permission of the company. l when using the products covered herein, please observe.the conditions written herein and the precautions outlined in the following paragraphs. in no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) the products covered herein are designed and manufactured for the following application areas. when using the products covered herein for the equipment listed in paragraph (2), even for the following application areas, be sure to observe the precautions given in paragraph (2). never use the products for the equipment listed in paragraph (3). *office electronics * instrumentation and measuring equipment *machine tools -audiovisual equipment *home appliances * communication equipment other than for trunk lines (2) those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-sale operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. *control and safety devices for airplanes, trains, automobiles, and other transportation equipment * mainframe computers -traffic control systems . gas leak detectors and automatic cutoff devices *rescue and security equipment . other safety devices and safety equipment,etc. (3) do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. . * aerospace equipment . communications equipment for trunk lines *control equipment for the nuclear power industry -medical equipment related to life support, etc. (4) please direct all queries and comments regarding the interpretation of the above three paragraphs to a sales representative of the company. l please direct all queries regarding the products covered herein to a sales representative of the company.
sharp LRS1329 1 1. description contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5. command definitions for flash memory - * - - * - * - - - - - * - - - - 5 8. absolute maximum ratings . . . . . . . . . . . . . . . f . . . . . 8 9. recommended dc operating conditions . . . . . . . . . . . . . . . 8 10. pi* capacitance . - . . . . . a . . . . . a . - . a s s s s s ?- s - e 8 11. dc electrical characteristics - * - * - * * * + * - * - - * - * - * 9 12. ac electrical characteristics (flash memory) - * - * * - * * - * - * - 11 13. ac electrical characteristic?s (sram) - - * - * - - - - - - * - - - * - 18 14. data retention characteristics for srm * - * - * - - - * - - - * - - - 21 15. notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 17. design consideration . . . . . . . . . . . . , . . . . . . . . . . . . 24
shari= LRS1329 2 part 1 overview 1. description the lr s 1 3 2 9 is a combination memory organized as lmx16/2m ~8 bit flash memory and 256k x8 bit static ram in one package. features opower supply . . . . 2.7 v to 3.6 v ooperat ing temperature . . . . -25 ?c to +85 ?c onot designed or rated as radiation hardened 0 72 pin csp ( lcspo72-p-0811 ) plastic package oflash memory has p-type bulk silicon, and sram has p-type bulk silicon. flash memory oaccess time . . . . 100 ns (max.) ooperating current (ihe current for f-v, pin) read word/byte write block erase odeep power down current (the current for f-v,, pin) . . . - 25 ma (max. t,u=200ns) . . . . 17 ma (max.) . . . - 17 ma (max.) * * * * 10 pa (max. f-zzf-vcc-0. 2v, f-eso. zv, f-v&o. 2v) ooptimized array blocking architecture two 4x-word/8k-byte boot blocks/ six 4k-word/8k-byte parameter blocks/ thirty-one 32x-word/64k-byte main blocks/ top boot location 0 extended cycling capabi 1 i ty ~100,000 block erase cycles 0 enhanced automated suspend options word/byte write suspend to read block erase suspend to nerd/byte write block erase suspend to read sram oaccess time . ooperat ing current ostandby current odata retention current . . . . 85 ns &ax. > . . . . 30 d ohl > . . . . 3 ma (max. t,, t,=lp s) . . . . 15 pa (max.) . . . . 15 ,ua (max.)
sharp LRS1329 3 2. pin configuration r index block erase and word/byte write : vi, or v w, read 1 v,, or v k,, deep power down : vil f7@ write protect (flash) two boot blocks locked : vil (with f-&v m, erase/write can operate to all block) f-byte byte enable (flash); x8 mode: vil, x16 mode: vi, f-ry/by ready/busy (flash) during an erase or write operation: v,, block erase and word/byte write suspend: high-z deep power down: v, dq,to dq, data input/outputs (common) f-dq 8 to f-dq is data inputs/outputs (flash) ; not used in x8 mode. f-v,, power supply (flash) s-?cc power supply (sral4) f-v,, write, erase power supply (flash) block erase and word/byte write : f-v,,=v,,, : al 1 blocks locked 1 f-v,, shari= LRS1329 4 3. truth table (*l) note f-a f-b f-3 f-e s-ce, s-ge, s-s s* f-mtodph f-dq flash sram , to hu& read *4.5 h dout l output h l dout 1 high-z disable ? standby l h *7 h x x.7-. bigh-z h l din write *2,3,4 l din high-z read *6 l dout output h standby disable *6 h h ? ? l h h x high-z high-z write *6 l din read *6 l dout reset power output h down disable *6 xlxxlh x high-z bigh-2 h - write *6 l din standby ? *6 h h reset power standby - x x *7 x x x high-z down *6 x l tes) *l. l=v,,, h=v,, , x=h or l . refer to dc characteristics. *2. command writes involving block erase or word/byte write are reliably executed when f-v,,+., and f-v,=2.7v to 3-w. block erase or word/byte write with v,, f-ry/?% f-x f-e :? 16m (x8/x16) b i t f-m + flash memory f-d?& to f-w,, f* :> f-byte :t s-a,, 4 b s-e, i > s-c> j > s-oe ; > s-ire 2m (x8) bit sram +dq, to w, s-v, s-gnd
sharp LRS1329 5 i 5 command definitions for flash memory (*i) i word/byte write block erase and word/byte write suspend block erase and word/byte write resume 2 *5 wr i t,e wa 4oh or 10h write wa wd 1 *5 write xa boll xa doh 1 *5 write note) *l. commands other than those shown above are reserved by sharp for future device implementations and should not be used. ? *2. bus operations are defined in 3. truth table. *3. xa=any valid address within the device. ia=identifier code address. ba=address within the block being erased. wa=address of memory location to be written. srd=data read from status register(see the next page?status register definition?). wd=data to be written at location wa. data is latched on the rising edge of f-%?or f-5 (whichever goes high first). ii&data read from identifier codes. *4. see the following identifier codes. *5. see the following write protection alternatives. write protection alternatives operation f-v,, f-i@ f?@ effect v il x x all blocks locked. block erase v x all blocks locked. or word/byte write >v,, ?t x all blocks unlocked. v ih v il 2 boot blocks locked. v ih v ih all blocks unlocks.
sharp LRS1329 6 6. status register definition wsms ess es wbws vpps wbwss dps r 7 6 5 4 3 2 1 0 notes : s r. 7= write state machine status ( w sms) check rym or sr.7 to determine block erase oi 1 = ready word/byte write completion. sr.6-0 are invalid 0 = busy whi 1 e sr. 7=?0?. sr. 6= erase suspend status( ess) 1 = block erase suspended 0 = block erase in progress/completed sr.5=erasestatus( es ) if both sr. 5 and sr.4 are ?1?s after a block 1 = error in block erasure erase attempt, an improper command sequence 0 = successful block erase was entered. s r. 4= word/byte write status ( wbws ) 1 = error in word/byte write 0 = successful word/byte write sr. 3= v,, status ( vpps ) sr.3 does not provide a continuous indication 1 = f-v,, low detect, operation abort of f-v,, level. the wsm interrogates and 0 = f-v,, ok indicates the f-v,, level only after block erase or word/bytewrite command sequences. sr.: s r. 2 = word/byte write suspended status is not guaranteed to reports accurate feedback (wbwss) on 1 y when f-v, +vepm,2. 1 =word/bytewrite suspended 0 =word/bytewrite in progress/completed s r . l= device protect status ( d p s ) 1 = f-?wp or f-@? lock detected, operation abort 0 = unlock the wsm interrogates the f-s and f-e only after block erase orword/bytewrite command sequences. it informs the system, depending on the attempted operation, if the f-w is not vim, f-e is not vm+ s r. 0 = reserved for future enbancements sr.0 is reserved for future use and should be 4,r > masked out when polling the status register.
sharp LRS1329 7 memory map for flash memory address [a,.-hl 4k*word/8k-byte parameter block 4k-word/bk-byte parameter block 4k-word/bk-byte parameter block 32k-word/64k-byte main block 32x-word/64k-byte main block 323.word/64k-byte main block 32k-word/64k-byte main block 32k-word/64k.byte main block 32k-word/64k-byte main block 32k-word/64k-byte main block 32k-word/64k-byte main block 32k-word/64k-byte main block 32k-word/64k-byte main block 32k-word/64k-byte main block 32k-aord/64k-byte main block 32k-word/64k-byte tdain block 32k-word/64k-byte main block 32k-word/64k-byte main block 32k-word/64k-byte main block 32k-word/64k-byte main block 32k-word/64k-byte main block 32k-word/64k-byte main block 32k-word/64k-byte main block 32k-word/64k-byte main block 32x-word/64k-byte main block 32k-word/64k-byte main block 32k-word/64k-byte main block 32k-word/64k-byte main block 32k-word/64k-byte main block 32k-word/64k-byte main block 32k-word/64k-byte main block 32k-word/64k-byte main block 32k-word/64k-byte main block i ~~~ 32k-word/64k-byte main block i 19 18 17 ..... 2 1 0 20 19 18 ..... 2 1 0 msb lsb ysb lsb x8 mode x16 mode i
sharp LRS1329 i? 8.absolute maximum ratings parameter symbo 1 * supply voltage (*l, 2) v cc ratings -0.2 to +4.6 unit v input voltage (*l, 3) v in -0.2 (*4) to vcc+o.3 v operating temperature t opt -25 to +85 ?c . storage temperature t, f-;pr -65 to +125 c f-v,, voltage (*l) -0.2 (*4) to +14.0(*5) v f-e voltage (*l) f-e -0.5 04 to +14.0(*5) v notes) *l. the maximum applicable voltage on any pins with respect to cnd. *2. except f-v,,. *3. except f-e. *4. -2.ov undershoot is allowed when the pulse width is less than 20nsec. *5. i-14.ov overshoot is allowed when the pulse width is less than 20nsec. 9.recommended dc operating conditions (t,= -25 ?c to +85 ?c ) parameter symbo 1 min. typ. max. unit supply voltage v, 2.7 3.0 3.6 v input voltage v iii 2.2 v,+o. 3(*1) v v il -0.2 (*2) 0.8 v v, (*3) 11.4 12.6 v notes) *1. v, is the lower one of s-v,, and f-v, _ *2. -2.ov undershoot is allowed when the pulse width is less than 20nsec. *3. this voltage is applicable to f-b pin only. 10. pin capacitance parameter symbo 1 condition input capacitance crw vin=ov i/o capac i tance c i/o vi/o=ov note) *1 sampled but not 100% jested (t,=25r, f=lmhz) min. typ. kx. unit 20 pf *i 22 pf *l
shari= LRS1329 9 11. dc characteristics character istics (t.= -25 ?r: to +85 c , v,= 2.7v to 3.6v) g#pjy f-v, parameter input leakage current (iti) )utput? leakage current (ij v, standby current t-v pi s-v, deep power-down current v, read current j,, word/byte write current v, block erase current j, word/byte write block !rase suspend current vp, st andby or read current v, deep power-down current fpp word/byte write curren vp, block erase ?current i,, word/byte write or slack erase suspend zurrent standby current operation current symbo 1 i lx ll bcs (*2,7) bcd (*7) i cm i,,, i pps i ppp i ppd i pw i ppe i ppis i ppes i sb isbl i cc1 i cc2 conditions v,, =v, or cnd voir =v, or gnd f-e=f-3=f-v, fo.2v f--%f-v, fo.2v or f-cndfo. 2v f -z=f -@=v,, f-%?=v,, or vil :-%=f-cndfo. 2v, lout (f-ry~bc-ma mos input :-cj?=f-gnd, f=5mlz. i,,, =oma tl input %=f-gnd, f=smbz, iom =oma f-v, =vpp, f-vpp =vpp? f -ce=v,, f-v,, = f-v,, f-v, > f-v,, f-@=f-gndfo. 2v f-v, =v,,, f - ?4, =vppii f-v, =v,,, . s-ce,, s-ce.&s-v,-0.2v or s-ce,io. 2v s -ce,=v,a or s - cea=vil s -ce,=v,,, t ,,=min. s - c&=v,, ii/o=oma vin=vi~ or v,ii s -ce,=o. 2v, t cya.b=~ p s s-c&=s-vcc-0.2v im--om vin=s-vcc-o. 2v or 0.2v -1.5 +1.5 pa 25 50 pa 0.2 2ma i i i i4ma i i i i i i i6b i i i i ,i i lo1 2ool pa i i i i 15 pa 3.0 dla 3o dla i i i 31* i i i i
sharp LRS1329 10 dc characteristics (continue) -25?c to +ss?c , v,= 2.7 v to 3.6v) notes) 1. reference values at v,=3.ov and t,=+25?c. 2. includes f-ry/by. 3. automatic power savings (aps) for flash memory reduces typical i,,, to 3ma at 2.7v v, in static operation. 4. cmos inputs are either v, fo.2v or gnmo.2v. ttl inputs are either vi, or vi,. 5. block erases and word/byte writes are inhibited when f-v,, sv,,, and not guaranteed in the range between v,, (max) and v,, (min), and above v,, (max). 6. f-3 connection to a v, supply is allowed for a maximum cumulative period of 80 hours. 7. f-m is v&o.2v in word mode and is cwo.2v in byte mode. f-@ is v&o.zv or cndzto. 2v.
sharp LRS1329 11 12. flash memory ac characteristics ac test condtions input pulse level 0 v to 2.7 v input rise and fall time 5 ns input and output timing ref. level 1.35 v ~ output load lttlfc, (30pf) read cycle ct,= -25c to +ss?c ) v,(y 2.7 to 3.6v ) notes) *l. f-n may be delayed up to tuq,-k,,after the falling edge of f-oewithout impact on t,, write cycle (f-e controlled) (*2) (t,= -25c to +85?c , v$ 2.7v to 3.6v) parameter min. max. unit write recovery before read f-v,, hold from valid srd, f-ry/bthigh z f-e v,,,, hold from valid srd, f-ry/k@-high z f-w vi, hold from valid srd, f-ry/b?high hhcl 0 ns wl 0 ns t9 vph 0 ns t9 vsl 0 ns f-byte setup to f-e going high f-byte hold from f% hinh hlh 50 ns tn 100 ns 1 i i 1 i i
sharp LRS1329 12 write cycle (f-z control led) (*2) (t,= -25c to +85x ) v,f 2.7v to 3.6v) notes) *2. read timing characteristics during block erase and word/byte write operations are th same as during read-only operations. refer to ac characteristics for read cycle. *3. refer to section 5. flash memory command definition for valid &n and din for block erase or word/byte write.
LRS1329 block erase and word/byte write performance (t,= -25c to +85 c, v,= 2.7 v to 3.6 v j hhav2 block erase 32k-word block 1.2 s t mpvz time 64k-byte block 4k-word block 0.5 s 8k-byte block huur word/bytewrite suspend 7.5 8.6 ps hnrz1 latency time to read hm3z2 erase suspend latency time 19.3 23.6 p?s hlmz2 to read ^- - --. __ - _--
sharp LRS1329 flash memory ac characteristic timing chart read cycle timing chart address dq f-v, high z device address selection address stable l data valid f-byte f-byte timing waveform standby address m device address selection address stable data valid )ata (d/q> high z (iq,-w> data @/cl) high z c t avpv k t pm i high z
sharp LRS1329 write cycle timeng chart (f-e controlled) w address f-e f-bm f-ry/by t, ( b.l l / \ himlii> hwh) l- ( ~wvll > tjt am f-wp f-i@ f-v,, notes: *l. v,, power -up and standby. *2. write block erase or word/byte write setup. *3. write block erase confirm or valid address and data. *4. automated erase or program delay. *5. read status register data. *6. write read array command. *1 *2 i-l-a , *6 ,_
sharp LRS1329 16 write cycle timing chart (f-e controlled) *1 l-v--% a address f-e f-z f-e w f-byte f-ry/by notes: *l. v,, power-up and standby. *2. write block erase or word/byte write setup. *3. write block erase confirm or valid address and data. *4. automated erase or program delay. *5. read status register data. %. wri te read array command.
sharp LRS1329 17 reset operations (t,= -25 ?c to +85 ?c , vcc= 2.7v to 3.6 v ) parameter sw. min. max. unit f-e pulse low time (if f-e.is tied to vcc, this specification is not true 100 ns applicable.) f?@ low to reset during block erase or hz 23.6 ,u s *1,2 write f-v,, 2.7v to f-b high h 100 ns *3 iotes)*l. if f-b is asserted while a block erase or word/bytewrite operation is not executing, the reset will complete with loons. *2. a reset time, t,,. is required from the later of f-ry/by going high z of f-e going high until outputs are valid. *3. when the device power-up, holding f-3 low minimum 1oons is required after vcc has been in predefined range and also has been in stable there. ac waveform for reset oneration high z fry/by @) vol v iii f -@ (p) vi, - \ / ( ) t,m (a)reset during read array mode high z f-ry/by(r) v ol v iii f-b (p) v il 7 i( tpu.2 > r i- ( > t,lpil (b)reset during block erase or word/byte write . f-i@(p) (c)f-e rising timing
sharp LRS1329 18 13. sram ac electrical characteristics sram ac test conditions input pulse level i 0.4 v to 2.2 v input rise and fall time 5 ns input and output timing ref.level 1.5 v 1 output load lltltc, (30pf) (*l) note) *l. including scope and jig capacitance. read cycle (t,= -25 =c to +85 ?c , v,= 2.7vto3.6 v) parameter read cycle time address access time chip enable access time(s-e) sym. min. max. unit . hc 85 ns ha 85 ns hce1 85 ns (s-c&j hca 85 ns *2 *2 *2 *2 *2 *2 write cycle (t,= -25 ?c to +85 c , v,=2.7 v to 3.6 v ) s-z high to output active t 01 5 ns *2 s-b low to output in high impedance t, 0 25 ns *2 l *2. active output to high impedance and high impedance to output active tests specified for a f20omv transition from steady state levels into the test load.
sharp LRS1329 19 sram ac charaterestics timing chart read cycle timing chart- (*3) address s -ce, s-c& s-x d ooi *3 s%? is high for read cycle. write cycle timing chart- (s-e controlled) address s-oe s-ce, s-ce, d out d in < tic > jf ?( t ? oil? i (*i < tow > \\\\\\\\\\\\\\ (*lo) trn ,, km /' (*8) / \ data valid
shari= LRS1329 20 write cycle timing chart-(s-alow fixed) address dwr / / / , , , , , i i i i i, < ta ./ tm i- /?a (*s) din / data valid notes) *4. a write occurs during the overlap of a low se,, a high s-c& and a low s-x, a write begins at the latest transition among s-m going low, s-ce,going high and s-mgoing low. a write ends at the earliest transition among s-z, going high, s-ce, going low and s-e going high. twis measured from the beginning of write to the end of write. *5. tcr is measured from the later of s-going low or s-c& going high to the end of write. . *6. tas is measured from the address valid to the beginning of write. *7. tm is measured from the end of write to the address change. a. during this period, w pins are in the output state, therefore the input signals of opposite phase to the outputs must not be applied. *9. if s-e, goes low or s-c& goes high simultaneously with s-e going low or after s-we going low, the outputs remain in high impedance state. *10. if s-xi goes high or s-c& goes low simultaneously with s% going high or s-e going high, the outputs remain in high impedance state.
sharp LRS1329 21 14.sram data retention characteristics (t,= -25c to +35?c > parameter sym. conditions min. typ. (*l) max. unit data retention vccdb s-c& so. 2v or supply volotage s-ce,~v,w-o. 2v (*2> 2.0 3.6 v data retention i cccm v,,=3v supply current s-c&so. 2v or s-e lv,,-0.2v (*2) 0.2 15 pa chip enable setup time bdr 0 ns chip enable hold time tr 5 lcs notes) *l. reference value at t,=25?c, s-v,=3. ov. *2. s-ce,zv,-o.2v, s-ce.&v,-0.2v (s-e, control led) or s-c&so. 2v (s-c& control led) data retention timing chart (s-%controlled)(*3) l data retention mode . ()v --.---i -_--- -.-----s-e- ____i__.___..._ _ . . ..-.....- -_ -i-..._- -i_ . . . . . ..--.. -- data retention timing chart (s-cez control led) -vcc . ce, data retention mode / . / 2.jv - . . . ..---.. _ . . . . ..- -i-? . .._. _ . . . .._ _._._-_..__._._ ._-_.--.-__-. _ .-._.... _.._ . . . . . . . . . . . . . _..__.._ _..__ . . . . . ..-_.... _..._.._...__.._----_ . . . . . . . . . . . . . . . cdp , 0. 8 v ___.. _..__ .___ _ _____ _ __._. __________________.........~ _ .__.____.____.______ _ _.____. ___ ________.__._______...................... ._..___._.__......................... _ . . . . . . . . . _ . . . . . . note) *3. to control the data retention mode at s-z,, fix the input level of s-c& between v,, and vcc, -0.2v or ov or 0.2v and during the data retetion mode.
sharp LRS1329 22 15. notes this product is a stacked csp package that a 16m(x8/x16) bit flash memory and a 2m (x8) bit swam are assembled into. supply power maximum difference (between f-v ,x and s-v,) of the voltage is less than 0.3v. power supply and chip enable of flash memory and sram s-e1 should not be low and s-q should not be bigh when f-eis low simulataneously. .if the two memories are active together, possibly they may not operate normally by interference noises or data collision on w bus. both f-v, and s-v, are needed to be applied by the recommended supply voltage at the same time except swam data retention mode. power up sequence when turping on flash memory power supply, keep f-b low. after f-v,, reaches over 2.7v, keep f-a low for more than 100nsec. device decoupling the power supply is needed to be designed carefully because one of the sram and the flash memory is in standby mode when the other is active. a careful decoupling of power supplies is necessary between swam and flash memory. note peak current caused by transition of control signals (f-e, s-ce,, s-c&).
sharp LRS1329 23 16.flash memory data protection noises having a level exceeding the limit specified in the specification may be generated under specific operating conditions on some systems. such noises, when induced onto f-w signal or power supply may be interpreted as false commands, causing undesired memory updating. to protect the data stored in the flash memory against unwanted overwriting, systems operating with the flash memory should have the following write protect designs, as appropriate: 1) protecting data in specific block by setting a f?? to low, only the boot block can be protected against overwriting. parameter and main blocks cannot be locked. system program, etc., can be locked by storing them in the boot block. when a high voltage is applied to f-e, overwrite operation is enabled for all blocks. for further information on setting/resetting of block bit,and controlling of f-e and f-d, refer to the specification. (see 5.command definitions p.5) 2) data protection through vpp when the level of vpp is lower than vpplk(lockout voltage), write operation on the flash memory is disabled. all blacks are locked and the data in the blocks are completely write protected. for the lockout voltage, refer to the specification. (see chapter 11. dc characteristics p-10) data protection during voltage transition 1) data protection thorough f-s when the f-e is kept low during power up and power down sequence, write operation on the flash memory is disabled, write protecting all blocks. . for the details of f-e control, refer to the specification. (see chapter 12. flash memory ac electrical.characteristics)
sharf) LRS1329 24 17. design considerations 1. power supply decoupling to avoid a bad effect to the system by flash memory power switching characteristics, each device should have a o.lpf ceramic capacitor connected between its v, and gnd and between its v,,and cnd. low inductance capacitors should be placed as close as possible to package leads. 2. v,,trace on printed circuit boards updating the memory contents of flash memories that reside in the target system requires that the printed circuit board designer pay attention to the vr, power supply trace. use similar trace widths and layout considerations given to the vcc power bus. 3. the inhibition of overwrite operation please do not execute reprogramming ?0? for?the bit which has already been programed ?0?. overwrite operation may generate unerasable bit. in case of reprogramming ?0? to the data which has been programed ?1?. * program ?0? for the bit in which you want to change data from ?1? to ?0?. * program ?1? for the bit which has already been programmed ?0?. for example, changing data from ?1011110110111101? to ?1010110110111100? requires ?1110111111111110? programming. 4. power supply block erase, full chip erase, word/byte write and lock-bit configuration with an invalid v,,(see 11. dc characteristics) produce spurious results and should not be attempted. device operations at invalid vcc voltage(see ll.dc characteristics) produce spurious results and should not be attempted. i
index top view-,-- i i ---e-e 0 -i- -----a 0 i : 0 01 6 +o 1 -- --- ----. 0 ai 1? \ , \ - \ ? \ / i i ii \ i ----____ 1 ? \/ i i 1 u c-1 , , :\j \ i ? \ i \ , 1. 1 typ. = typ. to c 0. 8 ,= oj 0. 4 typ. i 3 i \/ / i 000bol!000ooo \ ?z /i ? 0000~0000 a 4 --- bottom view p oooo;ooo~ i i m 0000~0000 1 .----e-v- 1 p 0 0 0 ot~~~j-cc.---- i ? ooooioooo m 0000~0000 i ti c a, d v ~0000601000000 1 2 3 4 5 6,171 6 9101112 i i=?es scale wi unit slf%h 16m flash .yemorycxl6aa) appl t c.4alz +zm sram cxsi 5/l l=l/lmm model - sc?b?j71 - matrix lcspo72-p-081

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