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????????????????????????????????????????????????????????????????? maxim integrated products 1 19-6278; rev 0; 5/12 general description the max98355a/max98355b are digital pulse-code modulation (pcm) input class d power amplifiers that provide class ab audio performance with class d effi - ciency. these ics offer five selectable gain settings (3db, 6db, 9db, 12db, and 15db) set by a single gain- select input (gain). the digital audio interface is highly flexible with the max98355a supporting i 2 s data and the max98355b supporting left-justified data. both ics support time divi - sion multiplexed (tdm) data. the digital audio interface accepts sample rates ranging from 8khz to 96khz for all supported data formats. the ics can be configured to produce a left channel, right channel, or (left + right)/2 output from the stereo input data. the ics operate using 16/24/32-bit data for i 2 s and left justified modes as well as 16-bit data with up to four slots when using tdm mode. the ics eliminate the need for the external mclk signal that is typically used for pcm communication. this reduces emi and possible board coupling issues in addi - tion to reducing the size and pin count of the ics. the ics also feature a very high wideband jitter tolerance (12ns typ) on bclk and lrclk to provide robust operation. active emissions-limiting, edge-rate limiting, and over - shoot control circuitry greatly reduce emi. a filterless spread-spectrum modulation scheme eliminates the need for output filtering found in traditional class d devices and reduces the component count of the solution. the ics are available in a 9-pin wlp package (1.345mm x 1.435mm x 0.64mm) and are specified over the -40 n c to +85 n c temperature range. applications cellular phones tablets portable media players notebook computers features s single-supply operation (2.5v to 5.5v) s 3.2w output power into 4 i at 5v s 2.2ma quiescent current s 92% efficiency (r l = 8 i , p out = 900mw, v dd = 3.7v) s 25v rms output noise (a v = 15db) s low 0.013% thd+n at 1khz s no mclk required s sample rates of 8khz to 96khz s supports left, right, or (left + right)/2 outputs s sophisticated edge rate control enables filterless class d outputs s 77db psrr at 217hz s low rf susceptibility rejects tdma noise from gsm radios s extensive click-and-pop reduction circuitry s robust short-circuit and thermal protection s available in space-saving package: 1.345mm x 1.435mm wlp (0.4mm pitch) ordering information appears at end of data sheet. functional diagram appears at end of data sheet. for related parts and recommended products to use with this part, refer to www.maxim-ic.com/max98355a.related . simplified block diagram dac class d output stage digital audio interface pcm input gain control shutdown and channel select max98355a max98355b max98355a/max98355b pcm input class d audio power amplifiers evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com.
????????????????????????????????????????????????????????????????? maxim integrated products 2 max98355a/max98355b pcm input class d audio power amplifiers table of contents general description ............................................................................ 1 applications .................................................................................. 1 features ..................................................................................... 1 simplified block diagram ........................................................................ 1 absolute maximum ratings ...................................................................... 4 package thermal characteristics .................................................................. 4 electrical characteristics ........................................................................ 4 typical operating characteristics ................................................................. 9 general .................................................................................... 9 speaker amplifier ............................................................................ 9 pin configuration ............................................................................. 16 pin description ............................................................................... 16 detailed description ........................................................................... 17 digital audio interface modes .................................................................. 17 mclk elimination ......................................................................... 17 jitter tolerance ........................................................................... 17 bclk polarity ............................................................................ 17 lrclk polarity ........................................................................... 17 pcm timing characteristics ................................................................. 18 standby mode ........................................................................... 26 dac digital filters .......................................................................... 26 s d_m o d e and shutdown operation ............................................................. 26 class d speaker amplifier .................................................................... 27 ultra-low emi filterless output stage ......................................................... 27 speaker current limit ..................................................................... 28 gain selection ........................................................................... 28 click-and-pop suppression ................................................................. 28 applications information ........................................................................ 29 filterless class d operation ................................................................... 31 power-supply input .......................................................................... 31 layout and grounding ....................................................................... 31 wlp applications information .................................................................. 31 functional diagram ........................................................................... 32 ordering information .......................................................................... 32 package information ........................................................................... 33 revision history .............................................................................. 34
????????????????????????????????????????????????????????????????? maxim integrated products 3 max98355a/max98355b pcm input class d audio power amplifiers list of figures list of tables figure 1. i 2 s audio interface timing diagram (max98355a) ............................................ 8 figure 2. left-justified audio interface timing diagram (max98355b) .................................... 8 figure 3. tdm audio interface timing diagram ....................................................... 8 figure 4. max98355a i 2 s digital audio interface timing, 16-bit resolution ............................... 18 figure 5. max98355a i 2 s digital audio interface timing, 24-bit resolution ............................... 19 figure 6. max98355b left-justified digital audio interface timing, 16-bit resolution ....................... 20 figure 7. max98355b left-justified digital audio interface timing, 24-bit resolution ........................ 21 figure 8. max98355a tdm digital audio interface timing ............................................. 22 figure 9. max98355b tdm digital audio interface timing ............................................. 23 figure 10. max98355a tdm digital audio interface timing, example of four 16-bit slots .................... 24 figure 11. max98355b tdm digital audio interface timing, example of four 16-bit slots .................... 25 figure 12. s d_m o d e resistor connection using open-drain driver ..................................... 27 figure 13. s d_m o d e resistor connection using pullup/down driver ..................................... 27 figure 14. emi with 12in of speaker cable and no output filtering ...................................... 28 figure 15. left-channel pcm operation with 6db gain ............................................... 29 figure 16. left-channel pcm operation with 12db gain .............................................. 29 figure 17. right-channel pcm operation with 6db gain .............................................. 29 figure 18. stereo pcm operation using two ics .................................................... 30 figure 19. (left + right)/2 pcm operation with 6db gain .............................................. 31 figure 20. max98355a/max98355b wlp ball dimensions ............................................ 31 table 1. rms jitter tolerance .................................................................... 17 table 2. bclk polarity ......................................................................... 17 table 3. lrclk polarity ........................................................................ 17 table 4. digital filter settings .................................................................... 26 table 5. s d_m o d e control ...................................................................... 26 table 6. examples of s d_m o d e pullup resistor values ............................................... 26 table 7. gain selection ......................................................................... 28
????????????????????????????????????????????????????????????????? maxim integrated products 4 max98355a/max98355b pcm input class d audio power amplifiers v dd , lrclk, bclk, and din to gnd .................... -0.3v to +6v all other pins to gnd .............................. -0.3v to (v dd + 0.3v) continuous current in/out of v dd /gnd/out_ ................. q 1.6a continuous input current (all other pins) ........................ q 20ma duration of out_ short circuit to gnd or v dd .. ... continuous duration of outp short to outn ............................. continuous continuous power dissipation (t a = +70 n c) wlp (derate 13.7mw/ n c above +70 n c) .................... 1096mw junction temperature ..................................................... +150 n c operating temperature range .......................... -40 n c to +85 n c storage temperature range ............................ -65 n c to +150 n c soldering temperature (reflow) ...................................... +230 n c wlp junction-to-ambient thermal resistance ( q ja ) .......... 73c/w junction-to-case thermal resistance ( q jc ) ............... 50c/w absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 1) electrical characteristics (v dd = 5v, v gnd = 0v, gain = v dd (+6db). bclk = 3.072mhz, lrclk = 48khz, speaker loads (z spk ) connected between outp and outn, z spk = j , t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c.) (note 2) parameter symbol conditions min typ max units supply voltage range v dd guaranteed by pssr test 2.5 5.5 v undervoltage lockout uvlo 1.5 1.8 2.2 v quiescent current i dd t a = +25 n c 2.5 3.3 ma t a = +25 n c, v dd = 3.7v 2.2 2.7 shutdown current i shdn sd_mode = 0v, t a = +25 n c 0.6 2 f a standby current i stndby sd_mode = 1.8v, no bclk, t a = +25 n c 300 400 f a turn-on time t on time from receipt of first clock cycle to full operation, including 6ms fade-in volume ramp 7 7.5 ms output offset voltage v os t a = +25 n c, gain = 15db q 0.3 q 1.5 mv click-and-pop level k cp peak voltage, t a = +25 n c, a-weighted, 32 samples per second (note 3) into shutdown -66 dbv out of shutdown -72 power-supply rejection ratio psrr v dd = 2.5v to 5.5v, t a = +25 n c 60 75 db t a = +25 n c (notes 3, 4) f = 217hz, 200mv p-p ripple 77 f = 10khz, 200mv p-p ripple 60
????????????????????????????????????????????????????????????????? maxim integrated products 5 max98355a/max98355b pcm input class d audio power amplifiers electrical characteristics (continued) (v dd = 5v, v gnd = 0v, gain = v dd (+6db). bclk = 3.072mhz, lrclk = 48khz, speaker loads (z spk ) connected between outp and outn, z spk = j , t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c.) (note 2) parameter symbol conditions min typ max units output power (note 3) p out thd+n 10%, gain = 12db z spk = 4 i + 33 f h 3.2 w z spk = 8 i + 68 f h 1.8 z spk = 8 i + 68 f h, v dd = 3.7v 0.93 thd+n = 1%, gain = 12db z spk = 4 i + 33 f h 2.5 z spk = 8 i + 68 f h 1.4 z spk = 8 i + 68 f h, v dd = 3.7v 0.77 total harmonic distortion + noise thd+n f = 1khz, p out = 1w, t a = +25 n c, z spk = 4 i + 33 f h 0.02 0.06 % f = 1khz, p out = 0.5w, t a = +25 n c, z spk = 8 i + 68 f h 0.013 dynamic range dr a-weighted, v rms = 2.54v, 24- or 32-bit data 99 db dynamic range, high gain dr hg a-weighted, gain = 15db, v rms = 4.55v (clipping), 24- or 32-bit data 105 db output noise v n a-weighted, 24- or 32-bit data (note 4) 25 f v rms output noise, high gain v n_hg a-weighted, gain = 15db, 24- or 32-bit data (note 4) 25 f v rms gain (relative to a 2.1dbv reference level) a v gain = gnd through 100k i 14.5 15 15.5 db gain = gnd 11.5 12 12.5 gain = unconnected 8.5 9 9.5 gain = v dd 5.5 6 6.5 gain = v dd through 100k i 2.5 3 3.5 current limit i lim 2.8 a efficiency h z spk = 8 i + 68 f h, thd+n = 10%, f = 1khz, gain = 12db 92 % dac gain error 1 % frequency response -0.2 +0.2 db dac digital filters voice mode iir lowpass filter (lrclk < 30khz) passband cutoff f plp ripple limit cutoff 0.443 x f s hz -3db cutoff 0.446 x f s stopband cutoff f slp 0.464 x f s hz stopband attenuation f > f slp 75 db
????????????????????????????????????????????????????????????????? maxim integrated products 6 max98355a/max98355b pcm input class d audio power amplifiers electrical characteristics (continued) (v dd = 5v, v gnd = 0v, gain = v dd (+6db). bclk = 3.072mhz, lrclk = 48khz, speaker loads (z spk ) connected between outp and outn, z spk = j , t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c.) (note 2) parameter symbol conditions min typ max units audio mode fir lowpass filter (30khz < lrclk < 50khz) passband cutoff f plp ripple limit cutoff 0.43 x f s hz -3db cutoff 0.47 x f s -6.02db cutoff 0.5 x f s stopband cutoff f slp 0.58 x f s hz stopband attenuation f > f slp 60 db audio mode fir lowpass filter (lrclk > 50khz) passband cutoff f plp ripple limit cutoff 0.24 x f s hz -3db cutoff 0.31 x f s stopband cutoff f slp 0.477 x f s hz stopband attenuation f < f slp 60 db digital audio interface lrclk range 1 f s1 7.6 8 8.4 khz lrclk range 2 f s2 15.2 16 16.8 lrclk range 3 f s3 30.4 48 50.4 lrclk range 4 f s4 83.8 96 100.8 resolution i 2 s/left justified mode 16/24/32 bits tdm mode 16 bclk frequency range f bclk bclk must be 32, 48, or 64x of lrclk 0.2432 6.4512 mhz bclk high time t bclkh 40 ns bclk low time t bclkl 40 ns maximum low frequency bclk and lrclk jitter rms jitter below 40khz 0.5 ns maximum high frequency bclk and lrclk jitter rms jitter above 40khz 12 input high voltage v ih digital audio inputs 1.3 v input low voltage v il digital audio inputs 0.6 v
????????????????????????????????????????????????????????????????? maxim integrated products 7 max98355a/max98355b pcm input class d audio power amplifiers electrical characteristics (continued) (v dd = 5v, v gnd = 0v, gain = v dd (+6db). bclk = 3.072mhz, lrclk = 48khz, speaker loads (z spk ) connected between outp and outn, z spk = j , t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c.) (note 2) note 2: 100% production tested at t a = +25 n c. specifications over temperature limits are guaranteed by design. note 3: class d amplifier testing performed with a resistive load in series with an inductor to simulate an actual speaker load. for r l = 8 i , l l = 68 f h. for r l = 4 i , l l = 33 f h. note 4: digital silence used for input signal. parameter symbol conditions min typ max units input leakage current i ih , i il v in = 0v, v dd = 5.5v, t a = +25 n c -1 +1 f a input capacitance c in 12 pf din to bclk setup time t setup 10 ns lrclk to bclk setup time t syncset 10 din to bclk hold time t hold 10 lrclk to bclk hold time t synchold 10 sd_mode comparator trip points b0 see sd_mode and shutdown operation for details 0.08 0.16 0.355 v b1 0.65 0.77 0.825 b2 1.245 1.4 1.5 sd_mode pulldown resistor r pd 92 100 108 k i gain comparator trip points v gain a v = 3db gain 0.65 x v dd 0.85 x v dd v a v = 6db gain 0.9 x v dd v dd a v = 9db gain 0.4 x v dd 0.6 x v dd a v = 12db gain 0 0.1 x v dd a v = 15db gain 0.15 x v dd 0.35 x v dd
????????????????????????????????????????????????????????????????? maxim integrated products 8 max98355a/max98355b pcm input class d audio power amplifiers figure 1. i 2 s audio interface timing diagram (max98355a) figure 3. tdm audio interface timing diagram figure 2. left-justified audio interface timing diagram (max98355b) bclk (input) lrclk (input) din (input) t bclk t setup t hold t bclkh t syncset t synchold lsb lsb msb msb t bclkl bclk (input) lrclk (input) max98355a max98355b din (input) bclk (input) lrclk (input) din (input) t bclk t bclk t setup t hold t bclkh t syncset t syncset t synchold lsb msb lsb msb t bclkl t bclkl t bclkh t setup t hold t synchold bclk (input) lrclk (input) din (input) t bclk t setup t hold t bclkh t syncset t synchold lsb lsb msb msb t bclkl
????????????????????????????????????????????????????????????????? maxim integrated products 9 typical operating characteristics (v dd = 5v, v g nd = 0v, gain = v dd (+6db). bclk = 3.072mhz, lrclk = 48khz, speaker loads (z spk ) connected between outp and outn, z s pk = j , t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c.) general speaker amplifier supply current vs. supply voltage max98355a /b toc01 supply current (ma) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 supply voltage (v) 5.0 4.5 4.0 3.5 3.0 2.5 5.5 0.1 0.2 0.3 0.4 0.5 0.6 shutdown current vs. supply voltage max98355a /b toc02 shutdown current (a) 0.7 0 supply voltage (v) 5.0 4.5 4.0 3.5 3.0 2.5 5.5 1 0.1 0.01 0.001 10 total harmonic distortion plus noise vs. output power max98355a /b toc03 output power (w) thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 v dd = 3.7v gain = 12db z spk = 8i + 68h f = 6khz f = 1khz f = 100hz total harmonic distortion plus noise vs. output power max98355a /b toc04 output power (w) thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 v dd = 4.2v gain = 12db z spk = 8i + 68h f = 6khz f = 1khz f = 100hz 1 0.1 0.01 0.001 10 total harmonic distortion plus noise vs. output power max98355a /b toc05 output power (w) thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 1 0.1 0.01 0.001 10 f = 6khz f = 1khz f = 100hz v dd = 5v gain = 12db z spk = 8i + 68h max98355a/max98355b pcm input class d audio power amplifiers
???????????????????????????????????????????????????????????????? maxim integrated products 10 typical operating characteristics (continued) (v dd = 5v, v g nd = 0v, gain = v dd (+6db). bclk = 3.072mhz, lrclk = 48khz, speaker loads (z spk ) connected between outp and outn, z s pk = j , t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c.) 10k 1k 100 10 100k total harmonic distortion plus noise vs. frequency max98355a /b toc09 frequency (hz) thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 v dd = 3.7v gain = 12db z spk = 8i + 68h p out = 75mw p out = 350mw total harmonic distortion plus noise vs. output power max98355a /b toc06 output power (w) thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 v dd = 3.7v gain = 12db z spk = 4i + 33h f = 6khz f = 1khz f = 100hz 1 0.1 0.01 0.001 10 10k 1k 100 10 100k total harmonic distortion plus noise vs. frequency max98355a /b toc10 frequency (hz) thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 v dd = 4.2v gain = 12db z spk = 8i + 68h p out = 100mw p out = 500mw total harmonic distortion plus noise vs. output power max98355a /b toc07 output power (w) thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 v dd = 4.2v gain = 12db z spk = 4i + 33h f = 6khz f = 1khz f = 100hz 1 0.1 0.01 0.001 10 10k 1k 100 10 100k total harmonic distortion plus noise vs. frequency max98355a /b toc11 frequency (hz) thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 v dd = 5v gain = 12db z spk = 8i + 68h p out = 150mw p out = 850mw total harmonic distortion plus noise vs. output power max98355a /b toc08 output power (w) thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 v dd = 5v gain = 12db z spk = 4i + 33h f = 6khz f = 1khz f = 100hz 1 0.1 0.01 0.001 10 max98355a/max98355b pcm input class d audio power amplifiers
???????????????????????????????????????????????????????????????? maxim integrated products 11 typical operating characteristics (continued) (v dd = 5v, v g nd = 0v, gain = v dd (+6db). bclk = 3.072mhz, lrclk = 48khz, speaker loads (z spk ) connected between outp and outn, z s pk = j , t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c.) output power vs. load resistance max98355a /b toc15 load ( i ) output power (w) 10 0.5 1.0 1.5 2.0 2.5 0 1 100 v dd = 3.7v gain = 12db z spk = r load i + 68h thd+n = 10% thd+n = 1% 10k 1k 100 10 100k total harmonic distortion plus noise vs. frequency max98355a /b toc12 frequency (hz) thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 v dd = 3.7v gain = 12db z spk = 4i + 33h p out = 150mw p out = 600mw 0.5 1.0 1.5 2.0 2.5 3.0 0 output power vs. load resistance max98355a /b toc16 load ( i ) output power (w) 10 1 100 v dd = 4.2v gain = 12db z spk = r load i + 68h thd+n = 10% thd+n = 1% 10k 1k 100 10 100k total harmonic distortion plus noise vs. frequency max98355a /b toc13 frequency (hz) thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 v dd = 4.2v gain = 12db z spk = 4i + 33h p out = 250mw p out = 850mw 0.5 1.0 1.5 2.0 3.0 2.5 4.5 4.0 3.5 0 output power vs. load resistance max98355a /b toc17 load ( i ) output power (w) 10 1 100 v dd = 5v gain = 12db z spk = r load i + 68h thd+n = 10% thd+n = 1% 10k 1k 100 10 100k total harmonic distortion plus noise vs. frequency max98355a /b toc14 frequency (hz) thd+n ratio (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 v dd = 5v gain = 12db z spk = 4i + 33h p out = 1.5w p out = 350mw max98355a/max98355b pcm input class d audio power amplifiers
???????????????????????????????????????????????????????????????? maxim integrated products 12 typical operating characteristics (continued) (v dd = 5v, v g nd = 0v, gain = v dd (+6db). bclk = 3.072mhz, lrclk = 48khz, speaker loads (z spk ) connected between outp and outn, z s pk = j , t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c.) efficiency vs. output power max98355a /b toc21 output power per channel (w) efficiency (%) 0.9 0.8 0.6 0.7 0.2 0.3 0.4 0.5 0.1 10 20 30 40 50 60 70 80 90 100 0 0 1.0 v dd = 3.7v gain = 12db z spk = 8i + 68h output power vs. supply voltage max98355a /b toc18 supply voltage (v) output power (w) 5.0 4.5 4.0 3.5 3.0 0.5 1.0 1.5 2.0 2.5 0 2.5 5.5 gain = 12db z spk = 8i + 68h thd+n = 10% thd+n = 1% efficiency vs. output power max98355a /b toc22 output power per channel (w) efficiency (%) 1.2 0.8 1.0 0.4 0.6 0.2 10 20 30 40 50 60 70 80 90 100 0 0 1.4 v dd = 4.2v gain = 12db z spk = 8i + 68h output power vs. supply voltage max98355a /b toc19 supply voltage (v) output power per channel (w) 5.0 4.5 4.0 3.5 3.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 2.5 5.5 gain = 12db z spk = 4i + 33h thd+n = 10% thd+n = 1% 1.6 1.8 1.2 1.4 0.2 0.4 0.6 0.8 1.0 efficiency vs. output power max98355a /b toc23 output power per channel (w) efficiency (%) 10 20 30 40 50 60 70 80 90 100 0 0 2.0 v dd = 5v gain = 12db z spk = 8i + 68h normalized gain vs. frequency max98355a-b toc20 frequency (hz) normalized gain (db) 10k 1k 100 -2 -1 0 1 2 3 -3 10 100k z spk = 8i + 68h max98355a/max98355b pcm input class d audio power amplifiers
???????????????????????????????????????????????????????????????? maxim integrated products 13 typical operating characteristics (continued) (v dd = 5v, v g nd = 0v, gain = v dd (+6db). bclk = 3.072mhz, lrclk = 48khz, speaker loads (z spk ) connected between outp and outn, z s pk = j , t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c.) power-supply rejection ratio vs. supply voltage max98355a-b toc27 supply voltage (v) psrr (db) 5.0 4.5 4.0 3.5 3.0 10 20 30 40 50 60 70 80 90 100 0 2.5 5.5 f = 1khz z spk = 8i + 68h efficiency vs. output power max98355a /b toc24 efficiency (%) 10 20 30 40 50 60 70 80 90 100 0 v dd = 3.7v gain = 12db z spk = 4i + 33h output power per channel (w) 1.6 1.8 1.2 1.4 0.2 0.4 0.6 0.8 1.0 0 10k 1k 100 10 100k power-supply rejection ratio vs. frequency max98355a-b toc28 frequency (hz) psrr (db) 10 20 30 40 50 60 70 80 90 100 0 v dd = 5v z spk = 8i + 68h output power per channel (w) 2.0 1.5 1.0 0.5 efficiency vs. output power max98355a /b toc25 efficiency (%) 10 20 30 40 50 60 70 80 90 100 0 0 2.5 v dd = 4.2v gain = 12db z spk = 4i + 33h inband output spectrum max98355a /b toc29 frequency (khz) amplitude (dbv) 18 16 2 4 6 10 12 8 14 -120 -100 -80 -60 -40 -20 0 20 -140 02 0 bclk = 6.144mhz lrclk = 96khz z spk = 8i + 68h efficiency vs. output power max98355a /b toc26 output power per channel (w) efficiency (%) 3.0 2.0 2.5 1.0 1.5 0.5 10 20 30 40 50 60 70 80 90 100 0 0 3.5 v dd = 5v gain = 12db z spk = 4i + 33h max98355a/max98355b pcm input class d audio power amplifiers
???????????????????????????????????????????????????????????????? maxim integrated products 14 typical operating characteristics (continued) (v dd = 5v, v g nd = 0v, gain = v dd (+6db). bclk = 3.072mhz, lrclk = 48khz, speaker loads (z spk ) connected between outp and outn, z s pk = j , t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c.) inband output spectrum max98355a /b toc33 frequency (khz) amplitude (dbv) 18 16 2 4 6 10 12 8 14 -120 -100 -80 -60 -40 -20 0 20 -140 02 0 bclk = 3.072mhz lrclk = 48khz z spk = 8i + 68h inband output spectrum max98355a /b toc30 frequency (khz) amplitude (dbv) 18 16 2 4 6 10 12 8 14 -120 -100 -80 -60 -40 -20 0 20 -140 02 0 bclk = 6.144mhz lrclk = 96khz z spk = 8i + 68h inband output spectrum max98355a /b toc34 frequency (khz) amplitude (dbv) 18 16 2 4 6 10 12 8 14 -120 -100 -80 -60 -40 -20 0 20 -140 02 0 bclk = 3.072mhz lrclk = 48khz z spk = 8i + 68h inband output spectrum max98355a /b toc35 frequency (khz) amplitude (dbv) 18 16 2 4 6 10 12 8 14 -120 -100 -80 -60 -40 -20 0 20 -140 02 0 bclk = 2.8224mhz lrclk = 44.1khz z spk = 8i + 68h inband output spectrum max98355a /b toc31 frequency (khz) amplitude (dbv) 18 16 2 4 6 10 12 8 14 -120 -100 -80 -60 -40 -20 0 20 -140 02 0 bclk = 5.6448mhz lrclk = 88.2khz z spk = 8i + 68h inband output spectrum max98355a /b toc32 frequency (khz) amplitude (dbv) 18 16 2 4 6 10 12 8 14 -120 -100 -80 -60 -40 -20 0 20 -140 02 0 bclk = 5.6448mhz lrclk = 88.2khz z spk = 8i + 68h inband output spectrum max98355a /b toc36 frequency (khz) amplitude (dbv) 18 16 2 4 6 10 12 8 14 -120 -100 -80 -60 -40 -20 0 20 -140 02 0 bclk = 2.8224mhz lrclk = 44.1khz z spk = 8i + 68h max98355a/max98355b pcm input class d audio power amplifiers
???????????????????????????????????????????????????????????????? maxim integrated products 15 typical operating characteristics (continued) (v dd = 5v, v g nd = 0v, gain = v dd (+6db). bclk = 3.072mhz, lrclk = 48khz, speaker loads (z spk ) connected between outp and outn, z s pk = j , t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c.) inband output spectrum max98355a-b toc39 frequency (khz) amplitude (dbv) -120 -100 -80 -60 -40 -20 0 20 -140 f bclk = 1.024mhz f lrclk = 16khz z spk = 8 i + 68h 02468 10 12 14 16 18 20 inband output spectrum max98355a-b toc40 frequency (khz) amplitude (dbv) -120 -100 -80 -60 -40 -20 0 20 -140 f bclk = 1.024mhz f lrclk = 16khz z spk = 8 i + 68h 02468 10 12 14 16 18 20 inband output spectrum max98355a /b toc37 frequency (khz) amplitude (dbv) 18 16 2 4 6 10 12 8 14 -120 -100 -80 -60 -40 -20 0 20 -140 02 0 f bclk = 2.048mhz f lrclk = 32khz z spk = 8i + 68h inband output spectrum max98355a-b toc41 frequency (khz) amplitude (dbv) -120 -100 -80 -60 -40 -20 0 20 -140 f bclk = 512khz f lrclk = 8khz z spk = 8 i + 68h 02468 10 12 14 16 18 20 inband output spectrum max98355a-b toc42 frequency (khz) amplitude (dbv) -120 -100 -80 -60 -40 -20 0 20 -140 02468 10 12 14 16 18 20 f bclk = 512khz f lrclk = 8khz z spk = 8 i + 68h inband output spectrum max98355a /b toc38 frequency (khz) amplitude (dbv) 18 16 2 4 6 10 12 8 14 -120 -100 -80 -60 -40 -20 0 20 -140 02 0 bclk = 2.048mhz lrclk = 32khz z spk = 8i + 68h max98355a/max98355b pcm input class d audio power amplifiers
???????????????????????????????????????????????????????????????? maxim integrated products 16 max98355a/max98355b pcm input class d audio power amplifiers pin description pin configuration pin name function a1 sd_mode shutdown and channel select. determines left, right, or (left + right)/2 mix and also used for shutdown. see table 5. a2 v dd power-supply input a3 outp positive speaker amplifier output b1 din digital input signal b2 gain amplifier gain gain connections gain (db) gnd through 100k i resistor 15 gnd 12 unconnected 9 v dd 6 v dd through 100k i resistor 3 b3 outn negative speaker amplifier output c1 bclk bit clock input signal. bclk must be 32, 48, or 64 x lrclk. valid frequency range: 256khzC6.144mhz. c2 gnd ground c3 lrclk left/right word clock input. valid frequency range: 8khzC96khz. wlp top view bump side down gnd bclk lrclk gain din outn v dd sd_mode outp max98355a max98355b + a1 b1 c1 c2 c3 b2 b3 a3 a2
???????????????????????????????????????????????????????????????? maxim integrated products 17 max98355a/max98355b pcm input class d audio power amplifiers detailed description the max98355a/max98355b are digital pcm input class d power amplifiers. the max98355a accepts standard i 2 s data through din, bclk, and lrclk while the max98355b accepts left justified data through the same inputs. both versions can accept 16-bit tdm data with up to four slots. these devices eliminate the need for an external mclk signal that is typically required for pcm data transmission. sd_mode selects which data word is output by the amplifier and is used to put the ic into shutdown. the gain pin offers five gain settings and allows the output of the amplifier to be tuned to the appropriate level. the output stage features low-quiescent current, com - prehensive click-and-pop suppression, and excellent rf immunity. the ics offer class ab audio performance with class d efficiency in a minimal board-space solution. the class d amplifier features spread-spectrum modula - tion with edge-rate and overshoot control circuitry that offers significant improvements in switch-mode amplifier radiated emissions. the amplifier features click-and-pop suppression that reduces audible transients on startup and shutdown. the amplifier includes thermal-overload and short-circuit protection. digital audio interface modes the input stage of the digital audio interface is highly flexible, supporting 8khzC96khz sampling rates with 16/24/32-bit resolution for i 2 s/left justified data as well as up to a 4-slot, 16-bit time division multiplexed (tdm) format (only the first two slots can be selected by the ics). when lrclk has a 50% duty cycle the data format is determined by the part number selection (max98355a/max98355b). when a frame sync pulse is used for the lrclk the data format is automatically configured in tdm mode. the frame sync pulse indicates the beginning of the first time slot. mclk elimination the ics eliminate the need for the external mclk sig - nal that is typically used for pcm communication. this reduces emi and possible board coupling issues in addi - tion to reducing the size and pin-count of the ics. jitter tolerance the ics feature a very high bclk and lrclk jitter toler - ance of 0.5ns for rms jitter below 40khz and 12ns for wideband rms jitter while maintaining a dynamic range greater than 98db ( table 1 ). bclk polarity when operating in i 2 s/left justified mode, incoming serial data is always clocked-in on the rising edge of bclk. in tdm mode, the max98355a clocks-in serial data on the rising edge of bclk while the max98355b clocks in serial data on the falling edge of bclk ( table 2 ). lrclk polarity lrclk specifies whether left-channel data or right- channel data is currently being read by the digital audio interface. the max98355a indicates the left channel word when lrclk is low, and the max98355b indicates the left channel word when lrclk is high ( table 3 ). table 1. rms jitter tolerance table 2. bclk polarity table 3. lrclk polarity frequency rms jitter tolerance (ns) < 40khz 0.5 40khzCbclk 12 mode part number bclk polarity i 2 s/left justified max98355a/max98355b rising edge tdm max98355a rising edge max98355b falling edge part number lrclk polarity (left channel) max98355a low max98355b high
???????????????????????????????????????????????????????????????? maxim integrated products 18 max98355a/max98355b pcm input class d audio power amplifiers figure 4. max98355a i 2 s digital audio interface timing, 16-bit resolution pcm timing characteristics the max98355a follows standard i 2 s timing by allowing a delay of one bclk cycle after the lrclk transition before the beginning of a new data word ( figure 4 and figure 5 ). the max98355b follows the left justified timing specification by aligning the lrclk transitions with the beginning of a new data word ( figure 6 and figure 7 ). figure 8 and figure 9 show tdm operation, in which a frame-sync pulse is used for lrclk. in tdm mode, there must be 32, 48, or 64 bclk cycles per lrclk. in tdm mode, the ic only accepts 16-bit formatted data and only the first two tdm slots can be selected. however, if the first 16 bits are selected ( sd_mode = logic-high), then the bit-depth or number of channels has no effect as long as there are 32, 48, or 64 bclk cycles per lrclk. all extra bits in the frame are ignored ( figure 10 and figure 11 ). if the second 16 bits are selected ( sd_mode = logic- high through r small ), then the tdm data must be 16-bit data and cannot include more than 4 channels (64 bclk cycles). tdm operation is available in both ics. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 lrlck lrlck i 2 s: 16-bit data, 16 bits/channel, sd_mode = pullup through r small left left right left left right bclk ignored din d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 ignored din d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 din i 2 s: 16-bit data, 16 bits /channel, sd_mode = logic-high bclk lrlck left left right i 2 s: 16-bit data, 16 bits /channel, sd_mode = pullup through r large bclk left and right averaged ignored
???????????????????????????????????????????????????????????????? maxim integrated products 19 max98355a/max98355b pcm input class d audio power amplifiers figure 5. max98355a i 2 s digital audio interface timing, 24-bit resolution ignored left right d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d23d 22 d21 d20 d19 d18 d17 d16d 15 d14d 13 d12 d11 d10d 9d 8d 7d 6d 5d 4d 3d 2d 1d 0 d23 d22 i 2 s: 24-bit data, 32 bits /channel, sd_mode = logic-high lrlck bclk din ignored ignored d23 d22 d21 d20 d19 d18d 17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d23d 22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d23 d22 left right i 2 s: 24-bit data, 32 bits /channel, sd_mode = pullup through r small lrlck bclk din left and right averaged left right i 2 s: 24-bit data, 32 bits /channel, sd_mode = pullup through r large lrlck bclk din d23 d22d 21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d23d 22 d21 d20 d19d 18 d17d 16 d15 d14 d13 d12 d11 d10d 9d 8d 7d 6d 5d 4d 3d 2d 1d 0d 23 d22
???????????????????????????????????????????????????????????????? maxim integrated products 20 max98355a/max98355b pcm input class d audio power amplifiers figure 6. max98355b left-justified digital audio interface timing, 16-bit resolution ignored d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 lrclk left right bclk din left justified: 16-bit data, sd_mode = logic-high ignored d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 lrclk left right bclk din left justified: 16-bit data, sd_mode = pullup through r small left and right averaged d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 lrclk left right bclk din left justified: 16-bit data, sd_mode = pullup through r large ignored
???????????????????????????????????????????????????????????????? maxim integrated products 21 max98355a/max98355b pcm input class d audio power amplifiers figure 7. max98355b left-justified digital audio interface timing, 24-bit resolution lrclk bclk din left right ignored d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d31 d30 d29 left justified: 24-bit data, 32 bits /channel, sd_mode = logic-high left ignored lrclk bclk din left left right ignored d23 d22 left justified: 24-bit data, 32 bits /channel, sd_mode = pullup through r small d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 lrclk bclk din left left right d22 d23 left justified: 24-bit data, 32 bits /channel, sd_mode = pullup through r large left and right averaged d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
???????????????????????????????????????????????????????????????? maxim integrated products 22 max98355a/max98355b pcm input class d audio power amplifiers figure 8. max98355a tdm digital audio interface timing ignored tdm: 16-bit data, 32-bit frame, sd_mode = logic-hig h r1 r0 l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 l15 l14 l13 left and right averaged l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 ignored tdm: 16-bit data, 32-bit frame, sd_mode = pullup through r small r1 r0 l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 l15 l14 l13 tdm: 16-bit data, 32-bit frame, sd_mode = pullup through r large ignored ignored
???????????????????????????????????????????????????????????????? maxim integrated products 23 max98355a/max98355b pcm input class d audio power amplifiers figure 9. max98355b tdm digital audio interface timing ignored tdm: 16-bit data, 32-bit frame, sd_mode = logic-hig h r1 r0 l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 l15 l14 l13 ignored tdm: 16-bit data, 32-bit frame, sd_mode = pullup through r small r1 r0 l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 l15 l14 l13 left and right averaged tdm: 16-bit data, 32-bit frame, sd_mode = pullup through r large l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 ignored ignored
???????????????????????????????????????????????????????????????? maxim integrated products 24 max98355a/max98355b pcm input class d audio power amplifiers figure 10. max98355a tdm digital audio interface timing, example of four 16-bit slots y1 y0 l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 x15 x14 x13 x12 x11 x10 x9 x8 x7 x6 x5 x4 x3 x2 x1 x0 y15 y14 y13 y12 y11 y10 y9 y8 y7 y6 y5 y4 y3 y2 y1 y0 l15 l14 lrclk bclk din ignored tdm: 64-bit data, 64-bit frame, sd_mode = logic-hig h y1 y0 l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 x15 x14 x13 x12 x11 x10 x9 x8 x7 x6 x5 x4 x3 x2 x1 x0 y15 y14 y13 y12 y11 y10 y9 y8 y7 y6 y5 y4 y3 y2 y1 y0 l15 l14 lrclk bclk din ignored ignored tdm: 64-bit data, 64-bit frame, sd_mode = pullup through r small y1 y0 l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 x15 x14 x13 x12 x11 x10 x9 x8 x7 x6 x5 x4 x3 x2 x1 x0 y15 y14 y13 y12 y11 y10 y9 y8 y7 y6 y5 y4 y3 y2 y1 y0 l15 l14 lrclk bclk din ignored left and right averaged tdm: 64-bit data, 64-bit frame, sd_mode = pullup through r large ignored ignored
???????????????????????????????????????????????????????????????? maxim integrated products 25 max98355a/max98355b pcm input class d audio power amplifiers figure 11. max98355b tdm digital audio interface timing, example of four 16-bit slots y1 y0 l15 l14 l13 l12 l11 l10l 9l 8l 7l 6l 5l 4l 3l 2l 1l 0 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 x15x 14 x13x 12 x11x 10 x9 x8 x7 x6 x5 x4 x3 x2 x1 x0 y15y 14 y13 y12y 11 y10y 9y 8y 7y 6y 5y 4y 3y 2y 1y 0 l15 l14 ignored lrclk bclk din tdm: 64-bit data, 64-bit frame, sd_mode = logic-hig h y1 y0 l15 l14 l13 l12 l11 l10l 9l 8l 7l 6l 5l 4l 3l 2l 1l 0 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 x15x 14 x13x 12 x11x 10 x9 x8 x7 x6 x5 x4 x3 x2 x1 x0 y15y 14 y13 y12y 11 y10y 9y 8y 7y 6y 5y 4y 3y 2y 1y 0 l15 l14 ignored ignored lrclk bclk din tdm: 64-bit data, 64-bit frame, sd_mode = pullup through r small y1 y0 l15 l14 l13 l12 l11 l10l 9l 8l 7l 6l 5l 4l 3l 2l 1l 0 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 x15x 14 x13x 12 x11x 10 x9 x8 x7 x6 x5 x4 x3 x2 x1 x0 y15y 14 y13y 12 y11y 10 y9 y8 y7 y6 y5 y4 y3 y2 y1 y0 l15 l14 ignored left and right averaged lrclk bclk din tdm: 64-bit data, 64-bit frame, sd_mode = pullup through r large ignored ignored
???????????????????????????????????????????????????????????????? maxim integrated products 26 max98355a/max98355b pcm input class d audio power amplifiers standby mode if bclk stops toggling, the ics automatically enter standby mode. in standby mode, the class d speaker is turned off and the outputs go into a high-impedance state, ensuring that unwanted current is not transferred to the load during this condition. standby mode should not be used in place of the shutdown mode, as the shutdown mode provides the lowest power consumption and the best power-on/off click-and-pop performance. dac digital filters the dac features a digital lowpass filter that is automati - cally configured for voice playback or music playback based on the sample rate that is used. this filter elimi - nates the effect of aliasing and any other high-frequency noise that might otherwise be present. table 4 shows the digital filter settings that are automatically selected. sd_mode and shutdown operation the ics feature a low-power shutdown mode, drawing less than 0.6 f a (typ) of supply current. during shutdown, all internal blocks are turned off, including setting the output stage to a high-impedance state. drive sd_mode low to put the ics into shutdown. the state of sd_mode determines the audio channel that is sent to the amplifier output ( table 5 ). drive sd_mode high to select the left word of the stereo input data. drive sd_mode high through a sufficiently small resistor to select the right word of the stereo input data. drive sd_mode high through a sufficiently large resistor to select both the left and right words of the stereo input data ((left + right)/2). r large and r small are determined by the v ddio voltage (logic voltage from control interface) that is driving sd_mode according to the following two equations: r small (k i ) = 98.5 x v ddio - 100 r large (k i ) = 222.2 x v ddio - 100 table 4. digital filter settings table 5. sd_mode control table 6. examples of sd_mode pullup resistor values lrclk frequency -3db cutoff frequency ripple limit cutoff frequency stopband cutoff frequency stopband attenuation (db) f lrclk < 30khz 0.446 x f lrclk 0.443 x f lrclk 0.464 x f lrclk 75 30khz < f lrclk < 50khz 0.47 x f lrclk 0.43 x f lrclk 0.58 x f lrclk 60 f lrclk > 50khz 0.31 x f lrclk 0.24 x f lrclk 0.477 x f lrclk 60 sd_mode status selected channel high v sd_mode > b2 trip point (1.4v typ) left pullup through r small b2 trip point (1.4v typ) > v sd_mode > b1 trip point (0.77v typ) right pullup through r large b1 trip point (0.77 typ) > v sd_mode > b0 trip point (0.16v typ) (left + right)/2 low b0 trip point (0.16v typ) > v sd_mode shutdown logic voltage level (v ddio ) (v) r small (k i , 1% tolerance) r large (k i , 1% tolerance) 1.8 76.8 300 3.3 226 634
???????????????????????????????????????????????????????????????? maxim integrated products 27 max98355a/max98355b pcm input class d audio power amplifiers when the devices are configured in left-channel mode ( sd_mode is directly driven to logic-high by the con - trol interface), take care to avoid violating the absolute maximum ratings limits for sd_mode . ensuring that v dd is always greater than v ddio is one way to prevent sd_mode from violating the absolute maximum ratings limits. if this is not possible in the application (e.g., if v dd < 3.0v and v ddio = 3.3v, then it is necessary to add a small resistance (~2k i ) in series with sd_mode to limit the current into the sd_mode pin. this is not a concern when using the right channel or (left + right)/2 modes. figure 12 and figure 13 show how to connect an external resistor to sd_mode when using an open-drain driver or a pullup/down driver. class d speaker amplifier the filterless class d amplifier offers much higher efficiency than class ab amplifiers. the high efficiency of a class d amplifier is due to the switching operation of the output stage transistors. any power loss associated with the class d output stage is mostly due to the i 2 r loss of the mosfet on-resistance and quiescent current overhead. ultra-low emi filterless output stage traditional class d amplifiers require the use of external lc filters, or shielding, to meet en55022b electromag - netic-interference (emi) regulation standards. maxims active emissions-limiting edge-rate control circuitry and spread-spectrum modulation reduces emi emissions while maintaining up to 92% efficiency. figure 13. sd_mode resistor connection using pullup/down driver figure 12. sd_mode resistor connection using open-drain driver gpio processor v ddio r 100ki 8% left mode right mode (left + right/2 mode b2 (1.4v typ) b1 (0.77v typ) b0 (0.16v typ) v sd_mode max98355a max98355b gpio processor v ddio r 100ki 8% left mode right mode (left + right)/2 mode b2 (1.4v typ) b1 (0.77v typ) b0 (0.16v typ) v sd_mode max98355a max98355b
???????????????????????????????????????????????????????????????? maxim integrated products 28 max98355a/max98355b pcm input class d audio power amplifiers maxims spread-spectrum modulation mode flattens wideband spectral components while proprietary tech - niques ensure that the cycle-to-cycle variation of the switching period does not degrade audio reproduction or efficiency. the ics spread-spectrum modulator random - ly varies the switching frequency by q 10khz around the center frequency (300khz). above 10mhz, the wideband spectrum looks like noise for emi purposes ( figure 14 ). speaker current limit if the output current of the speaker amplifier exceeds the current limit (2.8a typ), the ic disables the outputs for approximately 100 f s. at the end of the 100 f s, the out - puts are re-enabled. if the fault condition still exists, the ic continues to disable and re-enable the outputs until the fault condition is removed. gain selection the ics offer five programmable gain selections through a single gain input (gain). gain is referenced to the full-scale output of the dac, which is 2.1dbv ( table 7 ). assuming that the desired output swing is not limited by the supply voltage rail, the ics output level can be calcu - lated based on the digital input signal level and selected amplifier gain according to the following equation: output signal level (dbv) = input signal level (dbfs) + 2.1db + selected amplifier gain (db) where 0dbfs is referenced to 0dbv. click-and-pop suppression the ic speaker amplifier features maxims comprehen - sive click-and-pop suppression. during startup, the click- and-pop suppression circuitry reduces audible transient sources internal to the device by ramping the input signal from mute to 0db. when entering shutdown, the differen - tial speaker outputs immediately go into a high-imped - ance state without creating audible click-and-pop noise. figure 14. emi with 12in of speaker cable and no output filtering table 7. gain selection gain gain (db) connect to gnd through 100k i q 5% resistor 15 connect to gnd 12 unconnected 9 connect to v dd 6 connect to v dd through 100k i q 5% resistor 3 frequency (mhz) emissions level (dbv/m) 900 800 600 700 200 300 400 500 100 10 30 50 70 90 -10 0 1000
???????????????????????????????????????????????????????????????? maxim integrated products 29 max98355a/max98355b pcm input class d audio power amplifiers figure 15. left-channel pcm operation with 6db gain figure 17. right-channel pcm operation with 6db gain figure 16. left-channel pcm operation with 12db gain applications information outp outn gain v dd 2.5v to 5.5v 0.1f 10f gpio* codec bit clock frame clock data out sd_mode bclk lrclk din gnd *responds to left channel when gpio is high. the max98355a/max98355b is shutdown when gpio is low. max98355a max98355b b2 a2 a1 c1 c3 b1 c2 b3 a3 outp outn gain v dd 2.5v to 5.5v 0.1f 10f gpio* codec bit clock frame clock data out sd_mode bclk lrclk din *responds to left channel when gpio is high. the max98355a/max98355b is shutdown when gpio is low. max98355a max98355b gnd b2 a2 a1 c1 c3 b1 c2 b3 a3 outp outn gain v dd 2.5v to 5.5v 0.1f 10f sd_mode bclk lrclk r small (76.8ki)** din gnd *responds to right channel when gpio is high. **76.8ki assumes v gpio = 1.8v. the max98355a/max98355b are shutdown when gpio is low. max98355a max98355b gpio* codec bit clock frame clock data out b2 a2 a1 c1 c3 b1 c2 b3 a3
???????????????????????????????????????????????????????????????? maxim integrated products 30 max98355a/max98355b pcm input class d audio power amplifiers figure 18. stereo pcm operation using two ics outp outn gain v dd 2.5v to 5.5v 0.1f 10f gpio* codec bit clock frame clock data out sd_mode bclk lrclk r small (76.8ki)** din gnd *responds to right channel when gpio is high. **76.8ki assumes v gpio = 1.8v. the max98355a/max98355b is shutdown when gpio is low. max98355a max98355b outp outn gain v dd 2.5v to 5.5v 0.1f 10f sd_mode bclk lrclk din gnd *responds to left channel when gpio is high. the max98355a/max98355b is shutdown when gpio is low. max98355a max98355b b2 a2 a1 c1 c3 b1 c2 b3 a3 b2 a2 a1 c1 c3 b1 c2 b3 a3
???????????????????????????????????????????????????????????????? maxim integrated products 31 max98355a/max98355b pcm input class d audio power amplifiers filterless class d operation traditional class d amplifiers require an output filter to recover the audio signal from the amplifiers output. the filter adds cost, size, and decreases efficiency and thd+n performance. the ics filterless modulation scheme does not require an output filter. the device relies on the inherent inductance of the speaker coil and the natural filtering of both the speaker and the human ear to recover the audio component of the square-wave output. because the switching frequency of the ics is well beyond the bandwidth of most speakers, voice coil movement due to the switching frequency is very small. use a speaker with a series inductance > 10 f h. typical 8 i speakers exhibit series inductances in the 20 f h to 100 f h range. power-supply input v dd , which ranges from 2.5v to 5.5v, powers the ic, including the speaker amplifier. bypass v dd with a 0.1 f f and 10 f f capacitor to gnd. some applications might require only the 10 f f bypass capacitor, making it pos - sible to operate with a single external component. apply additional bulk capacitance at the ics if long input traces between v dd and the power source are used. layout and grounding proper layout and grounding are essential for optimum performance. good grounding improves audio perfor - mance and prevents switching noise from coupling into the audio signal. use wide, low-resistance output traces. as load imped - ance decreases, the current drawn from the device outputs increases. at higher current, the resistance of the output traces decreases the power delivered to the load. for example, if 2w is delivered from the speaker output to a 4 i load through 100m i of total speaker trace, 1.904w is being delivered to the speaker. if power is delivered through 10m i of total speaker trace, 1.951w is being delivered to the speaker. wide output, supply, and ground traces also improve the power dissipation of the ics. the ics are inherently designed for excellent rf immu - nity. for best performance, add ground fills around all signal traces on top or bottom pcb planes. wlp applications information for the latest application details on wlp construction, dimensions, tape carrier information, pcb techniques, bump-pad layout, and recommended reflow temperature profile, as well as the latest information on reliability testing results, refer to the application note 1891: wafer-level packaging (wlp) and its applications . figure 20 shows the dimensions of the wlp balls used on the ics. figure 19. (left + right)/2 pcm operation with 6db gain figure 20. max98355a/max98355b wlp ball dimensions outp outn gain v dd 2.5v to 5.5v 0.1f 10f sd_mode bclk lrclk r large (300ki)** din gnd *left and right channels summed when gpio is high. **300ki assumes v gpio = 1.8v. the max98355a/max98355b is shutdown when gpio is low. max98355a max98355b gpio* codec bit clock frame clock data out b2 a2 a1 c1 c3 b1 c2 b3 a3 0.21mm 0.24mm
???????????????????????????????????????????????????????????????? maxim integrated products 32 max98355a/max98355b pcm input class d audio power amplifiers functional diagram ordering information + denotes a lead(pb)-free/rohs-compliant package. part temp range pin-package max98355a ewl+ -40 n c to +85 n c 9 wlp max98355b ewl+ -40 n c to +85 n c 9 wlp 2.5v to 5.5v 0.1f 10f lrclk bclk din sd_mode interpolatord ac class d output stage outp gain v dd outn digital audio interface c3 b1 c1 a1 c2 a2 b2 a3 b3 max98355a max98355b gnd
???????????????????????????????????????????????????????????????? maxim integrated products 33 max98355a/max98355b pcm input class d audio power amplifiers package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 9 wlp w91f1+1 21-0459 refer to application note 1891 e d aaaa pin 1 indicator marking a3 a2 a1 a see note 7 0.05 s s e d1 e1 b se sd 0.05 m s ab a b side view a top view bottom view a 1 1 package outline 9 bumps, wlp pkg. 0.4mm pitch 21-0459 d 0.64 0.19 0.45 0.025 0.27 0.80 0.80 0.40 0.00 0.00 w91f1+1 1.45 1.36 3 2 b c w91b1+7 w91c1+1 1.42 1.22 1.56 1.63 1.30 1.33 1.38 1.22 1.45 1.30 w91g1+1 1.45 1.48 1.44 1.47 title document control no. rev. 1 1 approval common dimensions a a2 a1 a3 b e1 d1 e sd se 0.05 0.03 0.03 basic ref basic min max max min e d pkg. code depopulated bumps none notes: 1. terminal pitch is defined by terminal center to center value. 2. outer dimension is defined by center lines between scribe lines. 3. all dimensions in millimeter. 4. marking shown is for package orientation reference only. 5. tolerance is 0.02 unless specified otherwise. 6. all dimensions apply to pbfree (+) package codes only. 7. front - side finish can be either black or clear. basic basic - drawing not to scale - none none none
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 34 ? 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 5/12 initial release max98355a/max98355b pcm input class d audio power amplifiers

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