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| 1 of 39 ds2408 1 - wire 8 - channel addressable switch www.maxim - ic.com features ? eight channels of programmable i/o with open - drain outputs ? on - resistance of pio pulldown transistor 100 ? (max); off - resistance 10m ? (typ) ? individual activity latches capture as ynchronous state changes at pio inputs for interrogation by the bus master ? data - strobe output to synchronize pio logic states to external read/write circuitry ? built - in multidrop controller ensures compatibility with other dallas semiconductor 1- wire ? net p roducts ? supports 1 - wire conditional search command with response controlled by program mable pio conditions ? unique factory - lasered 64 - bit registration number ensures error - free device selection and absolute part identity ? communicates to host with a single digital signal at 15.3kbps or 100kbps using 1 - wire protocol ? operating range: 2.8v to 5.25v, - 40c to +85c pin configuration 150- mil so ordering information part temp range pin - package DS2408S + - 40c to +85c 16 so DS2408S + t&r - 40c to +85c 16 so + denotes a lead(pb) - free package. t&r = tape and reel. description the ds2408 is an 8 - channel, programmable i/o 1- wire chip. pio outputs are configured as open - drain and provide an on resistance of 100 ? max. a robust pio channe l - access communication protocol ensures that pio output - setting changes occur error - free. a data - valid strobe out put can be used to latch pio logic states into external circuitry such as a d/a converter (dac) or microcontroller data bus. ds2408 operatio n is controlled over the single - conductor 1- wire bus. device communication follows the standard dallas semiconductor 1 - wire protocol. each ds2408 has its own unalterable and unique 64- bit rom registration number that is factory lasered into the chip. the r egistration number guarantees unique identification and is used to address the device in a multidrop 1 - wire net environment. multiple ds2408 devices can reside on a common 1 - wire bus and can operate independently of each other. the ds2408 also supports 1 -w ire conditional search capability based on pio conditions or power -on - reset activity; the conditions to cause participation in the conditional search are programmable. the ds2408 has an optional v cc supply connection. when an external supply is absent, dev ice power is supplied parasitically from the 1 - wire bus. when an external supply is present, pio states are maintained in the absence of the 1 - wire bus power source. the rstz signal is configurable to serve as either a hard - wired reset for the pio output o r as a strobe for external circuitry to indicate that a pio write or pio read has completed. 1 - wire is a registered trademark of maxim integrated products, inc. 19 - 5702 ; 12/10
ds2408 2 of 39 absolute maximum ratings* p0 to p7, rstz, i/o voltage to gnd - 0.5v, +6v p0 to p7, rstz, i/o combined sink current 20ma operating temperature range - 40c to +8 5c junction temperature +150c storage temperature range - 55c to +125c lead temperature (soldering 10s) +300c soldering temperature (reflow) +260c * this is a stress rating only and functional operation of the device at these or any other conditio ns above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. electrical characteristics (v cc = 0v or v pup , t a = - 40c or +8 5c.) parameter symbol conditions min typ max units 1 - wire pullup voltage v pup standard speed 2.8 5.25 v overdrive speed 3.3 5.25 standby supply current i ccs v cc at v pup, i/o pin at 0.3v 1 a i/o pin general data 1 - wire pullup resistance r pup (notes 1, 2) 2.2 k ? input capacitance c io (notes 3, 4) 1200 pf input load current i l i/o pin at v pup, v cc at 0v 1 a high - to - low switching threshold v tl (notes 4, 5, 6) 0.5 3.2 v input - low voltage v il (notes 1, 7) 0.30 v low - to - high s witching threshold v th (notes 4, 5, 8) 0.8 3.4 v switching hysteresis v hy (notes 9, 4) 0.16 0.73 v output - low voltage at 4ma v ol (note 10) 0.4 v recovery time (note 1) t rec standard speed, r pup = 2.2k ? 5 s overdrive speed, r pup = 2.2k ? 2 overdrive speed, directly prior to reset pulse; r pup = 2.2k ? 5 rising - edge hold - off time (notes 11, 4) t reh standard speed 0.5 5 s overdrive speed 0.5 2 timeslot duration (notes 1, 12) t slot standard speed 65 s overdrive speed 10 ds2408 3 of 39 parameter symbol conditions min typ max units i/o pin, 1 - wire reset, presence - detect cycle reset - low time (notes 1, 12) t rstl standard speed, v pup > 4.5v 480 720 s standard speed 660 720 overdrive speed 53 80 presence - detect high time (note 12) t pdh standard speed 15 60 s over drive speed 2 7 presence - detect fall time (note 13) t fpd standard speed, v pup > 4.5v 1 5 s standard speed 1 8 overdrive speed 1 presence - detect low time (note 12) t pdl standard speed, v pup > 4.5v 60 240 s standard speed 60 280 ov erdrive speed 7 27 presence - detect sample time (note 1) t msp standard speed, v pup > 4.5v 65 75 s standard speed 68 75 overdrive speed 8 9 i/o pin, 1 - wire write write - 0 low time (notes 1, 12 , 14 ) t w0l standard speed 60 120 s overdr ive speed 8 13 write - 1 low time (notes 1, 12, 14) t w1l standard speed 5 15 s overdrive speed 1 1.8 write sample time (slave sampling) (note 12) t sls standard speed 15 60 s overdrive speed 1.8 8 i/o pin, 1 - wire read read - low time (n otes 1, 15) t rl standard speed 5 15 - s overdrive speed 1 1.8 - read - 0 low time (data from slave) (note 12) t spd standard speed 15 60 s overdrive speed 1.8 8 read - sample time (notes 1, 12, 15) t msr standard speed t rl + 15 s overd rive speed t rl + 1.8 p0 to p7, rstz pin input - low voltage v il (notes 1, 7) 0.30 v input - high voltage v ih v x = max (v pup ,v cc ) (note 1) v x - 0.8 5.25 v output - low voltage at 4ma v ol (note 10) 0.4 v leakage current i lp 5.25v at the pin 1 a output fall time t fpio (notes 4, 16) 100 ns minimum - sensed pio pulse t pwmin (notes 4, 17) 1 5 s ds2408 4 of 39 note 1: system requirement note 2: maximum allowable pullup resistance is a function of the number of 1 - wire devices in the system and 1 - wire rec overy times. the specified value here applies to systems with only one device and with the minimum 1 - wire recovery times. for more heavily loaded systems, an active pullup such as that found in the ds2480b may be required. note 3: if a 2.2k ? resistor is u sed to pull up the data line to v pup , 5s after power has been applied, the parasite capacitance does not affect normal communications. note 4: guaranteed by design ? not production tested. note 5: v tl and v th are functions of the internal supply voltage, which in parasitic power mode, is a function of v pup and the 1 - wire recovery times. the v th and v tl maximum specifications are valid at v pup = 5.25v. in any case, v tl < v th < v pup . note 6: voltage below which, during a falling edge on i/o, a logic '0' i s detected. note 7: the voltage on i/o needs to be less or equal to v ilmax whenever the master drives the line low. note 8: voltage above which, during a rising edge on i/o, a logic '1' is detected. note 9: after v th is crossed during a rising edge o n i/o, the voltage on i/o has to drop by v hy to be detected as logic '0'. note 10: the i - v characteristic is linear for voltages less than 1v. note 11: the earliest recognition of a negative edge is possible at t reh after v th has been reached before. note 12: highlighted numbers are not in compliance with the published 1 - wire standards. see compari son table below. note 13: interval during the negative edge on i/o at the beginning of a presence detect pulse between the time at which the voltage is 90% of v pup and the time at which the voltage is 10% of v pup . note 14: in figure 14 represents the time required for the pullup circuitry to pull the voltage on i/o up from v il to v th . the actual maximum duration for the master to pull the line low is t w1 lmax + t f - and t w0lmax + t f - respectively. note 15: in figure 14 represents the time required for the pullup circuitry to pull the voltage on i/o up from v il to the input high threshold of the bus master. t he actual maximum duration for the master to pull the line low is t rlmax + t f . note 16: interval during the device - generated negative edge on any pio pin or the rstz pin between the time at which the voltage is 90% of v pup and the time at which the voltage is 10% of v pup . pio pullup resistor = 2 .2k ? . note 17: width of the narrowest pulse which trips the activity latch (for any pio pin) or causes a reset (for the rstz pin). for a pulse duration t pw : if t pw < t pwmin(min) , the pulse will be rejected. if t pwmin(min) < t pw < t pwmin(max) , the pulse ma y or may not be rejected. if t pw > t pwmin(max) the pulse will be recognized and latched. note 18: maximum instantaneous pulldown current through all port pins and the rstz pin combined. no requirement for current balance among different pins. ds2408 5 of 39 parameter name standard values ds2408 values standard speed overdrive speed standard speed overdrive speed min max min max min max min max t slot (incl. t rec ) 61s (undef.) 7s (undef.) 65s 1) (undef.) 10s (undef.) t rstl 480s (undef.) 48s 80s 660s 720s 53s 80s t pdh 15s 60s 2s 6s 15s 60s 2s 7s t pdl 60s 240s 8s 24s 60s 280s 7s 27s t w0l 60s 120s 6s 16s 60s 120s 8s 13s t sls , t spd 15s 60s 2s 6s 15s 60s 1.8s 8s 1) intentional change, longer recovery - time requirement due t o modified 1 - wire front end. pin description pin name description 1 n.c. not connected 2 p0 i/o pin of channel 0. logic input/open - drain output with 100 ? maximum on - resistance; 0v to 5.25v operating range. power - on default is indeterminate . if it is a pplication - critical for the outputs to power up in the "off" state, the user should attach an appropriate power - on - reset circuit or supervisor ic to the rstz pin. 3 v cc optional power supply input. range 2.8v to 5.25v; must be tied to gnd if not used. 4 i/o 1 - wire interface. open - drain, requires external pullup resistor. 5 gnd ground 6 n.c. not connected 7 p7 i/o pin of channel 7. same characteristics as p0. 8 p6 i/o pin of channel 6. same characteristics as p0. 9 p5 i/o pin of channel 5. same chara cteristics as p0. 10 rstz sw configurable pio reset input ( rst ) or open - drain strobe output ( strb ). when configured as rst , a low input sets all pio outputs to the "off" state by setting all bits in the pi o output latch state register. when configured as strb , an output strobe will occur after a pio write (see channel - access write command) or after a pio read (see channel - access read command). the power - on default function of this pin is rst . 11 p4 i/o pin of channel 4; same characteristics as p0 12 p3 i/o pin of channel 3; same characteristics as p0 13 p2 i/o pin of channel 2; same characteristics as p0 14 p1 i/o pin of channel 1; same characteristics as p0 15 n.c. not connected 16 n.c. not connected ds2408 6 of 39 application the ds2408 is a multipurpose device. typical applications include port expander for microcontrollers, remote multichannel sensor/actuator, communication and control unit of a microterminal, or as network inter face of a microcontroller. typical application circuits and communication examples are found later in this data sheet (figures 17 to 22). overview figure 1 shows the relationships between the major function blocks of the ds2408. the device has two main d ata components: 1) 64 - bit lasered rom, and 2) 64 - bit register page of control and status registers. figure 2 shows the hierarchical structure of the 1 - wire protocol. the bus master must first provide one of the eight rom function commands: 1) read rom, 2) match rom, 3) search rom, 4) condi tional search rom, 5) skip rom, 6) overdrive - skip rom, 7) overdrive - match rom, or 8) resume. upon completion of an overdrive rom command byte executed at standard speed, the device will enter overdrive mode, where all sub sequent communication occurs at a higher speed. the protocol required for these rom function commands is described in figure 12. after a rom function command is success - fully executed, the control functions become accessible and the master may provide any one of the five available commands. the protocol for these control commands is described in figure 8. all data is read and written least significant bit first. figure 1. ds2408 block diagram v cc 64-bit lasered rom crc16 generator register page register function control 1-wire function control port function control i/o gnd parasite power internal v cc port inter- face rstz p0 p1 p2 p3 p4 p5 p6 p7 ds2408 7 of 39 figure 2. hierarchical structure for 1 - wire protocol 1-wire net other devices bus master command level: 1-wire rom function commands ds2408-specific control function commands ds2408 available commands: read rom match rom search rom skip rom conditional search rom overdrive match overdrive skip resume read pio registers channel access read channel access write write conditional search register reset activity latches data field affected: 64-bit rom, rc-flag 64-bit rom, rc-flag 64-bit rom, rc-flag rc-flag 64-bit rom, rc-flag, port status, cond. search settings, 64-bit rom, rc-flag, od-flag rc-flag, od-flag rc-flag pio registers port input latches port output latches conditional search register activity latches cmd . codes: 33h 55h f0h cch ech 69h 3ch a5h f0h f5h 5ah cch c3h parasite power the ds2408 can derive its power entirely from the 1 - wire bus by storing energy on an internal capacitor during periods of time when the signal line is high. during low times the device conti nues to operate from this ?parasite? power source until the 1 - wire bus returns high to replenish the parasite (capacitor) supply. if power is available, the v cc pin should be connected to the external voltage supply. figure 3. 64 - bit lasered rom msb ls b 8 - bit crc code 48- bit serial number 8 - bit family code (29h) msb lsb msb lsb msb lsb 64- bit lasered rom each ds2408 contains a unique rom code that is 64 bits long. the first 8 bits are a 1 - wire family code. the next 48 bits are a unique serial num ber. the last eight bits are a crc of the first 56 bits. see figure 3 for details. the 1 - wire crc is generated using a polynomial generator consisting of a shift register and xor gates as shown in figure 4. the polynomial is x 8 + x 5 + x 4 + 1. additional in formation about the dallas 1 - wire cyclic redundancy check is avail able in application note 27 . ds2408 8 of 39 the shift register bits are initialized to 0. then, starting with the least significant bit of the family code, one bit at a time is shifted in. after the eigh th bit of the family code has been entered, the serial number is entered. after the serial number has been entered, the shift register contains the crc value. shifting in the eight bits of crc returns the shift register to all 0s. figure 4. 1 - wire crc gen erator x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 polynomial = x 8 + x 5 + x 4 + 1 1 st stage 2 nd stage 3 rd stage 4 th stage 6 th stage 5 th stage 7 th stage 8 th stage input data register access the registers needed to operate the ds2408 are organized as a register page, as shown in figure 5. all registers are volatile, i. e., they lose their state when the device is powered down. pio, conditi onal search, and control/status registers are read/written using the device level read pio registers and write conditional search register commands described in subsequent sections and figure 8 of this document. figure 5. ds2408 register address map ad dress range access type description 0000h to 0087h r undefined data 0088h r pio logic state 0089h r pio output latch state register 008ah r pio activity latch state register 008bh r/w conditional search channel selection mask 008ch r/w conditional se arch channel polarity selection 008dh r/w control/status register 008eh to 008fh r these bytes always read ffh ds2408 9 of 39 pio logic - state register the logic state of the pio pins can be obtained by reading this register using the read pio registers command. readi ng this register does not generate a signal at the rstz pin, even if it is configured as strb . see the channel - access commands description for details on strb . pio logic state register bitmap addr b7 b6 b5 b4 b3 b2 b1 b0 0088h p7 p6 p5 p4 p3 p2 p1 p0 this register is read - only. each bit is associated with the pin of the respective pio channel as shown in figure 6 . the data in this register is sampled at the last (most significant) bit of the byte that proceeds reading th e first (least significant) bit of this register. see the read pio registers command description for details. pio output latch state register the data in this register represents the latest data written to the pio through the channel - access write command . this register is read using the read pio registers command. reading this register does not generate a signal at the rstz pin, even if it is configured as strb . see the channel - access commands description for details on strb . this register is not affected if the device reinitializes itself after an esd hit. pio output latch state register bitmap addr b7 b6 b5 b4 b3 b2 b1 b0 0089h pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl0 this register is read - only. each bit is associated with the output latch of the respective pio channel as shown in figure 6 . the flip - flops of this register will power up in a random state. if the chip has to power up with all pio channels off, a low pulse must be generated on the rstz pin, e.g., by means of an o pen - drain cpu supervisor chip (see figure 20). when using an rc circuit to generate the power - on reset, make sure that rstz is not configured as strobe output (ros bit in control/status register 008dh needs to be 0). pio activity latch state register the data in this register represents the current state of the pio activity latches. this register is read using the read pio registers command. reading this register does not generate a signal at the rstz pin, even if it is configured as strb . see the channel - access commands description for details on strb . pio activity latch state register bitmap addr b7 b6 b5 b4 b3 b2 b1 b0 008ah al7 al6 al5 al4 al3 al2 al1 al0 this register is read - only. each bit is associated with the ac tivity latch of the respective pio channel as shown in figure 6 . this register is cleared to 00h by a power - on reset, by a low pulse on the rstz pin (only if rstz is config ured as rst input), or by successful execution of the reset activit y latches command. ds2408 10 of 39 figure 6. channel i/o and rstz simplified logic diagram pio out put latch pio acti vity latch edge detector port function control to activity latch state register to pio logic state register to pio output latch state reg. r q d d q s q q "1" clr act latch ros strb channel i/o pin rstz pin data clock power on reset conditional search channel selection mask register the data in this register controls whether a pio channel qualifies for participation in the condit ional search command. to include one or more of the pio channels, the bits in this register that correspond to those channels need to be set to 1. this register can only be written through the write conditional search registers command. conditional search channel selection mask register bitmap addr b7 b6 b5 b4 b3 b2 b1 b0 008bh sm7 sm6 sm5 sm4 sm3 sm2 sm1 sm0 this register is read/write. each bit is associated with the respective pio channel as shown in figure 7 . this register is cleared to 00h by a pow er - on reset ds2408 11 of 39 conditional search channel polarity selection register the data in this register specifies the polarity of each selected pio channel for the device to respond to the conditional search command. within a pio channel, the data source may be eith er the channel's input signal (pin) or the channel's activity latch, as specified by the pls bit in the control/status register at ad - dress 008dh. this register can only be written through the write conditional search registers command. conditional search channel polarity selection register bitmap addr b7 b6 b5 b4 b3 b2 b1 b0 008ch sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 this register is read/write. each bit is associated with the respective pio channel as shown in figure 7 . this register is cleared to 00h by a power - on reset. figure 7. conditional search logic al7 p7 pls sp0 sm0 ct sm7 sp7 al0 p0 csr input from channels 1 to 6 (not shown) channel 0 channel 7 ds2408 12 of 39 control/status register the data in this register reports status information, determines the function of the rstz pin and further configures the device for conditional sear ch. this register can only be written through the write condi - tional search registers command. control/status register bitmap addr b7 b6 b5 b4 b3 b2 b1 b0 008dh vccp 0 0 0 porl ros ct pls this register is read/write. without v cc supply, this register r eads 08h after a power - on reset. the func - tional assignments of the individual bits are explained in the table below. bits 4 to 6 have no function; they will always read 0 and cannot be set to 1. control/status register details bit description bit(s) defi nition pls: pin or activity latch select b0 selects either the pio pins or the pio activity latches as input for the conditional search. 0: pin selected (default) 1: activity latch selected ct: conditional search logical term b1 specifies whether th e data of two or more channels needs to be or?ed or and?ed to meet the qualifying condition for the device to respond to a conditional search. if only a single channel is selected in the channel selection mask (008bh) this bit is a don't care. 0: bitwise or (default) 1: bitwise and ros: rstz pin mode control b2 configures rstz as either rst input or strb output 0: configured as rst input (default) 1: configured as strb output porl: power -o n reset latch b3 specifies whether the device has performed a power - on reset. this bit can only be cleared to 0 under software control. as long as this bit is 1 the device will always respond to a conditional search. vccp: v cc power status (read - only) b7 for v cc powered operation the v cc pin needs to be tied to a voltage source v pup . 0: v cc pin is grounded 1: v cc - powered operation the interaction of the various signals that determine whether the device responds to a conditional search is illustrat ed in figure 7. the selection mask sm selects the participating channels. the polarity selection sp determines for each channel whether the channel signal needs to be 1 or 0 to qualify. the pls bit determines whether all channel signals are taken from the activity latches or i/o pins. the signals of all channels are fed into an and gate as well as an or gate. the ct bit finally selects the and?ed or or?ed result as the conditional search response signal csr. note on ct bit: or the qualifying condition i s met if the input (pin state or activity latch) for one or more selected channels matches the corresponding polarity. and for the qualifying condition to be met, the input (pin state or activity latch) for every selected channel must match the correspondi ng polarity. ds2408 13 of 39 figure 8 - 1 . control functions flow chart bus master tx ta1 (t7 :t0), ta2 (t15:t8) y n f0h read pio reg.? y n address < 90h? to figure 8 2 nd part from figure 8 2 nd part bus master tx control function command to rom functions flow chart (figure 12) from rom functions flow chart (figure 12) ds2408 sets register address = (t15 :t0) bus master rx data byte from register address bus master rx crc16 of command, address, data bytes bus master rx ?1?s y n ds2408 incre- ments address counter y y n n master tx reset? address < 90h? master tx reset? master tx reset? y n note: to read the three pio state and latch register bytes, the target address should be 0088h. returned data for a target address <0088h is undefined. address = 88h? y n ds2408 samples pio pin status 1) note 1) see the command description for the exact timing of the pio pin sampling. ds2408 14 of 39 figure 8 - 2 . control functions flow chart ds2408 15 of 39 figure 8 - 3 . control functions flow chart ds2408 16 of 39 control function commands onc e a rom function command is completed, the control function commands can be issued. the control functions flow chart (figure 8) describes the protocols necessary for accessing the pio channels and the special function registers of the ds2408 . the communica tion between the master and the ds2408 takes place either at standard speed (default, od = 0) or at overdrive speed (od = 1). if not explicitly set into the overdrive mode, the device operates at standard speed. read pio registers [f0h] the read pio regi sters command is used to read any of the device's registers. after issuing the command, the master must provide the 2 - byte target address. after these two bytes, the master reads data beginning from the target address and may continue until address 008fh. if the master continues reading, it will receive an inverted 16 - bit crc of the command, address bytes, and all data bytes read from the initial starting byte through the end of the register page. this crc16 is the result of clearing the crc generator and t hen shifting in the command byte followed by the two address bytes and the data bytes beginning at the first addressed location and continuing through to the last byte of the register page. after the bus master has received the crc16, the ds2408 responds t o any subsequent read - time slots with logical 1?s until a 1 - wire reset command is issued. if this command is issued with target address 0088h (pio logic state register), the pio sampling takes place during the transmission of the ms bit of ta2. if the targ et address is lower than 0088h, the sampling takes place while the master reads the ms bit from address 0087h. channel - access read [f5h] in contrast to reading the pio logical state from address 88h, this command reads the status in an endless loop. afte r 32 bytes of pio pin status the ds2408 inserts an inverted crc16 into the data stream, which allows the master to verify whether the data was received error - free. a channel - access read can be terminated at any time with a 1 - wire reset. figure 9. channel - access read timing io (1-wire) strb\ example - sampled state = 72h ms 2 bits of pre- vious byte (8dh) ls 2 bits of data byte (72h) t spd t spd t spd sampling point notes: 1) the "previous byte" could be the command code, the data byte resulting from the previous pio sample, or the ms byte of a crc16. the example shows a read - 1 time slot. 2) the sample point timing also appli es to the channel - access write command, with the "previous byte" being the write confirmation byte (aah). no strb pulse results when sampling occurs during a channel - access write command. ds2408 17 of 39 the status of all eight pio channels is sampled at the same time. the first sampling occurs during the last (most significant) bit of the command code f5h. while the master receives the msb of the pio status (i.e., the status of pin p7) the next sampling occurs and so on until the master has received 3 1 pio samples. next, the master receives the inverted crc16 of the command byte and 32 pio samples (first pass) or the crc of 32 pio samples (subsequent passes). while the last (most significant) bit of the crc is transmitted the next pio sampling takes pl ace. the delay between the beginning of the time slot and the sampling point is independent of the bit value being transmitted and the data direction (see figure 9). if the rstz pin is configured as strb , a strobe signal will be generated d uring the transmission of the first two (least significant) bits of pio data. the strobe can signal a fifo or a microcontroller to apply the next data byte at the pio for the master to read through the 1 - wire line. channel - access write [5ah] the channel - access write command is the only way to write to the pio output - latch state register (address 0089h), which controls the open - drain output transistors of the pio channels. in an endless loop this command first writes new data to the pio and then reads back the pio status. the implicit read - after - write can be used by the master for status verification or for a fast communication with a microcontroller that is connected to the port pins and rstz for synchronization. a channel - access write can be termi - nated a t any time with a 1 - wire reset. figure 10. channel - access write timing io (1-wire) pio strb\ 39h 72h t sls t spd t spd case #1 - ms bit of new pio state is 0 example - old state = 39h, new state = 72h ms 2 bits of inverted new-state byte (8dh) ls 2 bits of confir- mation byte ( aah) case #2 - ms bit of new pio state is 1 example - old state = 72h, new state = 93h ms 2 bits of inverted new-state byte (6ch) ls 2 bits of confir- mation byte ( aah) 72h 93h t spd t spd v th note: both examples assume that the rstz pin is configured as strb output. if rstz is configured as rst input (default), t he rstz pin needs to be tied high (to v cc or v pup ) for the channel - access write to function properly. leaving the pin unconnected will force the output transistors of the pio channels to the "off" state and the pio output latches will all read "1". see fig ure 6 for a schematic of the logic. after the command code the master transmits a byte that determines the new state of the pio output transistors. the first (least significant) bit is associated to p0. to switch the output transistor off (non - conducting) the corresponding bit value is 1. to switch the transistor on that bit needs to be 0. this way the data byte transmitted as the new pio output state arrives in its true form at the pio pins. to protect the transmission against data errors, the master has to repeat the new pio byte in its inverted form. only if the transmission was successful will the pio status change. the actual transition at the pio to the new state occurs during the last (most significant) bit of the inverted new pio data byte and depen ds on the polarity of that bit, as shown in figure 10. if this bit is a 1, the transition begins after t sls is expired; in case of a 0, the transition begins at the end of the time slot, when the v th threshold is crossed. to inform the master about the suc cessful change of the pio status, the ds2408 transmits a confirmation byte with ds2408 18 of 39 the data pattern aah. if the rstz pin is configured as strb , a strobe signal will be generated during the transmission of the first two (least sig nificant) bit s of the confirmation byte. the strobe can signal a fifo or a microcontroller to read the new data byte from the pio. while the last bit of the confirmation byte is transmitted, the ds2408 samples the status of the pio pins, as shown in figure 9, and sends it to the master. depending on the data, the mas ter can either continue writing more data to the pio or issue a 1 - wire reset to end the command. write conditional search register [cch] this command is used to tell the ds2408 the conditions that need to be met for the device to respond to a conditional search command, to define the function of the rstz pin and to clear the power - on reset flag. after issuing the command the master sends the 2 - byte target address, which must be a value between 008bh and 008dh. next the master sends the byte to be written to the addressed cell. if the address was valid, the byte is immediately written to its location in the register page. the master now can either end the command by issuing a 1 - wire reset or send another b yte for the next higher address. once register address 008dh has been written, any subsequent data bytes will be ignored. the master has to send a 1 - wire reset to end the command. since the write conditional search register flow does not include any error - checking for the new register data, it is important to verify correct writing by reading the registers using the read pio registers command. reset activity latches [c3h] each pio channel includes an activity latch that is set whenever there is a state tr ansition at a pio pin. this change may be caused by an external event/signal or by writing to the pio. depending on the application there may be a need to reset the activity latch after having captured and serviced an external event. since there is only re ad access to the pio activity latch state register, the ds2408 supports a special command to reset the latches. after having received the command code, the device resets all activity latches simultaneously. there are two ways for the master to verify the e xecution of the reset activity latches command. the easiest way is to start reading from the 1 - wire line right after the command code is transmitted. in this case the master will read aah bytes until it sends a 1 - wire reset. the other way to verify executi on is to read register address 008ah. 1 - wire bus system the 1 - wire bus is a system that has a single bus master and one or more slaves. in all instances the ds2408 is a slave device. the bus master is typically a microcontroller or pc. for small configur ations the 1 - wire communication signals can be generated under software control using a single port pin. for multisensor networks, the ds2480b 1 - wire line driver chip or serial port adapters based on this chip (ds9097u series) are recommended. this simplif ies the hardware design and frees the microprocessor from responding in real time. the discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1 - wire signaling (signal types and timing). the 1 - wir e protocol defines bus transactions in terms of the bus state during specific time slots that are initiated on the falling edge of sync pulses from the bus master. hardware configuration the 1 - wire bus has only a single line by definition; it is importan t that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1 - wire bus must have open drain or tri - state outputs. the 1 - wire port of the ds2408 is open - drain with an internal circuit equivalent to that shown in figure 11. ds2408 19 of 39 figure 11. hardware configuration open-drain port pin rx = receive tx = transmit 100 ? mosfet v pup rx tx tx rx data see text simple bus master ds2408 1-wire port r pup ds2480b +5v host cpu vdd pol rxd txd vpp 1-w nc gnd serial in serial out serial port to 1-wire data ds2480b bus master a multidrop bus consists of a 1 - wire bus with multiple slaves attached. at standard speed the 1 - wire bus has a maximum data rate of 15.3k bps. communication speed f or 1 - wire devices can be typically boosted to 142kbps by activating the overdrive mode; however, the maximum overdrive data rate for the ds2408 is 100kbps. the value of the pullup resistor primarily depends on the network size and load conditions. for most applications the optimal value of the pullup resistor will be approximately 2.2k ? for standard speed and 1.5k ? for overdrive speed. the idle state for the 1 - wire bus is high. if for any reason a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 16s (overdrive speed) or more than 120s (standard speed), one or more devices on the bus may be reset. with the ds2408 the bus must be left low f or no longer than 13s at overdrive speed to ensure that none of the slave devices on the 1 - wire bus performs a reset. the ds2408 communicates properly when used in conjunction with a ds2480b 1 - wire driver and serial port adapters that are based on this dr iver chip. when operating the device in overdrive or below 4.5v, some 1 - wire i/o timing values must be modified (see ec table). ds2408 20 of 39 transaction sequence the protocol for accessing the ds2408 through the 1 - wire port is as follows: ? initialization ? rom function c ommand ? control function command ? transaction/data illustrations of the transaction sequence for the various control function commands are found later in this document. initialization all transactions on the 1 - wire bus begin with an initialization sequence . the initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that the ds2408 is on the bus and is ready to operate. for more det ails, see the 1 - wire signaling section. rom function commands once the bus master has detected a presence, it can issue one of the seven rom function commands. all rom function commands are eight bits long. a list of these commands follows (see the flowch art in figure 12). read rom [33h] this command allows the bus master to read the ds2408's 8 - bit family code, unique 48 - bit serial number, and 8 - bit crc. this command can only be used if there is a single device on the bus. if more than one slave is presen t on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired - and result). the resultant family code and 48 - bit serial number will result in a mismatch of the crc. match rom [55h] the match rom command, followed by a 64 - bit rom sequence, allows the bus master to address a spe - cific ds2408 on a multidrop bus. only the ds2408 that exactly matches the 64 - bit rom sequence will respond to the following control function command. all slaves that do not match the 64 - bit rom se - quence will wait for a reset pulse. this command can be used with either single or multiple devices on the bus. search rom [f0h] when a system is initially brought up, the bus master might not know the number of devices on the 1- wire bus or their 64 - bit rom codes. the search rom command allows the bus master to use a process of elimination to identify the 64 - bit rom codes of all slave devices on the bus. the search rom process is the repetition of a simple three - step routine: read a bit, read the complement of the bit, then write the desired value of that bit. the bus master performs this simple, three - step routine on each bit of the rom. after one complete pass, the bus master knows the contents of the rom in one device. the remai ning number of devices and their rom codes may be identified by additional passes. see application note 187 for a detailed discussion on the search rom command process including a software example. conditional search [ech] the conditional search rom comm and operates similarly to the search rom command except that only devices fulfilling the specified condition will participate in the search. the condition is specified by the conditional search channel and polarity selection (addresses 008bh, 008ch), the b it functions ct and ds2408 21 of 39 pls of the control/status register (address 008dh), and the state of the pio channels. see figure 7 for a description of the conditional search logic. the device also responds to the conditional search if the porl bit is set. the condit ional search rom provides an efficient means for the bus master to deter - mine devices on a multidrop system that have to signal an important event, such as a state change at a pio pin caused by an external signal. after each pass of the conditional search that successfully deter - mined the 64 - bit rom for a specific device on the multidrop bus, that particular device can be individu - ally accessed as if a match rom had been issued, since all other devices will have dropped out of the search process and will be waiting for a reset pulse. skip rom [cch] this command can save time in a single - drop bus system by allowing the bus master to access the control functions without providing the 64 - bit rom code. if more than one slave is present on the bus and a read com mand is issued following the skip rom command, data collision will occur on the bus as multiple slaves transmit simultaneously (open - drain pulldowns will produce a wired - and result). resume command [a5h] in a typical application the ds2408 can be accessed several times to complete a control or adjustment function. in a multidrop environment this means that the 64 - bit rom sequence of a match rom com - mand has to be repeated for every access. to maximize the data throughput in a multidrop environment, the res ume command function is implemented. this function checks the status of the rc flag and, if it is set, directly transfers control to the control functions , similar to a skip rom com mand. the only way to set the rc flag is through successfully executing th e match rom, search rom, conditional search rom, or overdrive - match rom command. once the rc flag is set, the device can be repeatedly accessed through the resume command function. accessing another device on the bus will clear the rc flag, preventing two or more devices from simultaneously responding to the resume com mand function. skip rom [3ch] on a single - drop bus this command can save time by allowing the bus master to access the control functions without providing the 64 - bit rom code. unlike the no rmal skip rom command, the overdrive skip rom sets the ds2408 in the overdrive mode (od = 1). all communication following this command has to occur at overdrive speed until a reset pulse of minimum 480s duration resets all devices on the bus to standard s peed (od = 0). when issued on a multidrop bus this command will set all overdrive - supporting devices into overdrive mode. to subsequently address a specific overdrive - supporting device, a reset pulse at overdrive speed has to be issued followed by a match rom or search rom command sequence. this will speed up the time for the search process. if more than one slave supporting overdrive is present on the bus and the overdrive skip rom command is followed by a read command, data collision will occur on the bus as multiple slaves transmit simultaneously (open - drain pulldowns will produce a wired - and result). overdrive match rom [69h] the overdrive match rom command followed by a 64 - bit rom sequence transmitted at overdrive speed allows the bus master to address a specific ds2408 on a multidrop bus and to simultaneously set it in overdrive mode. only the ds2408 that exactly matches the 64 - bit rom sequence will respond to the subsequent control function command. slaves already in overdrive mode from a previous ove rdrive skip or match command will remain in overdrive mode. all overdrive - capable slaves will return to standard speed at the next reset pulse of minimum 480s duration. the overdrive match rom command can be used with either single or multiple devices on the bus. ds2408 22 of 39 figure 12 - 1. rom functions flow chart from figure 12 2 nd part to control functions flow chart (figure 8) master tx bit 0 master tx bit 63 master tx bit 1 rc = 1 ds2408 tx crc byte ds2408 tx serial number (6 bytes) ds2408 tx family code (1 byte) bit 0 match? y n bit 1 match? y n bit 63 match? y n ds2408 tx bit 0 ds2408 tx bit 0 master tx bit 0 ds2408 tx bit 1 ds2408 tx bit 1 master tx bit 1 ds2408 tx bit 63 ds2408 tx bit 63 master tx bit 63 rc = 1 bit 0 match? y n bit 1 match? y n bit 63 match? y n to figure 12 2 nd part rc = 0 rc = 0 rc = 0 rc = 0 y y y y n f0h search rom command? n 55h match rom command? n ech cond. search command? n 33h read rom command? to figure 12 2 nd part from control functions flow chart (figure 8) bus master tx rom function command ds2408 tx presence pulse od reset pulse? n y od = 0 bus master tx reset pulse from figure 12, 2 nd part condition met? y n ds2408 tx bit 0 ds2408 tx bit 0 master tx bit 0 ds2408 tx bit 1 ds2408 tx bit 1 master tx bit 1 ds2408 tx bit 63 ds2408 tx bit 63 master tx bit 63 rc = 1 bit 0 match? y n bit 1 match? y n bit 63 match? y n ds2408 23 of 39 figure 12 - 2. rom functions flow chart from figure 12 1 st part from figure 12 1 st part to figure 12, 1 st part rc = 1 ? n y rc = 0 ; od = 1 master tx bit 0 master tx bit 63 master tx bit 1 rc = 1 bit 0 match? y n bit 1 match? y n bit 63 match? y n y n 69h overdri ve match rom ? rc = 0 ; od = 1 master tx reset ? y n master tx reset ? n y y n 3ch overdri ve skip rom? y n a5h resum e comm and? rc = 0 y n cch skip rom comm and? to figure 12 1 st part ds2408 24 of 39 1 - wire signaling the ds2408 requires strict protocols to ensure data integrity. the protocol consists of four ty pes of signaling on one line: reset sequence with reset pulse and presence pulse, write - zero, write - one, and read - data. except for the presence pulse, the bus master initiates all these signals. the ds2408 can communicate at two different speeds, standard speed, and overdrive speed. if not explicitly set into the overdrive mode, the ds2408 will communicate at standard speed. while in overdrive mode, the fast timing applies to all waveforms. to get from idle to active, the voltage on the 1 - wire line needs to fall from v pup below the v tl threshold. to get from active to idle, the voltage needs to rise from v ilmax past the v th threshold. the v ilmax voltage is relevant for the ds2408 when determining a logical level, not triggering any events. figure 13 show s the initialization sequence required to begin any communication with the ds2408. a reset pulse followed by a presence pulse indicates the ds2408 is ready to receive data, given the correct rom and control function command. if the bus master uses slew - rat e control on the falling edge, it must pull down the line for t rstl + t f to compensate for the edge. a t rstl duration of 480s or longer will exit the overdrive mode returning the device to standard speed. if the ds2408 is in overdrive mode and t rstl is no longer than 80s the device will remain in overdrive mode. figure 13. initialization procedure ?reset and presence pulses? after the bus master has released the line it goes into receive mode (rx). the 1 - wire bus is then pul led to v pup via the pullup resistor or, in case of a ds2480b driver, by active circuitry. when the v th threshold is crossed, the ds2408 waits for t pdh and then transmits a presence pulse by pulling the line low for t pdl . to detect a presence pulse, the mas ter must test the logical state of the 1 - wire line at t msp . the t rsth window must be at least the sum of t pdhmax , t pdlmax , and t recmin . immediately after t rsth is expired, the ds2408 is ready for data communication. in a mixed population network, t rsth s hould be extended to a minimum of 480s at standard speed and 48s at overdrive speed to accommodate other 1 - wire devices. ds2408 25 of 39 read/write time slots data communication with the ds2408 takes place in time slots, which carry a single bit each. write time slot s transport data from bus master to slave. read time slots transfer data from slave to master. the definitions of the write and read time slots are illustrated in figure 14. all communication begins with the master pulling the data line low. as the volta ge on the 1 - wire line falls below the threshold v tl , the ds2408 starts its internal time base. the tolerance of the slave time base creates a slave - sampling window, which stretches from t slsmin to t slsmax . the voltage on the data line at the sampling point determines whether the ds2408 decodes the time slot as 1 or 0. master - to - slave for a write - one time slot, the voltage on the data line must have crossed the v thmax threshold after the write - one low time t w1lmax has expired. for a write - zero time slot, t he voltage on the data line must stay below the v thmin threshold until the write - zero low time t w0lmin has expired. for most reliable communication, the voltage on the data line should not exceed v ilmax during the entire t w0l window. after the v thmax thres hold has been crossed, the ds2408 needs a recovery time t rec before it is ready for the next time slot. figure 14. read/write timing diagram write - one time slot v pup v ihmaster v th v tl v ilmax 0v ds2408 sampling window t slsmin t f t slot t w1l t slsmax write - zero time slot t rec v pup v ihmaster v th v tl v ilmax 0v ds2408 sampling window t slsmin t f t slot t slsmax t w0l ds2408 26 of 39 read - data time slot slave - to - master a read - data time slot begins like a write - one time slot. the voltage on the data line must remain below v tlmin until the read low time t rl has expired. during the t rl window, when responding with a 0, the ds2408 starts pulling the data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. when responding with a 1, the ds2408 does not hold the data line low at all, and the voltage starts rising as soo n as t rl is over. the sum of t rl + (rise time) on one side and the internal timing generator of the ds2408 on the other side define the master sampling window (t msrmin to t msrmax ) in which the master must perform a read from the data line. for most rel iable communication, t rl should be as short as permissible and the master should read close to but no later than t msrmax . after reading from the data line, the master must wait until t slot is expired. this guarantees sufficient recovery time t rec for the d s2408 to get ready for the next time slot. improved network behavior in a 1 - wire environment, line termination is possible only during transients controlled by the bus master (1 - wire driver). 1 - wire networks therefore are susceptible to noise of various origins. depending on the physical size and topology of the network, reflections from end points and branch points can add up or cancel each other to some extent. such reflections are visible as glitches or ringing on the 1 - wire communication line. noise c oupled onto the 1 - wire line from external sources can also result in signal glitching. a glitch during the rising edge of a time slot can cause a slave device to lose synchronization with the master and, as a consequence, result in a search rom command com ing to a dead end or cause a device level command to abort. for better performance in network applications, the ds2408 uses a new 1- wire front end, which makes it less sensitive to noise and also reduces the magnitude of noise injected by the slave device itself. the 1 - wire front end of the ds2408 differs from traditional slave devices in four characteristics. 1) the falling edge of the presence pulse has a controlled slew rate. this provides a better match to the line impedance than a digitally switched tr ansistor, converting the high - frequency ringing known from traditional devices into a smoother low - bandwidth transition. the slew rate control is specified by the parameter t fpd , which has different values for standard and overdrive speed. 2) there is additi onal lowpass filtering in the circuit that detects the falling edge at the beginning of a time slot. this reduces the sensitivity to high - frequency noise. this additional filtering does not apply at overdrive speed. ds2408 27 of 39 3) the input buffer was designed with hyst eresis. if a negative glitch crosses v th but doesn?t go below v th - v hy , it will not be recognized (figure 15, case a). the hysteresis is effective at any 1 - wire speed. 4) there is a time window specified by the rising edge hold - off time t reh during which gl itches will be ignored, even if they extend below the v th - v hy threshold (figure 15, case b, t gl < t reh ). deep voltage droops or glitches that appear late after crossing the v th threshold and extend beyond the t reh window cannot be filtered out and will b e taken as the beginning of a new time slot (figure 15, case c, t gl t reh ). figure 15. noise suppression scheme v pup v th v hy 0v t reh t gl t reh t gl case a case c case b crc generation the ds2408 has two different types of cyclic redundancy checks (crcs). one crc is an 8 - bit typ e and is stored in the most significant byte of the 64 - bit rom. the bus master can compute a crc value from the first 56 bits of the 64 - bit rom and compare it to the value stored within the ds2408 to determine if the rom data has been received error free. the equivalent polynomial function of this crc is x 8 + x 5 + x 4 + 1. this 8 - bit crc is received in the true (noninverted) form. it is computed at the factory and lasered into the rom. the other crc is a 16 - bit type, generated according to the standardized crc16 - polynomial function x 16 + x 15 + x 2 + 1. this crc is used for error detection when reading data through the end of the register page using the read pio registers command, for fast verification of the data transfer when writing to or reading from the s cratchpad, and when reading from the pio using the channel - access read command. in contrast to the 8 - bit crc, the 16 - bit crc is always communicated in the inverted form. a crc - generator inside the ds2408 chip (figure 16) calculates a new 16 - bit crc as show n in the command flow chart of figure 8. the bus master compares the crc value read from the device to the one it calculates from the data and decides whether to continue with an operation or to reread the portion of the data with the crc error. with the read pio registers flow chart, the 16 - bit crc value is the result of shifting the command byte into the cleared crc generator, followed by the 2 address bytes and the data bytes beginning at the target address and ending with the last byte of the register page, address 008fh. with the initial pass through the channel - access read command flow, the crc is generated by first clearing the crc generator and then shifting in the command code followed by 32 bytes of pio pin data. subsequent passes through the c ommand flow will generate a 16 - bit crc that is the result of clearing the crc generator and then shifting in 32 bytes read from the pio pins. for more information on generating crc values see application note 27. ds2408 28 of 39 figure 16. crc - 16 hardware description and polynomial polynomial = x 16 + x 15 + x 2 + 1 x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 x 9 x 10 x 11 x 12 x 13 x 14 x 15 x 16 1 st stage 2 nd stage 3 rd stage 4 th stage 6 th stage 5 th stage 7 th stage 8 th stage 9 th stage 10 th stage 11 th stage 12 th stage 13 th stage 14 th stage 15 th stage 16 th stage input data crc output figure 17. ds2408 as slave interface for microcontroller vcc ds80c520 p1.0 3 p1.1 4 p1.2 5 p1.3 6 p1.4 7 p1.5 8 p1.6 9 p1.7 10 rst 12 p 3 . 7 / r d 22 p 3 . 6 / w r 21 p3.5/t1 20 p3.4/t0 19 p 3 . 3 / i n t 1 18 p 3 . 2 / i n t 0 17 p3.1/txd0 16 p3.0/rxd0 15 e a 42 xtal2 23 xtal1 24 rtcx2 27 rtcx1 28 p2.6/ad14 36 p2.5/ad13 35 p2.4/ad12 34 p2.3/ad11 33 p2.2/ad10 32 p2.7/ad15 37 p2.1/ad9 31 p2.0/ad8 30 psen 38 ale 39 p0.7/ad7 43 p0.6/ad6 44 p0.5/ad5 45 p0.4/ad4 46 p0.3/ad3 47 p0.2/ad2 48 p0.1/ad1 49 p0.0/ad0 50 47u ds2408 p0 2 p1 14 p2 13 p3 12 p4 11 p5 9 p6 8 p7 7 10 gnd 5 vcc 3 io 4 pullup provided by cpu 8051 equiv cpu gnd vcc 1w rstz the data direction (upload/download) is determined by application - specific data protocol. ds2408 29 of 39 figure 18. ds2408 as slave inter face for intelligent display 47 ds9503 1 2 5 6 3 4 47u vcc ledk 16 leda 15 d7 14 d6 13 d5 12 d4 11 d3 10 d2 9 d1 8 d0 7 s t b 6 r / w 5 d / c 4 contrast 3 vcc 2 gnd 1 vcc 10k 10 9 8 7 6 5 4 3 2 1 vcc ds2408 p0 2 p1 14 p2 13 p3 12 p4 11 p5 9 p6 8 p7 7 10 gnd 5 vcc 3 io 4 local ibutton probe lcd display up down select 5vdc gnd 1w rstz acm1601b 16x1 display with back light vcc figure 19. ds2408 as microcontroller port expander ds2408 io 4 vcc 3 gnd 5 10 p7 7 p6 8 p5 9 p4 11 p3 12 p2 13 p1 14 p0 2 vc c 2.2k vcc pic12c508 osc2/p4 3 osc1/p5 2 p0 7 p1 6 p2/ck 5 clr/p3 4 gnd 8 vcc 1 vcc microcontroller with few i/o pins rstz 24 i/o lines or 3 byte-wide buses from a single pin io 4 vcc 3 gnd 5 10 p7 7 p6 8 p5 9 p4 11 p3 12 p2 13 p1 14 p0 2 vcc rstz ds2408 io 4 vcc 3 gnd 5 10 p7 7 p6 8 p5 9 p4 11 p3 12 p2 13 p1 14 p0 2 vcc rstz ds2408 ds2408 30 of 39 figure 20. ds2408 as c - operated keyboard scanner vcc 10k ? 10 9 8 7 6 5 4 3 2 1 10u ds2408 p0 2 p1 14 p2 13 p3 12 p4 11 p5 9 p6 8 p7 7 10 gnd 5 vcc 3 io 4 por circuit to more switch rows (up to 4 x 4, 3 x 5 or 2 x 6) gnd vcc rst gnd ds1811 vcc vcc 1w rstz the ds1811 has an internal pull-up resistor of 5.5 k ? figure 21. ds2408 as parasite - powere d push - button sensor bat54 0.1u 100k 1 2 3 4 5 6 7 8 9 10 ds2408 p0 2 p1 14 p2 13 p3 12 p4 11 p5 9 p6 8 p7 7 10 gnd 5 vcc 3 io 4 switches or push-buttons parasite power vcc 1w gnd rstz ds2408 31 of 39 figure 22. ds2408 as multipurpose sensor/actuator 10k ? 10 9 8 7 6 5 4 3 2 1 vcc bss-84 5v 1n4004 47u vcc optoiso 1 2 4 5 6 1k ? 470 ? vcc led ds2408 p0 2 p1 14 p2 13 p3 12 p4 11 p5 9 p6 8 p7 7 10 gnd 5 vcc 3 io 4 4ma 8ma 1w vcc gnd rstz switches or push- buttons isolated output dry contact led indi- cator vcc ds2408 32 of 39 command - specific 1 - wire communication protocol ? legend symbol description rst 1 - wire reset pulse generated by master. pd 1 - w ire presence pulse generated by slave. select command and data to satisfy the rom function protocol. rpr command "read pio registers". car command "channel - access read". caw command "channel - access write". wcs command "write conditional search registe r". ral command "reset activity latches". ta target address ta1, ta2. transfer of an undetermined amount of data. crc16\ transfer of an inverted crc16. ff loop indefinite loop where the master reads ff bytes. aa loop indefinite loop where the master reads aa bytes. <32 samples>, crc16\ loop indefinite loop where the master reads 32 pio samples followed by an inverted crc16. ds2408 33 of 39 channel - access write (success) rst pd select caw ds2408 34 of 39 master mode data (lsb first) comments tx (reset) reset pulse rx (presence) presence pulse step 2 tx cch issue skip rom command tx f0h issue read pio registers command tx 8d h ta1, target address = 8dh tx 00h ta2, target address = 00 8dh rx 84h read control/status register and verify tx (reset) reset pulse rx (presence) presence pulse step 3 tx cch issue skip rom command tx 5ah issue channel - access write command tx ds2408 35 of 39 master mode dat a (lsb first) comments tx 04h write b yte to control/status register tx (reset) reset pulse rx (presence) presence pulse step 2 tx cch issue skip rom command tx f0h issue read pio registers command tx 8dh ta1, target address = 8dh tx 00h ta2, target address = 00 8dh rx 84h read control/s tatus register and verify tx (reset) reset pulse rx (presence) presence pulse step 3 tx cch issue skip rom command tx f5h issue channel - access read command ( ? ) ( ? ) ds2408 samples pio pin status rx ds2408 36 of 39 control/status register , source is activity latch ? pls = 1 term is or ? ct = 0 rstz = inactive (input) ? ros = 0 clear power - on reset latch ? porl = 0 the resulting setup d ata for the control/status register is 01h. for each ds2408 in the application, perform the following initialization: master mode data (lsb first) comments step 1 tx (reset) reset pulse rx (presence) presence pulse tx 55h issue match rom command tx <8 byte rom id> send rom id of the device to be accessed tx cch issue write conditional search register command tx 8bh ta1, target address = 8bh tx 00h ta2, target address = 00 8bh tx ffh write channel selection mask tx ffh write channel polarity selec tion tx 01h write control/status register tx (reset) reset pulse rx (presence) presence pulse tx a5h issue resume command tx f0h issue read pio registers command tx 8bh ta1, target address = 8bh tx 00h ta2, target address = 00 8bh rx ds2408 37 of 39 after all DS2408S are initialized, perform the search process below as an endless loop: master mode data (lsb first) comments step 4 tx (reset) reset pulse rx (presence) presence pulse tx ech issue conditional search rom command rx <2 bits> read 2 bits; if both bits are 1, no push button has been pressed; in this case return to step 4. if the bit pattern is 01 or 10 or 00, a push bu tton has been pressed; in this case continue with step 5. step 5 tx <1 bits> identify and select the ls bit of the rom id of the ds2408 that has responded to the conditional search. rx <2 bits> read 2 bits; this relates to the next bit of the rom id of the participating device(s). tx <1 bits> identify and select the next bit of the rom id of the ds2408 that has responded to the conditional search. (?) (?) repeat the previous 2 steps until one device has been identified and accessed. (see note 1) tx f0h issue read pio registers command tx 88h ta1, target address = 88h tx 00h ta2, target address = 00 00h rx <8 data bytes> read register page; the data in the activity latch state register tells which button has been pressed. rx <2 bytes crc16> read crc16 and verify correct data transmission. tx (reset) reset pulse rx (presence) presence pulse tx a5h issue resume command tx c3 issue reset activity latch command rx aah read for verification (aah = success) (?) (?) now, as the device and push but ton are identified and the activity latch is cleared, continue at step 4. note 1 : for a full description of the search algorithm see application note 187 . ds2408 38 of 39 applications information power - up timing the ds2408 is sensitive to the power - on slew rate and can inadvertently power up with a test mode feature enabled. when this occurs, the p0 port does not respond to the channel access write command. for most reliable operation, i t is recommended to disable the test mode after every power - on reset using the disable test mode sequence shown below. the 64 - bit rom code must be transmitted in the same bit sequence as with the match rom command, i.e., least significant bit first. this precaution is recommended in parasite power mode (v cc pin connected to gnd) as w ell as with v cc power. disable test mode rst pd 96h < 64- bit ds2408 rom code> 3ch rst pd power - up state of p0 to p7 when the ds2408 powers up, the state of the i/o pins p0 to p7 is indeterminate. this behavior may not be acceptable for some application s. to ensure that p0 to p7 power up in the "off" state, it is necessary to have a suitable power - on - reset circuit, such as the ds1811, or a supervisor ic connected to the rstz pin. rstz pin when not configured as strb output, the rstz pi n is to be connected to v cc , directly or through a resistor. a local v cc supply can be created by taking energy from the 1 - wire line, as shown in figure 21. package information for the latest package outline information and land patterns, go to www.maxim - ic.com/packages . note that a ?+?, ?#?, or ? - ? in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 16 so (150 mils) s16+5 21- 0041 90- 0097 ds2408 39 of 39 revi sion history revision date description pages changed 051403 initial release ? 122203 corrected the wiring in figure 18: in 4 - bit mode, the display uses d4 to d7. 28 061604 deleted empty page at the end 37 12/10 updated the ordering information for lea d(pb) - free; updated soldering temperature in the absolute maximum ratings . applied ec table note 14 to t w0l . deleted from the t w1l spec in the ec table. v tl /v th clarification: added to ec table note 5 the text ", which in parasitic power mode, is a fun ction of ..." added to ec table notes 14 and 15 the reference to figure 14 and the text "the actual maximum duration...." added to the write zero time slot graphic in figure 14. a dded the applications information section; added the package information section 1, 2 , 3, 4, 2 5, 38 maxim/dallas semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim/dallas semiconductor product. no circuit patent licenses are implied . maxim/dallas semiconductor reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 ? 2010 maxim integrated products maxim is a r egistered trademark of maxim integrated products, inc. the dallas logo is a registered trademark of dallas semiconductor. |
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