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universal single-chip clock solution for via p4m266/km266 ddr systems cy28347 cypress semiconductor corporation ? 3901 north first street san jose , ca 95134 408-943-2600 document #: 38-07352 rev. *c revised december 26, 2002 features ? supports via p4m266/km266 chipsets supports pentium ? 4, athlon ? processors supports two ddr dimms provides ? two different programmable cpu clock pairs ? six differential ddr sdram pairs ? two low-skew/low-jitter agp clocks ? six low-skew/low-jitter pci clocks ? one 48m output for usb ? one programmable 24m or 48m for sio dial-a-frequency ? and dial-a-db ? features spread spectrum for best electromagnetic interference (emi) reduction smbus-compatible for programmability 56-pin ssop and tssop packages note: 1. pins marked with [*] have internal pull-up resistors. pins marked with [**] have internal pull-down resistors. table 1. frequency selection table fs(3:0) cpu agp pci 0000 66.80 66.80 33.40 0001 100.20 66.80 33.40 0010 120.00 60.00 30.00 0011 133.33 66.67 33.33 0100 72.00 72.00 36.00 0101 105.00 70.00 35.00 0110 160.00 64.00 32.00 0111 140.00 70.00 35.00 1000 77.00 77.00 38.50 1001 110.00 73.33 36.67 1010 180.00 60.00 30.00 1011 150.00 60.00 30.00 1100 90.00 60.00 30.00 1101 100.00 66.67 33.33 1110 200.00 66.67 33.33 1111 133.33 66.67 33.33 block diagram pin configuration [1] vssr *fs0/ref0 xin xout vddagp *mode/agp0 *selp4_k7#/agp1 vssagp *pci_stp# pci1 *multsel/pci2 vsspci pci3 pci4 vddpci pci5 *cpu_stp# vss48m **fs3/48m **fs2/24_48m vdd48m vdd vss iref *pd# sclk sdata **fs1/pci_f vddr vttpwrgd#/ref1 vssc cput/cpuod_t cpuc/cpuod_c vddc vddi cpucs_t cpucs_c fbout buf_in ddrt0 ddrc0 ddrt1 ddrc1 vddd vssd ddrt2 ddrc2 ddrt3 ddrc3 vddd vssd ddrt4 ddrc4 ddrt5 ddrc5 vssi cy28347 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 2 3 4 5 6 7 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 pll1 s2d convert smbus cpucs_t vddc vddi cput/cpu0d_t selp4_k7# pci(3:5) pci_f fs1 ref(0:1) vddr fs0 48m 24_48m fbout ddrt(0:5) sclk sdata pd# agp(0:1) vddagp vdd48m vddd xtal xout xin fs2 pci2 pci1 vddpci pll2 / 2 buf_in ref0 fs3 multsel selsdr_ddr# ddrc(0:5) cpu_stp# pci_stp# cpucs_c cpuc/cpu0d_c
cy28347 document #: 38-07352 rev. *c page 2 of 22 pin description [2] pin name pwr i/o description 3xin i oscillator buffer input . connect to a crystal or to an external clock. 4xout vddo oscillator buffer output . connect to a crystal. do not connect when an external clock is applied at xin. 1 fs0/ref0 vdd i/o pu power-on bidirectional input/output . at power-up, fs0 is the input. when the power supply voltage crosses the input threshold voltage, fs0 state is latched and this pin becomes ref0, buffered copy of signal applied at xin. (1 ? 2 x strength, selectable by smbus. default value is 1 x strength.) 56 vttpwrgd# vddr i if selp4_k7# = 1, with a p4 processor setup as cpu(t:c) . at power-up, vtt_pwrgd# is an input. when this input is sampled low, the fs (3:0) and multsel are latched and all output clocks are enabled. after the first transition to a low on vtt_pwrgd#, this pin is ignored and will not effect the behavior of the device thereafter. when the vtt_pwrgd# feature is not used, please connect this signal to ground through a 10k ? resistor. ref1 vddr o if selp4_k7# = 0, with an athlon (k7) processor as cpuod_(t:c) . vtt_pwrgd# function is disabled, and the feature is ignored. this pin becomes ref1 and is a buffered copy of the signal applied at xin. 44,42,38, 36,32,30 ddrt(0:5) vddd o these pins are configured for ddr clock outputs . they are ? true ? copies of signal applied at pin45, buf_in. 43,41,37 35,31,29 ddrc(0:5) vddd o these pins are configured for ddr clock outputs . they are ? complementary ? copies of signal applied at pin45, buf_in. 7 selp4_k7#/ agp1 vddagp i/o pu power-on bidirectional input/output . at power-up, selp4_k7# is the input. when the power supply voltage crosses the input threshold voltage, selp4_k7# state is latched and this pin becomes agp1 clock output. selp4_k7# = 1 selects p4 mode. selp4_k7# = 0 selects k7 mode. 12 multsel/pci2 vddpci i/o pu power-on bidirectional input/output . at power-up, multsel is the input. when the power supply voltage crosses the input threshold voltage, multsel state is latched and this pin becomes pci2 clock output. multsel = 0, ioh is 4 x irefmultsel = 1, ioh is 6 x iref 53 cput/cpuod_t vddc o 3.3v true cpu clock outputs . this pin is programmable through strapping pin7, selp4_k7#. if selp4_k7# = 1, this pin is configured as the cput clock output. if selp4_k7# = 0, this pin is configured as the cpuod_t open drain clock output. see table 1. 5 2 cpuc/cpuod_c v d d c o 3.3v complementary cpu clock outputs . this pin is programmable through strapping pin7, selp4_k7#. if selp4_k7# = 1, this pin is configured as the cpuc clock output. if selp4_k7# = 0, this pin is configured as the cpuod_c open drain clock output. see table 1. 14,15,17 pci (3:5) vddpci o pci clock outputs . are synchronous to cpu clocks. see table 1. 48,49 cpucs_t/c vddi o 2.5v cpu clock outputs for chipset . see table 1 . 18 cpu_stp# vddpci i pu if pin 6 is pulled down at power on reset, then this pin becomes cpu_stp#. when cpu_stp# is asserted low, then both of the cpu signals stop at the next high to low transition or stays low if it already is low. this does not stop the cpucs signals. 10 fs1/pci_f vddpci i/o pd power-on bidirectional input/output . at power-up, fs1 is the input. when the power supply voltage crosses the input threshold voltage, fs1 state is latched and this pin becomes pci_f clock output. 20 fs3/48m vdd48m i/o pd power-on bidirectional input/output . at power-up, fs3 is the input. when the power supply voltage crosses the input threshold voltage, fs3 state is latched and this pin becomes 48m, a usb clock output. 11 pci1 vddpci o pci clock output . 21 fs2/24_48m vdd48m i/o pd power-on bidirectional input/output. at power-up, fs2 is the input. when the power supply voltage crosses the input threshold voltage, fs2 state is latched and this pin becomes 24_48m, a sio programmable clock output. note: 2. pu = internal pull-up. pd = internal pull-down. typically = 250 k ? (range 200 k ? to 500 k ? ).
cy28347 document #: 38-07352 rev. *c page 3 of 22 6 mode/agp0 vddagp i/o pu power-on bidirectional input/output . at power-up, mode is an input and becomes agp0 output after the power supply voltage crosses the input threshold voltage. must have 10k ? resistor to v ss . see table 2 . 8 pci_stp# vddagp i pu if pin 6 is pulled down at power on reset, then this pin becomes pci_stp# . when pci_stp# is asserted low, then all of the pci signals, except the pci_f, stops at the next high to low transition or stays low if it already is low. 25 iref i current reference programming input for cpu buffers . a precise resistor is attached to this pin, which is connected to the internal current reference. 28 sdata i/o serial data input . conforms to the smbus specification of a slave receive/transmit device. it is an input when receiving data. it is an open drain output when acknowledging or transmitting data. 27 sclk i serial clock input . conforms to the smbus specification. 26 pd# i pu when pd# is asserted low , the device enters power down mode. see power management function. 45 buf_in i 2.5v cmos type input to the ddr differential buffers . 46 fbout o this is the single-ended, sdram buffered output of the signal applied at buf_in . it is in phase with the ddrt(0:5) signals. 5vddagp 3.3v power supply for agp clocks . 51 vddc 3.3v power supply for cpu (t: c) clocks . 16 vddpci 3.3v power supply for pci clocks . 55 vddr 3.3v power supply for ref clock . 50 vddi 2.5v power supply for cpucs_t/c clocks . 22 vdd48m 3.3v power supply for 48m . 23 vdd 3.3v common power supply . 34,40 vddd 2.5v power supply for ddr clocks . 9 vssagp ground for agp clocks . 13 vsspci ground for pci clocks . 54 vssc ground for cpu (t:c) clocks . 33,39 vssd ground for ddr clocks . 19 vss48m ground for 48m clock . 47 vssi ground for cpucs_t/c clocks . 24 vss common ground . pin description (continued) [2] pin name pwr i/o description table 2. mode pin-power management input control mode, pin 6 (latched input) pin 26 pin 18 pin 8 0 pd# cpu_stp# pci_stp# invalid reserved reserved reserved table 3. swing select functions through hardware multsel board target trace/term z reference r, iref = vdd/(3*rr) output current voh@z 0 50 ohm rr = 221 1%, iref = 5.00 ma ioh = 4* iref 1.0v@50 1 50 ohm rr = 475 1%, iref = 2.32 ma ioh = 6* iref 0.7v@50
cy28347 document #: 38-07352 rev. *c page 4 of 22 serial data interface to enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. through the serial data interface, various device functions such as individual clock output buffers, etc., can be individually enabled or disabled. the registers associated with the serial data interface initializes to their default setting upon power-up, and therefore use of this interface is optional. clock device register changes are normally made upon system initialization, if any are required. the interface can also be used during system operation for power management functions. data protocol the clock driver serial protocol accepts byte write, byte read, block write, and block read operation from the controller. for block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. for byte write and byte read operations, the system controller can access individual indexed bytes. the offset of the indexed byte is encoded in the command code, as described in table 4 . the block write and block read protocol is outlined in table 5 while table 6 outlines the corresponding byte write and byte read protocol. the slave receiver address is 11010010 (d2h). table 4. command code definition bit description 7 0 = block read or block write operation 1 = byte read or byte write operation (6:0) byte offset for byte read or byte write operation. for block read or block write operations, these bits should be ? 0000000 ? table 5. block read and block write protocol block write protocol block read protocol bit description bit description 1 start 1 start 2:8 slave address - 7 bits 2:8 slave address - 7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 11:18 command code - 8 bit ? 00000000 ? stands for block operation 11:18 command code - 8 bit ? 00000000 ? stands for block operation 19 acknowledge from slave 19 acknowledge from slave 20:27 byte count - 8 bits 20 repeat start 28 acknowledge from slave 21:27 slave address - 7 bits 29:36 data byte 0 - 8 bits 28 read 37 acknowledge from slave 29 acknowledge from slave 38:45 data byte 1 - 8 bits 30:37 byte count from slave - 8 bits 46 acknowledge from slave 38 acknowledge .... data byte n/slave acknowledge... 39:46 data byte from slave - 8 bits .... data byte n - 8 bits 47 acknowledge .... acknowledge from slave 48:55 data byte from slave - 8 bits .... stop 56 acknowledge .... data bytes from slave/acknowledge .... data byte n from slave - 8 bits .... not acknowledge .... stop table 6. byte read and byte write protocol byte write protocol byte read protocol bit description bit description 1 start 1 start 2:8 slave address - 7 bits 2:8 slave address - 7 bits 9 write 9 write
cy28347 document #: 38-07352 rev. *c page 5 of 22 10 acknowledge from slave 10 acknowledge from slave 11:18 command code - 8 bits ? 1xxxxxxx ? stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed 11:18 command code - 8 bits ? 1xxxxxxx ? stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed 19 acknowledge from slave 19 acknowledge from slave 20:27 data byte from master ? 8 bits 20 repeat start 28 acknowledge from slave 21:27 slave address - 7 bits 29 stop 28 read 29 acknowledge from slave 30:37 data byte from slave - 8 bits 38 not acknowledge 39 stop table 6. byte read and byte write protocol (continued) byte 0: frequency select register bit @pup pin# name description 7 0 reserved. 6 h/w setting 21 fs2 for selecting frequencies see table 1. 5 h/w setting 10 fs1 for selecting frequencies see table 1. 4 h/w setting 1 fs0 for selecting frequencies see table 1. 3 0 if this bit is programmed to ? 1, ? it enables writes to bits (6:4,1) for selecting the frequency via software (smbus) if this bit is programmed to a ? 0 ? it enables only reads of bits (6:4,1), which reflect the hardware setting of fs(0:3). 2 h/w setting 11 reserved reserved 1 h/w setting 20 fs3 for selecting frequencies in table 1 . 0 h/w setting 7 selp4_k7# only for reading the hardware setting of the cpu interface mode, status of selp4_k7# strapping. byte 1 : cpu clocks register bit @pup pin# name description 7 0 ssmode 0 = down spread. 1 = center spread. see table 9 . 6 1 sscg 1 = enable (default). 0 = disable 5 1 sst1 select spread bandwidth. see table 9 . 4 1 sst0 select spread bandwidth. see table 9 . 3 1 48,49 cpucs_t/c_ en# 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 2 1 53,52 cpuod_t/c_en# 1 = output enabled (running). 0 = output disable asynchronously in a low state. 1 0 53,52 cput/c_pd_cntrl in k7 mode, this bit is ignored. in p4 mode, when pd# asserted low, 0 = drive cput to 2xiref and cpuc low and 1 = three-state cput and cpuc. 0 1 11 mult0 only for reading the hardware setting of the pin11 mult0 value. byte 2: pci clock register bit @pup pin# name description 7 0 pci_drv pci clock output drive strength 0 = normal, 1 = increase the drive strength 20%. 6 1 10 pci_f 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 5 1 reserved, set = 1.
cy28347 document #: 38-07352 rev. *c page 6 of 22 4 1 17 pci5 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 3 1 15 pci4 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 2 1 14 pci3 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 1 12 pci2 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 0 1 11 pci1 1 = output enabled (running). 0 = output disabled asynchronously in a low state. byte 3 : agp/peripheral clocks register bit @pup pin# name description 7 0 21 24_48m ? 0 ? = pin 21 output is 24 mhz. writing a ? 1 ? into this register asynchronously changes the frequency at pin 21 to 48 mhz. 6 1 20 48mhz 1 = output enabled (running). 0 = output disabled asynchro- nously in a low state. 5 1 21 24_48m 1 = output enabled (running). 0 = output disabled asynchro- nously in a low state. 4 0 6,7,8 dasag1 programming these bits allow shifting skew of the agp(0:2) signals relative to their default value. see table 7 . 3 0 6,7,8 dasag0 2 1 reserved, set = 1. 1 1 7 agp1 1 = output enabled (running). 0 = output disabled asynchro- nously in a low state. 0 1 6 agp0 1 = output enabled (running). 0 = output disabled asynchro- nously in a low state. byte 4 : peripheral clocks register bit @pup pin# name description 7 1 20 48m 1 = strength x 1. 0= strength x 2 1 = strength x 1. 0= strength x 2 6 1 21 24_48m 1 = strength x 1. 0= strength x 2 1 = strength x 1. 0= strength x 2 5 0 6,7,8 darag1 programming these bits allow modifying the frequency ratio of the agp(2:0), pci(6:1, f) clocks relative to the cpu clocks. see table 8 . 4 0 6,7,8 darag0 3 1 1 ref0 1 = output enabled (running). 0 = output disabled asynchro- nously in a low state. 2 1 56 ref1 1 = output enabled (running). 0 = output disabled asynchro- nously in a low state. (k7 mode only.) 1 1 1 ref0 1 = strength x 1. 0 = strength x 2 0 1 56 ref1 1 = strength x 1. 0 = strength x 2 (k7 mode only) byte 2: pci clock register (continued) bit @pup pin# name description table 7. dial-a-skew ? agp(0:2) dasag (1:0) agp(0:2) skew shift 00 default 01 ? 280 ps 10 +280 ps 11 +480 ps
cy28347 document #: 38-07352 rev. *c page 7 of 22 table 8. dial-a-ratio ? agp(0:2) darag (1:0) cu/agp ratio 00 frequency selection default 01 2/1 10 2.5/1 11 3/1 byte 5 : ddr clock register bit @pup pin# name description 7 0 45 buf_in threshold voltage ddr mode, buf_in threshold setting. 0 = 1.15v, 1 = 1.05v. 6 1 46 fbout 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 5 1 29,30 ddrt/c5 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 4 1 31,32 ddrt/c4 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 3 1 35,36 ddrt/c3 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 2 1 37,38 ddrt/c2 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 1 41,42 ddrt/c1 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 0 1 43,44 ddrt/c0 1 = output enabled (running). 0 = output disabled asynchronously in a low state. byte 6 : reserve register bit @pup description 71reserved. 60reserved. 50reserved. 40reserved. 30reserved. 20reserved. 10reserved. 00reserved. byte 7 : dial-a-frequency control register n bit @pup name description 7 0 reserved reserved for device function test. 6 0 n6, msb these bits are for programming the pll ? s internal n register. this access allows the user to modify the cpu frequency at very high resolution (accuracy). all other synchronous clocks (clocks that are generated from the same pll, such as pci) remain at their existing ratios relative to the cpu clock. 50n5 40n4 30n3 20n2 10n1 00n0, lsb
cy28347 document #: 38-07352 rev. *c page 8 of 22 dial-a-frequency feature smbus dial-a-frequency feature is available in this device via byte7 and byte9. p is a pll constant that depends on the frequency selection prior to accessing the dial-a-frequency feature. spread spectrum clock generation (sscg) spread spectrum is enabled/disabled via smbus register byte 1, bit 6. byte 8 : silicon signature register (all bits are read-only) bit @pup name description 7 0 revision_id3 revision id bit [3] 6 0 revision_id2 revision id bit [2] 5 0 revision_id1 revision id bit [1] 4 0 revision_id0 revision id bit [0] 3 1 vender_id3 cypress ? s vendor id bit [3] 2 0 vender_id2 cypress ? s vendorid bit [2] 1 0 vender_id1 cypress ? s vendor id bit [1] 0 0 vender_id0 cypress ? s vendor id bit [0] byte9 : dial-a-frequency control register r bit @pup name description 70 reserved 6 0 r5, msb these bits are for programming the pll ? s internal r register. this access allows the user to modify the cpu frequency at very high resolution (accuracy). all other synchronous clocks (clocks that are generated from the same pll, such as pci) remain at their existing ratios relative to the cpu clock. 50r4 40r3 30r2 20r1 10r0 0 0 daf_enb r and n register mux selection. 0=r and n values come from the rom. 1=data is load from daf (i2c) registers. fs(4:0) p xxxxx 96016000 table 9. spread spectrum table mode sst1 sst0 % spread 00 0 ? 1.5% 00 1 ? 1.0% 01 0 ? 0.7% 01 1 ? 0.5% 10 0 0.75% 10 1 0.5% 11 0 0.35% 11 1 0.25%
cy28347 document #: 38-07352 rev. *c page 9 of 22 maximum ratings [3] input voltage relative to v ss :.............................. v ss ? 0.3v input voltage relative to v ddq or av dd : ............. v dd + 0.3v storage temperature: ................................ ? 65 c to + 150 c operating temperature: .................................... 0 c to +70 c maximum esd .............................................................2000v maximum power supply: ................................................5.5v this device contains circuitry to protect the inputs against damage due to high static voltages or electric field. however, precautions should be take to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, v in and v out should be constrained to the range. v ss < (v in or v out ) < v dd unused inputs must always be tied to an appropriate logic voltage level (either v ss or v dd ). dc parameters (v dd = v ddpci = v ddagp = v ddr = v dd48m = v ddc = 3.3v 5%, v ddi = v dd = 2.5 5%, t a = 0 c to +70 c) parameter description conditions min. typ. max. unit vil1 input low voltage applicable to pd#, f s(0:4) 1.0 vdc vih1 input high voltage 2.0 vdc vil2 input low voltage applicable to sdata and sclk 1.0 vdc vih2 input high voltage 2.2 vdc vol output low voltage for sreset# iol 0.4 v iol pull-down current for sreset# vol = 0.4v 24 35 ma ioz three-state leakage current 10 a idd3.3v dynamic supply current cpu frequency set at 133.3 [4] 156 180 ma idd2.5v dynamic supply current cpu frequency set at 133.3 mhz [4] 177 200 ma ipd power-down supply current pd# = 0 3.8 4.0 ma ipup internal pull-up device current input @ v ss ? 25 a ipdwn internal pull-down device current input @ v dd 10 a cin input pin capacitance 5pf cout output pin capacitance 6pf lpin pin inductance 7pf cxtal crystal pin capacitance measured from the x in or x out to v ss 27 36 45 pf ac parameters parameter description 66 mhz 100 mhz 133 mhz 200 mhz unit notes min. max. min. max. min. max. min. max. crystal tdc xin duty cycle 4555455545554555%5,6,7,8 tperiod xin period 69.84 71.0 69.84 71.0 69.84 71.0 69.84 71.0 ns 5,6,7,8 vhigh xin high voltage 0.7v dd v dd 0.7v dd v dd 0.7v dd v dd 0.7v dd v dd v7,9 vlow xin low voltage 0 0.3v dd 00.3v dd 00.3v dd 00.3v dd v tr / tf xin rise and fall times 10.0 10.0 10 10 ns 7 tccj xin cycle to cycle jitter 500 500 500 500 ps 10,11,12,13 txs crystal start-up time 30 30 30 30 ms 9 notes: 3. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required. 4. all outputs loaded as per maximum capacitative load table in p4 and ddr mode. see tab le 11 . 5. all outputs loaded as per loading specified in the loading table. see ta ble 11 . 6. this measurement is applicable with spread on or spread off. 7. this is required for the duty cycle on the ref clock out to be as specified. the device will operate reliably with input duty cycles up to 30/70 but the ref clock duty cycle will not be within data sheet specifications. 8. the typical value of vx is expected to be 0.5*vddd (or 0.5*vddc for cpucs signals) and will track the variations in the dc le vel of the same. 9. measured between 0.2vdd and 0.7vdd. 10. probes are placed on the pins, and measurements are acquired between 0.4v and 2.4v for 3.3v signals and between 0.4v and 2.0 v for 2.5v signals, and between 20% and 80% for differential signals. 11. probes are placed on the pins, and measurements are acquired at 2.4v for 3.3v signals and at 2.0v for 2.5v signals. 12. when xin is driven from and external clock source (3.3v parameters apply). 13. when crystal meets minimum 40 ohm device series resistance specification.
cy28347 document #: 38-07352 rev. *c page 10 of 22 p4 mode cpu at 0.7v tdc cput/c duty cycle 45 55 45 55 45 55 45 55 % 5,6,10,14,15 tperiod cput/c period 14.85 15.3 9.85 10.2 7.35 7.65 4.85 5.1 ns 5,6,10,14,15 tr/tf cput/c rise and fall times 175 700 175 700 175 700 175 700 ps 15,16 rise/fall matching 20% 20% 20% 20% 16,17 delta tr/tf rise/fall time variation 125 125 125 125 ps 10,15,16,18 tskew cput/c to cpucs_t/c clock skew 100 100 100 100 ps 10,11,12,14,1 5 tccj cput/c cycle-to-cycle jitter 150 150 150 150 ps 6,10,11,12,14, 15 vcross crossing point voltage 280 430 280 430 280 430 280 430 mv 15. p4 mode cpu at 1.0v tdc cput/c duty cycle 4555455545554555%5,10,6,14 tperiod cput/c period 14.85 15.3 9.85 10.2 7.35 7.65 4.85 5.1 ns 5,10,6,14 differ- ential tr/tf cput/c rise and fall times 175 467 175 467 175 467 175 467 ps 10,11,19 delta tr/tf rise/fall time variation 125 125 125 125 ps 10,18 tskew cput/c to cpucs_t/c clock skew 100 100 100 100 ps 10,11,12,14 tccj cput/c cycle-to-cycle jitter 150 150 150 150 ps 10,11,12,14 vcross crossing point voltage 510 760 510 760 510 760 510 760 mv 19 se- deltaslew absolute single-ended rise/fall waveform symmetry 325 325 325 325 ps 20 k7 mode tdc cpuod_t/c duty cycle4555455545554555%5,6,10 tperiod cpuod_t/c period 14.85 15.3 9.85 10.2 7.35 7.65 4.85 5.1 ns 5,6,10 tlow cpuod_t/c low time 2.8 2.8 1.67 2.8 ns 5,6,10 tf cpuod_t/c fall time 0.4 1.6 0.4 1.6 0.4 1.6 0.4 1.6 ns 5,10,21 tccj cpuod_t/c cycle-to-cycle jitter 250 250 250 250 ps 6,10 vd differential voltage ac .4 vp+.6v .4 vp+.6v .4 vp+.6v .4 vp+.6v v 22 vx differential crossover voltage 500 1100 500 1100 500 1100 500 1100 mv 23 chipset tdc cpucs_t/c duty cycle 45 55 45 55 45 55 45 55 % 5,10,6 tperiod cpucs_t/c period 15 15.5 10.0 10.5 7.35 7.65 4.85 5.1 ns 5,10,6 notes: 14. measured at vx between the rising edge and the following falling edge of the signal. 15. determined as a fraction of 2*(trise-tfall)/(trise+tfall). 16. see figure 6 for 0.7v loading specification. 17. measurement taken from differential waveform, from -0.35v to +0.35v. 18. the time specified is measured from when all vdd ? s reach their respective supply rail (3.3v and 2.5v) till the frequency output is stable and operating within specifications. 19. ideally the probes should be placed on the pins. if there is a transmission line between the test point and the pin for one signal of the pair (e.g., cpu), you should add the same length transmission line to the other signal of the pair (e.g., agp). 20. measured in absolute voltage, i.e., single-ended measurement. 21. probes are placed on the pins, and measurements are acquired at 1.5v for 3.3v signals and at 1.25v for 2.5v, and 50% point f or differential signals. 22. measured at vx, or where subtraction of clk ? clk# crosses 0 volts. 23. vd is the magnitude of the difference between the measured voltage level on a ddrt (and cpucs_t) clock and the measured volt age level on its complementary ddrc (and cpucs_c) one. ac parameters (continued) parameter description 66 mhz 100 mhz 133 mhz 200 mhz unit notes min. max. min. max. min. max. min. max.
cy28347 document #: 38-07352 rev. *c page 11 of 22 tr / tf cpucs_t/c rise and fall times 0.4 1.6 0.4 1.6 0.4 1.6 0.4 1.6 ns 5,10,21 vd differential voltage ac 0.4 vp+ 0.6v 0.4 vp+ 0.6v 0.4 vp+ 0.6v 0.4 vp+ 0.6v v24 vx differential crossover voltage 0.5*vd di ? 0.2 0.5*vd di+0.2 0.5*vd di ? 0.2 0.5*vd di+0.2 0.5*vd di ? 0.2 0.5*vd di+0.2 0.5*vd di ? 0.2 0.5*vd di+0.2 v14 agp tdc agp(0:2) duty cycle 4555455545554555%5,6,10 tperiod agp(0:2) period 15 16 15 16 15 16 15 16 ns 5,6,10 thigh agp(0:2) high time 5.25 5.25 5.25 5.25 ns 10,25 tlow agp(0:2) low time 5.05 5.05 5.05 5.05 ns 10,18 tr/tf agp(0:2) rise and fall times 0.4 1.6 0.4 1.6 0.4 1.6 0.4 1.6 ns 10,21 tskew any agp to any agp clock skew 250 250 250 250 ps 10,11,12 tccj agp(0:2) cycle-to-cycle jitter 500 500 500 500 ps 6,10,11,12 pci tdc pci(_f,1:6) duty cycle4555455545554555%5,6,10 tperiod pci(_f,1:6) period 30.0 30.0 30.0 30.0 ns 5,6,10 thigh pci(_f,1:6) high time 12.0 12.0 12.0 12.0 ns 10,25 tlow pci(_f,1:6) low time 12.0 12.0 12.0 12.0 ns 10,18 tr/tf pci(_f,1:6) rise and fall times 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 ns 10,21 tskew any pci to any pci clock skew 500 500 500 500 ps 10,11,12 tccj pci(_f,1:6) cycle-to-cycle jitter 500 500 500 500 ps 10,6,11,12 48 mhz tdc 48-mhz duty cycle 4555455545554555%5,6,10 tperiod 48-mhz period 20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 ns 5,6,10 tr/tf 48-mhz rise and fall times 1.0 4.0 1.0 4.0 1.0 4.0 1.0 4.0 ns 10,21 tccj 48-mhz cycle-to-cycle jitter 500 500 500 500 ps 10,6,11,12 24 mhz tdc 24-mhz duty cycle 4555455545554555%5,6,10 tperiod 24-mhz period 41.660 41.667 41.660 41.667 41.660 41.667 41.660 41.667 ns 5,6,10 tr / tf 24-mhz rise and fall times 1.0 4.0 1.0 4.0 1.0 4.0 1.0 4.0 ns 10,21 tccj 24-mhz cycle-to-cycle jitter 500 500 500 500 ps 6,10,11,12 notes: 24. measured at vx between the falling edge and the following rising edge of the signal. 25. probes are placed on the pins, and measurements are acquired at 0.4v. ac parameters (continued) parameter description 66 mhz 100 mhz 133 mhz 200 mhz unit notes min. max. min. max. min. max. min. max.
cy28347 document #: 38-07352 rev. *c page 12 of 22 connection circuit ddrt/c signals ref tdc ref duty cycle 4555455545554555%5,10,6 tperiod ref period 69.8413 71.0 69.8413 71.0 69.8413 71.0 69.8413 71.0 ns 5,6,10 tr/tf ref rise and fall times 1.0 4.0 1.0 4.0 1.0 4.0 1.0 4.0 ns 10,21 tccj ref cycle-to-cycle jitter 1000 1000 1000 1000 ps 6,10,11,12 ddr vx crossing point voltage of ddrt/c 0.5*vd dd ? 0.2 0.5*vd dd+0.2 0.5*vd dd ? 0.2 0.5*vd dd+0.2 0.5*vd dd ? 0.2 0.5*vd dd+0.2 0.5*vd dd ? 0.2 0.5*vd dd+0.2 v23 vd differential voltage swing 0.7 vddd + 0.6 0.7 vddd + 0.6 0.7 vddd + 0.6 0.7 vddd + 0.6 v22 tdc ddrt/c(0:5) duty cycle 45 55 45 55 45 55 45 55 % 14 tperiod ddrt/c(0:5) period 14.85 15.3 9.85 10.2 14.85 15.3 9.85 10.2 ns 14 tr/tf ddrt/c(0:5) rise/fall slew rate 13131313v/ns21 tskew ddrt/c to any ddrt/c clock skew 100 100 100 100 ps 10,11,14 tccj ddrt/c(0:5) cycle-to-cycle jitter 75 75 75 75 ps 10,11,14 thpj ddrt/c(0:5) half period jitter 100 100 100 100 ps 10,11,14 tdelay buf_in to any ddrt/c delay 14141414ns6,10 tskew fbout to any ddrt/c skew 100 100 100 100 ps 6,10 tstable all clock stabilization from power-up 1.5 1.5 1.5 1.5 ms 12 ac parameters (continued) parameter description 66 mhz 100 mhz 133 mhz 200 mhz unit notes min. max. min. max. min. max. min. max. measurement point ddrt t pcb t pcb ddrc 100 ? measurement point 16 pf 16 pf figure 1. differential ddr termination
cy28347 document #: 38-07352 rev. *c page 13 of 22 for open drain cpu output signals (with k7 processor selp4_k7# = 0) for differential cpu output signals (with p4 processor selp4_k7#= 1) the following diagram shows lumped test load configurations for the differential host clock outputs. figure 4 is for the 1.0v amplitude signalling and figure 5 is for the 0.7v amplitude signalling. measurement point measurement point 20 pf 20 pf 680 pf 680 pf 47 ohm 47 ohm 52 ohm 5" 52 ohm 5" cpuod_t cpuod_c vddcpu(1.5v) 500 ohm vddcpu(1.5v) 500 ohm 60.4 ohm 60.4 ohm 301 ohm 500 ohm 500 ohm 3.3v 3.3v 52 ohm 1 " 52 ohm 1" figure 2. k7 termination 6? 6 ? figure 3. chipset termination measurement point 2 pf cput multsel t pcb t pcb cpuc 221 ? 63.4 ? 63.4 ? 475 ? 33.2 ? 33.2 ? measurement point 2 pf iref figure 4. p4 1.0v configuration
cy28347 document #: 38-07352 rev. *c page 14 of 22 cput multsel t pcb t pcb cpuc 33 ? 33 ? 49.9 ? 49.9 ? measurement point 2 pf 475 ? iref measurement point 2 pf figure 5. p4 0.7v configuration table 10. group timing relationships and tolerances offset (ps) tolerance (ps) conditions t csagp cpucs to agp 750 500 cpucs leads t ap agp to pci 500 500 agp leads table 11. signal loading clock name max. load (in pf) ref (0:1), 48mhz (usb), 24_48mhz 20 agp(0:2), pci_f(0:5)sdram (0:11) 30 fbout 10 ddrt/c see figure 1 cput/c see figure 4 and figure 5 cpuod_t/c see figure 2 cpucs_t/c see figure 3 0 ns 10 ns 20 ns 30 ns agp clock 66.6 mhz pci clock 33.3 mhz cpu clock 66.6 mhz cpu clock 100 mhz cpu clock 133.3 mhz t ap t csagp figure 6. clock timing relationships
cy28347 document #: 38-07352 rev. *c page 15 of 22 cpu_stp# assertion (p4 mode) when cpu_stp# pin is asserted, all cpu outputs will be stopped after being sampled by two rising cpuc clock edges. the final state of the stopped cpu signal is cput = high and cpuc = low. there is no change to the output drive current values during the stopped state. the cput is driven high with a current value equal to (mult 0 ? select ? ) x (iref), and the cpuc signal will not be driven. due to external pulldown circuitry cpuc will be low during this stopped state. cpu_stp# deassertion (p4 mode) the deassertion of the cpu_stp# signal will cause all cpu outputs that were stopped to resume normal operation in a synchronous manner. synchronous manner meaning that no short or stretched clock pulses will be produce when the clock resumes. the maximum latency from the deassertion to active outputs is no more than two cpu clock cycles. cpu_stp# cput cpuc figure 7. cpu_stp# assertion waveform (p4 mode) table 12. cpu_stp# functionality cpu_stp# cpu#4 cpu 1 normal normal 0iref*multfloat cpu_stp# cpucs_t cpucs_c cput cpuc figure 8. cpu_stp# deassertion waveform (p4 mode)
cy28347 document #: 38-07352 rev. *c page 16 of 22 cpu_stp# assertion (k7 mode) when cpu_stp# pin is asserted, all cpu outputs will be stopped after being sampled by two rising cpuc clock edges. the final state of the stopped cpu signal is cpuod_t = low and cpuod_c = low. cpu_stp# deassertion (k7 mode) the deassertion of the cpu_stp# signal will cause all cpu outputs that were stopped to resume normal operation in a synchronous manner. synchronous manner meaning that no short or stretched clock pulses will be produce when the clock resumes. the maximum latency from the deassertion to active outputs is no more than two cpu clock cycles. cpu_stp# cpuod_t cpuod_c figure 9. cpu_stp# assertion waveform (k7 mode) cpu_stp# cpucs_t cpucs_c cpuod_t cpuod_c figure 10. cpu_stp# deassertion waveform (k7 mode)
cy28347 document #: 38-07352 rev. *c page 17 of 22 pci_stp# assertion the pci_stp# signal is an active low input used for synchronous stopping and starting the pci outputs while the rest of the clock generator continues to function. the setup time for capturing pci_stp# going low is 10 ns (t setup ). the pci_f clock will not be affected by this pin. pci_stp#- deassertion the deassertion of the pci_stp# signal will cause all pci clocks to resume running in a synchronous manner within one pci clock period after pci_stp# transitions to a high level. power management functions all clocks can be individually enabled or stopped via the 2-wire control interface. all clocks maintain valid high period on transitions from running to stop and on transitions from stopped to running when the chip was not powered off. power down assertion (p4 mode) when pd# is sampled low by two consecutive rising edges of cpuc clock then all clocks must be held low on their next high to low transition. cput clocks must be held with a value of 2 x iref, pci_stp# pci_f pci(1:6) setup t figure 11. pci_stp# assertion waveform pci_stp# pci_f pci(1:6) setup t figure 12. pci_stp# deassertion waveform
cy28347 document #: 38-07352 rev. *c page 18 of 22 p4 processor selp4_k7# = 1 . power-down deassertion (p4 mode) the power-up latency needs to less than 1.5ms. pci 33mhz pw rdw n# cput 133mhz cpuc 133mhz ref 14.318mhz usb 48mhz ddrt 133mhz ddrc 133mhz agp 66mhz figure 13. power-down assertion timing waveform (in p4 mode) ref 14.318mhz pci 33mhz pw rdw n# cput 133mhz cpuc 133mhz agp 66mhz usb 48mhz <1.5 m sec ddrt 133mhz ddrc 133mhz figure 14. power-down deassertion timing waveform (in p4 mode)
cy28347 document #: 38-07352 rev. *c page 19 of 22 amd k7 processor selp4_k7# = 0 power-down assertion (k7 mode) when the pd# signal is asserted low, all clocks are disabled to a low level in an orderly fashion prior to removing power from the cpu. when pd# is sampled low by two consecutive rising edges of the cpucs_c clock, then all affected clocks are stopped in a low state after the next high to low transition or remains low. when in power-down (and before power is removed), all outputs are synchronously stopped in a low state (see figure 15 below), all plls are shut off, and the crystal oscillator is disabled. when the device is shutdown, the i2c function is also disabled. power down deassertion (k7 mode) when deasserted pd# to high level, all clocks are enabled and start running on the rising edge of the next full period in order to guarantee a glitch-free operation, no partial clock pulses. pci 33mhz pwrdwn# ref 14.318mhz usb 48mhz ddrt 133mhz ddrc 133mhz agp 66mhz cpuod_c 133mhz cpucs_c 133mhz cpuod_t 133mhz cpucs_t 133mhz figure 15. power-down assertion timing waveform (in k7 mode) pci 33mhz pwrdwn# agp 66mhz ref 14.318mhz usb 48mhz <1.5 msec ddrt 133mhz ddrc 133mhz cpuod_t 133mhz cpucs_t 133mhz cpuod_c 133mhz cpucs_c 133mhz figure 16. power-down deassertion timing waveform (in k7 mode)
cy28347 document #: 38-07352 rev. *c page 20 of 22 note: 26. this timing diagram shows that vtt_pwrgd# transits to a logic low in the first time at power up. after the first high to low transition of vtt_pwrgd#, device is not affected, vtt_pwrgd# is ignored. vid (0:3), sel (0,1) vtt_pwrgd# pwrgd vdd clock gen clock state clock outputs clock vco 0.2-0.3ms delay state 0 state 2 state 3 wait for vtt_gd# sample sels off off on on state 1 (note a) figure 17. vtt_pwgd# timing diagram (with advanced piii processor selp4_k7# = 1) [26] v t t p w r g d # = l o w delay 0.25m s s1 power off s0 vdda = 2.0v sample inputs fs(3:0) s2 vdd3.3 = off normal operation s3 wait for 1.146m s enable outputes figure 18. clock generator power-up/run state diagram (with p4 processor selp4_k7# = 1 ) ordering information part number package type product flow cy28347oc 56-pin shrunk small outline package (ssop) commercial, 0 to 70 c cy28347oct 56-pin shrunk small outline package (ssop) ? tape and reel commercial, 0 to 70 c cy28347zc 56-pin thin shrunk small outline package (tssop) commercial, 0 to 70 c CY28347ZCT 56-pin thin shrunk small outline package (tssop) ? tape and reel commercial, 0 to 70 c
cy28347 document #: 38-07352 rev. *c page 21 of 22 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package drawing and dimensions purchase of i2c components from cypress or one of its sublicensed associated companies conveys a license under the philips i2c patent rights to use these components in an i2c system, provided that the system conforms to the i2c standard specification as defined by philips. via is a trademark of via technologies, inc. pentium 4 is a registered trademark of intel corporation. athlon is a trademark of amd corporation, inc. dial-a-frequency, dial-a-db, dial-a-skew, and dial-a-ratio are trademarks of cypress semiconductor. all product and company names mentioned in this document may be the trademarks of their respective holders. 56-lead shrunk small outline package o56 51-85062-*c 51-85060-*b 56-lead thin shrunk small outline package, type ii (6 mm x 14 mm) z56
cy28347 document #: 38-07352 rev. *c page 22 of 22 document title: cy28347 universal single-chip clock solution for via p4m266/km266 ddr systems document number: 38-07352 rev. ecn no. issue date orig. of change description of change ** 112259 03/29/02 dmg new data sheet *a 120421 10/23/02 rgl changed the package drawing and dimension per cypress standards. *b 121771 12/06/02 rgl corrected the sentence in the spread spectrum clock generation area from byte1,bit7 to byte1, bit6 corrected the text in the description column of table 6 bit 20:27 from byte count ? 8 bits to data byte from master ? 8 bits *c 122902 12/26/02 rbi update power requirements to maximum ratings information.

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