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vdp 31xxb video processor family edition sept. 25, 1998 6251-437-2pd preliminar y d a t a sheet micr onas m i c r o n a s
preliminary data sheet vdp 31xxb 2 micronas contents page section title 5 1. introduction 6 1.1. vdp applications 7 2. functional description 7 2.1. analog front-end 7 2.1.1. input selector 7 2.1.2. clamping 7 2.1.3. automatic gain control 7 2.1.4. analog-to-digital converters 7 2.1.5. adc range 7 2.1.6. digitally controlled clock oscillator 7 2.1.7. analog video output 9 2.2. adaptive comb filter 10 2.3. color decoder 10 2.3.1. if-compensation 11 2.3.2. demodulator 11 2.3.3. chrominance filter 11 2.3.4. frequency demodulator 11 2.3.5. burst detection 11 2.3.6. color killer operation 11 2.3.7. pal compensation /1-h comb filter 12 2.3.8. luminance notch filter 12 2.3.9. skew filtering 13 2.4. horizontal scaler 13 2.5. black-line detector 13 2.6. test pattern generator 14 2.7. video sync processing 15 2.8. display part 15 2.8.1. luma contrast adjustment 15 2.8.2. black level expander 16 2.8.3. dynamic peaking 17 2.8.4. digital brightness adjustment 17 2.8.5. soft limiter 17 2.8.6. chroma input 17 2.8.7. chroma interpolation 18 2.8.8. chroma transient improvement 18 2.8.9. inverse matrix 18 2.8.10. rgb processing 18 2.8.11. osd color lookup table 19 2.8.12. picture frame generator 19 2.8.13. priority codec 19 2.8.14. scan velocity modulation 19 2.8.15. display phase shifter
preliminary data sheet vdp 31xxb 3 micronas contents, continued page section title 21 2.9. analog back end 21 2.9.1. crt measurement and control 22 2.9.2. scart output signal 23 2.9.3. average beam current limiter 23 2.9.4. analog rgb insertion 24 2.9.5. fast blank monitor 24 2.9.6. half contrast control 24 2.10. io port expander 26 2.11. synchronization and deflection 26 2.11.1. deflection processing 26 2.11.2. horizontal phase adjustment 28 2.11.3. vertical and east/west deflection 28 2.11.4. protection circuitry 29 2.12. reset function 29 2.13. standby and power-on 30 3. serial interface 30 3.1. i 2 c-bus interface 30 3.2. control and status registers 43 3.2.1. scaler adjustment 46 3.2.2. calculation of vertical and east-west deflection coefficients 47 4. specifications 47 4.1. outline dimensions 47 4.2. pin connections and short descriptions 49 4.3. pin descriptions 51 4.4. pin configuration 52 4.5. pin circuits 54 4.6. electrical characteristics 54 4.6.1. absolute maximum ratings 54 4.6.2. recommended operating conditions 54 4.6.3. recommended crystal characteristics 55 4.6.4. characteristics 56 4.6.4.1. 5 mhz clock output 56 4.6.4.2. 20 mhz clock input/output, external clock input (xtal1) 56 4.6.4.3. reset input, test input 57 4.6.4.4. i 2 c-bus interface 57 4.6.4.5. io port expander 57 4.6.4.6. analog video inputs 58 4.6.4.7. analog front-end and adcs 59 4.6.4.8. picture bus input 60 4.6.4.9. intlc, front sync output 60 4.6.4.10. main sync output 60 4.6.4.11. combined sync output
vdp 31xxb preliminary data sheet 4 micronas contents, continued page section title 61 4.6.4.12. horizontal flyback input 61 4.6.4.13. horizontal drive output 61 4.6.4.14. vertical protection input 61 4.6.4.15. vertical safety input 62 4.6.4.16. vertical and east/west drive output 62 4.6.4.17. sense a/d converter input 62 4.6.4.18. analog rgb and fb inputs 63 4.6.4.19. half contrast switch input 64 4.6.4.20. analog rgb outputs, d/a converters 66 4.6.4.21. dac reference, beam current safety 66 4.6.4.22. scan velocity modulation output 67 5. application circuit 72 6. data sheet history
preliminary data sheet vdp 31xxb 5 micronas video, display, and deflection processor release notes: this data sheet describes functions and characteristics of the vdp 31xxb?c2. revision bars indicate significant changes to the previous edition. 1. introduction the vdp 31xxb is a video ic family of high-quality single-chip video processors. modular design and a submicron technology allow the economic integration of features in all classes of tv sets. the vdp 31xxb family is based on functional blocks contained in the two chips: vpc 3200a video processor and ddp 3300a display and deflection processor. each member of the family contains the entire video, display, and deflection processing for 4:3 and 16:9 50/60 tv sets. its performance and flexibility allow the user to standardize his product development. hardware and software applications can profit from the modularity, as well as manufacturing, systems support, or mainte- nance. an overview of the vdp 31xxb video processor family is shown in fig. 1?1. 2h adapt. comb scan vel. mod. vdp 31xxb 1h combfilter vdp 3104b vdp 3108b vdp 3112b vdp 3116b vdp 3120b horizontal scaler color trans. impr. rgb insertion tube control prog. rgb matrix family fig. 1?1: vdp 31xxb family overview vin2 vin3 rgb out 20.25 mhz color decoder horizontal scaler sync & deflection clock gen. dco ntsc, pal, secam agc, 2*8bit adc vin1 vin4 analog frontend display processor i 2 c vout i 2 c fig. 1?2: block diagram of the vdp 3120b analog backend rgb matrix, clut, scan veloc. 3*10bit dac, tube control, rgb switch measurement adc h/v/ew rgb/fb in1 svm sense 2h adaptive combfilter rgb/fb in2 panorama mode color bus xref half contrast vrt cin
vdp 31xxb preliminary data sheet 6 micronas 1.1. vdp applications as a member of the vdp 31xxb family, the vdp 3120b offers all video features necessary to design a state-of- the-art tv set: video decoding ? 4 composite inputs, 1 s-vhs input ? composite video & sync output ? integrated high-quality a/d converters ? adaptive 2h comb filter y/c separator ? 1h ntsc comb filter ? multistandard color decoder (1 crystal) ? multistandard sync decoder ? black line detector video processing ? horizontal scaling (0.25 to 4) ? panorama vision ? black level expander ? dynamic peaking ? soft limiter (gamma correction) ? color transient improvement rgb processing ? programmable rgb matrix ? digital color bus interface ? additional analog rgb / fast blank input ? half-contrast switch ? picture frame generator deflection ? scan velocity modulation output ? high-performance h/v deflection ? separate adc for tube measurements ? eht compensation miscellaneous ? one 20.25 mhz crystal, few external components ? embedded risc controller (80 mips) ? i 2 c-bus interface ? single 5 v power supply ? submicron cmos technology ? 64-pin psdip package fig. 1 ? 3: full-feature tv set with vdp 3120b rgb vdp 3120b video 2 h/vdefl. rgb 1 tpu 3040 msp 3410 3 x stereo dram ccu 300x video 1 audio dpl 3420 dolby surround rgb 2
preliminary data sheet vdp 31xxb 7 micronas 2. functional description 2.1. analog front-end this block provides the analog interfaces to all video in- puts and mainly carries out analog-to digital conversion for the following digital video processing. a block dia- gram is given in fig. 2 ? 1. most of the functional blocks in the front-end are digitally controlled (clamping, agc, and clock-dco). the con- trol loops are closed by the fast processor ( ? fp ? ) em- bedded in the decoder. 2.1.1. input selector up to five analog inputs can be connected. four inputs are for input of composite video or s-vhs luma signal. these inputs are clamped to the sync back porch and are amplified by a variable gain amplifier. one input is for connection of s-vhs carrier-chrominance signal. this input is internally biased and has a fixed gain ampli- fier. 2.1.2. clamping the composite video input signals are ac coupled to the ic. the clamping voltage is stored on the coupling ca- pacitors and is generated by digitally controlled current sources. the clamping level is the back porch of the vid- eo signal. s-vhs chroma is also ac coupled. the input pin is internally biased to the center of the adc input range. 2.1.3. automatic gain control a digitally working automatic gain control adjusts the magnitude of the selected baseband by +6/ ? 4.5 db in 64 logarithmic steps to the optimal range of the adc. the gain of the video input stage including the adc is 213 steps/v with the agc set to 0 db. 2.1.4. analog-to-digital converters two adcs are provided to digitize the input signals. each converter runs with 20.25 mhz and has 8 bit reso- lution. an integrated bandgap circuit generates the re- quired reference voltages for the converters. 2.1.5. adc range the adc input range for the various input signals and the digital representation is given in table 2 ? 1 and fig. 2 ? 2. the corresponding output signal levels of the vdp 31xxb are also shown. 2.1.6. digitally controlled clock oscillator the clock generation is also a part of the analog front end. the crystal oscillator is controlled digitally by the control processor; the clock frequency can be adjusted within 150 ppm. 2.1.7. analog video output the input signal of the luma adc is available at the ana- log video output pin. the signal at this pin must be buff- ered by a source follower. the output voltage is 2 v, thus the signal can be used to drive a 75 line. the magni- tude is adjusted with an agc in 8 steps together with the main agc. dvco 150 ppm input mux clamp bias frequency 20.25 mhz gain adc agc reference generation adc vin3 +6/ ? 4.5 db fig. 2 ? 1: analog front-end vin2 vin1 cin digital chroma digital cvbs or luma system clocks cvbs/y cvbs/y cvbs/y/c chroma analog video output 3 vin4 cvbs/y
vdp 31xxb preliminary data sheet 8 micronas table 2 ? 1: adc input range for pal input signal and corresponding signal ranges signal input level [mv pp ] adc range yc r c b internal range ? 6 db 0 db + 4.5 db [steps] [steps] cvbs 100% cvbs 667 1333 2238 252 ? 75% cvbs 500 1000 1679 213 ? video (luma) 350 700 1175 149 224 sync height 150 300 504 64 ? clamp level 68 16 chroma burst 300 64 ? 100% chroma 890 190 128 112 75% chroma 670 143 128 84 bias level 128 128 255 192 128 0 black white 217 video = 100 ire sync = 41 ire 68 32 192 128 228 80 32 upper headroom = 38 steps = 1.4 db = 25 ire lower headroom = 4 steps = 0.2 db headroom = 56 steps = 2.1 db = clamp level cvbs/y chroma 75% chroma 100% chroma burst fig. 2 ? 2: adc ranges for cvbs/luma and chroma, pal input signal
preliminary data sheet vdp 31xxb 9 micronas 2.2. adaptive comb filter the adaptive comb filter is used for high-quality lumi- nance/chrominance separation for pal or ntsc sig- nals. the comb filter improves the luminance resolution (bandwidth) and reduces interferences like cross-lumi- nance and cross-color artifacts. the adaptive algorithm can eliminate most of the mentioned errors without introducing new artifacts or noise. a block diagram of the comb filter is shown in fig. 2 ? 3. the filter uses two line delays to process the information of three adjacent video lines. to have a fixed phase rela- tionship of the color subcarrier in the three channels, the system clock (20.25 mhz) is fractionally locked to the color subcarrier. this allows the processing of all color standards and substandards using a single crystal fre- quency. the cvbs signal in the three channels is filtered at the subcarrier frequency by a set of bandpass / notch filters. the output of the three channels is used by the adaption logic to select the weighting that is used to reconstruct the luminance/chrominance signal from the 4 bandpass/ notch filter signals. by using soft mixing of the 4 signals switching artifacts of the adaption algorithm are com- pletely suppressed. the comb filter uses the middle line as reference, there- fore, the comb filter delay is one line. if the comb filter is switched off, the delay lines are used to pass the luma/ chroma signals from the a/d converters to the luma/ chroma outputs. thus, the comb filter delay is always one line. various parameters of the comb filter are adjustable, hence giving to the user the ability to adjust his own de- sired picture quality. two parameters (ky, kc) set the global gain of luma and chroma comb separately; these values directly weigh the adaption algorithm output. in this way, it is possible to obtain a luma/chroma separation ranging from stan- dard notch/bandpass to full comb decoding. the parameter kb allows to choose between the two proposed comb booster modes. this so-called feature widely improves vertical high to low frequency transi- tions areas, the typical example being a multiburst to dc change. for kb=0, this improvement is kept moderate, whereas, in case of kb=1, it is maximum, but the risk to increase the ? hanging dots ? amount for some given color transitions is higher. using the default setting, the comb filter has separate luma and chroma decision algorithms; it is however pos- sible to switch the chroma comb factor to the current luma adaption output by setting cc to 1. another interesting feature is the programmable limita- tion of the luma comb amount; proper limitation, associated to adequate luma peaking, gives rise to an enhanced 2-d resolution homogeneity. this limitation is set by the parameter clim, ranging from 0 (no limitation) to 31 (max. limitation). the daa parameter (1:off , 0:on) is used to disable/en- able a very efficient built-in ? rain effect ? suppressor; many comb filters show this side effect which gives some vertical correlation to a 2-d uniform random area, due to the vertical filtering. this unnatural-looking phe- nomenon is mostly visible on tuner images, since they are always corrupted by some noise; and this looks like rain. 1 h line delay 1 h line delay cvbs input chroma input bandpass filter bandpass filter bandpass/ notch filter luma / chroma mixers adaption logic luma output chroma output fig. 2 ? 3: block diagram of the adaptive comb filter
vdp 31xxb preliminary data sheet 10 micronas 2.3. color decoder in this block, the standard luma/chroma separation and multi-standard color demodulation is carried out. the color demodulation uses an asynchronous clock, thus allowing a unified architecture for all color standards. a block diagram of the color decoder is shown in fig. 2 ? 5. the luma as well as the chroma processing, is shown here. the color decoder provides also some spe- cial modes, e.g. wide band chroma format which is in- tended for s-vhs wide bandwidth chroma. if the adaptive comb filter is used for luma chroma sepa- ration, the color decoder uses the s-vhs mode proces- sing. the output of the color decoder is yc r c b in a 4:2:2 format. 2.3.1. if-compensation with off-air or mistuned reception, any attenuation at higher frequencies or asymmetry around the color sub- carrier is compensated. four different settings of the if- compensation are possible: ? flat (no compensation) ? 6 db /octave ? 12 db /octave ? 10 db/mhz the last setting gives a very large boost to high frequen- cies. it is provided for secam signals that are decoded using a saw filter specified originally for the pal stan- dard. fig. 2 ? 4: frequency response of chroma if-compensation chroma if compensation dc-reject mixer lowpass filter phase/freq acc color-pll / color-acc 1 h delay mux mux cross-switch notch filter demodulator luma / cvbs luma fig. 2 ? 5: color decoder chroma / c r c b
preliminary data sheet vdp 31xxb 11 micronas 2.3.2. demodulator the entire signal (which might still contain luma) is now quadrature-mixed to the baseband. the mixing frequen- cy is equal to the subcarrier for pal and ntsc, thus achieving the chroma demodulation. for secam, the mixing frequency is 4.286 mhz giving the quadrature baseband components of the fm modulated chroma. after the mixer, a lowpass filter selects the chroma com- ponents; a downsampling stage converts the color dif- ference signals to a multiplexed half rate data stream. the subcarrier frequency in the demodulator is gener- ated by direct digital synthesis; therefore, substandards such as pal 3.58 or ntsc 4.43 can also be demodu- lated. 2.3.3. chrominance filter the demodulation is followed by a lowpass filter for the color difference signals for pal/ntsc. secam requires a modified lowpass function with bell-filter characteristic. at the output of the lowpass filter, all luma information is eliminated. the lowpass filters are calculated in time multiplex for the two color signals. three bandwidth settings (narrow, normal, broad) are available for each standard. for pal/ ntsc, a wide band chroma filter can be selected. this filter is intended for high bandwidth chroma signals, e.g. a nonstandard wide bandwidth s-vhs signal. fig. 2 ? 6: frequency response of chroma filters pal/ntsc secam 2.3.4. frequency demodulator the frequency demodulator for demodulating the se- cam signal is implemented as a cordic-structure. it calculates the phase and magnitude of the quadrature components by coordinate rotation. the phase output of the cordic processor is differen- tiated to obtain the demodulated frequency. after the deemphasis filter, the dr and db signals are scaled to standard c r c b amplitudes and fed to the crossover- switch. 2.3.5. burst detection in the pal/ntsc-system the burst is the reference for the color signal. the phase and magnitude outputs of the cordic are gated with the color key and used for controlling the phase-lock-loop (apc) of the demodula- tor and the automatic color control (acc) in pal/ntsc. the acc has a control range of +30 ... ? 6 db. for secam decoding, the frequency of the burst is mea- sured. thus, the current chroma carrier frequency can be identified and is used to control the secam proces- sing. the burst measurements also control the color kill- er operation; they can be used for automatic standard detection as well. 2.3.6. color killer operation the color killer uses the burst-phase / burst-frequency measurement to identify a pal/ntsc or secam color signal. for pal/ntsc, the color is switched off (killed) as long as the color subcarrier pll is not locked. for se- cam, the killer is controlled by the toggle of the burst fre- quency. the burst amplitude measurement is used to switch-off the color if the burst amplitude is below a pro- grammable threshold. thus, color will be killed for very noisy signals. the color amplitude killer has a program- mable hysteresis. 2.3.7. pal compensation / 1-h comb filter the color decoder uses one fully integrated delay line. only active video is stored. the delay line application depends on the color stan- dard: ? ntsc: 1-h comb filter or color compensation ? pal: color compensation ? secam: crossover-switch in the ntsc compensated mode, fig. 2 ? 7 c), the color signal is averaged for two adjacent lines. thus, cross- color distortion and chroma noise is reduced. in the ntsc combfilter mode, fig. 2 ? 7 d), the delay line is in the composite signal path, thus allowing reduction of
vdp 31xxb preliminary data sheet 12 micronas cross-color components, as well as cross-luminance. the loss of vertical resolution in the luminance channel is compensated by adding the vertical detail signal with removed color information. chroma notch filter 8 chroma process. cvbs y 1 h delay 8 cvbs chroma process. notch filter y 8 chroma process. luma y 8 a) conventional b) s-vhs d) comb filter fig. 2 ? 7: ntsc color decoding options c c r b c c r b c c r b notch filter 1 h delay 8 chroma process. cvbs y c) compensated c c r b chroma notch filter 1 h delay 8 chroma process. cvbs y 8 chroma process. luma y 8 1 h delay a) conventional b) s-vhs fig. 2 ? 8: pal color decoding options c c r b c c r b mux notch filter 1 h delay 8 chroma process. cvbs y fig. 2 ? 9: secam color decoding c c r b 2.3.8. luminance notch filter if a composite video signal is applied, the color informa- tion is suppressed by a programmable notch filter. the position of the filter center frequency depends on the subcarrier frequency for pal/ntsc. for secam, the notch is directly controlled by the chroma carrier fre- quency. this considerably reduces the cross-lumi- nance. the frequency responses for all three systems are shown in fig. 2 ? 10. pal/ntsc notch filter db mhz 10 02 4 68 10 0 ? 10 ? 20 ? 30 ? 40 db mhz 10 02 4 68 10 0 ? 10 ? 20 ? 30 ? 40 fig. 2 ? 10: frequency responses of the luma notch filter for pal, ntsc, and secam secam notch filter 2.3.9. skew filtering the system clock is free-running and not locked to the tv line frequency. therefore, the adc sampling pattern is not orthogonal. the decoded yc r c b signals are con- verted to an orthogonal sampling raster by the skew fil- ters, which are part of the scaler block. the skew filters allow the application of a group delay to the input signals without introducing waveform or fre- quency response distortion. the amount of phase shift of this filter is controlled by the horizontal pll1. the accuracy of the filters is 1/32 clocks for luminance and 1/4 clocks for chroma. thus the 4:2:2 yc r c b data is in an orthogonal pixel format even in the case of nonstandard input signals such as vcr.
preliminary data sheet vdp 31xxb 13 micronas 2.4. horizontal scaler the 4:2:2 ycrcb signal from the color decoder is pro- cessed by the horizontal scaler. the scaler block allows a linear or nonlinear horizontal scaling of the input video signal in the range of 0.25 to 4. nonlinear scaling, also called ? panorama vision ? , provides a geometrical distor- tion of the input picture. it is used to fit a picture with 4:3 format on a 16:9 screen by stretching the picture geome- try at the borders. also, the inverse effect can be pro- duced by the scaler. a summary of scaler modes is given in table 2 ? 2. the scaler contains a programmable decimation filter, a 1-line fifo memory, and a programmable interpolation filter. the scaler input filter is also used for pixel skew correction, see 2.3.9. the decimator/interpolator struc- ture allows optimal use of the fifo memory. the con- trolling of the scaler is done by the internal fast proces- sor. table 2 ? 2: scaler modes mode scale factor description compression 4:3 16:9 0.75 linear 4:3 source displayed on a 16:9 tube, with side panels panorama 4:3 16:9 non- linear compr 4:3 source displayed on a 16:9 tube, borders distorted zoom 4:3 4:3 1.33 linear letterbox source (pal+) displayed on a 4:3 tube, vertical overscan with cropping of side panels panorama 4:3 4:3 non- linear zoom letterbox source (pal+) displayed on a 4:3 tube, vertical overscan, bor- ders distorted, no crop- ping 2.5. black-line detector in case of a letterbox format input video, e.g. cinema- scope, pal+ etc., black areas at the upper and lower part of the picture are visible. it is suitable to remove or reduce these areas by a vertical zoom and/or shift op- eration. the vdp 31xxb supports this feature by a letterbox de- tector. the circuitry detects black video lines by measur- ing the signal amplitude during active video. for every field the number of black lines at the upper and lower part of the picture are measured, compared to the pre- vious measurement and the minima are stored in the i 2 c-register blklin. to adjust the picture amplitude, the external controller reads this register, calculates the ver- tical scaling coefficient and transfers the new settings, e.g. vertical sawtooth parameters, horizontal scaling co- efficient etc., to the vdp. letterbox signals containing logos on the left or right side of the black areas are processed as black lines, while subtitles, inserted in the black areas, are pro- cessed as non-black lines. therefore the subtitles are visible on the screen. to suppress the subtitles, the verti- cal zoom coefficient is calculated by selecting the larger number of black lines only. dark video scenes with a low contrast level compared to the letterbox area are indi- cated by the blkpic bit. 2.6. test pattern generator the ycrcb outputs of the front-end can be switched to a test mode where ycrcb data are generated digitally in the vdp 31xxb. test patterns include luma/chroma ramps, flat fields and a pseudo color bar pattern.
vdp 31xxb preliminary data sheet 14 micronas 2.7. video sync processing fig. 2 ? 11 shows a block diagram of the front-end sync processing. to extract the sync information from the video signal, a linear phase lowpass filter eliminates all noise and video contents above 1 mhz. the sync is sep- arated by a slicer; the sync phase is measured. a vari- able window can be selected to improve the noise immu- nity of the slicer. the phase comparator measures the falling edge of sync, as well as the integrated sync pulse. the sync phase error is filtered by a phase-locked loop that is computed by the fp. all timing in the front-end is derived from a counter that is part of this pll, and it thus counts synchronously to the video signal. a separate hardware block measures the signal back porch and also allows gathering the maximum/minimum of the video signal. this information is processed by the fp and used for gain control and clamping. for vertical sync separation, the sliced video signal is in- tegrated. the fp uses the integrator value to derive ver- tical sync and field information. the information extracted by the video sync processing is multiplexed onto the hardware front sync signal (fsy) and is distributed to the rest of the video processing sys- tem. the format of the front sync signal is given in fig. 2 ? 12. the data for the vertical deflection, the sawtooth, and the east-west correction signal is calculated by the vdp 31xxb. the data is buffered in a fifo and trans- ferred to the back-end by a single wire interface. frequency and phase characteristics of the analog vid- eo signal are derived from pll1. the results are fed to the scaler unit for data interpolation and orthogonaliza- tion and to the clock synthesizer for line-locked clock generation. horizontal and vertical syncs are latched with the line-locked clock. phase comparator & lowpass counter front-end timing front sync lowpass 1 mhz & syncslicer horizontal sync separation vertical sync separation fifo sawtooth video input skew front sync generator vertical serial data vertical sawtooth e/w parabola calculation clamping, colorkey, fifo_write pll1 clamp & signal meas. fig. 2 ? 11: sync separation block diagram vblank field clock synthesizer syncs clock h/v syncs f1 (not in scale) input analog video fsy f1 parity v: vertical sync 0 = off 1 = on f: field # 0 = field 1 1 = field 2 fig. 2 ? 12: front sync format f0 skew skew lsb not used fv f0 reserved msb
preliminary data sheet vdp 31xxb 15 micronas 2.8. display part in the display part the conversion from digital yc r c b to analog rgb is carried out. a block diagram is shown in figure 2 ? 20. in the luminance processing path, contrast and brightness adjustments and a variety of features, such as black level expansion, dynamic peaking and soft limiting, are provided. in the chrominance path, the c r c b signals are converted to 20.25 mhz sampling rate and filtered by a color transient improvement circuit. the yc r c b signals are converted by a programmable matrix to rgb color space. the display processor provides separate control set- tings for two pictures, i.e. different coefficients for a ? main ? and a ? side ? picture. the digital osd insertion circuit allows the insertion of a 5-bit osd signal. the color space for this signal is con- trolled by a partially programmable color look-up table (clut) and contrast adjustment. the osd signals and the display clock are synchronized to the horizontal flyback. for the display clock, a gate delay phase shifter is used. in the analog backend, three 10-bit digital-to-analog converters provide the analog output signals. 2.8.1. luma contrast adjustment the contrast of the luminance signal can be adjusted by multiplication with a 6-bit contrast value. the contrast value corresponds to a gain factor from 0 to 2, where the value 32 is equivalent to a gain of 1. the contrast can be adjusted separately for main picture and side picture. l in l out l min l max l t l tr fig. 2 ? 13: characteristics of the black level expander l tr bam bthr btlt 2.8.2. black level expander the black level expander enhances the contrast of the picture. therefore the luminance signal is modified with an adjustable, non-linear function. dark areas of the pic- ture are changed to black, while bright areas remain un- changed. the advantage of this black level expander is that the black expansion is performed only if it will be most noticeable to the viewer. the black level expander works adaptively. depending on the measured amplitudes ? l min ? and ? l max ? of the low- pass-filtered luminance and an adjustable coefficient btlt, a tilt point ? l t ? is established by l t = l min + btlt (l max ? l min ). above this value there is no expansion, while all lumi- nance values below this point are expanded according to: l out = l in + bam (l in ? l t ) a second threshold, l tr , can be programmed, above which there is no expansion. the characteristics of the black level expander are shown in fig. 2 ? 13 and fig. 2 ? 14. the tilt point l t is a function of the dynamic range of the video signal. thus, the black level expansion is only per- formed when the video signal has a large dynamic range. otherwise, the expansion to black is zero. this al- lows the correction of the characteristics of the picture tube. a) l min l max l t l t b) fig. 2 ? 14: black-level-expansion a) luminance input b) luminance input and output
preliminary data sheet vdp 31xxb 16 micronas 2.8.3. dynamic peaking especially with decoded composite signals and notch fil- ter luminance separation, as input signals, it is neces- sary to improve the luminance frequency characteris- tics. with transparent, high-bandwidth signals, it is sometimes desirable to soften the image. in the vdp 31xxb, the luma response is improved by ? dy- namic ? peaking. the algorithm has been optimized re- garding step and frequency response. it adapts to the amplitude of the high frequency part. small ac ampli- tudes are processed, while large ac amplitudes stay nearly unmodified. the dynamic range can be adjusted from 14 to 14 db for small high frequency signals. there is sepa- rate adjustment for signal overshoot and for signal un- dershoot. for large signals, the dynamic range is limited by a non-linear function that does not create any visible alias components. the peaking can be switched over to ? softening ? by inverting the peaking term by software. the center frequency of the peaking filter is switchable from 2.5 mhz to 3.2 mhz. for s-vhs and for notch filter color decoding, the total system frequency responses for both pal and ntsc are shown in figure 2 ? 16. transients, produced by the dynamic peaking when switching video source signals, can be suppressed via the priority bus. fig. 2 ? 15: dynamic peaking frequency response db mhz 20 5 ? 5 ? 10 ? 15 ? 20 02 4 68 10 15 10 0 db mhz 20 5 ? 5 ? 10 ? 15 ? 20 02 4 68 10 15 10 0 db mhz 20 5 ? 5 ? 10 ? 15 ? 20 02 4 68 10 15 10 0 cf= 3.2 mhz cf= 2.5 mhz s-vhs db mhz 20 5 ? 5 ? 10 ? 15 ? 20 02 4 68 10 15 10 0 db mhz 20 5 ? 5 ? 10 ? 15 ? 20 02 4 68 10 15 10 0 cf= 3.2 mhz cf= 2.5 mhz pal/secam db mhz 20 5 ? 5 ? 10 ? 15 ? 20 02 4 68 10 15 10 0 db mhz 20 5 ? 5 ? 10 ? 15 ? 20 02 4 68 10 15 10 0 cf= 2.5 mhz cf= 3.2 mhz fig. 2 ? 16: total frequency response for peaking filter and s-vhs, pal, ntsc ntsc
preliminary data sheet vdp 31xxb 17 micronas 2.8.4. digital brightness adjustment the dc-level of the luminance signal can be adjusted by adding an 8-bit number in the luminance signal path in front of the softlimiter. with a contrast adjustment of 32 (gain 1) the signal can be shifted by 100%. after the brightness addition, the negative going signals are limited to zero. it is desirable to keep a small positive offset with the signal to prevent undershoots produced by the peaking from being cut. the digital brightness adjustment is separate for main and side picture. 2.8.5. soft limiter the dynamic range of the processed luma signal must be limited to prevent the crt from overload. an appro- priate headroom for contrast, peaking and brightness can be adjusted by the tv manufacturer according to the crt characteristics. all signals above this limit will be ? soft ? -clipped. a characteristic diagram of the soft limiter is shown in fig. 2 ? 17. the total limiter consists of three parts: part 1 includes adjustable tilt point and gain. the gain before the tilt value is 1. above the tilt value, a part (0...15/16) of the input signal is subtracted from the input signal itself. therefore, the gain is adjustable from 16/16 to 1/16, when the slope value varies from 0 to 15. the tilt value can be adjusted from 0 to 511. part 2 has the same characteristics as part 1. the sub- tracting part is also relative to the input signal, so the total differential gain will become negative if the sum of slope 1 and slope 2 is greater than 16 and the input sig- nal is above the both tilt values (see characteristics). finally, the output signal of the soft limiter will be clipped by a hard limiter adjustable from 256 to 511. 2.8.6. chroma input the chroma input signal is a multiplexed c r and c b sig- nal in 8-bit binary offset code. it can be switched be- tween normal and inverted signal and between two ? s complement and binary offset code. the delay in re- spect to the luminance input can be adjusted in 5 steps within a range of 2 clock periods. 2.8.7. chroma interpolation a linear phase interpolator is used to convert the chroma sampling rate from 10.125 mhz (4:2:2) to 20.25 mhz (4:4:4). all further processing is carried out at the full sampling rate. fig. 2 ? 17: characteristic of soft limiter a and b and hard limiter output limiter input 0 2 4 6 8 12 10 0 2 4 6 8 10 12 14 14 slope 1 [0...15] slope 2 [0...15] part 1 part 2 hard limiter tilt 1 [ 0...511] tilt 2 [0...511] range= 256...511 0 511 0 1023 calculation example for the softlimiter input amplitude. (the real signal processing in the limiter is 2 bit more than described here) y input 16...235 (itur) contrast 63 dig. brightness 20 ble off peaking off limiter input signal: (yin-black level) contr./32 + brightn. (235 ? 16) 63/32 + 20 = 451 black level 16 (constant) 100 200 300 400 500 600 700 800 900 100 200 300 400
preliminary data sheet vdp 31xxb 18 micronas 2.8.8. chroma transient improvement the intention of this block is to enhance the chroma resolution. a correction signal is calculated by differenti- ation of the color difference signals. the differentiation can be selected according to the signal bandwidth, e.g. for pal/ntsc/secam or digital component signals, respectively. the amplitude of the correction signal is adjustable. small noise amplitudes in the correction sig- nal are suppressed by an adjustable coring circuit. to eliminate ? wrong colors ? , which are caused by over and undershoots at the chroma transition, the sharpened chroma signals are limited to a proper value automati- cally. fig. 2 ? 18: digital color transient improvement t t t cr out cb out ampl. cr in cb in a) b) c) a) cr cb input of dti b) cr cb input correction signal c) sharpened and limited cr cb 2.8.9. inverse matrix a 6-multiplier matrix transcodes the cr and cb signals to r ? y, b ? y, and g ? y. the multipliers are also used to adjust color saturation in the range of 0 to 2. the coeffi- cients are signed and have a resolution of 9 bits. there are separate matrix coefficients for main and side pic- tures. the matrix computes: r ? y mr1*cb mr2*cr g ? y mg1*cb mg2*cr b ? y mb1*cb mb2*cr the initialization values for the matrix are computed from the standard itur (ccir) matrix: r g b 1 1 1 0 0.345 1.773 1.402 0.713 0 y cb cr for a contrast setting of ctm 32, the matrix values are scaled by a factor of 64, see also table 3 ? 1. 2.8.10. rgb processing after adding the post-processed luma, the digital rgb signals are limited to 10 bits. three multipliers are used to digitally adjust the white drive. using the same multi- pliers an average beam current limiter is implemented. see also section 2.9.1. ? crt measurement and con- trol ? . 2.8.11. osd color lookup table the vdp 31xxb has five input lines for an osd signal. this signal forms a 5-bit address for a color look-up table (clut). the clut is a memory with 32 words where each word holds a rgb value. bits 0 to 3 (bit 4 0) form the addresses for the rom part of the osd, which generates full rgb signals (bit 0 to 2) and half-contrast rgb signals (bit 3). bit 4 addresses the ram part of the osd with 16 freely programmable colors, addressable with bit 0 to 3. the programming is done via the i 2 c-bus. the amplitude of the clut output signals can be ad- justed separately for r, g and b via the i 2 c-bus. the switchover between video rgb and osd rgb is done via the priority bus.
preliminary data sheet vdp 31xxb 19 micronas 2.8.12. picture frame generator when the picture does not fill the total screen (height or width too small) it is surrounded with black areas. these areas (and more) can be colored with the picture frame generator. this is done by switching over the rgb signal from the matrix to the signal from the osd color look-up table. the width of each area (left, right, upper, lower) can be adjusted separately. the generator starts on the right, respectively lower side of the screen and stops on the left, respectively upper side of the screen. this means, it runs during horizontal, respectively vertical flyback. the color of the complete border can be stored in the programmable osd color look-up table in a separate address. the format is 3 4 bit rgb. the contrast can be adjusted separately. the picture frame generator includes a priority master circuit. its priority is programmable and the border is generated only if the priority is higher than the priority at the prio bus. therefore the border can be underlay or overlay depending on the picture source. 2.8.13. priority codec the priority decoder has three input lines for up to eight priorities. the highest priority is all three lines at low lev- el. a 5-bit information is attached to each priority (see table 3 ? 1 ? priority bus ? ). these bits are programmable via the i 2 c-bus and have the following meanings: ? one of two contrast, brightness and matrix values for main and side picture ? rgb from video signal or color look-up table ? disable/enable black level expander ? disable/enable peaking transient suppression when signal is switched ? disable/enable analog fast blank input 1 ? disable/enable analog fast blank input 2 2.8.14. scan velocity modulation the rgb input signal of the svm is converted to y in a simple matrix. then the y signal is differentiated by a fil- ter of the transfer function 1 ? z ? n , where n is program- mable from 1 to 6. with a coring, some noise can be sup- pressed. this is followed by a gain adjustment and an adjustable limiter. the analog output signal is generated by an 8-bit d/a converter. the signal delay can be adjusted by 3.5 clocks in half- clock steps. for the gain and filter adjustment there are two parameter sets. the switching between these two sets is done with the same rgb switch signal that is used for switching between video-rgb and osd-rgb for the rgb outputs. (see fig. 2 ? 19). 2.8.15. display phase shifter a phase shifter is used to partially compensate the phase differences between the video source and the fly- back signal. by using the described clock system, this phase shifter works with an accuracy of approximately 1 ns. it has a range of 1 clock period which is equivalent to 24.7 ns at 20.25 mhz. the large amount of phase shift (full clock periods) is realized in the front-end circuit. fig. 2 ? 19: svm block diagram g rb matrix and shaping modulation notch differen- tiator 1 ? z ? nx n1 n2 coring adjustment gain adjustment limiter delay adjustment d/a converter coring gain1 gain2 limit delay rgb switch output
preliminary data sheet vdp 31xxb 20 micronas contrast dynamic peaking brightness + offset softlimiter whitedrive measurement clock horizontal flyback dti (cr) dti (cb) interpol 4:4:4 black level expander 10 dig. rout dig. gout dig. bout cr cb dig. y in dig. crcb in 8 8 matrix saturation whitedrive r x beamcurr. lim. display & clock control prio in prio decoder select coefficients main picture side picture 3 matrix r ? matrix g ? matrix b ? y r g b luma insert for crtmeasurement clut, for crtmeasurement blanking fig. 2 ? 20: digital back-end dig. osd in 5 contrast svmout 10 10 scan velocity modulation picture frame generator prio prio whitedrive g x beamcurr. lim. whitedrive b x beamcurr. lim. phase shift 0...1 clock phase shift 0...1 clock phase shift 0...1 clock
preliminary data sheet vdp 31xxb 21 micronas 2.9. analog back end the digital rgb signals are converted to analog rgbs using three video digital to analog converters (dac) with 10-bit resolution. an analog brightness value is provided by three additional dacs. the adjustment range is 40% of the full rgb range. controlling the whitedrive/analog brightness and also the external contrast and brightness adjustments is done via the fast processor, located in the front-end. control of the cutoff dacs is via i 2 c-bus registers. finally cutoff and blanking values are added to the rgb signals. cutoff (dark current) is provided by three 9-bit dacs. the adjustment range is 60% of full scale rgb range. the analog rgb-outputs are current outputs with cur- rent-sink characteristics. the maximum current drawn by the output stage is obtained with peak white rgb. an external half contrast signal can be used to reduce the output current of the rgb outputs to 50%. 2.9.1. crt measurement and control the display processor is equipped with an 8-bit pdm- adc for all measuring purposes. the adc is connected to the sense input pin, the input range is 0 to 1.5v. the bandwidth of the pdm filter can be selected; it is 40/80 khz for small/large bandwidth setting. the input impedance is more than 1 m ? . cutoff and white drive current measurement are carried out during the vertical blanking interval. they always use the small bandwidth setting. the current range for the cutoff measurement is set by connecting a sense resis- tor to the madc input. for the whitedrive measurement, the range is set by using another sense resistor and the range select switch 2 output pin (rsw2). during the ac- tive picture, the minimum and maximum beam current is measured. the measurement range can be set by us- ing the range select switch 1 pin (rsw1) as shown in fig. 2 ? 21 and fig. 2 ? 22. the timing window of this mea- surement is programmable. the intention is to automati- cally detect letterbox transmission or to measure the ac- tual beam current. all control loops are closed via the external control microprocessor. sense rsw1 rsw2 r2 r3 beam current a d madc r1 fig. 2 ? 21: madc range switches ultra black black cutoff white drive cr + ibrm cr + ibrm + wdrv wdr r g b tml cg + ibrm cb + ibrm picture meas. picture meas. tube measurement active measurement resistor r1 r2 r3 rsw1=on, rsw2=on r1 r1 r3 rsw2 r r cutoff cutoff g b r1 r2 r3 fig. 2 ? 22: madc measurement timing rsw1=on, rsw2=on pmst pmso =on lines
preliminary data sheet vdp 31xxb 22 micronas in each field two sets of measurements can be taken: a) the picture tube measurement returns results for ? cutoff r ? cutoff g ? cutoff b ? white drive r or g or b (sequentially) b) the picture measurement returns data on ? active picture maximum current ? active picture minimum current the tube measurement is automatically started when the cutoff blue result register is read. cutoff control for rgb requires one field only while a complete white-drive control requires three fields. if the measurement mode is set to ? offset check ? , a measurement cycle is run with the cutoff/whitedrive signals set to zero. this allows to compensate the madc offset as well as input the leakage currents. during cutoff and whitedrive measure- ments, the average beam current limiter function (ref. 2.9.3.) is switched off and a programmable value is used for the brightness setting. the start line of the tube mea- surement can be programmed via i 2 c-bus, the first line used for the measurement, i.e. measurement of cutoff red, is 2 lines after the programmed start line. the picture measurement must be enabled by the con- trol microprocessor after reading the min./max. result registers. if a ? 1 ? is written into bit 2 in subaddress 25, the measurement runs for one field. for the next measure- ment a ? 1 ? has to be written again. the measurement is always started at the beginning of active video. the vertical timing for the picture measurement is pro- grammable, and may even be a single line. also the sig- nal bandwidth is switchable for the picture measure- ment. two horizontal windows are available for the picture measurement. the large window is active for the entire active line. tube measurement is always carried out with the small window. measurement windows for picture and tube measurement are shown in figure 2 ? 23. active video field 1/ 2 small window for tube measurement (cutoff, white drive) large window for active picture picture meas. start tube measurement picture meas. end fig. 2 ? 23: windows for tube and picture measure- ments 2.9.2. scart output signal the rgb output of the vdp 31xxb can also be used to drive a scart output. in the case of the scart signal, the parameter clmpr (clamping reference) has to be set to 1. then, during blanking, the rgb outputs are au- tomatically set to 50% of the maximum brightness. the dc offset values can be adjusted with the cutoff parame- ters cr, cg, and cb. the amplitudes can be adjusted with the drive parameters wdr, wdg, and wdb.
preliminary data sheet vdp 31xxb 23 micronas 2.9.3. average beam current limiter the average beam current limiter (bcl) uses the sense input for the beam current measurement. the bcl uses a different filter to average the beam current during the active picture. the filter bandwidth is approx. 2 khz. the beam current limiter has an automatic offset adjustment that is active two lines before the first cutoff measure- ment line. the beam current limiter function is located in the front- end. the data exchange between the front-end and the back-end is done via a single-wire serial interface. the beam current limiter allows the setting of a threshold current. if the beam current is above the threshold, the excess current is low-pass filtered and used to attenuate the rgb outputs by adjusting the white-drive multipliers for the internal (digital) rgb signals, and the analog con- trast multipliers for the analog rgb inputs, respectively. the lower limit of the attenuator is programmable, thus a minimum contrast can always be set. during the tube measurement, the abl attenuation is switched off. after the white drive measurement line it takes 3 lines to switch back to bcl limited drives and brightness. typical characteristics of the abl for different loop gains are shown in fig. 2 ? 24; for this example the tube has been assumed to have square law characteristics. fig. 2 ? 24: beam current limiter characteristics: beam current output vs. drive bcl threshold: 1 beam current drive 2.9.4. analog rgb insertion the vdp 31xxb allows insertion of 2 external analog rgb signals. each rgb signal is key-clamped and in- serted into the main rgb by the fast blank switch. the selected external rgb input is virtually handled as a priority bus signal. thus, it can be overlaid or underlaid to the digital picture. the external rgb signals can be adjusted independently as regards dc-level (bright- ness) and magnitude (contrast). which analog rgb input is selected depends on the fast blank input signals and the programming of a number of i 2 c-bus register settings (see table 2 ? 3 and fig. 2 ? 25). both fast blank inputs must be either active-low or ac- tive-high. all signals for analog rgb insertion (rin1/2, gin1/2, bin1/2, fblin1/2, hcs) must be synchronized to the horizontal flyback, otherwise a horizontal jitter will be vis- ible. the vdp 31xxb has no means for timing correction of the analog rgb input signals. table 2 ? 3: rgb input selection fbfoh1 = 0, fbfoh2 = 0, fbfol1 = 0, fbfol2 = 0 fblin1 fblin2 fbpol fbprio rgb output 0 0 0 x video 0 1 0 x rgb input 2 1 0 0 x rgb input 1 1 1 0 0 rgb input 1 1 1 0 1 rgb input 2 0 0 1 0 rgb input 1 0 0 1 1 rgb input 2 0 1 1 x rgb input 1 1 0 1 x rgb input 2 1 1 1 x video
preliminary data sheet vdp 31xxb 24 micronas 2.9.5. fast blank monitor the presence of external analog rgb sources can be detected by means of a fast blank monitor. the status of the selected fast blank input can be monitored via an i 2 c bus register. there is a 2 bit information, giving static and dynamic indication of a fast blank signal. the static bit is directly reading the fast blank input line, whereas the dy- namic bit is reading the status of a flip-flop triggered by the negative edge of the fast blank signal. with this monitor logic it is possible to detect if there is an external rgb source active and if it is a full screen in- sertion or only a box. the monitor logic is connected di- rectly to the fblin1 or fblin2 pin. selection is done via i 2 c bus register. fblin1 fblin2 # fast blank monitor fbpol fbfoh1 fbprio fb int fast blank selection fbfoh2 fbmon fbfol1 fbfol2 fig. 2 ? 25: fast blank selection logic # 2.9.6. half contrast control insertion of transparent text pages or osd onto the vid- eo picture is often difficult to read, especially if the video contrast is high. the vdp 31xxb allows contrast reduc- tion of the video background by means of a half contrast input (hcs pin). this input can be supplied with a fast switching signal (similar to the fast blank input), typically defining a rectangular box in which the video picture is displayed with reduced contrast. the analog rgb inputs are still displayed with full contrast. the hcs input is multiplexed with the port0 input/out- put on the same pin, selection is done via i 2 c-bus regis- ter. if the hcs input is selected, then the port function of this pin is disabled and writing data into port0 will have no effect. if the hcs input is not selected, the i 2 c-bus register bits hcsfoh and hcspol must be used to disable the half contrast function. hcs hcsen hcsfoh fig. 2 ? 26: half contrast switch logic # hcs intern hcspol 2.10. io port expander the vdp 31xxb provides a general purpose io port to control and monitor up to seven external signals. the port direction is programmable for each bit individually. via i 2 c bus register it is possible to write or read each port pin. because of the relatively low i 2 c bus speed, only slow or static signals can be handled. the port signals are multiplexed with other signals to minimize pin count. port0 is multiplexed with the hcs input signal, port1 is multiplexed with the fsy output signal, port[6:2] are multiplexed with the color bus in- put color[4:0]. the pin configuration is programmable via i 2 c bus register. all register bits can be read back, the default configuration after reset is input on port[1:0] and color[4:0] enabled.
preliminary data sheet vdp 31xxb 25 micronas ext. contrast * cutoff r 10 bit dac video 3.75ma blank & timing 8 bit adc measurm. 9 bit u/i ? dac 3.75ma clamp key analog r in sense analog r out analog g out analog b out analog g in analog b in measurement buffer digital r in h v measurem. 10 9 bit dac 1.5 ma digital g in digital b in 9 bit dac 2.2 ma 10 bit dac video 3.75ma 10 bit dac video 3.75ma 9 bit u/i ? dac 3.75ma 9 bit u/i ? dac 3.75ma cutoff g 9 bit dac 2.2 ma cutoff b 9 bit dac 2.2 ma 9 bit dac 1.5 ma 9 bit dac 1.5 ma input ext. brightness * i/o fig. 2 ? 27: analog back-end white drive r * white drive r ext. brightness * white drive g ext. brightness * white drive b 9 bit dac 1.5 ma white drive g 9 bit dac 1.5 ma int. brightness * white drive b 9 bit dac 1.5 ma white drive r int. brightness * int. brightness * fast beam current lim. ext. contrast * white drive g * beam current lim. ext. contrast * white drive b * beam current lim. white drive r white drive g white drive b int . brightness ext. contrast ext. brightness 10 10 analog svm ou t 8 8 bit dac svm 1.88ma 0.94ma digital svm in 750 a blanking 750 a blanking 750 a blanking serial interface & mux clamp & mux clamp & mux 12 12 12 12 blank in fbl prio hcs
vdp 31xxb preliminary data sheet 26 micronas 2.11. synchronization and deflection the synchronization and deflection processing is distributed over front-end and back-end. the video clamping, horizontal and vertical sync separation and all video related timing information are processed in the front-end. most of the processing that runs at the hori- zontal frequency is programmed on the internal fast processor (fp). also the values for vertical and east/ west deflection are calculated by the fp software. the information extracted by the video sync processing is multiplexed onto the hardware front sync signal (fsy) and distributed internally to the rest of the video proces- sing system. the data for the vertical deflection, the sawtooth and the east/west correction signal is calculated in the front end. the data is transferred to the back-end by a single wire interface. the display related synchronization, i.e. generation of horizontal and vertical drive and synchronization of hori- zontal and vertical drive to the video timing extracted in the front-end, are implemented in hardware in the back- end. 2.11.1. deflection processing the deflection processing generates the signals for the horizontal and vertical drive (see fig. 2 ? 28). this block contains two phase-locked loops: ? pll2 generates the horizontal and vertical timing, e.g. blanking, clamping and composite sync. phase and frequency are synchronized by the front sync signal. ? pll3 adjusts the phase of the horizontal drive pulse and compensates for the delay of the horizontal output stage. phase and frequency are synchronized by the oscillator signal of pll2. the horizontal drive circuitry uses a digital sine wave generator to produce the exact (subclock) timing for the drive pulse. the generator runs at 1 mhz; in the output stage the frequency is divided down to give drive-pulse period and width. in standby mode, the output stage is driven from an internal 1 mhz clock that is derived from the 5 mhz clock signal and a fixed drive pulse width is used. when the circuit is switched out of standby operation, the drive pulse width is programmable. the horizontal drive uses an open drain output transistor. the main sync (msy) signal that is generated from pll3 is a multiplex of all display-related data (fig. 2 ? 29). this signal is intended for use by other pro- cessors, e.g. a pip processor can use this signal to ad- just to a certain display position. 2.11.2. horizontal phase adjustment this section describes a simple way to align pll phases and the horizontal frame position. 1. the parameter newlin in the front-end has to be adjusted. the minimum possible value is 34 (recom- mended for a standard 4:3 signal). 2. with hdrv, the duration of the horizontal drive pulse has to be adjusted. 3. with pofs2, the clamping pulse for the analog rgb input has to be adjusted to the correct position, e.g. the pedestal of the generator signal. 4. with pofs3, the horizontal position of the analog rgb signal (from scart) has to be adjusted. 5. with hpos, the digital rgb output signal (from vpc) has to be adjusted to the correct horizontal position. 6. with hbst and hbso, the start and stop values for the horizontal blanking have to be adjusted. note: the processing delay of the internal digital video path differs depending on the comb filter option of the vdp 31xxb. the versions with comb filter have an addi- tional delay of 35 clock cycles. therefore, the timing of the external analog rgb signals has to be adjusted (with pofs2 and pofs3) according to the actual hardware version of the vdp 31xxb. the hardware version can be read out via fp subaddress 0xf1.
vdp 31xxb preliminary data sheet 27 micronas phase comparator & lowpass pll2 composite sync generator e/w correction sawtooth pwm 15 bit csy e/w ouput v output v flyback pwm 15 bit dco front sync interface fsy vdata main sync generator vertical serial data phase comparator & lowpass pll3 1:64 & output stage h flyback h drive dco display timing line counter blanking, clamping, etc. clock & control sinewave generator & dac lpf standby clock fig. 2 ? 28: deflection processing block diagram msy vertical reset skew measure ? ment m1 m2 (not in scale) m1 m2 f v line [0] line [7] line [8] not used parity input analog video msy not used not used not used not used timing reference for picture bus ? chroma multiplex sync ? active picture data after xxx clocks v: vert. blanking 0 = off 1 = on f: field # 0 = field 1 1 = field 2 line: field line # 1...n parity fig. 2 ? 29: main sync format
vdp 31xxb preliminary data sheet 28 micronas 2.11.3. vertical and east/west deflection the calculations of the vertical and east/west deflection waveforms is done by the internal fast processor (fp). the algorithm uses a chain of accumulators to generate the required polynomial waveforms. to produce the deflection waveforms, the accumulators are initialized at the beginning of each field. the initialization values must be computed by the tv control processor and are written to the front-end once. the waveforms are described as polynomials in x, where x varies from 0 to 1 for one field. p: a + b (x ? 0.5) + c (x ? 0.5) 2 + d (x ? 0.5) 3 + e (x ? 0.5) 4 the initialization values for the accumulators a0..a3 for vertical deflection and a0..a4 for east/west deflection are 12-bit values. the vertical waveform can be scaled according the average beam current. this is used to compensate the effects of electric high tension changes due to beam cur- rent variations. in order to get a faster vertical retrace timing, the output impedance of the vertical d/a-converter can be reduced by 50% during the re- trace. fig. 2 ? 30 shows several vertical and east/west deflec- tion waveforms. the polynomial coefficients are also stated. 2.11.4. protection circuitry ? picture tube and drive stage protection is provided through the following measures: ? vertical flyback protection input: this pin searches for a negative edge in every field, otherwise the rgb drive signals are blanked. ? drive shutoff during flyback: this feature can be se- lected by software. ? safety input pin: this input has two thresholds. be- tween zero and the lower threshold, normal function- ing takes place. between the lower and the higher threshold, the rgb signals are blanked. above the higher threshold, the rgb signals are blanked and the horizontal drive is shut off. both thresholds have a small hysteresis. ? the main oscillator and the horizontal drive circuitry are run from a separate (standby) power supply and are already active while the tv set is powering up. fig. 2 ? 30: vertical and east/west deflection waveforms east/west: a,b,c,d,e 0,0,1,0,0 0,0,0,0,1 0,0,1,1,1 vertical: a,b,c,d 0,1,0,0 0,1,1,0 0,1,0,1
preliminary data sheet vdp 31xxb 29 micronas 2.12. reset function reset of most vdp 31xxb functions is performed by the reset pin. when this pin becomes active, all internal registers and counters are lost. when the reset pin is released, the internal reset is still active for 4 s. after that time, the initialization of all required registers is per- formed by the internal fast processor. during this initial- ization procedure (see fig. 2 ? 31) it is not possible to ac- cess the vdp 31xxb via the serial interface (i 2 c). access to other ics via the serial bus is possible during that time. the 5 mhz clock divider and the 1 mhz standby clock di- vider are not affected by reset. the clock source for the horizontal output generator is switched to the standby clock during reset. reset internal reset initialization 4 s approx. 60 s fig. 2 ? 31: external reset 2.13. standby and power-on in standby mode the whole signal processing of the vdp 31xxb is disabled and only some basic functions are working. the standby mode is realized by switching off the supplies for analog front-end (vsupf), analog back- end (vsupo) and digital circuitry (vsupd). the stand- by supply (vstby) still has its nominal voltage. to disable all the analog and digital functions, it is neces- sary to bring the analog and digital supplies below 0.5 v. only this guarantees that all the normal functions are disabled and the standby current for analog and digital supply is at its minimum. when switched off, the negative slope of the supply voltage vsupd should not be larger than approximately 0.2 v/ s (see recommended operating conditions). in the standby mode, all registers and counter values in the vdp 31xxb are lost, they will be re-initialized via the internal fast processor after analog and digital supplies are switched on again and the reset pin is released. in the standby mode the following functions are still available (see also 2.11.1.): ? 20.25 mhz crystal oscillator ? 5 mhz clock output (clk5) ? horizontal drive output (hout) the clock source for the horizontal output generator is switched to the standby clock which is derived from the 5 mhz clock. the duty cycle of hout is set to 50%. protection modes with safety and horizontal flyback pins are not available. the vdp 31xxb has clock and voltage supervision cir- cuits to generate a stable hout signal during power-on and standby. the hout signal is disabled until a proper clk5 signal (5 mhz clock) is detected. when released, the hout generator runs with the standby clock. cou- pling the hout generator to the deflection pll has to be done by ccu using the ehpll bit. fig. 2 ? 32 shows the signals during power-on and standby. vstby vsup d standby mode xtal clk5 clock release hout fig. 2 ? 32: power-on, standby on/off 1 s reset switching the hout signal into standby mode can be done by the ccu via the ehpll bit or by the internal volt- age supervision. the voltage supervision activates a power-down signal when the supply for the digital cir- cuits (vsupd) goes below 4.5 v for more than 50ns. this power down signal is extended by 50 s after vsupd is back again. the power-down signal switches the clock source for the hout generation to the standby clock and sets the duty cycle to 50%. this is exactly what the ehpll bit does. as the clocks from the deflection pll and the standby clock are not in phase, the actual phase (high/low) of the hout signal may be up to one pll or standby clock ( 1 s) longer than a regular one when the clock source is changed.
vdp 31xxb preliminary data sheet 30 micronas 3. serial interface 3.1. i 2 c-bus interface communication between the vdp and the external con- troller is done via i 2 c-bus. the vdp has two i 2 c-bus slave interfaces (for compatibility with vpc/ddp ap- plications) ? one in the front-end and one in the back- end. both i 2 c-bus interfaces use i 2 c clock synchroniza- tion to slow down the interface if required. both i 2 c-bus interfaces use one level of subaddress: the i 2 c-bus chip address is used to address the ic and a subaddress se- lects one of the internal registers. the i 2 c-bus chip ad- dresses are given below: chip address a6 a5 a4 a3 a2 a1 a0 r/w front-end 1 0 0 0 1 1 1 1/0 back-end 1 0 0 0 1 0 1 1/0 the registers of the vdp have 8 or 16-bit data size; 16-bit registers are accessed by reading/writing two 8-bit data words. figure 3 ? 1 shows i 2 c-bus protocols for read and write operations of the interface; the read operation requires an extra start condition and repetition of the chip address with read command set. 3.2. control and status registers table 3 ? 1 gives definitions of the vdp control and status registers. the number of bits indicated for each register in the table is the number of bits implemented in hard- ware, i.e. a 9-bit register must always be accessed using two data bytes but the 7 msb will be ? don ? t care ? on write operations and ? 0 ? on read operations. write registers that can be read back are indicated in table 3 ? 1. functions implemented by software in the on-chip con- trol microprocessor (fp) are explained in table 3 ? 3. a hardware reset initializes all control registers to 0. the automatic chip initialization loads a selected set of regis- ters with the default values given in table 3 ? 1. the register modes given in table 3 ? 1 are ? w: write only register ? w/r: write/read data register ? r: read data from vdp ? v: register is latched with vertical sync ? h: register is latched with horizontal sync the mnemonics used in the micronas vdp demo soft- ware are given in the last column. wp 1 or 2 byte data w high byte data s s ack ack ack ack 0111 1100 0111 1100 r s ack sda scl 1 0 sp p low byte data ack w= 0 r= 1 ack = 0 nak = 1 s = start p = stop ack nak fig. 3 ? 1: i 2 c-bus protocols 1000 111 1000 111 1000 111 i 2 c write access subaddress 7c i 2 c read access subaddress 7c
preliminary data sheet vdp 31xxb 31 micronas table 3 ? 1: i 2 c control and status registers of front-end i 2 c sub address number of bits mode function default name fp interface h ? 35 8 r fp status bit [0] write request bit [1] read request bit [2] busy fpsta h ? 36 16 w bit[8:0] 9-bit fp read address bit[11:9] reserved, set to zero fprd h ? 37 16 w bit[8:0] 9-bit fp write address bit[11:9] reserved, set to zero fpwr h ? 38 16 w/r bit[11:0] fp data register, reading/writing to this register will autoincrement the fp read/ write address. only 16 bit of data are transferred per i 2 c telegram. fpdat black line detector h ? 12 16 w/r read only register, do not write to this register! after reading, lowlin and uplin are reset to 127 to start a new measurement bit[6:0] number of lower black lines bit[7] always 0 bit[14:8] number of upper black lines bit[15] 0/1 normal/black picture blklin lowlin uplin blkpic pin circuits h ? 1f 16 w/r intlc & port pins: bit[2:0] 0..7 output strength for intlc & port pins (7 = tristate, 6 = weak ... 0 = strong) bit[3] 0 reserved (set to 0) bit[4] 0/1 pushpull/tristate for intlc pin bit[5] 0/1 synchronization/no synchronization with horizontal msy for signal intlc bit[15:6] reserved (set to 0) 0 0 0 trpad sncstr sncdis vasysel h ? 20 8 w/r sync generator control: bit[6:0] 0 reserved (set to 0) bit[7] 0/1 positive/negative polarity for intlc signal 0 synmode intlcinv priority bus h ? 24 8 w/r priority bus id register and control bit [2:0] 0..7 priority id, 0 highest bit [4:3] 0..3 pad driver strength, 0 (strong) to 3 (weak) bit [5] 0/1 reserved (set to 0) bit [6] 0/1 source for prio request: active video/clamp_to_1 bit [7] 0/1 disable/enable priority interface, if disabled frontend is disconnected from priority bus! 0 0 0 0 0 priomode pid priostr pidsrc pide
vdp 31xxb preliminary data sheet 32 micronas name default function mode number of bits i 2 c sub address sync generator h ? 21 16 w/r line length: bit[10:0] line length register line length has to be set to 1295 for correct adjustment of vertical signals. bit[15:11] reserved (set to 0) 1295 linlen h ? 29 16 w/r avo stop: bit[10:0] reserved (set to 0) bit[11] 0/1 disable/enable test pattern generator bit[13:12] luma output mode: 00 y = rampe (240 ... 17) 01 y = 16 10 y = 90 11 y = 240 bit[14] 0/1 reserved (set to 0) bit[15] 0/1 chroma output: pseudo color bar/zero 0 0 0 0 0 avstop colbaren lmode cmode h ? 22 16 w/r newline: bit[10:0] newline register this register defines the readout start of the next line in respect to the value of the sync counter. value of this register must be greater than 31 for correct operation. bit [15:11] reserved (set to 0) 50 newlin
vdp 31xxb preliminary data sheet 33 micronas table 3 ? 2: backend i 2 c-control and status registers i 2 c sub address number of bits mode function default name priority bus priority mask register, if bit[x] is set to 1 then the function is active for the respective signal priority h ? 75 9 w v bit [7:0] bit[x] 0/1: select contrast,brightness,matrix for main/side picture 0 pbct h ? 71 9 w v bit [7:0] bit[x] 0/1: select main (video)/external (via clut) rgb 0 pbergb h ? 7d 9 w v bit [7:0] bit[x] 0/1: enable/disable black level expander 0 pbble h ? 79 9 w v bit [7:0] bit[x] 0/1: disable/enable peaking transient suppression when signal is switched 0 pbpk h ? 4b 9 w v bit [7:0] bit[x] 0/1: disable/enable analog fast blank input 0 pbfb h ? 47 9 w v bit [2:0] picture frame generator priority id bit [8] enable prio id for picture frame generator 0 pfgid pfgen luma channel h ? 61 9 w v bit [5:0] 0..63/32 main picture contrast 32 ctm h ? 65 9 w v bit [5:0] 0..63/32 side picture contrast 32 cts h ? 51 9 w v bit [8:0] ? 256..255 main picture brightness 0 brm h ? 55 9 w v bit [8:0] ? 256..255 side picture brightness 0 brs h ? 59 9 w v black level expander: bit [3:0] 0..15 tilt coefficient bit [8:4] 0...31 amount 8 12 btlt bam h ? 5d 9 w v black level expander: bit [8:0] 0..511 disable expansion, threshold value 200 bthr h ? 69 9 w v luma peaking filter, the gain at high frequencies and small signal amplitudes is: 1 + (k1+k2)/8 bit [3:0] 0..15 k1: peaking level undershoot bit [7:4] 0..15 k2: peaking level overshoot bit [8] 0/1 peaking value normal/inverted (peaking/softening) 4 4 0 pkun pkov pkinv h ? 6d 9 w v luma peaking filter, coring bit [4:0] 0..31 coring level bit [7:5] reserved bit [8] 0/1 peaking filter center frequency high/low 3 0 cor pfs h ? 41 9 w v luma soft limiter, slope a and b bit [3:0] slope segment a bit [7:4] slope segment b 0 0 lslsa lslsb h ? 45 9 w v bit [7:0] luma soft limiter absolute limit (unsigned) bit [8] 0/1 modulation off/on 255 1 lslal lslm h ? 49 9 w v bit [8:0] luma soft limiter segment b tilt point (unsigned) 300 lsltb h ? 4d 9 w v bit [8:0] luma soft limiter segment a tilt point (unsigned) 250 lslta
vdp 31xxb preliminary data sheet 34 micronas name default function mode number of bits i 2 c sub address chroma channel h ? 14 8 w/r luma/chroma matching delay bit [2:0] ? 3...3 variable chroma delay bit [3] 0/1 chroma polarity signed / offset binary bit [4] 0/1 c b (u) sample first / c r (v) sample first bit [7:5] reserved, set to 0 0 1 0 0 ldb cob envu h ? 66 9 w v digital transient improvement bit [3:0] 0..15 coring value bit [7:4] 0..15 dti gain bit [8] 0/1 narrow/wide bandwidth mode 1 5 1 dtico dtiga dtimo inverse matrix h ? 7c h ? 74 9 9 w v w v main picture matrix coefficient r ? y = mr1m*c b + mr2m*c r bit [8:0] ? 256/128 ... 255/128 bit [8:0] ? 256/128 ... 255/128 0 86 mr1m, mr2m h ? 6c h ? 64 9 9 w v w v main picture matrix coefficient g ? y = mg1m*c b + mg2m*c r bit [8:0] ? 256/128 ... 255/128 bit [8:0] ? 256/128 ... 255/128 ? 22 ? 44 mg1m, mg2m h ? 5c h ? 54 9 9 w v w v main picture matrix coefficient b ? y = mb1m*c b + mb2m*c r bit [8:0] ? 256/128 ... 255/128 bit [8:0] ? 256/128 ... 255/128 113 0 mb1m, mb2m h ? 78 h ? 70 9 9 w v w v side picture matrix coefficient r ? y = mr1s*c b + mr2s*c r bit [8:0] ? 256/128 ... 255/128 bit [8:0] ? 256/128 ... 255/128 0 73 mr1s, mr2s h ? 68 h ? 60 9 9 w v w v side picture matrix coefficient g ? y = mg1s*c b + mg2s*c r bit [8:0] ? 256/128 ... 255/128 bit [8:0] ? 256/128 ... 255/128 ? 19 ? 37 mg1s, mg2s h ? 58 h ? 50 9 9 w v w v side picture matrix coefficient b ? y = mb1s*c b + mb2s*c r bit [8:0] ? 256/128 ... 255/128 bit [8:0] ? 256/128 ... 255/128 97 0 mb1s, mb2s color look-up table h ? 00 ? h ? 0f 16 w h color look-up table : 16 entries, 12 bit wide, the clut registers are initialized at power-up bit [3:0] 0..15 blue amplitude bit [7:4] 0..15 green amplitude bit [11:8] 0..15 red amplitude 000h f00h 0f0h ff0h 00fh f0fh 0ffh fffh 7ffh 700h 070h 770h 007h 707h 077h 777h clut0 clut15 h ? 11 16 w h picture frame color 12 bit wide, bit [3:0] 0..15 blue amplitude bit [7:4] 0..15 green amplitude bit [11:8] 0..15 red amplitude 0 0 0 pfcb pfcg pfcr
vdp 31xxb preliminary data sheet 35 micronas name default function mode number of bits i 2 c sub address h ? 4c 9 w v digital osd insertion contrast for r (amplitude range: 0 to 255) bit [3:0] 0..13 r amplitude = clutn (drct + 4) 14,15 invalid picture frame insertion contrast for r (ampl. range: 0 to 255) bit [7:4] 0..13 r amplitude = pfcr (pfrct + 4) 14,15 invalid 8 8 drct pfrct h ? 48 9 w v digital osd insertion contrast for g (amplitude range: 0 to 255) bit [3:0] 0..13 g amplitude = clutn (dgct + 4) 14,15 invalid picture frame insertion contrast for g (ampl. range: 0 to 255) bit [7:4] 0..13 g amplitude = pfcg (pfgct + 4) 14,15 invalid 8 8 dgct pfgct h ? 44 9 w v digital osd insertion contrast for b (amplitude range: 0 to 255) bit [3:0] 0..13 b amplitude = clutn (dbct + 4) 14,15 invalid picture frame insertion contrast for b (ampl. range: 0 to 255) bit [7:4] 0..13 b amplitude = pfcb (pfbct + 4) 14,15 invalid 8 8 dbct pfbct picture frame generator h ? 4f 9 w v bit [8:0] horizontal picture frame begin code 0 = picture frame generator horizontally disabled code 1ff = full frame 0 pfghb h ? 53 9 w v bit [8:0] horizontal picture frame end 0 pfghe h ? 63 9 w v bit [8:0] vertical picture frame begin code 0 = picture frame generator vertically disabled 270 pfgvb h ? 6f 9 w v bit [8:0] vertical picture frame end 56 pfgve enable and priority ? see under ? priority bus ? picture frame color ? see under ? color look-up table ? scan velocity modulation h ? 62 9 w v video mode coefficients bit [5:0] gain1 bit [8:6] differentiator delay 1 (0= filter off, 1...6= delay) 60 4 svg1 svd1 h ? 5e 9 w v text mode coefficients bit [5:0] gain 2 bit [8:6] differentiator delay 2 (0= filter off, 1...6= delay) 60 4 svg2 svd2 h ? 5a 9 w v limiter bit [6:0] limit value bit [8:5] not used, set to ? 0 ? 100 0 svlim h ? 56 9 w v delay and coring bit [3:0] adjustable delay, in 1/2 display clock steps, (value 5 : delay of svmout is the same as for rgbout bit [7:4] coring value bit [8] not used, set to ? 0 ? 7 0 svdel svcor
vdp 31xxb preliminary data sheet 36 micronas name default function mode number of bits i 2 c sub address display controls h ? 52 h ? 4e h ? 4a 9 9 9 w v w v w v cutoff red cutoff green cutoff blue 0 0 0 cr cg cb tube and picture measurement h ? 7b 9 w v picture measurement start line bit [8:0] (tml+9)..511 first line of picture measurement 23 pmst h ? 6b 9 w v picture measurement stop line bit [8:0] (pmst+1)..511 last line of picture measurement 308 pmso h ? 7f 9 w v tube measurement line bit [8:0] 0..511 start line for tube measurement 15 tml h ? 25 8 w/r tube and picture measurement control bit [0] 0/1 disable/enable tube measurement bit [1] 0/1 80/40 khz bandwidth for picture measurement bit [2] 0/1 disable/enable picture measurement (writing a ? 1 ? starts one measurement cycle) bit [3] 0/1 large/small picture measurement window, will be disabled from bit[3] in address h ? 32 bit [4] 0/1 measure / offset check for adc bit [7:5] reserved 0 pmc tmen pmbw pmen pmwin ofsen h ? 13 16 w/r white drive measurement control bit [9:0] 0..1023 rgb values for white drive beam current measurement bit [10] reserved bit [11] 0/1 rgb values for white drive beam current measurement disabled/enabled 512 0 wdrv ewdm h ? 18 h ? 19 h ? 1a h ? 1d h ? 1c h ? 1b 8 r measurement result registers minimum in active picture maximum in active picture white drive cutoff/leakage red cutoff/leakage green cutoff/leakage blue, read pulse starts tube measurement ? mrmin mrmax mrwdr mrcr mrcg mrcb h ? 1e 8 r measurement adc status and fast blank input status measurement status register bit [0] 0/1 tube measurement active / complete bit [2:1] white drive measurement cycle 00 red 01 green 10 blue 11 reserved bit [3] 0/1 picture measurement active / complete bit [4] 0/1 fast blank input low / high (static) bit [5] 1 fast blank input negative transition since last read (bit reset at read) bit [7:6] reserved ? pms
vdp 31xxb preliminary data sheet 37 micronas name default function mode number of bits i 2 c sub address timing h ? 67 9 w v vertical blanking start bit [8:0] 0..511 first line of vertical blanking 305 vbst h ? 77 9 w v vertical blanking stop bit [8:0] 0..511 last line of vertical blanking 25 vbso h ? 73 9 w v start of black level expander measurement bit [8:0] 0..511 first line of measurement, stop with first line of vertical blanking 30 avst h ? 5f 9 w v bit [8:0] free running field period = (value 4) lines 0 stimp horizontal deflection h ? 7a 9 w v adjustable delay of pll2, clamping, and blanking (relative to front sync) adjust clamping pulse for analog rgb input bit [8:0] ? 256..+255 8 s ? 141 pofs2 h ? 76 9 w v adjustable delay of flyback, main sync, csync and analog rgb (relative to pll2) adjust horizontal drive or csync bit [8:0] ? 256..+255 8 s 0 pofs3 h ? 7e 9 w v adjustable delay of main sync (relative to flyback) adjust horizontal position for digital picture bit [8:0] 20 steps 1 s 120 hpos h ? 5b 9 w/r start of horizontal blanking bit [8:0] 0..511 1 hbst h ? 57 9 w/r end of horizontal blanking bit [8:0] 0..511 48 hbso h ? 6a h ? 6e h ? 72 9 9 9 w v w v w v pll2/3 filter coefficients, 1of5 bit code (n set bit number) bit [5:0] proportional coefficient pll3, 2 ? n ? 1 bit [5:0] proportional coefficient pll2, 2 ? n ? 1 bit [5:0] integral coefficient pll2, 2 ? n ? 5 2 1 2 pkp3 pkp2 pki2 h ? 15 16 w/r horizontal drive and vertical signal control register bit [5:0] 0..63 horizontal drive pulse duration in s (internally limited to 4..61) bit [6] 0/1 disable/enable horizontal pll2 and pll3 bit [7] 0/1 1: disable horizontal drive pulse during flyback bit [8] 0/1 reserved, set to ? 0 ? bit [9] 0/1 enable/disable ultra black blanking bit [10] 0/1 0: all outputs blanked 1: normal mode bit [11] 0/1 enable/disable clamping for analog rgb input bit [12] 0/1 disable/enable vertical free running mode (field is set to field2, no interlace) bit [13] 0/1 enable/disable vertical protection bit [14] 0/1 internal/external (under vpc control) start of vertical and e/w signal bit [15] 0/1 disable/enable phase shift of display clock 32 0 0 0 1 0 0 0 0 1 hdrv ehpll eflb dubl ebl dcrgb selft dvpr xdefl diska
vdp 31xxb preliminary data sheet 38 micronas name default function mode number of bits i 2 c sub address output pins h ? 10 8 w/r output pin configuration bit [2:0] pin driver strength, msy and csy 7 = tristate 6 = minimum strength 0 = maximum strength bit [4:3] reserved (set to 0) bit [5] 0/1 disable/enable internal resistor for vertical and east/west drive output bit [7:6] function of csy pin : 00 composite sync signal output 01 25 hz output (field1/field2 signal) 10 no interlace (field 2), output = 0 11 1 mhz horizontal drive clock 0 pstsy vewxr csym miscellaneous h ? 32 8 w/r fast blank interface mode bit [0] 0 internal fast blank 1 from fblin1 pin 1 force internal fast blank 1 signal to high bit [1] 0/1 internal fast blank active high/low bit [2] 0/1 disable/enable clamping reference for rgb outputs bit [3] 1 full line madc measurement window, disables bit [3] in address h ? 25 bit [4] 0/1 horizontal flyback input active high/low bit [6:5] reserved (set to 0) bit [7] 0 internal fast blank 1 from fblin1 pin 1 force internal fast blank 1 signal to low 0 fbmod fbfoh1 fbpol clmpr flmw flpol fbfol1 h ? 31 8 w/r fast blank interface mode 2 bit [0] 0 internal fast blank 2 from fblin2 pin 1 force internal fast blank 2 signal to high bit [1] 0 internal fast blank 2 from fblin2 pin 1 force internal fast blank 2 signal to low bit [2] fast blank input priority 0 fblin1 > fblin2 1 fblin1 < fblin2 bit [3] fast blank monitor input select 0 monitor connected to fblin1 pin 1 monitor connected to fblin2 pin bit [4] half contrast switch enable 0 port0 enable / hcs disable 1 port0 disable / hcs enable bit [5] 0 half contrast from hcs pin 1 force half contrast signal to high bit [6] 0/1 half contrast active high/low at hcs pin bit [7] reserved (set to 0) 0 fbmod2 fbfoh2 fbfol2 fbprio fbmon hcsen hcsfoh hcspol h ? 34 16 w/r io port bit [6:0] data to/from port[6:0] bit [7] front sync output at port1 0 port1 input/output enable 1 fsy output enable bit [14:8] port direction 0 switch port[bit ? 8] to input 1 switch port[bit ? 8] to output bit [15] port enable 0 color[4:0] enable / port[6:2] disable 1 color[4:0] disable / port[6:2] enable 0 ioport iodata fsyoen iodir ioen
preliminary data sheet vdp 31xxb 39 micronas table 3 ? 3: control registers of the fast processor for control of front-end functions ? default values are initialized at reset fp sub- address function default name standard selection h ? 20 standard select: bit[2:0] standard 0 pal b,g,h,i (50 hz) 4.433618 1 ntsc m (60 hz) 3.579545 2 secam (50 hz) 4.286 3 ntsc44 (60 hz) 4.433618 4 pal m (60 hz) 3.575611 5 pal n (50 hz) 3.582056 6 pal 60 (60 hz) 4.433618 7 ntsc comb (60 hz) 3.579545 bit[3] 0/1 standard modifier pal modified to simple pal ntsc modified to compensated ntsc secam modified to monochrome 625 ntscc modified to monochrome 525 bit[4] reserved (set to 0) bit[5] 0/1 2-h comb filter off/on bit[6] 0/1 s-vhs mode off/on option bits allow to suppress parts of the initialization, this can be used for color standard search: bit[7] no hpll setup bit[8] no vertical setup bit[9] no acc setup bit[10] 2-h comb filter set-up only bit[11] status bit, normally write 0. after the fp has switched to a new standard, this bit is set to 1 to indicate operation complete. standard is automatically initialized when the insel register is written. 0 sdt pal ntsc secam ntsc44 palm paln pal60 ntscc sdtmod comb svhs sdtopt h ? 22 picture start position, this register sets the start point of active video, this can be used e.g. for panning. the setting is updated when ? sdt ? register is updated. 0 sfif h ? 23 luma/chroma delay adjust. the setting is updated when ? sdt ? register is updated. bit[5:0] reserved, set to zero bit[11:6] luma delay in clocks, allowed range is +1 ... ? 7 0 ldly
vdp 31xxb preliminary data sheet 40 micronas name default function fp sub- address standard selection h ? 21 input select: writing to this register will also initialize the standard bit[1:0] luma selector 00 vin3 01 vin2 10 vin1 11 vin4 bit[2] chroma selector 0/1 vin1/cin bit[4:3] if compensation 00 off 01 6 db/okt 10 12 db/okt 11 10 db/mhz only for secam bit[6:5] chroma bandwidth selector 00 narrow 01 normal 10 broad 11 wide bit[7] 0/1 adaptive/fixed secam notch filter bit[8] 0/1 enable luma lowpass filter bit[10:9] hpll speed 00 no change 01 terrestrial 10 vcr 11 mixed bit[11] status bit, write 0, this bit is set to 1 to indicate operation complete. 00 1 00 01 insel vis cis ifc cbw fntch lowp hpllmd comb filter h ? 27 comb filter control register bit[0] 0 comb coefficients are calculated for luma/chroma 1 comb coefficients for luma are used for luma and chroma bit[1] 0 luma comb strength depends on signal amplitude 1 luma comb strength is independent of amplitude bit[2] 0 reduced comb booster 1 max comb booster bit[4:3] 0..3 comb strength for chroma signal bit[6:5] 0..3 comb strength for luma signal bit[11:7] 0..31 overall limitation of the calculated comb coefficients 0 no limitation 31 max limitation (1/2) 0 0 1 3 2 0 cmb_uc cc daa kb kc ky clim color processing h ? 39 amplitude killer level (0:killer disabled) 25 kilvl h ? 3a amplitude killer hysteresis 5 kilhy h ? dc ntsc tint angle, 512 = /4 0 tint
preliminary data sheet vdp 31xxb 41 micronas name default function fp sub- address dvco h ? f8 crystal oscillator center frequency adjust, ? 2048 ... 2047 ? 720 dvco h ? f9 crystal oscillator center frequency adjustment value for line lock mode, true adjust value is dvco ? adjust. for factory crystal alignment, using standard video signal: set dvco = 0, set lock mode, read crystal offset from adjust register and use negative value for initial center frequency adjustment via dvco. read only adjust h ? f7 crystal oscillator line-locked mode, lock command/status write: 100 enable lock 0 disable lock read: 0 unlocked >2047 locked 0 xlck fp status register h ? 12 general purpose control bits bit[2:0] reserved, do not change bit[3] vertical standard force bit[8:4] reserved, do not change bit[9] disable flywheel interlace bit[11:10] reserved, do not change to enable vertical free run mode set vfrc to 1 and dflw to 0 0 1 vfrc dflw h ? 13 standard recognition status bit[0] 1 vertical lock bit[1] 1 horizontally locked bit[2] 1 no signal detected bit[3] 1 color amplitude killer active bit[4] 1 disable amplitude killer bit[5] 1 color ident killer active bit[6] 1 disable ident killer bit[7] 1 interlace detected bit[8] 1 no vertical sync detection bit[9] 1 spurious vertical sync detection bit[11:10] reserved ? asr h ? cb number of lines per field, p/s: 312, n: 262 read only nlpf h ? 15 vertical field counter, incremented per field vcnt h ? 74 measured sync amplitude value, nominal: 768 (pal), 732 (ntsc) read only sampl h ? 31 measured burst amplitude read only bampl h ? f0 firmware version number bit[7:0] internal revision number bit[11:8] firmware release read only sw_version h ? f1 hardware version number bit[7:0] internal hardware revision number bit[11:8] hardware id 0000 = vdp 3120b 1000 = vdp 3116b 0100 = vdp 3112b 1100 = vdp 3108b 1110 = vdp 3104b read only hw_version
vdp 31xxb preliminary data sheet 42 micronas name default function fp sub- address scaler control register h ? 40 scaler mode register bit[1:0] scaler mode 0 linear scaling mode 1 nonlinear scaling mode, ? panorama ? 2 nonlinear scaling mode, ? waterglass ? 3 reserved bit[10:2] reserved, set to 0 bit[11] scaler update 0 start scaler update command, when the registers are updated the bit is set to 1 0 scmode pano h ? 41 luma offset register bit[6:0] luma offset 0..127 itu-r output format: 57 cvbs output format: 4 this register is updated when the scaler mode register is written 57 yoffs h ? 42 active video length for 1-h fifo bit[11:0] length in pixels this register is updated when the scaler mode register is written 1080 fflim h ? 43 scaler1 coefficient, this scaler is compressing the signal. for compression by a factor c the value c*1024 is required. bit[11:0] allowed values from 1024..4095 this register is updated when the scaler mode register is written 1024 scinc1 h ? 44 scaler2 coefficient, this scaler is expanding the signal. for expansion by a factor c the value 1/c*1024 is required. bit[11:0] allowed values from 256..1024 this register is updated when the scaler mode register is written 1024 scinc2 h ? 45 scaler1/2 nonlinear scaling coefficient this register is updated when the scaler mode register is written 0 scinc h ? 47 ? h ? 4b scaler1 window controls, see table 5 12-bit registers for control of the nonlinear scaling this register is updated when the scaler mode register is written 0 scw1_0 ? 4 h ? 4c ? h ? 50 scaler2 window controls see table 5 12-bit registers for control of the nonlinear scaling this register is updated when the scaler mode register is written 0 scw2_0 ? 4
preliminary data sheet vdp 31xxb 43 micronas 3.2.1. scaler adjustment in case of linear scaling, most of the scaler registers need not be set. only the scaler mode, active video length, and the fixed scaler increments (scinc1/scinc2) must be written. the adjustment of the scaler for nonlinear scaling modes should use the parameters given in table 3 ? 4. table 3 ? 4: set-up values for nonlinear scaler modes register scaler modes ? waterglass ? border 35% ? panorama ? border 30% center compression 3/4 5/6 4/3 6/5 scinc1 1643 1427 1024 1024 scinc2 1024 1024 376 611 scinc 90 56 85 56 fflim 945 985 921 983 scw1 ? 0 110 115 83 94 scw1 ? 1 156 166 147 153 scw1 ? 2 317 327 314 339 scw1 ? 3 363 378 378 398 scw1 ? 4 473 493 461 492 scw2 ? 0 110 115 122 118 scw2 ? 1 156 166 186 177 scw2 ? 2 384 374 354 363 scw2 ? 3 430 425 418 422 scw2 ? 4 540 540 540 540
vdp 31xxb preliminary data sheet 44 micronas table 3 ? 5: control registers of the fast processor for control of back-end functions ? default values are initialized at reset fp sub- address function default name fp display control register h ? 130 white drive red (0...1023) 700 wdr 1) h ? 131 white drive green (0...1023) 700 wdg 1) h ? 132 white drive blue (0...1023) 700 wdb 1) h ? 139 internal brightness, picture (0...511), the center value is 256, the range allows for both increase and reduction of brightness. 256 ibr h ? 13c internal brightness, measurement (0...511), the center value is 256, the brightness for measurement can be set to measure at higher cutoff cur- rent. the measurement brightness is independent of the drive values. 256 ibrm h ? 13a analog brightness for external rgb (0...511), the center value is 256, the range allows for both increase and reduction of brightness. 256 abr h ? 13b analog contrast for external rgb (0...511) 350 act 1) the white drive values will become active only after writing the blue value wdb, latching of new values is indicated by setting the msb of wdb. fp display control register, bcl h ? 144 bcl threshold current, 0...2047 (max adc output ~1152) 1000 bclthr h ? 142 bcl time constant 0...15 13 ... 1700 msec 15 bcltm h ? 143 bcl loop gain. 0..15 0 bclg h ? 145 bcl minimum contrast 0...1023 307 bclmin h ? 105 test register for bcl/eht comp. function, register value: 0 normal operation 1 stop adc offset compensation x>1 use x in place of input from measurement adc 0 bcltst fp display control register, deflection h ? 103 interlace offset, ? 2048..2047 this value is added to the sawtooth output during one field. 0 intlc h ? 102 discharge sample count for deflection retrace, sawtooth dac output impedance is reduced for dscc lines after ver- tical retrace. 7 dscc h ? 11f vertical discharge value, sawtooth output value during discharge operation, typically same as a0 init value for sawtooth. ? 1365 dscv h ? 10b eht (electronic high tension) compensation coefficient, 0...511 0 eht h ? 10a eht time constant. 0..15 ?? > 3.2..410 msec 15 ehttm
preliminary data sheet vdp 31xxb 45 micronas control registers, continued fp sub- address function default name fp display control register, vertical sawtooth h ? 110 dc offset of sawtooth output this offset is independent of eht compensation. 0 ofs h ? 11b accu0 init value ? 1365 a0 h ? 11c accu1 init value 900 a1 h ? 11d accu2 init value 0 a2 h ? 11e accu3 init value 0 a3 fp display control register, east-west parabola h ? 12b accu0 init value ? 1121 a0 h ? 12c accu1 init value 219 a1 h ? 12d accu2 init value 479 a2 h ? 12e accu3 init value ? 1416 a3 h ? 12f accu4 init value 1052 a4
vdp 31xxb preliminary data sheet 46 micronas 3.2.2. calculation of vertical and east-west deflection coefficients in table 3 ? 6 the formula for the calculation of the deflec- tion initialization parameters from the polynomial coeffi- cients a,b,c,d,e is given for the vertical and east-west deflection. let the polynomial be p : a b ( x 0.5) c ( x 0.5) 2 d ( x 0.5) 3 e ( x 0.5) 4 the initialization values for the accumulators a0..a3 for vertical deflection and a0..a4 for east-west deflection are 12-bit values. the coefficients that should be used to calculate the initialization values for different field fre- quencies are given below, the values must be scaled by 128, i.e. the value for a0 of the 50 hz vertical deflection is a 0 ( a * 128 b * 1365.3 c * 682.7 d * 682.7)
12 8 table 3 ? 6: tables for the calculation of initialization values for vertical sawtooth and east-west parabola vertical deflection 50 hz a b c d a0 128 ? 1365.3 +682.7 ? 682.7 a1 899.6 ? 904.3 +1363.4 a2 296.4 898.4 a3 585.9 vertical deflection 60 hz a b c d a0 128 ? 1365.3 +682.7 ? 682.7 a1 1083.5 ? 1090.2 +1645.5 a2 429.9 ? 1305.8 a3 1023.5 east-west deflection 50 hz a b c d e a0 128 ? 341.3 1365.3 ? 85.3 341.3 a1 111.9 ? 899.6 84.8 ? 454.5 a2 586.8 ? 111.1 898.3 a3 72.1 ? 1171.7 a4 756.5 east-west deflection 60 hz a b c d e a0 128 ? 341.3 1365.3 ? 85.3 341.3 a1 134.6 ? 1083.5 102.2 ? 548.4 a2 849.3 ? 161.2 1305.5 a3 125.6 ? 2046.6 a4 1584.8
preliminary data sheet vdp 31xxb 47 micronas 4. specifications 4.1. outline dimensions fig. 4 ? 1: 64-pin plastic shrink dual-inline package (psdip64) weight approximately 9.0 g dimensions in mm 0.457 1.29 132 33 64 3 0.3 1.9 (1) 1.778 0.05 1 0.1 57.7 0.1 3.2 0.4 3.8 0.1 4.8 0.4 19.3 0.1 18 0.1 20.1 0.5 0.27 0.06 spgs0016-4/3e 31 x 1.778 = 55.118 0.1 2.5 0.3 4.2. pin connections and short descriptions nc = not connected; leave vacant lv = if not used, leave vacant x = obligatory; connect as described in circuit diagram pin no. pin name type connection short description (if not used) 1 test in gnd df test pin, reserved for test 2 resq in x reset input, active low 3 scl in/out x i 2 c bus clock 4 sda in/out x i 2 c bus data 5 dsgnd x digital shield gnd d 6 port0 hcs in/out lv io port expander 0 / half contrast switch 7 port1 fsy in/out lv io port expander 1 / front sync output 8 csy out lv composite sync output 9 msy out lv main sync output 10 intlc out lv interlace control output 11 vprot in gnd o vertical protection input 12 safety in gnd o safety input 13 hflb in hout horizontal flyback input
vdp 31xxb preliminary data sheet 48 micronas short description connection type pin name pin no. (if not used) 14 gnd df x ground, digital circuitry front-end 15 vsup d x supply voltage, digital circuitry 16 gnd do x ground, digital circuitry back-end 17 pr0 in/out lv picture bus priority control (lsb) 18 pr1 in/out lv picture bus priority control 19 pr2 in/out lv picture bus priority control (msb) 20 color4 port2 in/out gnd df picture bus color address 4 / io port expander 2 21 color3 port3 in/out gnd df picture bus color address 3 / io port expander 3 22 color2 port4 in/out gnd df picture bus color address 2 / io port expander 4 23 color1 port5 in/out gnd df picture bus color address 1 / io port expander 5 24 color0 port6 in/out gnd df picture bus color address 0 / io port expander 6 25 dsgnd x digital shield gnd d 26 rsw2 out gnd o range switch2 for measurement adc 27 rsw1 out gnd o range switch1 for measurement adc 28 sense in gnd o sense adc input 29 gnd m x ground, madc input 30 gnd v out lv ground, vertical outputs 31 vert out lv vertical sawtooth output 32 ew out lv vertical parabola output 33 xref in x reference input for rgb dacs 34 svmout out vsup o scan velocity modulation output 35 gnd o x ground, analog back-end 36 vsup o x supply voltage, analog back-end 37 rout out vsup o analog red output 38 gout out vsup o analog green output 39 bout out vsup o analog blue output 40 vrd in x dac reference 41 rin in gnd o analog red input 42 gin in gnd o analog green input
preliminary data sheet vdp 31xxb 49 micronas short description connection type pin name pin no. (if not used) 43 bin in gnd o analog blue input 44 fblin in gnd o fast blank input 45 rin2 in gnd o analog red input 2 46 gin2 in gnd o analog green input 2 47 bin2 in gnd o analog blue input 2 48 fblin2 in gnd o fast blank input 2 49 clk20 out lv 20 mhz system clock output 50 hout out x horizontal drive output 51 xtal1 in x analog crystal input 52 xtal2 out x analog crystal output 53 vstby x standby supply voltage 54 clk5 out lv 5 mhz clock output 55 gnd f x ground, analog front-end 56 isgnd in gnd f signal ground for analog input 57 vrt in x reference voltage top, video adc 58 vsup f x supply voltage, analog front-end 59 vout out lv analog video output 60 cin in vrt analog chroma input 61 vin1 in vrt analog video 1 input 62 vin2 in vrt analog video 2 input 63 vin3 in vrt analog video 3 input 64 vin4 in vrt analog video 4 input 4.3. pin descriptions pin 1 ? test input, test (fig. 4 ? 3) this pin enables factory test modes. for normal opera- tion it must be connected to ground. pin 2 ? reset input, resq (fig. 4 ? 3) a low level on this pin resets the vdp 31xxb. pin 3 ? i 2 c bus clock, scl (fig. 4 ? 12) this pin connects to the i 2 c bus clock line. pin 4 ? i 2 c bus data, sda (fig. 4 ? 12) this pin connects to the i 2 c bus data line. pin 5 ? ground (digital shield), dsgnd pin 6, 7, 20 ? 24 ? io port expander, port[6:0] (fig. 4 ? 13) these pins provide an i 2 c programmable i/o port, which can be used to read and write slow external signals.
vdp 31xxb preliminary data sheet 50 micronas pin 6 ? half contrast switch input, hcs (fig. 4 ? 16) via this input pin the output level of the analog rgb out- put pins can be reduced by 3db. pin 7 ? front sync output, fsy (fig. 4 ? 13) this pin supplies the front sync information pin 8 ? composite sync output, csy (fig. 4 ? 13) this output supplies a standard composite sync signal that is compatible to the analog rgb output signals. pin 9 ? main sync output, msy (fig. 4 ? 13) this pin supplies the main sync information. pin 10 ? interlace output, intlc (fig. 4 ? 13) this pin supplies the interlace information, 0 indicates first field, 1 indicates second field. pin 11 ? vertical protection input, vprot (fig. 4 ? 14) the vertical protection circuitry prevents the picture tube from burn-in in the event of a malfunction of the vertical deflection stage. during vertical blanking, a signal level of 2.5v is sensed. if a negative edge cannot be detected, the rgb output signals are blanked. pin 12 ? safety input, safety (fig. 4 ? 14) this is a three-level input. low level means normal func- tion. at the medium level rgb signals are blanked and at high level rgb signals are blanked and horizontal drive is shut off. pin 13 ? horizontal flyback input, hflb (fig. 4 ? 14) via this pin the horizontal flyback pulse is supplied to the vdp 31xxb. pin 14 ? ground (digital circuitry front-end), gnd df pin 15 ? supply voltage (digital circuitry), vsup d pin 16 ? ground (digital circuitry back-end), gnd do pin 17, 18, 19 ? picture bus priority, pr[2:0] (fig. 4 ? 5) the picture bus priority lines carry the digital priority selection signals. the priority interface allows digital switching of up to 8 sources to the backend processor. switching for different sources is prioritized and can be done from pixel to pixel. pin 20...24 ? picture bus color address, color[4:0] (fig. 4 ? 16) the picture bus color lines carry the digital rgb col- or data. they are used as address for the color lookup table. pin 25 ? ground (digital shield), dsgnd . pin 26, 27 ? range switch for measurement adc , rsw1, rsw2 (fig. 4 ? 19) these pins are open drain pull-down outputs. rsw1 is switched off during cutoff and whitedrive measurement. rsw2 is switched off during cutoff measurement only. pin 28 ? measurement adc input, sense (fig. 4 ? 15) this is the input of the analog digital converter for the picture and tube measurement. pin 29 ? ground (measurement adc reference input), gnd m this is the ground reference for the measurement a/d converter. pin 30 ? ground (vertical sawtooth output), gnd v (fig. 4 ? 20) this is the ground reference for the vertical outputs. pin 31 ? vertical sawtooth output, vert (fig. 4 ? 20) this pin supplies the drive signal for the vertical output stage. the drive signal is generated with 15-bit precision by the fast processor in the front-end. the analog volt- age is generated by a 4-bit current-dac with external re- sistor and uses digital noise shaping. pin 32 ? east-west parabola output, ew (fig. 4 ? 20) this pin supplies the parabola signal for the east-west correction. the drive signal is generated with 15 bit pre- cision by the fast processor in the front-end. the analog voltage is generated by a 4-bit current-dac with exter- nal resistor and uses digital noise shaping. pin 33 ? dac current reference, xref (fig. 4 ? 21) external reference resistor for dac output currents, typi- cal 10 k ? to adjust the output current of the d/a convert- ers (see recommended operating conditions). this re- sistor has to be connected to analog ground as closely as possible to the pin. pin 34 ? scan velocity modulation output, svmout (fig. 4 ? 17) this output delivers the analog svm signal. the d/a converter is a current sink like the rgb d/a converters. at zero signal the output current is 50% of the maximum output current. pin 35 ? ground (analog back-end), gnd o pin 36 ? supply voltage (analog back-end), vsup o pin 37, 38, 39 ? analog rgb outputs, rout, gout, bout (fig. 4 ? 17) this are the analog red/green/blue outputs of the back- end. the outputs sink a current of max. 8ma. pin 40 ? dac reference decoupling, vrd (fig. 4 ? 21) via this pin the dac reference voltage is decoupled by an external capacitance. the dac output currents de- pend on this voltage, therefore a pull-down transistor can be used to shut off all beam currents. a decoupling capacitor of 3.3 f//100nf is required.
preliminary data sheet vdp 31xxb 51 micronas pin 41, 42, 43, 45, 46, 47 ? analog rgb inputs, rin1/2, gin1/2, bin1/2 (fig. 4 ? 15) these pins are used to insert an external analog rgb signal, e.g. from a scart connector which can by switched to the analog rgb outputs with the fast blank signal. the analog backend provides separate bright- ness and contrast settings for the external analog rgb signals. pin 44, 48 ? fast blank inputs, fblin1/2 (fig. 4 ? 15) these pins are used to switch the rgb outputs to the ex- ternal analog rgb inputs. pin 49 ? main clock output, clk20 (fig. 4 ? 4) this is the 20.25mhz main system clock, that is used by all circuits in a high-end vdp system. all external timing is derived from this clock. pin 50 ? horizontal drive output, hout (fig. 4 ? 18) this open drain output supplies the the drive pulse for the horizontal output stage. the polarity and gating with the flyback pulse are selectable by software. pin 51, 52 ? crystal input and output, xtal1 , xtal2 (fig. 4 ? 7) these pins are connected to an 20.25 mhz crystal oscil- lator is digitally tuned by integrated shunt capacitances. the clk20 and clk5 clock signals are derived from this oscillator. an external clock can be fed into xtal1. in this case clock frequency adjustment must be switched off. pin 53 ? standby supply voltage, vstby in standby mode, only the clock oscillator and the hori- zontal drive circuitry are active. pin 54 ? ccu 5 mhz clock output, clk5 (fig. 4 ? 10) this pin provides a clock frequency for the tv microcon- troller, e.g. a ccu3000 controller. pin 55 ? ground (analog front-end), gnd f pin 56 ? ground (analog signal input), isgnd (fig. 4 ? 8) this is the high quality ground reference for the video input signals. pin 57 ? reference voltage top, vrt (fig. 4 ? 8) via this pin, the reference voltage for the a/d converters is decoupled. the pin is connected with 10 f/47 nf to the signal ground pin. pin 58 ? supply voltage (analog front-end), vsup f pin 59 ? analog video output, vout (fig. 4 ? 6) the analog video signal that is selected for the main (luma, cvbs) adc is output at this pin. an emitter follower is required at this pin. pin 60 ? analog chroma input, cin (fig. 4 ? 9) this pin is connected to the s-vhs chroma signal. a re- sistive divider is used to bias the input signal to the middle of the converter input range. cin can only be connected to the chroma (video 2) a/d converter. the signal must be ac-coupled. pin 61...64 ? analog video input 1 ? 4, vin1 ? 4 (fig. 4 ? 11) these are the analog video inputs. a cvbs or s-vhs luma signal is converted using the luma (video 1) ad converter. the input signal must be ac-coupled. 4.4. pin configuration

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vdp 31xxb preliminary data sheet 52 micronas 4.5. pin circuits fig. 4 ? 3: input pins resq, test v supd gnd d gnd d v supd p n fig. 4 ? 4: output pin clk20 p n v supd n p n fig. 4 ? 5: input/output pins pr[2:0] gnd d fig. 4 ? 6: output pin vout v supf gnd f p + ? n v out v in ? s v ref gnd f v stby p n p n f eclk 0.5m fig. 4 ? 7: input/output pins xtal1, xtal2 v supf p + ? isgnd fig. 4 ? 8: pins vrt , isgnd vrt vref gnd f fig. 4 ? 9: chroma input cin v supf to adc gnd f fig. 4 ? 10: output pin clk5 p n v stby gnd f v supf to adc fig. 4 ? 11: input pins vin1 ? vin4 fig. 4 ? 12: pins sda, scl gnd d
preliminary data sheet vdp 31xxb 53 micronas fig. 4 ? 13: output pins fsy, msy, csy, intlc, port[6:0] p n v supd gndd pp nn v supd bias fig. 4 ? 14: input pins safety, vprot, hflb gndd pp nn v supo bias fig. 4 ? 15: input pins fblin1/2, rin1/2, bin1/2, gin1/2, sense gndo fig. 4 ? 16: input pins color[4:0], hcs, port[6:0] p n v supd gndd v supo bias n n fig. 4 ? 17: analog output pins rout, gout, bout, svmout gndo v stdby gndd fig. 4 ? 18: output pin hout n gndm fig. 4 ? 19: output pins rsw1, rsw2 n v supo pp v supo fig. 4 ? 20: output pins vert, ew gndv + ? int. ref. voltage ref. current v supo gndo vrd xref fig. 4 ? 21: input pins xref, vrd
vdp 31xxb preliminary data sheet 54 micronas 4.6. electrical characteristics 4.6.1. absolute maximum ratings symbol parameter pin no. min. max. unit t a ambient operating temperature ? 0 65 c t s storage temperature ? ? 40 125 c v sup supply voltage, all supply inputs ? 0.3 6 v v i input voltage, all inputs ? 0.3 v sup +0.3 v v o output voltage, all outputs ? 0.3 v sup +0.3 v stresses beyond those listed in the ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions beyond those indicated in the ? recommended operating conditions/characteristics ? of this specification is not implied. exposure to absolute maxi- mum ratings conditions for extended periods may affect device reliability. 4.6.2. recommended operating conditions symbol parameter pin name min. typ. max. unit t a ambient operating temperature ? 0 ? 65 c v sup supply voltages, all supply pins 4.75 5.0 5.25 v f xtal clock frequency xtal1/2 ? 20.25 ? mhz r xref rgb ? dac current defining re- sistor xref 9.5 10 10.5 k ns vdd negative slope of vdd (power down) vsupd 0.2 v/ s 4.6.3. recommended crystal characteristics symbol parameter min. typ. max. unit t a operating ambient temperature 0 ? 65 c f p parallel resonance frequency with load capacitance c l = 13 pf ? 20.250000 ? mhz f p /f p accuracy of adjustment ? ? 20 ppm f p /f p frequency temperature drift ? ? 30 ppm r r series resistance ? ? 25 c 0 shunt capacitance 3 ? 7 pf c 1 motional capacitance 20 ? 30 ff
preliminary data sheet vdp 31xxb 55 micronas recommended crystal characteristics, continued symbol parameter min. typ. max. unit load capacitance recommendation c lext external load capacitance 1) from pins to ground (pin names: xtal1 xtal2) ? 3.3 ? pf dco characteristics 2) c icloadmin effective load capacitance @ min. dco-position, code 0, 3.6 4.3 5 pf c icloadrng effective load capacitance range, dco codes from 0..255 11.7 12.7 13.7 pf 1) remarks on defining the external load capacitance: external capacitors at each crystal pin to ground are required. they are necessary to tune the effective load capacitance of the pcbs to the required load capacitance c l of the crystal. the higher the capacitors, the lower the clock frequency re- sults. the nominal free running frequency should match f p mhz. due to different layouts of customer pcbs the matching capacitor size should be determined in the application. the suggested value is a figure based on experience with various pcb layouts. tunin g condition: c ode dv co re g ister = ? 72 0 tuning condition: code dvco register 7 20 2) remarks on pulling range of dco: the pulling range of the dco is a function of the used crystal and effective load capacitance of the ic (c icload +c loadboard ). the resulting frequency f l with an effective load capacitance of c leff = c icload + c loadboard is 1 + 0.5 * [ c 1 / (c 0 + c leff ) ] f l = f p * ??????????????????????? 1 + 0.5 * [ c 1 / (c 0 + c l ) ] 4.6.4. characteristics at t a = 0 to 65 c, v supd/f/o = 4.75 to 5.25 v, f = 20.25 mhz for min./max. values at t c = 60 c, v supd/f/o = 5 v, f = 20.25 mhz for typical values symbol parameter pin name min. typ. max. unit i vsupf current consumption v supf ? 38 ? ma i vsupd current consumption v supd ? 123 ? ma i vsupo current consumption v supo ? 64 ? ma i vstdby current consumption v stdby ? 3.3 ? ma p tot total power dissipation ? 1145 1200 w il input / output leakage current all i/o pins ? 1 ? 1 a
vdp 31xxb preliminary data sheet 56 micronas 4.6.4.1. 5 mhz clock output symbol parameter pin name min. typ. max. unit test conditions v ol output low voltage clk5 ? ? 0.4 v i ol = 0.4 ma v oh output high voltage 4.0 ? v stdby v ? i ol = 0.9 ma t ot output transition time ? 50 ? ns c load = 30 pf 4.6.4.2. 20 mhz clock input/output, external clock input (xtal1) (see fig. 4 ? 22) symbol parameter pin name min. typ. max. unit test conditions v dcav dc average clk20 v sup /2 ? 0.3 v sup /2 v sup/ 2 + 0.3 v c load = 30 pf v pp v out peak to peak 1.3 1.6 ? v c load = 30 pf t ot output transition time ? ? 18 ns c load = 30 pf v it input trigger level 2.1 2.5 2.9 v only for test purposes f main clock frequency xtal 1 10 20.25 24 mhz v midc main clock input dc voltage 1.0 ? 3.5 v v miac m clock input ac voltage (p ? p) 0.8 ? 2.5 v t mih t mil m clock input high/low ratio 0.9 1.0 1.1 t mihl m clock input high to low transition time ? ? 0.15 f m t milh m clock input low to high transition time ? ? 0.15 f m 0 v v midc v miac t mihl t mih t mi l t milh dvss fig. 4 ? 22: main clock input 4.6.4.3. reset input, test input symbol parameter pin name min. typ. max. unit test conditions v il input low voltage resq test ? ? 1.5 v v ih input high voltage test 3.0 ? ? v
preliminary data sheet vdp 31xxb 57 micronas 4.6.4.4. i 2 c bus interface symbol parameter pin name min. typ. max. unit test conditions v il input low voltage sda, scl ? ? 1.5 v v ih input high voltage 3.0 ? ? v v ol output low voltage ? ? 0.4 0.6 v v i l = 3 ma i l = 6 ma v ih input capacitance ? ? 4 pf t f signal fall time ? ? 300 ns c l = 400 pf t r signal rise time ? ? 300 ns c l = 400 pf f scl clock frequency scl 0 ? 400 khz t low low period of scl 1.3 ? ? s t high high period of scl 0.6 ? ? s t su data data set up time to scl high sda 100 ? ? ns t hd data data hold time to scl low 0 ? 0.9 s 4.6.4.5. io port expander symbol parameter pin name min. typ. max. unit test conditions v il input low voltage port[6:0] ? ? 0.8 v v ih input high voltage 1.5 ? ? v v ol output low voltage ? 0.2 0.4 v i ol = 1.6 ma, strength 6 v oh output high voltage v supd ? 0.4 ? v supd v ? i ol = 1.6ma, strength 6 t od output transition time ? ? 35 ns c load = 70pf i ol output current ? 10 ? 10 ma driver imp. = 0 4.6.4.6. analog video inputs symbol parameter pin name min. typ. max. unit test conditions v vin analog input voltage vin1 vin2 vin3 vin4 cin 0 ? 3.5 v c cp input coupling capacitor video inputs vin1 vin2 vin3 vin4 ? 680 ? nf c cp input coupling capacitor chroma input cin ? 1 ? nf
vdp 31xxb preliminary data sheet 58 micronas 4.6.4.7. analog front-end and adcs symbol parameter pin name min. typ. max. unit test conditions v vrt reference voltage top vrt 2.5 2.6 2.8 v 10 f/10 nf, 1 g probe luma ? path r vin input resistance vin1 vin2 1 m code clamp ? dac = 0 c vin input capacitance vin2 vin3 vin4 4.5 pf v vin full scale input voltage vin4 1.8 2.0 2.2 v pp min. agc gain v vin full scale input voltage 0.5 0.6 0.7 v pp max. agc gain agc agc step width 0.166 db 6-bit resolution = 64 steps f i = 1 mhz dnl agc agc differential non-linearity 0.5 lsb f sig = 1 mhz , ? 2 dbr of max. agc-gain v vincl input clamping level, cvbs 1.0 v binary level = 64 lsb min. agc gain q cl clamping dac resolution ? 16 15 steps 5 bit ? i-dac, bipolar v vin =15v i cl ? lsb input clamping current per step 0.7 1.0 1.3 a v vin = 1 . 5 v dnl icl clamping dac differential non- linearity 0.5 lsb c icl clamping-capacity 220 ? nf coupling-cap. @ inputs chroma ? path r cin input resistance svhs chroma cin vin1 1.4 2.0 2.6 k v cin full scale input voltage, chroma 1.08 1.2 1.32 v pp v cindc input bias level, svhs chroma ? 1.5 ? v binary code for open chroma input 128 dynamic characteristics for all video paths (luma + chroma) bw bandwidth vin1 vin2 10 12.5 mhz ? 2 dbr input signal level xtalk crosstalk, any two video inputs vin2 vin3 vin4 ? 56 db 1 mhz, ? 2 dbr signal level thd total harmonic distortion vin4 cin 50 db 1 mhz, 5 harmonics, ? 2 dbr signal level sinad signal to noise and distortion ratio 45 db 1 mhz, all outputs, ? 2 dbr signal level inl integral non-linearity, 1 lsb code density, dc ram p dnl differential non-linearity 0.8 lsb dc - ramp dg differential gain 3 % ? 12 dbr, 4.4 mhz signal on dc- ram p dp differential phase 1.5 deg ramp
preliminary data sheet vdp 31xxb 59 micronas analog front-end and adcs, continued symbol parameter pin name min. typ. max. unit test conditions analog video output v out output voltage vout 1.7 2.0 2.3 v pp v vin = 1 v pp , agc = 0 db agc vout agc step width, vout 1.333 db 3 bit resolution = 7 steps 3 msb ? s of main agc dnl agc agc differential non-linearity 0.5 lsb 3 msb ? s of main agc v outdc dc-level 1 v clamped to back porch bw v out bandwidth 10 mhz input: ? 2 dbr of main adc range, c l 10 pf thd v out total harmonic distortion ? 45 ? 40 db input: ? 2 dbr of main adc range, c l 10 pf 1 mhz, 5 harmonics c lvout load capacitance ? ? 10 pf i lvout output current ? ? 0.1 ma 4.6.4.8. picture bus input (see fig. 4 ? 23) symbol parameter pin name min. typ. max. unit test conditions v il input low voltage pr[2:0] col ? ? 0.8 v v ih input high voltage col - or[4:0] 1.5 ? ? v t is input setup time 7 ? ? ns t ih input hold time 5 ? ? ns data inputs main clock t is t ih fig. 4 ? 23: picture bus input timing
vdp 31xxb preliminary data sheet 60 micronas 4.6.4.9. intlc, front sync output symbol parameter pin name min. typ. max. unit test conditions v ol output low voltage intlc fsy ? 0.2 0.4 v i ol = 1.6 ma, strength 6 v oh output high voltage v supd ? 0.4 ? v supd v ? i ol = 1.6ma, strength 6 t oh output hold time 6 14 ns c load = 70pf t od output delay time ? ? 35 ns c load = 70pf i ol output current ? 10 ? 10 ma driver imp. = 0 4.6.4.10. main sync output symbol parameter pin name min. typ. max. unit test conditions v ol output low voltage msy ? 0.2 0.4 v i ol = 1.6 ma, strength 6 v oh output high voltage v supd ? 0.4 ? v supd v ? i ol = 1.6ma, strength 6 t oh output hold time 6 14 ns c load = 70pf t od output delay time ? ? 35 ns c load = 70pf i ol output current ? 10 ? 10 ma driver imp. = 0 4.6.4.11. combined sync output symbol parameter pin name min. typ. max. unit test conditions v ol output low voltage csy ? ? 0.4 v i ol = 1.6 ma strength 6 v oh output high voltage v supd ? 0.4 ? v supd v ? i ol = 1.6 ma strength 6 t ot output transition time ? 10 20 ns c load = 30 pf i ol output current ? 10 ? 10 ma driver imp. = 0
preliminary data sheet vdp 31xxb 61 micronas 4.6.4.12. horizontal flyback input symbol parameter pin name min. typ. max. unit test conditions v il input low voltage hflb ? ? 1.8 v v ih input high voltage 2.6 ? ? v v ihst input hysteresis 0.1 ? ? v psrr hf power supply rejection ratio of trigger level 0 db f = 20 mhz psrr mf power supply rejection ratio of trigger level ? 20 db f < 15 khz psrr lf power supply rejection ratio of trigger level ? 40 db f < 100 hz t pid internal delay 12 ns slew rate 500 mv/ns swing 1 v pp 4.6.4.13. horizontal drive output symbol parameter pin name min. typ. max. unit test conditions v ol output low voltage hout ? ? 0.4 v i ol = 10 ma v oh output high voltage (open drain stage) ? ? 5 v external pull-up resistor t of output fall time ? 8 20 ns c load = 30pf i ol output low current ? ? 10 ma 4.6.4.14. vertical protection input symbol parameter pin name min. typ. max. unit test conditions v il input low voltage vprot ? ? 1.8 v v ih input high voltage 2.6 ? ? v v ihst input hysteresis 0.1 ? ? v 4.6.4.15. vertical safety input symbol parameter pin name min. typ. max. unit test conditions v ila input low voltage a safety ? ? 1.8 v v iha input high voltage a 2.6 ? ? v v ilb input low voltage b ? ? 3.1 v v ihb input high voltage b 3.9 ? ? v v ihst input hysteresis a and b 0.1 ? ? v t pid internal delay 100 ns
vdp 31xxb preliminary data sheet 62 micronas 4.6.4.16. vertical and east / west drive output symbol parameter pin name min. typ. max. unit test conditions v ol output voltage low ew vert 0 v r load = 6800 r xref = 10 k v oh output voltage high 2.82 3 3.2 v r load = 6800 r xref = 10 k i dacn full scale dac output current 415 440 465 a vo = 0 v r xref = 10 k psrr power supply rejection ratio 20 ? ? db 4.6.4.17. sense a/d converter input symbol parameter pin name min. typ. max. unit test conditions v i input voltage range sense 0 ? v sup v v i255 input voltage for code 255 1.4 1.54 1.7 v read cutoff blue register c 0 digital output for zero input 16 lsb offset check, read cutoff blue register r i input impedance 1 ? ? m range switch outputs r on output on resistance rsw1 rsw2 ? ? 50 i ol = 10 ma i max maximum current rsw2 ? ? 15 ma i leak leakage current ? ? 600 na rsw high impedance c in input capacitance ? ? 4 pf 4.6.4.18. analog rgb and fb inputs (continued on next page) symbol parameter pin name min. typ. max. unit test conditions v rgbin external rgb inputs voltage range rin gin bin ? 0.3 ? 1.1 v v rgbin nominal rgb input voltage peak-to-peak bin rin2 gin2 bin2 0.5 0.7 1.0 v pp scart spec: 0.7 v 3 db v rgbin rgb inputs voltage for maxi- mum output current bin2 0.44 contrast setting: 511 rgb inputs voltage for maxi- mum output current 0.7 contrast setting: 323 rgb inputs voltage for maxi- mum output current 1.1 contrast setting: 204
preliminary data sheet vdp 31xxb 63 micronas analog rgb and fb inputs, continued symbol parameter pin name min. typ. max. unit test conditions c rgbin external rgb input coupling capacitor rin gin bin 15 nf clamp pulse width bin rin2 gin2 3.1 s c in input capacitance gin2 bin2 ? ? 13 pf i il input leakage current ? 0.5 ? 0.5 a clamping off, v in ? 0.3..3 v v clip rgb input voltage for clipping current 2 v v clamp clamp level at input 40 60 80 mv clamping on v inoff offset level at input ? 10 10 mv extrapolated from v in = 100 mv and 200 mv v inoff offset level match at input ? 10 10 mv extrapolated from v in = 100 mv and 200 mv r clamp clamping-on-resistance 140 ? ? v fbloff fblin low level fblin fblin2 ? ? 0.5 v v fblon fblin high level fblin2 0.9 ? ? v v fbltrig fast blanking trigger level typical 0.7 t pid delay fast blanking to rgb out from midst of fblin-transition to 90% of rgb out -transition 8 15 ns internal rgb = 3.75 ma full scale int. brightness = 0 external brightness = 1.5 ma (full scale) rgbin = 0 v fbloff = 0.4 v v fblon = 1.0 v rise and fall time = 2 ns difference of internal delay to external rgbin delay ? 5 +5 ns switch-over-glitch 0.5 pas switch from 3.75 ma (int) to 1.5 ma (ext) 4.6.4.19. half contrast switch input symbol parameter pin name min. typ. max. unit test conditions v il input low voltage hcs ? ? 0.8 v v ih input high voltage 1.5 ? ? v t hcs delay hcs to rgb out from 50% of hcs-transition to 90% of rgb out -transition 80 120 ns internal rgb = 3.75 ma v hcsl = 0.4 v v hcsh = 1.0 v rise and fall time = 2 ns
vdp 31xxb preliminary data sheet 64 micronas 4.6.4.20. analog rgb outputs, d/a converters symbol parameter pin name min. typ. max. unit test conditions internal rgb signal d/a converter characteristics resolution rout gout ? 10 ? bit i out full scale output current gout bout 3.6 3.75 3.9 ma r ref = 10 k ? i outhc half contrast output current 1.74 1.87 2.0 ma r ref = 10 k ?, i out = 3.75 ma differential nonlinearity 0.5 lsb integral nonlinearity 1 lsb glitch pulse charge 0.5 pas ramp signal, 25 ? output ter- mination t t rise and fall time 3 ns 10% to 90%, 90% to 10% t rhc half contrast rise time 50 75 ns 60% to 90% i out = 3.75ma t fhc half contrast fall time 25 40 ns 90% to 60% i out = 3.75ma intermodulation ? 50 db 2/2.5 mhz full scale signal to noise +50 db signal: 1mhz full scale bandwidth: 10mhz rgb matching r ? g, r ? b, g ? b ? 2 2 % rgbhc half contrast matching r ? g, r ? b, g ? b ? 5 5 % r/b/g crosstalk one channel talks two channels talk ? 46 db passive channel: i out =1.88 ma crosstalk-signal: 1.25 mhz, 375ma pp rgb input crosstalk from external rgb one channel talks two channels talk three channels talk ? 50 ? 50 ? 50 db db db 3 . 75 ma pp internal rgb brightness d/a converter characteristics resolution rout gout 9 bits i br full scale output current relative gout bout 39.2 40 40.8 % ref to max. digital rgb i br full scale output current absolute 1.5 ma i br differential nonlinearity 0.5 lsb i br integral nonlinearity 1 lsb i br match r ? g, r ? b, g ? b ? 2 2 % i br match to digital rgb r ? r, g ? g, b ? b ? 2 2 % external rgb voltage/current converter characteristics resolution rout gout 9 bits i exout full scale output current relative gout bout 96 100 104 % ref. to max. digital rgb v in = 0.7 v pp , contrast = 323 full scale output current absolute 3.75 ma same as digital rgb
preliminary data sheet vdp 31xxb 65 micronas analog rgb outputs, d/a converters, continued symbol parameter pin name min. typ. max. unit test conditions cr contrast adjust range rout gout 16:511 gain match r ? g, r ? b, g ? b gout bout ? 2 2 % measured at rgb outputs v in = 0.7 v, contrast = 323 gain match to rgb ? dacs r ? r, g ? g, b ? b ? 3 3 % measured at rgb outputs v in = 0.7 v, contrast = 323 r/b/g input crosstalk one channel talks two channels talk ? 46 db passive channel: v in = 0.7v, contrast = 323 rgb input crosstalk from internal rgb one channel talks two channels talk three channels talk ? 50 db crosstalk signal: 1.25 mhz, 3.75 ma pp rgb input noise and distortion ? 50 db v in = 0.7 v pp at 1 mhz contrast = 323 bandwidth: 10 mhz rgb input bandwidth ? 3db 10 15 ? mhz v in = 0.7 v pp , contrast = 323 rgb input thd ? 50 ? 40 db db input signal 1 mhz input signal 6 mhz v in = 0.7 v pp contrast = 323 differential nonlinearity of contrast adjust 1.0 lsb v in = 0.44 v integral nonlinearity of contrast adjust 7 lsb v rgbo rgb output voltage ? 1.0 0.3 v referred to v supo rgb output load resistance 100 ? ref. to v supo v outc rgb output compliance ? 1.5 ? 1.3 ? 1.2 v ref. to v supo sum of max. current of rgb ? dacs and max. cur- rent of int. brightness dacs is 2% degraded external rgb brightness d/a converter characteristics resolution rout gout 9 bits i exbr full scale output current relative gout bout 39.2 40 40.8 % ref to max. digital rgb full scale output current absolute 1.5 ma differential nonlinearity 0.5 lsb integral nonlinearity 1 lsb matching r ? g, r ? b, g ? b ? 2 2 % matching to digital rgb r ? r, g ? g, b ? b ? 2 2 %
vdp 31xxb preliminary data sheet 66 micronas analog rgb outputs, d/a converters, continued symbol parameter pin name min. typ. max. unit test conditions rgb output cutoff d/a converter characteristics resolution rout gout 9 bits i cut full scale output current relative gout bout 58.8 60 61.2 % ref to max. digital rgb i cut full scale output current absolute 2.25 ma i cut differential nonlinearity 0.5 lsb i cut integral nonlinearity 1 lsb i cut match to digital rgb r ? r, g ? g, b ? b ? 2 2 % rgb output ultrablack d/a converter characteristics resolution rout gout 1 bits i ub full scale output current relative gout bout 19.6 20 20.4 % ref to max. digital rgb full scale output current absolute 0.75 ma match to digital rgb r ? r, g ? g, b ? b 2 2 % 4.6.4.21. dac reference, beam current safety symbol parameter pin name min. typ. max. unit test conditions v dacref dac-reference voltage vrd/bcs 2.38 2.50 2.67 v dac-reference output resistance vrd/bcs 18 25 32 k v xref dac-reference voltage bias current generation xref 2.25 2.34 2.43 v r ref = 10 k ?, 4.6.4.22. scan velocity modulation output symbol parameter pin name min. typ. max. unit test conditions svm d/a converter characteristics resolution svmout 8 bit i out full scale output current 1.55 1.875 2.25 ma i out differential nonlinearity 0.5 lsb i out integral nonlinearity 1 lsb i out glitch pulse charge 0.5 pas ramp, output line is terminated on both ends with 50 ohms i out rise and fall time 3 nsec 10% to 90%, 90% to 10%
preliminary data sheet vdp 31xxb 67 micronas 5. application circuit
vdp 31xxb preliminary data sheet 68 micronas
preliminary data sheet vdp 31xxb 69 micronas
vdp 31xxb preliminary data sheet 70 micronas
preliminary data sheet vdp 31xxb 71 micronas
vdp 31xxb preliminary data sheet 72 micronas 6. data sheet history 1. preliminary data sheet: ? vdp 31xxb video proces- sor family ? , edition may 15, 1997, 6251-437-1pd. first release of the preliminary data sheet. 2. preliminary data sheet: ? vdp 31xxb video proces- sor family ? , edition sept. 25, 1998, 6251-437-2pd. second release of the preliminary data sheet. major changes: ? section 4.1.: package outline dimensions changed ? section 4.6.: missing values have been defined ? section 5.: application circuit diagram corrected micronas gmbh hans-bunte-strasse 19 d-79108 freiburg (germany) p.o. box 840 d-79008 freiburg (germany) tel. +49-761-517-0 fax +49-761-517-2174 e-mail: docservice@micronas.com internet: www.micronas.com printed in germany order no. 6251-437-2pd all information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. any new issue of this data sheet invalidates previous issues. product availability and delivery are exclusively subject to our respective order confirma- tion form; the same applies to orders based on development samples delivered. by this publication, micronas gmbh does not assume re- sponsibility for patent infringements or other rights of third parties which may result from its use. further, micronas gmbh reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. no part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of micronas gmbh.

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