View L691005_5235674.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1/29 l6910 l6910a may 2005 1 features operating supply voltage from 5v to 12v buses up to 1.3a gate current capability adjustable output voltage n-inverting e/a input available 0.9v 1.5% voltage reference voltage mode pwm control very fast load transient response 0% to 100% duty cycle power good output overvoltage protection hiccup overcurrent protection 200khz internal oscillator oscillator externally adjustable from 50khz to 1mhz soft start and inhibit packages: so-16 & htssop16 2 applications supply for memories and termi- nations computer add-on cards low voltage distributed dc-dc mag-amp replacement 3 description the device is a pwm controller for high performance dc-dc conversion from 3. 3v, 5v and 12v buses. the output voltage is adjustable down to 0.9v; higher voltages can be obtained with an external voltage divider. high peak current gate drivers provide for fast switch- ing to the external power section, and the output current can be in excess of 20a. the device assures protections against load overcur- rent and overvoltage. an internal crowbar is also pro- vided turning on the low side mosfet as long as the over-voltage is detected. in case of over-current de- tection, the soft start capacitor is discharged and the system works in hiccup mode. adjustable step down controller with synchronous rectification figure 2. block diagram monitor protection & ref osc e/a pwm ugate boot boot lgate pgnd gnd vfb ss osc earef r t vref pgood vcc ocset comp 300k + - - + v o v in 5v to 12v d03in1509 rev. 9 fi gure 1. p ac k ages table 1. order codes part number package l6910 so-16 l6910tr so-16 in tape & reel l6910a htssop16 l6910atr htssop16 in tape & reel so-16 (narrow) htssop16 (exposed pad)
l6910 - l6910a 2/29 table 2. absolute maximum ratings table 3. thermal data (*) device soldered on 1 s2p pc board figure 3. pins connection (top view) symbol parameter value unit vcc vcc to gnd, pgnd 15 v v boot - v phase boot voltage 15 v v hgate - v phase 15 v ocset, lgate, phase -0.3 to vcc+0.3 v ss, fb, pgood, vref, earef, rt 7 v comp 6.5 v t j junction temperature range -40 to 150 c t stg storage temperature range -40 to 150 c p tot maximum power dissipation at tamb = 25 c1w symbol parameter so-16 htssop16 htssop16 (*) unit r th j-amb thermal resistance junction to ambient 120 110 50 c/w vref osc ocset ss/inh comp gnd fb earef pgood phase boot hgate pgnd lgate vcc n.c. 1 3 2 4 5 6 7 8 14 13 12 11 10 9 15 16 d03in1510 vref osc ocset ss/inh n.c. fb comp gnd earef pgood hgate phase boot pgnd lgate vcc d03in1511 1 3 2 4 5 6 7 8 14 13 12 11 10 9 15 16
3/29 l6910 - l6910a table 4. pins function so htssop name description 1 1 vref internal 0.9v 1.5% reference is available for external regulators or for the internal error amplifier (connecting this pin to earef) if external reference is not available. a minimum 1nf capacitor is required. if the pin is forced to a voltage lower than 70%, the device enters the hiccup mode. 2 2 osc oscillator switching frequency pin. connecting an external resistor (r t ) from this pin to gnd, the external frequency is increased according to the equation: connecting a resistor (r t ) from this pin to vcc (12v), the switching frequency is reduced according to the equation: if the pin is not connected, the switching frequency is 200khz. the voltage at this pin is fixed at 1.23v. forcing a 50 a current into this pin, the built in oscillator stops to switch. in over voltage condition this pin goes over 3v until that conditon is removed. 3 3 ocset a resistor connected from this pin and the upper mos drain sets the current limit protection. the internal 200 a current generator sinks a constant current through the external resistor. the over-current threshold is due to the following equation: 4 4 ss/inh the soft start time is programmed connecting an external capacitor from this pin and gnd. the internal current generator forces through the capacitor 10 a. this pin can be used to disable the device forcing a voltage lower than 0.4v 5 6 comp this pin is connected to the error amplifier output and is used to compensate the voltage control feedback loop. 6 7 fb this pin is connected to the error amplifier inverting input and is used to compensate the voltage control feedback loop. connected to the output resistor divider, if used, or directly to vout, it manages also over- voltage conditions and the pgood signal 7 8 gnd all the internal references are referred to this pin. connect it to the pcb signal ground. 8 9 earef error amplifier non-inverting input. connect to this pin an external reference (from 0.9v to 3v) for the pwm regulation or short it to vref pin to use the internal reference. if this pin goes under 650mv (typ), the device shuts down. 910 pgood this pin is an open collector output and it is pulled low if the output voltage is not within the above specified thresholds. if not used it may be left floating. 10 11 phase this pin is connected to the source of the upper mosfet and provides the return path for the high side driver. this pin monitors the drop across the upper mosfet for the current limit together with ocset. 11 12 hgate high side gate driver output. 12 13 boot bootstrap capacitor pin. through this pin is supplied the high side driver and the upper mosfet. connect through a capacitor to the phase pin and through a diode to vcc (cathode vs. boot). 13 14 pgnd power ground pin. this pin has to be connected closely to the low side mosfet source in order to reduce the noise injection into the device 14 5 lgate this pin is the lower mosfet gate driver output 15 16 vcc device supply voltage. the operative supply voltage ranges is from 5v to 12v. do not connect v in to a voltage greater than v cc . 16 5 n.c. this pin is not internally bonded. it may be left floating or connected to gnd. f osc,rt 200khz 4.94 10 6 ? r t k ? () ------------------------- + = f osc,rt 200khz 4.306 10 7 ? r t k ? () ---------------------------- - ? = i p i ocset r ocset ? r dson --------------------------------------------- - =
l6910 - l6910a 4/29 table 5. electrical characteristics (v cc = 12v, t j =25c unless otherwise specified) symbol parameter test condition min typ max unit v cc supply current icc vcc supply current osc = open; ss to gnd 4 7 9 ma power-on turn-on vcc threshold vocset = 4v 4.0 4.3 4.6 v turn-off vcc threshold vocset = 4v 3.8 4.1 4.4 v rising v ocset threshold 1.24 1.4 v turn on earef threshold vocset = 4v 650 750 mv soft start and inhibit iss soft start current s.s. current in inh condition ss = 2v ss = 0 to 0.4v 610 35 14 60 a a oscillator f osc initial accuracy osc = open osc = open; t j = 0 to 125 180 170 200 220 230 khz khz f osc,rt total accuracy 16 k ? < r t to gnd < 200 k ? -15 15 % ? vosc ramp amplitude 1.9 v reference v out output voltage accuracy v out = v fb ; v earef = v ref 0.886 0.900 0.913 v v ref reference voltage c ref = 1nf; i ref = 0 to 100 a 0.886 0.900 0.913 v v ref reference voltage c ref = 1nf; t j = 0 to 125 c-2 +2% error amplifier i earef n.i. bias current v earef = 3v 10 a earef input resistance vs. gnd 300 k ? i fb i.i. bias current v fb = 0v to 3v 0.01 0.5 a v cm common mode voltage 0.8 3 v v comp output voltage 0.5 4 v g v open loop voltage gain 70 85 db gbwp gain-bandwidth product 10 mhz sr slew-rate comp = 10pf 10 v/ s gate drivers i hgate high side source current v boot - v phase = 12v v hgate - v phase = 6v 11.3 a r hgate high side sink resistance v boot - v phase = 12v 2 4 ? i lgate low side source current vcc = 12v; v lgate = 6v 0.9 1.1 a r lgate low side sink resistance vcc = 12v 1.5 3 ? output driver dead time phase connected to gnd 90 210 ns protections i ocset ocset current source v ocset = 4v 170 200 230 a over voltage trip (v fb / v earef )v fb rising 117 120 % i osc osc sourcing current v fb > ovp trip 15 30 ma power good upper threshold (v fb / v earef )v fb rising 108 110 112 % lower threshold (v fb / v earef )v fb falling 88 90 92 % hysteresis (v fb / v earef ) upper and lower threshold 2 % v pgood pgood voltage low i pgood = -4ma 0.4 v i pgood output leakage current v pgood = 6v 0.2 1 a
5/29 l6910 - l6910a 4 device description the device is an integrated circuit realized in bcd technology. the controller provides complete con- trol logic and protection for a high performance step-down dc-dc converter. it is designed to drive n channel mosfets in a synchronous-rectified buck topology. the output voltage of the converter can be precisely regulated down to 900mv with a maximum tolerance of 1.5% when the internal reference is used (simply connecting together earef and vref pins). the device allows also using an external reference (0.9v to 3v) for the regulation. the device provides voltage-mode control with fast transient response. it includes a 200khz free-running oscillator that is adjustable from 50khz to 1mhz. the er- ror amplifier features a 10mhz gain-bandwidth product and 10v / s slew rate that permits to realize high converter bandwidth for fast transient performance. the pwm duty cycle can range from 0% to 100%. the device protects against over-current conditions entering in hiccup mode. the device monitors the current by using the r ds(on) of the upper mosfet(s) that eliminates the need for a cur- rent sensing resistor. the device is available in so16 narrow package. 4.1 oscillator the switching frequency is internally fixed to 200khz. the internal oscillator generates the triangular waveform for the pwm charging and discharging with a constant current an internal capacitor. the current delivered to the oscillator is typically 50 a (f sw = 200khz) and may be varied using an external resistor (r t ) connected between osc pin and gnd or v cc . since the osc pin is maintained at fixed voltage (typ. 1.235v), the frequency is var- ied proportionally to the current sunk (forced) from (into) the pin. in particular connecting r t vs. gnd the frequency is increased (current is sunk from the pin), according to the following relationship: connecting r t to v cc = 12v or to v cc = 5v the frequency is reduced (current is forced into the pin), according to the following relationships: v cc = 12v v cc = 5v switching frequency variation vs. rt are repeated in fig. 4. note that forcing a 50 a current into this pin, the device stops switching because no current is delivered to the oscillator. figure 4. f osc,rt 200khz 4.94 10 6 ? r t k ? () ------------------------- + = f osc,rt 200khz 4.306 10 7 ? r t k ? () ---------------------------- - ? = f osc,rt 200khz 15 10 6 ? r t k ? () --------------------- ? = 10 100 1000 frequency [khz] 10 100 1000 10000 resistance [kohm] rt to gnd rt to vcc=12v rt to vcc=5v
l6910 - l6910a 6/29 4.2 reference a precise 1.5% 0.9v reference is available. this reference must be filtered with 1nf ceramic capacitor to avoid instability in the internal linear regulator. it is able to deliver up to 100 a and may be used as reference for the device regulation and also for other devices. if forced under 70% of its nominal value, the device enters in hic- cup mode until this condition is removed. through the earef pin the reference for the regulation is taken. this pin directly connects the non-inverting input of the error amplifier. an external reference (or the internal 0.9v 1.5%) may be used. the input for this pin can range from 0.9v to 3v. it has an internal pull-down (300k ? resistor) that forces the device shutdown if no reference is connected (pin floating). however the device is shut down if the voltage on the earef pin is lower than 650mv (typ). 4.3 soft start at start-up a ramp is generated charging the external capacitor c ss with an internal current generator. the initial value for this current is of 35 a and speeds-up the charge of the capacitor up to 0.5v. after that it becames 10 a until the final charge value of approximatively 4v. when the voltage across the soft start capacitor (v ss ) reaches 0.5v the lower power mos is turned on to dis- charge the output capacitor. as v ss reaches 1.1v (i.e. the oscillator triangular wave inferior limit) also the upper mos begins to switch and the output voltage starts to increase. no switching activity is observable if ss is kept lower than 0.5v and both mosfets are off. if vcc and ocset pins are not above their own turn-on thresholds and v earef is not above 650mv, the soft- start will not take place, and the relative pin is internal ly shorted to gnd. during normal operation, if any under- voltage is detected on one of the two supplies, the ss pin is internally shorted to gnd and so the ss capacitor is rapidly discharged. figure 5. soft start (with reference present) 4.4 driver section the driver capability on the high and low side drivers allows using different types of power mos (also multiple mos to reduce the r dson ), maintaining fast switching transition. the low-side mos driver is supplied directly by vcc while the high-side driver is supplied by the boot pin. adaptative dead time control is implemented to prevent cross-conduction and allow to use several kinds of mos- fets. the upper mos turn-on is avoided if the lower gate is over about 200mv while the lower mos turn-on is timing diagram vcc turn-on threshold vin turn-on threshold 0.5v 1v vcc vin vss lgate vout to gnd acquisition: ch1 = phase; ch2 = v out ; ch3 = pgood; ch4 = v ss
7/29 l6910 - l6910a avoided if the phase pin is over about 500mv. the lower mos is in any case turned-on after 200ns from the high side turn-off. the peak current is shown for both the upper (fig. 6) and the lower (fig. 7) driver at 5v and 12v. a 3.3nf capac- itive load has been used in these measurements. for the lower driver, the source peak current is 1.1a @ v cc = 12v and 500ma @ v cc = 5v, and the sink peak current is 1.3a @ v cc = 12v and 500ma @ v cc = 5v. similarly, for the upper driver, the source peak current is 1.3a @ vboot-vphase = 12v and 600ma @ vboot- vphase = 5v, and the sink peak current is 1.3a @ vboot-vphase =12v and 550ma @ vboot-vphase = 5v. figure 6. high side driver peak current. vboot-vphase = 12v (right) vboot-vphase = 5v (left) figure 7. low side driver peak current. v cc = 12v (right) v cc = 5v (left) 4.5 monitoring and protections the output voltage is monitored by means of pin fb. if it is not within 10% (typ.) of the programmed value, the powergood output is forced low. the device provides overvoltage protection, when the voltage sensed on pin fb reaches a value 17% (typ.) greater than the reference the osc pin is forced high (3v typ.) and the lower driver is turned on as long as the over-voltage is detected. ch1 = high side gate ch4 = gate current ch1 = low side gate ch4 = gate current
l6910 - l6910a 8/29 overcurrent protection is performed by the device compar ing the drop across the high side mos, due to the r dson , with the voltage across the external resistor (r ocs ) connected between the ocset pin and drain of the upper mos. thus the overcurrent threshold (i p ) can be calculated with the following relationship: where the typical value of i ocs is 200 a. to calculate the r ocs value it must be considered the maximum r dson (also the variation with temperature) and the minimum value of i ocs . to avoid undesirable trigger of overcurrent protection this relationship must be satisfied: where ? i is the inductance ripple current and i outmax is the maximum output current. in case of over current detectionthe soft start capacitor is discharged with constant current (10 a typ.) and when the ss pin reaches 0.5v the soft start phase is restarted. during the soft start the over-current protection is al- ways active and if such kind of event occurs, the devic e turns off both mosfets, and the ss capacitor is dis- charged again (after reaching the upper threshold of about 4v). the system is now working in hiccup mode, as shown in figure 8. after removing the cause of the ove r-current, the device restart working normally without power supplies turn off and on. i p r ocs i ocs ? r dson --------------------------------- = i p i outmax i ? 2 ---- - + i peak = figure 8. hiccup mode figure 9. inductor ripple current vs. vout ch1 = ss; ch4 = inductor current 0 1 2 3 4 5 6 7 8 9 0.5 1.5 2.5 3.5 output voltage [v] inductor ripple [a] l=3 h, vin=12v l=2 h, vin=12v l=1.5 12 2 h, vin=5v l=1.5 h, vin=5v l=3 4.6 inductor design the inductance value is defined by a compromise between the transient response time, the efficiency, the cost and the size. the inductor has to be calculated to sustain the output and the input voltage variation to maintain the ripple current ? i l between 20% and 30% of the maximum output current. the inductance value can be cal- culated with this relationship: where f sw is the switching frequency, v in is the input voltage and v out is the output voltage. figure 9 shows the ripple current vs. the output voltage for different values of the inductor, with v in = 5v and v in = 12v. increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter response time to a load transient. if the compensation network is well designed, the device is able to open or close the duty cycle up to 100% or down to 0%. the response time is now the time required by the inductor to change its current from initial to final value. since the inductor has not finished its charging time, the output cur- rent is supplied by the output capacitors. minimizing t he response time can minimize the output capacitance required. l v in v out ? f sw i l ? ? ------------------------------ v out v in -------------- - ? =
9/29 l6910 - l6910a the response time to a load transient is different for the application or the removal of the load: if during the ap- plication of the load the inductor is charged by a voltage equal to the difference between the input and the output voltage, during the removal it is discharged only by the output voltage. the following expressions give approx- imate response time for ? i load transient in case of enough fast compensation network response: the worst condition depends on the input voltage avai lable and the output voltage selected. anyway the worst case is the response time after removal of the load with the minimum output voltage programmed and the max- imum input voltage available. 4.7 output capacitor the output capacitor is a basic component for the fast re sponse of the power supply. in fact, during load tran- sient, for first few microseconds they supply the current to the load. the controller recognizes immediately the load transient and sets the duty cycle at 100%, but the curr ent slope is limited by the inductor value. the output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the esl): a minimum capacitor value is required to sustain the current during the load transient without discharge it. the voltage drop due to the output capacitor discharge is given by the following equation: where d max is the maximum duty cycle value that is 100%. th e lower is the esr, the lower is the output drop during load transient and the lower is the output voltage static ripple. 4.8 input capacitor the input capacitor has to sustain the ripple current produced during the on time of the upper mos, so it must have a low esr to minimize the losses. the rms value of this ripple is: where d is the duty cycle. the equation reaches its maximu m value with d = 0.5. the losses in worst case are: 4.9 compensation network design the control loop is a voltage mode (figure 10). the output voltage is regulated to the input reference voltage level (earef). the error amplifier output v comp is then compared with the oscillator triangular wave to provide a pulse-width modulated (pwm) wave with an amplitude of v in at the phase node. this wave is filtered by the output filter. the modulator transfer function is the small-signal transfer function of v out /v comp . this function has a double pole at frequency f lc depending on the l-c out resonance and a zero at f esr depending on the output capacitor esr. the dc gain of the modulator is simply the input voltage v in divided by the peak-to-peak oscillator voltage ? v osc . t application li ? ? v in v out ? ------------------------------ t removal li ? ? v out -------------- - == v out ? i out ? esr ? = v out ? i out 2 ? l ? 2c out v inmin d max v out ? ? () ?? --------------------------------------------------------------------------------------------- = i rms i out d1d ? () ? = p esr i rms 2 ? =
l6910 - l6910a 10/29 figure 10. compensation network the compensation network consists in the internal error amplifier and the impedance networks z in (r3, r4 and c20) and z fb (r5, c18 and c19). the compensation network has to provide a closed loop transfer function with the highest 0db crossing frequency to have fast response (but always lower than fsw/10) and the highest gain in dc conditions to minimize the load regulation. a stable control loop has a gain crossing with -20db/decade slope and a phase margin greater than 45. include worst-case component variations when determining phase margin. to locate poles and zeroes of the compensation networks, the following suggestions may be used: modulator singularity frequencies: compensation network singularity frequency: ? put the gain r5/r3 in order to obtain the desired converter bandwidth; ?place z1 before the output filter resonance lc ; ?place z2 at the output filter resonance lc ; ?place p1 at the output capacitor esr zero esr ; ?place p2 at one half of the switching frequency; ? check the loop gain considering the error amplifier open loop gain. + - l pwm comparator esr c out v out v comp earef ? v osc v in r3 c19 r5 c18 c20 r4 d03in1512 lc 1 lc out ? --------------------------- esr 1 esr c out ? -------------------------------- - == p1 1 r5 c18 c19 ? c18 c19 + ---------------------------- - ?? ?? ? ----------------------------------------------- p2 1 r4 c20 ? ----------------------- - == z1 1 r5 c19 ? ----------------------- - z2 1 r3 r4 + () c20 ? ------------------------------------------- ==
11/29 l6910 - l6910a figure 11. asymptotic bode plot of converter's gain 5 15a demo board description the demo board shows the operation of the device in a g eneral purpose application. this evaluation board al- lows voltage adjustability from 0.9v to 5v through the sw itches s2-s5 according to the reported table when the internal 0.9v reference is used (g1 closed). output cu rrent in excess of 20a can be reached dependently on the kind of mosfet used: up to three so8 mosfet ma y be used for both high side and low side switches. external reference may be used for the regulation simply leaving open g1 and the switches s2-s5. the device may also be disabled with the switch s1. the v cc input rail supplies the device while the power conversion starts from the v in input rail. the device is also able to operate with a single supply voltage; in this case the jumper g2 has to be closed and a 5v to 12v input can be directly connected to the v in input. the four layers demo board's copper thickness is of 70 m in order to minimize conduction losses considering the high current that the circuit is able to deliver.the pgood signal is used as a logic level and it's been pulled up to v in because there's no other appropriate voltage available on the demo board. in case of input voltage higher than 7v (pgood pin maximum absolute rating) a 5v reference is required. figure 12 shows the demo board's schematic circuit figure 12. 15a demo board schematic error am p lifier 1 2 p1 p2 esr r5/r3 modulator gain compensation network gain error amplifier closed loop gain lc db ugate phase lgate pgnd pgood vfb ss osc earef vref r1 gnd v cc boot c17 c16 c21 c15 vin gndin vcc gndcc refin gndrefin +vref gndref r7 r6 c13 q1-3 q4-6 d2 c14 g2 ocset comp 5 12 15 7 8 1 4 2 13 14 10 11 9 3 6 s2 s1 s4 s5 s3 r10 sr12 sr13 r11 v out pwrgd gndout l2 l1 d1 c1-c3 c4- 11 d03in1513 g1 f1 c19 c18 r5 r3 r8 r2 r9 r4 c20 c22 c12 v out s2 open open open open on open open open on open open open on on open open open open on open open open open on open open on on s3 s4 s5 0.9 1.2 1.5 1.8 2.5 3.3 5.0
l6910 - l6910a 12/29 table 6. part list table 7. other inductor manufacturer reference description manufacturer r1 n.c neohm r2 10k 5% 125mw neohm smd 0805 r3 4.7k 5% 125mw neohm smd 0805 r4 1kohm 5% 125mw neohm smd 0805 r5 2.7k 5% 125mw neohm smd 0805 r6 10ohm 5% 125mw neohm smd 0805 r7 510ohm 5% 125mw neohm smd 0805 r8 n.c r9 0 ohm smd 0805 r10 14k 5% 125mw neohm smd 0805 r11 6.98k 5% 125mw neohm smd 0805 r12 2.61k 5% 125mw neohm smd 0805 r13 1.74k 5 5% 125mw neohm smd 0805 c1, c3 100 f - 20v oscon 20sa100m radial 10x10.5 c9, c10 330 f - 6.3v poscap 6tpb330m smd7343 c12, c13, c15, c21 100nf kemet smd0805 c14 1nf kemet smd0805 c16 100nf kemet c17 4.7 f - 16v aux sma6032 c18 1.5nf kemet smd0805 c19 15nf kemet smd0805 c20 47nf kemet smd0805 c22 n.c l1 short l2 3 h (t50-52b core, 7t awg15) micrometals q2,q3,q4,q6 sts11nf30l st so8 d1 1n4148 sot23 d2 stps2l25u st smb u1 device l6910 st so16narrow f1 short switch dip switch 6 pos. manufacturer series inductor value ( h) saturation current (a) wrth elektronik 744318 1.8 to 2.7 16 to 20 panasonic etqp6f1r8fa 1.8 20 sumida cdep134-2r7mc-h 2.7 15
13/29 l6910 - l6910a figure 13. pcb and components layouts figure 14. pcb and components layouts figure 15. efficiency vs output current component side internal signal gnd layer internal power gnd layer solder side 75 80 85 90 95 100 1357911131517 vo=1.2v vo=1.5v vo=1.8v vo=2.5v vin=vcc=5v fsw=200khz vo=3.3v vo=0.9v efficiency (%) 75 80 85 90 95 100 1357911131517 vo=1.2v vo=1.5v vo=1.8v vo=2.5v vin=vcc=5v fsw=200khz vo=3.3v vo=0.9v efficiency (%) output current (a)
l6910 - l6910a 14/29 figure 16. efficiency vs output current 6 components selection 6.1 inductor selection to select the right inductor value, the application c onditions must be fixed. for example we can consider: vin=12v vout =3.3v iout=15a considering a ripple of approximately 25% to 30% of iout, the inductor value will be l=3 h. an iron powder core (to50-52b) with 7 windings has been chosen. 6.2 output capacitors 2 poscap capacitors, model 6tpb330m, have been chosen, with a maximum ers equal to 40m ? each. therefore, the resultant esr is of 20m ? . considering a current ripple of 4a, the output voltage ripple is: ? vout = 4 0.02 = 80mv 6.3 input capacitors for i out = 15a and d = 0.5 (worst case for input current ripple), the rms current of the input capacitor is equal to 7.5a. two oscon electrolytic capacitors 6sp680m, with a maximum esr equal to 13m ? , have been chosen to sus- tain the ripple. therefore, the resultant esr is equal to 13m ? /2 = 6.5m ? . the losses, in worst case, are: p = esr i 2 rms = 366mw 6.4 over-current protection the current limit can be set to approximately 20a. substituting the demo board parameters in the relation- ship reported in the relative section, (i oscmin =170 a; ip = 20a; r dsonmax = 9m ? / 2=4.5m ?) it results that r ocs = 510 ? output current (a) efficiency (%) 50 55 60 65 70 75 80 85 90 95 100 1357911131517 vin=vcc=12v fsw.=200khz vo=1.2v vo=1.8v vo=3.3v vo=5v vo=0.9v vin=vcc=12v fsw.=200khz vo=1.2v vo=1.8v vo=3.3v vo=5v vo=0.9v vo=1.5v vo=2.5v vo=1.5v vo=2.5v output current (a)
15/29 l6910 - l6910a 6.5 application suggestions for higher currents for higher output currents, up to 20a, the following confi guration can be used (with reference to the demo board schematic): q1,q2,q3: sts11nf30l q4,q5,q6: sts17nf3ll l: 2.5 h magnetic 77121a7 core 7t 2x awg16 in these conditions, the following performance have been achieved: table 8. for currents higher than 20a, bigger mosfets should be selected (e.g. sts25nh3ll) both for the high side and low side (depending on the duty cycle and input voltage). 7 6a demo board description a compact demo board has been realized to manage currents in the range of 5a-6a . the external power mosfets are included in a single so8 package to save space and increase power density. two separate rails are provided, for v cc and v in . they can be connected together by shorting the jumper j1. the pgood signal is used as a logic level and it's been pulled up to v in because there's no other appropriate voltage available on the demo board. in case of input voltage higher than 7v (pgood pin maximum ab- solute rating) a 5v reference is required. figure 17. 6a demo board schematic v in (v) v out (v) i out (a) (%) v in (v) v out (v) i out (a) (%) 5 1.2 20 81 12 1.2 20 80 5 1.5 20 83 12 1.5 20 83 5 1.8 20 85 12 1.8 20 85 5 2.5 20 89 12 2.5 20 88 5 3.3 20 91 12 3.3 20 91 12 5 20 93 l1 r7 c1- c2 c7 c3-4 q1/q1 d2 13 14 10 11 3 1 u1 l6910 vin vout pwrgd 6 12 5 4 2 15 7 9 vcc gnd vref ss osc ocset ugate phase lgate pgnd pgood vfb comp c19 r10 c9 c6 d1 gndout gndin r2 c8 c5 r6 c18 8 gndcc vcc r5 j1 r3 r4 c20 earef boot r1 c10 r11 q2/q1 r8 r9 l1 r7 c1- c2 c7 c3-4 q1/q1 d2 13 14 10 11 3 1 u1 l6910 vin vout pwrgd 6 12 5 4 2 15 7 9 vcc gnd vref ss osc ocset ugate phase lgate pgnd pgood vfb comp c19 r10 c9 c9 c6 d1 gndout gndin gndin r2 c8 c5 r6 c18 8 gndcc vcc r5 j1 r3 r4 r4 c20 c20 earef boot r1 c10 r11 q2/q1 r8 r9
l6910 - l6910a 16/29 table 9. part list table 10. other inductor manufacturer reference description manufacturer resistor r1 2k7 ohm 0805 5% 125mw neohm (vout = 2.5v) 1k8 ohm 0805 5% 125mw neohm (vout = 3.3v) 1k ohm 0805 5% 125mw neohm (vout = 5v) r2 10k 5% 125mw neohm smd 0805 r3 4k7 5% 125mw neohm smd 0805 r4 4k7 5% 125mw neohm smd 0805 r5 2k7 5% 125mw neohm smd 0805 r6 10 ohm 5% 125mw neohm smd 0805 r7 680 ohm 5% 125mw neohm smd 0805 r8 r9 2.2 ohm 5% 125mw neohm smd 0805 r10 n.c r11 n.c capacitors c1,c2 10 f 25v tokin c34y5u1e106zte12 c3,c4 100 f - 6.3v poscap 6tpb100m smd7343 c5,c6,c9 100nf kemet smd0805 c7,c8 1nf kemet smd0805 c10 n.c c18 1.5nf kemet smd0805 c19 15nf kemet smd0805 c20 47nf kemet smd0805 magnetics l1 7 h (t50-52b core, 12t awg 21) micrometals transistor q1 sts8dnf3ll st diodes d1 1n4148 sot23 d2 stps2l25u st smb device u1 device l6910 st so16narrow manufacturer series inductor value ( h) saturation current (a) wrth elektronik 744 382 4.8 to 5.8 7.5 to 8 panasonic etqp6f 4.6 to 6.4 9.3 to 7.9 sumida cdep134-h 6 to 8 7.2 to 9.6 coilcraft do3316p-472hc 4.7 5.4 do3340p 10 to 22 8 to 5.5 coiltronics dr125-8r2 8.2 7.8
17/29 l6910 - l6910a figure 18. pcb and components layouts 7.1 compact demo board performances figures 19, 20 show the measured efficienc y versus load current for different values of output voltage. the mea- sure has been done at 5v and 12v input. output voltage has been changed modifying the value of r1 in the demo board as reported in the part list. figure 19. efficiency vs. output current figure 20. efficiency vs. output current component side solder side 70 75 80 85 90 95 100 12345678 vin=vcc=5v fsw=200khz vo=1.2v vo=1.5v vo=1.8v vo=3.3v vo=2.5v output current (a) efficiency (%) 70 75 80 85 90 95 100 12345678 vin=vcc=5v fsw=200khz vo=1.2v vo=1.5v vo=1.8v vo=3.3v vo=2.5v output current (a) efficiency (%) 70 75 80 85 90 95 12345678 70 75 80 85 90 95 12345678 vo=1.2v vo=1.5v vo=1.8v vo=2.5v vo=3.3v vo=5v efficiency (%) output current (a) vin=vcc=12v fsw=200khz vo=1.2v vo=1.5v vo=1.8v vo=2.5v vo=3.3v vo=5v efficiency (%) output current (a) vin=vcc=12v fsw=200khz
l6910 - l6910a 18/29 8 15a htssop16 demo board description a specific demo board has been realized for the htssop16 package. the features are the same of the 15a demo board previously described but thermal performanc e are improved. the pgood signal is used as a logic level and it's been pulled up to v in because there's no other appropriate voltage available on the demo board. in case of input voltage higher than 7v (pgood pi n maximum absolute rating) a 5v reference is re- quired . figure 21. 15a htssop16 demo board schematic table 11. part list reference description manufacturer r1 n.c r2 10k 5% 125mw neohm smd 0805 r3 4.7k 5% 125mw neohm smd 0805 r4 1k ohm 5% 125mw neohm smd 0805 r5 2.7k 5% 125mw neohm smd 0805 r6 10 ohm 5% 125mw neohm smd 0805 r7 560 ohm 5% 125mw neohm smd 0805 r8 n.c r9 0 ohm neohm smd 0805 r10 14k 5% 125mw neohm smd 0805 r11 6.98k 5% 125mw neohm smd 0805 r12 2.61k 5% 125mw neohm smd 0805 r13 1.74k 5% 125mw neohm smd 0805 r14 0 ohm neohm smd 0805 r15 0 ohm neohm smd 0805 r16 n.c c1,c3 100uf 20v oscon 20sa100m radial 10x10.5 c9,c10 330uf - 6.3v poscap 6tpb330m smd7343 l2 r7 c1- c3 c14 c4 q4-6 q1-3 d2 c17 f1 14 15 11 12 3 1 u1 l6910a vin vout pwrgd 7 13 6 4 2 16 8 10 vcc gnd vref ss osc ocset ugate phase lgate pgnd pgood vfb comp c19 r1 c21 c13 d1 -11 gndin gndout r2 gndref +vref c12 gndref ref in c16 c15 r6 c18 9 l1 gndcc vcc r5 g2 r8 r3 r4 r9 c22 c20 s1 s2 s3 s4 s5 r10 r11 r12 r13 earef boot vout s2 s3 s4 s5 0.9 1.2 1.5 1.8 2.5 3.3 5.0 open open on open open open open open open open open open open open open open open on on on open open on on on on open open r14 r15 r16 c23
19/29 l6910 - l6910a table 12. other inductor manufacturer figure 22. pcb and components layout reference description manufacturer c12,c13, c15,c21,c16 100nf kemet smd0805 c14 1nf kemet smd0805 c17 4.7uf - 16v avx sma6032 c18 1.5nf kemet smd0805 c19 15nf kemet smd0805 c20 47nf kemet smd0805 c22 n.c c23 n.c l1 short l2 3uh t50-52b core, 7t awg15 micrometals q2,q3,q4,q6 sts11nf30l st so8 d1 1n4148 sot23 d2 stps340u st smb u1 device l6910 st htssop16 f1 short switch dip switch manufacturer series inductor value ( h) saturation current (a) wrth elektronik 744318 1.8 to 2.7 16 to 20 panasonic etqp6f1r8fa 1.8 20 sumida cdep134-2r7mc-h 2.7 15 table 11. part list (continued) component side internal power gnd layer internal signal gnd layer solder side
l6910 - l6910a 20/29 9 application idea 1: ddr memory and termination supply double data rate (ddr) memories require a particular power management architecture. this is due to the fact that the trace between the driving chipset and the memory input must be terminated with resistors. since the chipset driving the memory has a push pull output buffer, the termination voltage must be capable of sourcing and sinking current. moreover, the termination voltage must be equal to one half of the memory supply (the input of the memory is a differential stage requiring a reference bias midpoint) and in tracking with it. for ddri the memory supply is 2.5v and the termination voltage is 1.25v while, for ddrii, the memory supply is 1.8v and the termination voltage is 0.9v. fig. 23 shows a complete ddri memory and termination power supply realized by using 2 x l6910. the 2.5v section is powering the memory while the 1.25v section is providing the termination voltage. the tracking between the two sections is realized by prov iding the earef voltage of the 1.25v section through a resistor divider connected to the 2.5v. figure 23. application idea : ddr memory supply the current required by the memory and the termination supply, depends on the memory type and size. the figure 24, 25 shows the efficiency of the l6910 for the termination section of the application shown in fig. 23, in sink and source mode. the figures show the effici ency values also when the input voltage is coming di- rectly from the 12v rail. vref 13 14 10 11 3 1 6 12 5 4 2 15 7 9 vcc gnd vref ss osc ocset ugate phase lgate pgnd pgood vfb comp vin 12v 8 earef boot 13 14 10 11 3 1 pwrgd 6 12 5 4 2 15 7 9 vcc gnd vref ss osc ocset ugate phase lgate pgnd pgood vfb comp 8 earef boot sts8dnf3ll sts11nf3ll r + - v ddq 2.5v@15a v tt 1.25v@ - 5a vin 12v u1 l6910 u2 l6910 pwrgd r termination network bus sts11nf3ll ddr memory chipset + vref 13 14 10 11 3 1 6 12 5 4 2 15 7 9 vcc gnd vref ss osc ocset ugate phase lgate pgnd pgood vfb comp vin 12v 8 earef boot 13 14 10 11 3 1 pwrgd 6 12 5 4 2 15 7 9 vcc gnd vref ss osc ocset ugate phase lgate pgnd pgood vfb comp 8 earef boot sts8dnf3ll sts11nf3ll r + - v ddq 2.5v@15a v tt 1.25v@ - 5a vin 12v u1 l6910 u2 l6910 pwrgd r termination network bus sts11nf3ll ddr memory chipset + vref 13 14 10 11 3 1 6 12 5 4 2 15 7 9 vcc gnd vref ss osc ocset ugate phase lgate pgnd pgood vfb comp vin 12v 8 earef boot 13 14 10 11 3 1 pwrgd 6 12 5 4 2 15 7 9 vcc gnd vref ss osc ocset ugate phase lgate pgnd pgood vfb comp 8 earef boot sts8dnf3ll sts11nf3ll r + - v ddq 2.5v@15a v tt 1.25v@ - 5a vin 12v u1 l6910 u2 l6910 pwrgd r termination network bus sts11nf3ll ddr memory chipset +
21/29 l6910 - l6910a figure 24. efficiency vs output current source mode figure 25. efficiency vs output current sink mode for very big systems (e.g. servers), the ddr memory termination can require much higher currents, in the range of 10a-15a and more. figures 26, 27 and 28, 29 show the efficiency of the l6910 in sink and source mode, up to 17a both for ddri and ddrii memories.the measurements have been re- alized with the 15a demo board. (see pag.11 ) figure 26. efficiency vs output current sink mode figure 27. efficiency vs output current sink mode figure 28. efficiency vs output current source mode figure 29. efficiency vs output current source mode 8 60 65 70 75 80 85 90 95 1234567 efficiency (%) output current (a) vin=12v vin=2.5v vcc=12v vout=1.25v fsw=200khz 8 60 65 70 75 80 85 90 95 1234567 8 60 65 70 75 80 85 90 95 1234567 efficiency (%) output current (a) vin=12v vin=2.5v vcc=12v vout=1.25v fsw=200khz 60 65 70 75 80 85 90 95 12345678 vin=12v vin=2.5v vcc=12v vout=1.25v fsw=200khz output current (a) efficiency (%) 60 65 70 75 80 85 90 95 12345678 vin=12v vin=2.5v vcc=12v vout=1.25v fsw=200khz output current (a) efficiency (%) vin=12v vin=2.5v vcc=12v vout=1.25v fsw=200khz output current (a) efficiency (%) vin=12v 50 60 70 80 90 100 1357911131517 vin=2.5v vin=12v vcc=12v vout=1.25v fsw=200khz efficiency (%) output current (a) vin=12v 50 60 70 80 90 100 1357911131517 vin=2.5v vin=12v vcc=12v vout=1.25v fsw=200khz efficiency (%) output current (a) 50 60 70 80 90 100 1357911131517 vin=2.5v vin=12v vcc=12v vout=1.25v fsw=200khz efficiency (%) output current (a) vin=2.5v vin=12v vcc=12v vout=1.25v fsw=200khz efficiency (%) output current (a) 40 50 60 70 80 90 100 1 3 5 7 9 11 13 15 17 vin=12v vin=1.8v vcc=12v vout=0.9v fsw=200khz output current (a) efficiency (%) 40 50 60 70 80 90 100 1 3 5 7 9 11 13 15 17 vin=12v vin=1.8v vcc=12v vout=0.9v fsw=200khz 40 50 60 70 80 90 100 1 3 5 7 9 11 13 15 17 40 50 60 70 80 90 100 1 3 5 7 9 11 13 15 17 vin=12v vin=1.8v vcc=12v vout=0.9v fsw=200khz output current (a) efficiency (%) 50 60 70 80 90 100 1357911131517 vout=12v vcc=12v vout=1.25v fsw=200khz vout=2.5v efficiency (%) output current (a) 50 60 70 80 90 100 1357911131517 vout=12v vcc=12v vout=1.25v fsw=200khz vout=2.5v efficiency (%) output current (a) 50 60 70 80 90 100 1357911131517 vin=12v vout=0.9v fsw=200khz vin=12v vin=1.8v efficiency (%) output current (a) 50 60 70 80 90 100 1357911131517 vin=12v vout=0.9v fsw=200khz vin=12v vin=1.8v 50 60 70 80 90 100 1357911131517 vin=12v vout=0.9v fsw=200khz vin=12v vin=1.8v efficiency (%) output current (a)
l6910 - l6910a 22/29 10 application idea 2: positive buck-boost regulator 3v to 13.2v input / 5v 2.5a output in some applications the input voltage changes in a very wide range while the output must be regulated to a fixed value. in this case a buck-boost topology can be required in order to keep the output voltage in regulation. the schematic below shows how to implement a buck-boost regulating 5v at the output from both 3.3v and 5v and 12v input buses. in a buck-boost topology the current is delivered to the output during the off phase only. so, for a given current limit, the maximum output current depends strongly on the duty cycle. assuming a 100% efficiency and neglect- ing the current ripple across the inductor, the relati onship betweent the current limit and the maximum output current is the following: where i lim is the current limit and d is the duty cycle of the application. the worst case is with d max . since, in a buck-boost application, d is given by the following formula: the worst case is with v inmin . obviously, since the efficiency is lower than 100% and the ripple is usually not negligible, the maximum output current is always lower than the value calculated in the above formula figure 30. positive buck-boost regulator 3v to 13.2v input / 5v 2.5a output circuit i omax i lim 1d ? () ? = d v o v in v o + ----------------------- = l1 r1 c1- c2 c3 q2 q2 q1 d2 c6 13 14 10 11 3 1 u1 l6910/a vin (3.3v-5v-12v buses) vout ( 5v 2.5a ) 6 12 5 4 2 15 7 9 vcc gnd vref ss osc ocset ugate phase lgate pgnd pgood vfb comp c9 c8 c4 d1 -14 c13 -14 c13 gndout r2 c12 c7 c7 c5 r7 c10 8 gndin gndin vcc (12v bus) r5 g1 r6 earef boot q3 q4 r3 r4 c11 gndcc gndcc
23/29 l6910 - l6910a table 13. part list figure 31. efficiency vs. output current reference description manufacturer r1 910 ohm 5% 125mw neohm smd 0805 r2 10k 5% 125mw neohm smd 0805 r3 4.7k 5% 125mw neohm smd 0805 r4 1k 5% 125mw neohm smd 0805 r5 2.7k 5% 125mw neohm smd 0805 r6 1k1 neohm smd 0805 r7 10 ohm 125mw neohm smd 0805 c1,c2 100 f - 20v oscon 20sa100m radial 10x10.5 c13,c14 330 f - 6.3v poscap 6tpb330m smd7343 c12,c5,c8 100nf kemet smd0805 c3 1nf kemet smd0805 c4 470nf kemet smd0805 c6 4.7 f - 16v aux sma6032 c7 100nf kemet c9 15nf kemet smd0805 c10 1.5nf kemet smd0805 c11 47nf kemet smd0805 g1 open jumper l1 2.5 h (77121a7 core, double winding 7 awg16) magnetics q1,q2,q3 sts11nf30l st so8 q4 sts5p30l st so8 d1 1n4148 sot23 d2 stps3l25u (stps340u) st smb (d0144) u1 device l6910 st so16 narrow 65 70 75 80 85 90 1 1.5 2 2.5 3 3.5 output current (a) efficiency (%) vcc=5v vout=5v fsw=200khz vin=12v vin=5v vin=3.3v 65 70 75 80 85 90 1 1.5 2 2.5 3 3.5 output current (a) efficiency (%) vcc=5v vout=5v fsw=200khz vin=12v vin=5v vin=3.3v
l6910 - l6910a 24/29 11 application idea 3: buck-boost regulator 3v to 5.5v input/-5v 3a output in applications where a negative output voltage is required, a standard buck-boost topology can be implement- ed. the considerations related to the maximum output current are the same of the "positive buck-boost" (ap- plication idea 2). a particularity of this topology is that the device undergoes a voltage that is the sum of v in and v out . so, con- verting 5v to -5v, the device undergoes 10v voltage. it must be checked that the sum of the input and output voltage is lower than the maximum operating input voltage of the device. figure 32. buck-boost regulator 3v to 5.5v input / -5v 3a output circuit table 14. part list reference description manufacturer r1 910 ohm 5% 125mw neohm smd 0805 r2 10k 5% 125mw neohm smd 0805 r3 4.7k 5% 125mw neohm smd 0805 r4 1k ohm 5% 125mw neohm smd 0805 r5 2.7k 5% 125mw neohm smd 0805 r6 1k 5% 125mw neohm smd 0805 r7 10 ohm 5% 125mw neohm smd 0805 c1,c2 100 f - 20v oscon 20sa100m radial 10x10.5 c13,c14 330 f - 6.3v poscap 6tpb330m smd7343 c12,c4,c5,c8 100nf kemet smd0805 c3 1nf kemet smd0805 c6 4.7 f - 16v aux sma6032 c7 100nf kemet l1 r1 c1- c2 c3 c13 - 14 q2 q1 d2 c6 13 14 10 11 3 1 u1 l6910/a vin (3v to 5.5v ) vout (-5v 3a) 6 12 5 4 2 15 7 9 vcc gnd vref ss osc ocset ugate phase lgate pgnd pgood vfb comp c9 c8 c4 d1 gndout c7 c5 r7 c10 c12 8 gnd i n = gndout r5 r3 r4 c11 r6 earef boot g1 vcc (5v) gndcc l1 r1 c1- c2 c3 c13 - 14 q2 q1 d2 c6 13 14 10 11 3 1 u1 l6910/a vin (3v to 5.5v ) vout (-5v 3a) 6 12 5 4 2 15 7 9 vcc gnd vref ss osc ocset ugate phase lgate pgnd pgood vfb comp c9 c8 c4 d1 gndout c7 c5 r7 c10 c12 8 gnd i n = gndout r5 r3 r4 c11 r6 earef boot g1 vcc (5v) gndcc l1 r1 c1- c2 c1- c2 c3 c13 - 14 q2 q1 d2 c6 13 14 10 11 3 1 u1 l6910/a vin (3v to 5.5v ) vout (-5v 3a) 6 12 5 4 2 15 7 9 vcc gnd vref ss osc ocset ugate phase lgate pgnd pgood vfb comp c9 c8 c8 c4 d1 gndout gndout c7 c7 c5 r7 c10 c12 c12 8 gnd i n = gndout r5 r3 r4 c11 r6 earef boot g1 vcc (5v) gndcc
25/29 l6910 - l6910a figure 33. efficiency vs. output current c9 15nf kemet smd0805 c10 1.5nf kemet smd0805 reference description manufacturer c11 47nf kemet smd0805 g1 open jumper l1 2.5 h (77121a7 core, double winding 7 awg16) magnetics q1,q2 sts11nf30l st so8 d1 1n4148 sot23 d2 stps3l25u ( stps340u) st smb (d0144) u1 device l6910 st so16 narrow table 14. part list (continued) 82 84 86 88 90 92 94 11.522.53 output current (a) efficiency (%) vcc=5v vout= - 5v fsw=200khz vin=5v vin=3.3v 82 84 86 88 90 92 94 11.522.53 output current (a) efficiency (%) vcc=5v vout= - 5v fsw=200khz vin=5v vin=3.3v
l6910 - l6910a 26/29 figure 34. htssop16 (exposed pad) mechanical data & package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a1.20.047 a1 0.15 0.006 a2 0.8 1.0 1.05 0.031 0.039 0.041 b 0.19 0.3 0.007 0.012 c 0.09 0.2 0.003 0.008 d (*) 4.9 5.0 5.1 0.192 0.197 0.200 d1 1.7 0.067 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 (*) 4.3 4.4 4.5 0.169 0.173 0.177 e2 1.5 0.059 e 0.65 0.026 l 0.45 0.6 0.75 0.018 0.024 0.029 l1 1.0 0.039 k 0? (min), 8? (max) aaa 0.10 0.004 (*) dimensions d and e1 does not include mold flash or protusions. mold flash or protusions shall not exeed 0.15mm per side. htssop16 7419276 (exposed pad)
27/29 l6910 - l6910a figure 35. so-16 (narrow) mechanical data & package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.75 0.069 a1 0.1 0.25 0.004 0.009 a2 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 c 0.5 0.020 c1 45 (typ.) d (1) 9.8 10 0.386 0.394 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 f (1) 3.8 4.0 0.150 0.157 g 4.60 5.30 0.181 0.208 l 0.4 1.27 0.150 0.050 m 0.62 0.024 s8 (max.) (1) "d" and "f" do not include mold flash or protrusions - mold flash or protrusions shall not exceed 0.15mm (.006inc.) so16 (narrow) 0016020 d
l6910 - l6910a 28/29 table 1. revision history date revision description of changes january 2004 7 migration from st-press to edocs dms. august 2004 8 changed any figures and textes; add. the section ?15a htssop16 demo board description?. changed the style-look following the new ?corporate technical pubblications design guide? rules; and figs 23, 30, 32 may 2005 9 changed the figure 30.
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com 29/29 l6910 - l6910a

▲Up To Search▲

Price & Availability of L691005

	To Download L691005 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .