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application note tea2037a horizontal & vertical deflection circuit AN410/1293 by b. d'halluin summary page i introduction .................................... ................... 2 ii functional description of tea2037a ................................ 2 ii.1 general description . . . . . . ......................................... 2 ii.1.1 block diagram. . . . . . . . . ............................. ................... 2 ii.1.2 pin description . . . . . ................................................... 3 ii.1.3 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............................. 3 ii.2 sync. pulse separator . . . . . . ....................................... 3 ii.2.1 extraction of sync. pulses from the composite video signal . . . . . . . . . . . . . . ....... 3 ii.2.2 negative ttl sync. (monitor application) . . . . . . . . . . . . . ....................... 3 ii.2.3 frame sync extraction . . . . . . . . . . . ....................................... 4 ii.3 line oscillator . ................................................... 4 ii.4 line output stage . . . . . . . . . . . ....................................... 5 ii.5 phase comparator (pll) . . . ......................................... 5 ii.5.1 functional description ................................................... 5 ii.5.2 phase comparator operation . . . . . . ....................................... 6 ii.5.3 output filter . . . . ............. ......................................... 7 ii.6 frame oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................... 8 ii.7 frame output amplifier . . . . . . . . . . . . . . . ............................. 8 ii.8 frame flyback generator. . . ....................................... 9 ii.9 shunt regulator . . . . . . . . . . . ....................... ................ 10 ii.10 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . ................... 10 iii application examples .............................................. 11 iii.1 monitor applications . ............................................. 11 iii.1.1 low-cost monitor (french minitel). . . ....................................... 11 iii.1.2 monitor with geometry and frequency adjustments . .......................... 12 iii.1.3 high frequency monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................... 13 iii.2 black & white application . . . . . . . . . . . . . ............................. 14 iii.3 using composite ttl synchronization signals. . . ................... 15 iii.4 direct frame synchronization . . . . . . . . . . . . . . . . . . ................... 15 iii.5 constant amplitude 50/60hz switching. ............................. 15 iii.6 modifying the line output duration . . . ............................. 16 iii.7 starting the tea2037a from +6v power supply. . . . . . . . . . . . . . . . . . . . . . 16 iv design consideration .............................................. 17 iv.1 precaution for interlaced scanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 iv.2 printed circuit board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1/17
i - introduction the tea2037a is a horizontal and vertical deflec- tion circuit for monitors and black and white tv sets. this device includes all functions required for de- flection, namely : - line and frame sync separation - line oscillator with phase comparator - driver stage for line deflection darlington transis- tor - frame oscillator - frame amplifier with flyback generator for direct drive of the vertical deflection yoke. the tea2037a is particularly well-suited for low- cost monitors since it is cased in a low-cost pack- age and requires a few number of external components and hence optimized for small dis- plays. however, application areas are by no means lim- ited. sophisticated applications requiring various adjustment possibilities such as for display geome- try and centering settings (amplitude, linearity,...) and operating at different line and frame frequen- cies (line frequencies up to 64khz), are readily configured around tea2037a. in large screen applications, addition of a heatsink mounted on tea2037a will enable the vertical deflection yoke current to be boosted to 2a peak- to-peak. ii - functional description of tea2037a ii.1 - general description the tea2037a is a 16-pin dip package. the 4 center pins (2 on each side) are connectedtogether and used as heatsink. from composite video or ttl-compatible sync. signals, the device will extract and generate all signals required for the line scanning darlington transistor and direct drive of the frame yoke. the following functional blocks are implemented on-chip : - line and frame sync. separator - line oscillator - line phase comparator - line output stage - frame oscillator - frame amplifier - frame flyback generator - shunt regulator the common device power supply is implemented by the on-chip shunt regulator. in order to optimize the drive to frame deflection yoke and also enable appropriate use of the flyback generator, the frame amplifier is powered by an independentsupply. the ground is connected to the 4 center pins of the device. frame oscillator 12 3 5 6 7 8 9 10 11 12 15 16 yoke v cc1 4 13 14 power stage + - frame-sync. separator frame oscillator phase detector line oscillator output stage flyback generator input stage tea2037a 2037a-02.eps figure 1 ii.1.1 - block diagram tea2037a - horizontal & vertical deflection circuit 2/17
ii.1.2 - pin description 1 frame oscillator 2v cc2 (flyback generator power supply) 3 flyback generator output 4, 5 ground 6 frame feed-back (frame amplifier inverting input) 7v cc2 (positive power supply for frame output stage) 8 frame output (direct drive to frame yoke) 9 line oscillator 10 phase comparator output 11 phase comparator input (line flyback) 14 line output (drive to line darlington transistor) 15 video input (or ttl-compatible sync.) 16 v cc1 (shunt regulator) ii.1.3 - package batwing dip16 (plastic package) sl1 sl2 15 v r2 r1 video r 2037a-03.eps figure 2 : synchronization separator circuit ii.2 - sync. pulse separator the tea2037a extracts, first the line and frame sync. pulses from the composite video signal and then the largest pulses, i.e., the frame syncs. ii.2.1 - extraction of sync. pulses from the composite video signal (tv application) 15 v r ttl sync tea2037a 2037a-14.eps figure 5 15 1m w 100nf 220pf composite video tea2037a 1.5k w 2037a-13.eps figure 4 t t video level 0 0 pin 15 voltage (v) 1.6 1 line (64 m s) 2037a-12.eps figure 3 - the sync. detection level is set at 1.6v. - the value of r2 is typically 1m w (fixed for a good internal bias). - resistor r1 limits the output current of pin 15. as illustrated in the figure 4, it is recommended to employ a low-pass filter which will suppress high- frequency harmonics susceptible to produce jitters on line sync signal in composite video tv applica- tions. ii.2.2 - negative ttl sync. (monitor application) in monitor application, the sync. signal is generally separated from the video signal. in this case, the sync. signal is applied to pin 15 through a single limiting resistor. similar to the former case, the sync. is detected when the input voltage falls below 1.6v level. tea2037a - horizontal & vertical deflection circuit 3/17
v q4 q3 z sl1 3i i st1 st2 v/2 z 2037a-04.eps figure 7 : frame separator ttl sync level (v) t t 5 1.6 5 1.6 pin 15 voltage (v) 2037a-15.eps figure 6 ii.2.3 - frame sync. extraction this function is processed internally and hence does not require any external component. line and frame sync. pulses are distinguished by an inte- grated capacitor which is more or less discharged during each sync. pulse interval as follows : - if the sync pulse duration is short, i.e. it is line sync, then the capacitor is slightly discharged - on the other hand, if the pulse width is larger, the capacitor is fully discharged and an internal frame signal is thus generated. t t v z v z /2 sync pulse integrated capacitor voltage (v) 2037a-16.eps figure 8 ii.3 - line oscillator 9 16 1.4k w rc tea2037a v cc1 2037a-17.eps figure 9 t 6.6 3.2 pin 9 voltage(v) line period 2037a-18.eps figure 10 this function is processed internally and hence does not require any external component. line and frame sync. pulses are distinguished by an inte- grated capacitor which is more or less discharged during each sync. pulse interval as follows : - if the sync pulse duration is short, i.e. it is line sync, then the capacitor is slightly discharged - on the other hand, if the pulse width is larger, the capacitor is fully discharged and an internal frame signal is thus generated. the line saw-tooth is generated by charging an external capacitor on pin 9 via a resistor connected to v cc1 (pin 16). the capacitor is discharged via an internal 1.4k w resistor. the saw-tooth amplitude is set by two on-chip threshold levels : - lower threshold : 3.2v - higher threshold : 6.6v the free-running period is approximately given by the following relationship : t osc 0.85 rc tea2037a - horizontal & vertical deflection circuit 4/17
the phase comparator will modify the capacitor charge by injecting a positive or negative current so as to produce correct phase and frequency relationships with respect to the synchronization signal. ii.4 - line output stage the line output stage has been designed for direct base drive of the horizontal scanning darlington transistor. the low level interval on pin 14, i.e. the power line transistor blocking period, is determined by the time when the voltage of the line oscillator capacitor (pin 9) is below 4.8v (internally set threshold level). in a typical application, this interval corresponds to 22 m sat64 m s free-running period. 14 tea2037a line yoke cc v r1 c d r3 t r2 ref v = 4.8v t1 = 470 w r2 = 10 w r3 = 47 w c = 2.2 m f d : 1n4148 t : bu184 6.6v 3.2v line sawtooth 2037a-19.eps figure 11 t t t t 6.6 4.8 3.2 22 m s 64 m s v (sat) pin9 voltage (v) pin14 voltage (v) darlington v ce yoke current 2037a-20.eps figure 12 ii.5 - phase comparator (pll) ii.5.1 - functional description the duty of phase comparator is to synchronize the horizontal scanning with the line sync pulse and ensure correct line flyback during the horizontal blanking phase. video signal line flyback 2037a-21.eps figure 13 the line flyback signal (i.e. the pulse on the collec- tor of the line scanning transistor) is compared with the line sync. signal issued by sync. separator. if the detected coincidence is incorrect, the compa- rator will then generate an appropriate positive or negative current so as to charge or discharge the line oscillator capacitor thereby providing for fre- quency and phase locking. tea2037a - horizontal & vertical deflection circuit 5/17
ii.5.2 - phase comparator operation line flyback integrated flyback sync pulse output current v c 2037a-06.eps figure 15 : phase comparator 11 r1 c2 c1 i 3 i 1 i 2 t4 t1 t2 t3 v cc1 i t5 t6 9 10 c3 c4 c5 r3 r4 r5 v cc1 i out v ref ls fs line oscillator 2037a-22.eps figure 14 the line flyback signal goes through integrator network r1c1 the output of which, a saw-tooth signal, is applied to comparator input (pin 11) via capacitor c2. the comparator input stage is formed by the differ- ential pair t1 and t2. t3 and t4 transistors are arranged in current mirror configuration and thus : i 3 =i 2 the sum of currents going through t1 and t2 transistors is determined by the current generator oio so that : i=i 1 +i 2 the comparator output current is the difference current through the differential pair, i.e. : i out =i 2 -i 1 the comparator is enabled by t5 transistor only during the line sync. interval. transistor t6 inhibits the phase comparison during the frame sync. interval. during the first portion of the flyback, the voltage at comparator input (pin 11) is lower than the refer- ence voltage. t1 is off and t2 conducts ; conse- quently the comparator output goes positive : i out =+i during the second portion, the input voltage ex- ceeds the reference voltage and as a result, the comparator ouput falls to negative level : i out =-i if the line flyback is in retard with respect to the horizontal sync. pulse (which is the case of too long line periods), the interval for which the phase com- parator's output current is positive would increase. this current is then filtered and applied to the line oscillator capacitor (c5) thereby accelerating its charge-up phase and hence reducing the line pe- riod. inverse action takes place if the line flyback is in advance - the negative current at comparator's output will rise, c5 is charged more slowly and the line period is thus increased. tea2037a - horizontal & vertical deflection circuit 6/17
ii.5.3 - output filter line flyback sawtooth (pin 11) internal line sync pulse output current (pin 10) the line flyback in retard with respect to the line sync pulse the line flyback in advance with respect to the line sync pulse v ref v ref 2037a-23.eps figure 16 9 10 c3 c4 c5 r3 r4 r5 v cc1 filter 2037a-24.eps figure 17 gain frequency f1 f2 f3 2037a-25.eps figure 18 f 1 = 1 2 p( r3 + r4 ) c3 f 2 = 1 2 p r3c3 f 3 = r3 + r4 2 p r3 r4c4 the duty of the output filter is to ensure the stability of the locked loop and its characteristics will have a partial influence on capture range and also on capture time. the holding range, which is larger than the capture range, dependson the ratio of the current available at the comparator output and the charging current of the line oscillator. the holding range does not depend directly on the cut-off frequencies of the output filter. but, as the voltage range at the com- parator output is limited, a too high value for r4 will limit the holding range. the sync. pulse duration has significant influence on capture range and also on the holding range of the device. the output current duration is directly related to synchronization pulse width. - first the r5 x c5 product is selected to yield the required free-running line oscillator frequency. - then, the value of c5 capacitor is selected as follows : ? for monitor applications (large holding range) low value; e.g. : 2.2nf @ 16khz, 1nf @ 32khz ? for tv applications ? higher value; e.g. : 4.7nf @ 16khz - finally, the filter components are selected to match the required capture range. (r4 100k w to prevent comparator output satu- ration) tea2037a - horizontal & vertical deflection circuit 7/17
ii.6 - frame oscillator similar to line oscillator, the frame saw-tooth is generated by charging an external capacitor on pin 1 through a resistor connected to v cc1 . 9 16 500 w rc v cc1 frame sync pulse tea2037a 2037a-26.eps figure 19 3.1 2 3.1 2 amplitude amplitude t t t sync period frame free-running period pin 1 voltage (v) pin 1 voltage (v) internal frame sync 2037a-27.eps figure 20 the capacitor is discharged via an internal 500 w resistor. the saw-tooth amplitude is set at two on-chip threshold levels. the free-running period is approximately given by : t osc 0.15 rc synchronization is achieved by period reduction. the frame sync. pulse issued by the sync. separa- tor will modify the current through the resistor bridge which is used to set the saw-tooth threshold levels. the minimum synchronized frame period (msfp) is given by : msfp t osc 1.8 ii.7 - frame output amplifier the frame saw-tooth generated by frame oscillator is first inverted (gain : - 0.4) and then applied to the non-inverting input of the frame amplifier. the out- put current capability of this amplifier is as high as 1athus enabling to drive vertical deflection yokes requiring 2a peak-to-peak. as a function of dissipated power, the device may require the addition of a heatsink. a feed-back loop is connected to the inverting input of the frame amplifier (pin 6). as the crt screen is not part of a sphere centered on the deflectioncenter point, if the yoke is actually driven by a saw-tooth waveform, the image is expanded at the top and bottom. the yoke must therefore be provided with an oso waveform cur- rent, by applying linearity correction. 4 5 6 8 12 13 r3 c3 r6 frame yoke 7 v cc2 r4 r5 c2 r2 r1 p c1 frame sawtooth 2037a-28.eps figure 21 tea2037a - horizontal & vertical deflection circuit 8/17
t t t yoke current output voltage (pin 8) frame sawtooth (non-inverting input) 2037a-29.eps figure 22 the circuit configuration depicted above does not require any linearity adjustment - only an amplitude adjustment potentiometer opo has been provided for. - d.c. feedback : the c1 capacitor is charged to approximately 1/2 x v cc2 . divider bridge formed by r2 + r4 and r5 networks will set the d.c. feedback. the component values of this divider network will be choosen to avoid saturation at top and bottom of the output voltage (pin 6 biasing voltage is approximately 0.6v). - linearity correction : aparabolic signal at frame frequency is available on o+o terminal of the c1 capacitor. this signal is integrated by r2, c2 network. an oso waveform is thus obtained,which is applied to pin 6 via resistor r4. any correction to this oso waveform depends on c1 and c2 values. the linearity correction de- pends on ratio : r2/r4 - vertical amplitude : frame current amplitude is determined by the value of measurement resistor or1o, potentiometer opo settings and the value of or5o resistor. ii.8 - frame flyback generator the output stage of the vertical amplifier includes a frame flyback generator connected to pin 3. during the vertical scanning flyback time, the value of the yoke inductance olo must be taken into account since the time constant l/r is no longer negligible. in television applications, the frame blanking time is 1.6ms. thus when l/r > 1.6 x 10 -3 , it is necessary to increase the supply voltage to the frame output amplifier so as to reduce the flyback time. this surplus is required only for the frame flyback and energy is wasted by boosting the sup- ply to the amplifier at all times (during the frame scanningtime, the minimum voltage issubstantially ri, where i is peak-to-peak frame current). the configuration of the flyback generator is de- picted in figure 23. 2 t2 t1 3 7 k c d1 d2 8 frame amplifier output l, r v cc 2037a-30.eps figure 23 t t t v cc v cc2 amplifier supply amplifier output voltage (pin 8) output current (yoke current) 2037a-31.eps figure 24 during the second half of the vertical scanning time, transistor t2 conducts and capacitor c is charged to v cc through d1, d2, r3 and t2. (switch k open) on flyback, switch k closes and pin 3 is connected to v cc . the voltage at pin 7 (v cc2 ), which was equal to v cc -v d1 , is almost doubled during the flyback time. the only external components re- quired are therefore d1, d2 and c. in addition to reducing the flyback time, the flyback generator reduces the power consumed by the power stage, and can in certain cases avoid the need to use a heatsink. diode d2 is a low-signal diode (1n4148) but diode d1 must be appropriately rated since the positive current in the first part of the saw-tooth is supplied to the yoke through d1 and t1. a 1n4001 is gen- erally used. tea2037a - horizontal & vertical deflection circuit 9/17
ii.9 - the shunt regulator the tea2037a incorporates an internal shunt regulator which delivers the common supply volt- age v cc to various blocks such as oscillators, comparator, sync separator and so on. the voltage on pin 16 is 9.7v (9v min, 10.5v max). the value of the series resistor r must be so calculated to obtain a 15ma current on pin 16 - this current can be 10ma min. and 20ma max. 16 r tea2037a v cc v cc1 2037a-32.eps figure 25 the external current supply from v cc1 to both oscillators (i.e. line and frame) can be neglected in majority of cases. the resistor value is found to be 1.2k w at v cc = +28v. at v cc = + 12v, and taking into account the voltage tolerance on pin 16, a 150 w series resistor must be used. ii.10 - thermal considerations in order to ensure reliable device operation, the dissipated power should be accurately determined. calculation will allow an evaluation of the dissi- pated power and should be completed by package temperature measurements in actual applications. according to results obtained, a heatsink may or may not be required. ? power drawn from v cc1 supply : p1 = v cc1 .i 1 where i 1 is the current through the shunt regulator (pin 16). ? power drawn from v cc2 supply : p2 = v cc2 ? ? ? i pp 8 + i 2 ? ? ? where : - ipp = peak-to-peak current through the vertical deflection yoke. -i 2 = pin 7 quiescent current. -v cc2 = pin 7 voltage. ? power dissipated in deflection yoke and the measurement resistor : p y = ( r y + r m ) i 2 pp 12 where : -r y = frame deflection yoke resistance -r m = measurement resistor value thus, the overall power dissipated in the integrated circuit is : p d =p1+p2-p y p d = ? ? v cc1 ? i 1 ? ? + ? ? ? v cc2 ? ? ? ipp 8 + i 2 ? ? ? ? ? ? - ? ? ? ( r y + r m ) i 2 pp 12 ? ? ? in application using the flyback generator, the v cc2 specified above becomes ov cc2 -v d o, where v d is the voltage drop across the series diode. 4 5 7 8 16 12 13 i 12 i v cc v cc2 tea2037a r m frame yoke ly, ry 2037a-33.eps figure 26 frame yoke current i pp 2037a-34.eps figure 27 tea2037a - horizontal & vertical deflection circuit 10/17
iii - applications iii.1 - monitor applications iii.1.1 - low-cost monitor (french minitel type) (see figure 28) characteristics - screen : 9o monochrome - frame deflection yoke : 72mh, 40 w , 220ma peak-to-peak -v cc = + 25v without flyback generator - frame flyback time : 1.2ms - vertical frequency : 50hz (20ms) - vertical free-running period : 24.5ms - horizontal frequency : 15 625hz - capture range : 5 m s - holding range : 10 m s - input signal : composite video - dissipated power : 1.15w - only one adjustment : vertical amplitude this is a low-cost application used in french minitel type configurations and requires minimum number of additional components and adjustments. the input is a composite video signal at line fre- quency = 15 625hz and frame frequency of 50hz. the free-running horizontal frequency is deter- mined by the component values of rc network on pin 9. since no adjustment is available, precision components must be used to ensure correct syn- chronization : [r = 35.7k w , 1% and c = 2.2nf, 2% for f h = 15 625hz] the capture range is large enough to compensate for possible variations. - synchronizationrange of the vertical oscillator is quite large which consequentlyallows use of less accurate components : [r = 910 k w , 5 % and c = 180 nf, 5 %] - since the frame flyback time is short enough at supply voltage used here, the flyback generator is not used in this application. 123 45 6 7 8 9 10 16 11 12 13 14 15 2.2nf 2% 22nf 100k w 35.7k w 1% 3.9k w 1 m f 15k w line flyback 47nf 22nf 1m w 1.5k w 100nf video input 180nf 5% v cc v cc1 100 m f 1k w 910k w 5% +25v v cc1 470k w 470k w 220nf 56k w 100 w vertical amplitude adjust frame yoke 72mh, 40 w 1k w 470 m f 2.2k w 100nf v cc 470 w 1w 10 w 2.2 m f 47 w 1n4148 line darlington 4.7k w tea2037a 2037a-35.eps figure 28 tea2037a - horizontal & vertical deflection circuit 11/17
123 45 6 7 8 9 10 16 11 12 13 14 15 22nf 100k w 22k w 3.9k w 1 m f 15k w line flyback 47nf 22nf ttl sync 180nf v cc v cc1 100 m f 150 w 470k w +12v v cc1 v cc 180 w 1/2w 10 w 47 m f 47 w 1n4148 line darlington tea2037a 10k w 100k w v cc1 470k w p3 p5 47k w 1n4002 1000 m f 18k w 180k w 470nf 39k w 100 w frame yoke 18mh, 10 w 220 w 2.2 w 100nf 1.2k w p1 p2 100k w 680pf v cc 330 w 330 w 1 2 3 1n4148 2.2 m f 22nf 22k w p4 p1 : vertical amplitude p2 : vertical linearity p3 : vertical frequency p4 : horizontal frequency p5 : horizontal shift 1-2-3 switching : vertical position 2037a-36.eps figure 29 iii.1.2 - monitor with geometry and frequency adjustments (see figure 29) characteristics - screen : 12o colour - frame deflection yoke : 18mh, 10 w , 500ma peak-to-peak -v cc = + 12v with flyback generator - frame flyback time : 0.7ms - vertical frequency : 50/60hz - vertical free-running period : 23ms (adjustable) - horizontal frequency : 15.7khz (adjustable) - capture range : = 5 m s - holding range : 10 m s - input signal : negative ttl sync (line + frame) - dissipated power : 0.9w - adjustments : ? vertical amplitude ? vertical linearity ? vertical frequency ? horizontal frequency ? horizontal phase-shift tea2037a - horizontal & vertical deflection circuit 12/17
123 45 6 7 8 9 10 16 11 12 13 14 15 6.8nf 4.7k w 22k w 3.9k w 1 m f 15k w line flyback 47nf 22nf ttl sync 150nf v cc v cc1 100 m f 170 w 470k w +14v v cc1 v cc 220 w 1/2w 10 w 47 m f 47 w 1n4148 line darlington tea2037a 10k w 470k w p3 1n4002 2200 m f 39k w 68k w 330nf 18k w 100 w frame yoke 18mh, 10 w 180 w 2.2 w 100nf 1 w p1 p2 47k w 680pf 1n4148 2.2 m f 1nf 22k w p4 p1 : vertical amplitude p2 : vertical linearity p3 : vertical frequency p4 : horizontal frequency 2.2 w 1000 m f 2037a-37.eps figure 30 iii.1.3 - high frequency monitor (see figure 30) characteristics - screen : 14o colour - frame deflection yoke : 11mh, 7 w , 750ma peak-to-peak -v cc = + 14 v with flyback generator - frame flyback time : 0.6ms - vertical frequency : 72hz - vertical free-running period : 16ms (adjustable) - horizontal frequency : 35khz (adjustable) - line flyback time : 5.5 m s - capture range : 5 m s (@sync pulse = 4.7 m s) - input signal : negative ttl sync (line + frame) - dissipated power : 1.4w (heatsink required) - adjustments : ? vertical amplitude ? vertical linearity ? vertical frequency ? horizontal frequency tea2037a - horizontal & vertical deflection circuit 13/17
p2 33k w 47k w 123 4 5 6 7 8 9 10 16 11 12 13 14 15 4.7nf 22nf 100k w 4.7k w 2.2 m f 15k w line flyback 47nf 22nf 1m w 1.5k w 100nf video input 180nf 5% v cc v cc1 100 m f 1k w 910k w 5% +24v v cc1 100k w 220k w 680nf 15k w frame yoke 30mh, 12 w 680 w 470 m f 2.2 w 100nf v cc 470 w 1w 10 w 2.2 m f 47 w 1n4148 line darlington tea2037a 220pf 4.7 w 470 m f 15k w p3 4.7k w 47 m f 1n4148 2.2k w frame blanking 24v 1n4002 p1 100 w 1 w 680nf 680pf p1 : vertical amplitude p2 : vertical linearity p3 : horizontal frequency 2037a-38.eps figure 31 iii.2 - black & white tv application (see figure 31) characteristics - screen : 20o b & w 110 o - frame yoke : 30mh, 12 w , 850mapeak-to-peak -v cc = + 24 v with flyback generator - frame flyback time : 1ms - vertical frequency : 50hz - vertical free-running period : 24.5ms - horizontal frequency : 15 625hz (adjustable) - capture range : 2 m s - holding range : 4.5 m s - input signal : composite video - dissipated power : 2.3w (10 o c/w - heatsink required) - adjustments : ? vertical amplitude ? vertical linearity ? horizontal frequency tea2037a - horizontal & vertical deflection circuit 14/17
15 line sync input 10k w tea2037a 33nf 330 w 47k w frame sync input 2037a-41.eps note : specified component values are purely theoretical and must be calculated to meet specific application requirements. figure 34 : application example 15 line sync input frame sync input 10k w tea2037a 2037a-40.eps figure 33 15 tea2037a reference 10k w 2037a-39.eps figure 32 iii.3 - using composite ttl synchronization since the threshold level on input pin 15 is inter- nally set at 1.6v, the device can directly accept ttl signals. however, a series resistor is required to limit the current sunk by the on-chip transistor (pin 15). if composite sync signal is not available, line and frame sync signals can be recombined at circuit input as illustrated in figure 33. 1 16 15 680k w 10k w 10k w 220nf positive frame sync negative line sync v cc1 tea2037a 2037a-42.eps figure 35 1 tea2037a vertical oscillator 60hz 50hz 60hz amplitude adjust v cc1 2037a-43.eps figure 36 this arrangement is particularly interesting in ap- plications where the available signals differ from those commonly used. an example is the case where the frame signal is of quite long duration (sometimes as long as frame blanking period). in such case, efficient synchronization can be achieved by differentiating the signal so that it will behave as a signal of only few lines duration which is the condition required for appropriate frame and line sync separation and also a picture without flag effect. iii.4 - direct frame synchronization the vertical scanning can be directly synchronized by the frame oscillator (pin 1) and without any need of using the synchronization input (pin 15). figure 35 illustrates an example : in this case, only the line sync pulse is applied to pin 15. iii.5 - constant amplitude 50/60hz switching in applications requiring 50/60hz standard switch- ing feature, the arrangement shown below allows to maintain the amplitude of the oscillator saw-tooth (pin 1) constant thus yielding uniform vertical scan- ning. 3.1 2 pin 11 voltage(v) constant amplitude t upper threshold lower threshold 60hz sync 50hz sync 6 0 h z 5 0 h z 2037a-44.eps figure 37 tea2037a - horizontal & vertical deflection circuit 15/17
1 16 2.2k w 910k w 150nf 10k w t v cc1 50hz amplitude adjust 50hz : t conduc ts 60hz : t turnedoff tea2037a 10k w 2037a-45.eps figure 38 9 16 14 r1 r2 c r3 v cc v cc1 tea2037a 2037a-46.eps figure 39 pin 9 voltage (v) t t 6.6 4.8 3.2 pin 14 voltage (v) 2037a-47.eps figure 40 a practical application configuration is illustrated in figure 38. iii.6 - modifying the line output duration (see figures 39 and 40) the line output pulse duration is determined by two internally set threshold levels. this interval can be altered by modifying the charge current of the line oscillator (pin 9). iii.7 - starting the tea2037a from a +6v power supply the line oscillator of tea2037ais capable of start- ing at a low supply voltage (< 6v). the period of oscillation is practically the same as at nominal operation. it is thus possible to initiate the line power supply 7 16 14 tea2037a 1k w v cc1 cc2 v +25v eht transformer eht line yoke +6v ... +12v 100 m f 2037a-48.eps figure 16 scanning at a reduced supply voltage (e.g. +6v) and then supply the overall configuration by the power available on the line transformer (see fig- ure 41). tea2037a - horizontal & vertical deflection circuit 16/17
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no licence is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved purchase of i 2 c components of sgs-thomson microelectronics, conveys a license under the philips i 2 c patent. rights to use these components in a i 2 c system, is granted provided that the system conforms to the i 2 c standard specifications as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. iv - design considerations iv.1 - precautions for interlaced scanning - the links interconnecting the ground terminals of v cc and v cc1 power supplies, as well as those of device decoupling capacitors, must be kept to as short as possible - ahigh value decouplingcapacitor can be used for v cc supply, provided that a good quality low series resistance capacitor is employed. interlac- ing is very sensitive to decoupling quality. the value of the decoupling capacitor can vary from 22 m f to 100 m f. - the interconnecting links between the frame os- cillator capacitor, the line oscillator capacitor and tea2037a grounds must be kept to as short as possible. perfect line and frame synchronization is achieved by observing the above guidelines and recommen- dations. iv.2 - printed circuit board layout the usual precautions observed in design of tv timebase pc boards must be employed the line output stage handles high amounts of voltage and current. components employed must therefore be appropriately rated, the width of and the clearance between the wiring tracks should be carefully selected. all connectionsmust be as short as possible and all signals at the line frequency gathered at this section. the supply to the frame scanning section of the circuit must not be influenced by the horizontal scanning function, particularly when interlaced scanning is used. generally speaking, interactions on the pc board between the high-gain/low-level and the high-cur- rent sections of the output stages must be mini- mized by as much as possible. as indicated in previous chapters, the four center pins of the device must be earthed. the pad used for this purpose must be as large as possible since it acts as the heatsink for the device. a cruciform pad underlying the circuit should be employed. there should be a single connection to the chassis earth terminal. tea2037a - horizontal & vertical deflection circuit 17/17

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