1 ? fn7291.1 el7551 monolithic 1amp dc:dc step-down regulator the el7551 is an integrated, synchronous step-down regulator with output voltage adjust able from 1.0v to 3.8v. it is capable of delivering 1a continuous current at up to 95% efficiency. the el7551 operat es at a constant frequency pulse width modulation (pwm) mode, making external synchronization possible. pa tented on-chip resistorless current sensing enables cu rrent mode control, which provides cycle-by-cycle curren t limiting, ov er-current protection, and excellent step load response. the el7551 is available in a fused-lead 16-pin qsop package. with proper external components, the whol e converter fits into a less than 0.4 in 2 area. the minimal external components and small size make this el7551 ideal for desktop and portable applications. the el7551 is specified for operation over the -40c to +85c temperature range. pinout el7551 (16-pin qsop) top view features integrated synchronous mosfets and current mode controller 1a continuous output current up to 95% efficiency 4.5v to 5.5v input voltage adjustable output from 1v to 3.8v cycle-by-cycle current limit precision reference 0.5% load and line regulation adjustable switching frequency to 1.2mhz oscillator synchronization possible internal soft start over temperature protection under voltage lockout 16-pin qsop package pb-free plus anneal available (rohs compliant) applications dsp, cpu core and io supplies logic/bus supplies portable equipment dc:dc converter modules gtl + bus power supply manufactured under u.s. patent no. 57,323,974 1 2 3 4 16 15 14 13 5 6 7 12 11 10 8 9 sgnd cosc vdd pgnd pgnd vin vin en pgnd vref fb vdrv lx lx vhi pgnd r3 r2 l1 c3 c4 c1 c5 r1 c6 c 7 v o (3.3v,1a) v in (4.5v-5.5v) 2.37k ? 10h 1k ? 0.1f 47f 0.1f 0.1f 270pf 39 ? 10f ceramic ordering information part number part marking package tape & reel pkg. dwg. # el7551cu 7551cu 16-pin qsop - mdp0040 el7551cu-t7 7551cu 16-pin qsop 7? mdp0040 el7551cu-t13 7551cu 16-pin qsop 13? mdp0040 el7551cuz (see note) 7551cuz 16-pin qsop (pb-free) - mdp0040 el7551cuz-t7 (see note) 7551cuz 16-pin qsop (pb-free) 7? mdp0040 EL7551CUZ-T13 (see note) 7551cuz 16-pin qsop (pb-free) 13? mdp0040 note: intersil pb-free plus anneal produc ts employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. inters il pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet march 21, 2006 n o t r e c o m m e n d e d f o r n e w d e s i g n s s e e e l 7 5 3 1 o r e l 7 5 3 6 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2002, 2003, 2006. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 absolute maximum ratings (t a = 25c) supply voltage between v in or v dd and gnd . . . . . . . . . . . . +6.5v v lx voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v in +0.3v input voltage . . . . . . . . . . . . . . . . . . . . . . . . gnd -0.3v, v dd +0.3v v hi voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd -0.3v, v lx +6v storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c operating ambient temperature . . . . . . . . . . . . . . . .-40c to +85c operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . +135 caution: stresses above those listed in ?a bsolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a dc electrical specifications v dd = v in = 5v, t a = t j = 25c, c osc = 1.2nf, unless otherwise specified. parameter description conditions min typ max unit v ref reference accuracy 1.24 1.26 1.28 v v reftc reference temperature coefficient 50 ppm/c v refload reference load regulation 0 < i ref < 50a -1 % v ramp oscillator ramp amplitude 1.15 v i osc_chg oscillator charge current 0.1v < v osc < 1.25v 200 a i osc_dis oscillator dischar ge current 0.1v < v osc < 1.25v 8 ma i vdd +v drv v dd +v drv supply current v en = 4v, f osc = 120khz 3.5 5 ma i vdd_off v dd standby current en = 0 1 1.5 ma v dd_off v dd for shutdown 3.5 4 v v dd_on v dd for startup 3.95 4.45 v t ot over temperature threshold 135 c t hys over temperature hysteresis 20 c i leak internal fet leakage current en = 0, l x = 5v (low fet), l x = 0v (high fet) 10 a i lmax peak current limit 2 a r dson fet on resistance wafer level test only 45 95 m ? r dsontc r dson tempco 0.2 m ? /c v fb output initial accuracy i load = 0a 0.960 0.975 0.99 v v fb_line output line regulation v in = 5v, ? v in = 10%, i load = 0a 0.5 % v fb_load output load regulation 0.1a < i load < 1a 0.5 % v fb_tc output temperature stability -40c < t a < 85c, i load = 0.5a 1 % i fb feedback input pull up current v fb = 0v 100 200 na v en_hi en input high level 3.2 4 v v en_lo en input low level 1 v i en enable pull up current v en = 0 -4 -2.5 a el7551
3 closed-loop ac electrical specifications v s = v in = 5v, t a = t j = 25c, c osc = 1.2nf, unless otherwise specified. parameter description conditions min typ max unit f osc oscillator initial accuracy 105 117 130 khz t sync minimum oscillator sync width 25 ns m ss soft start slope 0.5 v/ms t brm fet break before make delay 15 ns t leb high side fet minimum on time 150 ns d max maximum duty cycle 95 % pin descriptions pin number pin name pin function 1 sgnd control circuit negative supply. 2 cosc oscillator timing capac itor. fosc can be approximated by: fosc (khz) = 0.1843/cosc, cosc in f. 3 vdd control circuit positive supply. 4 pgnd ground return of the regulator. connected to the source of the low-side synchronous nmos power fet. 5 pgnd ground return of the regulator. connected to the source of the low-side synchronous nmos power fet. 6 vin power supply input of the regulator. connected to the drain of the high-side nmos power fet. 7 vin power supply input of the regulator. connected to the drain of the high-side nmos power fet. 8 en chip enable, active high. a 2a internal pull- up current enables the device if the pin is left open. 9 pgnd ground return of the regulator. 10 vhi positive supply of the high-side driver. 11 lx inductor drive pin. high current digital output whose average voltage equals the regulator output voltage. 12 lx inductor drive pin. high current digital output whose average voltage equals the regulator output voltage. 13 vdrv positive supply of the low-side driver and input voltage for the high-side boot strap. 14 fb voltage feedback input. connected to an external resist or divider between vout and gnd. a 125na pull-up current forces vout to vs in the event that fb is floating. 15 vref bandgap reference bypass capac itor. typically 0.1f to gnd. 16 pgnd ground return of the regulator. el7551
4 typical performance curves efficiency vs i o v in =5v 100 95 90 85 80 75 70 65 60 0.1 0.2 0.4 0.6 1 load current i o (a) efficiency (%) v o =3.3v v o =1.8v v o =1.2v v o =1v v o =2.5v power loss vs i o v in =5v 0.25 0.2 0.15 0.1 0.05 0 0 0.2 0.4 0.8 1 output current i o (a) power loss (w) load regulation v o =3.3v 0.6 0.4 0 -0.2 -0.4 -0.6 0 0.2 0.4 0.8 1 load current i o (a) output voltage (%) v ref vs temperature 1.258 1.256 1.254 1.252 1.25 1.248 1.246 1.244 1.242 -40 10 60 110 160 temperature (c) v ref (v) efficiency vs i o v o =3.3v 100 95 90 85 80 75 70 65 60 00.20.40.6 1 load current i o (a) efficiency (%) line regulation v o =3.3v 0.6 0.5 0.4 0.2 0 -0.2 -0.4 4.5 4.7 5.1 5.3 5.5 v in (v) v o (%) v in =4.5v v in =5v v in =5.5v v in =4.5v v in =5v v in =5.5v 4.9 i o =0.1a i o =1a v o =1.5v v o =3.3v v o =1v 0.6 0.8 0.6 0.2 0.3 0.1 -0.1 -0.3 0.8 f s =500khz l=coilcraft do3316p-472 f s =500khz l=coilcraft do3316p-472 el7551
5 typical performance curves (continued) switching waveforms v in =5v, v o =3.8v, i o =1a ? v i v lx ? v o i l power-up v in =5v, v o =3.8v, i o =1a transient response v in =5v, v o =3.8v, i o =0a-1a i o ? v o v in v o oscillator frequen cy vs temperature 390 385 380 375 370 365 360 -40 0 40 80 120 temperature (c) oscillator frequency (khz) input current vs temperature (enable connected to gnd) 0.96 0.94 0.92 0.88 0.86 0.84 0.82 0.8 -40 10 60 110 160 temperature (c) input current (ma) switching frequency vs c osc 1400 1200 1000 800 600 400 200 0 0 400 600 800 1000 c osc (pf) f s (khz) 0.9 v in =4.5v v in =5v v in =5.5v 200 el7551
6 typical performance curves (continued) block diagram releasing en v in =5v, v o =3.8v, i o =1a shut-down v in =5v, v o =3.8v, i o =1a short-circuit protection v in =5v v in v o e n v o i o v o power-down v in =5v, v o =3.8v, i o =1a v in v o drivers pwm controller current sense voltage reference thermal shut-down oscillator 0.1f 39 ? controller supply sgnd power power fet fet 270pf 0.1f 0.1f 10h v out 2370 ? 1k ? 47f vref cosc vhi vin pgnd vdd vdrv fb en el7551
7 applications information circuit description general the el7551 is a fixed frequency, current mode controlled dc:dc converter with integrated n-channel power mosfets and a high precision reference. the device incorporates all the active circuitry required to implement a cost effective, user-programmable 1a synchronous step- down regulator suitable for use in dsp core power supplies. theory of operation the el7551 is composed of 5 major blocks: 1. pwm controller 2. nmos power fets and drive circuitry 3. bandgap reference 4. oscillator 5. thermal shut-down pwm controller the el7551 regulates output voltage through the use of current-mode controlled pulse width modulation. the three main elements in a pwm controller are the feedback loop and reference, a pulse width modulator whose duty cycle is controlled by the feedback error signal, and a filter which averages the logic level modulator output. in a step-down (buck) converter, the feedback loop forces the time-averaged output of the modulator to equal the desired output voltage. unlike pure voltage-mode control systems, current-mode control utilizes dual feedback loops to provide both output voltage and inductor current info rmation to the controller. the voltage loop minimizes dc and transient errors in the output voltage by adjusting the pwm duty-cycle in response to changes in line or load conditions. since the output voltage is equal to the time-averaged of the modulator output, the relatively large lc time constant found in power supply applications generally results in low bandwidth and poor transient response. by directly monitoring changes in inductor current via a series sense resistor the controller's response time is not entirely limited by the output lc filter and can react more quickly to changes in line and load conditions. this feed-forward characteristic also simplifies ac loop compensation since it adds a zero to the overall loop response. through proper selection of the current- feedback to voltage-feedback ratio the overall loop response will approach a one-pole system. the resulting system offers several advantages over traditional voltage control systems, including simpler loop compensation, pulse by pulse current limiting, rapid response to line variation and good load step response. the heart of the controller is an input direct summing comparator which sum voltage feedback, current feedback, slope compensation ramp and power tracking signals together. slope com pensation is required to prevent system instability that occurs in current-mode topologies operating at duty-cycles greater than 50% and is also used to define the open-loop gain of the overall system. the slope compensation is fixed internally and optimized for 500ma inductor ripple current. the power tracking will not contribute any input to the comparator st eady-state operation. current feedback is measured by the patented sensing scheme that senses the inductor current flowing through the high-side switch whenever it is conducting. at the beginning of each oscillator period the high-side nmos switch is turned on. the comparator inputs are gated off for a minimum period of time of about 150ns (leb) afte r the high-side switch is turned on to allow the system to settle. the leading edge blanking (leb) period prevents the detection of erroneous voltages at the comparator inputs due to switching noise. if the inductor current exceeds the maximum current limit (ilmax) a secondary over-current comparator will terminate the high-side switch on time. if ilmax has not been reached, the feedback voltage fb derived from the regulator output voltage vout is then compared to the internal feedback reference voltage. the resultant error voltage is summed with the current feedback and slope compensation ramp. the high-side switch remains on until all four comparator inputs have summed to zero, at which time the high-side switch is turned off and the low-side switch is turned on. however, the maximum on-duty ratio of the high-side switch is limited to 95%. in order to eliminate cross-conduction of the high-side and low-side switches a 15ns break-before- make delay is incorporated in the switch drive circuitry. the output enable (en) input allows the regulator output to be disabled by an external logic control signal. output voltage setting in general: however, due to the relatively low open loop gain of the system, gain errors will occur as the output vo ltage and loop- gain is changed. this is shown in the performance curves. a 100na pull-up current from fb to vdd forces vout to gnd in the event that fb is floating. nmos power fets and drive circuitry the el7551 integrates low on-resistance (60m ? ) nmos fets to achieve high efficiency at 1a. in order to use an nmos switch for the high-side drive it is necessary to drive the gate voltage above the source voltage (lx). this is accomplished by bootstrapping the vhi pin above the lx voltage with an external capacitor cvhi and internal switch and diode. when the low-side switch is turned on and the lx voltage is close to gnd potential, capacitor cvhi is charged through internal switch to vdrv, typically 5v. at the beginning of the next cycle the high-side switch turns on and the lx pins begin to rise from gnd to vin potential. as the v out 0.975v 1 r 2 r 1 ------ - + ?? ?? ?? = el7551
8 lx pin rises the positive plate of capacitor cvhi follows and eventually reaches a value of vdrv+vin, typically 10v, for vdrv=vin=5v. this voltage is then level shifted and used to drive the gate of the high-side fet, via the vhi pin. a value of 0.1f for cvhi is recommended. reference a 1.5% temperature compensated bandgap reference is integrated in the el7551. the external vref capacitor acts as the dominant pole of the amplifier and can be increased in size to maximize transient noise rejection. a value of 0.1f is recommended. oscillator the system clock is generated by an internal relaxation oscillator with a maximum duty -cycle of approximately 95%. operating frequency can be adjusted through the cosc pin or can be driven by an external source. if the oscillator is driven by an external source care must be taken in selecting the ramp amplitude. since cslope value is derived from the cosc ramp, changes to cosc ramp will change the cslope compensation ramp which determine the open- loop gain of the system. when external synchronization is required, always choose c osc such that the free-running frequency is at least 20% lower than that of sync source to accommodate component and temperature variations. figure 1 shows a typical connection. thermal shut-down an internal temperature sensor continuously monitors die temperature. in the event that die temperature exceeds the thermal trip-point, the system is in fault state and will be shut down. the upper and low trip-points are set to 135c and 115c respectively. start-up delay a capacitor can be added to the en pin to delay the converter start-up (figure 2) by utilizing the pull-up current. the delay time is approximately: figure 1. oscillator synchronization 2 3 11 10 9 6 7 8 15 14 el7551 1 16 external oscillator bat54s 100pf t d ms () 1200 c f () = figure 2. start-up delay time v o v in t d v out c 2 3 11 10 9 6 7 8 15 14 el7551 1 16 el7551
9 all intersil u.s. products are manufactured, asse mbled and tested utilizin g iso9000 quality systems. intersil corporation?s quality certifications c an be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com layout considerations the layout is very important for the converter to function properly. power ground ( ) and signal ground ( ) should be separated to ensure that the high pulse current in the power ground never interferes with the sensitive signals connected to signal ground. th ey should only be connected at one point (normally at the ne gative side of either the input or output capacitor.) the trace connected to pin 14 (fb) is the most sensitive trace. it needs to be as short as possible and in a ?quiet? place, preferably between pgnd or sgnd traces. in addition, the bypass capacitor connected to the vdd pin needs to be as close to the pin as possible. the heat of the chip is mainly dissipated through the pgnd pins. maximizing the copper area around these pins is preferable. in addition, a solid ground plane is always helpful for the emi performance. the demo board is a good example of layout based on these principles. please refer to the el7551 application brief for the layout. el7551
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