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| 8 bit microcontroller tlcs-870/c series TMP86FH12MG
page 2 TMP86FH12MG the information contained herein is su bject to change without notice. 021023 _ d toshiba is continually working to improve the qual ity and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fa il due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products , to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that to shiba products are used within specified operating ranges as set forth in the most re cent toshiba products specifications. also, please keep in mind the precautio ns and conditions set forth in the ? handling guide for semiconductor devices, ? or ? toshiba semiconductor reliability handbook ? etc. 021023_a the toshiba products listed in this document are inte nded for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ( ? unintended usage ? ). unintended usage include atomic energy control instruments, airplane or spaceship instruments, tr ansportation instruments, traffic signal instruments, combustion control instruments, medical instrument s, all types of safety devices, etc. unintended usage of toshiba products listed in this document shall be made at the customer's own risk. 021023_b the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohib ited under any applicable laws and regulations. 060106_q the information contained he rein is presented only as a guide for the applications of our products. no responsibility is assumed by tosh iba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. 021023_c the products described in this document may include products subject to the foreign exchange and foreign trade laws. 021023_f for a discussion of how the reliability of microcontro llers can be predicted, please refer to section 1.3 of the chapter entitled quality and reli ability assurance/hand ling precautions. 030619_s ? 2006 toshiba corporation all rights reserved revision history date revision 2005/10/26 1 first release 2006/4/21 2 contents revised 2006/6/29 3 periodical updating.no change in contents. 2006/10/17 4 contents revised i table of contents TMP86FH12MG 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 pin names and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. operational description 2.1 cpu core functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 memory address map ............................................................................................................................... 7 2.1.2 program memory (flash) .......................................................................................................................... 7 2.1.3 data memory (ram) ............................................................................................................................... .. 8 2.2 system clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.1 clock generator ............................................................................................................................... ......... 8 2.2.2 timing generator ............................................................................................................................... ..... 10 2.2.2.1 configuration of timing generator 2.2.2.2 machine cycle 2.2.3 operation mode control circuit .............................................................................................................. 11 2.2.3.1 single-clock mode 2.2.3.2 dual-clock mode 2.2.3.3 stop mode 2.2.4 operating mode control ......................................................................................................................... 16 2.2.4.1 stop mode 2.2.4.2 idle1/2 mode and sleep1/2 mode 2.2.4.3 idle0 and sleep0 modes (idle0, sleep0) 2.2.4.4 slow mode 2.3 reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3.1 external reset input ............................................................................................................................... 29 2.3.2 address trap reset ............................................................................................................................... ... 30 2.3.3 watchdog timer reset .............................................................................................................................. 30 2.3.4 system clock reset ............................................................................................................................... ... 30 3. interrupt control circuit 3.1 interrupt latches (il28 to il2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.2 interrupt enable register (eir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.2.1 interrupt master enable flag (imf) .......................................................................................................... 34 3.2.2 individual interrupt enable flags (ef28 to ef4) ...................................................................................... 35 note 3: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.3 interrupt sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.3.1 interrupt acceptance processing is packaged as follows. ....................................................................... 37 3.3.2 saving/restoring general-purpose registers ............................................................................................ 38 3.3.2.1 using push and pop instructions 3.3.2.2 using data transfer instructions 3.3.3 interrupt return ............................................................................................................................... ......... 39 3.4 software interrupt (intsw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.4.1 address error detection .......................................................................................................................... 40 3.4.2 debugging ............................................................................................................................... ............... 40 ii 3.5 undefined instruction interrupt (intundef) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.6 address trap interrupt (intatrap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.7 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4. special function r egister (sfr) 4.1 sfr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2 dbr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5. i/o ports 5.1 port p0 (p07 to p00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.2 port p1 (p17 to p10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.3 port p2 (p22 to p20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.4 port p3 (p37 to 30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6. watchdog timer (wdt) 6.1 watchdog timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.2 watchdog timer control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.2.1 malfunction detection methods using the watchdog timer ................................................................... 60 6.2.2 watchdog timer enable ......................................................................................................................... 61 6.2.3 watchdog timer disable ........................................................................................................................ 62 6.2.4 watchdog timer interrupt (intwdt) ...................................................................................................... 62 6.2.5 watchdog timer reset ........................................................................................................................... 63 6.3 address trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3.1 selection of address trap in internal ram (atas) ................................................................................ 64 6.3.2 selection of operation at address trap (atout) .................................................................................. 64 6.3.3 address trap interrupt (intatrap) ....................................................................................................... 64 6.3.4 address trap reset ............................................................................................................................... . 65 7. time base timer (tbt) 7.1 time base timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.1.1 configuration ............................................................................................................................... ........... 67 7.1.2 control ............................................................................................................................... ..................... 67 7.1.3 function ............................................................................................................................... ................... 68 7.2 divider output (dvo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.2.1 configuration ............................................................................................................................... ........... 69 7.2.2 control ............................................................................................................................... ..................... 69 8. real-time clock 8.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8.2 control of the rtc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 iii 9. 10-bit timer/counter (tc7) 9.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 9.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 9.3 configuring control and data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.4 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9.4.1 programmable pulse generator output (ppg output) ............................................................................. 78 9.4.1.1 50% duty mode 9.4.1.2 variable duty mode 9.4.1.3 ppg1/ppg2 independent mode 9.4.2 starting a count ............................................................................................................................... ........ 82 9.4.2.1 command start and capture mode 9.4.2.2 command start and trigger start mode 9.4.2.3 trigger start mode 9.4.2.4 trigger capture mode (cstc = 00) 9.4.2.5 trigger start/stop acceptance mode 9.4.3 configuring how the timer stops ............................................................................................................. 89 9.4.3.1 counting stopped with the outputs initialized 9.4.3.2 counting stopped with the outputs maintained 9.4.3.3 counting stopped with the outputs initialized at the end of the period 9.4.4 one-time/continuous output mode .......................................................................................................... 89 9.4.4.1 one-time output mode 9.4.4.2 continuous output mode 9.4.5 ppg output control (initial value/out put logic, enabling/disabling output) ............................................... 91 9.4.5.1 specifying initial values and output logic for ppg outputs 9.4.5.2 enabling or disabling ppg outputs 9.4.5.3 using the tc7 as a normal timer/counter 9.4.6 eliminating noise from the tc7 pin input ................................................................................................ 91 9.4.7 interrupts ............................................................................................................................... .................. 93 9.4.7.1 inttc7t (trigger start interrupt) 9.4.7.2 inttc7p (period interrupt) 9.4.7.3 intemg (emergency output stop interrupt) 9.4.8 emergency ppg output stop feature ...................................................................................................... 94 9.4.8.1 enabling/disabling input on the emg pin 9.4.8.2 monitoring the emergency ppg output stop state 9.4.8.3 emg interrupt 9.4.8.4 canceling the emergency ppg output stop state 9.4.8.5 restarting the timer after canceling the emergency ppg output stop state 9.4.8.6 response time between emg pin input and ppg outputs being initialized 9.4.9 tc7 operation and microcontroller operating mode ............................................................................... 96 10. 16-bit timercounter 1 (tc1) 10.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 10.2 timercounter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 10.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10.3.1 timer mode ............................................................................................................................... .......... 100 10.3.2 external trigger timer mode .............................................................................................................. 102 10.3.3 event counter mode ........................................................................................................................... 104 10.3.4 window mode ............................................................................................................................... ...... 105 10.3.5 pulse width measurement mode ........................................................................................................ 106 10.3.6 programmable pulse generate (ppg) output mode ......................................................................... 109 11. 8-bit timercounter (tc3, tc4) 11.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.2 timercounter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.3.1 8-bit timer mode (tc3 and 4) ............................................................................................................ 119 11.3.2 8-bit event counter mode (tc3, 4) .................................................................................................... 120 11.3.3 8-bit programmable divider output (pdo) mode (tc3, 4) ................................................................. 120 11.3.4 8-bit pulse width modulation (pwm) output mode (tc3, 4) .............................................................. 123 iv 11.3.5 16-bit timer mode (tc3 and 4) .......................................................................................................... 125 11.3.6 16-bit event counter mode (tc3 and 4) ............................................................................................ 126 11.3.7 16-bit pulse width modulation (pwm) output mode (tc3 and 4) ...................................................... 126 11.3.8 16-bit programmable pulse generate (ppg) output mode (tc3 and 4) ........................................... 129 11.3.9 warm-up counter mode ..................................................................................................................... 131 11.3.9.1 low-frequency warm-up counter mode (normal1 normal2 slow2 slow1) 11.3.9.2 high-frequency warm-up counter mode (slow1 slow2 normal2 normal1) 12. synchronous serial interface (sio) 12.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 12.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 12.3 serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 12.3.1 clock source ............................................................................................................................... ........ 135 12.3.1.1 internal clock 12.3.1.2 external clock 12.3.2 shift edge ............................................................................................................................... ............. 137 12.3.2.1 leading edge 12.3.2.2 trailing edge 12.4 number of bits to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 12.5 number of words to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 12.6 transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.6.1 4-bit and 8-bit transfer modes ............................................................................................................. 138 12.6.2 4-bit and 8-bit receive modes ............................................................................................................. 140 12.6.3 8-bit transfer / receive mode ............................................................................................................... 141 13. asynchronous serial interface (uart ) 13.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 13.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 13.3 transfer data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 13.4 transfer rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 13.5 data sampling method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 13.6 stop bit length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 13.7 parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 13.8 transmit/receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 13.8.1 data transmit operation .................................................................................................................... 148 13.8.2 data receive operation ..................................................................................................................... 148 13.9 status flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 13.9.1 parity error ............................................................................................................................... ........... 149 13.9.2 framing error ............................................................................................................................... ....... 149 13.9.3 overrun error ............................................................................................................................... ....... 149 13.9.4 receive data buffer full ..................................................................................................................... 150 13.9.5 transmit data buffer empty ............................................................................................................... 150 13.9.6 transmit end flag .............................................................................................................................. 151 14. 10-bit ad converter (adc) 14.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 14.2 register configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 14.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 14.3.1 software start mode ........................................................................................................................... 157 14.3.2 repeat mode ............................................................................................................................... ....... 157 v 14.3.3 register setting ............................................................................................................................... . 158 14.4 stop/slow modes during ad conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.5 analog input voltage and ad conversion result . . . . . . . . . . . . . . . . . . . . . . . 160 14.6 precautions about ad converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 14.6.1 analog input pin voltage range ........................................................................................................... 161 14.6.2 analog input shared pins .................................................................................................................... 161 14.6.3 noise countermeasure ....................................................................................................................... 161 15. key-on wakeup (kwu) 15.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 15.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 15.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 16. flash memory 16.1 flash memory control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 16.1.1 flash memory command sequence execution control (flscr vi 17.8 checksum (sum) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 17.8.1 calculation method ............................................................................................................................. 1 96 17.8.2 calculation data ............................................................................................................................... ... 197 17.9 intel hex format (binary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 17.10 passwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 17.10.1 password string ............................................................................................................................... . 199 17.10.2 handling of password error .............................................................................................................. 199 17.10.3 password management during program development .................................................................... 199 17.11 product id code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 17.12 flash memory status code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 17.13 specifying the erasure area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 17.14 port input control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 17.15 flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 17.16 uart timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 18. input/output circuit 18.1 control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 18.2 input/output ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 19. electrical characteristics 19.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 19.2 recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 19.2.1 mcu mode (flash memory writing and erasing) ................................................................................ 209 19.2.2 mcu mode (except flash memory writing and erasing) ...................................................................... 210 19.2.3 serial prom mode ............................................................................................................................. 2 10 19.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 19.4 ad conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 19.5 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 19.6 flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 19.7 recommended oscillating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 19.8 handling precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 20. package dimension this is a technical docu ment that describes the operat ing functions and electrical specifications of the 8-bit microc ontroller series tlcs-870/c (lsi). page 1 060116ebp TMP86FH12MG cmos 8-bit microcontroller ? the information contained herein is subject to change without notice. 021023_d ? toshiba is continually working to improve the quality and reli ability of its products. neverthel ess, semiconductor devices in general can malfunction or fail due to their inherent el ectrical sensitivity and vul nerability to physical stre ss. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of sa fety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, pleas e ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling gui de for semiconductor devices,? or ?toshiba se miconductor reliability handbook? etc. 021023_a ? the toshiba products listed in this document are intended for usage in general electronics applic ations (computer, personal eq uip- ment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neithe r intended nor warranted for usage in equipment that requires extr aordinarily high quality and/or re liability or a malfunctionor failure of which may cause loss of human life or bod ily injury (?unintended usage?). unintended us age include atomic energy control instru ments, airplane or spaceship instruments, transporta tion instruments, traffic signal instrume nts, combustion control instruments, medi cal instru- ments, all types of safety dev ices, etc. unintended usage of toshiba products li sted in this document shall be made at the cust omer's own risk. 021023_b ? the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and /or sale are prohibited under any appl icable laws and regulations. 060106_q ? the information contained herein is present ed only as a guide for the applications of our products. no responsibility is assum ed by toshiba for any infringements of patents or other rights of the th ird parties which may result from its use. no license is gran ted by impli- cation or otherwise under any patent or patent rights of toshiba or others. 021023_c ? the products described in this document are subjec t to the foreign exchange and foreign trade laws. 021023_e ? for a discussion of how the reliability of microcontrollers c an be predicted, please refer to section 1.3 of the chapter entit led quality and reliability assurance/h andling precautions. 030619_s this product uses the super flash ? technology under the licence of silicon storage technology, inc. super flash ? is registered trademark of silicon storage technology, inc. TMP86FH12MG the TMP86FH12MG is a single-chip 8-bit high-speed and high-functionality microcomputer incorporating 16384 bytes of flash memory. it is pin-compatible with the tmp86ch12mg (mask rom version). the TMP86FH12MG can realize operations equivalent to those of the tmp86ch12mg by programming the on-chip flash memory. 1.1 features 1. 8-bit single chip microcomputer tlcs-870/c series - instruction execution time : 0.25 s (at 16 mhz) 122 s (at 32.768 khz) - 132 types & 731 basic instructions 2. 22interrupt sources (external : 6 internal : 16) 3. input / output ports (24 pins) large current output: 8pins (typ. 20ma), led direct drive 4. watchdog timer 5. prescaler - time base timer - divider output function 6. 10-bit timer counter: 1ch (2 output pins) 2ports output ppg (programmed pulse generator) 50%duty output mode variable duty output mode external-triggered start and stop product no. rom (flash) ram package mask rom mcu emulation chip TMP86FH12MG 16384 bytes 512 bytes p-ssop30-56-0.65 tmp86ch12mg tmp86c912xb page 2 1.1 features TMP86FH12MG emargency stop pin 7. 16-bit timer counter: 1 ch - timer, external trigger, wi ndow, pulse width measurement, event counter, programmable pulse generate (ppg) modes 8. 8-bit timer counter : 2 ch - timer, event counter, programmable divider output (pdo), pulse width modulation (pwm) output, programmable pulse generation (ppg) modes 9. 8-bit sio: 1 ch 10. 8-bit uart : 1 ch 11. 10-bit successive approximation type ad converter - analog input: 8 ch 12. key-on wakeup : 4 ch 13. clock operation single clock mode dual clock mode 14. low power consumption operation stop mode: oscillation stops. (battery/capacitor back-up.) slow1 mode: low power consumption operation usin g low-frequency clock.(high-frequency clock stop.) slow2 mode: low power consumption operation usin g low-frequency clock.(high-frequency clock oscillate.) idle0 mode: cpu stops, and only the time-based-tim er(tbt) on peripherals operate using high fre- quency clock. release by falling edge of th e source clock which is set by tbtcr page 3 TMP86FH12MG 1.2 pin assignment figure 1-1 pin assignment 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 vss xout test vdd (xtin) p21 (xtout) p22 reset ( int5 / stop ) p20 (tc1/int4) p14 (txd) p00 xin (boot/rxd) p01 (si) p03 (so) p04 p05 (tc7) p07 (ppg2/int2) p10 (tc3/ pdo3/pwm3 ) p11 (tc4/ pdo4/pwm4/ppg4 ) p12 ( dvo ) ( sck ) p02 p06 (ppg1/int1) p32 (ain2) p34 (ain4/stop1) p35 (ain5/stop2) p37 (ain7) p36 (ain6/stop3) p33 (ain3/stop0) p31 (ain1/ int0 ) p30 (ain0/ emg ) p13 ( ppg /int3) page 4 1.3 block diagram TMP86FH12MG 1.3 block diagram figure 1-2 block diagram page 5 TMP86FH12MG 1.4 pin names and functions the TMP86FH12MG has mcu mode, parallel prom mode, and serial prom mode. table 1-1 shows the pin functions in mcu mode. the serial prom mode is explained later in a separate chapter. table 1-1 pin names and functions(1/2) pin name pin number input/output functions p07 ppg2 int2 18 io o i port07 timer counter 7 ppg2 output external interrupt 2 input p06 ppg1 int1 17 io o i port06 timer counter 7 ppg1 output external interrupt 1 input p05 tc7 16 io i port05 timer counter 7 input p04 so 15 io o port04 serial data output p03 si 14 io i port03 serial data input p02 sck 13 io io port02 serial clock i/o p01 rxd boot 12 io i i port01 uart data input serial prom mode control input p00 txd 11 io o port00 uart data output p14 int4 tc1 10 io i i port14 external interrupt 4 input tc1 input p13 ppg int3 22 io o i port13 ppg output external interrupt 3 input p12 dvo 21 io o port12 divider output p11 tc4 pdo4/pwm4/ppg4 20 io i o port11 tc4 input pdo4/pwm4/ppg4 output p10 tc3 pdo3/pwm3 19 io i o port10 tc3 input pdo3/pwm3 output p22 xtout 7 io o port22 resonator connecting pins(32.768 khz) for inputting external clock p21 xtin 6 io i port21 resonator connecting pins(32.768 khz) for inputting external clock p20 stop int5 9 io i i port20 stop mode release signal input external interrupt 5 input p37 ain7 30 io i port37 analog input7 page 6 1.4 pin names and functions TMP86FH12MG p36 ain6 stop3 29 io i i port36 analog input6 stop3 input p35 ain5 stop2 28 io i i port35 analog input5 stop2 input p34 ain4 stop1 27 io i i port34 analog input4 stop1 input p33 ain3 stop0 26 io i i port33 analog input3 stop0 input p32 ain2 25 io i port32 analog input2 p31 ain1 int0 24 io i i port31 analog input1 external interrupt 0 input p30 ain0 emg 23 io i i port30 analog input0 timer counter 7 emergency stop input xin 2 i resonator connecting pins for high-frequency clock xout 3 o resonator connecting pins for high-frequency clock reset 8 i reset signal test 4 i test pin for out-going test. normally, be fixed to low. vdd 5 i +5v vss 1 i 0(gnd) table 1-1 pin names and functions(2/2) pin name pin number input/output functions page 7 TMP86FH12MG 2. operational description 2.1 cpu core functions the cpu core consists of a cpu, a system cl ock controller, and an interrupt controller. this section provides a description of the cpu core, the program memory, the data memory, and the reset circuit. 2.1.1 memory address map the TMP86FH12MG memory is compos ed flash, ram, dbr(data buffer register) and sfr(special func- tion register). they are all mapped in 64-kbyte address space. figure 2-1 shows the TMP86FH12MG memory address map. figure 2-1 memory address map 2.1.2 program memory (flash) the TMP86FH12MG has a 16384 bytes (address c000h to ffffh) of program memory (flash ). sfr 0000 h 64 bytes sfr: ram: special function register includes: i/o ports peripheral control registers peripheral status registers system control registers program status word random access memory includes: data memory stack 003f h ram 0040 h 512 bytes 023f h dbr 0f80 h 128 bytes dbr: data buffer register includes: peripheral control registers peripheral status registers 0fff h c000 h flash: program memory flash 16384 bytes ffa0 h vector table for interrupts (32 bytes) ffbf h ffc0 h vector table for vector call instructions (32 bytes) ffdf h ffe0 h vector table for interrupts (32 bytes) ffff h page 8 2. operational description 2.2 system clock controller TMP86FH12MG 2.1.3 data memory (ram) the TMP86FH12MG has 512bytes (address 0040h to 023fh ) of internal ram. the first 192 bytes (0040h to 00ffh) of the internal ram are locat ed in the direct area; instructions with shorten operations are available against such an area. the data memory contents become un stable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. 2.2 system clock controller the system clock controller consists of a clock generator, a timing generator, and a standby controller. figure 2-2 syst em colck control 2.2.1 clock generator the clock generator generates the basic clock which pr ovides the system clocks supplied to the cpu core and peripheral hardware. it contains two oscillation ci rcuits: one for the high-frequency clock and one for the low-frequency clock. power consumption can be reduced by switching of the standby controller to low-power operation based on the low-frequency clock. the high-frequency (fc) clock and low-frequency (fs) clock can easily be obtained by connecting a resonator between the xin/xout and xtin/xtout pins respectively. clock input from an exte rnal oscillator is also possible. in this case, external clock is applied to xin/xtin pin with xout/xtout pin not connected. example :clears ram to ?00h?. (TMP86FH12MG) ld hl, 0040h ; start address setup ld a, h ; initial value (00h) setup ld bc, 01ffh sramclr: ld (hl), a inc hl dec bc jrs f, sramclr tbtcr syscr2 syscr1 xin xout xtin xtout fc 0036 h 0038 h 0039 h fs timing generator control register timing generator standby controller system clocks clock generator control high-frequency clock oscillator low-frequency clock oscillator clock generator system control registers page 9 TMP86FH12MG figure 2-3 examples of resonator connection note:the function to monitor the basic clock directly at external is not provided for hardware, however, with dis- abling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program. the system to require the adjustment of the oscilla tion frequency should create the program for the adjust- ment in advance. xout xin (open) xout xin xtout xtin (open) xtout xtin (a) crystal/ceramic resonator (b) external oscillator (c) crystal (d) external oscillator high-frequency clock low-frequency clock page 10 2. operational description 2.2 system clock controller TMP86FH12MG 2.2.2 timing generator the timing generator generates the various system cloc ks supplied to the cpu core and peripheral hardware from the basic clock (fc or fs). the timing generator provides the following functions. 1. generation of main system clock 2. generation of divider output ( dvo ) pulses 3. generation of source clocks for time base timer 4. generation of source clocks for watchdog timer 5. generation of internal source clocks for timer/counters 6. generation of warm-up clocks for releasing stop mode 2.2.2.1 configuration of timing generator the timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator, and machine cycle counters. an input clock to the 7th stage of the divider depends on the operating mode, syscr2 page 11 TMP86FH12MG note 1: in single clock mode, do not set dv7ck to ?1?. note 2: do not set ?1? on dv7ck while the low-frequency clock is not operated stably. note 3: fc: high-frequency clock [hz], fs : low-frequency clock [hz], *: don?t care note 4: in slow1/2 and sleep1/2 modes, the dv7ck setting is ineffective, and fs is input to the 7th stage of the divider. note 5: when stop mode is entered from normal1/2 mode, the dv 7ck setting is ineffective during the warm-up period after release of stop mode, and the 6th stage of the divider is input to the 7th stage during this period. 2.2.2.2 machine cycle instruction execution and peripheral hardware operat ion are synchronized with the main system clock. the minimum instruction execution uni t is called an ?machine cycle?. th ere are a total of 10 different types of instructions for the tlcs-870/c series: ra nging from 1-cycle instructions which require one machine cycle for execution to 10-cyc le instructions which require 10 machine cycles fo r execution. a machine cycle consists of 4 states (s0 to s3), and each state consists of one main system clock. figure 2-5 machine cycle 2.2.3 operation mode control circuit the operation mode control circuit starts and stops th e oscillation circuits for the high-frequency and low- frequency clocks, and switches the main system clock. there are three operating modes: single clock mode, dual clock mode and stop mode. these modes are cont rolled by the system cont rol registers (syscr1 and syscr2). figure 2-6 shows the operating mode transition diagram. 2.2.3.1 single-clock mode only the oscillation circuit for the high-frequenc y clock is used, and p21 (xtin) and p22 (xtout) pins are used as input/output ports . the main-system clock is obtained from the high-frequency clock. in the single-clock mode, the machine cycle time is 4/fc [s]. (1) normal1 mode in this mode, both the cpu core and on-chip pe ripherals operate using the high-frequency clock. the TMP86FH12MG is placed in this mode after reset. timing generator control register tbtcr (0036h) 76543210 (dvoen) (dvock) dv7ck (tbten) (tbtck) (initial value: 0000 0000) dv7ck selection of input to the 7th stage of the divider 0: fc/2 8 [hz] 1: fs r/w main system clock state machine cycle s3 s2 s1 s0 s3 s2 s1 s0 1/fc or 1/fs [s] page 12 2. operational description 2.2 system clock controller TMP86FH12MG (2) idle1 mode in this mode, the internal oscillation circuit remains active. the cpu and the watchdog timer are halted; however on-chip peripherals remain active (operate using the high-frequency clock). idle1 mode is started by syscr2 page 13 TMP86FH12MG switching back and forth between slow1 and slow2 modes are performed by syscr2 page 14 2. operational description 2.2 system clock controller TMP86FH12MG note 1: normal1 and normal2 modes are generically called no rmal; slow1 and slow2 are called slow; idle0, idle1 and idle2 are called idle; sleep0, sleep1 and sleep2 are called sleep. note 2: the mode is released by fa lling edge of tbtcr page 15 TMP86FH12MG note 1: always set retm to ?0? when transiting from normal mode to stop mode. always set retm to ?1? when transiting from slow mode to stop mode. note 2: when stop mode is released with reset pin input, a return is made to normal1 regardless of the retm contents. note 3: fc: high-frequency clock [hz], fs : low-frequency clock [hz], *; don?t care note 4: bits 1 and 0 in syscr1 are read as undefined data when a read instruction is executed. note 5: as the hardware becomes stop mode under outen = ?0?, input value is fixed to ?0?; therefore it may cause external interrupt request on account of falling edge. note 6: when the key-on wakeup is used, relm should be set to "1". note 7: port p20 is used as stop pin. therefore, when stop mode is started, outen does not affect to p20, and p20 becomes high-z mode. note 8: the warmig-up time should be set correctly for using oscillator. note 1: a reset is applied if both xen and xten are cleared to ?0?, xen is cleared to ?0? when sysck = ?0?, or xten is cleared to ?0? when sysck = ?1?. note 2: *: don?t care, tg: timing generator, *; don?t care note 3: bits 3, 1 and 0 in syscr2 are always read as undefined value. note 4: do not set idle and tghalt to ?1? simultaneously. note 5: because returning from idle0/sleep0 to normal1/slow 1 is executed by the asynchronous internal clock, the period of idle0/sleep0 mode might be shorter than the period setting by tbtcr page 16 2. operational description 2.2 system clock controller TMP86FH12MG 2.2.4 operating mode control 2.2.4.1 stop mode stop mode is controlled by the system control register 1, the stop pin input and key-on wakeup input (stop3 to stop0) which is controlled by the stop mode release control register (stopcr). the stop pin is also used both as a port p20 and an int5 (external interrupt input 5) pin. stop mode is started by setting syscr1 page 17 TMP86FH12MG figure 2-7 level-s ensitive release mode note 1: even if the stop pin input is low after warm-up start, the stop mode is not restarted. note 2: in this case of changing to the level-s ensitive mode from the edge-s ensitive mode, the release mode is not switched until a rising edge of the stop pin input is detected. (2) edge-sensitive release mode (relm = ?0?) in this mode, stop mode is released by a rising edge of the stop pin input. this is used in appli- cations where a relatively short pr ogram is executed repeat edly at periodic intervals. this periodic signal (for example, a clock from a low-power consumption oscillator) is input to the stop pin. in the edge-sensitive release mode, stop mode is started even when the stop pin input is high level. do not use any stop3 to stop0 pin input for releasing stop mode in edge-sensitive release mode. figure 2-8 edge-sensitive release mode example 2 :starting stop mode from normal mode with an int5 interrupt. pint5: test (p2prd). 0 ; to reject noise, stop mode does not start if jrs f, sint5 port p20 is at high ld (syscr1), 01010000b ; sets up the level-sensitive release mode. di ; imf 0 set (syscr1). 7 ; starts stop mode sint5: reti example :starting stop mode from normal mode di ; imf 0 ld (syscr1), 10010000b ; starts after specified to the edge-sensitive release mode v ih normal operation warm up stop operation confirm by program that the stop pin input is low and start stop mode. always released if the stop pin input is high. stop pin xout pin stop mode is released by the hardware. normal operation normal operation normal operation v ih stop mode is released by the hardware at the rising edge of stop pin input. warm up stop mode started by the program. stop operation stop operation stop pin xout pin page 18 2. operational description 2.2 system clock controller TMP86FH12MG stop mode is released by the following sequence. 1. in the dual-clock mode, when returning to normal2, both the high-frequency and low- frequency clock oscillators are turned on; when returning to slow1 mode, only the low- frequency clock oscillator is turned on. in the single-clock mode, only the high-frequency clock oscillator is turned on. 2. a warm-up period is inserted to allow oscillation time to stabilize. during warm up, all internal operations remain halted. four differ ent warm-up times can be selected with the syscr1 page 19 TMP86FH12MG figure 2-9 stop mode start/release instruction address a + 4 0 instruction address a + 3 turn on turn on warm up 0 n halt set (syscr1). 7 turn off (a) stop mode start (example: start with set (syscr1). 7 instruction located at address a) a + 6 a + 5 a + 4 a + 3 a + 2 n + 2 n + 3 n + 4 a + 3 n + 1 instruction address a + 2 2 1 0 3 (b) stop mode release count up turn off halt oscillator circuit program counter instruction execution divider main system clock oscillator circuit stop pin input program counter instruction execution divider main system clock page 20 2. operational description 2.2 system clock controller TMP86FH12MG 2.2.4.2 idle1/2 mode and sleep1/2 mode idle1/2 and sleep1/2 modes are controlled by the system control register 2 (syscr2) and maskable interrupts. the following status is maintained during these modes. 1. operation of the cpu and watchdog timer (wdt) is halted. on-chip peripherals continue to operate. 2. the data memory, cpu registers, program status word and port output latches are all held in the status in effect before these modes were entered. 3. the program counter holds the address 2 ahead of th e instruction which starts these modes. figure 2-10 idle1/ 2 and sleep1/2 modes reset reset input ?0? ?1? (interrupt release mode) yes no no cpu and wdt are halted interrupt request imf interrupt processing normal release mode yes starting idle1/2 and sleep1/2 modes by instruction execution of the instruc- tion which follows the idle1/2 and sleep1/2 modes start instruction page 21 TMP86FH12MG ? start the idle1/2 and sleep1/2 modes after imf is set to "0", set the individual inte rrupt enable flag (ef) which releases idle1/2 and sleep1/2 modes. to start idle1/2 and sl eep1/2 modes, set syscr2 page 22 2. operational description 2.2 system clock controller TMP86FH12MG figure 2-11 idle1/2 and sleep1/2 modes start/release halt halt halt halt operate instruction address a + 2 a + 3 a + 2 a + 4 a + 3 a + 3 halt set (syscr2). 4 operate operate operate acceptance of interrupt ?r:w normal release mode ?s:w interrupt release mode main system clock interrupt request program counter instruction execution watchdog timer main system clock interrupt request program counter instruction execution watchdog timer main system clock interrupt request program counter instruction execution watchdog timer (a) idle1/2 and sleep1/2 modes start (example: star ting with the set instruction located at address a) (b) idle1/2 and sleep1/2 modes release page 23 TMP86FH12MG 2.2.4.3 idle0 and sleep0 modes (idle0, sleep0) idle0 and sleep0 modes are controlled by the system control register 2 (syscr2) and the time base timer control register (tbtcr). the following stat us is maintained during idle0 and sleep0 modes. 1. timing generator stops feeding clock to peripherals except tbt. 2. the data memory, cpu registers, program status word and port output latches are all held in the status in effect before idle0 and sleep0 modes were entered. 3. the program counter holds the address 2 ahead of the instru ction which starts idle0 and sleep0 modes. note: before starting idle0 or sleep0 mode, be sure to stop (disable) peripherals. figure 2-12 idle 0 and sleep0 modes yes (normal release mode) yes (interrupt release mode) no yes reset input cpu and wdt are halted reset tbt source clock falling edge tbtcr page 24 2. operational description 2.2 system clock controller TMP86FH12MG ? start the idle0 and sleep0 modes stop (disable) peripherals such as a timer counter. to start idle0 and sleep0 modes, set syscr2 page 25 TMP86FH12MG figure 2-13 idle0 and slee p0 modes start/release halt halt operate instruction address a + 2 halt operate set (syscr2). 2 halt operate acceptance of interrupt halt ?r:w normal release mode ?s:w interrupt release mode main system clock interrupt request program counter instruction execution watchdog timer main system clock tbt clock tbt clock program counter instruction execution watchdog timer main system clock program counter instruction execution watchdog timer a + 3 a + 2 a + 4 a + 3 a + 3 (a) idle0 and sleep0 modes start (example: starting with the set instruction located at address a (b) idle and sleep0 modes release page 26 2. operational description 2.2 system clock controller TMP86FH12MG 2.2.4.4 slow mode slow mode is controlled by the sy stem control register 2 (syscr2). the following is the methods to switch the mode with the warm-up counter. (1) switching from normal2 mode to slow1 mode first, set syscr2 page 27 TMP86FH12MG (2) switching from slow1 mode to normal2 mode note: after sysck is cleared to ?0?, executing the in structions is continiued by the low-frequency clock for the period synchronized with low-frequency and high-frequency clocks. first, set syscr2 page 28 2. operational description 2.2 system clock controller TMP86FH12MG figure 2-14 switching between the normal2 and slow modes set (syscr2). 7 normal2 mode clr (syscr2). 7 set (syscr2). 5 normal2 mode turn off (a) switching to the slow mode slow1 mode slow2 mode clr (syscr2). 5 (b) switching to the normal2 mode high- frequency clock low- frequency clock main system clock instruction execution sysck xen high- frequency clock low- frequency clock main system clock instruction execution sysck xen slow1 mode warm up during slow2 mode page 29 TMP86FH12MG 2.3 reset circuit the TMP86FH12MG has four types of re set generation procedures: an external reset input, an address trap reset, a watchdog timer reset and a system cloc k reset. of these reset, the address trap reset, the watchdog timer and the system clock reset are a malfunction re set. when the malfunction reset request is detected, reset occurs during the maximum 24/fc[s]. the malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initial- ized when power is turned on. therefore, reset may occur during maximum 24/fc[s] (1.5 s at 16.0 mhz) when power is turned on. table 2-3 shows on-chip hardware initialization by reset action. 2.3.1 external reset input the reset pin contains a schmitt trigger (hysteresis) with an internal pull-up resistor. when the reset pin is held at ?l? level for at least 3 machin e cycles (12/fc [s]) wi th the power supply volt- age within the operating voltage range and oscillation stab le, a reset is applied and the internal state is initial- ized. when the reset pin input goes high, the reset operation is rele ased and the program execution starts at the vector address stored at addresses fffeh to ffffh. figure 2-15 reset circuit table 2-3 initializing internal status by reset action on-chip hardware initial value on-chip hardware initial value program counter (pc) (fffeh) prescaler and divider of timing generator 0 stack pointer (sp) not initialized general-purpose registers (w, a, b, c, d, e, h, l, ix, iy) not initialized jump status flag (jf) not initialized watchdog timer enable zero flag (zf) not initialized output latches of i/o ports refer to i/o port circuitry carry flag (cf) not initialized half carry flag (hf) not initialized sign flag (sf) not initialized overflow flag (vf) not initialized interrupt master enable flag (imf) 0 interrupt individual enable flags (ef) 0 control registers refer to each of control register interrupt latches (il) 0 ram not initialized internal reset reset vdd malfunction reset output circuit watchdog timer reset address trap reset system clock reset page 30 2. operational description 2.3 reset circuit TMP86FH12MG 2.3.2 address trap reset if the cpu should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip ram (when wdtcr1 page 31 TMP86FH12MG page 32 2. operational description 2.3 reset circuit TMP86FH12MG page 33 TMP86FH12MG 3. interrupt control circuit the TMP86FH12MG has a total of 22 interrupt sources excl uding reset. interrupts can be nested with priorities. four of the internal interrupt sources ar e non-maskable while the rest are maskable. interrupt sources are provided with interrupt latches (il) , which hold interrupt requests, and independent vectors. the interrupt latch is set to ?1? by th e generation of its interrupt request wh ich requests the cpu to accept its inter- rupts. interrupts are enabled or disabled by software using the interrupt master enable fl ag (imf) and in terrupt enable flag (ef). if more than one interrupts are generated simultaneously, interrup ts are accepted in order which is domi- nated by hardware. however, there are no prioritized interrupt factors among non-maskable interrupts. note 1: to use the address trap interrupt (intatrap), clear wdtcr1 page 34 3. interrupt control circuit 3.1 interrupt latches (il28 to il2) TMP86FH12MG 3.1 interrupt latches (il28 to il2) an interrupt latch is provided for eac h interrupt source, except for a software interrupt and an executed the unde- fined instruction interrupt. when interrupt request is genera ted, the latch is set to ?1?, and the cpu is requested to accept the interrupt if its interrupt is enabled. the interrupt latch is cleared to "0" immediately after accepting inter- rupt. all interrupt latches are initialized to ?0? during reset. the interrupt latches are located on address 002eh, 002fh, 003ch and 003dh in sfr area. each latch can be cleared to "0" individually by instruction. however, il2 and il3 should not be cleared to "0" by software. for clear- ing the interrupt latch, load instruction should be used and then il2 and il3 should be set to "1". if the read-modify- write instructions such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately if interrupt is requeste d while such instructions are executed. interrupt latches are not set to ?1? by an instruction. since interrupt latches can be read, the status fo r interrupt requests can be monitored by software. note: in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf new ly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0 " automatically, clearing imf need not execute normally on interrupt service routine. however, if using multiple inte rrupt on interrupt service routine, manipulating ef or il should be executed before setting imf="1". 3.2 interrupt enab le register (eir) the interrupt enable register (eir) enables and disables the acceptance of interrupts, except fo r the non-maskable interrupts (software interrupt, undefined instruction interr upt, address trap interrupt and watchdog interrupt). non- maskable interrupt is accepted regardless of the contents of the eir. the eir consists of an interrupt mast er enable flag (imf) and the individua l interrupt enable flags (ef). these registers are located on address 002ch, 002dh, 003ah and 003bh in sfr area, and they can be read and written by an instructions (including read-modify-write instruc tions such as bit manipulation or operation instructions). 3.2.1 interrupt ma ster enable flag (imf) the interrupt enable register (imf ) enables and disables the acceptance of the whole maskable interrupt. while imf = ?0?, all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag (ef). by setting imf to ?1?, the interrupt becomes acceptable if the individuals are enabled. when an interrupt is accepted, imf is cleared to ?0? after the latest status on imf is stacked. thus the maskable inter- rupts which follow are disabled. by executing return interrupt instruction [reti/retn], the stacked data, which was the status before interrup t acceptance, is loaded on imf again. the imf is located on bit0 in eirl (address: 003ah in sfr), and can be read and written by an instruction. the imf is normally set and cl eared by [ei] and [di] instruction respectively. during reset, the imf is initial- ized to ?0?. example 1 :clears interrupt latches di ; imf 0 ldw (ill), 111010000011 1111b ; il12, il10 to il6 0 ei ; imf 1 example 2 :reads interrupt latchess ld wa, (ill) ; w ilh, a ill example 3 :tests interrupt latches test (ill). 7 ; if il7 = 1 then jump jr f, sset page 35 TMP86FH12MG 3.2.2 individual interrupt enable flags (ef28 to ef4) each of these flags enables and disables the acceptan ce of its maskable interrupt . setting the corresponding bit of an individual interrupt enable flag to ?1? enables acceptan ce of its interrupt, and setting the bit to ?0? dis- ables acceptance. during reset, all the i ndividual interrupt enable flags (ef28 to ef4) ar e initialized to ?0? and all maskable interrupts are not accepted until they are set to ?1?. note:in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf become s "0" automatically, clearing imf need not execute nor- mally on interrupt service routine. however, if using mult iple interrupt on interrupt service routine, manipulat- ing ef or il should be executed before setting imf="1". example 1 :enables interrupts individually and sets imf di ; imf 0 ldw : (eirl), 1110100010100000b ; ef15 to ef13, ef11, ef7, ef5 1 note: imf should not be set. : ei ; imf 1 example 2 :c compiler description example unsigned int _io (3ah) eirl; /* 3ah shows eirl address */ _di(); eirl = 10100000b; : _ei(); page 36 3. interrupt control circuit 3.2 interrupt enable register (eir) TMP86FH12MG note 1: to clear any one of bits il7 to il4, be sure to write "1" into il2 and il3. note 2: in main program, before manipulating the interrupt enable fl ag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clear ing imf need not execute normally on inter- rupt service routine. however, if using multiple interrupt on interrupt service routine, mani pulating ef or il should be exe- cuted before setting imf="1". note 3: do not clear il with read-modify-w rite instructions such as bit operations. note 1: *: don?t care note 2: do not set imf and the interrupt enable flag (ef15 to ef4) to ?1? at the same time. note 3: in main program, before manipulating the interrupt enable fl ag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clear ing imf need not execute normally on inter- rupt service routine. however, if using multiple interrupt on interrupt service routine, mani pulating ef or il should be exe- cuted before setting imf="1". interrupt latches (initial value: *00*0000 00*000**) ilh,ill (003dh, 003ch) 1514131211109876543210 ? il14 il13 ? il11 il10 il9 il8 il7 il6 ? il4 il3 il2 ilh (003dh) ill (003ch) (initial value: ***00*** 0000000*) ild,ile (002fh, 002eh) 1514131211109876543210 ??? il28 il27 ??? il23 il22 il21 il20 il19 il18 il17 ? ild (002fh) ile (002eh) il28 to il2 interrupt latches at rd 0: no interrupt request 1: interrupt request at wr 0: clears the interrupt request 1: (interrupt latch is not set.) r/w interrupt enable registers (initial value: *00*0000 00*0***0) eirh,eirl (003bh, 003ah) 1514131211109876543210 ? ef14 ef13 ? ef11 ef10 ef9 ef8 ef7 ef6 ? ef4 imf eirh (003bh) eirl (003ah) (initial value: ***00*** 0000000*) eird,eire (002dh, 002ch) 1514131211109876543210 ??? ef28 ef27 ??? ef23 ef22 ef21 ef20 ef19 ef18 ef17 ? eird (002dh) eire (002ch) ef28 to ef4 individual-interrupt enable flag (specified for each bit) 0: 1: disables the acceptance of each maskable interrupt. enables the acceptance of each maskable interrupt. r/w imf interrupt master enable flag 0: 1: disables the acceptance of all maskable interrupts enables the acceptance of all maskable interrupts page 37 TMP86FH12MG 3.3 interrupt sequence an interrupt request, which raised inte rrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to ?0? by resetting or an instruct ion. interrupt acceptance sequence requires 8 machine cycles (2 s @16 mhz) after the completion of the current instruction. the interrupt service task terminates upon execution of an interrupt return instruction [reti] (for maskable interrupts) or [retn] (for non-maskable interrupts). figure 3-1 shows the timing chart of interrupt acceptance processing. 3.3.1 interrupt acceptance proc essing is packaged as follows. a. the interrupt master enab le flag (imf) is cleared to ?0? in or der to disable the acceptance of any fol- lowing interrupt. b. the interrupt latch (il) for the interrupt source accepted is cleared to ?0?. c. the contents of the program coun ter (pc) and the program status word, including the interrupt master enable flag (imf), are saved (pushed) on the st ack in sequence of psw + imf, pch, pcl. mean- while, the stack pointer (s p) is decremented by 3. d. the entry address (interrupt vect or) of the corresponding interrupt service program, loaded on the vec- tor table, is transferred to the program counter. e. the instruction stored at the entry address of the inte rrupt service program is executed. note:when the contents of psw are saved on the stack, the contents of imf are also saved. note 1: a: return address entry address, b: entry address, c: address which reti instruction is stored note 2: on condition that interrupt is enabled, it takes 38/fc [s ] or 38/fs [s] at maximum (if the interrupt latch is set at the first machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set. figure 3-1 timing chart of interrupt acceptance/return in terrupt instruction example: correspondence be tween vector table address for inttbt an d the entry address of the interrupt service program figure 3-2 vector table address,entry address a b a c + 1 execute instruction sp pc execute instruction n n ? 2 n - 3 n ? 2n ? 1 n ? 1 n a + 2 a + 1 c + 2 b + 3 b + 2 b + 1 a + 1 a a ? 1 execute reti instruction interrupt acceptance execute instruction interrupt service task 1-machine cycle interrupt request interrupt latch (il) imf d2h 03h d203h d204h 06h vector table address entry address 0fh vector interrupt service program ffech ffedh page 38 3. interrupt control circuit 3.3 interrupt sequence TMP86FH12MG a maskable interrupt is not accepted until the imf is set to ?1? even if th e maskable interrupt higher than the level of current servicing interrupt is requested. in order to utilize nested interrupt service, the imf is set to ?1? in the interrupt service program. in this case, acceptable interrupt sources are selectively en abled by the individual interrupt enable flags. to avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting imf to ?1?. as for non-maskable interr upt, keep interrupt service shorten compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested. 3.3.2 saving/restoring general-purpose registers during interrupt acceptance processing , the program counter (pc) and the program status word (psw, includes imf) are automati cally saved on the stack, but the accumulato r and others are not. these registers are saved by software if necessary. when multiple interrupt se rvices are nested, it is also necessary to avoid using the same data memory area for saving registers. the fo llowing methods are used to save/restore the general- purpose registers. 3.3.2.1 using push and pop instructions if only a specific register is saved or interrupts of the same source are nested , general-purpose registers can be saved/restored using the push/pop instructions. figure 3-3 save/store register using push and pop instructions 3.3.2.2 using data transfer instructions to save only a specific register wi thout nested interrupts, data tran sfer instructions are available. example :save/store register us ing push and pop instructions pintxx: push wa ; save wa register (interrupt processing) pop wa ; restore wa register reti ; return pcl pch psw at acceptance of an interrupt at execution of push instruction at execution of reti instruction at execution of pop instruction b-4 b-3 b-2 b-1 b pcl pch psw pcl pch psw sp address (example) sp sp sp a w b-5 page 39 TMP86FH12MG figure 3-4 saving/restoring general-purpose r egisters under interrupt processing 3.3.3 interrupt return interrupt return instructions [reti]/[retn] perform as follows. as for address trap interrupt (intatrap), it is requir ed to alter stacked data for program counter (pc) to restarting address, during interrupt service program. note:if [retn] is executed with the above data unaltered, the program returns to the address trap area and intatrap occurs again.when interrupt acceptance pr ocessing has completed, stacked data for pcl and pch are located on address (sp + 1) and (sp + 2) respectively. example :save/store register us ing data transfer instructions pintxx: ld (gsava), a ; save a register (interrupt processing) ld a, (gsava) ; restore a register reti ; return [reti]/[retn] interrupt return 1. program counter (pc) and program status word (psw, includes imf) are restored from the stack. 2. stack pointer (sp) is incremented by 3. example 1 :returning from address trap interrupt (intatrap) service program pintxx: pop wa ; recover sp by 2 ld wa, return address ; push wa ; alter stacked data (interrupt processing) retn ; return interrupt acceptance interrupt service task restoring registers saving registers interrupt return saving/restoring general-purpose registers using push/pop data transfer instruction main task page 40 3. interrupt control circuit 3.4 software interrupt (intsw) TMP86FH12MG interrupt requests are sampled during the final cycle of the instruction being executed. thus, the next inter- rupt can be accepted immediat ely after the interrupt retu rn instruction is executed. note 1: it is recommended that stack pointer be return to rate before intatrap (increment 3 times), if return inter- rupt instruction [retn] is not utilized during inte rrupt service program under intatrap (such as example 2). note 2: when the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task. 3.4 software interrupt (intsw) executing the swi instruction generates a software interr upt and immediately starts interrupt processing (intsw is highest prioritized interrupt). use the swi instruction only for detection of the address error or for debugging. 3.4.1 address error detection ffh is read if for some cause such as noise the cpu attempts to fetch an instruction from a non-existent memory address during single chip mode. code ffh is th e swi instruction, so a software interrupt is gener- ated and an address error is detect ed. the address error detection range can be further expanded by writing ffh to unused areas of the program memory. address trap reset is generated in case that an instruction is fetched from ram, dbr or sfr areas. 3.4.2 debugging debugging efficiency can be increased by placing the swi instruction at the software break point setting address. 3.5 undefined instruct ion interrupt (intundef) taking code which is not defined as authorized instru ction for instruction causes intundef. intundef is gen- erated when the cpu fetches such a co de and tries to execute it. intundef is accepted even if non-maskable inter- rupt is in process. contemporary process is broken and intundef interrupt process starts, soon after it is requested. note: the undefined instruction interrupt (intundef) forces cpu to jump into vector address, as software interrupt (swi) does. 3.6 address trap interrupt (intatrap) fetching instruction from unauthorized area for instructio ns (address trapped area) cause s reset output or address trap interrupt (intatrap). intatrap is accepted even if non-maskable interrupt is in process. contemporary pro- cess is broken and intatrap interrupt pro cess starts, soon afte r it is requested. note: the operating mode under address trapped, whether to be reset output or interrupt processing, is selected on watchdog timer control register (wdtcr). example 2 :restarting without returning interrupt (in this case, psw (includes imf) befo re interrupt acceptance is discarded.) pintxx: inc sp ; recover sp by 3 inc sp ; inc sp ; (interrupt processing) ld eirl, data ; set imf to ?1? or clear it to ?0? jp restart address ; jump into restarting address page 41 TMP86FH12MG 3.7 external interrupts the TMP86FH12MG has 6 external interrupt inputs. these in puts are equipped with di gital noise reject circuits (pulse inputs of less than a certa in time are elimin ated as noise). edge selection is also possible with int1 to int4. the int0 /p31 pin can be configured as either an external inter- rupt input pin or an input/output port, and is configured as an input port during reset. edge selection, noise reject control and int0 /p31 pin function selection are performed by the external interrupt control register (eintcr). note 1: in normal1/2 or idle1/2 mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "si g- nal establishment time + 6/fs[s]" from the input signal's edge to set the interrupt latch. note 2: when int0en = "0", il6 is not set even if a falling edge is detected on the int0 pin input. note 3: when a pin with more than one function is used as an out put and a change occurs in data or input/output status, an inter - rupt request signal is generated in a pseudo manner. in this ca se, it is necessary to perform appropriate processing such as disabling the interrupt enable flag. source pin enable conditions release edge (level) digital noise reject int0 int0 imf ? ef6 ? int0en=1 falling edge pulses of less than 2/fc [s] are eliminated as noise. pulses of 7/fc [s ] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are consid- ered to be signals. int1 int1 imf ? ef8 = 1 falling edge or rising edge pulses of less than 15/fc or 63/fc [s] are elimi- nated as noise. pulses of 49/fc or 193/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are considered to be signals. int2 int2 imf ? ef10 = 1 falling edge or rising edge pulses of less than 7/fc [s] are eliminated as noise. pulses of 25/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are consid- ered to be signals. int3 int3 imf ? ef17 = 1 falling edge or rising edge pulses of less than 7/fc [s] are eliminated as noise. pulses of 25/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are consid- ered to be signals. int4 int4 imf ? ef22 = 1 falling edge, rising edge, falling and rising edge or h level pulses of less than 7/fc [s] are eliminated as noise. pulses of 25/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are consid- ered to be signals. int5 int5 imf ? ef28 = 1 falling edge pulses of less than 2/fc [s] are eliminated as noise. pulses of 7/fc [s ] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are consid- ered to be signals. page 42 3. interrupt control circuit 3.7 external interrupts TMP86FH12MG note 1: fc: high-frequency clock [hz], *: don?t care note 2: when the system clock frequency is switched between high and low or when the external interrupt control register (eintcr) is overwritten, the noise canceller may not operat e normally. it is recommended that external interrupts are dis- abled using the interrupt enable register (eir). note 3: the maximum time from modifying int1 nc until a noise reject time is changed is 2 6 /fc. note 4: in case reset pin is released while the state of int4 pin keeps "h" level, the external interrupt 4 request is not generated even if the int4 edge select is specified as "h" level. the rising edge is needed after reset pin is released. external interrupt control register eintcr76543210 (0037h) int1nc int0en int4es int3es int2es int1es (initial value: 0000 000*) int1nc noise reject time select 0: pulses of less than 63/fc [s] are eliminated as noise 1: pulses of less than 15/fc [s] are eliminated as noise r/w int0en p31/ int0 pin configuration 0: p31 input/output port 1: int0 pin (port p31 should be set to an input mode) r/w int4 es int4 edge select 00: rising edge 01: falling edge 10: rising edge and falling edge 11: h level r/w int3 es int3 edge select 0: rising edge 1: falling edge r/w int2 es int2 edge select 0: rising edge 1: falling edge r/w int1 es int1 edge select 0: rising edge 1: falling edge r/w page 43 TMP86FH12MG 4. special function register (sfr) the TMP86FH12MG adopts the memory mapp ed i/o system, and all peripheral control and data transfers are per- formed through the special function register (sfr) or the data buffer register (dbr). the sfr is mapped on address 0000h to 003fh, dbr is mapped on address 0f80h to 0fffh. this chapter shows the arrangement of the special functi on register (sfr) and data buffer register (dbr) for TMP86FH12MG. 4.1 sfr address read write 0000h p0dr 0001h p1dr 0002h p2dr 0003h p3dr 0004h p0outcr 0005h p1cr 0006h p3cr1 0007h p3cr2 0008h tc7dral 0009h tc7drah 000ah tc7drbl 000bh tc7drbh 000ch tc7drcl 000dh tc7drch 000eh p0prd - 000fh p2prd - 0010h tc1dral 0011h tc1drah 0012h tc1drbl 0013h tc1drbh 0014h tc1cr 0015h tc3cr 0016h tc4cr 0017h pwreg3 0018h pwreg4 0019h ttreg3 001ah ttreg4 001bh rtccr 001ch reserved 001dh reserved 001eh reserved 001fh adcdr2 - 0020h adcdr1 - 0021h uartsr uartcr1 0022h - uartcr2 0023h reserved 0024h reserved 0025h adccr1 page 44 4. special function register (sfr) 4.1 sfr TMP86FH12MG note 1: do not access reserved areas by the program. note 2: ? ; cannot be accessed. note 3: write-only registers and interrupt latches cannot use the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical operation instructions such as and, or, etc.). 0026h adccr2 0027h reserved 0028h reserved 0029h tc7cr1 002ah tc7cr2 002bh tc7cr3 002ch eire 002dh eird 002eh ile 002fh ild 0030h reserved 0031h - siocr1 0032h siosr siocr2 0033h reserved 0034h - wdtcr1 0035h - wdtcr2 0036h tbtcr 0037h eintcr 0038h syscr1 0039h syscr2 003ah eirl 003bh eirh 003ch ill 003dh ilh 003eh reserved 003fh psw address read write page 45 TMP86FH12MG 4.2 dbr address read write 0f80h siobr0 0f81h siobr1 0f82h siobr2 0f83h siobr3 0f84h siobr4 0f85h siobr5 0f86h siobr6 0f87h siobr7 0f88h - stopcr 0f89h rdbuf tdbuf 0f8ah reserved 0f8bh reserved 0f8ch reserved 0f8dh reserved 0f8eh reserved 0f8fh reserved 0f90h reserved 0f91h reserved 0f92h reserved 0f93h reserved 0f94h reserved 0f95h reserved 0f96h reserved 0f97h reserved 0f98h reserved 0f99h reserved 0f9ah reserved 0f9bh reserved 0f9ch reserved 0f9dh reserved 0f9eh reserved 0f9fh reserved page 46 4. special function register (sfr) 4.2 dbr TMP86FH12MG address read write 0fa0h reserved 0fa1h reserved 0fa2h reserved 0fa3h reserved 0fa4h reserved 0fa5h reserved 0fa6h reserved 0fa7h reserved 0fa8h reserved 0fa9h reserved 0faah reserved 0fabh reserved 0fach reserved 0fadh reserved 0faeh reserved 0fafh reserved 0fb0h tc7drdl 0fb1h tc7drdh 0fb2h tc7drel 0fb3h tc7dreh 0fb4h tc7capal - 0fb5h tc7capah - 0fb6h tc7capbl - 0fb7h tc7capbh - 0fb8h reserved 0fb9h reserved 0fbah reserved 0fbbh reserved 0fbch reserved 0fbdh reserved 0fbeh reserved 0fbfh reserved address read write 0fc0h reserved : : : : 0fdfh reserved page 47 TMP86FH12MG note 1: do not access reserved areas by the program. note 2: ? ; cannot be accessed. note 3: write-only registers and interrupt latches cannot use the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical operation instructions such as and, or, etc.). address read write 0fe0h reserved 0fe1h reserved 0fe2h reserved 0fe3h reserved 0fe4h reserved 0fe5h reserved 0fe6h reserved 0fe7h reserved 0fe8h reserved 0fe9h - flsstb 0feah spcr 0febh reserved 0fech reserved 0fedh reserved 0feeh reserved 0fefh reserved 0ff0h reserved 0ff1h reserved 0ff2h reserved 0ff3h reserved 0ff4h reserved 0ff5h reserved 0ff6h reserved 0ff7h reserved 0ff8h reserved 0ff9h reserved 0ffah reserved 0ffbh reserved 0ffch reserved 0ffdh reserved 0ffeh reserved 0fffh flscr page 48 4. special function register (sfr) 4.2 dbr TMP86FH12MG page 49 TMP86FH12MG 5. i/o ports the TMP86FH12MG has 4 parallel input/output ports (24 pins) as follows. each output port contains a latch, which holds the output data. all input ports do not have latches, so the external input data should be externally held until the input data is read from outside or reading should be performed several timer before processing. figure 5-1 shows input/output timing examples. external data is read from an i/o port in the s1 state of the read cycle during execution of the read instruction. this timing cannot be recognized from outside, so that transient input such as chattering must be processed by the pro- gram. output data changes in the s2 state of the write cycle du ring execution of the instruct ion which writes to an i/o port. note: the positions of the read and write c ycles may vary, depending on the instruction. figure 5-1 input/output timing (example) primary function secondary functions port p0 8-bit i/o port external interrupt, serial interface input/output, uart input/output and timer counter input/output. port p1 5-bit i/o port external interrupt and timer counter input/output. port p2 3-bit i/o port low-frequency resonator connections, external interrupt input, stop mode release signal input. port p3 8-bit i/o port external interrupt, anal og input and stop mode release signal input. data output data input new old example: ld a, (x) fetch cycle read cycle fetch cycle s0 s1 s2 s3 s0 s1 s2 s3 s0 s1 s2 s3 instruction execution cycle input strobe (a) input timing example: ld (x), a fetch cycle write cycle fetch cycle s0 s1 s2 s3 s0 s1 s2 s3 s0 s1 s2 s3 (b) output timing instruction execution cycle output strobe page 50 5. i/o ports 5.1 port p0 (p07 to p00) TMP86FH12MG 5.1 port p0 (p07 to p00) port p0 is an 8-bit input/output port. port p0 is also used as an external interrupt input, a serial interface input/output, an uart input/output and a timer/counter input/output. it can be selected whether output circuit of p0 port is a c-mos output or a sink open drain individually, by setting p0outcr. during reset, the p0dr is initialized to "1", and the p0outcr is initialized to "0". when a correspond- ing bit of p0outcr is "0". the output circuit is selected to a sink open drain and when a corresponding bit of p0outcr is "1", the output circuit is selected to a c-mos output. when used as an input port, an exte rnal interrupt input, a serial interface input ,a n uart input and a timer/counter input , the corresponding output control (p0outcr) should be set to "0" after p0dr is set to "1". when using this port as a ppg1 and/or ppg2 output, set the output latch (p0dr), and then set the p0outcr. next, set the ppg output initial value in the ppg1ini and/ or ppg2ini, and set the ppg1oe and/or ppg2oe to "1" to enable ppg output. at this time, the output latch (p0dr) should be set to the same value as the ppg output initial value in the ppg1ini, ppg2ini. during reset, the p0dr is initialized to "1", and the p0outcr is initialized to "0". p0 port output latch (p0dr) and p0 port terminal input (p0prd) are located on their respective address. when read the output latch data, the p0dr should be read . when read the terminal input data, the p0prd register should be read. table 5-1 register programming for multi-function ports (p07 to p00) function programmed value p0dr p0outcr port input, external interrupt input, serial interface input, timer counter input or uart input ?1? ?0? port ?0? output ?0? programming for each applications port ?1? output, serial interface output or uart output ?1? timer counter 7 output set to the same value as ppg1ini and ppg2ini page 51 TMP86FH12MG note: i = 5 to 0, j = 7 and 6, k = 2 and 1 figure 5-2 port 0 & c v c q w v r w v (p0dr) % q p v t q n q w v r w v stop outen p0outcri dq p0i p0outcri k p r w v & c v c k p r w v (p0prd) 1 7 v r w v n c v e j t g c f (p0dr) % q p v t q n k p r w v dq 1 w v r w v n c v e j data output (p0dr) 2 2 ) m stop outen p0outcrj dq p0j p0outcrj i & c v c k p r w v (p0prd) 1 w v r w v n c v e j t g c f (p0dr) % q p v t q n k p r w v dq a b s 2 2 ) m + 0 + 2 2 ) m 1 ' 1 w v r w v n c v e j page 52 5. i/o ports 5.1 port p0 (p07 to p00) TMP86FH12MG p0dr (0000h) r/w 76543210 p07 ppg2 int2 p06 ppg1 int1 p05 tc7 p04 so p03 si p02 sck p01 rxd p00 txd (initial value: 1111 1111) p0outcr (0004h) (initial value: 0000 0000) p0outcr port p0 output circuit control (set for each bit individually) 0: sink open-drain output 1: c-mos output r/w p0prd (0008h) read only p07 p06 p05 p04 p03 p02 p01 p00 page 53 TMP86FH12MG 5.2 port p1 (p17 to p10) port p1 is an 5-bit input/output port which can be configured as an input or output in one-bit unit. port p1 is also used as a timer/counter input/output, an external interrupt input and a divider output. input/output mode is specified by the p1 control register (p1cr). during reset, the p1cr is initialized to "0" and port p1 becomes an input mode. and the p1dr is initialized to "0". when used as an input port, a timer/counter input and an external interrupt input, the corresponding bit of p1cr should be set to "0". when used as an output port, the corresponding bit of p1cr should be set to "1". when used as a timer/counter output and a divider output, p1dr is set to "1" beforehand and the corresponding bit of p1cr should be set to "1". when p1cr is "1", the content of the corresponding output latch is read by reading p1dr. if a read instruction is executed for the p1dr and p1cr, read data of bits 7 to 5 are unstable. note: asterisk (*) indicates ?1? or ?0? either of which can be selected. note: i = 7 to 0 figure 5-3 port 1 note: the port set to an input mode reads the terminal input data. therefore, when the input and output modes are used together, the content of the output latch which is s pecified as input mode might be changed by executing a bit manipulation instruction. table 5-2 register programming for multi-function ports function programmed value p1dr p1cr port input, timer/counter input or external interrupt input * ?0? port ?0? output ?0? ?1? port ?1? output, a timer output or a divider output ?1? ?1? p1i dq dq stop outen p1cri p1cri input data input (p1dr) data output (p1dr) control output control input output latch page 54 5. i/o ports 5.2 port p1 (p17 to p10) TMP86FH12MG p1dr (0001h) r/w 76543210 p14 tc1 int4 p13 ppg int3 p12 dvo p11 tc4 pwm4 pdo4 ppg4 p10 tc3 pwm3 pdo3 (initial value: ***0 0000) p1cr (0005h) 76543210 (initial value: ***0 0000) p1cr i/o control for port p1 (specified for each bit) 0: input mode 1: output mode r/w page 55 TMP86FH12MG 5.3 port p2 (p22 to p20) port p2 is a 3-bit input/output port. it is also used as an external interr upt, a stop mode release signal input, and low-frequency crys tal oscillator con- nection pins. when used as an input port or a secondary function pins, respective output latch (p2dr) should be set to ?1?. during reset, the p2dr is initialized to ?1?. a low-frequency crystal osci llator (32.768 khz) is connected to pins p21 (xtin) and p22 (xtout) in the dual- clock mode. in the single-clock mode, pins p21 and p22 can be used as normal input/output ports. it is recommended that pin p20 should be used as an exte rnal interrupt input, a stop mode release signal input, or an input port. if it is used as an output port, the in terrupt latch is set on the falling edge of the output pulse. p2 port output latch (p2dr) and p2 port terminal i nput (p2prd) are located on their respective address. when read the output latch data, the p2dr should be r ead and when read the termin al input data, the p2prd reg- ister should be read. if a read instruction is execute d for port p2, read data of bits 7 to 3 are unstable. figure 5-4 port 2 note: port p20 is used as stop pin. therefore, when stop mode is started, outen does not affect to p20, and p20 becomes high-z mode. p2dr (0002h) r/w 76543210 p22 xtout p21 xtin p20 int5 stop (initial value: **** *111) p2prd (0009h) read only p22 p21 p20 output latch osc. enable output latch dq p20 (int5, stop) dq output latch dq p21 (xtin) p22 (xtout) data input (p20prd) data input (p20) data output (p20) contorl input data input (p21prd) output latch read (p21) data output (p21) data input (p22prd) output latch read (p22) data output (p22) stop outen xten fs page 56 5. i/o ports 5.4 port p3 (p37 to 30) TMP86FH12MG 5.4 port p3 (p37 to 30) port p3 is an 8-bit input/output port which can be configured as an input or output in one-bit unit. port p3 is also used as an analog input, key-on wakeup input, an external interrupt and tc7 emergency stop input. input/output mode is specified by the p3 control register (p3cr1) and p3 input control register (p3cr2). during reset, the p3cr1 is initialized to "0" the p3cr2 is initialized to "1" and port p3 becomes an input mode. and the p3dr is initialized to "0". when used as an output port, the corresponding bit of p3cr1 should be set to "1". when used as an input port, key-on wakeup input, an external interrupt input and tc7 emergency stop input, the corresponding bit of p3cr1 should be set to "0" and then, the corresponding bit of p3cr2 should be set to "1". when used as an analog input, the corresponding bit of p3cr1 should be set to "0" and then, the corresponding bit of p6cr2 should be set to "0". when p3cr1 is "1", the content of the corres ponding output latch is read by reading p3dr. note: asterisk (*) indicates ?1? or ?0? either of which can be selected. table 5-3 register programming for multi-function ports function programmed value p3dr p3cr1 p3cr2 port input or key-on wakeup input or external input or tc7 emergency stop input *?0??1? analog input * ?0? ?0? port ?0? output ?0? ?1? * port ?1? output ?1? ?1? * table 5-4 values read from p3dr and register programming conditions values read from p3dr p3cr1 p3cr2 ?0? ?0? ?0? ?0? ?1? terminal input data ?1? ?0? output latch contents ?1? page 57 TMP86FH12MG note: i = 7 to 0 figure 5-5 port 3 p3i dq dq p3cr2i p3cr2i k p r w v p3cr1i p3cr1i k p r w v & c v c k p r w v (p3dri) & c v c q w v r w v (p3dri) stop outten # p c n q i k p r w v ainds sain dq % q p v t q n q w v r w v p3j dq dq p3cr2j p3cr2j k p r w v p3cr1j p3cr1j k p r w v & c v c q w v r w v (p3drj) stop outten # p c n q i k p r w v ainds stopken - g [ q p y c m g w r dq & c v c k p r w v (p3drj) a) p37,p32 to p30 sain b) p36 to p33 page 58 5. i/o ports 5.4 port p3 (p37 to 30) TMP86FH12MG note 1: the port placed in input mode reads the pin input stat e. therefore, when the input and output modes are used together, the output latch contents for the port in input mode might be changed by executing a bi t manipulation instruction. note 2: when used as an analog inport, be sure to clear the corresponding bit of p3cr2 to disable the port input. note 3: do not set the output mode (p3cr1 = ?1?) for the pin used as an analog input pin. note 4: pins not used for analog input can be used as i/o ports. during ad conversion, output instructions should not be execute d to keep a precision. in addition, a variabl e signal should not be input to a port ad jacent to the analog input during ad con- version. p3dr (0003h) r/w 76543210 p37 ain7 p36 ain6 stop3 p35 ain5 stop2 p34 ain4 stop1 p33 ain3 stop0 p32 ain2 p31 ain1 int0 p30 ain0 emg (initial value: 0000 0000) p3cr1 (0006h) 76543210 (initial value: 0000 0000) p3cr1 i/o control for port p3 (specified for each bit) 0: input mode 1: output mode r/w p3cr2 (0007h) 76543210 (initial value: 1111 1111) p3cr2 p3 port input control (specified for each bit) 0: analog input 1: port input or key-on wakeup input or external interrupt input or tc7 emergency stop input r/w page 59 TMP86FH12MG 6. watchdog timer (wdt) the watchdog timer is a fail-safe system to detect rapidl y the cpu malfunctions such as endless loops due to spu- rious noises or the deadlock conditions, and return the cpu to a sy stem recovery routine. the watchdog timer signal for detecting malfunctions can be programmed only once as ?reset request? or ?inter- rupt request?. upon the reset release, this signal is initialized to ?reset request?. when the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic inter- rupt. note: care must be taken in system des ign since the watchdog timer functions are not be operated completely due to effect of disturbing noise. 6.1 watchdog timer configuration figure 6-1 watchdog timer configuration 0034 h overflow wdt output internal reset binary counters wdtout writing clear code writing disable code wdten wdtt 2 0035 h watchdog timer control registers wdtcr1 wdtcr2 intwdt interrupt request interrupt request reset request reset release clock clear 1 2 controller q sr s r q selector fc/2 23 or fs/2 15 fc/2 21 or fs/2 13 fc/2 19 or fs/2 11 fc/2 17 or fs/2 9 page 60 6. watchdog timer (wdt) 6.2 watchdog timer control TMP86FH12MG 6.2 watchdog timer control the watchdog timer is controlled by the watchdog timer control registers (wdtcr1 and wdtcr2). the watch- dog timer is automatically enabled after the reset release. 6.2.1 malfunction detection me thods using the watchdog timer the cpu malfunction is detected, as shown below. 1. set the detection time, select the output, and clear the binary counter. 2. clear the binary counter repeatedly within the specified detection time. if the cpu malfunctions such as en dless loops or the deadlock condition s occur for some reason, the watch- dog timer output is activated by the binary-counter overflow unless the binary counters are cleared. when wdtcr1 page 61 TMP86FH12MG note 1: after clearing wdtout to ?0?, the program cannot set it to ?1?. note 2: fc: high-frequency clock [hz], fs : low-frequency clock [hz], *: don?t care note 3: wdtcr1 is a write-only register and must not be used with any of read-modify-write instructions. if wdtcr1 is read, a don?t care is read. note 4: to activate the stop mode, disable the watchdog timer or clear the counter immediately before entering the stop mode. after clearing the counter, clear the counter again immediately after the stop mode is inactivated. note 5: to clear wdten, set the register in accordance wi th the procedures shown in ?1.2.3 watchdog timer disable?. note 1: the disable code is valid only when wdtcr1 page 62 6. watchdog timer (wdt) 6.2 watchdog timer control TMP86FH12MG 6.2.3 watchdog timer disable to disable the watchdog timer, set the register in accordance with the fo llowing procedures . setting the reg- ister in other procedures causes a malfunction of the microcontroller. 1. set the interrupt master flag (imf) to ?0?. 2. set wdtcr2 to the clear code (4eh). 3. set wdtcr1 page 63 TMP86FH12MG 6.2.5 watchdog timer reset when a binary-counter overflow occurs while wdt cr1 page 64 6. watchdog timer (wdt) 6.3 address trap TMP86FH12MG 6.3 address trap the watchdog timer control register 1 and 2 share the a ddresses with the control regi sters to generate address traps. 6.3.1 selection of address tr ap in internal ram (atas) wdtcr1 page 65 TMP86FH12MG 6.3.4 address trap reset while wdtcr1 page 66 6. watchdog timer (wdt) 6.3 address trap TMP86FH12MG page 67 TMP86FH12MG 7. time base timer (tbt) the time base timer generates time base for key scanning, dynamic displaying, etc. it also provides a time base timer interrupt (inttbt). 7.1 time base timer 7.1.1 configuration figure 7-1 time base timer configuration 7.1.2 control time base timer is controled by time base timer control register (tbtcr). note 1: fc; high-frequency clock [hz], fs ; low-frequency clock [hz], *; don't care time base timer control register 7 6543210 tbtcr (0036h) (dvoen) (dvock) (dv7ck) tbten tbtck (initial value: 0000 0000) tbten time base timer enable / disable 0: disable 1: enable tbtck time base timer interrupt frequency select : [hz] normal1/2, idle1/2 mode slow1/2 sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 000 fc/2 23 fs/2 15 fs/2 15 001 fc/2 21 fs/2 13 fs/2 13 010 fc/2 16 fs/2 8 ? 011 fc/2 14 fs/2 6 ? 100 fc/2 13 fs/2 5 ? 101 fc/2 12 fs/2 4 ? 110 fc/2 11 fs/2 3 ? 111 fc/2 9 fs/2 ? fc/2 23 or fs/2 15 fc/2 21 or fs/2 13 fc/2 16 or fs/2 8 fc/2 14 or fs/2 6 fc/2 13 or fs/2 5 fc/2 12 or fs/2 4 fc/2 11 or fs/2 3 fc/2 9 or fs/2 tbtcr tbten tbtck 3 mpx source clock falling edge detector time base timer control register inttbt interrupt request idle0, sleep0 release request page 68 7. time base timer (tbt) 7.1 time base timer TMP86FH12MG note 2: the interrupt frequency (tbtck) must be selected with t he time base timer disabled (tbten="0"). (the interrupt fre- quency must not be changed with the disable from the enable state.) both frequency selection and enabling can be per- formed simultaneously. 7.1.3 function an inttbt ( time base timer interrupt ) is generated on the first falling edge of source clock ( the divider output of the timing generato which is selected by tbtck. ) after time base timer has been enabled. the divider is not cleared by the progra m; therefore, only the first interrupt may be generated ahead of the set interrupt period ( figure 7-2 ). figure 7-2 time base timer interrupt example :set the time base timer frequency to fc/2 16 [hz] and enable an inttbt interrupt. ld (tbtcr) , 00000010b ; tbtck 010 ld (tbtcr) , 00001010b ; tbten 1 di ; imf 0 set (eirh) . 1 table 7-1 time base timer interrupt frequency ( example : fc = 16.0 mhz, fs = 32.768 khz ) tbtck time base timer interrupt frequency [hz] normal1/2, idle1/2 mode normal1/2, idle1/2 mode slow1/2, sleep1/2 mode dv7ck = 0 dv7ck = 1 000 1.91 1 1 001 7.63 4 4 010 244.14 128 ? 011 976.56 512 ? 100 1953.13 1024 ? 101 3906.25 2048 ? 110 7812.5 4096 ? 111 31250 16384 ? source clock enable tbt interrupt period tbtcr page 69 TMP86FH12MG 7.2 divider output ( dvo ) approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. divider output is from dvo pin. 7.2.1 configuration figure 7-3 divider output 7.2.2 control the divider output is controlled by the time base timer control register. note: selection of divider output frequency (dvock) must be made whil e divider output is disabled (dvoen="0"). also, in other words, when changing the state of the divider output frequen cy from enabled (dvoen="1") to disable(dvoen="0"), do not change the setting of the divider output frequency. time base timer control register 7654 321 0 tbtcr (0036h) dvoen dvock (dv7ck) (tbten) (tbtck) (initial value: 0000 0000) dvoen divider output enable / disable 0: disable 1: enable r/w dvock divider output ( dvo ) frequency selection: [hz] normal1/2, idle1/2 mode slow1/2 sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 00 fc/2 13 fs/2 5 fs/2 5 01 fc/2 12 fs/2 4 fs/2 4 10 fc/2 11 fs/2 3 fs/2 3 11 fc/2 10 fs/2 2 fs/2 2 tbtcr output latch port output latch mpx dvoen tbtcr page 70 7. time base timer (tbt) 7.2 divider output (dvo) TMP86FH12MG example :1.95 khz pulse output (fc = 16.0 mhz) ld (tbtcr) , 00000000b ; dvock "00" ld (tbtcr) , 10000000b ; dvoen "1" table 7-2 divider output frequency ( exam ple : fc = 16.0 mhz, fs = 32.768 khz ) dvock divider output frequency [hz] normal1/2, idle1/2 mode slow1/2, sleep1/2 mode dv7ck = 0 dv7ck = 1 00 1.953 k 1.024 k 1.024 k 01 3.906 k 2.048 k 2.048 k 10 7.813 k 4.096 k 4.096 k 11 15.625 k 8.192 k 8.192 k page 71 TMP86FH12MG 8. real-time clock the TMP86FH12MG include a real time co unter (rtc). a low-frequency clock can be used to provide a periodic interrupt (0.0625[s],0.125[s],0 .25[s],0.50[s]) at a programm ed interval, implement the clock function. the rtc can be used in the mode in which the low-frequency oscillator is active (except for the sleep0 mode). 8.1 configuration figure 8-1 confi guration of the rtc 8.2 control of the rtc the rtc is controlled by the rtc control register (rtccr). note 1: program the rtccr during low-freque ncy oscillation (when syscr2 page 72 8. real-time clock 8.3 function TMP86FH12MG 8.3 function the rtc counts up on the internal low-frequency clock. when rtccr page 73 TMP86FH12MG 9. 10-bit timer/counter (tc7) 9.1 configuration figure 9-1 10-bi t timer/counter 7 9.2 control timer/counter 7 is controlled by timer/counter control register 1 (tc7cr1), timer/counter control register 2 (tc7cr2), timer/counter control register 3 (tc7cr3), 10-b it dead time 1 setup register (tc7dra), pulse width 1 setup register (tc7drb), period setup register (tc7drc) , dead time 2 setup register (tc7drd), pulse width 2 setup register (tc7dre), and two capture value registers (tc7capa and tc7capb). timer/counter 7 control register 1 tc7cr1 (0029h) 76543210 trgam trgsel ppg2ini ppg1ini ncrsel tc7ck (initial value: 0000 0000) 10-bit up counter compare register e a b cy d s compare register d compare register c compare register b compare register a tc7cr1 tc7cr2 tc7capa tc7capb tc7cr3 noise canceller emergency output stop control edge detection ppg output control comparator tc7dra tc7drb tc7drc tc7drd tc7dre transfer control capture control inttc7t interrupt request fc fc/2 fc/2 2 fc/2 3 inttc7p interrupt request intemg interrupt request emergency stop tc7ck tgram start/ clear emgf csidis cstc tc7st stm cntbf trgsel emgf cstc emgie emgr ppg2oe ppg1oe tc7out csidis ncrsel tc7 pin emg pin ppg1 ppg2 ppg2ini ppg1ini ppg1ini/ ppg2ini ppg1oe/ ppg2oe tc7out page 74 9. 10-bit timer/counter (tc7) 9.2 control TMP86FH12MG note: due to the circuit configuration, a pulse shorter than 1/fc may be eliminated as noise or accepted as a trigger. tc7ck select a source clock (supplied to the up counter). 00: fc [hz] 01: fc/2 [hz] 10 fc/2 2 [hz] 11: fc/2 3 [hz] r/w ncrsel select the duration of noise elimination for tc7 input (after passing through the flip-flop). 00: eliminate pulses shorter than 16/fc [s] as noise. 01: eliminate pulses shorter than 8/fc [s] as noise. 10: eliminate pulses shorter than 4/fc [s] as noise. 11: do not eliminate noise. (note) ppg1ini specify the initial value of ppg1 out- put. select positive or negative logic. 0: low (positive logic) 1: high (negative logic) ppg2ini specify the initial value of ppg2 out- put. 0: low (positive logic) 1: high (negative logic) trgsel select a trigger start edge. 0: start on trigger falling edge. 1: start on trigger rising edge. trgam trigger edge acceptance mode 0: always accept trigger edges. 1: do not accept trigger edges during active output. timer/counter 7 control register 2 tc7cr2 (002ah) 76543210 emgr emgie ppg2oe ppg1oe cstc tc7out (initial value: 0000 0000) tc7out select an output waveform mode. 00: ppg1/ppg2 independent output 01: ? 10: output with variable duty ratio 11: output with 50% duty ratio r/w cstc select a count start mode. 00: command start and capture mode 01: command start and trigger start mode. 10: trigger start mode 11: - ppg1oe enable/disable ppg1 output. 0: disable 1: enable ppg2oe enable/disable ppg2 output. 0: disable 1: enable emgie enable/disable input on the emg pin. 0: disable input. 1: enable input. emgr cancel the emergency output stop state. 0: - 1: cancel the emergency output stop state. (upon canceling the state, this bit is automatically cleared to 0.) timer/counter 7 control register 3 tc7cr3 (002bh) 76543210 emgf cntbf csidis stm tc7st (initial value: **00 0000) page 75 TMP86FH12MG note 1: the tc7cr1 and tc7cr2 registers should not be rewritten afte r a timer start (when tc7st, bit0 of the tc7cr3, is set to 1). note 2: before attempting to modify the tc7cr1 or tc7cr2, clear tc7st and then check that cntbf = 0 to determine that the timer is stopped. note 3: the tc7st bit only causes the timer to start or stop; it does not indicate the current operating state of the counter. i ts value does not change automatically when counting starts or stops note 4: in command start and capture mode or command start and tr igger start mode, writing 1 to tc7st causes the timer to restart immediately. it means that rewriting any bit other than tc7st in the tc7cr3 after a command start causes the rewriting of tc7st, resulting in the timer being restarted (ppg output is started from the initial state). when tc7st is set to 1, rewriting the tc7cr3 (using a bit manipulation or ld instruction) clears the counter and restarts the timer. note 5: tc7cr2 page 76 9. 10-bit timer/counter (tc7) 9.2 control TMP86FH12MG note 1: data registers tc7dra to tc7dre have double-stage configur ation, consisting of a data register that stores data written by an instruction and a compare register to be compared with the counter. note 2: when writing data to data registers tc7dra to tc7dre, first write the lower byte and then the upper byte. note 3: unused bits (bits 10 to 15) in the upper bytes of dat a registers tc7dra to tc7dre ar e not assigned specific register functions. these bits are always read as 0 even when a 1 is written. note 4: values read from data registers tc7dra to tc7dre may differ from the actual ppg output waveforms due to their dou- ble-stage configuration. note 5: data registers are not updated by merely modifying the output mode with tc7cr2 page 77 TMP86FH12MG 9.3 configuring control and data registers configure control and data registers in the following order: 1. configure mode settings: tc7cr1, tc7cr2 2. configure data registers (dead time, pulse width): tc7dra, tc7drb, tc7drd, tc7dre (only those required for selected mode) 3. configure data registers (period): tc7drc 4. configure timer start/stop:tc7cr3 ? data registers have double-stage conf iguration, consisting of a data regi ster that stores data written by an instruction and a compare register to be compared with the counter. ? data stored in a data register is processed accord ing to the output mode specified in the tc7out, transferred to the compare regi ster, and then used for comp arison with th e up counter. ? data registers required for the speci fied output mode are used for data register processing and transfer to the compare register. ensure that the output mode is specified in the tc7out (bits 0 and 1 of the tc7cr2) before configuring data registers. ? writing data to the upper byte of the tc7drc causes a da ta transfer request to be issued for data in data registers tc7dra to tc7dre. if a counter matc h or clear occurs while th at request is valid, the data is transferred to the compare re gister and becomes valid for comparison. ? if a data register is written more than once within a period, the data in the data register that was set when the upper byte of the tc7drc was written is valid as data for the next period. the data in the data register written last in the first period will be valid for the period that follows the next period. figure 9-2 example c onfiguration of contro l/data registers (1) if data is rewritten more than once within a period, the data written first is valid in the next period. valid in next period execute write instruction. period (1) tc7dra tc7drb tc7drc period (2) period (3) period (4) a1 b1 c1 execute write instruction. a2 b2 c2 execute write instruction. a3 b3 c3 previous data is maintained if data is not rewritten within the period. execute write instruction. data valid in each period period (1) tc7dra tc7drb tc7drc period (2) period (3) period (4) period (5) a1 b1 c1 execute write instruction. a5 c7 a1 b1 c1 a2 b1 c2 a3 b2 c5 a5 b2 c7 a2 c2 a4 c6 a3 c5 b2 c4 c3 execute write instruction. a6 b3 c8 a7 b4 c9 a6 b3 c8 if data is rewritten more than once within a period, the data written last is valid in the period following the next period. execute more than one data write instruction. no data write page 78 9. 10-bit timer/counter (tc7) 9.4 features TMP86FH12MG figure 9-3 example c onfiguration of contro l/data registers (2) 9.4 features 9.4.1 programmable pulse gener ator output (ppg output) the ppg1 and ppg2 pins provide ppg outputs. the output waveform mode for ppg outputs is specified with tc7cr2 page 79 TMP86FH12MG when the value set in the tc7drc is an odd number, the ppg2 pulse width is one count longer than the ppg1 pulse width. (b) dead time tc7dra: 000h tc7dra < tc7drc/2 to specify no dead time, set the tc7dra to 000h. figure 9-4 example oper ation in 50% duty mode: command and capture start, pos itive logic, continuous output 9.4.1.2 variable duty mode (1) description with a period specified in the tc7drc and a pulse width in the tc7drb, the ppg1 pin provides a waveform having the specified pulse width while the ppg2 pin provides a waveform having a pulse width that equals (tc7drc ? tc7drb). the ppg1 output is active at the beginning of a period, remains active during the pulse width spec- ified in the tc7drb, after which it is inactive until the end of the period. the ppg2 output is inac- tive at the beginning of a period, remains inactive during the pulse width specified in the tc7drb, after which it is active until the end of the peri od, that is, during the pulse width of (tc7drc ? tc7drb). if a dead time is specified in the tc7dra, the pulse width (active duration) is shortened by the dead time. (2) register settings tc7out = ?10?, tc7dra = ?dead time?, tc7drb = ?pulse width?, tc7drc = ?period? s, 0 m s m ' s 1 m s/2 s, 0 2 13 s/2+1 s/2+m counter period dead time source clock ppg1 output m: dead time dead time (tc7dra) period (tc7drc) pulse width (tc7drc / 2) pulse width (tc7drc / 2) dead time (tc7dra) m: dead time s: period active duration active duration ppg2 output inttc7t inttc7p page 80 9. 10-bit timer/counter (tc7) 9.4 features TMP86FH12MG (3) valid range for data register values (a) period: 002h tc7drb + tc7dra < tc7drc 400h (writing 400h to tc7drc results in 000h being read from it.) (b) pulse width: 001h tc7drb < tc7drc (c) dead time: 000h tc7dra < tc7drb, 000h tc7dra < (tc7drc ? tc7drb) (to specify no dead time, set the tc7dra to 000h.) figure 9-5 example operat ion in variable duty mode: command and capture start, positi ve logic, c ontinuous output 9.4.1.3 ppg1/ppg2 independent mode (1) description for the ppg1 output, specify the dead time in the tc7dra and pulse width in the tc7drb. for the ppg2 output, specify the dead time in the tc7drd and pulse width in the tc7dre. with a common period specified in the tc7drc, the ppg1 and ppg2 pins provide waveforms having the specified pulse widths. s, 0 m s m ' s 1m n s, 02 13 n+1 n+m counter period dead time n n ' pulse width source clock ppg1 output m: dead time dead time (tc7dra) period (tc7drc) pulse width (tc7drc ? tc7drb) pulse width (tc7drb) dead time (tc7dra) m: dead time s: period n: pulse width active duration active duration ppg2 output inttc7t inttc7p page 81 TMP86FH12MG the ppg1 output is active at the beginning of a period, remains active during the pulse width spec- ified in the tc7drb, after which it is inactive until the end of the period. the ppg2 output is active at the beginning of a period, remains active during the pulse width spec- ified in the tc7dre, after which it is inactive until the end of the period. if a dead time is specified in the tc7dra for the ppg1 output or in the tc7drd for the ppg2 output, the pulse width (active duration) is shortened by the dead time. (2) register settings tc7out = ?00?, tc7drc = ?period? tc7dra = ?ppg1 dead time?, tc7drb = ?ppg1 pulse width? tc7drd = ?ppg2 dead time?, tc7dre = ?ppg2 pulse width? (3) valid range for data register values (a) period: 002h tc7drc 400h (writing 400h to tc7drc results in 000h being read from it.) (b) pulse width: 001h tc7drb 400h (writing 400h to tc7drb results in 000h being read from it.) 001h tc7dre 400h (writing 400h to tc7dre results in 000h being read from it.) (c) dead time: 000h tc7dra 3ffh, where tc7dra < tc7drb tc7drc 000h tc7drd 3ffh, where tc7drd < tc7dre tc7drc (to specify no dead time, write 000h.) ? settings for a duty ratio of 0% 002h tc7drc tc7dra 3ffh (ppg1 output) 002h tc7drc tc7drd 3ffh (ppg2 output) ? settings for a duty ratio greater than 0%, up to 100% 000h tc7dra < tc7drb tc7drc 400h (ppg1 output) 000h tc7drd < tc7dre tc7drc 400h (ppg2 output) period 0% duty period 100% duty page 82 9. 10-bit timer/counter (tc7) 9.4 features TMP86FH12MG figure 9-6 example operati on in ppg1/ppg2 independent mode: command and capture start, positi ve logic, c ontinuous output 9.4.2 starting a count a count can be started by using a command or tc7 pin input. 9.4.2.1 command start and capture mode (1) description writing a 1 to tc7st causes the current count to be cleared and the counter to start counting. once the count has reached a specified period, the count er is cleared. the counter subsequently restarts counting if stm specifies continuous mode; it stops counting if stm specifies one-time mode. writing a 1 to tc7st before the count reaches a period causes the counter to be cleared, after which it operates as specified with stm. the count values at the rising and falling edges on the tc7 pin can be stored in capture registers (details for the capture are gi ven in a separate section). 0 m s m ' s 1m t us, 02 13 n counter period dead time n n ' pulse width source clock ppg1 output m: dead time ppg1 dead time (tc7dra) period (tc7drc) ppg2 pulse width (tc7dre) ppg2 dead time (tc7drd) ppg1 pulse width (tc7drb) s: period u: pulse width t: dead time n: pulse width active duration active duration ppg2 output inttc7t inttc7p t t ' dead time u u ' pulse width page 83 TMP86FH12MG (2) register settings cstc = ?00?: command start and capture mode stm: continuous/one-time output tc7st = ?1?: starts counting figure 9-7 exampl e operation in comma nd start and capture mode 9.4.2.2 command start and trigger start mode (1) description writing a 1 to tc7st causes the current count to be cleared and the counter to start counting. the operation is the same as that in command start and capture mode if there is no trigger input on the tc7 pin. if an edge specified with the start edge selection field (trgsel) appears on the tc7 pin, however, the timer starts counting. the counter is cleared and stopped while the tc7 pin is driven to the specified clear/stop level. if the tc7 pin is at the clear/stop level when a count start command is issued (1 is written to tc7st), counting does not start (inttc7p does not occur) until a trigger start edge appears, causing inttc7t to occur (a trig ger input takes precedence over a command start). note: for more information on the acceptance of a trigger, see 9.4.2.5 ?trigger start/stop acceptance mode?. (2) register settings cstc = ?01?: command start and trigger start mode stm: continuous/one-time output tc7st = ?1?: starts counting trgsel: trigger selection figure 9-8 example operation in command st art and trigger start mode tc7st = 1 count start (command) count cleared start count cleared start count cleared restart ppg1 ppg output with a period specified with tc7drc ppg output with a period specified with tc7drc ppg output with a period specified with tc7drc count start (command) count cleared start count cleared count start ppg1 when trgsel = 0 (start on falling edge) tc7 input (signal after noise elimination) period (tc7drc) count stopped ppg output with a period specified with tc7drc if there is no trigger count stops with a trigger (high level). count starts with a trigger (falling edge). page 84 9. 10-bit timer/counter (tc7) 9.4 features TMP86FH12MG 9.4.2.3 trigger start mode (1) description if an edge specified with the st art edge selection field (trgsel) appears on the tc7 pin, the timer starts counting. the counter is cleared and stopped wh ile the tc7 pin is driven to the specified clear/ stop level. in trigger start mode, writing a 1 to tc7st is ignored and does not initialize the ppg output. note: for more information on the acceptance of a trigger, see 9.4.2.5 ?trigger start/stop acceptance mode?. (2) register settings cstc = ?10?: trigger start mode stm: continuous/one-time output tc7st = ?1?: starts waiting for a trigger on the tc7 pin trgsel: trigger selection figure 9-9 example operat ion in trigger start mode 9.4.2.4 trigger capture mode (cstc = 00) (1) description when counting starts in command start and capture mode, the count values at the rising and falling edges of the tc7 pin input are captured and st ored in capture registers tc7capa and tc7capb, respectively. count start count stopped count stopped count start count cleared count cleared ppg1 output (example) tc7 input (signal after noise elimination) after a command is set, counting does not start until a specified trigger appears. count start count stopped count start command set command set count cleared ppg1 output (example) tc7 input (signal after noise elimination) after a command is set, counting does not start until a specified trigger appears. page 85 TMP86FH12MG the captured data is first stored in the capture buffer. at the end of the period, the data is trans- ferred from the capture buffer to the capture register. if a trigger input does not appear within a period, the data captured in the previous period rema ins in the capture buffer and is transferred to the capture register at the end of the period. if more th an one trigger edge is detected within a period, the data captured last is written to the capture register. captured data must be read in the following order: lower byte of capture register a (tc7capal), upper byte of capture register a (tc7capah), lo wer byte of capture register b (tc7capbl), and upper byte of capture register b (tc7capbh). note that reading only the rising-edge captured data (tc7capa) does not update the next captured data. the falling-edge captured data (tc7capb) must also be read. an attempt to read a captured va lue from a register other than the upper byte of the tc7capb causes the capture registers to enter protected state, in which captured data cannot be updated. read- ing a value from the upper byte of the tc7capb can cels that state, re-enabl ing the updating of cap- tured data (the tc7capa and tc7capb ar e read as a single set of operation). note that the protected state may be still effectiv e immediately after the c ounter starts. ensure that a dummy read of capture registers is performed in the first period to cancel the protected state. the capture feature of the tc7 assumes that a capture trigger (rising or falling edge) appears within a period. captured data is updated (an edge is detected) only when the timer is operating (tc7st = 1). if a timer stop command (tc7st = 0) is written within a period, captured data will be undefined. captured data is not updated after a one -time stop command is written. in one-time stop mode, no trigger is accepted af ter a stop command is given. (2) register settings cstc = ?00?: command start and capture mode stm: continuous/one-time output tc7st = ?1?: starts counting page 86 9. 10-bit timer/counter (tc7) 9.4 features TMP86FH12MG figure 9-10 exam ple operation in tr igger capture mode 9.4.2.5 trigger start/stop acceptance mode (1) selecting an input signal logi c for the tc7 pin (trigger input) the logic for an input trigger signal on the tc7 pin can be specified using tc7cr1 page 87 TMP86FH12MG figure 9-11 tr igger input signal when trgsel is set to 0 to select a falling-edge trigger, a falling edge detected on the tc7 pin causes the counter to start counting and a high level on the tc7 pin causes the counter to be cleared and the ppg output to be initialized. the counter is stopped while the tc7 pin input is high. when trgsel is set to 1 to sel ect a rising-edge trigger, a rising edge detected on the tc7 pin causes the counter to start counting and a low leve l on the tc7 pin causes the counter to be cleared and the ppg output to be initialized. the counter is stopped while the tc7 pin input is low. in one-time stop mode, th e counter accepts a stop trigger but does not accept a start trigger (when a stop trigger is accepted within a period, the output is immediatel y initialized a nd the counter is stopped). all triggers (start and stop) are ignored when the timer is stopped (tc7st = 0). (2) specifying whether triggers are always accepted or ignored when ppg outputs are active the tc7cr1 page 88 9. 10-bit timer/counter (tc7) 9.4 features TMP86FH12MG figure 9-12 start and clear /stop triggers on the tc7 pin: falling-edge trigger (counting stopped at high leve l), triggers always accepted (3) ignoring triggers when ppg outputs are active setting trgam to 1 specifies that triggers are ignored when ppg outputs are active; trigger edges detected when ppg1 and ppg2 ou tputs are inactive are accepted and cause the counter to be cleared and stopped. if a trigger is de tected when ppg1 and ppg2 outputs are active, the counter does not stop immediately but continues counting until the outputs become inactive. if the trigger signal level is a stop level when the outputs become inactive, the counter is cl eared/stopped and waits for a next start trigger. if output is enabled for both ppg 1 and ppg2, triggers ar e accepted only when both ppg1 and ppg2 outputs are inactive. figure 9-13 start tr iggers on the tc7 pin: falling-edge trigger (counting stopped at high level), tri ggers ignored when ppg outputs are active tc7 pin input ppg1 output ( positive logic) ppg2 output ( positive logic) inttc7t inttc7p counter operating counter operating counter operating counter operating counter stopped counter stopped counter stopped count started count started count started count started count cleared count cleared end of a period count cleared tc7 pin input (signal after noise elimination) igbt1 (positive logic) igbt2 (positive logic) inttc7 triggers not accepted inttcr counter operating counter operating counter operating counter stopped counter stopped a trigger detected when ppg1 and ppg2 are inactive causes the counter to stop or start. a trigger detected when ppg1 or ppg2 is active does not cause the counter to stop. a high level of the trigger input causes the counter to stop when ppg1 and ppg2 become inactive. a trigger detected when ppg1 or ppg2 is active does not cause the counter to stop or restart. page 89 TMP86FH12MG 9.4.3 configuring how the timer stops setting tc7st to 0 causes the timer to stop with the specified output st ate according to the setting of stm. 9.4.3.1 counting stopped with the outputs initialized when stm is set to 00, the counter stops immediately with the ppg1 and ppg2 outputs initialized to the values specified wi th ppg1ini and ppg2ini. 9.4.3.2 counting stopped with the outputs maintained when stm is set to 01, the counter stops immediat ely with the curr ent ppg1 and ppg2 output states maintained. to restart the counter from the maintained state (stm = 01), set tc7st to 1. the counter is restarted with the initial output values, specified with ppg1ini and ppg2ini. 9.4.3.3 counting stopped with the outputs initialized at the end of the period when stm is set to 10, the counter continues counting until the end of the current period and then stops. if a stop trigger is detect ed before the end of the period, how ever, the counter stops immediately. tc7cr1 and tc7cr2 must not be rewritten before the counter stops completely. the cntbf flag (tc7cr3 page 90 9. 10-bit timer/counter (tc7) 9.4 features TMP86FH12MG figure 9-14 immedi ately stopping and clearing the count er with the ou tputs initialized (stm = 00) figure 9-15 immediately st opping and clearing the counter with the outputs maintained (stm = 01) figure 9-16 stopping th e counter at the end of the period (stm = 10) figure 9-17 stopping the counter at the end of the period (stm = 10): tc7st = 1, one-time output mode count started tc7st = 1 stm = 00 output enabled ppg1e/ppg2e = 1 stop command tc7st = 0 the counter is forcibly stopped and cleared, with the outputs initialized. ppg1 (positive logic) ppg1ini = 0 ppg2 (negative logic) ppg1ini = 1 count started tc7st = 1 stm = 01 output enabled ppg1e/ppg2e = 1 stop command tc7st = 0 the counter is forcibly stopped and cleared, with the outputs maintained. ppg1 (positive logic) ppg1ini = 0 ppg2 (negative logic) ppg1ini = 1 count started tc7st = 1 stm = 00 or 01 1 period 1 period count stopped output enabled ppg1e/ppg2e = 1 stop command tc7st = 0 stm = 10 after a stop command is executed, the counter continues counting until the end of the period. it stops at the end of the period. ppg1 (positive logic) ppg1ini = 0 ppg2 (negative logic) ppg1ini = 1 count started tc7st = 1 stm = 10 1 period output enabled ppg1e/ppg2e = 1 count stopped at the end of the period the counter stops at the end of the period and then waits for a command start or a start trigger. ppg1 (positive logic) ppg1ini = 0 ppg2 (negative logic) ppg1ini = 1 page 91 TMP86FH12MG 9.4.5 ppg output control (initial value/output logi c, enabling/disabling output) 9.4.5.1 specifying initial values and output logic for ppg outputs the ppg1ini and ppg2ini bits (tc7cr1 page 92 9. 10-bit timer/counter (tc7) 9.4 features TMP86FH12MG figure 9-19 noise canceller operation ? when ncrsel = 00, a tc7 input level after passing th rough the f/f is always canceled if its duration is 16/fc [s] or less and always assumed as a signal if its duration is 20/fc [s] or greater. after the input signal supplied on the tc7 pin passes through the f/f, there is a delay between 21/fc [s] and 24/fc [s] before the ppg outputs vary. ? when ncrsel = 01, a tc7 input level after passing th rough the f/f is always canceled if its duration is 8/fc [s] or less and always assumed as a signal if its duration is 10/fc [s] or greater. after the input signal supplied on the tc7 pin passes through the f/f, there is a delay between 13/fc [s] and 14/fc [s] before the ppg outputs vary. ? when ncrsel = 10, a tc7 input level after passing th rough the f/f is always canceled if its duration is 4/fc [s] or less and always assumed as a signal if its duration is 5/fc [s] or greater. after the input sig- nal supplied on the tc7 pin passes through the f/f, there is a delay of 5/fc [s] before the ppg outputs vary. ? when ncrsel = 11, a pulse shorter than 1/fc may be assumed as a signal or canceled as noise in the first-stage f/f. ensure that input signal pulses are longer than 1/fc. after the input signal supplied on the tc7 pin passes through the f/f, there is a delay of 4/fc [s] before the ppg outputs vary. table 9-1 noise canceller settings ncrsel sampling frequency (number of samplings) pulse width always assumed as nois e pulse width always assumed as signal at 8 mhz at 16 mhz at 8 mhz at 16 mhz 00 fc/4 (5) 16/fc [s] 2 [ms] 1 [ms] 20/fc [s] 2.5 [ms] 1.25 [ms] 01 fc/2 (5) 8/fc [s] 1 [ms] 500 [ns] 10/fc [s] 1.25 [ms] 0.625 [ms] 10 fc (5) 4/fc [s] 0.5 [ms] 250 [ns] 5/fc [s] 0.625 [ms] 0.3125 [ms] 11 (none) none ? ? (1/fc) fc fc/2 a fter noise elimination fc/4 when ncrsel = 00 when ncrsel = 01 when ncrsel = 10 pulses of 5/fc or longer are assumed as a signal. pulses of 10/fc or longer are assumed as a signal. pulses of 20/fc or longer are assumed as a signal. pulses of 4/fc or shorter are canceled. pulses of 8/fc or shorter are canceled. pulses of 16/fc or shorter are canceled. tc7 pin input (after passing through f/f) 1 2 3 4 5 1 2 3 4 5 1 2 3 4 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5 b a z s a b z c noise canceller edge detection ppg output control circuit f/f tc7 input fc ppg output sampling clock fc fc/2 fc/4 ncrsel ncrsel = 11 page 93 TMP86FH12MG note 1: if the pin input level changes while the specified noi se elimination threshold is being modified, the noise canceller may assume noise as a pul se or cancel a pulse as noise. note 2: if noise occurs in synchronization with the inter nal sampling timing consecutiv ely, it may be assumed as a signal. note 3: the signal supplied on the tc7 pin require s 1/fc [s] or less to pass through the f/f. 9.4.7 interrupts the tc7 supports three interrupt sources. 9.4.7.1 inttc7t (trigger start interrupt) a trigger interrupt (inttc7t) occurs when the counter star ts upon the detection of a trigger edge spec- ified with tc7cr1 page 94 9. 10-bit timer/counter (tc7) 9.4 features TMP86FH12MG if a command start is specified (1 is written in tc7st) when the tc7 pin is at a stop level, the counter does not start (inttc7p does not occur); a subsequent trigger start edge causes the counter to start and inttc7t to occur. 9.4.7.3 intemg (emergency output stop interrupt) an emergency output stop interrupt (intemg) occurs when the emergency output stop circuit operates to stop ppg outputs in emergency. 9.4.8 emergency ppg output stop feature setting tc7cr2 page 95 TMP86FH12MG 9.4.8.3 emg interrupt an emg interrupt (intemg) occurs when an emergency ppg out put stop input is accepted. to use an intemg interrupt for some processing, ensure that the interrupt is enabled beforehand. when the emg pin is low with emgie set to 1 ( emg pin input enabled), an at tempt to cancel the emer- gency ppg output stop state results in an interrupt being generated again, with the emergency ppg output stop state reestablished. an intemg interrupt occurs when ever a stop input is accepted when emgie = 1, regardless of whether the timer is operating. 9.4.8.4 canceling the emergency ppg output stop state to cancel the emergency ppg output stop state, en sure that the input on the emg pin is high, set tc7cr3 page 96 9. 10-bit timer/counter (tc7) 9.4 features TMP86FH12MG figure 9-23 timing between emg pin input being detected and ppg outputs being dis- abled 9.4.9 tc7 operation and mi crocontroller operating mode the tc7 operates when the microcontroller is pl aced in normal1, normal2, idle1, or idle2 mode. if the mode changes from normal or idle to stop, sl ow, or sleep while the tc7 is operating, the tc7 is initialized and stops operating. to change the microcontroller operating mode from normal or idle to stop, slow, or sleep, ensure that the tc7 timer is stopped before attempting to execute a mode change instruction. to change the mode from stop, slow, or sleep to normal to restart the tc7, reconfigure all registers according to the appropriate tc7 operation procedure. ppg pin output emg pin input emgie 10/fc [s] 1.25 s (at 8 mhz) tc7st stm emgf ( state monitor ) emg interrupt specified with an instruction emergency stop input output initialized forcibly initial output state emergency stop input share port in input mode emgr = 1, protection feature enabled intemg (emg interrupt) emgf = 1, emergency output stop state emergency output stop state tc7st = 1, timer operating stm = 01, timer operating (continuous mode) emgr = 1, cancel emergency output stop state stm = 00 tg7st = 0 page 97 TMP86FH12MG 10. 16-bit timercounter 1 (tc1) 10.1 configuration figure 10-1 timercounter 1 (tc1) :::? pin tc1 :w:?::? mett1 start capture clear source clock ppg output mode write to tc1cr 16-bit up-counter clear tc1drb selector tc1dra tc1cr tc1 control register match inttc1 interript tff1 acap1 tc1ck window mode set toggle q 2 toggle set clear q y a d b c s b a y s tc1s clear mppg1 ppg output mode internal reset s enable mcap1 s y a b tc1s 2 set clear command start decoder external trigger start edge detector note: function i/o may not operate depending on i/o port setting. for more details, see the chapter "i/o port". port (note) q pulse width measurement mode falling rising trigger external cmp 16-bit timer register a, b pulse width measurement mode port (note) fc/2 11, fs/2 3 fc/2 7 fc/2 3 page 98 10. 16-bit timercounter 1 (tc1) 10.2 timercounter control TMP86FH12MG 10.2 timercounter control the timercounter 1 is controlled by the timercounter 1 control register (tc1cr) and two 16-bit timer registers (tc1dra and tc1drb). note 1: fc: high-frequency clock [hz], fs: low-frequency clock [hz] note 2: the timer register consists of two shift registers. a va lue set in the timer register becomes valid at the rising edge o f the first source clock pulse that occurs after the upper byte (t c1drah and tc1drbh) is written. therefore, write the lower byte and the upper byte in this order (it is recommended to write the register with a 16-bit acce ss instruction). writing only the lower byte (tc1dral and tc1drbl) does not enable the setting of the timer register. note 3: to set the mode, source clock, ppg output control and time r f/f control, write to tc1cr1 during tc1s=00. set the timer f/f1 control until the first timer start after setting the ppg mode. timer register 1514131211109876543210 tc1dra (0011h, 0010h) tc1drah (0011h) tc1dral (0010h) (initial value: 1111 1111 1111 1111) read/write tc1drb (0013h, 0012h) tc1drbh (0013h) tc1drbl (0012h) (initial value: 1111 1111 1111 1111) read/write (write e nabled only in the ppg output mode) timercounter 1 control register tc1cr (0014h) 76543210 tff1 acap1 mcap1 mett1 mppg1 tc1s tc1ck tc1m read/write (initial value: 0000 0000) tff1 timer f/f1 control 0: clear 1: set r/w acap1 auto capture control 0:auto-capture disable 1:auto-capture enable r/w mcap1 pulse width measure- ment mode control 0:double edge capture 1:single edge capture mett1 external trigger timer mode control 0:trigger start 1:trigger start and stop mppg1 ppg output control 0:continuous pulse generation 1:one-shot tc1s tc1 start control timer extrig- ger event win- dow pulse ppg r/w 00: stop and counter clear oooooo 01: command start o????o 10: rising edge start (ex-trigger/pulse/ppg) rising edge count (event) positive logic count (window) ? ooooo 11: falling edge start (ex-trigger/pulse/ppg) falling edge count (event) negative logic count (window) ? ooooo tc1ck tc1 source clock select [hz] normal1/2, idle1/2 mode divider slow, sleep mode r/w dv7ck = 0 dv7ck = 1 00 fc/2 11 fs/2 3 dv9 fs/2 3 01 fc/2 7 fc/2 7 dv5 ? 10 fc/2 3 fc/2 3 dv1 ? 11 external clock (tc1 pin input) tc1m tc1 operating mode select 00: timer/external trigger timer/event counter mode 01: window mode 10: pulse width measurement mode 11: ppg (programmable pulse generate) output mode r/w page 99 TMP86FH12MG note 4: auto-capture can be used only in t he timer, event counter, and window modes. note 5: to set the timer registers, the following relationship must be satisfied. tc1dra > tc1drb > 1 (ppg output mode), tc1dra > 1 (other modes) note 6: set tff1 to ?0? in the mode except ppg output mode. note 7: set tc1drb after setting tc1m to the ppg output mode. note 8: when the stop mode is entered, the start control (tc1s) is cleared to ?00? automatically, and the timer stops. after the stop mode is exited, set the tc1s to use the timer counter again. note 9: use the auto-capture function in the operative condition of tc1. a captured value may not be fixed if it's read after th e execution of the timer stop or auto-capture disable. read the capture value in a capture enabled condition. note 10:since the up-counter value is captured into tc1drb by the source clock of up-counter after setting tc1cr page 100 10. 16-bit timercounter 1 (tc1) 10.3 function TMP86FH12MG 10.3 function timercounter 1 has six types of operating modes: timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output modes. 10.3.1 timer mode in the timer mode, the up-counter counts up using the internal clock. when a match between the up-counter and the timer register 1a (tc1dra) value is detected, an inttc1 interr upt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counting. setting tc1cr page 101 TMP86FH12MG figure 10-2 timer mode timing chart match detect acap1 tc1drb tc1dra inttc1 interruput request source clock counter source clock counter ? (a) timer mode (b) auto-capture ? 7 6 345 0 timer start 12 3 2 1 4 0 counter clear capture n + 1 n n n m + 2 m + 1 m m capture m + 2 m + 1 n + 1 n m ? 1 m ? 1 m ? 2 n ? 1 n ? 1 n ? 1 page 102 10. 16-bit timercounter 1 (tc1) 10.3 function TMP86FH12MG 10.3.2 external tr igger timer mode in the external trigger timer mode, the up-counter starts counting by the input pulse triggering of the tc1 pin, and counts up at the edge of the internal clock. for the trigger edge used to start counting, either the rising or falling edge is defined in tc1cr page 103 TMP86FH12MG figure 10-3 external tri gger timer mode timing chart inttc1 interrupt request source clock up-counter tc1dra tc1 pin input inttc1 interrupt request source clock up-counter tc1dra tc1 pin input 0 at the rising edge (tc1s = 10) at the rising edge (tc1s = 10) (a) trigger start (mett1 = 0) count start match detect count start 0 1 2 3 4 2 3 n (b) trigger start and stop (mett1 = 1) count start count start 0 1 2 3 m 0 n n 0 count clear note: m < n count clear 1 2 3 1 n m ? 1 n ? 1 match detect count clear page 104 10. 16-bit timercounter 1 (tc1) 10.3 function TMP86FH12MG 10.3.3 event counter mode in the event counter mode, the up-counter counts up at the edge of the input pulse to the tc1 pin. either the rising or falling edge of the input pulse is se lected as the count up edge in tc1cr page 105 TMP86FH12MG 10.3.4 window mode in the window mode, the up-counter counts up at the rising edge of the pulse that is logical anded product of the input pulse to the tc1 pin (window pulse) and the internal source clock. eith er the positive logic (count up during high-going pulse) or negative logic (count up during low-going pulse) can be selected. when a match between the up-counter and the tc1dra va lue is detected, an inttc1 interrupt is generated and the up-counter is cleared. define the window pulse to the frequency which is sufficiently lower than the internal source clock pro- grammed with tc1cr page 106 10. 16-bit timercounter 1 (tc1) 10.3 function TMP86FH12MG 10.3.5 pulse widt h measurement mode in the pulse width measurement mode, the up-counter starts counting by the input pulse triggering of the tc1 pin, and counts up at the edge of the internal clock. either the rising or falling edge of the internal clock is selected as the trigger edge in tc1cr< tc1s>. either the single- or double-e dge capture is selected as the trig- ger edge in tc1cr page 107 TMP86FH12MG example :duty measurem ent (resolution fc/2 7 [hz]) clr (inttc1sw). 0 ; inttc1 serv ice switch initial setting address set to convert inttc1sw at each inttc1 ld (tc1cr), 00000110b ; sets the tc1 mode and source clock di ; imf = ?0? set (eirl). 7 ; enables inttc1 ei ; imf = ?1? ld (tc1cr), 00100110b ; starts tc1 with an external trigger at mcap1 = 0 : pinttc1: cpl (inttc1sw). 0 ; inttc1 interrupt, inverts and tests inttc1 service switch jrs f, sinttc1 ld a, (tc1drbl) ; reads tc1drb (high-level pulse width) ld w,(tc1drbh) ld (hpulse), wa ; stores high-level pulse width in ram reti sinttc1: ld a, (tc1drbl) ; reads tc1drb (cycle) ld w,(tc1drbh) ld (width), wa ; stores cycle in ram : reti ; duty calculation : vinttc1: dw pinttc1 ; inttc1 interrupt vector width hpulse tc1 pin inttc1 interrupt request inttc1sw page 108 10. 16-bit timercounter 1 (tc1) 10.3 function TMP86FH12MG figure 10-6 pulse wi dth measurement mode tc1drb inttc1 interrupt request interrupt request tc1 pin input counter internal clock (mcap1 = "1") 23 n count start count start trigger (tc1s = "10") 1 3 2 1 4 0 n 0 capture n - 1 tc1drb inttc1 tc1 pin input counter internal clock (mcap1 = "0") 12 n count start count start (tc1s = "10") 3 2 1 4 0 n capture capture n + 1 m - 2 n + 3 n + 2 n + 1 m - 1 m0 m [application] high-or low-level pulse width measurement [application] (1) cycle/frequency measurement (2) duty measurement (a) single-edge capture (b) double-edge capture page 109 TMP86FH12MG 10.3.6 programmable pulse generate (ppg) output mode in the programmable pulse generation (ppg) mode, an arbitrary duty pulse is generated by counting per- formed in the internal clock. to start the timer, tc1c r page 110 10. 16-bit timercounter 1 (tc1) 10.3 function TMP86FH12MG figure 10-7 ppg output example :generating a pulse which is high-going for 800 s and low-going for 200 s (fc = 16 mhz) setting port ld (tc1cr), 10000111b ; sets the ppg mode, selects the source clock ldw (tc1dra), 007dh ; sets the cycle (1 ms 2 7 /fc ms = 007dh) ldw (tc1drb), 0019h ; sets the low-level pulse width (200 s 2 7 /fc = 0019h) ld (tc1cr), 10010111b ; starts the timer example :after stopping ppg, setting the ppg pin to a high-level to restart ppg (fc = 16 mhz) setting port ld (tc1cr), 10000111b ; sets the ppg mode, selects the source clock ldw (tc1dra), 007dh ; sets the cycle (1 ms 2 7 /fc s = 007dh) ldw (tc1drb), 0019h ; sets the low-level pulse width (200 s 2 7 /fc = 0019h) ld (tc1cr), 10010111b ; starts the timer :: ld (tc1cr), 10000111b ; stops the timer ld (tc1cr), 10000100b ; sets the timer mode ld (tc1cr), 00000111b ; sets the ppg mode, tff1 = 0 ld (tc1cr), 00010111b ; starts the timer q r d ppg pin function output port output enable i/o port output latch shared with ppg output data output toggle set clear q tc1cr page 111 TMP86FH12MG figure 10-8 ppg mode timing chart inttc1 tc1dra internal clock counter tc1drb tc1dra ppg pin output 0 inttc1 interrupt request interrupt request 12 m01 2 n m01 n 2 n n + 1 n + 1 m (a) continuous pulse generation (tc1s = 01) tc1drb trigger count start timer start counter internal clock tc1 pin input ppg pin output 0 1m n n n + 1 m 0 (b) one-shot pulse generation (tc1s = 10) match detect note: m > n note: m > n [application] one-shot pulse output page 112 10. 16-bit timercounter 1 (tc1) 10.3 function TMP86FH12MG page 113 TMP86FH12MG 11. 8-bit timercounter (tc3, tc4) 11.1 configuration figure 11-1 8-bit timercouter 3, 4 8-bit up-counter decode en a y b s a b y c d e f g h s a y b s s a y b toggle q set clear 8-bit up-counter a b y c d e f g h s decode en toggle q set clear pwm mode pdo, ppg mode pdo mode pwm, ppg mode pwm mode pwm mode 16-bit mode 16-bit mode 16-bit mode 16-bit mode timer, event counter mode overflow overflow timer, event couter mode 16-bit mode clear clear fc/2 7 fc/2 5 fc/2 3 fc/2 fc fc/2 7 fc/2 5 fc/2 3 fc/2 fc pdo, pwm, ppg mode pdo, pwm mode 16-bit mode fc/2 11 or fs/2 3 fc/2 11 or fs/2 3 fs fs tc4cr tc3cr ttreg4 pwreg4 ttreg3 pwreg3 tc3 pin tc4 pin tc4s tc3s inttc3 interrupt request inttc4 interrupt request tff4 tff3 pdo 4/pwm 4/ ppg 4 pin pdo 3/pwm 3/ pin tc3ck tc4ck tc3m tc3s tff3 tc4m tc4s tff4 timer f/f4 timer f/f3 page 114 11. 8-bit timercounter (tc3, tc4) 11.1 configuration TMP86FH12MG 11.2 timercounter control the timercounter 3 is controlled by the timercounter 3 control register (tc3cr) and two 8-bit timer registers (ttreg3, pwreg3). note 1: do not change the timer register (t treg3) setting while the timer is running. note 2: do not change the timer register (pwreg3) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. note 1: fc: high-frequency clock [hz] fs: low-frequency clock[hz] note 2: do not change the tc3m, tc3ck and tff3 settings while the timer is running. note 3: to stop the timer operation (tc3s= 1 0), do not change the tc3m, tc3ck and tff3 settings. to start the timer opera- tion (tc3s= 0 1), tc3m, tc3ck and tff3 can be programmed. note 4: to use the timercounter in the 16-bit mode, set th e operating mode by programming tc4cr page 115 TMP86FH12MG note 7: the timer register settings are limited depending on the timer operating mode. for the detailed descriptions, see table 11- 3. note 8: the operating clock fc in t he slow or sleep mode can be used only as the high-frequency warm-up mode. page 116 11. 8-bit timercounter (tc3, tc4) 11.1 configuration TMP86FH12MG the timercounter 4 is controlled by the timercounter 4 control register (tc4cr) and two 8-bit timer registers (ttreg4 and pwreg4). note 1: do not change the timer register (t treg4) setting while the timer is running. note 2: do not change the timer register (pwreg4) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. note 1: fc: high-frequency clock [hz] fs: low-frequency clock [hz] note 2: do not change the tc4m, tc4ck and tff4 settings while the timer is running. note 3: to stop the timer operation (tc4s= 1 0), do not change the tc4m, tc4ck and tff4 settings. to start the timer operation (tc4s= 0 1), tc4m, tc4ck and tff4 can be programmed. note 4: when tc4m= 1** (upper byte in the 16-bit mode), the sour ce clock becomes the tc4 over flow signal regardless of the tc3ck setting. note 5: to use the timercounter in the 16-bit mode, select the operating mode by programming tc4m, where tc3cr page 117 TMP86FH12MG note 6: to the timercounter in the 16-bit mode, select the so urce clock by programming tc3cr page 118 11. 8-bit timercounter (tc3, tc4) 11.1 configuration TMP86FH12MG note: n = 3 to 4 table 11-3 constraints on register values being compared operating mode register value 8-bit timer/event counter 1 (ttregn) 255 8-bit pdo 1 (ttregn) 255 8-bit pwm 2 (pwregn) 254 16-bit timer/event counter 1 (ttreg4, 3) 65535 warm-up counter 256 (ttreg4, 3) 65535 16-bit pwm 2 (pwreg4, 3) 65534 16-bit ppg 1 (pwreg4, 3) < (ttreg4, 3) 65535 and (pwreg4, 3) + 1 < (ttreg4, 3) page 119 TMP86FH12MG 11.3 function the timercounter 3 and 4 have the 8-bit timer, 8-bit ev ent counter, 8-bit programmable divider output (pdo), 8- bit pulse width modulation (pwm) output modes. the time rcounter 3 and 4 (tc3, 4) are cascadable to form a 16- bit timer. the 16-bit timer has the operat ing modes such as the 16-bit timer, 16-bit event counter, warm-up counter, 16-bit pulse width modulation (pwm) output and 16-bit programmable pulse generation (ppg) modes. 11.3.1 8-bit timer mode (tc3 and 4) in the timer mode, the up-counter counts up using the internal clock. when a match between the up-counter and the timer register j (ttregj) value is detected, an inttcj interrupt is generated and the up-counter is cleared. after being cl eared, the up-counter restarts counting. note 1: in the timer mode, fix tcjcr page 120 11. 8-bit timercounter (tc3, tc4) 11.1 configuration TMP86FH12MG figure 11-2 8-bit time r mode timing chart (tc4) 11.3.2 8-bit event counter mode (tc3, 4) in the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the tcj pin. when a match between the up-counter and the ttregj valu e is detected, an inttcj interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counti ng at the falling edge of the input pulse to the tcj pin. two machine cycles are required for the low- or high-level pulse input to the tcj pin. therefore, a maximum freque ncy to be supplied is fc/2 4 hz in the normal1/2 or idle1/2 mode, and fs/2 4 hz in the slow1/2 or sleep1/2 mode. note 1: in the event counter mode, fix tcjcr page 121 TMP86FH12MG note 1: in the programmable divider output mode, do not change the ttregj setting while the timer is running. since ttregj is not in the shift register configur ation in the programmable divider output mode, the new value programmed in ttregj is in effect immediatel y after programming. therefore, if ttregi is changed while the timer is running, an ex pected operation may not be obtained. note 2: when the timer is stopped during pdo output, the pdoj pin holds the output status when the timer is stopped. to change the output status, program tcjcr page 122 11. 8-bit timercounter (tc3, tc4) 11.1 configuration TMP86FH12MG figure 11-4 8-bit pdo mode timing chart (tc4) 12 0 n 0 n 0 n 0 n 0 1 2 2 1 2 1 2 3 1 0 n ? internal source clock counter match detect match detect match detect match detect held at the level when the timer is stopped set f/f write of "1" tc4cr page 123 TMP86FH12MG 11.3.4 8-bit pulse width modulat ion (pwm) output mode (tc3, 4) this mode is used to generate a pulse-width modulated (pwm) signals with up to 8 bits of resolution. the up-counter counts up using the internal clock. when a match between the up-counter and the pwregj value is detected, the logic level output from the timer f/fj is switched to the opposite state. the counter continues counting. the logic level output from the timer f/fj is switched to the opposite state again by the up-co unter overflow, and the counter is cleared. the inttcj interrupt request is generated at this time. since the initial value can be set to the timer f/fj by tcjcr page 124 11. 8-bit timercounter (tc3, tc4) 11.1 configuration TMP86FH12MG figure 11-5 8-bit pwm mode timing chart (tc4) 1 0 n n+1 ff 0 n n+1 ff 0 1 m m+1 ff 0 1 1 p n ? internal source clock counter write to pwreg4 write to pwreg4 m p m p n ? shift registar shift shift shift shift match detect match detect one cycle period match detect match detect n m p n tc4cr page 125 TMP86FH12MG 11.3.5 16-bit timer mode (tc3 and 4) in the timer mode, the up-counter counts up using the internal clock. the timercounter 3 and 4 are cascad- able to form a 16-bit timer. when a match between the up-counter and the timer regi ster (ttreg3, ttreg4) valu e is detected after the timer is started by setting tc4cr page 126 11. 8-bit timercounter (tc3, tc4) 11.1 configuration TMP86FH12MG 11.3.6 16-bit event c ounter mode (tc3 and 4) 11.3.7 16-bit pulse width modulatio n (pwm) output mode (tc3 and 4) this mode is used to generate a pulse-width modulated (pwm) signals with up to 16 bits of resolution. the timercounter 3 and 4 are cascadable to form the 16-bit pwm signal generator. the counter counts up using the internal clock or external clock. when a match between the up-counter and the timer register (pwreg3, pwreg4) value is detected, the logic level output from the timer f/f4 is switched to the opposite state. the counter continues counting. the logic level output from the timer f/f4 is switched to the opposite state again by the counter overflow, and the counter is cleared. the inttc4 interrupt is generated at this time. two machine cycles are required for the high- or low-level pulse input to the tc3 pin. therefore, a maxi- mum frequency to be supplied is fc/2 4 hz in the normal1 or idle1 mode, and fs/2 4 to in the slow1/2 or sleep1/2 mode. since the initial value can be set to the timer f/f4 by tc4cr page 127 TMP86FH12MG clr (tc4cr).3: stops the timer. clr (tc4cr).7 : sets the pwm 4 pin to the high level. note 3: to enter the stop mode, stop the timer and then enter the stop mode. if the stop mode is entered with- out stopping of the timer when fc, fc/2 or fs is select ed as the source clock, a pulse is output from the pwm 4 pin during the warm-up period time after exiting the stop mode. table 11-7 16-bit pwm output mode source clock resolution repeated cycle normal1/2, idle1/2 mode slow1/2, sleep1/2 mode fc = 16 mhz fs = 32.768 khz fc = 16 mhz fs = 32.768 khz dv7ck = 0 dv7ck = 1 fc/2 11 fs/2 3 [hz] fs/2 3 [hz] 128 s244.14 s 8.39 s 16 s fc/2 7 fc/2 7 ?8 s ? 524.3 ms ? fc/2 5 fc/2 5 ?2 s ? 131.1 ms ? fc/2 3 fc/2 3 ? 500ns ? 32.8 ms ? fs fs fs 30.5 s30.5 s2 s 2 s fc/2 fc/2 ? 125 ns ? 8.2 ms ? fc fc ? 62.5 ns ? 4.1 ms ? example :generating a pulse with 1-ms high-level width and a period of 32.768 ms (fc = 16.0 mhz) setting ports ldw (pwreg3), 07d0h : sets the pulse width. ld (tc3cr), 33h : sets the operating clock to fc/2 3 , and 16-bit pwm output mode (lower byte). ld (tc4cr), 056h : sets tff4 to the initial value 0, and 16-bit pwm signal generation mode (upper byte). ld (tc4cr), 05eh : starts the timer. page 128 11. 8-bit timercounter (tc3, tc4) 11.1 configuration TMP86FH12MG figure 11-7 16-bit pwm mode timing chart (tc3 and tc4) 1 0 an an+1 ffff 0 an an+1 ffff 0 1 bm bm+1 ffff 0 bm cp b c 1 1 cp n a an ? ? ? internal source clock 16-bit shift register shift shift shift shift counter match detect match detect one cycle period match detect match detect an bm cp an m p tc4cr page 129 TMP86FH12MG 11.3.8 16-bit programmable pulse generate (ppg) ou tput mode (tc3 and 4) this mode is used to generate pulses with up to 16- bits of resolution. the timer counter 3 and 4 are cascad- able to enter the 16-bit ppg mode. the counter counts up using the inte rnal clock or external clock. when a match between the up-counter and the timer register (pwreg3, pwreg4 ) value is detected, the logic level output from the timer f/f4 is switched to the opposite state. the counter continues counting. the logic level output from the timer f/f4 is switched to the opposite state again when a match betw een the up-counter and th e timer register (ttreg3, ttreg4) value is detected, and the counter is cleared. the inttc4 interrupt is generated at this time. since the initial value can be set to the timer f/f4 by tc4cr page 130 11. 8-bit timercounter (tc3, tc4) 11.1 configuration TMP86FH12MG figure 11-8 16-bit ppg mode timing chart (tc3 and tc40) 1 0 mn mn+1 qr-1 mn qr-1 1 mn mn+1 mn+1 0 qr 0 qr 1 0 internal source clock counter write of "0" match detect match detect match detect mn mn mn match detect match detect ? n m ? ? r q ? held at the level when the timer stops f/f clear tc4cr page 131 TMP86FH12MG 11.3.9 warm-up counter mode in this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. the timer counter 3 and 4 are cascadable to form a 16-bit timercouter. the warm-up counter mode has two types of mode; switching from the high-frequency to low-frequency, and vice-versa. note 1: in the warm-up counter mode, fi x tcicr page 132 11. 8-bit timercounter (tc3, tc4) 11.1 configuration TMP86FH12MG 11.3.9.2 high-frequency warm-up counter mode (slow1 slow2 normal2 normal1) in this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation sta- bility is obtained. before starting the timer, set sy scr2 page 133 TMP86FH12MG 12. synchronous serial interface (sio) the TMP86FH12MG has a clocked-synchron ous 8-bit serial interface. serial interface has an 8-byte transmit and receive data buffer that can automatically and continuously transfer up to 64 bits of data. serial interface is connected to outside peripherl devices via so, si, sck port. 12.1 configuration figure 12-1 serial interface sio control / status register serial clock shift clock shift register 3 2 1 0 7 6 5 4 transmit and receive data buffer (8 bytes in dbr) control circuit cpu serial data output serial data input 8-bit transfer 4-bit transfer serial clock i/o buffer control circuit so si sck siocr2 siocr1 siosr intsio interrupt request page 134 12. synchronous serial interface (sio) 12.2 control TMP86FH12MG 12.2 control the serial interface is controlled by sio control registers (s iocr1/siocr2). the serial interface status can be determined by reading sio status register (siosr). the transmit and receive data buffer is controlled by the siocr2 page 135 TMP86FH12MG note 1: the lower 4 bits of each buffer are used during 4-bit tr ansfers. zeros (0) are stored to the upper 4bits when receiving. note 2: transmitting starts at the lowest address. received data are also stored starting from the lowest address to the highest address. ( the first buffer address transmitted is 0f80h ). note 3: the value to be loaded to buf is held after transfer is completed. note 4: siocr2 must be set when the serial interface is stopped (siof = 0). note 5: *: don't care note 6: siocr2 is write-only register, whic h cannot access any of in read-modify-wri te instruction such as bit operate, etc. note 1: t f ; frame time, t d ; data transfer time note 2: after sios is cleared to "0", siof is cleared to "0" at the termination of transfer or the setting of sioinh to "1". figure 12-2 fr ame time (t f ) and data transfer time (t d ) 12.3 serial clock 12.3.1 clock source internal clock or external clock for the source clock is selected by siocr1 page 136 12. synchronous serial interface (sio) 12.3 serial clock TMP86FH12MG 12.3.1.1 internal clock any of six frequencies can be selected. the serial clock is output to the outside on the sck pin. the sck pin goes high when transfer starts. when data writing (in the transmit mo de) or reading (in the receive mode or the transmit/receive mode) cannot keep up with the serial clock rate, there is a wa it function that automatically stops the serial clock and holds the next shift operation until the read/write processing is completed. note: 1 kbit = 1024 bit (fc = 16 mhz, fs = 32.768 khz) figure 12-3 automatic wait fu nction (at 4-bit transmit mode) 12.3.1.2 external clock an external clock connected to the sck pin is used as the serial clock. in this case, output latch of this port should be set to "1". to ensure shifting, a pulse width of at least 4 machine cycles is required. this pulse is needed for the shift operatio n to execute certainly. actually, there is necessary processing time for interrupting, writing, and reading. the minimum pulse is determined by setting the mode and the pro- gram. therfore, maximum transfer frequenc y will be 488.3k bit/sec (at fc=16mhz). figure 12-4 external clock pulse width table 12-1 serial clock rate normal1/2, idle1/2 mode slow1/2, sleep1/2 mode dv7ck = 0 dv7ck = 1 sck clock baud rate clock baud rate clock baud rate 000 fc/2 13 1.91 kbps fs/2 5 1024 bps fs/2 5 1024 bps 001 fc/2 8 61.04 kbps fc/2 8 61.04 kbps - - 010 fc/2 7 122.07 kbps fc/2 7 122.07 kbps - - 011 fc/2 6 244.14 kbps fc/2 6 244.14 kbps - - 100 fc/2 5 488.28 kbps fc/2 5 488.28 kbps - - 101 fc/2 4 976.56 kbps fc/2 4 976.56 kbps - - 110 - - - - - - 111 external external external external external external a 1 a 2 b 0 b 1 b 2 b 3 c 0 c 1 a 3 a c b a 0 pin (output) pin (output) written transmit data a utomat i ca ll y wait function sck so t sckl t sckh tcyc = 4/fc (in the normal1/2, idle1/2 modes) 4/fs (in the slow1/2, sleep1/2 modes) t sckl , t sckh > 4tcyc sck pin (output) page 137 TMP86FH12MG 12.3.2 shift edge the leading edge is used to transmit, a nd the trailing edge is used to receive. 12.3.2.1 leading edge transmitted data are shifted on the leading ed ge of the serial clock (falling edge of the sck pin input/ output). 12.3.2.2 trailing edge received data are shifted on the trailing edge of the serial clock (rising edge of the sck pin input/out- put). figure 12-5 shift edge 12.4 number of bits to transfer either 4-bit or 8-bit serial transfer can be selected. when 4-bit serial transfer is selected, only the lower 4 bits of the transmit/receive data buffer re gister are used. the upper 4 bits are cleared to ?0? when receiving. the data is transferred in sequence star ting at the least significant bit (lsb). 12.5 number of w ords to transfer up to 8 words consisting of 4 bits of data (4-bit serial tran sfer) or 8 bits (8-bit serial tr ansfer) of data can be trans- ferred continuously. the number of words to be transferred can be selected by siocr2 page 138 12. synchronous serial interface (sio) 12.6 transfer mode TMP86FH12MG figure 12-6 number of words to transfer (example: 1word = 4bit) 12.6 transfer mode siocr1 page 139 TMP86FH12MG siocr1 page 140 12. synchronous serial interface (sio) 12.6 transfer mode TMP86FH12MG figure 12-9 transmiiied data ho ld time at end of transfer 12.6.2 4-bit and 8- bit receive modes after setting the control registers to the receive mode , set siocr1 |