ics680-01 mds 680-01 f 1 revision 020305 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com networking clock synthesizer and zero delay buffer description the ics680-01 generates four high-frequency clock outputs and a reference from a 25 mhz crystal or clock input. the device includes a low-skew, single input to four output zero delay clock buffer. it can replace multiple crystals and oscillators, saving board space and cost. the device has a power-down tri-state (pdts ) pin that place the clock outputs in a high-impedance state when pulled low. the pdts pin includes an internal pull-up resistor. features ? packaged in 24-pin tssop ? available in pb (lead) free package ? replaces multiple cr ystals and oscillators ? input crystal or clock frequency of 25 mhz ? five output driver driven by external clock ? duty cycle of 45/55 ? operating voltage of 3.3 v ? advanced, low-power cmos process ? fixed output frequencies of 25 mhz and 48 mhz ? selectable output frequencies of 24 mhz, 48 mhz, 50 mhz and 66.6666 mhz ? qx outputs replace costly discrete buffer ? low-skew buffer outputs (250 ps) block diagram divide logic and output enable control external capacitors may be required. s0 vdd clk2 clk1 48m 25m q0 5 q2 q3 gnd pdts 2 x1/iclk x2 crystal oscillator 25 mhz crystal or clock plla pllb q1 iclk s1 pll/buffer pllc qfb
networking clock synthesizer and zero delay buffer mds 680-01 f 2 revision 020305 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics680-01 pin assignment output clock select table pin descriptions 13 4 5 clk1 8 9 10 25m q1 qfb 48m q2 vdd 17 16 vdd 3 s0 vdd s1 18 pdts 1 x1/iclk gnd vdd 20 x2 19 14 2 7 gnd gnd iclk vdd 15 6 24-pin tssop 11 12 gnd q3 clk2 q4 21 22 23 24 s0 s1 clk1 (mhz) clk2 (mhz) mm off 48 0 0 50 48 0 1 66.6666 48 1 0 50 24 1 1 66.6666 24 pin number pin name pin type pin description 1 x1/iclk xi crystal input. connect this pin to a crystal or external clock source. 2 gnd power connect to ground. 3 s0 input select pin 0. see table above. 4 vdd power connect to voltage supply. 5 clk1 output selectable output clock. see table above. weak internal pull-down when tri-state. 6 gnd power connect to ground. 7 gnd power connect to ground. 8 q1 output clock output 1. weak internal pull-down when tri-state. 9 q2 output clock output 2. weak internal pull-down when tri-state. 10 vdd power connect to voltage supply. 11 q3 output clock output 3. weak internal pull-down when tri-state. 12 q4 output clock output 4. weak internal pull-down when tri-state. 13 gnd power connect to ground. 14 clk2 output selectable output clock. see table above. weak internal pull-down when tri-state. 15 48m output 48 mhz output clock. weak internal pull-down when tri-state. 16 vdd power connect to voltage supply. 17 qfb output feedback pin. internally connected.
networking clock synthesizer and zero delay buffer mds 680-01 f 3 revision 020305 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics680-01 external components the ics680-01 requires a minimum number of external components for proper operation. decoupling capacitor a decoupling capacitor of 0.01f must be connected between vdd (pins 5 and 16) and gnd (pins 6 and 15), as close to these pins as possible. for optimum device performance, the decoupling capacitor should be mounted on the component side of the pcb. avoid the use of vias in the decoupling circuit. series termination resistor when the pcb trace between the clock outputs and the loads are over 1 inch, series termination should be used. to series terminate a 50 ? trace (a commonly used trace impedance) place a 33 ? resistor in series with the clock line, as close to the clock output pin as possible. the nominal impedance of the clock output is 20 ? . crystal information the crystal used should be a fundamental mode (do not use third overtone), parallel resonant. crystal capacitors should be connected from pins x1 to ground and x2 to ground to optimize the initial accuracy. the value of these capacitors is given by the following equation crystal caps (pf) = (c l -6)x2 in the equation, c l is the crystal load capacitance. so for a crystal with a 16 pf load capacitance, two 20 pf[(16-6)x2] capacitors should be used pcb layout recommendations for optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) the 0.01f decoupling capacitor should be mounted on the component side of the board as close to the vdd pin as possible. no vias should be used between decoupling capacitor and vdd pin. the pcb trace to vdd pin should be kept as short as possible, as should the pcb trace to the ground via. 2) the external crystal should be mounted just next to the device with short traces. the x1 and x2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) to minimize emi, the 33 ? series termination resistor (if needed) should be placed close to the clock output. 4) an optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. other signal traces should be routed away from the ics680-01. this includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. 18 vdd power connect to voltage supply. 19 iclk input zero delay buffer input. weak internal pull-up. 20 25m output 25 mhz reference output clock. weak internal pull-down when tri-state. 21 s1 input select pin 1. see table above. 22 pdts power power-down tri-state. powers down entire chip and tri-states outputs when low. internal pull-up resistor. 23 vdd power connect to voltage supply. 24 x2 xo crystal output. connect this pin to a crystal. float for clock input. pin number pin name pin type pin description
networking clock synthesizer and zero delay buffer mds 680-01 f 4 revision 020305 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics680-01 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the ics680-01. these ratings, which are standard values for ics commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions item rating supply voltage, vdd 7 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature 0 to +70 c storage temperature -65 to +150 c junction temperature 125 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature 0 +70 c power supply voltage (measured in respect to gnd) +3.13 +3.3 +3.46 v
networking clock synthesizer and zero delay buffer mds 680-01 f 5 revision 020305 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics680-01 dc electrical characteristics unless stated otherwise, vdd = 3.3 v 5% , ambient temperature 0 to +70 c parameter symbol conditions min. typ. max. units operating voltage vdd 3.13 3.3 3.46 v supply current idd no load,pdts =1 32 ma no load,pdts =0 300 a input high voltage, binary inputs v ih pdts , iclk 2 v input high voltage, trinary inputs v ih s0, s1 vdd-0.5 v input low voltage, binary inputs v il pdts , iclk 0.8 v input low voltage, trinary inputs v il s0, s1 0.5 v output high voltage v oh i oh = -4 ma vdd-0.4 v output high voltage v oh i oh = -12 ma 2.4 v output low voltage v ol i ol = 12 ma 0.8 v i ol = 4 ma 0.4 v short circuit current i os clk output 50 ma input capacitance, inputs c in 5pf nominal output impedance z out 20 ? on-chip pull-up resistor, inputs r pu pdts , sel 250 k ? on-chip pull-down resistor, outputs r pd clk outputs 250 k ?
networking clock synthesizer and zero delay buffer mds 680-01 f 6 revision 020305 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics680-01 ac electrical characteristics unless stated otherwise, vdd = 3.3 v 5% , ambient temperature 0 to +70 c note 1: measured with a 15 pf load. note 2: duty cycle is configuration dependent. most configurations are min 45% / max 55%. note 3: skew is measured at 1.4 v on rising edges with a 33 mhz iclk. parameter symbol conditions min. typ. max. units input frequency f in x1 25 mhz iclk 33 mhz output frequency f out q0 to q3, qfb, note 1 33 mhz output rise time t or 20% to 80%, note 1 1.5 ns output fall time t of 80% to 20%, note 1 1.5 ns output clock duty cycle t d at vdd/2, note 2 40 60 % power-up time pll lock-time from power-up to 1% of final frequency 10 ms pdts goes high until stable clk outputs at 1% of final frequency 2ms one sigma clock period jitter configuration dependent 50 ps maximum absolute jitter t ja deviation from mean. configuration dependent. 200 ps qfb to iclk skew t pd measured at vdd/2, note 3 -350 350 pin-to-pin skew qfb, q0 to q3, note 3 -250 250 ps
networking clock synthesizer and zero delay buffer mds 680-01 f 7 revision 020305 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics680-01 package outline and package dimensions (24-pin tssop, 173 mil. body) package dimensions are kept current with jedec publication no. 95 ordering information ?lf? denotes pb (lead) free package. while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems (ics) assumes no responsibility for either its use or for the infringemen t of any patents or other rights of third parties, which wou ld result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring ex tended temperature range, high re liability, or other extraordina ry environmental requirements are not recomm ended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices o r critical medical instruments. part / order number marking shipping packaging package temperature ics680g-01 680g-01 tubes 24-pin tssop 0 to +70 c ICS680G-01T 680g-01 tape and reel 24-pin tssop 0 to +70 c ics680g-01lf 680g-01lf tubes 24-pin tssop 0 to +70 c ics680g-01lft 680g-01lf tape and reel 24-pin tssop 0 to +70 c index area 1 2 24 d e1 e seating plane a1 a a2 e - c - b .10 (.004) c c l millimeters inches symbol min max min max a ? 1.20 ? .047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 7.70 7.90 0.303 0.311 e 6.40 basic 0.252 basic e1 4.30 4.50 0.169 0.177 e 0.65 basic 0.0256 basic l 0.450.75.018.030 0 8 0 8
networking clock synthesizer and zero delay buffer mds 680-01 f 8 revision 020305 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics680-01 revision history rev. originator date description of change d p.griffith 10/01/04 removed power supply ramp-up time spec; added trinary input specs to dc chars; added a second output low voltage spec; updated su pply current specs from 50 to 32 ma, and 50 to 300 ua; changed pull-down resistor value from 525 to 250 kohms; changed output rise/fall times from 1 to 1.5 ns e p.griffith 12/21/04 released as stand ard product from custom device. f j. sarma 02/03/05 add lf ordering info.
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