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S3C72I9/p72i9 product overview 1- 1 1 product overview overview the S3C72I9 single-chip cmos microcontroller has been designed for high performance using samsung's newest 4 -bit cpu core, sam47 (samsung arrangeable microcontrollers). with an up-to-896-dot lcd direct drive capability, 8-bit timer/counter 0, 16-bit timer/counter 1 , and serial i/o, the S3C72I9 offers an excellent design solution for a wide variety of applications which require lcd func tions. up to 39 pins of the 100-pin qfp package can be dedicated to i/o. eight vectored interrupts provide fast response to internal and external events. in addi tion, the S3C72I9 's advanced cmos technology pro vides for low power consumption and a wide oper at ing voltage range. otp the S3C72I9 microcontroller is also available in otp (one time programmable) version, s3p72i9. s3p72i9 microcontroller has an on-chip 32 k-byte one-time-programable eprom instead of masked rom. the s3p72i9 is comparable to S3C72I9, both in function and in pin configuration.
product overview S3C72I9/p72i9 1- 2 features summary memory ? 8,192 4-bit ram (excluding lcd display ram) ? 32 , 768 8-bit rom 39 i/o pins ? i/o: 35 pins ? input only: 4 pins lcd controller/driver ? 56 segments and 16 common terminals ? 8 and 16 common selectable ? internal resistor circuit for lcd bias ? all dot can be switched on/off 8-bit basic timer ? 4 interval timer functions ? watchdog timer 8-bit timer/counter 0 ? programmable 8-bit timer ? external event counter ? arbitrary clock frequency output ? external clock signal divider ? serial i/o interface clock generator 16-bit timer/counter 1 ? programmable 16-bit timer ? external event counter ? arbitrary clock frequency output ? ext ernal clock signal divider 8-bit serial i/o interface ? 8-bit transmit/receive mode ? 8-bit receive mode ? lsb-first or msb-first transmission selectable ? internal or external clock source memory-mapped i/o structure ? data memory bank 15 watch timer ? time interval generation: 0.5 s, 3.9 ms at 32 . 768 hz ? 4 frequency outputs to buz pin ? clock source generation for lcd interrupts ? four internal vectored interrupts ? four external vectored interrupts ? two quasi-interrupts bit sequential carrier ? suppor ts 16-bit serial data transfer in arbitrary format power-down modes ? idle mode (only cpu clock stops) ? stop mode (main system clock and cpu clock stop ) ? sub-system clock stop mode oscillation sources ? crystal, ceramic, or rc for main system clock ? crystal oscillator for subsystem clock ? main system clock frequency: 0.4 - 6 mhz ? subsystem clock frequency: 32.768 khz ? cpu clock divider circuit (by 4, 8, or 64) instruction execution times ? 0.67, 1.33, 10.7 s at 6 mhz ? 0.95, 1.91, 15.3 s at 4.19 mhz ? 122 s at 32.768 khz operating temperature ? - 40 c to 85 c operating voltage range ? 1.8 v to 5.5 v (3.0 mhz @ 1.8 v) package type ? 100-pin qfp
S3C72I9/p72i9 product overview 1- 3 block diagram vlc1-vlc5 com0-com7 p4.0-p5.3/ com8-com15 seg0-seg39 p9.3-p6.0/ seg40-seg55 lcd driver/ controller program status word stack pointer arithmetic and logic unit instruction internal interrupts reset p8.0-p8.3 seg47-seg44 i/o port 8 i/o port 9 p9.0-p9.3 seg43-seg40 8-bit timer/ counter 0 interrupt control block instruction register clock 16-bit timer/ counter 1 32 k byte program memory 8192 x 4-bit data memory serial i/o i/o port 0 p0.0/ sck /ko p0.1/so/k1 p0.2/si/k2 p0.3/buz/k3 p6.0-p6.3 seg55-seg52 ks4-ks7 p7.0-p7.3 seg51-seg48 i/o port 7 i/o port 6 p5.0-p5.3/ com12-com15 p4.0-p4.3/ com8-com11 i/o port 5 i/o port 4 i/o port 3 p3.0/tclo0 p3.1/tclo1 p3.2/tcl0 p3.3/tcl1 i/o port 2 p2.0/clo p2.1/lcdck p2.2/lcdsy input port 1 p1.0-p1.3/ int0-int4 xt out x out xt in x in basic timer watch timer figure 1 -1 . S3C72I9 simplified block diagram
product overview S3C72I9/p72i9 1- 4 pin assignments seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 p3.1/tclo1 p3.2/tcl0 p3.3/tcl1 com0 com1 com2 com3 com4 com5 com6 com7 p4.0/com8 p4.1/com9 p4.2/com10 p4.3/com11 p5.0/com12 p5.1/com13 p5.2/com14 p5.3/com15 p6.0/seg55/k4 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 p9.3/seg40 p9.2/seg41 p9.1/seg42 p9.0/seg43 p8.3/seg44 p8.2/seg45 p8.1/seg46 p8.0/seg47 p7.3/seg48 p7.2/seg49 p7.1/seg50 p7.0/seg51 p6.3/seg52/k7 p6.2/seg53/k6 p6.1/seg54/k5 seg4 seg3 seg2 seg1 seg0 v lc5 v lc4 v lc3 v lc2 v lc1 p0.0/ sck /k0 p0.1/so/k1 p0.2/si/k2 p0.3/buz/k3 v dd v ss x out x in test xt in xt out reset p1.0/int0 p1.1/int1 p1.2/int2 p1.3/int4 p2.0/clo p2.1/lcdck p2.2/lcdsy p3.0/tclo0 S3C72I9 (100-qfp-1420c) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 figure 1 -2 . S3C72I9 100-qfp pin assignment diagram
S3C72I9/p72i9 product overview 1- 5 pin descriptions table 1- 1 . S3C72I9 pin descriptions pin name pin type description number share pin p0.0 p0.1 p0.2 p0.3 i/o 4-bit i/o port. 1-bit and 4-bit read/write and test are possible. individual pins are software configurable as input or output. individual pins are software configurable as open- drain or push-pull output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. 11 12 13 14 sck /k0 so/k1 si/k2 buz/k3 p1.0 p1.1 p1.2 p1.3 i 4-bit input port. 1-bit and 4-bit read and test are possible. 4 -bit pull-up resistors are assignable by software . 23 24 25 26 int0 int1 int2 int4 p2.0 p2.1 p2.2 i/o same as port 0 except that port 2 is 3-bit i/o port. 27 28 29 clo lcdck lcdsy p3.0 p3.1 p3.2 p3.3 i/o same as port 0 . 30 31 32 33 tclo0 tclo1 tcl0 tcl1 p4.0 - p4.3 p5.0 - p5.3 i/o 4-bit i/o ports. 1-, 4-bit or 8-bit read/write and test are possible. individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. 42-45 46-49 com8 - com11 com12 - com15 p6.0 - p6.3 p7.0 - p7.3 i/o same as p4, p5. 50-53 54-57 seg55/k4 - seg52/k7 seg5 1- seg48 p8.0 - p8.3 p9.0 - p9.3 i/o same as p4, p5. 58-61 62-65 seg47 - seg44 seg43 - seg40 sck i/o serial i/o interface clock signal . 11 p0.0/k0 so i/o serial data output . 12 p0.1/k1 si i/o serial data input . 13 p0.2/k2 buz i/o 2 khz, 4 khz, 8 khz or 16 khz frequency output for buzzer signal. 14 p0.3/k3 int0, int1 i external interrupts. the triggering edge for int0 and int1 is selectable. 23, 24 p1.0, p1.1
product overview S3C72I9/p72i9 1- 6 table 1- 1. S3C72I9 pin descriptions (continued) pin name pin type description number share pin int2 i quasi-interrupt with detection of rising or falling edges . 25 p1.2 int4 i external interrupt with detection of rising or falling edges . 26 p1.3 clo i/o clock output . 27 p2.0 lcdck i/o lcd clock output for display expansion . 28 p2.1 lcdsy i/o lcd synchronization clock output for display expansion . 29 p2.2 tclo0 i/o timer/counter 0 clock output . 30 p3.0 tclo1 i/o timer/counter 1 clock output . 31 p3.1 tcl0 i/o external clock input for timer/counter 0 . 32 p3.2 tcl1 i/o external clock input for timer/counter 1 . 33 p3.3 com0 - com7 o lcd common signal output . 34-41 ? com8 - com11 i/o 42 -45 p4.0 - p4.3 com12 - com15 46-49 p5.0 - p5.3 seg0 - seg39 o lcd segment signal output . 5-1, 100-66 ? seg40 - seg43 i/o 65-62 p9.3 - p9.0 seg44 - seg47 61-58 p8.3 - p8.0 seg48 - seg51 57-54 p7.3 - p7.0 seg52 - seg55 53-50 p6.3/k7 - p6.0/k4 k0 - k3 i/o external interrupt. the triggering edge is selectable. 11-14 p0.0 - p0.3 k4 - k7 50-53 p6.0 - p6.3 v dd ? main power supply . 15 ? v ss ? ground . 16 ? reset i reset signal . 22 ? v lc 1- v lc5 ? lcd power supply . 10-6 ? x in, x out ? crystal, c eramic or rc oscillator pins for system clock. 18, 17 ? xt in, xt out ? crystal oscillator pins for subsystem clock. 20, 21 ? test i test signal input . (must be connected to v ss ) 19 ? note: pull-up resistors for all i/o ports are automatically disabled if they are configured to output mode.
S3C72I9/p72i9 product overview 1- 7 table 1- 2 . overview of S3C72I9 pin data pin names share pins i/o type reset value circuit type p0. 1, p0.3 so/k1, buz/k3 i/o input e-1 p0. 0, p0.2 sck /k0, si/k2 i/o input e-2 p1.0 - p1. 3 int0 - int2 , int4 i input a- 3 p2.0 - p2.2 clo, lcdck, lcdsy i/o input e p3.0 - p3.1 tclo0, tclo1 i/o input e p3.2 - p3.3 tcl0, tcl1 i/o input e-1 p4.0 - p4.3 p5.0 - p5.3 com8 - com11 com12 - com15 i/o input h-13 p6.0 - p6.3 seg55/k4 - seg52/k7 i/o input h-16 p7.0 - p7.3 seg5 1- seg48 i/o input h-13 p8.0 - p8.3 p9.0 - p9.3 seg47 - seg44 seg43 - seg40 i/o input h-13 com0 - com7 ? o high h-3 seg0 - seg39 ? o high h-15 v dd ? ? ? ? v ss ? ? ? ? reset ? i ? b v lc 1 - v lc5 ? ? ? ? x in , x out ? ? ? ? xt in , xt out ? ? ? ? test ? i ? ?
product overview S3C72I9/p72i9 1- 8 pin circuit diagrams p-channel n-channel in v dd figure 1 -3 . pin circuit type a schmitt trigger pull-up resistor v dd pull-up resistor enable in p-channel figure 1 -4 . pin circuit type a- 3 schmitt trigger in v dd pull-up resistor figure 1 -5 . pin circuit type b p-channel n-channel v dd out output disable data figure 1 -6 . pin circuit type c
S3C72I9/p72i9 product overview 1- 9 n-ch v dd pull-up resistor enable v dd i/o pne pull-up resistor p-ch output disable data figure 1 -7 . pin circuit type e schmitt trigger n-ch v dd pull-up resistor enable v dd i/o pne pull-up resistor p-ch output disable data figure 1 -8 . pin circuit type e-1
product overview S3C72I9/p72i9 1- 10 n-ch v dd pull-up resistor enable v dd i/o pne pull-up resistor p-ch output disable data schmitt trigger figure 1 -9 . pin circuit type e-2
S3C72I9/p72i9 product overview 1- 11 out v dd v lc1 com v lc5 v lc4 figure 1 -10 . pin circuit type h-3 out v dd v lc2 seg v lc5 v lc3 figure 1 - 1 1 . pin circuit type h-15
product overview S3C72I9/p72i9 1- 12 com/seg output disable type h-3 i/o data type c v dd p-ch pull-up resistor pull-up resistor enable figure 1 - 1 2 . pin circuit type h-13 seg output disable type h-15 i/o data schmitt trigger type c v dd p-ch pull-up resistor pull-up resistor enable figure 1 - 1 3 . pin circuit type h-16
S3C72I9/p72i9 address spaces 2- 1 2 address spaces program memory (rom) overview rom maps for S3C72I9 devices are mask programmable at the factory. in its standard configuration, the device's 32 , 768 8-bit program memory has three areas that are directly addressable by the program counter (pc): ? 16-byte area for vector addresses ? 96-byte instruction reference area ? 16-byte general-purpose area ? 32,640 -byte general-purpose area general- p urpose program memory two program memory areas are allocated for general-purpose use: one area is 16 bytes in size and the other is 32,640 bytes. vector addresses a 16-byte vector address area is used to store the vector addresses required to execute system resets and interrupts. start addresses for interrupt service routines are stored in this area, along with the values of the enable memory bank (emb) and enable register bank (erb) flags that are used to set their initial value for the corre sponding service routines. the 16-byte area can be used alternately as general-purpose rom. ref instructions locations 0020h - 007fh are used as a reference area (look-up table) for 1-byte ref instructions. the ref instruction reduces the byte size of instruction operands. ref can reference one 2 -byte instruction, two 1-byte instructions, and one 3 -byte instructions which are stored in the look-up table. unused look-up table addresses can be used as general-purpose rom. table 2 - 1. program memory address ranges rom area function address ranges area size (in bytes) vector address area 0000h - 000fh 16 general-purpose program memory 0010h - 001fh 16 ref instruction look-up table area 0020h - 007fh 96 general-purpose program memory 0080h -7 fffh 32 , 640
address spaces S3C72I9/p72i9 2- 2 general-purpose memory areas the 16-byte area at rom locations 0010h - 001fh and the 32,640 -byte area at rom locations 0080h -7 fffh are used as general-purpose program memory. unused locations in the vector address area and ref instruction look-up table areas can be used as general-purpose program memory. however, care must be taken not to overwrite live data when writing programs that use special-purpose areas of the rom. vector address area the 16-byte vector address area of the rom is used to store the vector addresses for executing system resets and interrupts. the starting addresses of interrupt service routines are stored in this area, along with the enable memory bank (emb) and enable register bank (erb) flag values that are needed to initialize the service routines. 16-byte vector addresses are organized as follows: emb erb pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 to set up the vector address area for specific programs, use the instruction ventn. the programming tips on the next page explain how to do this. vector address area (16 bytes) general purpose area (16 bytes) instruction reference area (96 bytes) general purpose area (32,640 bytes) 0000h 001fh 0020h 007fh 0080h 7fffh 000fh 0010h figure 2 - 1. rom address structure 0000h reset intb/int4 int0 int1 ints intt0 intt1 intk 7 6 5 4 3 2 1 0 0002h 0004h 0006h 0008h 000ah 000ch 000eh figure 2 - 2. vector address map
S3C72I9/p72i9 address spaces 2- 3 + + p rogramming tip ? defining vectored interrupts the following examples show you several ways you can define the vectored interrupt and instruction reference areas in program memory: 1. when all vector interrupts are used: org 0000h ; vent0 1,0, reset ; emb ? 1, erb ? 0; jump to reset address by reset vent1 0,0,intb ; emb ? 0, erb ? 0; jump to intb address by intb vent2 0,0,int0 ; emb ? 0, erb ? 0; jump to int0 address by int0 vent3 0,0,int1 ; emb ? 0, erb ? 0; jump to int1 address by int1 vent4 0,0,ints ; emb ? 0, erb ? 0; jump to ints address by ints vent5 0,0,intt0 ; emb ? 0, erb ? 0; jump to intt0 address by intt0 vent6 0,0,intt1 ; emb ? 0, erb ? 0; jump to intt1 address by intt1 vent7 0,0,intk ; emb ? 0, erb ? 0; jump to intk address by intk 2. when a specific vectored interrupt such as int0, and intt0 is not used, the unused vector interrupt locations must be skipped with the assembly instruction org so that jumps will address the correct locations: org 0000h ; vent0 1,0, reset ; emb ? 1, erb ? 0; jump to reset address by reset vent1 0,0,intb ; emb ? 0, erb ? 0; jump to intb address by intb org 0006h ; int 0 interrupt not used vent3 0,0,int1 ; emb ? 0, erb ? 0; jump to int1 address by int1 vent4 0,0,ints ; emb ? 0, erb ? 0; jump to ints address by ints ; org 000ch ; intt0 interrupt not used ; vent6 0,0,intt1 ; emb ? 0, erb ? 0; jump to intt1 address by intt1 vent7 0,0,intk ; emb ? 0, erb ? 0; jump to intk address by intk ; org 0010h
address spaces S3C72I9/p72i9 2- 4 + + p rogramming tip ? defining vectored interrupts (continued) 3. if an int0 interrupt is not used and if its corresponding vector interrupt area is not f ully utilized, or if it is not written by a org instruction as in example 2, a cpu malfunction will occur: org 0000h ; vent0 1,0, reset ; emb ? 1, erb ? 0; jump to reset address by reset vent1 0,0,intb ; emb ? 0, erb ? 0; jump to intb address by intb vent3 0,0,int1 ; emb ? 0, erb ? 0; jump to int 1 address by int0 vent4 0,0,ints ; emb ? 0, erb ? 0; jump to int s address by int1 vent5 0,0,intt0 ; emb ? 0, erb ? 0; jump to int t0 address by ints vent6 0,0,intt1 ; emb ? 0, erb ? 0; jump to intt 1 address by intt0 vent7 0,0,intk ; emb ? 0, erb ? 0; jump to int k address by intt1 ; org 0010h ; general-purpose rom area ; in this example, when an ints interrupt is generated, the corresponding vector area is not vent4 ints, but vent5 intt0. this causes an ints interrupt to jump incorrectly to the intt0 address and causes a cpu malfunction to occur.
S3C72I9/p72i9 address spaces 2- 5 instruction reference area using 1-byte ref instructions, you can easily reference instructions with larger byte sizes that are stored in ad - dresses 0020h - 007fh of program memory. this 96-byte area is called the ref instruction reference area, or look-up table. locations in the ref look-up table may contain two 1 -byte instructions, one 2 -byte instruc tion, or one 3-byte instruction such as a jp (jump) or call. the starting address of the instruction you are referenc ing must always be an even number. to reference a jp or call instruction, it must be written to the reference area in a two-byte format: for jp, this format is tjp; for call, it is tcall. in summary, there are three ways to the ref instruction: by using ref instructions you can execute instructions larger than one byte . in summary, there are three ways you can use the ref instruction: ? using the 1-byte ref instruction to execute one 2-byte or two 1-byte instructions, ? branching to any location by referencing a branch instruction stored in the look-up table, ? calling subroutines at any location by referencing a call instruction stored in the look-up table. + + programming tip ? using the ref look-up table here is one example of how to use the ref instruction look-up table: org 0020h ; jmain tjp main ; 0, main keyck btsf keyfg ; 1, keyfg check watch tcall clock ; 2, call clock inchl ld @hl,a ; 3, (hl) ? a incs hl ? ? ? abc ld ea,#00h ; 47, ea ? #00h org 0080 ; main nop nop ? ? ? ref keyck ; btsf keyfg (1-byte instruction) ref jmain ; keyfg = 1, jump to main ( 1-byte instruction) ref watch ; keyfg = 0, call clock (1-byte instruction) ref inchl ; ld @hl,a ; incs hl ref abc ; ld ea,#00h (1-byte instruction) ? ? ?
address spaces S3C72I9/p72i9 2- 6 data memory (ram) overview in its standard configuration, the 8,448 4 -bit data memory has five areas: ? 32 4-bit working register area in bank 0 ? 224 4 -bit general-purpose area in bank 0 which is also used as the stack area ? 31 pages (00h?1eh pages) with 256 4-bit general-purpose area in bank 1 ? 32 4 -bit general-purpose area in bank 2 ? 224 4 -bit area for lcd data in bank 2 ? 128 4-bit area in bank 15 for memory-mapped i/o addresses to make it easier to reference, the data memory area has four memory banks ? bank 0, bank 1, bank 2 and bank 15. the select memory bank instruction (smb) and the page selection register (pasr) are used to select the bank and page you want to select as working data memory. data stored in ram locations are 1-, 4-, and 8-bit addressable. initialization values for the data memory area are not defined by hardware and must therefore be initialized by program software following power reset . however, when reset signal is generated in power-down mode, the most of data memory contents are held. bank 1 page selection register (pasr) pasr is a 5-bit write-only register for selecting the page of bank 1, and is mapped to the ram address fd2h. it should be written by a 8-bit ram control instruction only and the msb 3 bits should be ?0?. pasr retains the previous value as long as change is not required, and the reset value is 0. therefore, when it returns to the bank 1 from other bank (bank 0 or bank 15) without changing the contents of pasr, the previously specified bank 1 page is selected. the pasr must not be changed in the interrupt service routine because it?s value cannot be recovered as the original value when the routine is finished.
S3C72I9/p72i9 address spaces 2- 7 100h page (1eh) 1ffh 100h page (1dh) 1ffh 100h page (1ch) 1ffh 100h page (1bh) 1ffh 100h 1ffh 100h page (07h) 1ffh 100h page (06h) 1ffh 100h page (05h) 1ffh 100h page (04h) 1ffh 100h page (03h) 1ffh 100h page (02h) 1ffh 100h page (01h) 1ffh 000h 1ffh bank 1 (emb=1,smb=1) 020h 0ffh 100h 3 2 1 0 general- purpose registers page (00h) general- purpose and stack registers working registers 200h 201h 202h 203h 204h 205h 206h 207h 208h 209h 2f6h 2f7h 2f8h 2f9h 2fah 2fbh 2fch 2fdh 2feh 2ffh lcd display data registers and general-purpose registers bank 2 (emb=1, smb=2) f80h fffh peripheral hardware register bank15 (emb=0 or emb=1, smb=15) bank 0 (emb=0 or emb = 1, smb=0) figure 2 - 3. data memory (ram) map
address spaces S3C72I9/p72i9 2- 8 memory banks 0, 1, 2, and 15 bank 0 (000h - 0ffh) the lowest 32 nibbles of bank 0 (000h - 01fh) are used as working registers; the next 224 nibbles (020h - 0ffh) can be used both as stack area and as general-purpose data memory. use the stack area for implementing subroutine calls and returns, and for interrupt processing. bank 1 (100h - 1ffh) bank 1 has the data memory of 31 pages, the 31 pages for general-purpose data memory are comprised of 256 4-bits, respectively. the S3C72I9 uses specially the page selection register (pasr) for selecting one of these 31 pages in bank 1. bank 2 (200h - 2f f h) the 224 nibbles of bank 2 are for display registers or general-purpose use; locations 2xe and 2xf (x = 0 - f) are for general-purpose use in bank 2. detailed map on bank 2 is shown in section 12 lcd controller/driver. bank 15 (f80h - fffh) the microcontroller uses bank 15 for memory-mapped peripheral i/o. fixed ram locations for each peripheral hardware address are mapped into this area. data memory addressing modes the enable memory bank (emb) flag controls the addressing mode for data memory banks 0, 1, 2, or 15. when the emb flag is logic zero, the addressable area is restricted to specific locations, depending on whether direct or indirect addressing is used. with direct addressing, you can access locations 000h - 07fh of bank 0 and bank 15. with indirect addressing, only bank 0 (000h - 0ffh) can be accessed. when the emb flag is set to logic one, all four data memory banks can be accessed according to the current smb value. for 8-bit addressing, two 4-bit registers are addressed as a register pair. also, when using 8-bit instructions to address ram locations, remember to use the even-numbered register address as the instruction operand. working registers the ram working register area in data memory bank 0 is further divided into four register banks (bank 0, 1, 2, and 3). each register bank has eight 4-bit registers and paired 4-bit registers are 8-bit addressable. register a is used as a 4-bit accumulator and register pair ea as an 8-bit extended accumulator. the carry flag bit can also be used as a 1-bit accumulator. register pairs wx, wl, and hl are used as address pointers for indirect addressing. to limit the possibility of data corruption due to incorrect register addressing, it is advisable to use register bank 0 for the main program and banks 1, 2, and 3 for interrupt service routines. lcd data register area bit values for lcd segment data are stored in data memory bank 2. register locations in this area that are not used to store lcd data can be assigned to general-purpose use.
S3C72I9/p72i9 address spaces 2- 9 table 2 - 2. data memory organization and addressing addresses register areas bank emb value smb value 000h - 01fh working registers 0 0, 1 0 020h - 0ffh stack and general-purpose registers 100h - 1ffh general-purpose registers (31 pages) 1 1 1 200h - 2f f h display registers and general-purpose registers 2 1 2 f80h - fffh i/o-mapped hardware registers 15 0, 1 15 + + programming tip ? clearing data memory bank 0 and p age 00h in bank 1 clear the bank 0 and the page 00h in bank 1 of the data memory area : ramclr smb 0 ; ram ( 0 10h -0 ffh) clear in bank 0 ld hl,#10h ld a,#0h rmcl0 ld @hl,a incs hl jr rmcl 0 ; smb 15 ld ea, #00h ld pasr, ea ; smb 1 ; ram (1 0 0h -1 ffh) clear page 00h in bank 1 ld hl,#00h rmcl1 ld @hl,a incs hl jr rmcl 1
address spaces S3C72I9/p72i9 2- 10 working registers working registers, mapped to ram address 000h-01fh in data memory bank 0, are used to temporarily store intermediate results during program execution, as well as pointer values used for indirect addressing. unused registers may be used as general-purpose memory. working register data can be manipulated as 1-bit units, 4-bit units or, using paired registers, as 8-bit units. a e l h x w z y a ...y a ...y a ...y 000h 001h 002h 003h 004h 005h 006h 007h 008h 00fh 010h 017h 018h 01fh register bank 1 register bank 2 register bank 3 working register bank 0 data memory bank 0 figure 2 - 4. working register map
S3C72I9/p72i9 address spaces 2- 11 working register banks for addressing purposes, the working register area is divided into four register banks ? bank 0, bank 1, bank 2, and bank 3. any one of these banks can be selected as the working register bank by the register bank selection instruction (srb n) and by setting the status of the register bank enable flag (erb). generally, working register bank 0 is used for the main program, and banks 1, 2, and 3 for interrupt service rou - tines. following this convention helps to prevent possible data corruption during program execution due to con - tention in register bank addressing. table 2 - 3. working register organization and addressing erb setting srb settings selected register bank 3 2 1 0 0 0 0 x x always set to bank 0 1 0 0 0 0 bank 0 0 1 bank 1 1 0 bank 2 1 1 bank 3 note : 'x' means don't care. paired working registers each of the register banks is subdivided into eight 4-bit registers. these registers, named y, z, w, x, h, l, e and a, can either be manipulated individually using 4-bit instructions, or together as register pairs for 8-bit data manipulation. the names of the 8-bit register pairs in each register bank are ea, hl, wx, yz and wl. registers a, l, x and z always become the lower nibble when registers are addressed as 8-bit pairs. this makes a total of eight 4-bit registers or four 8-bit double registers in each of the four working register banks. (msb) (lsb) (msb) (lsb) y w h e z x l a figure 2 - 5. register pair configuration
address spaces S3C72I9/p72i9 2- 12 special-purpose working registers register a is used as a 4-bit accumulator and double register ea as an 8-bit accumulator. the carry flag can also be used as a 1-bit accumulator. 8-bit double registers wx, wl and hl are used as data pointers for indirect addressing. when the hl register serves as a data pointer, the instructions ldi, ldd, xchi, and xchd can make very efficient use of working registers as program loop counters by letting you transfer a value to the l register and increment or decrement it using a single instruction. c a ea 1-bit accumulator 4-bit accumulator 8-bit accumulator figure 2 - 6. 1-bit, 4-bit, and 8-bit accumulator recommendation for multiple interrupt processing if more than four interrupts are being processed at one time, you can avoid possible loss of working register data by using the push rr instruction to save register contents to the stack before the service routines are exe cuted in the same register bank. when the routines have executed successfully, you can restore the register con tents from the stack to working memory using the pop instruction.
S3C72I9/p72i9 address spaces 2- 13 + + programming tip ? selecting the working register area the following examples show the correct programming method for selecting working register area: 1. when erb = "0": vent2 1,0,int0 ; emb ? 1, erb ? 0, jump to int0 address ; int0 push sb ; push current smb, srb srb 2 ; instruction does not execute because erb = "0" push hl ; push hl register contents to stack push wx ; push wx r egister contents to stack push yz ; push yz register contents to stack push ea ; push ea register contents to stack smb 0 ld ea,#00h ld 80h,ea ld hl,#40h incs hl ld wx,ea ld yz,ea pop ea ; pop ea register contents from stack pop yz ; pop yz register contents from stack pop wx ; pop wx register contents from stack pop hl ; pop hl register contents from stack pop sb ; pop current smb, srb iret the pop instructions execute alternately with the push instructions. if an smb n instruction is used in an interrupt service routine, a push and pop sb instruction must be used to store and restore the current smb and srb values, as shown in example 2 below. 2. when erb = "1": vent2 1,1,int0 ; emb ? 1, erb ? 1, jump to int0 address ; int0 push sb ; store current smb, srb srb 2 ; select register bank 2 because of erb = "1" smb 0 ld ea,#00h ld 80h,ea ld hl,#40h incs hl ld wx,ea ld yz,ea pop sb ; restore smb, srb iret
address spaces S3C72I9/p72i9 2- 14 stack operations stack pointer (sp) the stack pointer (sp) is an 8-bit register that stores the address used to access the stack, an area of data memory set aside for temporary storage of data and addresses. the sp can be read or written by 8 -bit control instruc tions. when addressing the sp, bit 0 must always remain cleared to logic zero. f80h sp3 sp2 sp1 "0" f81h sp7 sp6 sp5 sp4 there are two basic stack operations: writing to the top of the stack (push), and reading from the top of the stack (pop). a push decrements the sp and a pop increments it so that the sp always points to the top address of the last data to be written to the stack. the program counter contents and program status word are stored in the stack area prior to the execution of a call or a push instruction, or during interrupt service routines. stack operation is a lifo (last in-first out) type. the stack area is located in general-purpose data memory bank 0. during an interrupt or a subroutine, the pc value and the psw are saved to the stack area. when the routine has completed, the stack pointer is referenced to restore the pc and psw, and the next in struction is executed. the sp can address stack registers in bank 0 (addresses 000h-0ffh) regardless of the current value of the en - able memory bank (emb) flag and the select memory bank (smb) flag. although general-purpose register areas can be used for stack operations, be careful to avoid data loss due to simultaneous use of the same register(s). since the reset value of the stack pointer is not defined in firmware, we recommend that you initialize the stack pointer by program code to location 00h. this sets the first register of the stack area to 0ffh. note a subroutine call occupies six nibbles in the stack; an interrupt requires six. when subroutine nesting or interrupt routines are used continuously, the stack area should be set in accordance with the maximum number of subroutine levels. to do this, estimate the number of nibbles that will be used for the subroutines or interrupts and set the stack area correspondingly. + + p rogramming tip ? initializing the stack pointer to initialize the stack pointer (sp): 1. when emb = "1": smb 15 ; select memory bank 15 ld ea,#00h ; bit 0 of sp is always cleared to "0" ld sp,ea ; stack area initial address (0ffh) ? (sp) - 1 2. when emb = "0": ld ea,#00h ld sp,ea ; memory addressing area (00h - 7fh, f80h - fffh)
S3C72I9/p72i9 address spaces 2- 15 push operations three kinds of push operations reference the stack pointer (sp) to write data from the source register to the stack: push instructions, call instructions, and interrupts. in each case, the sp is decremented by a number determined by the type of push operation and then points to the next available stack location. push instructions a push instruction references the sp to write two 4-bit data nibbles to the stack. two 4-bit stack addresses are referenced by the stack pointer: one for the upper register value and another for the lower register. after the push has executed, the sp is decremented by two and points to the next available stack location. call instructions when a subroutine call is issued, the call instruction references the sp to write the pc's contents to six 4 -bit stack locations. current values for the enable memory bank (emb) flag and the enable register bank (erb) flag are also pushed to the stack. since six 4-bit stack locations are used per call, you may nest subroutine calls up to the number of levels permitted in the stack. interrupt routines an interrupt routine references the sp to push the contents of the pc and the program status word (psw) to the stack. six 4-bit stack locations are used to store this data. after the interrupt has executed, the sp is decremented by six and points to the next available stack location. during an interrupt sequence, subroutines may be nested up to the number of levels which are permitted in the stack area. lower register upper register sp - 2 sp - 1 sp push (after push, sp sp - 2) sp - 1 sp pc11 - pc8 pc14 - pc12 0 pc3 - pc0 pc7 - pc4 0 0 emb erb 0 0 0 0 sp - 2 sp - 3 sp - 4 sp - 5 sp - 6 psw sp - 1 sp interrupt (when int is acknowledged sp sp - 6) pc11 - pc8 pc14 - pc12 0 pc3 - pc0 pc7 - pc4 is1 is0 emb erb c sp - 2 sp - 3 sp - 4 sp - 5 sp - 6 psw sc2 sc1 sc0 call, lcall (after call or lcall, sp sp - 6) figure 2 - 7. push-type stack operations
address spaces S3C72I9/p72i9 2- 16 pop operations for each push operation there is a corresponding pop operation to write data from the stack back to the source register or registers: for the push instruction it is the pop instruction; for call, the instruction ret or sret; for interrupts, the instruction iret. when a pop operation occurs, the sp is incremented by a number determined by the type of operation and points to the next free stack location. pop instructions a pop instruction references the sp to write data stored in two 4-bit stack locations back to the register pairs and sb register. the value of the lower 4-bit register is popped first, followed by the value of the upper 4-bit register. after the pop has executed, the sp is incremented by two and points to the next free stack location. ret and sret instructions the end of a subroutine call is signaled by the return instruction, ret or sret. the ret or sret uses the sp to reference the six 4-bit stack locations used for the call and to write this data back to the pc, the emb, and the erb. after the ret or sret has executed, the sp is incremented by six and points to the next free stack location. iret instructions the end of an interrupt sequence is signaled by the instruction iret. iret references the sp to locate the six 4-bit stack addresses used for the interrupt and to write this data back to the pc and the psw. after the iret has executed, the sp is incremented by six and points to the next free stack location. sp pc11 - pc8 pc14 - pc12 0 pc3 - pc0 pc7 - pc4 0 0 emb erb 0 0 0 0 psw pc11 - pc8 pc14 - pc12 0 pc3 - pc0 pc7 - pc4 is1 is0 emb erb c psw sc2 sc1 sc0 iret (sp sp + 6) ret or sret (sp sp + 6) pop (sp sp + 2) sp + 1 sp + 1 lower register upper register sp + 5 sp + 6 sp + 4 sp + 3 sp + 2 sp + 1 sp sp + 5 sp + 6 sp + 4 sp + 3 sp + 2 sp + 1 sp figure 2 - 8. pop-type stack operations
S3C72I9/p72i9 address spaces 2- 17 bit sequential carrier (bsc) the bit sequential carrier (bsc) is a 16-bit general register that can be manipulated using 1-, 4-, and 8-bit ram control instructions. reset clears all bsc bit values to logic zero. using the bsc, you can specify sequential addresses and bit locations using 1-bit indirect addressing (memb.@l). (bit addressing is independent of the current emb value.) in this way, programs can process 16-bit data by moving the bit location sequentially and then incrementing or decrementi ng the value of the l register. bsc data can also be manipulated using direct addressing. for 8-bit manipulations, the 4-bit register names bsc0 and bsc2 must be specified and the upper and lower 8 bits manipulated separately. if the values of the l register are 0h at bsc0.@l, the address and bit location assignment is fc0h.0. if the l register content is fh at bsc0.@l, the address and bit location assignment is fc3h.3. table 2 - 4. bsc register organization name address bit 3 bit 2 bit 1 bit 0 bsc0 fc0h bsc0.3 bsc0.2 bsc0.1 bsc0.0 bsc1 fc1h bsc1.3 bsc1.2 bsc1.1 bsc1.0 bsc2 fc2h bsc2.3 bsc2.2 bsc2.1 bsc2.0 bsc3 fc3h bsc3.3 bsc3.2 bsc3.1 bsc3.0 + + programming tip ? using the bsc register to output 16-bit data to use the bit sequential carrier (bsc) register to output 16-bit data (5937h) to the p3.0 pin: bits emb smb 15 ld ea,#37h ; ld bsc0,ea ; bsc0 ? a, bsc1 ? e ld ea,#59h ; ld bsc2,ea ; bsc2 ? a, bsc3 ? e smb 0 ld l,#0h ; agn ldb c,bsc0.@l ; ldb p3.0,c ; p3.0 ? c incs l jr agn ret
address spaces S3C72I9/p72i9 2- 18 program counter (pc) a 14-bit program counter (pc) stores addresses for instruction fetches during program execution. whenever a reset operation or an interrupt occurs, bits pc13 through pc0 are set to the vector address. usually, the pc is incremented by the number of bytes of the instruction being fetched. one exception is the 1-byte ref instruction which is used to reference instructions stored in the rom. program status word (psw) the program status word (psw) is an 8-bit word that defines system status and program execution status and which permits an interrupted process to resume operation after an inter rupt request has been serviced. psw values are mapped as follows: (msb) (lsb) fb0h is1 is0 emb erb fb1h c sc2 sc1 sc0 the psw can be manipulated by 1-bit or 4-bit read/write and by 8-bit read instructions, depending on the spe cific bit or bits being addressed. the psw can be addressed during program execution regardless of the current value of the enable memory bank (emb) flag. part or all of the psw is saved to stack prior to execution of a subroutine call or hardware interrupt. after the in - terrupt has been processed, the psw values are popped from the stack back to the psw address. when a reset is generated, the emb and erb values are set according to the reset vector address, and the carry flag is left undefined (or the current value is retained). psw bits is0, is1, sc0, sc1, and sc2 are all cleared to logical zero. table 2 - 5. program status word bit descriptions psw bit identifier description bit addressing read/write is1, is0 interrupt status flags 1, 4 r/w emb enable memory bank flag 1 r/w erb enable register bank flag 1 r/w c carry flag 1 r/w sc2, sc1, sc0 program skip flags 8 r
S3C72I9/p72i9 address spaces 2- 19 interrupt status flags (is0, is1) psw bits is0 and is1 contain the current interrupt execution status values. you can manipulate is0 and is1 flags directly using 1-bit ram control instructions . by manipulating interrupt status flags in conjunction with the interrupt priority register (ipr), you can process multiple interrupts by anticipating the next interrupt in an execution sequence. the interrupt priority control circuit determines the is0 and is1 settings in order to control multiple interrupt processing. when both interrupt status flags are set to "0", all interrupts are allowed. the priority with which interrupts are processed is then determined by the ipr. when an interrupt occurs, is0 and is1 are pushed to the stack as part of the psw and are automatically incremented to the next higher priority level. then, when the interrupt service routine ends with an iret instruction, is0 and is1 values are restored to the psw. table 2 - 6 shows the effects of is0 and is1 flag settings. table 2 - 6. interrupt status flag bit settings is1 value is0 value status of currently executing process effect of is0 and is1 settings on interrupt request control 0 0 0 all interrupt requests are serviced . 0 1 1 only high-priority interrupt(s) as determined in the interrupt priority register (ipr) are serviced . 1 0 2 no more interrupt requests are serviced . 1 1 ? not applicable; these bit settings are undefined . since interrupt status flags can be addressed by write instructions, programs can exert direct control over inter rupt processing status. before interrupt status flags can be addressed, however, you must first execute a di in struction to inhibit additional interrupt routines. when the bit manipulation has been completed, execute an ei instruction to re -enable interrupt processing. + + programming tip ? setting isx flags for interrupt processing the following instruction sequence shows how to use the is0 and is1 flags to control interrupt processing: intb di ; disable interrupt bitr is1 ; is1 ? 0 bits is0 ; allow interrupts according to ipr priority level ei ; enable interrupt
address spaces S3C72I9/p72i9 2- 20 emb flag (emb) the emb flag is used to allocate specific address locations in the ram by modifying the upper 4 bits of 12-bit data memory addresses. in this way, it controls the addressing mode for data memory banks 0, 1, 2, or 15. when the emb flag is "0", the data memory address space is restricted to bank 15 and addresses 000h - 07fh of memory bank 0, regardless of the smb register contents. when the emb flag is set to "1", the general-purpose areas of bank 0, 1, 2, and 15 can be accessed by using the appropriate smb value. if it is selected the general purpose area of bank 1 using smb 1, a page in bank 1 can be selected by means of the page selection register (pasr). + + programming tip ? using the emb flag to select memory banks emb flag settings for memory bank selection: 1. when emb = "0": smb 15 ld ea,#00h ld pasr,ea smb 1 ; non-essential instruction since emb = "0" ld a,#9h ld 90h,a ; (f90h) ? a, bank 15 is selected ld 34h,a ; (034h) ? a, bank 0 is selected smb 0 ; non-essential instruction since emb = "0" ld 90h,a ; (f90h) ? a, bank 15 is selected ld 34h,a ; (034h) ? a, bank 0 is selected smb 15 ; non-essential instruction, since emb = "0" ld 20h,a ; (020h) ? a, bank 0 is selected ld 90h,a ; (f90h) ? a, bank 15 is selected 2. when emb = "1": smb 15 ld ea,#00h ld pasr,ea smb 1 ; select memory bank 1 ld a,#9h ld 90h,a ; (190h) ? a, page 00h in bank 1 is selected ld 34h,a ; (134h) ? a, page 00h in bank 1 is selected smb 0 ; select memory bank 0 ld 90h,a ; (090h) ? a, bank 0 is selected ld 34h,a ; (034h) ? a, bank 0 is selected smb 15 ; select memory bank 15 ld 20h,a ; program error, but assembler does not detect it ld 90h,a ; (f90h) ? a, bank 15 is selected
S3C72I9/p72i9 address spaces 2- 21 erb flag (erb) the 1-bit register bank enable flag (erb) determines the range of addressable working register area. when the erb flag is "1", the working register area from register banks 0 to 3 is selected according to the register bank selection register (srb). when the erb flag is "0", register bank 0 is the selected working register area, regardless of the current value of the register bank selection register (srb). when an internal reset is generated, bit 6 of program memory address 0000h is written to the erb flag. this automatically initializes the flag. when a vectored interrupt is generated, bit 6 of the respective address table in program memory is written to the erb flag, setting the correct flag status before the interrupt service routine is executed. during the interrupt routine, the erb value is automatically pushed to the stack area along with the other psw bits. afterwards, it is popped back to the fb0h.0 bit location. the initial erb flag settings for each vectored interrupt are defined using ventn instructions. + + programming tip ? using the erb flag to select register banks erb flag settings for register bank selection: 1. when erb = "0": srb 1 ; register bank 0 is selected (since erb = "0", the srb is configured to bank 0) ld ea,#34h ; bank 0 ea ? #34h ld hl,ea ; bank 0 hl ? ea srb 2 ; register bank 0 is selected ld yz,ea ; bank 0 yz ? ea srb 3 ; register bank 0 is selected ld wx,ea ; bank 0 wx ? ea 2. when erb = "1": srb 1 ; register bank 1 is selected ld ea,#34h ; bank 1 ea ? #34h ld hl,ea ; bank 1 hl ? bank 1 ea srb 2 ; register bank 2 is selected ld yz,ea ; bank 2 yz ? bank2 ea srb 3 ; register bank 3 is selected ld wx,ea ; bank 3 wx ? bank 3 ea
address spaces S3C72I9/p72i9 2- 22 skip condition flags (sc2, sc1, sc0) the skip condition flags sc2, sc1, and sc0 in the psw indicate the current program skip conditions and are set and reset automatically during program execution. skip condition flags can only be addressed by 8-bit read instructions. direct manipulation of the sc2, sc1, and sc0 bits is not allowed. carry flag (c) the carry flag is used to save the result of an overflow or borrow when executing arithmetic instructions involving a carry (adc, sbc). the carry flag can also be used as a 1-bit accumulator for performing boolean operations involving bit-addressed data memory. if an overflow or borrow condition occurs when executing arithmetic instructions with carry (adc, sbc), the carry flag is set to "1". otherwise, its value is "0". when a reset occurs, the current value of the carry flag is retained during power-down mode, but when normal operating mode resumes, its value is undefined. the carry flag can be directly manipulated by predefined set of 1-bit read/write instructions, independent of other bits in the psw. only the adc and sbc instructions, and the instructions listed in table 2 - 7, affect the carry flag. table 2 - 7. valid carry flag manipulation instructions operation type instructions carry flag manipulation direct manipulation scf set carry flag to "1" . rcf clear carry flag to "0" (reset carry flag) . ccf invert carry flag value (complement carry flag) . btst c test carry and skip if c = "1" . bit transfer ldb (operand) (1) ,c load carry flag value to the specified bit . ldb c,(operand) (1) load contents of the specified bit to carry flag . boolean manipulation band c,(operand) (1) and the specified bit with contents of carry flag and save the result to the carry flag . bor c,(operand) (1) or the specified bit with contents of carry flag and save the result to the carry flag . bxor c,(operand) (1) xor the specified bit with contents of carry flag and save the result to the carry flag . interrupt routine intn (2) save carry flag to stack with other psw bits . return from interrupt iret restore carry flag from stack with other psw bits . notes : 1. the operand has three bit addressing formats: mema.a, memb.@l, and @h + da.b. 2. 'intn' refers to the specific interrupt being executed and is not an instruction.
S3C72I9/p72i9 address spaces 2- 23 + + programming tip ? using the carry flag as a 1-bit accumulator 1. set the carry flag to logic one: scf ; c ? 1 ld ea,#0c3h ; ea ? #0c3h ld hl,#0aah ; hl ? #0aah adc ea,hl ; ea ? #0c3h + #0aah + #1h, c ? 1 2. logical-and bit 3 of address 3fh with p3.3 and output the result to p5.0: ld h,#3h ; set the upper four bits of the address to the h register ; value ldb c,@h+0fh.3 ; c ? bit 3 of 3fh band c,p3.3 ; c ? c and p3.3 ldb p5.0,c ; output result from carry flag to p5.0
S3C72I9/p72i9 addressing modes 3 - 1 3 addressing modes overview the enable memory bank flag, emb, controls the two addressing modes for data memory. when the emb flag is set to logic one, you can address the entire ram area; when the emb flag is cleared to logic zero, the addressable area in the ram is restricted to specific locations. the emb flag works in connection with the select memory bank instruction, smbn. you will recall that the smbn instruction is used to select ram bank 0, 1, 2, or 15. the smb setting is always contained in the upper four bits of a 12-bit ram address. for this reason, both addressing modes (emb = "0" and emb = "1") apply specifically to the memory bank indicated by the smb instruction, and any restrictions to the addressable area within banks 0, 1, 2, or 15. direct and indirect 1-bit, 4-bit, and 8-bit addressing methods can be used. several ram locations are addressable at all times, regardless of the current emb flag setting. here are a few guidelines to keep in mind regarding data memory addressing: ? when you address peripheral hardware locations in bank 15, the mnemonic for the memory-mapped hardware component can be used as the operand in place of the actual address location. ? always use an even-numbered ram address as the operand in 8-bit direct and indirect addressing. ? with direct addressing, use the ram address as the instruction operand; with indirect addressing, the instruction specifies a register which contains the operand's address.
addressing modes S3C72I9/p72i9 3 - 2 notes: 1. 'x' means don't care. 2. blank columns indicate ram areas that are not addressable, given the addressing method and enable memory bank (emb) flag setting shown in the column headers. 3. the bank 1 has 31 pages (00h-1eh), and a page in bank 1 can be selected by means of the page selection register (pasr). addressing mode ram areas working registers da da.b @hl @h+da.b @wx @wl mema.b memb.@l emb = 0 emb = 1 emb = 0 emb = 1 x x x bank 0 (general registers and stack) bank 1 (3) (general registers) bank 2 (lcd display registers and general registers) bank 15 (peripheral hardware registers) 000h 01fh 020h 07fh 080h 0ffh 100h 1ffh 200h 2ffh f80h fffh smb = 0 smb = 0 smb = 1 smb = 1 smb = 2 smb = 2 smb = 15 smb = 15 ff0h fb0h fbfh fc0h figure 3 - 1. ram address structure
S3C72I9/p72i9 addressing modes 3 - 3 emb and erb initialization values the emb and erb flag bits are set automatically by the values of the reset vector address and the interrupt vector address. when a reset is generated internally, bit 7 of program memory address 0000h is written to the emb flag, initializing it automatically. when a vectored interrupt is generated, bit 7 of the respective vector address table is written to the emb. this automatically sets the emb flag status for the interrupt service routine. when the interrupt is serviced, the emb value is automatically saved to stack and then restored when the interrupt routine has completed. at the beginning of a program, the initial emb and erb flag values for each vectored interrupt must be set by using vent instruction. the emb and erb can be set or reset by bit manipulation instructions (bits, bitr) despite the current smb setting. + + programming tip ? initializing the emb and erb flags the following assembly instructions show how to initialize the emb and erb flag settings: org 0000h ; rom address assignment vent0 1,0, reset ; emb ? 1, erb ? 0 ; jump to reset address by reset vent1 0,1,intb ; emb ? 0, erb ? 1 ; jump to intb address by intb vent2 0,1,int0 ; emb ? 0, erb ? 1 ; jump to int0 address by int0 vent3 0,1,int1 ; emb ? 0, erb ? 1 ; jump to int1 address by int1 vent4 0,1,ints ; emb ? 0, erb ? 1 ; jump to ints address by ints vent5 0,1,intt0 ; emb ? 0, erb ? 1 ; jump to intt0 address by intt0 vent6 0,1,intt1 ; emb ? 0, erb ? 1 ; jump to intt1 address by intt1 vent7 0,1,intk ; emb ? 0, erb ? 1 ; jump to intk address by intk reset ? ? ? bitr emb
addressing modes S3C72I9/p72i9 3 - 4 enable memory bank settings emb = "1" when the enable memory bank flag emb is set to logic one, you can address the data memory bank specified by the select memory bank (smb) value (0, 1, 2, or 15) using 1-, 4-, or 8-bit instructions. you can use both direct and indirect addressing modes. the addressable ram areas when emb = "1" are as follows: if smb = 0, 000h - 0ffh (bank 0 is selected) if smb = 1, 1 00h - 1ffh (bank 1 is selected: bank 1 has the data memory of 31 pages (00h-1eh)) if smb = 2, 200h - 2ffh (bank 2 is selected) if smb = 15, f80h - fffh (bank 15 is selected) emb = "0" when the enable memory bank flag emb is set to logic zero, the addressable area is defined independently of the smb value, and is restricted to specific locations depending on whether a direct or indirect address mode is used. if emb = "0", the addressable area is restricted to locations 000h - 07fh in bank 0 and to locations f80h - fffh in bank 15 for direct addressing. for indirect addressing, only locations 000h - 0ffh in bank 0 are addressable, regardless of smb value. to address the peripheral hardware register (bank 15) using indirect addressing, the emb flag must first be set to "1" and the smb value to "15". when a reset occurs, the emb flag is set to the value contained in bit 7 of rom address 0000h. emb-independent addressing at any time, several areas of the data memory can be addressed independent of the current status of the emb flag. these exceptions are described in table 3 - 1. table 3 - 1. ram addressing not affected by the emb value address addressing method affected hardware program examples 000h - 0ffh 4-bit indirect addressing using wx and wl register pairs; 8-bit indirect addressing using sp not applicable ld a,@wx push pop fb0h - fbfh ff0h - fffh 1-bit direct addressing psw, scmod, iex, irqx, i/o bits emb bitr ie4 fc0h - fffh 1-bit indirect addressing using the l register bsc, i/o btst fc3h.@l band c,p3.@l
S3C72I9/p72i9 addressing modes 3 - 5 select bank register (sb) the select bank register (sb) is used to assign the memory bank and register bank. the 8-bit sb register con - sists of the 4-bit select register bank register (srb) and the 4-bit select memory bank register (smb), as shown in figure 3 - 2. during interrupts and subroutine calls, sb register contents can be saved to stack in 8-bit units by the push sb instruction. you later restore the value to the sb using the pop sb instruction. smb 3 sb register smb 2 smb 1 smb 0 0 0 srb 1 srb 0 smb (f83h) srb (f82h) figure 3 -2. smb and srb values in the sb register select register bank (srb) instruction the select register bank (srb) value specifies which register bank is to be used as a working register bank. the srb value is set by the 'srb n' instruction, where n = 0, 1, 2, 3. one of the four register banks is selected by the combination of erb flag status and the srb value that is set using the 'srb n' instruction. the current srb value is retained until another register is requested by program software. push sb and pop sb instructions are used to save and restore the contents of srb during interrupts and subroutine calls. reset clears the 4-bit srb value to logic zero. select memory bank (smb) instruction to select one of the four available data memory banks, you must execute an smb n instruction specifying the number of the memory bank you want (0, 1, 2, or 15). for example, the instruction 'smb 1' selects bank 1 and 'smb 15' selects bank 15. (and remember to enable the selected memory bank by making the appropriate emb flag setting ) . the upper four bits of the 12-bit data memory address are stored in the smb register. if the smb value is not specified by software (or if a reset does not occur) the current value is retained. reset clears the 4-bit smb value to logic zero. the push sb and pop sb instructions save and restore the contents of the smb register to and from the stack area during interrupts and subroutine calls.
addressing modes S3C72I9/p72i9 3 - 6 direct and indirect addressing 1-bit, 4-bit, and 8-bit data stored in data memory locations can be addressed directly using a specific register or bit address as the instruction operand. indirect addressing specifies a memory location that contains the required direct address. the s3c7 instruction set supports 1-bit, 4-bit, and 8 -bit indirect addressing. for 8-bit indirect addressing, an even-numbered ram address must always be used as the instruction operand. 1-bit addressing table 3 - 2. 1-bit direct and indirect ram addressing operand notation addressing mode description emb flag setting addressable area memory bank hardware i/o mapping da.b direct: bit is indicated by the 0 000h - 07fh bank 0 ? ram address (da), memory bank selection, and specified bit number (b). f80h - fffh bank 15 all 1-bit addressable peripherals (smb = 15) 1 000h - fffh smb = 0, 1, 2, 15 mema.b direct: bit is indicated by ad dressable area (mema) and bit number (b). x fb0h - fbfh ff0h - fffh bank 15 is0, is1, emb, erb, iex, irqx, pn.n memb.@l indirect: address is indicated by the upper 6 bits of ram area (memb) and the upper 2 bits of register l, and bit is indicated by the lower 2 bits of register l. x fc0h - fffh bank 15 bscn.x pn.n @h + da.b indirect: bit is indicated by the lower 4 bits of the address (da), memory bank selection, and the h register identifier. 0 000h - 0ffh bank 0 ? 1 000h - fffh smb = 0, 1, 2, 15 all 1-bit addressable peripherals (smb = 15) note : 'x' means don't care.
S3C72I9/p72i9 addressing modes 3 - 7 + + programming tip ? 1-bit addressing modes 1-bit direct addressing 1. if emb = "0": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 bits aflag ; 34h.3 ? 1 bits bflag ; f85h.3 ? 1 btst cflag ; if fbah.0 = 1, skip bits bflag ; else if, fbah.0 = 0, f85h.3 (bmod.3) ? 1 bits p3.0 ; ff3h.0 (p3.0) ? 1 2. if emb = "1": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 bits aflag ; 34h.3 ? 1 bits bflag ; 85h.3 ? 1 btst cflag ; if 0bah.0 = 1, skip bits bflag ; else if 0bah.0 = 0, 085h.3 ? 1 bits p3.0 ; ff3h.0 (p3.0) ? 1
addressing modes S3C72I9/p72i9 3 - 8 + + programming tip ? 1-bit addressing modes (continued) 1-bit indirect addressing 1. if emb = "0": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 ld h,#0bh ; h ? #0bh btstz @h+cflag ; if 0bah.0 = 1, 0bah.0 ? 0 and skip bits cflag ; else if 0ba h.0 = 0, fbah.0 ? 1 2. if emb = "1": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 ld h,#0bh ; h ? #0bh btstz @h+cflag ; if 0bah.0 = 1, 0bah.0 ? 0 and skip bits cflag ; else if 0bah.0 = 0, 0bah.0 ? 1
S3C72I9/p72i9 addressing modes 3 - 9 4-bit addressing table 3 -3. 4-bit direct and indirect ram addressing operand notation addressing mode description emb flag setting addressable area memory bank hardware i/o mapping da direct: 4-bit address indicated 0 000h - 07fh bank 0 ? by the ram address (da) and the memory bank selection f80h - fffh bank 15 all 4-bit ad dressable pe ripherals 1 000h - fffh smb = 0, 1, 2, 15 (smb = 15) @hl indirect: 4-bit address indi cated by the memory bank selection and register hl 0 000h - 0ffh bank 0 ? 1 000h - fffh smb = 0, 1, 2, 15 all 4-bit ad dressable pe ripherals (smb = 15) @wx indirect: 4-bit address indi cated by register wx x 000h - 0ffh bank 0 ? @wl indirect: 4-bit address indi cated by register wl x 000h - 0ffh bank 0 note : 'x' means don't care. + + programming tip ? 4-bit addressing modes 4-bit direct addressing 1. if emb = "0": adata equ 46h bdata equ 8eh smb 15 ; non-essential instruction, since emb = "0" ld a,p3 ; a ? (p3) smb 0 ; non-essential instruction, since emb = "0" ld adata,a ; (046h) ? a ld bdata,a ; (f8eh (lcon)) ? a 2. if emb = "1": adata equ 46h bdata equ 8eh smb 15 ld a,p3 ; a ? (p3) s mb 0 ld adata,a ; (046h) ? a ld bdata,a ; (08eh) ? a
addressing modes S3C72I9/p72i9 3 - 10 + + programming tip ? 4-bit addressing modes (continued) 4-bit indirect addressing (example 1) 1. if emb = "0", compare bank 0 locations 040h - 046h with bank 0 locations 060h - 066h: adata equ 46h bdata equ 66h smb 1 ; non-essential instruction, since emb = "0" ld hl,#bdata ld wx,#adata comp ld a,@wl ; a ? bank 0 (040h - 046h) cpse a,@hl ; if bank 0 (060h - 066h) = a, skip sret decs l jr comp ret 2. if emb = "1", compare bank 0 locations 040h - 046h to bank 1 locations 160h - 166h: adata equ 46h bdata equ 66h smb 1 ld hl,#bdata ld wx,#adata comp ld a,@wl ; a ? bank 0 (040h - 046h) cpse a,@hl ; if bank 1 (160h - 166h) = a, skip sret decs l jr comp ret
S3C72I9/p72i9 addressing modes 3 - 11 + + programming tip ? 4-bit addressing modes (concluded) 4-bit indirect addressing (example 2) 1. if emb = "0", exchange bank 0 locations 040h - 046h with bank 0 locations 060h - 066h: adata equ 46h bdata equ 66h smb 1 ; non-essential instruction, since emb = "0" ld hl,#bdata ld wx,#adata trans ld a,@wl ; a ? bank 0 (040h - 046h) xchd a,@hl ; bank 0 (060h - 066h) ? a jr trans 2. if emb = "1", exchange bank 0 locations 040h - 046h to bank 1 locations 160h - 166h: adata equ 46h bdata equ 66h smb 1 ld hl,#bdata ld wx,#adata trans ld a,@wl ; a ? bank 0 (040h - 046h) xchd a,@hl ; bank 1 (160h - 166h) ? a jr trans
addressing modes S3C72I9/p72i9 3 - 12 8-bit addressing table 3 - 4. 8-bit direct and indirect ram addressing instruction notation addressing mode description emb flag setting addressable area memory bank hardware i/o mapping da direct: 8-bit address indicated 0 000h - 07fh bank 0 ? by the ram address ( da = even number ) and memory bank selection f80h - fffh bank 15 all 8-bit ad dressable pe ripherals 1 000h - fffh smb = 0, 1, 2, 15 (smb = 15) @hl indirect: the 8-bit address indi - cated by the memory bank selection and register hl; (the 4 -bit l register value must be an even number) 0 000h - 0ffh bank 0 ? 1 000h - fffh smb = 0, 1, 2, 15 all 8-bit ad dressable pe ripherals (smb = 15) + + programming tip ? 8-bit addressing modes 8-bit direct addressing 1. if emb = "0": adata equ 46h bdata equ 8eh smb 15 ; non-essential instruction, since emb = "0" ld ea,p4 ; e ? (p5), a ? (p4) smb 0 ld adata,ea ; (046h) ? a, (047h) ? e ld bdata,ea ; (f8eh) ? a, (f8fh) ? e 2. if emb = "1": adata equ 46h bdata equ 8eh smb 15 ld ea,p4 ; e ? (p5), a ? (p4) smb 0 l d adata,ea ; (046h) ? a, (047h) ? e ld bdata,ea ; (08eh) ? a, (08fh) ? e
S3C72I9/p72i9 addressing modes 3 - 13 + + programming tip ? 8-bit addressing modes (continued) 8-bit indirect addressing 1. if emb = "0": adata equ 46h smb 1 ; non-essential instruction, since emb = "0" ld hl,#adata ld ea,@hl ; a ? (046h), e ? (047h) 2. if emb = "1": adata equ 46h smb 1 ld hl,#adata ld ea,@hl ; a ? ( 146h ), e ? (147h)
S3C72I9/p72i9 memory map 4 - 1 4 memory map overview to support program control of peripheral hardware, i/o addresses for peripherals are memory-mapped to bank 15 of the ram. memory mapping lets you use a mnemonic as the operand of an instruction in place of the specific memory location. access to bank 15 is controlled by the select memory bank (smb) instruction and by the enable memory bank flag (emb) setting. if the emb flag is "0", bank 15 can be addressed using direct addressing, regardless of the current smb value. 1-bit direct and indirect addressing can be used for specific locations in bank 15, regardless of the current emb value. i/o map for hardware registers table 4 - 1 contains detailed information about i/o mapping for peripheral hardware in bank 15 (register loca tions f80h - fffh). use the i/o map as a quick-reference source when writing application programs. the i/o map gives you the following information: ? register address ? register name (mnemonic for program addressing) ? bit values (both addressable and non-manipulable) ? read-only, write-only, or read and write addressability ? 1-bit, 4-bit, or 8-bit data manipulation characteristics
memory map S3C72I9/p72i9 4 - 2 table 4 - 1 . i/o map for memory bank 15 memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit f80h sp .3 .2 .1 "0" r/w no no yes f81h .7 .6 .5 .4 locations f82h-f84h are not mapped. f85h bmod .3 .2 .1 .0 w .3 yes no f86h bcnt r no no yes f87h f88h wmod .3 .2 .1 .0 w .3 (1) no yes f89h .7 "0" .5 .4 locations f8ah-f8bh are not mapped. f8ch lmod .3 .2 .1 .0 w no no yes f8dh .7 .6 .5 .4 f8eh lcon "0" .2 .1 .0 w no yes no locations f8fh is not mapped. f90h tmod0 .3 .2 "0" "0" w .3 no yes f91h "0" .6 .5 .4 f92h toe1 toe0 "u " (4) "0" r/w yes yes no locations f93h is not mapped. f94h tcnt0 r no no yes f95h f96h tref0 w no no yes f97h f98h wdmod .3 .2 .1 .0 w no no yes f99h .7 .6 .5 .4 f9ah wdflag (2) wdtcf "0" "0" "0" w .3 yes no locations f9bh-f9fh are not mapped. fa0h tmod1 .3 .2 "0" "0" w .3 no yes fa1h "0" .6 .5 .4 locations fa2h-fa3h are not mapped. fa4h tcnt1a r no no yes fa5h fa6h tcnt1b fa7h
S3C72I9/p72i9 memory map 4 - 3 table 4 - 1 . i/o map for memory bank 15 (continued) memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit fa8h tref1a w no no yes fa9h faah tref1b fabh locations fach-fafh are not mapped. fb0h psw is1 is0 emb erb r/w yes yes yes fb1h c ( 3 ) sc2 sc1 sc0 r no no fb2h ipr ime .2 .1 .0 w ime yes no fb3h pcon .3 .2 .1 .0 w no yes no fb4h imod0 "0" "0" .1 .0 w no yes no fb5h imod1 "0" "0" "0" .0 w no yes no fb6h imodk "0" .2 .1 .0 w no yes no fb7h scmod .3 .2 "0" .0 w yes no no fb8h ie4 irq4 ieb irqb r/w yes yes no locations fb9h is not mapped. fbah "0" "0" iew irqw r/w yes yes no fbbh iek irqk iet1 irqt1 fbch "0" "0" iet0 irqt0 fbdh "0" "0" ies irqs fbeh ie1 irq1 ie0 irq0 fbfh "0" "0" ie2 irq2 fc0h bsc0 r/w yes yes yes fc1h bsc1 fc2h bsc2 fc3h bsc3 locations fc4h-fcfh are not mapped.
memory map S3C72I9/p72i9 4 - 4 table 4 - 1 . i/o map for memory bank 15 (continued) memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit fd0h clmod .3 "0" .1 .0 w no yes no location fd1h is not mapped. fd 2 h pasr .3 .2 .1 .0 w no no yes fd3h "0" "0" "0" .4 locations fd4h-fd5h are not mapped. fd6h pne1 .3 .2 .1 .0 w no no yes fd7h "0" .6 .5 .4 fd8h pne2 .3 .2 .1 .0 no yes no locations fd9h is not mapped. fdah imod2 "0" "0" "0" .0 w no yes no locations fdbh is not mapped. fdch pumod1 pur3 pur2 pur1 pur0 w no no yes fddh pur7 pur6 pur5 pur4 fdeh pumod2 "0" "0" pur9 pur8 no yes no locations fdfh is not mapped. fe0h smod .3 .2 .1 .0 w .3 no yes fe1h .7 .6 .5 "0" locations fe2h-fe3h are not mapped. fe4h sbuf r/w no no yes fe5h fe6h pmg1 pm0.3 pm0.2 pm0.1 pm0.0 w no no yes fe7h "0" pm2.2 pm2.1 pm2.0 fe8h pmg2 pm3.3 pm3.2 pm3.1 pm3.0 yes fe9h "0" "0" "0" "0" feah pmg3 pm4.3 pm4.2 pm4.1 pm4.0 yes febh pm5.3 pm5.2 pm5.1 pm5.0 fech pmg4 pm6.3 pm6.2 pm6.1 pm6.0 yes fedh pm7.3 pm7.2 pm7.1 pm7.0 feeh pmg5 pm8.3 pm8.2 pm8.1 pm8.0 yes fefh pm9.3 pm9.2 pm9.1 pm9.0
S3C72I9/p72i9 memory map 4 - 5 table 4 - 1 . i/o map for memory bank 15 (concluded) memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit ff0h port 0 .3 .2 .1 .0 r/w yes yes no ff1h port 1 .3 .2 .1 .0 r ff2h port 2 "0" .2 .1 .0 r/w ff3h port 3 .3 .2 .1 .0 r/w ff4h port 4 .3 .2 .1 .0 r/w yes ff5h port 5 .3 / .7 .2 / .6 .1 / .5 .0 / .4 ff6h port 6 .3 .2 .1 .0 r/w ff7h port 7 .3 / .7 .2 / .6 .1 / .5 .0 / .4 ff8h port 8 .3 .2 .1 .0 r/w ff9h port 9 .3 / .7 .2 / .6 .1 / .5 .0 / .4 locations ffah-fffh are not mapped. notes: 1. bit 3 in the wmod register is read only. 2. f9ah.0, f9ah.1 and f9ah.2 are fixed to "0". 3 . the carry flag can be read or written by specific bit manipulation instructions only. 4. the ?u? means that the bit is undefined.
memory map S3C72I9/p72i9 4 - 6 register descriptions in this section, register descriptions are presented in a consistent format to familiarize you with the memory- mapped i/o locations in bank 15 of the ram. figure 4 - 1 describes features of the register description format. register descriptions are arranged in alphabetical order. programmers can use this section as a quick-reference source when writing application programs. counter registers, buffer registers, and reference registers, as well as the stack pointer and port i/o latches, are not included in these descriptions. more detailed information about how these registers are used is included in part ii of this manual, "hardware descriptions," in the context of the corresponding peripheral hardware module descriptions.
S3C72I9/p72i9 memory map 4 - 7 clmod - - clock output mode control register clmod.3 enable/disable clock output control bit clmod.2 bit 2 0 always logic zero clmod.1 - - .0 clock source and frequency selection control bits 3 2 1 0 bit identifier .3 .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 r = read-only w = write-only r/w = read/write bit value immediately after a reset bit number in msb to lsb order type of addressing that must be used to address the bit (1-bit, 4-bit, or 8-bit) description of the effect of specific bit settings bit identifier used for bit addressing register and bit ids used for bit addressing cpu fd0h associated hardware module register location in ram bank 15 name of individual bit or related bits register name register id select cpu clock souce fx/4, fx/8, fx/64 (1.05 mhz, 524khz, or 65.5 khz), or fxt/4 select system clock fxx/8 (524 khz at 4.19 mhz) select system clock fxx/16 (262 khz at 4.19 mhz) select system clock fxx/64 (65.5 khz at 4.19 mhz) 0 0 1 1 0 1 0 1 0 disable clock output at the clo pin 0 enable clock output at the clo pin figure 4 - 1 . register description format
memory map S3C72I9/p72i9 4 - 8 bmod ? basic timer mode register bt f85h bit 3 2 1 0 identifier .3 .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 1/4 4 4 4 bmod.3 basic timer restart bit 1 restart basic timer, then clear irqb flag, bcnt and bmod.3 to logic zero bmod.2 - .0 input clock frequency and interrupt interval time 0 0 0 input clock frequency: interrupt interval time (wait time) fxx/2 12 (1.02 khz) 2 20 /fxx (250 ms) 0 1 1 input clock frequency: interrupt interval time (wait time) fxx /2 9 (8.18 khz) 2 17 / fxx (31.3 ms) 1 0 1 input clock frequency: interrupt interval time (wait time) fxx/2 7 (32.7 khz) 2 15 /fxx (7.82 ms) 1 1 1 input clock frequency: interrupt interval time (wait time) fxx/2 5 (131 khz) 2 13 /fxx (1.95 ms) notes: 1 . when a reset occurs, the oscillator stabilization wait time is 31.3 ms (2 17 /fxx) at 4.19 mhz. 2 . 'fxx' is the system clock rate given a clock frequency of 4.19 mhz.
S3C72I9/p72i9 memory map 4 - 9 clmod ? clock output mode register cpu fd0h bit 3 2 1 0 identifier .3 "0" .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 clmod.3 enable/disable clock output control bit 0 disable clock output at the clo pin 1 enable clock output at the clo pin clmod.2 bit 2 0 always logic zero clmod.1 - .0 clock source and frequency selection control bits 0 0 select cpu clock source fx/4, fx/8, fx/64 (1.05 mhz, 524 khz, or 65.5 khz) or fxt/4 0 1 select system clock fxx/8 (524 khz) 1 0 select system clock fxx/16 (262 khz) 1 1 select system clock fxx/64 (65.5 khz) note : 'fxx' is the system clock, given a clock frequency of 4.19 mhz.
memory map S3C72I9/p72i9 4 - 10 ie0, irq0 ? int0 interrupt enable/request flags cpu fbeh ie 1 , irq 1 ? int1 interrupt enable/request flags cpu fbeh bit 3 2 1 0 identifier ie1 irq1 ie0 irq0 reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 ie1 int1 interrupt enable flag 0 disable interrupt requests at the int1 pin 1 enable interrupt requests at the int1 pin irq1 int1 interrupt request flag ? generate int1 interrupt (this bit is set and cleared by hardware when rising or falling edge detected at int1 pin.) ie0 int0 interrupt enable flag 0 disable interrupt requests at the int0 pin 1 enable interrupt requests at the int0 pin irq0 int0 interrupt request flag ? generate int0 interrupt (this bit is set and cleared automatically by hardware when rising or falling edge detected at int0 pin.)
S3C72I9/p72i9 memory map 4 - 11 ie2 , irq2 ? int2 interrupt enable/request flags cpu fbfh bit 3 2 1 0 identifier "0" "0" ie2 irq2 reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 - .2 bits 3 - 2 0 always logic zero ie2 int2 interrupt enable flag 0 disable int2 interrupt requests at the int2 pin 1 enable int2 interrupt requests at the int2 pin irq2 int2 interrupt request flag ? generate int2 quasi-interrupt (this bit is set and is not cleared automatically by hardware when a rising or falling edge is detected at int2. since int2 is a quasi-interrupt, irq2 flag must be cleared by software.)
memory map S3C72I9/p72i9 4 - 12 ie4 , irq4 ? int4 interrupt enable/request flags cpu fb8h ieb, irqb ? intb interrupt enable/request flags cpu fb8h bit 3 2 1 0 identifier ie4 irq4 ieb irqb reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 ie4 int4 interrupt enable flag 0 disable interrupt requests at the int4 pin 1 enable interrupt requests at the int4 pin irq4 int4 interrupt request flag ? generate int4 interrupt (this bit is set and cleared automatically by hardware when rising and falling signal edge detected at int4 pin.) ieb intb interrupt enable flag 0 disable intb interrupt requests 1 enable intb interrupt requests irqb intb interrupt request flag ? generate intb interrupt (this bit is set and cleared automatically by hardware when reference interval signal received from basic timer.)
S3C72I9/p72i9 memory map 4 - 13 ies , irqs ? ints interrupt enable/request flags cpu fbdh bit 3 2 1 0 identifier "0" "0" ies irqs reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 - .2 bits 3 - 2 0 always logic zero ies ints interrupt enable flag 0 disable ints interrupt requests 1 enable ints interrupt requests irqs ints interrupt request flag ? generate ints interrupt (this bit is set and cleared automatically by hardware when serial data transfer completion signal received from serial i/o interface.)
memory map S3C72I9/p72i9 4 - 14 iet0 , irqt0 ? intt0 interrupt enable/request flags cpu fbch bit 3 2 1 0 identifier "0" "0" iet0 irqt0 reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 - .2 bits 3 - 2 0 always logic zero iet0 intt0 interrupt enable flag 0 disable intt0 interrupt requests 1 enable intt0 interrupt requests irqt0 intt0 interrupt request flag ? generate intt0 interrupt (this bit is set and cleared automatically by hardware when contents of tcnt0 and tref0 registers match.)
S3C72I9/p72i9 memory map 4 - 15 iet1 , irqt1 ? intt1 interrupt enable/request flags cpu fbbh iek, irqk ? intk interrupt enable/request flags cpu fbbh bit 3 2 1 0 identifier iek irqk iet1 irqt1 reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 iek intk interrupt enable flag 0 disable interrupt requests at the k0 - k7 pins 1 enable interrupt requests at the k0 - k7 pins irqk intk interrupt request flag ? generate intk interrupt (this bit is set and cleared automatically by hardware when rising or falling edge detected at k0 - k7 pins.) iet1 intt1 interrupt enable flag 0 disable intt1 interrupt requests 1 enable intt1 interrupt requests irqt1 intt1 interrupt request flag ? generate intt1 interrupt (this bit is set and cleared automatically by hardware when contents of tcnt1 and tref1 registers match.)
memory map S3C72I9/p72i9 4 - 16 iew , irqw ? intw interrupt enable/request flags cpu fbah bit 3 2 1 0 identifier "0" "0" iew irqw reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 - .2 bits 3 - 2 0 always logic zero iew intw interrupt enable flag 0 disable intw interrupt requests 1 enable intw interrupt requests irqw intw interrupt request flag ? generate intw interrupt (this bit is set when the timer interval is set to 0.5 seconds or 3.91 milliseconds.) note : since intw is a quas i-interrupt, the irqw flag must be cleared by software.
S3C72I9/p72i9 memory map 4 - 17 imod0 ? external interrupt 0 (int0) mode register cpu fb 4 h bit 3 2 1 0 identifier "0" "0" .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 imod0. 3 - . 2 bit s 3- 2 0 always logic zero imod0.1 - .0 external interrupt mode control bits 0 0 interrupt request is triggered by a rising signal edge 0 1 interrupt request is triggered by a falling signal edge 1 0 interrupt request is triggered by both rising and falling signal edges 1 1 interrupt request flag (irq 0 ) cannot be set to logic one
memory map S3C72I9/p72i9 4 - 18 imod 1 ? external interrupt 1 (int 1 ) mode register cpu fb 5 h bit 3 2 1 0 identifier "0" "0" "0" imod1.0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 imod1.3 - .1 bits 3 - 1 0 always logic zero imod1.0 external interrupt 1 edge detection control bit 0 rising edge detection 1 falling edge detection
S3C72I9/p72i9 memory map 4 - 19 imod2 ? external interrupt 2 (int2) mode register cpu fdah bit 3 2 1 0 identifier "0" "0" "0" imod2.0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 imod2.3 - .1 bits 3 - 1 0 always logic zero imod2.0 external interrupt 2 edge detection selection bit 0 interrupt request at int2 pin trigged by rising edge 1 interrupt request at int2 pin trigged by falling edge
memory map S3C72I9/p72i9 4 - 20 imodk ? external key interrupt mode register cpu fb6h bit 3 2 1 0 identifier "0" imodk.2 imodk.1 imodk.0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 imodk.3 bit 3 0 always logic zero imodk.2 external key interrupt edge detection selection bit 0 falling edge detection 1 rising edge detection imodk.1 - .0 external key interrupt mode control bits 0 0 disable key interrupt 0 1 enable edge detection at k0 - k3 pins 1 0 enable edge detection at k4 - k7 pins 1 1 enable edge detection at k0 - k7 pins notes: 1. to generate a key interrupt, all of the selected pins must be configured to input mode. if any one of the selected pins is configured to output mode, only falling edge can be detected. 2. to generate a key interrupt, all of the selected pins must be at input high state for falling edge detection, or all of the selected pins must be at input low state for rising edge detection. if any one of them or more is at input low state or input high state, the interrupt may be not occurred at falling edge or rising edge. 3. to generate a key interrupt, first, configure pull-up resistors or external pull-down resistors. and then, select edge detection and pins by setting imodk register.
S3C72I9/p72i9 memory map 4 - 21 ipr ? interrupt priority register cpu fb2h bit 3 2 1 0 identifier ime .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 1/4 4 4 4 ime interrupt master enable bit 0 disable all interrupt processing 1 enable processing for all interrupt service requests ipr.2 - .0 interrupt priority assignment bits 0 0 0 normal interrupt handling according to default priority settings 0 0 1 process intb and int4 interrupts at highest priority 0 1 0 process int0 interrupt at highest priority 0 1 1 process int1 interrupt at highest priority 1 0 0 process ints interrupt at highest priority 1 0 1 process intt0 interrupt at highest priority 1 1 0 process intt1 interrupt at highest priority 1 1 1 process intk interrupt at highest priority
memory map S3C72I9/p72i9 4 - 22 lcon ? lcd output control register lcd f8eh bit 3 2 1 0 identifier "0" .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 lcon.3 bit 3 0 always logic zero lcon.2 lcd clock output disable/enable bit 0 disable lcdck and lcdsy signal outputs. 1 enable lcdck and lcdsy signal outputs. lcon.1 - .0 lcd output control bit 0 0 lcd display off; cut off current to dividing resistor 0 1 lcd display on; application without contrast control 1 0 lcd display on; application with contrast control 1 1 lcd dispaly on; application without contrast control note s : 1. the function of lcon.0 is applied in case of using the internal gnd for lcd power; the function of lcon.1 is used for contrast control application. 2. the table for lcon.1 - lcon.0 also shows the case that internal bias resistors are built-in by mask option . for the case that external bias resistors are configured by mask option, refer to chapter 12.
S3C72I9/p72i9 memory map 4 - 23 lmod ? lcd mode register lcd f8dh, f8ch bit 3 2 1 0 3 2 1 0 identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 lmod.7 - .5 lcd output segment and pin configuration bits 0 0 0 segments 40 - 43, 44 - 47, 48 - 51 and 52 - 55 0 0 1 segments 40 - 43, 44 - 47 and 48 - 51; normal i/o at port 6 0 1 0 segments 40 - 43 and 44 - 47; normal i/o at port 6 and port 7 0 1 1 segments 40 -43; normal i/o at port 6, 7 and 8 1 0 0 normal i/o at port 6, 7, 8 and 9 note: segment pins that also can used for normal i/o should be configured to output mode when the seg function is used. lmod.4 - .3 lcd clock (lcdck) frequency selection bits 0 0 when 1/8 duty: fxx/2 7 (256 hz); when 1/16 duty: fxx/2 6 (512 hz) 0 1 when 1/8 duty: fxx/2 6 (512 hz); when 1/16 duty: fxx/ 2 5 (1024 hz) 1 0 when 1/8 duty: fxx/2 5 (1024 hz); when 1/16 duty: fxx/2 4 (2048 hz) 1 1 when 1/8 duty: fxx/2 4 ( 2048 hz); when 1/16 duty: fxx/ 2 3 (4096 hz) note: lcdck is supplied only when the watch timer operates. to use the lcd controller, bit 2 in the watch mode register wmod should be set to 1. lmod.2 lcd duty and selection bits 0 1/8 duty (com0 - com7 select) 1 1/16 duty (com0 - com15 select) note: when 1/16 duty is selected, ports 4 and 5 should be configured as output mode; when 1/8 duty is selected, ports 4 and 5 can be used as normal i/o ports. lmod.1 - .0 lcd display mode selection bits 0 0 all lcd dots off 0 1 all lcd dots on 1 1 normal display
memory map S3C72I9/p72i9 4 - 24 pasr ? page selection register f d2 h bit 7 6 5 4 3 2 1 0 identifier "0" "0" "0" .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 pasr. 7 - .5 bits 7 - 4 0 always logic zero pasr .4 - .0 page selection register in the bank 1 0 0 0 0 0 00h page in the b ank 1 0 0 0 0 1 01h page in the b ank 1 ? ? ? 2 1 1 1 1 0 1eh page in the bank 1 note: the 00h -1e h pages can be used in the S3C72I9 .
S3C72I9/p72i9 memory map 4 - 25 pcon ? power control register cpu fb3h bit 3 2 1 0 identifier .3 .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 pcon.3 - .2 cpu operating mode control bits 0 0 enable normal cpu operating mode 0 1 initiate idle power-down mode 1 0 initiate stop power-down mode pcon.1 - .0 cpu clock frequency selection bits 0 0 if scmod.0 = "0" , fx/64; if scmod.0 = "1", fxt/ 4 1 0 if scmod.0 = "0", fx/8; if scmod.0 = "1", fxt/ 4 1 1 if scmod.0 = "0", fx/4; if scmod.0 = "1", fxt/4 note : 'fx' is the main system clock; 'fxt' is the subsystem clock.
memory map S3C72I9/p72i9 4 - 26 pmg1 ? port i/o mode register 1 (group 1: port 0, 2) i/o fe7h, fe6h bit 7 6 5 4 3 2 1 0 identifier "0" pm2.2 pm2.1 pm2.0 pm0.3 pm0.2 pm0.1 pm0.0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 .7 bit 7 0 always logic zero pm2.2 p2.2 i/o mode selection flag 0 set p2.2 to input mode 1 set p2.2 to output mode pm2.1 p2.1 i/o mode selection flag 0 set p2.1 to input mode 1 set p2.1 to output mode pm2.0 p2.0 i/o mode selection flag 0 set p2.0 to input mode 1 set p2.0 to output mode pm0.3 p0.3 i/o mode selection flag 0 set p0.3 to input mode 1 set p0.3 to output mode pm0.2 p0.2 i/o mode selection flag 0 set p0.2 to input mode 1 set p0.2 to output mode pm0.1 p0.1 i/o mode selection flag 0 set p0.1 to input mode 1 set p0.1 to output mode pm0.0 p0.0 i/o mode selection flag 0 set p0.0 to input mode 1 set p0.0 to output mode
S3C72I9/p72i9 memory map 4 - 27 pmg2 ? port i/o mode register 2 (group 2: port 3) i/o fe9h, fe8h bit 7 6 5 4 3 2 1 0 identifier "0" "0" "0" "0" pm3.3 pm3.2 pm3.1 pm3.0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 .7 - .4 bits 7 - 4 0 always logic zero pm3.3 p3.3 i/o mode selection flag 0 set p3.3 to input mode 1 set p3.3 to output mode pm3.2 p3.2 i/o mode selection flag 0 set p3.2 to input mode 1 set p3.2 to output mode pm3.1 p3.1 i/o mode selection flag 0 set p3.1 to input mode 1 set p3.1 to output mode pm3.0 p3.0 i/o mode selection flag 0 set p3.0 to input mode 1 set p3.0 to output mode
memory map S3C72I9/p72i9 4 - 28 pmg3 ? port i/o mode register 3 (group 3: port 4, 5) i/o febh, feah bit 7 6 5 4 3 2 1 0 identifier pm5.3 pm5.2 pm5.1 pm5.0 pm4.3 pm4.2 pm4.1 pm4.0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 pm5.3 p5.3 i/o mode selection flag 0 set p5.3 to input mode 1 set p5.3 to output mode pm5.2 p5.2 i/o mode selection flag 0 set p5.2 to input mode 1 set p5.2 to output mode pm5.1 p5.1 i/o mode selection flag 0 set p5.1 to input mode 1 set p5.1 to output mode pm5.0 p5.0 i/o mode selection flag 0 set p5.0 to input mode 1 set p5.0 to output mode pm4.3 p4.3 i/o mode selection flag 0 set p4.3 to input mode 1 set p4.3 to output mode pm4.2 p4.2 i/o mode selection flag 0 set p4.2 to input mode 1 set p4.2 to output mode pm4.1 p4.1 i/o mode selection flag 0 set p4.1 to input mode 1 set p4.1 to output mode pm4.0 p4.0 i/o mode selection flag 0 set p4.0 to input mode 1 set p4.0 to output mode
S3C72I9/p72i9 memory map 4 - 29 pmg4 ? port i/o mode register 4 (group 4 : port 6, 7) i/o fedh, fech bit 7 6 5 4 3 2 1 0 identifier pm7.3 pm7.2 pm7.1 pm7.0 pm6.3 pm6.2 pm6.1 pm6.0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 pm7.3 p7.3 i/o mode selection flag 0 set p7.3 to input mode 1 set p7.3 to output mode pm7.2 p7.2 i/o mode selection flag 0 set p7.2 to input mode 1 set p7.2 to output mode pm7.1 p7.1 i/o mode selection flag 0 set p7.1 to input mode 1 set p7.1 to output mode pm7.0 p7.0 i/o mode selection flag 0 set p7.0 to input mode 1 set p7.0 to output mode pm6.3 p6.3 i/o mode selection flag 0 set p6.3 to input mode 1 set p6.3 to output mode pm6.2 p6.2 i/o mode selection flag 0 set p6.2 to input mode 1 set p6.2 to output mode pm6.1 p6.1 i/o mode selection flag 0 set p6.1 to input mode 1 set p6.1 to output mode pm6.0 p6.0 i/o mode selection flag 0 set p6.0 to input mode 1 set p6.0 to output mode
memory map S3C72I9/p72i9 4 - 30 pmg5 ? port i/o mode register 5 (group 5 : port 8, 9) i/o fefh, feeh bit 7 6 5 4 3 2 1 0 identifier pm9.3 pm9.2 pm9.1 pm9.0 pm8.3 pm8.2 pm8.1 pm8.0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 pm9.3 p9.3 i/o mode selection flag 0 set p9.3 to input mode 1 set p9.3 to output mode pm9.2 p9.2 i/o mode selection flag 0 set p9.2 to input mode 1 set p9.2 to output mode pm9.1 p9.1 i/o mode selection flag 0 set p9.1 to input mode 1 set p9.1 to output mode pm9.0 p9.0 i/o mode selection flag 0 set p9.0 to input mode 1 set p9.0 to output mode pm8.3 p8.3 i/o mode selection flag 0 set p8.3 to input mode 1 set p8.3 to output mode pm8.2 p8.2 i/o mode selection flag 0 set p8.2 to input mode 1 set p8.2 to output mode pm8.1 p8.1 i/o mode selection flag 0 set p8.1 to input mode 1 set p8.1 to output mode pm8.0 p8.0 i/o mode selection flag 0 set p8.0 to input mode 1 set p8.0 to output mode
S3C72I9/p72i9 memory map 4 - 31 pne1 ? n-channel open-drain mode register 1 i/o fd7h, fd6h bit 7 6 5 4 3 2 1 0 identifier "0" pne1.6 pne1 .5 pne1 .4 pne1 .3 pne1 .2 pne1 .1 pne1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 .7 bit 7 0 always logic 0 pne1 .6 p2.2 n-channel open-drain configurable bit 0 configure p2.2 as a push-pull 1 configure p2.2 as a n-channel open-drain pne1 .5 p2.1 n-channel open-drain configurable bit 0 configure p2.1 as a push-pull 1 configure p2.1 as a n-channel open-drain pne1 .4 p2.0 n-channel open-drain configurable bit 0 configure p2.0 as a push-pull 1 configure p2.0 as a n-channel open-drain pne1 .3 p0.3 n-channel open-drain configurable bit 0 configure p0.3 as a push-pull 1 configure p0.3 as a n-channel open-drain pne1 .2 p0.2 n-channel open-drain configurable bit 0 configure p0.2 as a push-pull 1 configure p0.2 as a n-channel open-drain pne1 .1 p0.1 n-channel open-drain configurable bit 0 configure p0.1 as a push-pull 1 configure p0.1 as a n-channel open-drain pne1 .0 p0.0 n-channel open-drain configurable bit 0 configure p0.0 as a push-pull 1 configure p0.0 as a n-channel open-drain
memory map S3C72I9/p72i9 4 - 32 pne2 ? n-channel open-drain mode register 2 i/o fd8h bit 3 2 1 0 identifier pne2 .3 pne2 .2 pne2 .1 pne2 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 pne2 .3 p3.3 n-channel open-drain configurable bit 0 configure p3.3 as a push-pull 1 configure p3.3 as a n-channel open-drain pne2 .2 p3.2 n-channel open-drain configurable bit 0 configure p3.2 as a push-pull 1 configure p3.2 as a n-channel open-drain pne2 .1 p3.1 n-channel open-drain configurable bit 0 configure p3.1 as a push-pull 1 configure p3.1 as a n-channel open-drain pne2 .0 p3.0 n-channel open-drain configurable bit 0 configure p3.0 as a push-pull 1 configure p3.0 as a n-channel open-drain
S3C72I9/p72i9 memory map 4 - 33 psw ? program status word cpu fb1h, fb0h bit 7 6 5 4 3 2 1 0 identifier c sc2 sc1 sc0 is1 is0 emb erb reset reset value (1) 0 0 0 0 0 0 0 read/write r/w r r r r/w r/w r/w r/w bit addressing (2) 8 8 8 1/4 /8 1/4 /8 1 /4/8 1 /4/8 c carry flag 0 no overflow or borrow condition exists 1 an overflow or borrow condition does exist sc2 - sc0 skip condition flags 0 no skip condition exists; no direct manipulation of these bits is allowed 1 a skip condition exists; no direct manipulation of these bits is allowed is1, is0 interrupt status flags 0 0 service all interrupt requests 0 1 service only the high-priority interrupt(s) as determined in the interrupt priority register (ipr) 1 0 do not service any more interrupt requests 1 1 undefined emb enable data memory bank flag 0 restrict program access to data memory to bank 15 (f80h - fffh) and to the locations 000h - 07fh in the bank 0 only 1 enable full access to data memory banks 0, 1, 2, and 15 erb enable register bank flag 0 select register bank 0 as working register area 1 select register banks 0, 1, 2, or 3 as working register area in accordance with the select register bank (srb) instruction operand notes : 1. the value of the carry flag after a reset occurs during normal operation is undefined. if a reset occurs during power-down mod e (idle or stop), the current value of the carry flag is retained. 2. the carry flag can only be addressed by a specific set of 1-bit manipulation instructions. see section 2 for detailed information.
memory map S3C72I9/p72i9 4 - 34 pumod1 ? pull- u p resistor mode register 1 i/o fddh, fdch bit 7 6 5 4 3 2 1 0 identifier pur7 pur6 pur5 pur4 pur3 pur2 pur1 pur0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 pur7 connect/disconnect port 7 pull- u p resistor control bit 0 disconnect port 7 pull-up resistor 1 connect port 7 pull-up resistor pur6 connect/disconnect port 6 pull- u p resistor control bit 0 disconnect port 6 pull-up resistor 1 connect port 6 pull-up resistor pur5 connect/disconnect port 5 pull- u p resistor control bit 0 disconnect port 5 pull-up resistor 1 connect port 5 pull-up resistor pur4 connect/disconnect port 4 pull- u p resistor control bit 0 disconnect port 4 pull-up resistor 1 connect port 4 pull-up resistor pur3 connect/disconnect port 3 pull- u p resistor control bit 0 disconnect port 3 pull-up resistor 1 connect port 3 pull-up resistor pur2 connect/disconnect port 2 pull- u p resistor control bit 0 disconnect port 2 pull-up resistor 1 connect port 2 pull-up resistor pur1 connect/disconnect port 1 pull- u p resistor control bit 0 disconnect port 1 pull-up resistor 1 connect port 1 pull-up resistor pur0 connect/disconnect port 0 pull- u p resistor control bit 0 disconnect port 0 pull-up resistor 1 connect port 0 pull-up resistor
S3C72I9/p72i9 memory map 4 - 35 pumod2 ? pull- u p resistor mode register 2 i/o fdeh bit 3 2 1 0 identifier "0" "0" pur9 pur8 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 .3 - .2 bits 3 - 2 0 always cleared to logic zero pur9 connect/disconnect port 9 pull- u p resistor control bit 0 disconnect port 9 pull-up resistor 1 connect port 9 pull-up resistor pur8 connect/disconnect port 8 pull- u p resistor control bit 0 disconnect port 8 pull-up resistor 1 connect port 8 pull-up resistor
memory map S3C72I9/p72i9 4 - 36 scmod ? system clock mode control register cpu fb7h bit 3 2 1 0 identifier .3 .2 "0" .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 1 1 1 1 scmod. 3 bit 3 0 enable main system clock (fx) 1 disable main system clock (fx) scmod. 2 bit 2 0 enable sub system clock (fxt) 1 disable sub system clock (fxt) scmod. 1 bit 1 0 always logic zero scmod. 0 bit 0 0 select main system clock (fx) 1 select sub system clock (fxt) note s : 1. sub-oscillation goes into stop mode only by scmod.2. pcon which revokes stop mode cannot stop the sub- oscillation. 2. you can use scmod.2 as follows (ex; after data bank was used, a few minutes have passed): main operation ? sub-operation ? sub-idle (lcd on, after a few minutes later without any external input) ? sub- operation ? main operation ? scmod.2 = 1 ? main stop mode (lcd off). 3. scmod bits 3 - 0 cannot be modified simultaneously by a 4-bit instruction; they can only be modified by separate 1-bit instructions.
S3C72I9/p72i9 memory map 4 - 37 smod ? serial i/o mode register sio fe1h, fe0h bit 7 6 5 4 3 2 1 0 identifier .7 .6 .5 "0" .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 1/8 8 8 8 smod.7 - .5 serial i/o clock selection and sbuf r/w status control bits 0 0 0 use an external clock at the sck pin; enable sbuf when sio operation is halted or when sck goes high 0 0 1 use the tol0 clock from timer/counter 0; enable sbuf when sio operation is halted or when sck goes high 0 1 x use the selected cpu clock (fxx/4, 8, or 64; 'fxx' is the system clock) then, enable sbuf read/write operation. 'x' means 'don't care.' 1 0 0 4.09 khz clock (fxx/2 10 ) 1 1 1 262 khz clock (fxx/2 4 ); note: you cannot select a fxx/2 4 clock fre - quency if you have selected a cpu clock of fxx/64 note : all khz frequency ratings assume a system clock of 4.19 mhz. smod.4 bit 4 0 always logic zero smod.3 initiate serial i/o operation bit 1 clear irqs flag and 3-bit clock counter to logic zero; then initiate serial trans - mission. when sio transmission starts, this bit is cleared by hardware to logic zero smod.2 enable/disable sio data shifter and clock counter bit 0 disable the data shifter and clock counter; the contents of irqs flag is retained when serial transmission is completed 1 enable the data shifter and clock counter; the irqs flag is set to logic one when serial transmission is completed smod.1 serial i/o transmission mode selection bit 0 receive-only mode 1 transmit-and-receive mode smod.0 lsb/msb transmission mode selection bit 0 transmit the most significant bit (msb) first 1 transmit the least significant bit (lsb) first
memory map S3C72I9/p72i9 4 - 38 tmod0 ? timer/counter 0 mode register t/c0 f91h, f90h bit 7 6 5 4 3 2 1 0 identifier "0" .6 .5 .4 .3 .2 "0" "0" reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 1/8 8 8 8 tmod0.7 bit 7 0 always logic zero tmod0.6 - .4 timer/counter 0 input clock selection bits 0 0 0 external clock input at tcl0 pin on rising edge 0 0 1 external clock input at tcl0 pin on falling edge 1 0 0 fxx/2 10 (4 .09 k hz) 1 0 1 fxx/2 6 (65.5 khz) 1 1 0 fxx/2 4 (262 khz) 1 1 1 fxx (4.19 mhz) note : ?fxx? is selected system clock of 4.19 mhz tmod0.3 clear counter and resume counting control bit 1 clear tcnt0, irqt0, and tol0 and resume counting immediately (this bit is cleared automatically when counting starts.) tmod0.2 enable/disable timer/counter 0 bit 0 disable timer/counter 0; retain tcnt0 contents 1 enable timer/counter 0 tmod0.1 bit 1 0 always logic zero tmod0.0 bit 0 0 always logic zero
S3C72I9/p72i9 memory map 4 - 39 tmod1 ? timer/counter 1 mode register t/c fa1h, fa0h bit 3 2 1 0 3 2 1 0 identifier "0" .6 .5 .4 .3 .2 "0" "0" reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 1/8 8 8 8 tmod1.7 bit 7 0 always logic zero tmod1.6 - .4 timer/counter 1 input clock selection bit 0 0 0 external clock input at tcl1 pin on rising edge 0 0 1 external clock input at tcl1 pin on falling edge 1 0 0 fxx/2 10 (4 .09 k hz) 1 0 1 fxx/2 8 ( 16.4 khz) 1 1 0 fxx/2 6 ( 65.5 khz) 1 1 1 fxx / 2 4 ( 262 k hz) note : ?fxx? is selected system clock of 4.19 mhz tmod1.3 clear counter and resume counting control bit 1 clear tcnt1, irqt1, and tol1 and resume counting immediately (this bit is cleared automatically when counting starts.) tmod1.2 enable/disable timer/counter 1 bit 0 disable timer/counter 1; retain tcnt1 contents 1 enable timer/counter 1 tmod1.1 bit 1 0 always logic zero tmod1.0 bit 0 0 always logic zero
memory map S3C72I9/p72i9 4 - 40 toe ? timer output enable flag register t/c f92h bit 3 2 1 0 identifier toe1 toe0 "u " "0" reset reset value 0 0 u 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 toe1 timer/counter 1 output enable flag 0 disable timer/counter 1 clock output at the tclo1 pin 1 enable timer/counter 1 clock output at the tclo1 pin toe0 timer/counter 0 output enable flag 0 disable timer/counter 0 clock output at the tclo0 pin 1 enable timer/counter 0 clock output at the tclo0 pin .1 bits 1 u this bit is undefined .0 bits 0 0 always logic zero note: the ?u? means that the bit is undefined.
S3C72I9/p72i9 memory map 4 - 41 w dflag ? watch dog timer 's counter clear flag wt f9a h .3 bit 3 2 1 0 identifier wdtcf "0" "0" "0" reset reset value 0 0 0 0 read/write w w w w bit addressing 1/4 1/4 1/4 1/4 wdtcf watchdog timer's counter clear bit 0 - 1 clear the wdt's counter to zero and restart the wdt's counter wdflag.2 - .0 bit2-0 0 always logic zero
memory map S3C72I9/p72i9 4 - 42 w d mod ? watch dog timer mode control register wt f 9 9h, f 9 8h bit 3 2 1 0 3 2 1 0 identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 1 0 1 0 0 1 0 1 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 wmod.7 - .0 watchdog timer enable/disable control 0 1 0 1 1 0 1 0 disable watchdog timer function other values enable watchdog timer function
S3C72I9/p72i9 memory map 4 - 43 wmod ? watch timer mode register wt f89h, f88h bit 7 6 5 4 3 2 1 0 identifier .7 "0" .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 ( note ) 0 0 0 read/write w w w w r w w w bit addressing 8 8 8 8 1 8 8 8 wmod.7 enable/disable buzzer output bit 0 disable buzzer (buz) signal output at the buz pin 1 enable buzzer (buz) signal output at the buz pin wmod.6 bit 6 0 always logic zero wmod.5 - .4 output buzzer frequency selection bits 0 0 2 khz buzzer (buz) signal output 0 1 4 khz buzzer (buz) signal output 1 0 8 khz buzzer (buz) signal output 1 1 16 khz buzzer (buz) signal output wmod.3 xt in input level control bit 0 input level to xt in pin is low; 1-bit read-only addressable for tests 1 input level to xt in pin is high; 1-bit read-only addressable for tests wmod.2 enable/disable watch timer bit 0 disable watch timer and clear frequency dividing circuits 1 enable watch timer wmod.1 watch timer speed control bit 0 normal speed; set irqw to 0.5 seconds 1 high-speed operation; set irqw to 3.91 ms wmod.0 watch timer clock selection bit 0 select main system clock (fx)/128 as the watch timer clock 1 select a subsystem clock as the watch timer clock note : reset sets wmod.3 to the current input level of the subsystem clock, xt in . if the input level is high, wmod.3 is set to logic one; if low, wmod.3 is cleared to zero along with all the other bits in the wmod register.
S3C72I9/p72i9 oscillator circuits 6 - 1 6 oscillator circuits overview the S3C72I9 microcontroller have two oscillator circuits: a main system clock circuit, and a subsystem clock circuit. the cpu and peripheral hardware operate on the system clock frequency supplied through these circuits. specifically, a clock pulse is required by the following peripheral modules: ? lcd controller ? basic timer ? timer/counter 0 and 1 ? watch timer ? serial i/o interface ? clock output circuit cpu clock notation in this document, the following notation is used for descriptions of the cpu clock: fx main - system clock fxt sub - system clock fxx selected system clock clock control registers when the system clock mode register, scmod, and the power control register, pcon, are both cleared to zero after reset , the normal cpu operating mode is enabled, a main system clock is selected as fx/64, and main system clock oscillation is initiated. the pcon is used to select normal cpu operating mode or one of two power down mode-stop or idle. bits 3 and 2 of the pcon register can be manipulated by stop of idle instruction to engage stop or idle power down mode. the scmod, lets you select the main system clock (fx) or a subsystem clock (fxt) as the cpu clock and start (or stop) main/sub system clock oscillation. the resulting clock source, either main system clock or subsystem clock, is referred to the selected system clock (fxx). the main system clock is selected and oscillation started when all scmod bits are cleared to ?0?. by setting scmod.3, scmod.2 and scmod.0 to different values, you can select a subsystem clock source and start or stop main/sub system clock oscillation. to stop main system clock oscillation, you must use the stop instruction (assuming the main system clock is selected) or manipulate scmod.3 (assuming the sub system clock is selected). the main system clock frequencies can be divided by 4, 8, or 64 and a subsystem clock frequencies can only be divided by 4. by manipulating pcon bits 1 and 0, you select one of the following frequencies as the cpu clock. fx/4, fxt/4, fx/8, fx/64
oscillator circuits S3C72I9/p72i9 6 - 2 using a subsystem clock if a subsystem clock is being used as the selected system clock, the idle power-down mode c an be initiated by executing an idle instruction. the watch timer, buzzer and lcd display operate normally with a subsystem clock source, since they operate at very low speed (as low as 122 s at 32.768 khz) and with very low power consumption . x in x out xt in xt out main-system oscillator circuit oscillator stop selector fxx selector oscillator stop sub-system oscillator circuit watch timer lcd controller scmod.3 scmod.0 scmod.2 selector fx/1, 2, 16 pcon.1 pcon.2 pcon.3 pcon.0 fxt 1/1-1/4096 frequency dividing circuit 1/2 1/16 basic timer timer/counter 0, and 1 watch timer lcd controller clock output circuit wait release signal internal reset signal power down release signal oscillator control circuit pcon.3, .2 clear 1/4 cpu clock fx: main-system clock fxt: sub-system clock fxx: selected system clock cpu stop signal (idle mode) idle stop fx fxt figure 6 - 1. clock circuit diagram
S3C72I9/p72i9 oscillator circuits 6 - 3 main system oscillator circuits x in x out figure 6 - 2. crystal/ceramic oscillator (fx) x in x out external clock figure 6 - 3. external oscillator (fx) x in x out r figure 6 - 4. rc oscillator (fx) sub system oscillator circuits xt in xt out 32.768 khz figure 6 - 5. crystal/ceramic oscillator (fxt) xt in xt out figure 6 - 6. external oscillator (fxt)
oscillator circuits S3C72I9/p72i9 6 - 4 power control register (pcon) the power control register, pcon, is a 4-bit register that is used to select the cpu clock frequency and to con trol cpu operating and power-down modes. pcon can be addressed di rectly by 4-bit write instructions or indirectly by the instructions idle and stop. fb3h pcon.3 pcon.2 pcon.1 pcon.0 pcon bits 3 and 2 are addressed by the stop and idle instructions, respectively, to engage the idle and stop power-down modes. idle and stop modes can be initiated by these instruction despite the current value of the enable memory bank flag (emb). pcon bits 1 and 0 are used to select a specific system clock frequency. there are two basic choices: ? main system clock (fx) or subsystem clock (fxt); ? divided fx /4, 8, 64 or fxt /4 clock frequency. pcon.1 and pcon.0 settings are also connected with the system clock mode control register, scmod. if scmod.0 = "0" the main system clock is always selected by the pcon.1 and pcon.0 setting; if scmod.0 = "1" the subsystem clock is selected. reset sets pcon register values (and scmod) to logic zero: scmod.3 and scmod.0 select the main sys tem clock (fx) and start clock oscillation; pcon.1 and pcon.0 divide the selected fx frequency by 64, and pcon.3 and pcon.2 enable normal cpu operating mode. table 6 - 1. power control register (pcon) organization pcon bit settings resulting cpu operating mode pcon.3 pcon.2 0 0 normal cpu operating mode 0 1 idle power-down mode 1 0 stop power-down mode pcon bit settings resulting cpu clock frequency pcon.1 pcon.0 if scmod.0 = "0" if scmod.0 = "1" 0 0 fx/64 fxt/4 1 0 fx/8 1 1 fx/4 + + programming tip ? setting the cpu clock to set the cpu clock to 0.95 s at 4.19 mhz: bits emb smb 15 ld a,#3h ld pcon,a
S3C72I9/p72i9 oscillator circuits 6 - 5 instruction cycle times the unit of time that equals one machine cycle varies depending on whether the main system clock (fx) or a subsystem clock (fxt) is used, and on how the oscillator clock signal is divided (by 4, 8, or 64). table 6 - 2 shows corresponding cycle times in microseconds. table 6 - 2. instruction cycle times for cpu clock rates selected cpu clock resulting frequency oscillation source cycle time (sec) fx/64 65.5 khz fx = 4.19 mhz 15.3 fx/8 524.0 khz 1.91 fx/4 1.05 mhz 0.95 fxt/4 8.19 khz fxt = 32.768 khz 122.0
oscillator circuits S3C72I9/p72i9 6 - 6 system clock mode register (scmod) the system clock mode register, scmod, is a 4-bit register that is used to select the cpu clock and to control main and sub- system clock oscillation. the scmod is mapped to the ram address fb7h. the main clock oscillation is stopped by setting scmod.3 when the clock source is subsystem clock and subsystem clock can be stopped by setting scmod.2 when the clock source is main system clock. scmod.0, scmod.3 cannot be simultaneously modified. the subsystem clock is stopped only by setting scmod.2, and pcon which revokes stop mode cannot stop the subsystem clock. the stop of subsystem clock is released by reset when the selected system clock is main system clock or subsystem clock and is released by setting scmod.2 when the selected system clock is main system clock. reset clears all scmod values to logic zero, selecting the main system clock (fx) as the cpu clock and starting clock oscillation. the reset value of the scmod is ?0? scmod.0, scmod.2, and scmod.3 bits can be manipulated by 1-bit write instructions (in other words, scmod.0, scmod.2, and scmod.3 cannot be modified simultaneously by a 4-bit write). bit 1 is always logic zero. fb7h scmod.3 scmod. 2 "0" scmod.0 a subsystem clock (fxt) can be selected as the system clock by manipulating the scmod.3 and scmod.0 bit settings. if scmod.3 = "0" and scmod.0 = "1", the subsystem clock is selected and main system clock oscillation continues. if scmod.3 = "1" and scmod.0 = " 1 ", fxt is selected, but main system clock oscillation stops. even i f you have selected fx as the cpu clock, setting scmod.3 to "1" will stop main system clock oscillation , and malfunction may be occured. to operate safely, main system clock should be stopped by a stop instruction is main system clock mode. table 6-3. system clock mode register (scmod) organization scmod register bit settings resulting clock selection scmod.3 scmod.0 cpu clock source fx oscillation 0 0 fx on 0 1 fxt on 1 1 fxt off scmod.2 sub-oscillation on/off 0 enable sub system clock 1 disable sub system clock note: you can use scmod.2 as follows (ex; after data bank was used, a few minutes have passed): main operation ? sub-operation ? sub-idle (lcd on, after a few minutes later without any external input) ? sub-operation ? main operation ? scmod.2 = 1 ? main stop mode (lcd off).
S3C72I9/p72i9 oscillator circuits 6 - 7 table 6-4 . main/sub oscillation stop mode mode condition method to issue osc stop osc stop release source (2) main oscillation stop mode main oscillator runs. sub oscillator runs (stops). system clock is the main oscillation clock. stop instruction: main oscillator stops. cpu is in idle mode. sub oscillator still runs (stops). interrupt and reset : after releasing stop mode, main oscillation starts and oscillation stabilization time is elapsed. and then the cpu operates. oscillation stabilization time is 1/ {256 x bt clock (fx)}. when scmod.3 is set to ?1? (1), main oscillator stops, halting the cpu operation. sub oscillator still runs (stops). reset : interrupt can?t start the main oscillation. therefore, the cpu operation can never be restarted. main oscillator runs. sub oscillator runs. system clock is the sub oscillation clock. stop instruction (1) : main oscillator stops. cpu is in idle mode. sub oscillator still runs (stops). sub oscillator still runs. bt overflow, interrupt, and reset : after the overflow of basic timer [1/ {256 x bt clock (fxt)}], cpu operation and main oscillation automatically start. when scmod.3 is set to ?1?, main oscillator stops. the cpu, however, would still operate. sub oscillator still runs. set scmod.3 to ?0? or reset sub oscillation stop mode main oscillator runs. sub oscillator runs. system clock is the main oscillation clock. when scmod.2 to ?1?, sub oscillator stops, while main oscillator and the cpu would still operate. set scmod.2 to ?0? or reset main oscillator runs (stops). sub oscillator runs. system clock is the sub oscillation clock. when scmod.2 to ?1?, sub oscillator stops, halting the cpu operation. main oscillator still runs (stops). reset notes : 1. this mode must not be used. 2. oscillation stabilization time by interrupt is 1/(256 x bt clocks). oscillation stabilization time by a reset is 31.3ms at 4.19mhz, main oscillation clock.
oscillator circuits S3C72I9/p72i9 6 - 8 switching the cpu clock together, bit settings in the power control register, pcon, and the system clock mode register, scmod, determine whether a main system or a subsystem clock is selected as the cpu clock, and also how this frequency is to be divided. this makes it possible to switch dynamically between main and subsystem clocks and to modify op erating frequencies. scmod.3 , scmod.2, and scmod.0 select the main system clock (fx) or a subsystem clock (fxt) and start or stop main system and sub system clock oscillation. pcon.1 and pcon.0 control the frequency divider circuit, and divide the selected fx clock by 4, 8, or 64, or fxt clock by 4. note a clock switch operation does not go into effect immediately when you make the scmod and pcon register modifications ? the previously selected clock continues to run for a certain number of machine cycles. for example, you are using the default cpu clock (normal operating mode and a main system clock of fx/64) and you want to switch from the fx clock to a subsystem clock and to stop the main system clock. to do this, you first need to set scmod.0 to "1". this switches the clock from fx to fxt but allows main system clock oscillation to continue. before the switch actually goes into effect, a certain number of machine cycles must elapse. after this time interval, you can then disable main system clock oscillation by setting scmod.3 to "1". this same 'stepped' approach must be taken to switch from a subsystem clock to the main system clock: first, clear scmod.3 to "0" to enable main system clock oscillation. then, after a certain number of machine cycles has elapsed, select the main system clock by clearing all scmod values to logic zero. following a reset , cpu operation starts with the lowest main system clock frequency of 15.3 s at 4.19 mhz after the standard oscillation stabilization interval of 31.3 ms has elapsed. table 6 -5 details the number of machine cycles that must elapse before a cpu clock switch modification goes into effect. table 6-5 . elapsed machine cycles during cpu clock switch after scmod.0 = 0 scmod.0 = 1 before pcon.1 = 0 pcon.0 = 0 pcon.1 = 1 pcon.0 = 0 pcon.1 = 1 pcon.0 = 1 pcon.1 = 0 n/a 1 machine cycle 1 machine cycle n/a pcon.0 = 0 scmod.0 = 0 pcon.1 = 1 8 machine cycles n/a 1 machine cycles n/a pcon.0 = 0 pcon.1 = 1 16 machine cycles 1 machine cycles n/a fx / 4fxt pcon.0 = 1 scmod.0 = 1 n/a n/a 1machine cycles n/a notes: 1. even if oscillation is stopped by setting scmod.3 during main system clock operation, the stop mode is not entered. 2. since the x in input is connected internally to v ss to avoid current leakage due to the crystal oscillator in stop mode, do not set scmod.3 to "1" or do not use stop instruction when an external clock is used as the main system clock. 3. when the system clock is switched to the subsystem clock, it is necessary to disable any interrupts which may occur during the time intervals shown in table 6 -5 . 4. 'n/a' means 'not available'. 5. fx: main-system clock, fxt: sub-system clock. when fx is 4.19 mhz, and fxt is 32.768 khz.
S3C72I9/p72i9 oscillator circuits 6 - 9 + + programming tip ? switching between main system and subsystem clock 1. switch from the main system clock to the subsystem clock: ma2sub bits scmod.0 ; switches to subsystem clock call dly80 ; delay 80 machine cycles bits scmod.3 ; stop the main system clock ret dly80 ld a,#0fh del1 nop nop decs a jr del1 ret 2. switch from the subsystem clock to the main system clock: sub2ma bitr scmod.3 ; start main system clock oscillation call dly80 ; delay 160 machine cycles call dly80 bitr scmod.0 ; switch to main system clock ret
oscillator circuits S3C72I9/p72i9 6 - 10 clock output mode register (clmod) the clock output mode register, clmod, is a 4-bit register that is used to enable or disable clock output to the clo pin and to select the cpu clock source and frequency. clmod is ad dressable by 4-bit write instructions only. fd0h clmod.3 "0" clmod.1 clmod.0 reset clears clmod to logic zero, which automatically selects the cpu clock as the clock source (without initiating clock oscillation), and disables clock output. clmod.3 is the enable/disable clock output control bit; clmod.1 and clmod.0 are used to select one of four possible clock sources and frequencies: normal cpu clock, fxx/8, fxx/16, or fxx/64. table 6 -6 . clock output mode register (clmod) organization clmod bit settings resulting clock output clmod.1 clmod.0 clock source frequency 0 0 cpu clock (fx/4, fx/8, fx/64 , fxt/4 ) 1.05 mhz, 524 khz, 65.5 khz , 8.2 khz 0 1 fxx/8 524 khz 1 0 fxx/16 262 khz 1 1 fxx/64 65.5 khz clmod.3 result of clmod.3 setting 0 disable clock output at the clo pin 1 enable clock output at the clo pin note : frequencies assume that fxx , fx = 4.19 mhz and fxt = 32.768 khz .
S3C72I9/p72i9 oscillator circuits 6 - 11 clock output circuit the clock output circuit, used to output clock pulses to the clo pin, has the following components: ? 4-bit clock output mode register (clmod) ? clock selector ? output latch ? port mode flag ? clo output pin (p2.0) clmod.2 clmod.1 clmod.0 clmod.3 clock selector clocks (fxx/8, fxx/16, fxx/64, cpu clock) 4 p2.0 output latch pm 2 clo figure 6 - 7. clo output pin circuit diagram clock output procedure the procedure for outputting clock pulses to the clo pin may be summarized as follows: 1. disa ble clock output by clearing clmod.3 to logic zero. 2. set the clock output frequency (clmod.1, clmod.0). 3. load a "0" to the output latch of the clo pin (p2.0). 4. set the p2.0 mode flag (pm2.0) to output mode. 5. enable clock output by setting clmod.3 to logic one. + + programming tip ? cpu clock output to the clo pin to output the cpu clock to the clo pin: bits emb smb 15 ld ea,#10h ld pmg1,ea ; p2.0 ? output mode bitr p2.0 ; clear p 2.0 output latch ld a,#9h ld clmod,a
S3C72I9/p72i9 interrupts 7 - 1 7 interrupts overview the S3C72I9 interrupt control circuit has five functional components: ? interrupt enable flags (iex) ? interrupt request flags (irqx) ? interrupt master enable register (ime) ? interrupt priority register (ipr) ? power-down release signal circuit three kinds of interrupts are supported: ? internal interrupts generated by on-chip processes ? external interrupts generated by external peripheral devices ? quasi-interrupts used for edge detection and as clock sources table 7 - 1 . interrupt types and corresponding port pin(s) interrupt type interrupt name corresponding port pins external interrupts int0, int1, int4, intk p1.0, p1.1, p1.3, k0 - k7 internal interrupts intb, intt0, intt1, ints not applicable quasi-interrupts int2 p1.2 intw not applicable
interrupts S3C72I9/p72i9 7 - 2 vectored interrupts interrupt requests may be processed as vectored interrupts in hardware, or they can be generated by program software. a vectored interrupt is generated when the following flags and register settings, corresponding to the specific interrupt (intn) are set to logic one: ? interrupt enable flag (iex) ? interrupt master enable flag (ime) ? interrupt request f lag (irqx) ? interrupt status flags (is0, is1) ? interrupt priority register (ipr) if all conditions are satisfied for the execution of a requested service routine, the start address of the interrupt is loaded into the program counter and the program starts executing the service routine from this address. emb and erb flags for ram memory banks and registers are stored in the vector address area of the rom during interrupt service routines. the flags are stored at the beginning of the program with the vent instruction. the initial flag values determine the vectors for resets and interrupts. enable flag values are saved during the main routine, as well as during service routines. any changes that are made to enable flag values during a service routine are not stored in the vector address. when an interrupt occurs, the emb and the erb flags before the interrupt is initiated are saved along with the pro gram status word (psw), and the emb and the erb flag for the interrupt are fetched from the respective vector address. then, if necessary, you can modify the enable flags during the interrupt service routine. when the interrupt service routine is returned to the main routine by the iret instruction, the original values saved in the stack are restored and the main program continues program execution with these values. software-generated interrupts to generate an interrupt request from software, the program manipulates the appropriate irqx flag. when the interrupt request flag value is set, it is retained until all other conditions for the vectored interrupt have been met, and the service routine can be initiated. multiple interrupts by manipulating the two interrupt status flags (is0 and is1), you can control service routine initialization and thereby process multiple interrupts simultaneously. if more than four interrupts are being processed at one time, you can avoid possible loss of working register data by using the push rr instruction to save register contents to the stack before the service routines are exe cute d in the same register bank. when the routines have executed successfully, you can restore the register con tents from the stack to working memory by using the pop instruction. power-down mode release an interrupt can be used to release power-down mode (stop or idle). interrupts for power-down mode release are initiated by setting the corresponding interrupt enable flag. even if the ime flag is cleared to zero, power-down mode will be released by an interrupt request signal when the interrupt enable flag has been set. in such cases, the interrupt routine will not be executed since ime = "0".
S3C72I9/p72i9 interrupts 7 - 3 no no retain value until iex = 1 retain value until iex = 1 no interrupt is generated (int xx) iex = 1? ime = 1? is1, 0 = 0, 0? is1, 0 = 0, 1? request flag (irqx) 1 generate corresponding vector interrupt and release power-down mode store contents of pc and psw in the stack area; set pc contents to corresponding vector address high-priority interrupt are both interrupt sources of shared vector address used? is1, 0 = 1, 0 retain value until interrupt service routine is completed no irqx flag value remains 1 jump to interrupt start address verify interrupt source and clear irqx with a btstz instruction reset corresponding irqx flag jump to interrupt start address is1, 0 = 0, 1 yes no yes yes yes yes no figure 7 - 1 . interrupt execution flowchart
interrupts S3C72I9/p72i9 7 - 4 ie2 iew ietk iet1 iet0 ies ie1 ie0 ie4 ieb intb ime ipr is1 is0 vector interrupt generator @ = edge detection circuit power-down mode release signal interrupt control unit k0-k7 int2 @ imod0 imod1 int4 int0 int1 intt1 intw ints intt0 @ @ imodk imod2 @ irqb irq4 irq0 irq1 irqs irqt0 irqk irqw irq2 irqt1 figure 7 - 2 . interrupt control circuit diagram
S3C72I9/p72i9 interrupts 7 - 5 multiple interrupts the interrupt controller can service multiple interrupts in two ways: as two-level interrupts, where either all inter - rupt requests or only those of highest priority are serviced, or as multi-level interrupts, when the interrupt service routine for a lower-priority request is accepted during the execution of a higher priority routine. two-level interrupt handling two-level interrupt handling is the standard method for processing multiple interrupts. when the is1 and is0 bits of the psw (fb0h.3 and fb0h.2, respectively) are both logic zero, program execution mode is normal and all interrupt requests are serviced (see figure 7 - 3). whenever an interrupt request is accepted, is1 and is0 are incremented by one and the values are stored in the stack along with the other psw bits. after the interrupt routine has been serviced, the modified is1 and is0 values are automatically restored from the stack by an iret instruction. is0 and is1 can be manipulated directly by 1-bit write instructions, regardless of the current value of the enable memory bank flag (emb). before you can modify an interrupt service flag, however, you must first disable interrupt processing with a di instruction. when is1 = "0" and is0 = "1", all interrupt service routines are inhibited except for the highest priority interrupt currently defined by the interrupt priority register (ipr). high level interrupt generated normal program processing (status 0) set ipr int enable int disable high or low level interrupt processing (status 1) high level interrupt processing (status 2) low or high level interrupt generated figure 7 - 3 . two-level interrupt handling
interrupts S3C72I9/p72i9 7 - 6 multi-level interrupt handling with multi-level interrupt handling, a lower-priority interrupt request can be executed while a high-priority inter rupt is being serviced. this is done by manipulating the interrupt status flags, is0 and is1 (see table 7 - 2). when an interrupt is requested during normal program execution, interrupt status flags is0 and is1 are set to "1" and "0", respectively. this setting allows only highest-priority interrupts to be serviced. when a high-priority request is accepted, both interrupt status flags are then cleared to "0" by software so that a request of any priority level can be serviced. in this way, the high- and low -priority requests can be serviced in parallel (see figure 7 - 4). table 7 - 2 . is1 and is0 bit manipulation for multi-level interrupt handling process status before int effect of isx bit setting after int ack is1 is0 is1 is0 0 0 0 all interrupt requests are serviced. 0 1 1 0 1 only high-priority interrupts as determined by the current settings in the ipr register are serviced. 1 0 2 1 0 no additional interrupt requests will be serviced. ? ? ? 1 1 value undefined ? ? normal program processing (status 0) low or high level interrupt generated int enable low or high level interrupt generated set ipr int disable int disable modify status int enable high level interrupt generated single interrupt status 0 status 0 3-level interrupt status 2 2-level interrupt status 1 status 1 figure 7 - 4 . multi-level interrupt handling
S3C72I9/p72i9 interrupts 7 - 7 interrupt priority register (ipr) the 4-bit interrupt priority register (ipr) is used to control multi-level interrupt handling. its reset value is logic zero. before the ipr can be modified by 4-bit write instructions, all interrupts must first be disabled by a di instruction. fb2h ime ipr.2 ipr.1 ipr.0 by manipulating the ipr settings, you can choose to process all interrupt requests with the same priority level, or you can select one type of interrupt for high-priority processing. a low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-priority interrupt. a high-priority interrupt cannot be interrupted by any other interrupt source. table 7 - 3 . standard interrupt priorities interrupt default priority intb, int4 1 int0 2 int1 3 ints 4 intt0 5 intt1 6 intk 7 the msb of the ipr, the interrupt master enable flag (ime), enables and disables all interrupt processing. even if an interrupt request flag and its corresponding enable flag are set, a service routine cannot be executed until the ime flag is set to logic one. the ime flag can be directly manipulated by ei and di instructions, regardless of the current enable memory bank (emb) value. table 7 - 4 . interrupt priority register settings ipr.2 ipr.1 ipr.0 result of ipr bit setting 0 0 0 normal interrupt handling according to default priority settings (note) 0 0 1 process intb and int4 interrupts at highest priority 0 1 0 process int0 interrupts at highest priority 0 1 1 process int1 interrupts at highest priority 1 0 0 process ints interrupts at highest priority 1 0 1 process intt0 interrupts at highest priority 1 1 0 process intt1 interrupts at highest priority 1 1 1 process intk interrupts at highest priority note : during normal interrupt processing, interrupts are processed in the order in which they occur. if two or more interrupt requests are received simultaneously, the priority level is determined according to the standard interrupt priorities in table 7- 3 (the default priority assigned by hardware when the lower three ipr bits = "0"). in this case, the higher-priority interrupt request is serviced and the other interrupt is inhibited. then, when the high-priority interrupt is returned from its service routine by an iret instruction, the inhibited service routine is started.
interrupts S3C72I9/p72i9 7 - 8 + + programming tip ? setting the int interrupt priority the following instruction sequence sets the int1 interrupt to high priority: bits emb smb 15 di ; ipr.3 (ime) ? 0 ld a,#3h ld ipr,a ei ; ipr.3 (ime) ? 1 external interrupt 0, 1 and 2 mode registers (imod0, imod1 and imod2) the following components are used to process external interrupts at the int0, int1 and int2 pins: ? edge detection circuit ? three mode registers, imod0, imod1 and imod2 the mode registers are used to control the triggering edge of the input signal. imod0, imod1 and imod2 settings let you choose either the rising or falling edge of the incoming signal as the interrupt request trigger. the int4 interrupt is an exception since its input signal generates an interrupt request on both rising and falling edges. since int2 is a qusi-interrupt, the interrupt request flag (irq2) must be cleared by software. fb4h "0" "0" imod0.1 imod0.0 fb5h "0" "0" "0" imod1.0 fdah "0" "0" "0" imod2.0 imod0, imod1 and imod2 are addressable by 4-bit write instructions. reset clears all imod values to logic zero, selecting rising edges as the trigger for incoming interrupt requests. table 7 - 5 . imod0, 1 and 2 register organization imod0 0 0 imod0.1 imod0.0 effect of imod0 settings 0 0 rising edge detection 0 1 falling edge detection 1 0 both rising and falling edge detection 1 1 irq0 flag cannot be set to "1" imod1 imod2 0 0 0 imod1.0 imod2.0 effect of imod1 and imod2 settings 0 rising edge detection 1 falling edge detection
S3C72I9/p72i9 interrupts 7 - 9 external interrupt 0, 1 and 2 mode registers (c ontinued ) 2 edge detection imod0 imod2 irq2 imod1 irq1 irq0 edge detection edge detection p1.0 p1.2 p1.1 int2 int1 int0 figure 7 - 5 . circuit diagram for int0, int1 and int2 pins when modifying the imod registers, it is possible to accidentally set an interrupt request flag. to avoid unwanted interrupts, take these precautions when writing your programs: 1. disable all interrupts with a di instruction. 2. modify the imod register. 3. clear all relevant interrupt request flags. 4. enable the interrupt by setting the appropriate iex flag. 5. enable all interrupts with an ei instructions.
interrupts S3C72I9/p72i9 7 - 10 external key interrupt mode register (imodk) the mode register for external key interrupts at the k0 - k7 pins, imodk, is addressable only by 4-bit write instructions. reset clears all imodk bits to logic zero. fb6h "0" imodk.2 imodk.1 imodk.0 rising or falling edge can be detected by bit imodk.2 settings. if a rising or falling edge is detected at any one of the selected k pin by the imodk register, the irqk flag is set to logic one and a release signal for power-down mode is generated. table 7 - 6 . imodk register bit settings imodk 0 imodk.2 imodk.1 imodk.0 effect of imodk settings 0, 1 0 0 disable key interrupt 0 1 enable edge detection at the k0 - k3 pins 1 0 enable edge detection at the k4 - k7 pins 1 1 enable edge detection at the k0 - k7 pins imodk.2 0 falling edge detection 1 rising edge detection note s : 1. to generate a key interrupt, the selected pins must be configured to input mode. if any one pin of the selected pins is configured to output mode, only falling edge can be detected. 2. to generate a key interrupt, all of the selected pins must be at input high state for falling edge detection, or all of the selected pins must be at input low state for rising edge detection. if any one of them or more is at input low state or input high state, the interrupt may be not occurred at falling edge or rising edge. 3. to generate a key interrupt, first, configure pull-up resistors or external pull-down resistors. and then, select edge detection and pins by setting imodk register.
S3C72I9/p72i9 interrupts 7 - 11 p6.3/k7 p6.2/k6 p6.1/k5 p6.0/k4 p0.3/k3 p0.2/k2 p0.1/k1 p0.0/k0 enable/ disable enable/ disable imodk rising/ falling edge selector irqk figure 7 - 6 . circuit diagram for intk
interrupts S3C72I9/p72i9 7 - 12 + + programming tip ? using intk as a key input interrupt when the key interrupt is used, the selected key interrupt source pin must be set to input: 1. when k0 - k7 are selected (eight pins): bits emb smb 15 ld a,#3h ld imodk,a ; (imodk) ? #3h, k0 - k7 falling edge select ld ea,#00h ld pmg1,ea ; p0 ? input mode ld pmg4,ea ; p6 ? input mode ld ea,#41h ld pumod1,ea ; enable p0 and p6 pull-up resistors 2. when k0 - k3 are selected (four pins): bits emb smb 15 ld a,#1h ld imodk,a ; (imodk) ? #1h, k0 - k3 falling edge select ld ea,#00h ld pmg1,ea ; p0 ? input mode ld ea,#1h ld pumod1,ea ; enable p0 pull-up resistors
S3C72I9/p72i9 interrupts 7 - 13 interrupt flags there are three types of interrupt flags: interrupt request and interrupt enable flags that correspond to each in - terrupt, the interrupt master enable flag, which enables or disables all interrupt processing. interrupt master enable flag (ime) the interrupt master enable flag, ime, enables or disables all interrupt processing. therefore, even when an irqx flag is set and its corresponding iex flag is enabled, the interrupt service routine is not executed until the ime flag is set to logic one. the ime flag is located in the ipr register (ipr.3). it can be directly be manipulated by ei and di instructions, regardless of the current value of the enable memory bank flag (emb). ime ipr.2 ipr.1 ipr.0 effect of bit settings 0 inhibit all interrupts 1 enable all interrupts interrupt enable flags (iex) iex flags, when set to logical one, enable specific interrupt requests to be serviced. when the interrupt request flag is set to logical one, an interrupt will not be serviced until its corresponding iex flag is also enabled. interrupt enable flags can be read, written, or tested directly by 1-bit instructions. iex flags can be addressed directly at their specific ram addresses, despite the current value of the enable memory bank (emb) flag. table 7 - 7 . interrupt enable and interrupt request flag addresses address bit 3 bit 2 bit 1 bit 0 fb8h ie4 irq4 ieb irqb fbah "0" "0" iew irqw fbbh iek irqk iet1 irqt1 fbch "0" "0" iet0 irqt0 fbdh "0" "0" ies irqs fbeh ie1 irq1 ie0 irq0 fbfh "0" "0" ie2 irq2 notes: 1. iex refers to all interrupt enable flags. 2. irqx refers to all interrupt request flags. 3. iex = 0 is interrupt disable mode. 4. iex = 1 is interrupt enable mode.
interrupts S3C72I9/p72i9 7 - 14 interrupt request flags (irqx) interrupt request flags are read/write addressable by 1-bit or 4-bit in structions. irqx flags can be addressed directly at their specific ram addresses, regardless of the current value of the enable memory bank (emb) flag. when a specific irqx flag is set to logic one, the corresponding interrupt request is generated. the flag is then automatically cleared to logic zero when the interrupt has been serviced. exceptions are the watch timer interrupt request flags, irqw, and the external interrupt 2 flag irq2, which must be cleared by software after the interrupt service routine has executed. irqx flags are also used to execute interrupt requests from software. in summary, follow these guidelines for using irqx flags: 1. irqx is set to request an interrupt when an interrupt meets the set condition for interrupt generation. 2. irqx is set to "1" by hardware and then cleared by hardware when the interrupt has been serviced (with the exception of irqw and irq2). 3. when irqx is set to "1" by software, an interrupt is generated. when two interrupts share the same service routine start address, interrupt processing may occur in one of two ways: ? when only one interrupt is enabled, the irqx flag is cleared automatically when the interrupt has been serviced. ? when two interrupts are enabled, the request flag is not automatically cleared so that the user has an opportunity to locate the source of the interrupt request. in this case, the irqx setting must be cleared manually using a btstz instruction. table 7 - 8 . interrupt request flag conditions and priorities interrupt source internal / external pre-condition for irqx flag setting interrupt priority irq flag name intb i reference time interval signal from basic timer 1 irqb int4 e both rising and falling edges detected at int4 1 irq4 int0 e rising or falling edge detected at int0 pin 2 irq0 int1 e rising or falling edge detected at int1 pin 3 irq1 ints i completion signal for serial transmit-and-re - ceive or receive-only operation 4 irqs intt0 i signals for tcnt0 and tref0 registers match 5 irqt0 intt1 i signals for tcnt1 and tref1 registers match 6 irqt1 intk e when a rising or falling edge detected at any one of the k0 - k7 pins 7 irqk int2 e rising or falling edge detected at int2 ? irq2 intw i time interval of 0.5 secs or 3.19 msecs ? irqw
S3C72I9/p72i9 interrupts 7 - 15 + + programming tip ? enabling the intb and int4 interrupts to simultaneously enable intb and int4 interrupts: intb di btstz irqb ; irqb = 1 ? jr int4 ; if no, int4 interrupt; if yes, intb interrupt is processed ? ? ? ei iret ; int4 bitr irq4 ; int4 is processed ? ? ? ei iret
S3C72I9/p72i9 power-down 8 - 1 8 power-down overview the S3C72I9 microcontroller has two power-down modes to reduce power consumption: idle and stop. idle mode is initiated by the idle instruction and stop mode by the instruction stop. (several nop instructions must always follow an idle or stop instruction in a program.) in idle mode, the cpu clock stops while pe ripherals and the oscillation source continue to operate normally. when reset occurs during normal operation or during a power-down mode, a reset operation is initiated and the cpu enters idle mode. when the standard oscillation stabilization time interval (31.3 ms at 4.19 mhz) has elapsed, normal cpu operation resumes. in stop mode, main system clock oscillation is halted (assuming it is currently operating), and peripheral hard - ware components are powered-down. the effect of stop mode on specific peripheral hardware components ? cpu, basic timer, serial i/o, timer/counters 0 and 1, watch timer, and lcd controller ? and on external interrupt requests, is detailed in table 8 - 1. idle or stop modes are terminated either by a reset , or by an interrupt which is enabled by the corresponding interrupt enable flag, iex. when power-down mode is terminated by reset , a normal reset operation is executed. assuming that both the interrupt enable flag and the interrupt request flag are set to "1", power-down mode is released immediately upon entering power-down mode. when an interrupt is used to release power-down mode, the operation differs depending on the value of the interrupt master enable flag (ime): ? if the ime flag = ?0?; if the power down mode release signal is generated, after releasing the power-down mode, program execution starts immediately under the instruction to enter power down mode without execution of interrupt service routine. the interrupt request flag remains set to logic one. ? if the ime flag = "1" ; if the power down mode release signal is generated, after releasing the power down mode, two instructions following the instruction to enter power down mode are executed first and the interrupt service routine is executed, finally program is resumed. however, when the release signal is caused by int2 or intw, the operation is identical to the ime = ?0? condition because int2 and intw are a quasi-interrupt. note do not use stop mode if you are using an external clock source because x in input must be restricted internally to v ss to reduce current leakage.
power-down S3C72I9/p72i9 8 - 2 table 8 - 1 . hardware operation during power-down modes operation stop mode (stop) idle mode (idle) system clock status stop mode can be used only if the main system clock is selected as system clock (cpu clock) idle mode can be used if the main system clock or subsystem clock is selected as system clock (cpu clock) clock oscillator main system clock oscillation stops cpu clock oscillation stops (main and subsystem clock oscillation continues) basic timer basic timer stops basic timer operates (with irqb set at each reference interval) serial i/o interface operates only if external sck input is selected as the serial i/o clock operates if a clock other than the cpu clock is selected as the serial i/o clock timer/counter 0 operates only if tcl0 is selected as the counter clock timer/counter 0 operates timer/counter 1 operates only if tcl1 is selected as the counter clock timer/counter 1 operates watch timer operates only if subsystem clock (fxt) is selected as the counter clock watch timer operates lcd controller operates only if a subsystem clock is se - lected as lcdck lcd controller operates external interrupts into, int1, int2, i nt4, and intk are acknowledged int0, int1, int2, int4 and intk are acknowledged cpu all cpu operations are disabled all cpu operations are disabled mode release signal interrupt request signals are enabled by an interrupt enable flag or by reset input interrupt request signals are enabled by an interrupt enable flag or by reset input
S3C72I9/p72i9 power-down 8 - 3 table 8-2 . system operating mode comparison mode condition stop/idle mode start method current consumption main operating mode main oscillator runs. sub oscillator runs (stops). system clock is the main oscillation clock. ? a main idle mode main oscillator runs. sub oscillator runs (stops). system clock is the main oscillation clock. idle instruction b main stop mode main oscillator runs. sub oscillator runs. system clock is the main oscillation clock. stop instruction d sub operating mode main oscillator is stopped by scmod.3. sub oscillator runs. system clock is the sub oscillation clock. ? c sub ldle mode main oscillator is stopped by scmod.3. sub oscillator runs. system clock is the sub oscillation clock. idle instruction d sub stop mode main oscillator is stopped by scmod.3. sub oscillator runs. system clock is the sub oscillation clock. setting scmod.2 to ?1?: this mode can be released only by an external reset . e main/sub stop mode main oscillator runs. sub oscillator is stopped by scmod.2. system clock is the main oscillation clock. stop instruction: this mode can be released by an interrupt and reset . e note: the current consumption is: a > b > c > d > e.
power-down S3C72I9/p72i9 8 - 4 idle mode timing diagrams oscillator stabilization wait time (31.3 ms/4.19 mhz) reset idle istruction normal mode normal mode normal mode clock signal normal oscillation figure 8 - 1 . timing when idle mode is released by reset reset clock signal normal oscillation mode release signal idle istruction interrupt acknowledge (ime = 1) normal mode idle mode normal mode figure 8 - 2 . timing when idle mode is released by an interrupt
S3C72I9/p72i9 power-down 8 - 5 stop mode timing diagrams oscillator stabilization wait time (31.3 ms/4.19 mhz) reset stop istruction normal mode normal mode clock signal stop mode idle mode oscillation stops oscillation resumes figure 8 - 3 . timing when stop mode is released by reset reset oscillator stabilization wait time (bmod setting) stop istruction normal mode normal mode clock signal stop mode idle mode oscillation stops oscillation resumes mode release signal int ack(ime=1) figure 8 - 4 . timing when stop mode is release d by an interrupt
power-down S3C72I9/p72i9 8 - 6 + + programming tip ? reducing power consumption for key input interrupt processing the following code shows real-time clock and interrupt processing for key inputs to reduce power consumption. in this example, the system clock source is switched from the main system clock to a subsystem clock and the lcd display is turned on: keyclk di call ma2sub ; main system ? clock subsystem clock switch subroutine smb 15 ld ea,#00h ld p4,ea ; all key strobe outputs to low level ld a,#3h ld imodk,a ; select k0 - k7 enable smb 0 bitr irqw bitr irqk bits iew bits iek clks1 call watdis ; execute clock and display changing subroutine btstz irqk jr cidle call sub2ma ; subsystem clock ? main system clock switch subroutine ei ret cidle idle ; engage idle mode nop nop jps clks1
S3C72I9/p72i9 power-down 8 - 7 recommended connections for unused pins to reduce overall power consumption, please configure unused pins according to the guidelines described in table 8 -3 . table 8 -3. unused pin connections for reducing power consumption pin/share pin names recommended connection p0.0/ sck /k0 p0.1/so/k1 p0.2/si/k2 p0.3/buz/k3 input mode: connect to v dd output mode: no connection p1.0/int0 - p1.2/int2 connect to v dd p1.3/int4 connect to v dd p2.0/clo p2.1/lcdck p2.2/lcdsy p3.0/tclo0 p3.1/tclo1 p3.2/tcl0 p3.3/tcl1 p4.0/com8 - p4.3/com11 p5.0/com12 - p5.3/com15 p6.0/seg55/k4 - p6.3/ seg52/k7 p7.0/seg51 - p7.3/seg48 p8.0/seg47 - p8.3/seg44 p9.0/seg43 - p9.3/seg40 input mode: connect to v dd output mode: no connection seg0 - seg39 com0 - com7 no connection v lc1 - v lc5 no connection x t in (note) stop sub-oscillator by setting the scmod.2 to logic ?1? x t out no connection test connect to v ss note: you can stop the sub-oscillator by settin g the scmod.2 to one.
S3C72I9/p72i9 reset reset 9 - 1 9 reset reset overview when a reset signal is input during normal operation or power-down mode, a hardware reset operation is initiated and the cpu enters idle mode. then, when the standard oscillation stabilization interval of 31.3 ms at 4.19 mhz has elapsed, normal system operation resumes. regardless of when the reset occurs ? during normal operating mode or during a power-down mode ? most hardware register values are set to the reset values described in table 9 - 1. the current status of several register values is, however, always retained when a reset occurs during idle or stop mode; if a reset occurs during normal operating mode, their values are undefined. current values that are retained in this case are as follows: ? carry flag ? data memory values ? general-purpose registers e, a, l, h, x, w, z, and y ? serial i/o buffer register (sbuf) oscillator stabilization wait time (31.3 ms/4.19 mhz) normal mode normal mode idle mode reset operation normal mode or power-down mode reset input figure 9 - 1 . timing for oscillation stabilization a fter reset reset hardware register values after reset reset table 9 - 1 gives you detailed information about hardware register values after a reset occurs during power- down mode or during normal operation.
reset S3C72I9/p72i9 9 - 2 table 9 - 1 . har dware register values a fter reset reset hardware component or subcomponent if reset reset occurs during power-down mode if reset reset occurs during normal operation program counter (pc) lower six bits of address 0000h are transferred to pc13 - 8, and the contents of 0001h to pc7 - 0. lower six bits of address 0000h are transferred to pc13 - 8, and the contents of 0001h to pc7 - 0. program status word (psw): carry flag (c) retained undefined skip flag (sc0 - sc2) 0 0 interrupt status flags (is0, is1) 0 0 bank enable flags (emb, erb) bit 6 of address 0000h in program memory is transferred to the erb flag, and bit 7 of the address to the emb flag. bit 6 of address 0000h in program memory is transferred to the erb flag, and bit 7 of the address to the emb flag. stack pointer (sp) undefined undefined data memory (ram): general registers e, a, l, h, x, w, z, y values retained undefined general-purpose registers values retained (note) undefined bank selection registers (smb, srb) 0, 0 0, 0 bsc register (bsc0 - bsc3) 0 0 clocks: power control register (pcon) 0 0 clock output mode register (clmod) 0 0 system clock mode register (scmod) 0 0 interrupts: interrupt request flags (irqx) 0 0 interrupt enable flags (iex) 0 0 interrupt priority flag (ipr) 0 0 interrupt master enable flag (ime) 0 0 int0 mode register (imod0) 0 0 int1 mode register (imod1) 0 0 int2 mode register (imod2) 0 0 intk mode register (imodk) 0 0 note: the values of the 0f8h-0fdh are not retained when a reset signal is input.
S3C72I9/p72i9 reset reset 9 - 3 table 9 - 1 . hardware register values a fter reset reset (continued) hardware component or subcomponent if reset reset occurs during power-down mode if reset reset occurs during normal operation i/o ports: output buffers off off output latches 0 0 port mode flags (pm) 0 0 pull-up resistor mode reg (pumod1/2) 0 0 basic timer: count register (bcnt) undefined undefined mode register (bmod) 0 0 mode register ( wd mod) a5h a5h counter clear flag (wdtcf) 0 0 timer/counter 0 and 1: count registers (tcnt0/1) 0 0 reference registers (tref0/1) ffh, ffffh ffh, ffffh mode registers (tmod0/1) 0 0 output enable flags (toe0/1) 0 0 watch timer: watch timer mode register (wmod) 0 0 lcd driver/controller: lcd mode register (lmod) 0 0 lcd control register (lcon) 0 0 display data memory values retained undefined output buffers off off serial i/o interface: sio mode register (smod) 0 0 sio interface buffer (sbuf) values retained undefined n-channel open-drain mode register pne0/3 0 0
S3C72I9/p72i9 i/o po rts 10- 1 10 i/o ports overview the S3C72I9 has 10 ports. there are total of 4 input pins and 35 configurable i/o pins, for a maximum number of 39 pins. pin addresses for all ports are mapped to bank 15 of the ram. the contents of i/o port pin latches can be read, written, or tested at the corresponding address using bit manipulation instructions. port mode flags port mode flags (pm) are used to configure i/o ports to input or output mode by setting or clearing the corresponding i/o buffer. pull-up resistor mode register (pumod) the pull-up resistor mode registers (pumod1, 2) are used to assign internal pull-up resistors by software to specific ports. when a configurable i/o port pin is used as an output pin, its assigned pull-up resistor is automatically disabled, even though the pin's pull-up is enabled by a corresponding pumod bit setting.
i/o ports S3C72I9/p72i9 10- 2 table 10-1. i/o port overview port i/o pins pin names address function description 0 i/o 4 p0.0-p0.3 ff0h 4-bit i/o port. 1-bit and 4-bit read/write and test is possible. individual pins are software configurable as input or output. individual pins are software configurable as open-drain or push-pull output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. 1 i 4 p1.0-p1.3 ff1h 4-bit input port. 1-bit and 4-bit read and test is possible. 4-bit pull-up resistors are assignable. 2 i/o 3 p2.0-p2.2 ff2h same as port 0 except that port 2 is 3-bit i/o port. 3 i/o 4 p3.0-p3.3 ff3h same as port 0. 4, 5 i/o 8 p4.0-p4.3 p5.0-p5.3 ff4h ff5h 4-bit i/o ports. 1-, 4-bit or 8-bit read/write and test is possible. individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. 6, 7 i/o 8 p6.0-p6.3 p7.0-p7.3 ff6h ff7h same as p4 and p5. 8, 9 i/o 8 p8.0-p8.3 p9.0-p9.3 ff8h ff9h same as p4 and p5. table 10-2. port pin status during instruction execution instruction type example input mode status output mode status 1-bit test 1-bit input 4-bit input 8-bit input btst ldb ld ld p0.1 c,p1.3 a,p7 ea,p4 input or test data at each pin input or test data at output latch 1-bit output bitr p2.3 output latch contents undefined output pin status is modified 4-bit output 8-bit output ld ld p2,a p6,ea transfer accumulator data to the output latch transfer accumulator data to the output pin
S3C72I9/p72i9 i/o po rts 10- 3 port mode flags (pm flags) port mode flags (pm) are used to configure i/o ports to input or output mode by setting or clearing the corresponding i/o buffer. for convenient program reference, pm flags are organized into five groups ? pmg1, pmg2, pmg3, pmg4 and pmg5 as shown in table 10-3. they are ad dressable by 8-bit write instructions only. when a pm flag is "0", the port is set to input mode; when it is "1", the port is enabled for output. reset clears all port mode flags to logical zero, automatically configuring the corresponding i/o ports to input mode. table 10-3. port mode group flags pm group id address bit 3 bit 2 bit 1 bit 0 pmg1 fe6h pm0.3 pm0.2 pm0.1 pm0.0 fe7h "0" pm2.2 pm2.1 pm2.0 pmg2 fe8h pm3.3 pm3.2 pm3.1 pm3.0 fe9h "0" "0" "0" "0" pmg3 feah pm4.3 pm4.2 pm4.1 pm4.0 febh pm5.3 pm5.2 pm5.1 pm5.0 pmg4 fech pm6.3 pm6.2 pm6.1 pm6.0 fedh pm7.3 pm7.2 pm7.1 pm7.0 pmg5 feeh pm8.3 pm8.2 pm8.1 pm8.0 fefh pm9.3 pm9.2 pm9.1 pm9.0 note: if bit = "0", the corresponding i/o pin is set to input mode. if bit = "1", the pin is set to output mode: pm0.0 for p0.0, pm0.1 for p0.1, etc,. all flags are cleared to "0" following reset . + + programming tip ? configuring i/o ports to input or output configure ports 0 and 2 as an output port: bits emb smb 15 ld ea,#7fh ld pmg1,ea ; p0 and p2 ? output
i/o ports S3C72I9/p72i9 10- 4 pull-up resistor mode register (pumod) the pull-up resistor mode registers (pumod1 and pumod2) are used to assign internal pull-up resistors by soft - ware to specific ports. when a configurable i/o port pin is used as an output pin, its assigned pull-up resistor is automatically disabled, even though the pin's pull-up is enabled by a corresponding pumod bit setting. pumod1 is addressable by 8-bit write instructions only, and pumod2 by 4-bit write instruction only. reset clears pumod register values to logic zero, automatically disconnecting all software-assignable port pull-up resis tors. table 10-4. pull-up resistor mode register (pumod) organization pumod id address bit 3 bit 2 bit 1 bit 0 pumod1 fdch pur3 pur2 pur1 pur0 fddh pur7 pur6 pur5 pur4 pumod2 fdeh "0" "0" pur9 pur8 note: when bit = "1", a pull-up resistor is assigned to the corresponding i/o port: pur3 for port 3, pur2 for port 2, and so on. + + programming tip ? enabling and disabling i/o port pull-up resistors p6 and p7 enable pull-up resistors. bits emb smb 15 ld ea,#0c0h ld pumod1,ea ; p6 and p7 enable n-channel open-drain mode register (pne) the n-channel, open-drain mode register (pne) is used to configure ports 0, 2 and 3 to n-channel, open-drain or as push-pull outputs. when a bit in the pne register is set to "1", the corresponding output pin is configured to n- channel, open-drain; when set to "0", the output pin is configured to push-pull. the pne register consists of an 8- bit register and a 4-bit register; pne0 can be addressed by 8-bit write instructions only and pne3 by 4-bit write instructions only. fd6h pne0.3 pne0.2 pne0.1 pne0.0 pne1 fd7h pne2.3 pne2.2 pne2.1 pne2.0 fd8h pne3.3 pne3.2 pne3.1 pne3.0 pne2
S3C72I9/p72i9 i/o po rts 10- 5 port 0 circuit diagram cmos push-pull, n-channel open-drain output latch mux type b type b buz sck so 1, 4 1, 4 type b type b p0.0/ sck p0.1/so p0.2/si p0.3/buz v dd when a port pin serves as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings in the pull-up resistor mode register (pumod). note: pm0.2 si pm0.0 sck pur0 pur0 pur0 pur0 pm0.0 pm0.1 pm0.2 pm0.3 output data input data pm0.x x=0-3 type b v dd p-ch n-ch pne0.x figure 10-1. port 0 circuit diagram
i/o ports S3C72I9/p72i9 10- 6 port 1 circuit diagram v dd p1.0/int0 p1.1/int1 p1.2/int2 p1.3/int4 int0 int4 int1 int2 pumod.1 figure 10-2. port 1 circuit diagram
S3C72I9/p72i9 i/o po rts 10- 7 port 2 circuit diagram cmos push-pull, n-channel open-drain output latch mux type b lcdsy 1, 4 1, 4 type b type b when a port pin serves as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings in the pull-up resistor-mode register (pumod). note: p2.0/clo p2.1/lcdck p2.2/lcdsy output data input data pm2.x x=0-2 type b v dd p-ch n-ch pne2.x pm2.0 pm2.1 pm2.2 pur2 pur2 pur2 v dd clo lcdck pm2.2 pm2.1 pm2.0 figure 10-3. port 2 circuit diagram
i/o ports S3C72I9/p72i9 10- 8 port 3 circuit diagram cmos push-pull, n-channel open-drain output latch mux type b type b tclo0 tclo1 1, 4 1, 4 type b type b p3.0/tclo0 p3.1/tclo1 p3.2/tcl0 p3.3/tcl1 v dd when a port pin serves as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings in the pull-up resistor-mode register (pumod). note: pm3.0 pur3 pur3 pur3 pur3 pm3.0 pm3.1 pm3.2 pm3.3 pm3.1 tcl1 tcl0 output data input data pm3.x x=0-3 type b v dd p-ch n-ch pne3.x figure 10-4. port 3 circuit diagram
S3C72I9/p72i9 i/o po rts 10- 9 port 4, 5, 6, 7, 8, 9 circuit diagram cmos push-pull, n-channel open-drain output latch mux 1, 4, 8 1, 4, 8 v dd purx purx purx purx pmx.0 pmx.1 pmx.2 pmx.3 when a port pin serves as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings in the pull-up resistor-mode register (pumod). port 6 is a schmitt trigger input. note: pmx.1 pmx.2 pmx.3 pmx.0 x = port number (4, 5, 6, 7, 8, 9) px.0 px.1 px.2 px.3 figure 10-5. ports 4, 5, 6, 7, 8, and 9 circuit diagram
S3C72I9/p72i9 timers and timer/counters 11 - 1 11 timers and timer/counters overview the S3C72I9 microcontroller has four timer and timer/counter modules: ? 8-bit basic timer (bt) ? 8-bit timer/counter (tc0) ? 16-bit timer/counter (tc1) ? w atch timer (wt) the 8-bit basic timer (bt) is the microcontroller's main interval timer and watch-dog timer . it generates an interrupt request at a fixed time interval when the appropriate modification is made to its mode register. the basic timer is also used to determine clock oscillation stabilization time when stop mode is released by an interrupt and after a reset . the 8-bit timer/counter (tc0) and the 16-bit timer/counter (tc1) are programmable timer/counters that are used primarily for event counting and for clock frequency modification and output. in addition, tc0 generates a clock signal that can be used by the serial i/o interface. the watch timer (wt) module consists of an 8-bit watch timer mode register, a clock selector, and a frequency divider circuit. watch timer functions include real-time and watch-time measurement, main and subsystem clock interval timing, buzzer output generation. it also generates a clock signal for the lcd controller.
timers and timer/counters S3C72I9/p72i9 11 - 2 basic timer (bt) overview the 8-bit basic timer (bt) has six functional components: ? clock selector logic ? 4-bit mode register (bmod) ? 8-bit counter register (bcnt) ? 8-bit watchdog timer mode register (wdmod) ? watchdog timer counter clear flag (wdtcf) the basic timer generates interrupt requests at precise intervals, based on the frequency of the system clock. you can use the basic timer as a "watchdog" timer for monitoring system events or use bt output to stabilize clock oscillation when stop mode is released by an interrupt and following reset . bit settings in the basic timer mode register bmod turns the bt module on and off, selects the input clock frequency, and controls interrupt or stabilization intervals. interval timer function the basic timer's primary function is to measure elapsed time intervals. the standard time interval is equal to 256 basic timer clock pulses. to restart the basic timer, one bit setting is required: bit 3 of the mode register bmod should be set to logic one. the input clock frequency and the interrupt and stabilization interval are selected by loading the appropriate bit values to bmod.2-bmod.0. the 8-bit counter register, bcnt, is incremented each time a clock signal is detected that corresponds to the frequency selected by bmod. bcnt continues incrementing as it counts bt clocks until an overflow occurs ( 3 255). an overflow causes the bt interrupt request flag (irqb) to be set to logic one to signal that the designated time interval has elapsed. an interrupt request is than generated, bcnt is cleared to logic zero, and counting continues from 00h. watchdog timer function the basic timer can also be used as a "watchdog" timer to signal the occurrence of system or program operation error. for this purpose, instruction that clear the watchdog timer (bits wdtcf) should be executed at proper points in a program within given period. if an instruction that clears the watchdog timer is not executed within the given period and the watchdog timer overflows, reset signal is generated and the system restarts with reset status. an operation of watchdog timer is as follows: ? write some values (except #5ah) to watchdog timer mode register, wdmod. ? if wdcnt overflows, system reset is generated.
S3C72I9/p72i9 timers and timer/counters 11 - 3 oscillation stabilization interval control bits 2-0 of the bmod register are used to select the input clock frequency for the basic timer. this setting also determines the time interval (also referred to as ?wait time?) required to stabilize clock signal oscillation when stop mode is released by an interrupt. when a reset signal is inputted, the standard stabilization interval for system clock oscillation following the reset is 31.3 ms at 4.19 mhz. table 11-1. basic timer register overview register name type description size ram address addressing mode reset value bmod control controls the clock frequency (mode) of the basic timer; also, the oscillation stabilization interval after stop mode release or reset 4-bit f85h 4-bit write-only; bmod.3: 1-bit writeable ?0? bcnt counter counts clock pulses matching the bmod frequency setting 8-bit f86h-f87h 8-bit read-only u (note) wdmod control controls watchdog timer operation. 8-bit f98h-f99h 8-bit write-only a5h wdtcf control clears the watchdog timer?s counter. 1-bit f9ah.3 1-, 4-bit write ?0? note: 'u' means the value is undetermined after a reset .
timers and timer/counters S3C72I9/p72i9 11 - 4 wait means stabilization time after reset or stabilization time after stop mode release. the reset signal can be generated if the wdmod is toggled for 8 times where "toggle" means change from 5ah to other value and vice versa. when the watchdog timer is enabled or the 3-bit counter of the watchdog timer is cleared to "0", the bcnt value is not clearedbut increased continuously. as a result, the 3-bit counter of the watchdog timer (wdcnt) cna be increased by 1. for example, when the bmod value is x000b and the watchdog timer is enabled, the watchdog timer interval time is from 2 3 x 2 12 x 2 8 /fxx to (2 3 - 1) x 2 12 x 2 8 /fxx. notes: 1. 2. 3. bmod.3 bmod.2 bmod.1 bmod.0 bits instruction overflow clear bcnt "clear" signal 1 pulse period = bt input clock 2 8 (1/2 duty) interrupt request clear irqb cpu clock start signal (power-down release) wait (note) 3-bit counter clear overflow reset bits instruction reset wdtcf clock selector wdcnt wdmod reset signal generation delay clear stop 8 8 bcnt irqb 1-bit r/w clock input 4 figure 11-1. basic timer circuit diagram
S3C72I9/p72i9 timers and timer/counters 11 - 5 basic timer mode register (bmod) the basic timer mode register, bmod, is a 4-bit write-only register. bit 3, the basic timer start control bit, is also 1-bit addressable. all bmod values are set to logic zero following reset and interrupt request signal generation is set to the longest interval. (bt counter operation cannot be stopped.) bmod settings have the following effects: ? restart the basic timer; ? control the frequency of clock signal input to the basic timer; ? determine time interval required for clock osci llation to stabilize following the release of stop mode by an interrupt. by loading different values into the bmod register, you can dynamically modify the basic timer clock frequency during program execution. four bt frequencies, ranging from fxx/2 12 to fxx/2 5 , are selectable. since bmod's reset value is logic zero, the default clock frequency setting is fxx/2 12 . the most significant bit of the bmod register, bmod.3, is used to restart the basic timer. when bmod.3 is set to logic one by a 1-bit write instruction, the contents of the bt counter register (bcnt) and the bt interrupt request flag (irqb) are both cleared to logic zero, and timer operation restarts. the combination of bit settings in the remaining three registers ? bmod.2, bmod.1, and bmod.0 ? determine the clock input frequency and oscillation stabilization interval. table 11-2. basic timer mode register (bmod) organization bmod.3 basic timer start control bit 1 start basic timer; clear irqb, bcnt, and bmod.3 to "0" bmod.2 bmod.1 bmod.0 basic timer input clock interrupt interval time (wait time) 0 0 0 fxx/2 12 (1.02 khz) 2 20 /fxx (250 ms) 0 1 1 fxx/2 9 (8.18 khz) 2 17 /fxx (31.3 ms) 1 0 1 fxx/2 7 (32.7 khz) 2 15 /fxx (7.82 ms) 1 1 1 fxx/2 5 (131 khz) 2 13 /fxx (1.95 ms) notes: 1. clock frequencies and interrupt interval time assume a system oscillator clock frequency (fxx) of 4.19 mhz. 2. fxx = selected system clock frequency. 3. wait time is the time required t o stabilize clock signal oscillation after stop mode is released. the data in the table column "interrupt interval time" can also be interpreted as "oscillation stabilization." 4. the standard stabilization time for system clock oscillation following a reset is 31.3 ms at 4.19 mhz.
timers and timer/counters S3C72I9/p72i9 11 - 6 basic timer counter (bcnt) bcnt is an 8-bit counter for the basic timer. it can be addressed by 8-bit read instructions. reset leaves the bcnt counter value undetermined. bcnt is automatically cleared to logic zero whenever the bmod register control bit (bmod.3) is set to "1" to restart the basic timer. it is incremented each time a clock pulse of the frequency determined by the current bmod bit settings is detected. when bcnt has incrementing to hexadecimal ?ffh? ( 3 255 clock pulses), it is cleared to ?00h? and an overflow is generated. the overflow causes the interrupt request flag, irqb, to be set to logic one. when the interrupt request is generated, bcnt immediately resumes counting incoming clock signals. note always execute a bcnt read operation twice to eliminate the possibility of reading unstable data while the counter is incrementing. if, after two consecutive reads, the bcnt values match, you can select the latter value as valid data. until the results of the consecutive reads match, however, the read operation must be repeated until the validation condition is met. basic timer operation sequence the basic timer's sequence of operations may be summarized as follows: 1. set bmod.3 to logic one to restart the basic timer. 2. bcnt is then incremented by one after each clock pulse corresponding to bmod selection. 3. bcnt overflows if bcnt 3 255 (bcnt = ffh). 4. when an overflow occurs, the irqb flag is set by hardware to logic one. 5. the interrupt request is generated. 6. bcnt is then cleared by hardware to logic zero. 7. basic timer resumes counting clock pulses.
S3C72I9/p72i9 timers and timer/counters 11 - 7 + + programming tip ? using the basic timer 1. to read the basic timer count register (bcnt): bits emb smb 15 bcntr ld ea,bcnt ld yz,ea ld ea,bcnt cpse ea,yz jr bcntr 2. when stop mode is released by an interrupt, set the oscillation stabilization interval to 31.3 ms: bits emb smb 15 ld a,#0bh ld bmod,a ; wait time is 31.3 ms nop stop ; set stop power-down mode nop nop nop cpu operation stop instruction stop mode is released by interrupt normal operating mode stop mode idle mode normal operating mode (31.3 ms) 3. to set the basic timer interrupt interval time to 1.95 ms (at 4.19 mhz): bits emb smb 15 ld a,#0fh ld bmod,a ei bits ieb ; basic timer interrupt enable flag is set to "1" 4. clear bcnt and the irqb flag and restart the basic timer: bits emb smb 15 bits bmod.3
timers and timer/counters S3C72I9/p72i9 11 - 8 watchdog timer mode register (wdmod) the watchdog timer mode register, wdmod, is a 8-bit write-only register. wdmod register controls to enable or disable the watchdog function. wdmod values are set to logic ?a5h? following reset and this value enables the watchdog timer. watchdog timer is set to the longest interval because bt overflow signal is generated with the longest interval. wdmod watchdog timer enable/disable control 5ah disable watchdog timer function any other value enable watchdog timer function watchdog timer counter (wdcnt) the watchdog timer counter, wdcnt, is a 3-bit counter. wdcnt is automatically cleared to logic zero, and restarts whenever the wdtcf register control bit is set to ?1?. reset , stop, and wait signal clears the wdcnt to logic zero also. wdcnt increments each time a clock pulse of the overflow frequency determined by the current bmod bit setting is generated. when wdcnt has incremented to hexadecimal ?07h?, it is cleared to ?00h? and an overflow is generated. the overflow causes the system reset . when the interrupt request is generated, bcnt immediately resumes counting incoming clock signals. watchdog timer counter clear flag (wdtcf) the watchdog timer counter clear flag, wdtcf, is a 1-bit write instruction. when wdtcf is set to one, it clears the wdcnt to zero and restarts the wdcnt. wdtcf register bits 2-0 are always logic zero. table 11 - 3. watchdog timer interval time bmod bt input clock wdt interval time (3) x000b fxx/2 12 2 3 2 12 2 8 /fxx - (2 3 -1) 2 12 2 8 /fxx 1.75-2.0 sec x011b fxx/2 9 2 3 2 9 2 8 /fxx - (2 3 -1) 2 9 2 8 /fxx 218.7-250 ms x101b fxx/2 7 2 3 2 7 2 8 /fxx - (2 3 -1) 2 7 2 8 /fxx 54.6-62.5ms x111b fxx/2 5 2 3 2 5 2 8 /fxx - (2 3 -1) 2 5 2 8 /fxx 13.6-15.6 ms notes: 1. clock frequencies assume a system oscillator clock frequency (fx) of 4.19 mhz 2. fxx = system clock frequency. 3. when the watchdog timer is enabled or the 3-bit counter of the watchdog timer is cleared to ?0?, the bcnt value is not cleared but increased continuously. as a result, the 3-bit counter of the watchdog timer (wdcnt) can be increased by 1. for example, when the bmod value is x000b and the watchdog timer is enabled, the watchdog timer interval time is from 2 3 2 12 2 8 /fxx to (2 3 -1) 2 12 2 8 /fxx.
S3C72I9/p72i9 timers and timer/counters 11 - 9 + + programming tip ? using the watchdog timer reset di ld ea,#00h ld sp,ea ld a,#0dh ; wdcnt input clock is 7.82 ms ld bmod,a main bits wdtcf ; main routine operation period must be shorter than ; watchdog-timer?s period jp main
timers and timer/counters S3C72I9/p72i9 11 - 10 8-bit timer/counter 0 (tc0) overview timer/counter 0 (tc0) is used to count system 'events' by identifying the transition (high-to-low or low-to-high) of incoming square wave signals. to indicate that an event has occurred, or that a specified time interval has elapsed, tc0 generates an interrupt request. by counting signal transitions and comparing the current counter value with the reference register value, tc0 can be used to measure specific time intervals. tc0 has a reloadable counter that consists of two parts: an 8-bit reference register (tref0) into which you write the counter reference value, and an 8-bit counter register (tcnt0) whose value is automatically incremented by counter logic. an 8-bit mode register, tmod0, is used to activate the timer/counter and to select the basic clock frequency to be used for timer/counter operations. to dynamically modify the basic frequency, new values can be loaded into the tmod0 register during program execution. tc0 function summary 8-bit programmable timer generates interrupts at specific time intervals based on the selected clock fre - quency. external event counter counts various system "events" based on edge detection of external clock sig - nals at the tc0 input pin, tcl0. to start the event counting operation, tmod0.2 is set to "1" and tmod0.6 is cleared to "0". arbitrary frequency output outputs selectable clock frequencies to the tc0 output pin, tclo0. external signal divider divides the frequency of an incoming external clock signal according to a modi fiable reference value (tref0), and outputs the modified frequency to the tclo0 pin. serial i/o clock source outputs a modifiable clock signal for use as the sck clock source.
S3C72I9/p72i9 timers and timer/counters 11 - 11 tc0 component summary mode register (tmod0) activates the timer/counter and selects the internal clock frequency or the external clock source at the tcl0 pin. reference register (tref0) stores the reference value for the desired number of clock pulses between in - terrupt requests. counter register (tcnt0) counts internal or external clock pulses based on the bit settings in tmod0 and tref0. clock selector circuit together with the mode register (tmod0), lets you select one of four internal clock frequencies or an external clock. 8-bit comparator determines when to generate an interrupt by comparing the current value of the counter register (tcnt0) with the reference value previously programmed into the reference register (tref0). output latch (tol0) where a clock pulse is stored pending output to the serial i/o circuit or to the tc0 output pin, tclo0. when the contents of the tcnt0 and tref0 registers coincide, the timer/counter interrupt request flag (irqt0) is set to "1", the status of tol0 is in verted, and an interrupt is generated. output enable flag (toe0) must be set to logic one before the contents of the tol0 latch can be output to tclo0. interrupt request flag (irqt0) cleared when tc0 operation starts and the tc0 interrupt service routine is executed and set to 1 whenever the counter value and reference value coincide. interrupt enable flag (iet0) must be set to logic one before the interrupt requests generated by timer/counter 0 can be processed. table 11 -4. tc0 register overview register name type description size ram address addressing mode reset value tmod0 control controls tc0 enable/disable (bit 2); clears and resumes counting operation (bit 3); sets input clock and clock frequency (bits 6 - 4) 8-bit f90h - f91h 8-bit write - only; (tmod0.3 is also 1 -bit writeable) "0" tcnt0 counter counts clock pulses matching the tmod0 frequency setting 8-bit f94h - f95h 8-bit read-only "0" tref0 reference stores reference value for the timer/counter 0 interval setting 8-bit f96h - f97h 8-bit write-only ffh toe0 flag controls timer/counter 0 output to the tclo0 pin 1-bit f92h.2 1 /4 -bit read/ write "0"
timers and timer/counters S3C72I9/p72i9 11 - 12 clear set clear inverted clocks (fxx/2 10 , fxx/2 6 , fxx/2 4 , fxx) tcl0 clear serial i/o clock selector tcnt0 tref0 8 8 8-bit comparator irqt0 tol0 p3.0 latch toe0 pm3.0 tmod0.7 tmod0.6 tmod0.5 tmod0.4 tmod0.3 tmod0.2 tmod0.1 tmod0.0 8 tclo0 figure 11 - 2 . tc0 circuit diagram tc0 enable/disable procedure enable timer/counter 0 ? set tmod0.2 to logic one . ? set the tc0 interrupt enable flag iet0 to logic one . ? set tmod0.3 to logic one . tcnt0, irqt0, and tol0 are cleared to logic zero, and timer/counter operation starts. disable timer/counter 0 ? set tmod0.2 to logic zero . clock signal input to the counter register tcnt0 is halted. the current tcnt0 value is retained and can be read if necessary.
S3C72I9/p72i9 timers and timer/counters 11 - 13 tc0 programmable timer/counter function timer/counter 0 can be programmed to generate interrupt requests at various intervals based on the selected system clock frequency. its 8-bit tc0 mode register tmod0 is used to activate the timer/counter and to select the clock frequency. the reference register tref0 stores the value for the number of clock pulses to be generated between interrupt requests. the counter register, tcnt0, counts the incoming clock pulses, which are compared to the tref0 value as tcnt0 is incremented. when there is a match (tref0 = tcnt0), an interrupt request is generated. to program timer/counter 0 to generate interrupt requests at specific intervals, choose one of four internal clock frequencies (divisions of the system clock, fxx) and load a counter reference value into the tref0 register. tcnt0 is incremented each time an internal counter pulse is detected with the reference clock frequency specified by tmod0.4 - tmod0.6 settings. to generate an interrupt request, the tc0 interrupt request flag (irqt0) is set to logic one, the status of tol0 is inverted, and the interrupt is generated. the content of tcnt0 is then cleared to 00h and tc0 continues counting. the interrupt request mechanism for tc0 includes an interrupt enable flag (iet0) and an interrupt request flag (irqt0). tc0 operation sequence the general sequence of operations for using tc0 can be summarized as follows: 1. set tmod0.2 to "1" to enable tc0. 2. set tmod0.6 to "1" to enable the system clock (fxx) input. 3. set tmod0.5 and tmod0.4 bits to desired internal frequency (fxx/2 n ). 4. load a value to tref0 to specify the interval between interrupt requests. 5. set the tc0 interrupt enable flag (iet0) to "1". 6. set tmod0.3 bit to "1" to clear tcnt0, irqt0, and tol0, and start counting. 7. tcnt0 increments with each i nternal clock pulse. 8. when the comparator shows tcnt0 = tref0, the irqt0 flag is set to "1" and an interrupt request is generated. 9. output latch (tol0) logic toggles high or low. 10. tcnt0 is cleared to 00h and counting resumes. 11. programmable timer/counter operation continues until tmod0.2 is cleared to "0".
timers and timer/counters S3C72I9/p72i9 11 - 14 tc0 event counter function timer/counter 0 can monitor or detect system 'events' by using the external clock input at the tcl0 pin as the counter source. the tc0 mode register selects rising or falling edge detection for incoming clock signals. the counter register tcnt0 is incremented each time the selected state transition of the external clock signal occurs. with the exception of the different tmod0.4 - tmod0.6 settings, the operation sequence for tc0's event counter function is identical to its programmable timer/counter function. to activate the tc0 event counter function, ? set tmod0.2 to "1" to enable tc0 . ? clear tmod0.6 to "0" to select the externa l clock source at the tcl0 pin . ? select tcl0 edge detection for rising or falling signal edges by loading the appropriate values to tmod0.5 and tmod0.4. ? p3.2 must be set to input mode. table 11 -5. tmod0 settings for tcl0 edge detection tmod0.5 tmod0.4 tcl0 edge detection 0 0 rising edges 0 1 falling edges
S3C72I9/p72i9 timers and timer/counters 11 - 15 tc0 clock frequency output using timer/counter 0, a modifiable clock frequency can be output to the tc0 clock output pin, tclo0. to select the clock frequency, load the appropriate values to the tc0 mode register, tmod0. the clock interval is selected by loading the desired reference value into the reference register tref0. to enable the output to the tclo0 pin, the following conditions must be met: ? tc0 output enable flag toe0 must be set to "1" . ? i/o mode flag for p3.0 (pm3.0) must be set to output mode ("1") . ? output latch value for p3.0 must be set to "0" . in summary, the operational sequence required to output a tc0-generated clock signal to the tclo0 pin is as follows: 1. load a reference value to tref0. 2. set the internal clock frequency in tmod0. 3. initiate tc0 clock output to tclo0 (tmod0.2 = "1"). 4. set p3.0 mode flag (pm3.0) to "1". 5. set p3.0 output latch to "0". 6. set toe0 flag to "1". each time tcnt0 overflows and an interrupt request is generated, the state of the output latch tol0 is in verted and the tc0-generated clock signal is output to the tclo0 pin. + + programming tip ? tc0 signal output to the tclo0 pin output a 30 ms pulse width signal to the tclo0 pin: bits emb smb 15 ld ea,#79h ld tref0,ea ld ea,#4ch ld tmod0,ea ld ea,#01h ld pmg2,ea ; p3.0 ? output mode bitr p3.0 ; p3.0 clear bits toe0
timers and timer/counters S3C72I9/p72i9 11 - 16 tc0 serial i/o clock generation timer/counter 0 can supply a clock signal to the clock selector circuit of the serial i/o interface for data shifter and clock counter operations. (these internal sio operations are controlled in turn by the sio mode register, smod). this clock generation function enables you to adjust data transmission rates across the serial interface. use tmod0 and tref0 register settings to select the frequency and interval of the tc0 clock signals to be used as sck input to the serial interface. the generated clock signal is then sent directly to the serial i/o clock selector circuit (the toe0 flag may be disabled). tc0 external input signal divider by selecting an external clock source and loading a reference value into the tc0 reference register, tref0, you can divide the incoming clock signal by the tref0 value and then output this modified clock frequency to the tclo0 pin. the sequence of operations used to divide external clock input can be summarized as follows: 1. load a signal divider value to the tref0 register. 2. clear tmod0.6 to "0" to enable external clock input at the tcl0 pin. 3. se t tmod0.5 and tmod0.4 to desired tcl0 signal edge detection. 4. set port 3.0 mode flag (pm3.0) to output ("1"). 5. set p3.0 output latch to "0". 6. set toe0 flag to "1" to enable output of the divided frequency to the tclo0 pin . + + programming tip ? external tcl0 clock output to the tclo0 pin output external tcl0 clock pulse to the tclo0 pin (divided by four): external (tcl0) clock pulse tclo0 output pulse bits emb smb 15 ld ea,#01h ld tref0,ea ld ea,#0ch ld tmod0,ea l d ea,#01h ld pmg2,ea ; p3.0 ? output mode bitr p3.0 ; p3.0 clear bits toe0
S3C72I9/p72i9 timers and timer/counters 11 - 17 tc0 mode register (tmod0) tmod0 is the 8-bit mode control register for timer/counter 0. it is addressable by 8-bit write instructions. one bit, tmod0.3, is also 1-bit writeable. reset clears all tmod0 bits to logic zero and disables tc0 operations. f90h tmod0.3 tmod0.2 "0" "0" f91h "0" tmod0.6 tmod0.5 tmod0.4 tmod0.2 is the enable/disable bit for timer/counter 0. when tmod0.3 is set to "1", the contents of tcnt0, irqt0, and tol0 are cleared, counting starts from 00h, and tmod0.3 is automatically reset to "0" for normal tc0 operation. when tc0 operation stops (tmod0.2 = "0"), the contents of the tc0 counter register tcnt0 are retained until tc0 is re-enabled. the tmod0.6, tmod0.5, and tmod0.4 bit settings are used together to select the tc0 clock source. this selection involves two variables: ? synchronization of timer/counter operations with either the rising edge or the falling edge of t he clock sig nal input at the tcl0 pin, and ? selection of one of four frequencies, based on division of the incoming system clock frequency, for use in internal tc0 operation. table 11 -6. tc0 mode register (tmod0) organization bit name setting resulting tc0 function address tmod0.7 0 always logic zero f91h tmod0.6 0,1 specify input clock edge and internal frequency tmod0.5 tmod0.4 tmod0.3 1 clear tcnt0, irqt0, and tol0 and resume counting immedi ately (this bit is automatically cleared to logic zero immediately after counting resumes.) f90h tmod0.2 0 disable timer/counter 0; retain tcnt0 contents 1 enable timer/counter 0 tmod0.1 0 always logic zero tmod0.0 0 always logic zero
timers and timer/counters S3C72I9/p72i9 11 - 18 table 11 -7. tmod0.6, tmod0.5, and tmod0.4 bit settings tmod0.6 tmod0.5 tmod0.4 resulting counter source and clock frequency 0 0 0 external clock input (tcl0) on rising edges 0 0 1 external clock input (tcl0) on falling edges 1 0 0 fxx/2 10 (4.09 khz) 1 0 1 fxx /2 6 (65.5 khz) 1 1 0 fxx/2 4 (262 khz) 1 1 1 fxx ( 4.19 mhz ) note : 'fxx' = selected system clock of 4.19 mhz. + + programming tip ? restarting tc0 counting operation 1. set tc0 timer interval to 4.09 khz: bits emb smb 15 ld ea,#4ch ld tmod0,ea ei bits iet0 2. clear tcnt0, irqt0, and tol0 and restart tc0 counting operation: bits emb smb 15 bits tm od0.3
S3C72I9/p72i9 timers and timer/counters 11 - 19 tc0 counter register (tcnt0) the 8-bit counter register for timer/counter 0, tcnt0, is read-only and can be addressed by 8-bit ram control instructions. reset sets all tcnt0 register values to logic zero (00h). whenever tmod0.3 is enabled, tcnt0 is cleared to logic zero and counting resumes. the tcnt0 register value is incremented each time an incoming clock signal is detected that matches the signal edge and frequency setting of the tmod0 register (specifically, tmod0.6, tmod0.5, and tmod0.4). each time tcnt0 is incremented, the new value is compared to the reference value stored in the tc0 refer-ence buffer, tref0. when tcnt0 = tref0, an overflow occurs in the tcnt0 register, the interrupt request flag, irqt0, is set to logic one, and an interrupt request is generated to indicate that the specified timer/counter interval has elapsed. reference value = n 0 n ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ n count clock tref0 tcnt0 ~ ~ interval time tol0 timer start instruction (tmod0.3 is set) irqt0 set irqt0 set 1 2 n-1 0 1 2 n-1 0 1 2 3 match match ~ ~ figure 11 - 3 . tc0 timing diagram
timers and timer/counters S3C72I9/p72i9 11 - 20 tc0 reference register (tref0) the tc0 reference register tref0 is an 8-bit write-only register. it is addressable by 8-bit ram control instructions. reset initializes the tref0 value to 'ffh'. tref0 is used to store a reference value to be compared to the incrementing tcnt0 register in order to iden tify an elapsed time interval. reference values will differ depending upon the specific function that tc0 is being used to perform ? as a programmable timer/counter, event counter, clock signal divider, or arbitrary frequency output source. during timer/counter operation, the value loaded into the reference register is compared to the tcnt0 value. when tcnt0 = tref0, the tc0 output latch (tol0) is inverted and an interrupt request is generated to signal the interval or event. the tref0 value, together with the tmod0 clock frequency selection, determines the specific tc0 timer interval. use the following formula to calculate the correct value to load to the tref0 reference register: tc0 timer interval = (tref0 value + 1) 1 tmod0 frequency setting (tref0 value 1 0) tc0 output enable flag (toe0) the 1-bit timer/counter 0 output enable flag toe0 controls output from timer/counter 0 to the tclo0 pin. toe0 is addressable by 1-bit and 4-bit read/write instruction . (msb) (lsb) f92h toe1 toe0 " u " "0" note: the ?u? means that the bit is undefined. when you set the toe0 flag to "1", the contents of tol0 can be output to the tclo0 pin. whenever a reset occurs, toe0 is automatically set to logic zero, disabling all tc0 output. even when the toe0 flag is disabled, timer/counter 0 can continue to output an internally-generated clock frequency, via tol0, to the serial i/o clock selector circuit. tc0 output latch (tol0) tol0 is the output latch for timer/counter 0. when the 8-bit comparator detects a correspondence between the value of the counter register tcnt0 and the reference value stored in the tref0 register, the tol0 value is inverted ? the latch toggles high-to-low or low-to-high. whenever the state of tol0 is switched, the tc0 signal is output. tc0 output may be directed to the tclo0 pin, or it can be output directly to the serial i/o clock selector circuit as the sck signal. assuming tc0 is enabled, when bit 3 of the tmod0 register is set to "1", the tol0 latch is cleared to logic zero, along with the counter register tcnt0 and the interrupt request flag, irqt0, and counting resumes immedi ately. when tc0 is disabled (tmod0.2 = "0"), the contents of the tol0 latch are retained and can be read, if necessary.
S3C72I9/p72i9 timers and timer/counters 11 - 21 + + programming tip ? setting a tc0 timer interval to set a 30 ms timer interval for tc0, given fxx = 4.19 mhz, follow these steps. 1. select the timer/counter 0 mode register with a maximum setup time of 6 2.5 ms (assume the tc0 counter clock = fxx/2 10 , and tref0 is set to ffh): 2. calculate the tref0 value: 30 ms = tref0 value + 1 4.09 khz tref0 + 1 = 30 ms 244 s = 122.9 = 7ah tref0 value = 7ah - 1 = 79h 3. load the value 79h to the tref0 register: bits emb smb 15 ld ea,#79h ld tref0,ea ld ea,#4ch ld tmod0,ea
timers and timer/counters S3C72I9/p72i9 11 - 22 16-bit timer/counter 1 overview timer/counter 1 (tc1) is used to count system 'events' by identifying the transition (high-to-low or low-to-high) of incoming square wave signals. to indicate that an event has occurred, or that a specified time interval has elapsed, tc1 generates an interrupt request. by counting signal transitions, it can be used to measure time inter - vals. the tc1 circuit also has 16-bit comparator logic. tc1 has a reloadable counter that consists of two parts: a 16-bit reference register (tref1) into which you can write data for use as a reference value, and a 16-bit counter register (tcnt1) whose contents are automatically incremented by counter logic. the 8-bit mode register, tmod1, is used to activate the timer/counter and to select the basic clock frequency to be used for timer/counter operations. you can modify the basic frequency dynamically by loading new values into tmod1 during program execution. the only functional differences between tc0 and tc1 are the size of the counter and reference value registers (8-bit versus 16-bit), and the fact that only tc0 can generate a clock signal for the serial i/o interface. timer/counter 1 function summary 16-bit programmable timer generates interrupts at specific time intervals based on the selected clock frequency. external event counter counts various system "events" based on edge detection of external clock signals at the tc1 input pin, tcl1. arbitrary frequency output outputs selectable clock frequencies to the tc1 output pin, tclo1. external signal divider divides the frequency of an incoming external clock signal according to the modifiable reference value (tref1), and outputs the modified frequency to the tclo1 pin.
S3C72I9/p72i9 timers and timer/counters 11 - 23 timer/counter 1 component summary mode register (tmod1) activates the timer/counter and selects the internal clock frequency or the external clock source at the tcl1 pin. reference register (tref1) stores the reference value for the desired number of clock pulses between in terrupt requests. counter register (tcnt1) counts internal clock pulses that are generated based on bit settings in the mode register and reference register. clock selector circuit together with the mode register (tmod1), lets you select one of four internal clock frequencies, or the external system clock source. 16-bit comparator determines when to generate an interrupt by comparing the current value of the counter (tcnt1) with the reference value previously programmed into the reference register (tref1). output latch (tol1) where a tc1 clock pulse is stored pending output to the tc1 output pin, tclo1. when the contents of the tcnt1 and tref1 registers coincide, the timer/counter interrupt request flag (irqt 1 ) is set to "1", the status of tol1 is in verted, and an interrupt is generated. output enable flag (toe1) must be set to logic one before the contents of the tol1 latch can be output to tclo1. interrupt request flag (irqt1) cleared when tc1 operation starts and set to logic one whenever the counter value and reference value match. interrupt enable flag (iet1) must be set to logic one before the interrupt requests generated by timer/counter 1 can be processed. table 11 -8. tc1 register overview register name type description size ram address addressing mode reset value tmod1 control controls tc1 enable/disable (bit 2); clears and resumes counting operation (bit 3); sets input clock and the clock frequency (bits 6 - 4) 8-bit fa0h - fa1h 8-bit write- only; (tmod1.3 is also 1 -bit writeable) "0" tcnt1 counter counts clock pulses matching the tmod1 frequency setting 16-bit fa4h - fa5h, fa6h - fa7h 8-bit read-only "0" tref1 reference stores reference value for tc1 interval setting 16-bit fa8h - fa9h, faah - fabh 8-bit write-only ffffh toe1 flag controls tc1 output to the tclo1 pin 1-bit f92h.3 1 /4 -bit read/ write "0"
timers and timer/counters S3C72I9/p72i9 11 - 24 clear set clear inverted clocks (fxx/2 10 , fxx/2 8 , fxx/2 6 , fxx 4 ) tcl1 clear clock selector tcnt1 tref1 16 16 16-bit comparator irqt1 tol1 p3.1 latch toe1 pm3.1 tmod1.7 tmod1.6 tmod1.5 tmod1.4 tmod1.3 tmod1.2 tmod1.1 tmod1.0 8 tclo1 figure 11 - 4 . tc1 circuit diagram tc1 enable/disable procedure enable timer/counter 1 ? set the tc1 interrupt enable flag iet1 to logic one . ? set tmod1.3 to logic one . tcnt1, irqt1, and tol1 are cleared to logic zero, and timer/counter operation starts. disable timer/counter 1 ? set tmod1.2 to logic zero . clock signal input to the counter register tcnt1 is halted. the current tcnt1 value is retained and can be read if necessary.
S3C72I9/p72i9 timers and timer/counters 11 - 25 tc1 programmable timer/counter function timer/counter 1 can be programmed to generate interrupt requests at variable intervals, based on the system clock frequency you select. the 8-bit tc1 mode register, tmod1, is used to activate the timer/counter and to select the clock frequency; the 16-bit reference register, tref1, is used to store the value for the desired number of clock pulses between interrupt requests. the 16-bit counter register, tcnt1, counts the incoming clock pulses, which are compared to the tref1 value. when there is a match, an interrupt request is generated. to program timer/counter 1 to generate interrupt requests at specific intervals, select one of the four internal clock frequencies (divisions of the system clock, fxx) and load a counter reference value into the tref1 register. tcnt1 is incremented each time an internal counter pulse is detected with the reference clock frequency specified by tmod1.4 - tmod1.6 settings. to generate an interrupt request, the tc1 interrupt request flag (irqt1) is set to logic one, the status of tol1 is inverted, and the interrupt is output. the content of tcnt1 is then cleared to 0000h, and tc1 continues counting. the interrupt request mechanism for tc1 includes an interrupt enable flag (iet1) and an interrupt request flag (irqt1). tc1 timer/counter operation sequence the general sequence of operations for using tc1 can be summarized as follows: 1. set tmod1.2 to "1" to enable tc1. 2. set tmod1.6 to "1" to enable the system clock (fxx) input. 3. set tmod1.5 and tmod1.4 bits to desired internal frequency (fxx/2 n ). 4. load a value to tref1 to specify the interval between interrupt requests. 5. set the tc1 interrupt enable flag (iet1) to "1". 6. set tmod1.3 bit to "1" to clear tcnt1, irqt1, and tol1, and start counting. 7. tcnt1 increments with each internal clock pulse. 8. when the comparator shows tcnt1 = tref1, the irqt1 flag is set to "1" and an interrupt request is generated. 9. output latch (tol1) logic toggles high or low. 10. tcnt1 is cleared to 0000h and counting resumes. 11. programmable timer/counter operation continues until tmod1.2 is cleared to "0".
timers and timer/counters S3C72I9/p72i9 11 - 26 tc1 event counter function timer/counter 1 can monitor system 'events' by using the external clock input at the tcl1 pin as the counter source. the tc1 mode register selects rising or falling edge detection for incoming clock signals. the counter register tcnt1 is incremented each time the selected state transition of the external clock signal occurs. with the exception of the different tmod1.4 - tmod1.6 settings, the operation sequence for tc1's event counter function is identical to its programmable timer/counter function. to activate the tc1 event counter function, ? set tmod1.2 to "1" to enable tc1. ? clear tmod1.6 to "0" to select the external clock source at the tcl1 pin. ? select tcl1 edge detection for rising or falling signal edges by loading the appropriate values to tmod1.5 and tmod1.4. ? pin p3.3 must be set to input mode. table 11 -9. tmod1 settings for tcl1 edge detection tmod1.5 tmod1.4 tcl1 edge detection 0 0 rising edges 0 1 falling edges
S3C72I9/p72i9 timers and timer/counters 11 - 27 tc1 clock frequency output using timer/counter 1, a modifiable clock frequency can be output to the tc1 clock output pin, tclo1. to select the clock frequency, load the appropriate values to the tc1 mode register, tmod1. the clock interval is selected by loading the desired reference value into the 16-bit reference register tref1. to enable the output to the tclo1 pin at i/o port 3.1, the following conditions must be met: ? tc1 output enable flag toe1 must be set to "1". ? i/o mode flag for p3.1 (pm3.1) must be set to output mode ("1"). ? p3.1 output latch must be cleared to "0". in summary, the operational sequence required to output a tc1-generated clock signal to the tclo1 pin is as follows: 1. load your reference value to tref1. 2. set the internal clock frequency in tmod1. 3. initiate tc1 clock output to tclo1 (tmod1.2 = "1"). 4. set port 3.1 mode flag (pm3.1) to "1". 5. clear the p3.1 output latch. 6. set toe1 flag to "1". each time tcnt1 overflows and an interrupt request is generated, the state of the output latch tol1 is in verted and the tc1-generated clock signal is output to the tclo1 pin. + + programming tip ? tc1 signal output to the tclo1 pin output a 30 ms pulse width signal to the tclo1 pin: bits emb smb 15 ld ea,#79h ld tref1a,ea ld ea,#00h ld tref1b,ea ld ea,#4ch ld tmod1,ea ld ea,#02h ld pmg2,ea ; p3.1 ? output mode bitr p3.1 ; p3.1 clear bits toe1
timers and timer/counters S3C72I9/p72i9 11 - 28 tc1 external input signal divider by selecting an external clock source and loading a reference value into the tc1 reference register, tref1, you can divide the incoming clock signal by the tref1 value and then output this modified clock frequency to the tclo1 pin. the sequence of operations used to divide external clock input and output the signals to the tclo1 pin can be summarized as follows: 1. load a signal divider value to the tref1 register. 2. clear tmod1.6 to "0" to enable external clock inpu t at the tclo1 pin. 3. set tmod1.5 and tmod1.4 to desired tcl signal edge detection. 4. set p3.1 mode flag (pm3.1) to output ("1") . 5. clear the p3.1 output latch. 6. set toe1 flag to "1" to enable output of the divided frequency. + + programming tip ? external tcl1 clock output to the tclo1 pin output the external tcl1 clock source to the tclo1 pin (divide by four): external (tcl1) clock pulse tclo1 output pulse bits emb smb 15 ld ea,#01h ld tref1a,ea ld ea,#00h ld tre f1b,ea ld ea,#0ch ld tmod1,ea ld ea,#02h ld pmg2,ea ; p3.1 ? output mode bitr p3.1 ; p3.1 clear bits toe1
S3C72I9/p72i9 timers and timer/counters 11 - 29 tc1 mode register (tmod1) tmod1 is the 8-bit mode register for timer/counter 1. it is ad dressable by 8-bit write instructions. the tmod1.3 bit is also 1-bit write addressable. reset clears all tmod1 bits to logic zero. following a reset , timer/counter 1 is disabled. fa0h tmod1.3 tmod1.2 "0" "0" fa1h "0" tmod1.6 tmod1.5 tmod1.4 tmod1.2 is the enable/disable bit for timer/counter 1. when tmod1.3 is set to "1", the contents of tcnt1, irqt1, and tol1 are cleared, counting starts from 0000h, and tmod1.3 is automatically reset to "0" for normal tc1 operation. when tc1 operation stops (tmod1.2 = "0"), the contents of the tc1 counter register, tcnt1, are retained until tc1 is re-enabled. the tmod1.6, tmod1.5, and tmod1.4 bit settings are used together to select the tc1 clock source. this selection involves two variables: ? synchronization of timer/counter opera tions with either the rising edge or the falling edge of the clock sig nal input at the tcl1 pin, and ? selection of one of four frequencies, based on division of the incoming system clock frequency, for use in internal tc1 operations. table 11 -10. tc1 mode register (tmod1) organization bit name setting resulting tc1 function address tmod1.7 0 always logic zero tmod1.6 0,1 specify input clock edge and internal frequency fa1h tmod1.5 tmod1.4 tmod1.3 1 clear tcnt1, irqt1, and tol1 and resume counting immedi ately (this bit is automatically cleared to logic zero immediately after counting resumes) . fa0h tmod1.2 0 disable timer/counter 1; retain tcnt1 contents 1 enable timer/counter 1 tmod1.1 0 always logic zero tmod1.0 0 always logic zero
timers and timer/counters S3C72I9/p72i9 11 - 30 table 11 - 1 1. tmod1.6, tmod1.5, and tmod1.4 bit settings tmod1.6 tmod1.5 tmod1.4 resulting counter source and clock frequency 0 0 0 external clock input (tcl1) on rising edges 0 0 1 external clock input (tcl1) on falling edges 1 0 0 fxx/2 10 ( 4.09 khz ) 1 0 1 fxx/2 8 ( 16.4 khz ) 1 1 0 fxx/2 6 ( 65.5 khz ) 1 1 1 fxx/2 4 ( 262 khz ) note : 'fxx' = selected system clock of 4.19 mhz. + + programming tip ? restarting tc1 counting operation 1. set tc1 timer interval to 4.09 khz: bits emb smb 15 ld ea,#4ch ld tmod1,ea ei bits iet1 2. clear tcnt1, irqt1, and tol1 and restart tc1 counting operation: sbits emb smb 15 bits tmod1.3
S3C72I9/p72i9 timers and timer/counters 11 - 31 tc1 counter register (tcnt1) the 16-bit counter register for timer/counter 1, tcnt1, is mapped to ram addresses fa5h - fa4h (tcnt1a) and fa7h - fa6h (tcnt1b). the two 8-bit registers are read-only and can be addressed by 8-bit ram control in - structions. reset sets all tcnt1 register values to logic zero (00h). whenever tmod1.2 and tmod1.3 are enabled, tcnt1 is cleared to logic zero and counting begins. the tcnt1 register value is incremented each time an incoming clock signal is detected that matches the signal edge and frequency setting of the tmod1 register (specifically, tmod1.6, tmod1.5, and tmod1.4). each time tcnt1 is incremented, the new value is compared to the reference value stored in the tc1 refer ence register, tref1. when tcnt1 = tref1, an overflow occurs in the tcnt1 register, the interrupt request flag, irqt1, is set to logic one, and an interrupt request is generated to indicate that the specified timer/counter interval has elapsed. reference value = n 0 n ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ n count clock tref1 tcnt1 ~ ~ interval time tol1 timer start instruction (tmod1.3 is set) irqt1 set irqt1 set 1 2 n-1 0 1 2 n-1 0 1 2 3 match match figure 11 - 5 . tc1 timing diagram
timers and timer/counters S3C72I9/p72i9 11 - 32 tc1 reference register (tref1) the tc1 reference register tref1 is a 16-bit write-only register that is mapped to ram locations fa9h - fa8h (tref1a) and fabh - faah (tref1b). it is addressable by 8-bit ram control instructions. reset clears the tref1 value to 'ffffh'. tref1 is used to store a reference value to be compared to the incrementing tcnt1 register in order to iden tify an elapsed time interval. reference values will differ depending upon the specific function that tc1 is being used to perform ? as a programmable timer/counter, event counter, clock signal divider, or arbitrary frequency output source. during timer/counter operation, the value loaded into the reference register compared to the tcnt1 value. when tcnt1 = tref1, the tc1 output latch (tol1) is inverted and an interrupt request is generated to signal the interval or event. the tref1 value, together with the tmod1 clock frequency selection, determines the specific tc1 timer interval. use the following formula to calculate the correct value to load to the tref1 reference register: tc1 timer interval = (tref1 value + 1) 1 tmod1 frequency setting (tref1 value 1 0) tc1 output enable flag (toe1) the 1-bit timer/counter 1 output enable flag toe1 flag controls output from timer/counter 1 to the tclo1 pin. toe1 is addressable by 1-bit read and write instructions. bit 3 bit 2 bit 1 bit 0 f92h toe1 toe0 "u " "0" note: the ?u? means that the bit is undefined. when you set the toe1 flag to "1", the contents of tol1 can be output to the tclo1 pin. whenever a reset occurs, toe1 is automatically set to logic zero, disabling all tc1 output. tc1 output latch (tol1) tol1 is the output latch for timer/counter 1. when the 16-bit comparator detects a correspondence between the value of the counter register tcnt1 and the reference value stored in the tref1 register, the tol1 logic toggles high-to-low or low-to-high. whenever the state of tol1 is switched, the tc1 signal exits the latch for output. tc1 output is directed (if toe1 = "1") to the tclo1 pin at i/o port 3.1. when timer/counter 1 is started, (tmod1.3 = "0"), the contents of the output latch are cleared automatically. however, when tc1 is disabled (tmod1.2 = "0"), the contents of the tol1 latch are retained and can be read, if necessary.
S3C72I9/p72i9 timers and timer/counters 11 - 33 + + programming tip ? setting a tc1 timer interval to set a 30 ms timer interval for tc1, given fxx = 4.19 mhz, follow these steps: 1. select the timer/counter 1 mode register with a max imum setup time of 16 seconds; assume the tc1 counter clock = fxx/2 10 and tref1 is set to ffffh. 2. calculate the tref1 value: 30 ms = tref1 value + 1 4.09 khz tref1 + 1 = 30 ms 244 s = 122.9 = 7ah tref1 value = 7ah - 1 = 79h 3. load the v alue 79h to the tref1 register: bits emb smb 15 ld ea,#79h ld tref1a,ea ld ea,#00h ld tref1b,ea ld ea,#4ch ld tmod1,ea
timers and timer/counters S3C72I9/p72i9 11 - 34 watch timer overview the watch timer is a multi-purpose timer which consists of three basic components: ? 8-bit watch timer mode register (wmod) ? clock selector ? frequency divider circuit watch timer functions include real-time and watch-time measurement and interval timing for the main and sub - system clock. it is also used as a clock source for the lcd controller and for generating buzzer (buz) output. real-time and watch-time measurement to start watch timer operation, set bit 2 of the watch timer mode register (wmod.2) to logic one. the watch timer starts, the interrupt request flag irqw is automatically set to logic one, and interrupt requests commence in 0.5-second intervals. since the watch timer functions as a quasi-interrupt instead of a vectored interrupt, the irqw flag should be cleared to logic zero by program software as soon as a requested interrupt service routine has been executed. using a main system or subsystem clock source the watch timer can generate interrupts based on the main system clock frequency or on the subsystem clock. when the zero bit of the wmod register is set to "1", the watch timer uses the subsystem clock signal (fxt) as its source; if wmod.0 = "0", the main system clock (fx) is used as the signal source, according to the following formula: watch timer clock (fw) = main system clock (fx) 128 = 32.768 khz (fx = 4.19 mhz) this feature is useful for controlling timer-related operations during stop mode. when stop mode is engaged, the main system clock (fx) is halted, but the subsystem clock continues to oscillate. by using the subsystem clock as the oscillation source during stop mode, the watch timer can set the interrupt request flag irqw to "1", thereby releasing stop mode. clock source generation for lcd controller the watch timer supplies the clock frequency for the lcd controller (f lcd ). therefore, if the watch timer is dis - abled, the lcd controller does not operate.
S3C72I9/p72i9 timers and timer/counters 11 - 35 buzzer output frequency generator the watch timer can generate a steady 2 khz, 4 khz, 8 khz, or 16 khz signal to the buz pin. to select the desired buz frequency , load the appropriate value to the wmod register. this output can then be used to actuate an external buzzer sound. to generate a buz signal, three conditions must be met: ? the wmod.7 register bit is set to "1" ? the output latch for i/o port 0.3 is cleared to "0" ? the port 0.3 output mode flag (pm0.3) set to 'output' mode timing tests in high-speed mode by setting wmod.1 to "1", the watch timer will operate in high-speed mode, generating an interrupt every 3.91 ms. at its normal speed (wmod.1 = '0'), the watch timer generates an interrupt request every 0.5 sec onds. high- speed mode is useful for timing events for program debugging sequences. check subsystem clock level feature the watch timer can also check the input level of the subsystem clock by testing wmod.3. if wmod.3 is "1", the input level at the xt in pin is high; if wmod.3 is "0", the input level at the xt in pin is low.
timers and timer/counters S3C72I9/p72i9 11 - 36 fw/2 (16 khz) fw/8 (4 khz) fw/16 (2 khz) enable/ disable irqw f lcd fw/2 3 (4096hz) fw/2 14 (2hz) fw/2 7 fw (32.768 khz) fx = main-system clock fxt = sub-system clock fw = watch timer frequency mux clock selector fxt fx/128 fw/4 (8 khz) frequency dividing circuit wmod.7 wmod.6 wmod.5 wmod.4 wmod.3 wmod.2 wmod.1 wmod.0 8 buz p0.3 latch pm0.3 selector circuit figure 11 - 6 . watch timer circuit diagram
S3C72I9/p72i9 timers and timer/counters 11 - 37 watch timer mode register (wmod) the watch timer mode register wmod is used to select specific watch timer operations. it is 8-bit write-only addressable. an exception is wmod bit 3 (the xt in input level control bit) which is 1-bit read-only addressable. a reset automatically sets wmod.3 to the current input level of the subsystem clock, xt in (high, if logic one; low, if logic zero), and all other wmod bits to logic zero. f88h wmod.3 wmod.2 wmod.1 wmod.0 f89h wmod.7 "0" wmod.5 wmod.4 in summary, wmod settings control the following watch timer functions: ? watch timer clock selection (wmod.0) ? watch timer speed control (wmod.1) ? enable/disable watch timer (wmod.2) ? xt in input level control (wmod.3) ? buzzer frequency selection (wmod.4 and wmod.5) ? enable/disable buzzer output (wmod.7) table 11 - 1 2. watch timer mode register (wmod) organization bit name values function address wmod.7 0 disable buzzer (buz) signal output at the buz pin f89h 1 enable buzzer (buz) signal output at the buz pin wmod.6 0 always logic zero wmod.5 - .4 0 0 2 khz buzzer (buz) signal output 0 1 4 khz buzzer (buz) signal output 1 0 8 khz buzzer (buz) signal output 1 1 16 khz buzzer (buz) signal output wmod.3 0 input level to xt in pin is low f88h 1 input level to xt in pin is high wmod.2 0 disable watch timer; clear frequency dividing circuits 1 enable watch timer wmod.1 0 normal mode; sets irqw to 0.5 seconds 1 high-speed mode; sets irqw to 3.91 ms wmod.0 0 select (fx/128 ) as the watch timer clock (fw) 1 select subsystem clock as watch timer clock (fw) note : main system clock frequen cy (fx) is assumed to be 4.19 mhz; subsystem clock (fxt) is assumed to be 32.768 khz.
timers and timer/counters S3C72I9/p72i9 11 - 38 + + programming tip ? using the watch timer 1. select a subsystem clock as the lcd display clock, a 0.5 second interrupt, and 2 khz buzzer enable: bits emb smb 15 ld ea,#8h ld pmg1,ea ; p0.3 ? output mode bitr p0.3 ld ea,#85h ld wmod,ea bits iew 2. sample real-time clock processing method: clock btstz irqw ; 0.5 second check ret ; no, return ? ; yes, 0.5 second interrupt generation ? ? ; increment hour, minute, second
S3C72I9/p72i9 lcd controller/driv er 12 - 1 12 lcd controller/driver overview the S3C72I9 microcontroller can directly drive an up-to-896-dot (56 segments x 16 commons) lcd panel. its lcd block has the following components: ? lcd controller/ driver ? display ram for storing display data ? 56 segment output pins (seg0 - seg55) ? 16 common output pins (com0 - com15) ? five lcd operating power supply pins (v lc1 - v lc5 ) ? v lc5 pin for controlling the driver and bias voltage to use the lcd controller, bit 2 in the watch mode register wmod must be set to 1, because lcdck is supplied by the watch timer. the frame frequency, duty and bias, and the segment pins used for display output, are determined by bit settings in the lcd mode register, lmod. the lcd control register, lcon, is used to turn the lcd display on and off, to switch current to the dividing resistors for the lcd display, and to output lcd clock (lcdck) and synchronizing signal (lcdsy) for lcd display expansion. data written to the lcd display ram can be transferred to the segment signal pins automatically without program control. when a subsystem clock is selected as the lcd clock source, the lcd display is enabled even during main clock stop and idle modes. lcd controller/ driver v lc1 -v lc5 com0-com7 com8-com15/ p4.0-p5.3 seg0-seg39 seg40-seg55/ p9.3-p6.0 5 16 40 8 8 8 data bus figure 12 - 1 . lcd function diagram
lcd controller/driver S3C72I9/p72i9 12 - 2 seg54/p6.1 seg40/p9.3 seg55/p6.0 com14/p5.2 com0 com15/p5.3 224 56 16 data bus lcdsy lcdck port latch port latch display ram (bank 2) lmod lcon timing controller mux selector com control p2.1 latch p2.2 latch pm2.1 pm2.2 8 f lcd seg0 v cl5 v cl1 lcd voltage control figure 12 - 2 . lcd circuit diagram
S3C72I9/p72i9 lcd controller/driv er 12 - 3 lcd ram address area ram addresses of bank 2 are used as lcd data memory. these locations can be addressed by 1-bit, 4-bit, or 8- bit instructions. when the bit value of a display segment is "1", the lcd display is turned on; when the bit value is "0", the display is turned off. display ram data are sent out through segment pins seg0 - seg55 using a direct memory access (dma) method that is synchronized with the f lcd signal. ram addresses in this location that are not used for lcd display can be allocated to general-purpose use. s e g 4 s e g 5 s e g 6 s e g 7 s e g 8 s e g 9 s e g 0 s e g 1 s e g 2 s e g 3 s e g 10 s e g 11 202h 212h 222h 232h 231h 201h 211h 221h 230h 220h 210h 200h 2cdh 2ddh 2edh 2fdh 2c2h 2d2h 2e2h 2f2h 2f1h 2c1h 2d1h 2e1h 2f0h 2e0h 2d0h 2c0h 23dh 22dh 21dh 20dh s e g 52 s e g 53 s e g 54 s e g 55 b0 b1 b2 b3 b0 b1 b2 b3 com0 com1 com2 com3 com12 com13 com14 com15 b0 b1 b2 b3 b0 b1 b2 b3 figure 12 - 3 . lcd display data ram organization table 12 - 1. common and segment pins per duty cycle duty common pins segment pins dot number 1/16 com0 - com15 40 pins - 56 pins 640 dots - 896 dots 1/8 com0 - com7 320 dots - 448 dots note: when 1/8 duty is selected, com8 - com15 (p4.0 - p5.3) can be used for normal i/o pins.
lcd controller/driver S3C72I9/p72i9 12 - 4 lcd control register (lcon) the lcd control register (lcon) is used to turn the lcd display on and off, to output lcd clock (lcdck) and synchronizing signal (lcdsy) for lcd display expansion, and to control the flow of current to dividing resistors in the lcd circuit. following a reset , all lcon values are cleared to "0". this turns the lcd display off and stops the flow of current to the dividing resistors. f8eh ? 0 ? lcon.2 lcon.1 lcon.0 the effect of the lcon.0 setting is dependent upon the current setting of bits lmod.0 and lmod.1. bit 1 in the lcon is used for contrast control application. table 12 - 2 . lcd control register (lcon) organization lcon bit setting description lcon.3 0 always logic zero. lcon.2 0 disable lcdck and lcdsy signal outputs. 1 enable lcdck and lcdsy signal outputs. lcon.1 0 0 lcd display off; cut off current to dividing resistor lcon.0 0 1 lcd display on; application without contrast control 1 0 lcd display on; application with contrast control 1 1 lcd disp la y on; application without contrast control note: the function of lcon.0 is applied in case of using the internal gnd for lcd power; the function of lcon1 is used for contrast control application. table 12 - 3 . lmod.1 - 0 bits settings lmod.1 - 0 com0 - com15 seg0 - seg55 seg40/p9.3 - seg55/p6.0 power supply to the dividing resistor 0, 0 all of the lcd dots off normal i/o port function on 0, 1 all of the lcd dots on 1, 1 common and segment signal output corresponds to display data (normal display mode) note : ' x ' means 'don't care.'
S3C72I9/p72i9 lcd controller/driv er 12 - 5 lcd mode register (lmod) the lcd mode control register lmod is used to control display mode; lcd clock, segment or port output, and display on/off. lmod can be manipulated using 8-bit write instructions. f8ch lmod.3 lmod.2 lmod.1 lmod.0 f8dh lmod.7 lmod.6 lmod.5 lmod.4 the lcd clock signal, lcdck, determines the frequency of com signal scanning of each segment output. this is also referred to as the 'frame frequency. since lcdck is generated by dividing the watch timer clock (fw), the watch timer must be enabled when the lcd display is turned on. reset clears the lmod register values to logic zero. the lcd display can continue to operate during idle and stop modes if a subsystem clock is used as the watch timer source. the lcd mode register lmod controls the output mode of the 16 pins used for normal outputs (p9.3 - p6.0). bits lmod.7 - 5 define the segment output and normal bit output configuration. table 12 - 4 . lcd clock signal (lcdck) frame frequency lcdck 256 hz 512 hz 1024 hz 2048 hz 4096 hz display duty cycle 1/8 32 64 128 256 ? 1/16 ? 32 64 128 256 note: 1 frame com0
lcd controller/driver S3C72I9/p72i9 12 - 6 table 12 - 5 . lcd mode register (lmod) organization segment/port output selection bits lmod.7 lmod.6 lmod.5 seg40 - 43 seg44 - 47 seg48 - 51 seg52 - 55 total number of segment 0 0 0 seg port seg port seg port seg port 56 0 0 1 seg port seg port seg port normal port 52 0 1 0 seg port seg port normal port normal port 48 0 1 1 seg port normal port normal port normal port 44 1 0 0 normal port normal port normal port normal port 40 note: segment pins that also can used for normal i/o should be configured to output mode when the seg function is used. lcd clock selection bits lmod.4 lmod.3 lcd clock (lcdck) 1/8 duty (com0 - com7) 1/16 duty (com0 - com15) 0 0 fxx/2 7 (256 hz) fxx/2 6 (512 hz) 0 1 fxx/2 6 (512 hz) fxx/2 5 (1024 hz) 1 0 fxx/2 5 (1024 hz) fxx/2 4 (2048 hz) 1 1 fxx/2 4 (2048 hz) fxx/ 2 3 (4096 hz) note: lcdck is supplied only when the watch timer is operating . to use the lcd contro ller, you must set bit 2 in the watch mode register wmod to ?1?. duty selection bits lmod.2 duty 0 1/8 duty (com0 - com7 select) 1 1/16 duty (com0 - com15 select) note: when 1/16 duty is selected, ports 4 and 5 should be configured as output mode; when 1/8 duty is selected, ports 4 and 5 can be used as normal i/o ports. display mode selection bits lmod.1 lmod.0 function 0 0 all lcd dots off 0 1 all lcd dots on 1 1 normal display
S3C72I9/p72i9 lcd controller/driv er 12 - 7 lcd voltage dividing resistors on-chip voltage dividing resistors for the lcd drive power supply are fixed to the v lc1 - v lc5 pins. power can be supplied without an external dividing resistor. figure 12 - 4 shows the bias connections for the S3C72I9 lcd drive power supply. to cut off the flow of current through the dividing resistor, clear bits 0 and 1 of the lcon register. S3C72I9 1/4 bais S3C72I9 1/5 bais v cl1 v cl2 v cl3 v cl4 v cl5 v cl1 v cl2 v cl3 v cl4 v cl5 figure 12 - 4 . lcd bias circuit connection
lcd controller/driver S3C72I9/p72i9 12 - 8 notes: 1. when the lcd module is turned off, clear lcon.0 and lcon.1 to "0" to reduce power consumption. 2. if an external variable resistor is used to connect v lc5 to ground, you can control lcd contrast using the variable resistor. S3C72I9 v ss application with contrast control v ss lcon.0 (off) lcon.1 (on) S3C72I9 fixed v ss application without contrast control v dd lcon.0 (on) lcon.1 (don't care) fixed v cl1 v cl2 v cl3 v cl4 v cl5 v cl1 v cl2 v cl3 v cl4 v cl5 v dd figure 12 - 5 . internal voltage dividing resistor connection (1/5 bias, display on)
S3C72I9/p72i9 lcd controller/driv er 12 - 9 common (com) signals the common signal output pin selection (com pin selection) varies according to the selected duty cycle. ? in 1/8 duty mode, com0 - com7 pins are selected . ? in 1/16 duty mode, com0 - com15 pins are selected . when 1/8 duty is selected by clearing lmod.2 to zero, com8 - com15 (p4.0 - p5.3) can be used for normal i/o port. segment (seg) signals the 56 lcd segment signal pins are connected to corresponding display ram locations at bank 2. bits of the display ram are synchronized with the common signal output pins. when the bit value of a display ram location is "1", a select signal is sent to the corresponding segment pin. when the display bit is "0", a 'no-select' signal is sent to the corresponding segment pin.
lcd controller/driver S3C72I9/p72i9 12 - 10 com0 v lc2 v lc3 v lc4 v lc5 v dd v lc1 com3 v lc2 v lc3 v lc4 v lc5 v dd v lc1 com2 v lc2 v lc3 v lc4 v lc5 v dd v lc1 com1 v lc2 v lc3 v lc4 v lc5 v dd v lc1 1 frame fr 0 1 2 3 0 1 2 3 15 15 v dd v ss com0 com1 com2 com3 com4 com5 com6 com7 s e g 0 s e g 1 s e g 2 s e g 3 s e g 4 com8 com9 com10 com11 com12 com13 com14 com15 figure 12 -6. lcd signal waveforms (1/16 duty, 1/5 bias)
S3C72I9/p72i9 lcd controller/driv er 12 - 11 1 frame fr 0 1 2 3 0 1 2 3 15 15 v dd v ss seg1 v lc2 v lc3 v lc4 v lc5 v dd v lc1 seg0-com0 seg1-com0 v lc2 v lc3 v lc4 v lc5 v dd v lc1 -v lc2 -v lc1 -v dd -v lc4 -v lc3 v lc2 v lc3 v lc4 v lc5 v dd v lc1 -v lc2 -v lc1 -v dd -v lc4 -v lc3 figure 12 -6. lcd signal waveforms (1/16 duty, 1/5 bias) (continued)
lcd controller/driver S3C72I9/p72i9 12 - 12 1 frame fr v dd v ss com0 com1 com2 com3 com4 com5 com6 com7 s e g 0 s e g 1 s e g 2 s e g 3 s e g 4 com8 com9 com10 com11 com12 com13 com14 com15 com1 v lc2 (v lc3 ) v lc4 v lc5 v dd v lc1 seg0 v lc2 (v lc3 ) v lc4 v lc5 v dd v lc1 com2 v lc2 (v lc3 ) v lc4 v lc5 v dd v lc1 com0 v lc2 ( v lc3 ) v lc4 v lc5 v dd v lc1 seg0-com0 v lc2 (v lc3 ) v dd v lc1 v lc5 v lc4 -v lc4 -v lc2 (-v lc3 ) -v lc1 -v dd 0 1 2 3 7 4 6 5 0 1 2 3 7 4 6 5 figure 12 -7. lcd signal waveforms (1/8 duty, 1/4 bias)
S3C72I9/p72i9 lcd controller/driv er 12 - 13 1 frame fr v dd v ss seg1 v lc2 ( v lc3 ) v lc4 v lc5 v dd v lc1 seg0-com0 v lc2 (v lc3 ) v dd v lc1 v lc5 v lc4 -v lc4 -v lc2 (-v lc3 ) -v lc1 -v dd 0 1 2 3 7 4 6 5 0 1 2 3 7 4 6 5 figure 12 -7. lcd signal waveforms (1/8 duty, 1/4 bias) (continued)
S3C72I9/p72i9 serial i/o interfac e 13 - 1 13 serial i/o interface overview the serial i/o interface (sio) has the following functional components: ? 8-bit mode register (smod) ? clock selector circuit ? 8-bit buffer register (sbuf) ? 3-bit serial clock counter using the serial i/o interface, 8-bit data can be exchanged with an external device. the transmission frequency is controlled by making the appropriate bit settings to the smod register. the serial interface can run off an internal or an external clock source, or the tol0 signal that is generated by the 8-bit timer/counter, tc0. if the tol0 clock signal is used, you can modify its frequency to adjust the serial data transmission rate. serial i/o operation sequence the general operation sequence of the serial i/o interface can be summarized as follows: 1. set sio mode to transmit-and-receive or to receive-only. 2. select msb-first or lsb-first transmission mode. 3. set the sck clock signal in the mode register, smod. 4. set sio interrupt enable flag (ies) to "1". 5. initiate sio transmission by setting bit 3 of the smod to "1". 6. when the sio operation is complete, irqs flag is set and an interrupt is generated.
serial i/o interface S3C72I9/p72i9 13 - 2 over flow so clear smod.7 q r s p0.0/ sck si irqs note : instruction execution bits (note) 8 8 8 sbuf (8-bit) lsb/msb clock selector tol0 cpu clk fxx/2 10 fxx/2 4 smod.6 smod.5 - - smod.3 smod.2 smod.1 smod.0 q0 q1 q2 3-bit counter r q d ck internal bus internal bus figure 13 - 1 . serial i/o interface circuit diagram
S3C72I9/p72i9 serial i/o interfac e 13 - 3 serial i/o mode register (smod) the serial i/o mode register, smod, is an 8-bit register that specifies the operation mode of the serial interface. its reset value is logical zero. smod is organized in two 4-bit registers, as follows: fe0h smod.3 smod.2 smod.1 smod.0 fe1h smod.7 smod.6 smod.5 0 smod register settings enable you to select either msb-first or lsb-first serial transmission, and to operate in transmit-and-receive mode or receive-only mode. smod is a write-only register and can be addressed only by 8- bit ram control instructions. one exception to this is smod.3, which can be written by a 1-bit ram control instruction. when smod.3 is set to 1, the contents of the serial interface interrupt request flag, irqs, and the 3- bit serial clock counter are cleared, and sio operations are initiated. when the sio transmission starts, smod.3 is cleared to logical zero. table 13 - 1 . sio mode register (smod) organization smod.0 0 most significant bit (msb) is transmitted first 1 least significant bit (lsb) is transmitted first smod.1 0 receive-only mode 1 transmit-and-receive mode smod.2 0 disable the data shifter and clock counter; retain contents of irqs flag when serial transmission is halted 1 enable the data shifter and clock counter; set irqs flag to "1" when serial transmission is halted smod.3 1 clear irqs flag and 3-bit clock counter to "0"; initiate transmission and then reset this bit to logic zero smod.4 0 bit not used; value is always "0" smod.7 smod.6 smod.5 clock selection r/w status of sbuf 0 0 0 external clock at sck pin sbuf is enabled when sio operation is halted or when sck goes high. 0 0 1 use tol0 clock from tc0 0 1 x cpu clock: fxx/4, fxx/8, fxx/64 enable sbuf read/write 1 0 0 4.09 khz clock: fxx/2 10 sbuf is enabled when sio operation is halted or when sck goes high. 1 1 1 262 khz clock: fxx/2 4 notes : 1. 'fxx' = system clock; 'x' means 'don't care.' 2. khz frequency ratings assume a system clock (fxx) running at 4.19 mhz. 3. the sio clock selector circuit cannot select a fxx/2 4 clock if the cpu clock is fxx/64 . 4. it must be selected msb-first or lsb-first transmission mode before loading the data to sbuf.
serial i/o interface S3C72I9/p72i9 13 - 4 serial i/o timing diagrams so si sck d17 d16 d15 d14 d13 d12 d11 d10 do6 do5 do4 do3 do2 do1 do0 do7 transmit complete irqs set smod.3 figure 13 - 2 . sio timing in transmit/receive mode si sck d17 d16 d15 d14 d13 d12 d11 d10 transmit complete irqs set smod.3 high impendence so figure 13 - 3 . sio timing in receive-only mode
S3C72I9/p72i9 serial i/o interfac e 13 - 5 serial i/o buffer register (sbuf) the serial i/o buffer register ,sbuf, can be read or written using 8-bit ram control instructions. following a reset , the value of sbuf is undetermined. when the serial interface operates in transmit-and-receive mode (smod.1 = "1"), transmit data in the sio buffer register are output to the so pin (p0.1) at the rate of one bit for each falling edge of the sio clock. receive data are simultaneously input from the si pin (p0.2) to sbuf at the rate of one bit for each rising edge of the sio clock. when receive-only mode is used, incoming data are input to the sio buffer at the rate of one bit for each rising edge of the sio clock. + + programming tip ? setting transmit/receive modes for serial i/o 1. transmit the data value 48h through the serial i/o interface using an internal clock frequency of fxx/2 and in msb-first mode: bits emb smb 15 ld ea,#03h ld pmg1,ea ld ea,#0e 6 h ld smod,ea ; p0.0/ sck and p0.1/so ? output ld ea,#48h ; ld sbuf,ea ; bits smod.3 ; sio data transfer external device sck /p0.0 so/p0.1 [S3C72I9] 2. use cpu clock to transfer and receive serial data at high speed: bits emb smb 15 ld ea,#03h ld pmg1,ea ; p0.0/ sck and p0.1/so ? output, p0.2/si ? input ld ea,#4 7 h ld smod,ea ; ld ea,tdata ld sbuf,ea bits s mod.3 ; sio start bitr ies stest btstz irqs jr stest ld ea,sbuf smb 0 ld rdata,ea
serial i/o interface S3C72I9/p72i9 13 - 6 + + programming tip ? setting transmit/receive modes for serial i/o (continued) 3. transmit and receive an internal clock frequency of 4.09 khz (at 4.19 mhz) in lsb-first mode: bits emb smb 15 ld ea,#03h ld pmg1,ea ld ea,#8 7 h ld smod,ea ; p0.0 / sck and p0.1/so ? output, p0.2/si ? input ld ea,tdata ld sbuf,ea bits smod.3 ; sio start ei bits ies . . ints push sb ; store smb, srb push ea ; store ea ld ea,tdata ; ea ? transmit data smb 15 xch ea,sbuf ; ea ? receive data smb 0 ld rdata,ea ; rdata ? receive data bits smod.3 ; sio start pop ea pop sb iret external device sck /p0.0 so/p0.1 si/p0.2 [S3C72I9]
S3C72I9/p72i9 serial i/o interfac e 13 - 7 + + programming tip ? setting transmit/receive modes for serial i/o (continued) 4. transmit and receive an external clock in lsb-first mode: bits emb smb 15 ld ea,#02h ld pmg1,ea ld ea,#0 7 h ld smod,ea ; p0.1/so ? output, p0.0/ sck and p0.2/si ? input ld ea,tdata ld sbuf,ea bits smod.3 ; sio start ei bits ies . . ints push sb ; store smb, srb push ea ; store ea ld ea,tdata ; ea ? transmit data smb 15 xch ea,sbuf ; ea ? receive data smb 0 ld rdata,ea ; rdata ? receive data bits smod.3 ; sio start pop ea pop sb iret high speed sio transmission external device sck /p0.0 so/p0.1 si/p0.2 [S3C72I9]
serial i/o interface S3C72I9/p72i9 13 - 8 + + programming tip ? setting transmit/receive modes for serial i/o (concluded) use cpu clock to transfer and receive serial data at high speed: b its emb smb 15 ld ea,#03h ld pmg1,ea ld ea,#4 7 h ld smod , ea ; p0.0/ sck and p0.1 /so ? output, p0.2/si ? input ld ea,tdata ld sbuf,ea bits scmod.3 ; sio start bitr ies stest btstz irqs jr stest ld ea,sbuf smb 0 ld rdata,ea
S3C72I9/p72i9 electrical data 14 - 1 14 electrical data overview in this section, information on S3C72I9 electrical characteristics is presented as tables and graphics. the information is arranged in the following order: standard electrical characteristics ? abs olute maximum ratings ? d.c. electrical characteristics ? main system clock oscillator characteristics ? subsystem clock oscillator characteristics ? i/o capacitance ? a.c. electrical characteristics ? operating voltage range miscellaneous timing waveforms ? a.c timing measurement point ? clock timing measurement at x in ? clock timing measurement at xt in ? tcl timing ? input timing for reset ? input timing for external interrupts ? serial data transfer timing stop mode characteristics and timing waveforms ? ram data retention supply voltage in stop mode ? stop mode release timing when initiated by reset ? stop mode release timing when initiated by an interrupt request
electrical data S3C72I9/p72i9 14 - 2 table 14 - 1 . absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? - 0.3 to + 6.5 v input voltage v i ports 0 - 9 - 0.3 to v dd + 0.3 v output voltage v o ? - 0.3 to v dd + 0.3 v output current high i oh one i/o p in active - 15 ma all i/o pins active - 3 5 output current low i ol one i/o pin active + 30 (peak value) ma + 15 (note) total for ports 0, 2 - 9 + 100 (peak value) + 60 (note) operating temperature t a ? - 40 to + 85 c storage temperature t stg ? - 65 to + 150 c note : the values for output current low ( i ol ) are calculated as peak value duty . table 14 - 2 . d.c. electrical characteristics (t a = - 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units input high voltage v ih1 all input pins except those specified below for v ih2 - v ih3 0.7 v dd ? v dd v v ih2 ports 0, 1, 6, p3.2, p3.3, and reset 0.8 v dd v dd v ih3 x in , x out , and xt in v dd - 0. 1 v dd input low voltage v il1 all input pins except those specified below for v il2 - v il3 ? ? 0.3 v dd v v il2 ports 0, 1, 6, p3.2, p3.3, and reset 0.2 v dd v il3 x in , x out , and xt in 0. 1 output high voltage v oh v dd = 4.5 v to 5.5 v i oh = - 1 m a ports 0, 2 - 9 v dd - 1.0 ? ? v output low voltage v ol v dd = 4.5 v to 5.5 v i ol = 15 ma p orts 0, 2 - 9 ? ? 2.0 v
S3C72I9/p72i9 electrical data 14 - 3 table 14 - 2 . d.c. electrical characteristics (continued) (t a = - 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units input high leakage current i lih1 v i = v dd all input pins except those specified below for i lih2 ? ? 3 a i lih2 v i = v dd x in , x out , xt in , and reset 20 input low leakage i lil1 v i = 0 v all input pins except those specified below for i lih2 ? ? - 3 a current i lil2 v i = 0 v x in , x out , and xt in - 20 output high leakage current i loh v o = v dd all output pins ? ? 3 a output low leakage current i lol v o = 0 v all output pins ? ? - 3 a pull-up resistor r l i v i = 0 v; v dd = 5 v port 0 - 9 25 47 100 k w v dd = 3 v 50 95 200 r l 2 v i = 0 v; v dd = 5 v , reset 100 220 400 v dd = 3 v 200 450 800 lcd voltage dividing resistor r lcd t a = 25 c 25 55 80 k w | v dd -com i | voltage drop (i = 0 - 15) v dc - 15 a per common pin ? ? 120 mv | v dd -segx| voltage drop (x = 0 - 55) v ds - 15 a per segment pin ? ? 120 v lc1 output voltage v lc1 lcd clock = 0 hz, v lc5 = 0 v 0.8 v dd - 0.2 0.8 v dd 0.8 v dd + 0.2 v v lc2 output voltage v lc2 0.6 v dd - 0.2 0.6 v dd 0.6 v dd + 0.2 v lc3 output voltage v lc3 0.4 v dd - 0.2 0.4 v dd 0.4 v dd + 0.2 v lc4 output voltage v lc4 0.2 v dd - 0.2 0.2 v dd 0.2 v dd + 0.2
electrical data S3C72I9/p72i9 14 - 4 table 14 - 2 . d.c. electrical characteristics (concluded) (t a = - 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units supply current i dd1 ( 2 ) v dd = 5 v 10% c rystal oscillator c1 = c2 = 22 pf 6.0 mhz 4.19 mhz ? 5.1 3.9 10.0 7.5 ma v dd = 3 v 10% 6.0 mhz 4.19 mhz 2.5 1.8 4.0 3.0 i dd2 ( 2 ) idle mode; v dd = 5 v 10% c rystal oscillator c1 = c2 = 22 pf 6.0 mhz 4.19 mhz 1.3 1.2 2.5 1.8 v dd = 3 v 10% 6.0 mhz 4.19 mhz 0.5 0.44 1.5 1.0 i dd3 ( 3 ) v dd = 3 v 10% 32 khz crystal oscillator ? 22.8 35 a i dd4 ( 3 ) idle mode; v dd = 3 v 10% 32 khz crystal oscillator 6.4 15 i dd5 stop mode; v dd = 5 v 10% scmod = 0000b 2.5 5 stop mode; v dd = 3 v 10% xt = 0v 0.5 3 stop mode; v dd = 5 v 10% scmod = 0100b 0.2 3 stop mode; v dd = 3 v 10% 0.1 2 notes: 1. data includes power consumption for subsystem clock oscillation. 2 . when the system clock control register, scmod, is set to 1001b, main system clock oscillation stops and the subsystem clock is used. 3. currents in the following circuits are not included; on-chip pull-up resistors, internal lcd voltage dividing resistors, output port drive currents .
S3C72I9/p72i9 electrical data 14 - 5 table 14 - 3 . main system clock oscillator characteristics (t a = - 40 c + 85 c, v dd = 1.8 v to 5.5 v ) oscillator clock configuration parameter test condition min typ max units ceramic oscillator x in c1 c2 x out oscillation frequency (1) ? 0.4 ? 6.0 mhz stabilization time (2) stabilization occurs when v dd is equal to the minimum oscillator voltage range ; v dd = 3.0 v. ? ? 4 ms crystal oscillator x in c1 c2 x out oscillation frequency (1) ? 0.4 ? 6.0 mhz stabilization time (2) v dd = 3.0 v ? ? 10 ms v dd = 2. 0 v to 5 .5 v ? ? 30 external clock x in x out x in input frequency (1) ? 0.4 ? 6.0 mhz x in input high and low level width (t xh, t xl ) ? 83.3 ? 1250 ns rc oscillator x in x out r frequency r = 2 0 k w , v dd = 5 v ? 2 ? mhz r = 39 k w , v dd = 3 v ? 1 ? notes: 1. oscillation frequency and x in in put frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is ter minated.
electrical data S3C72I9/p72i9 14 - 6 table 14-4. recommended oscillator constants (t a = - 40 c + 85 c, v dd = 1.8 v to 5.5 v ) manufacturer series number (1) frequency range load cap (pf) oscillator voltage range (v) remarks c1 c2 min max tdk fcr ? e ? m5 3.58 mhz-6.0 mhz 33 33 2.0 5.5 leaded type fcr ? e ? mc5 3.58 mhz-6.0 mhz (2) (2) 2.0 5.5 on-chip c leaded type ccr ? e ? mc3 3.58 mhz-6.0 mhz (3) (3) 2.0 5.5 on-chip c smd type note s: 1. please specify normal oscillator frequency. 2. on-chip c: 30pf built in. 3. on-chip c: 38 pf built in.
S3C72I9/p72i9 electrical data 14 - 7 table 14 -5. subsystem clock oscillator characteristics (t a = - 40 c + 85 c, v dd = 1.8 v to 5.5 v ) oscillator clock configuration parameter test condition min typ max units crystal oscillator xt in c1 c2 xt out oscillation frequency (1) ? 32 32.768 35 khz stabilization time (2) v dd = 2.7 v to 5.5 v ? 1.0 2 s v dd = 2. 0 v to 5 .5 v ? ? 10 external clock xt in xt out xt in input frequency (1) ? 32 ? 100 khz xt in input high and low level width (t xtl, t xth ) ? 5 ? 15 s notes: 1. oscillation frequency and xt in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs. table 14 -6. input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out ? ? 15 pf i/o capacitance c io ? ? 15 pf
electrical data S3C72I9/p72i9 14 - 8 table 14 -7. a.c. electrical characteristics (t a = - 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units instruction cycle time ( note ) t cy v dd = 2.7 v to 5.5 v 0.67 ? 64 s v dd = 2. 0 v to 5 .5 v 0.95 64 tcl0, tcl1 input frequency f ti0, f ti1 v dd = 2.7 v to 5.5 v 0 ? 1 .5 mhz v dd = 2. 0 v to 5 .5 v 1 tcl0, tcl1 input high, low width t tih0, t til0 t tih1, t til1 v dd = 2.7 v to 5.5 v 0.48 ? ? s v dd = 2. 0 v to 5 .5 v 1.8 sck cycle time t kcy v dd = 2.7 v to 5.5 v; input 800 ? ? ns internal sck source ; output 650 v dd = 2. 0 v to 5.5 v; input 3200 internal sck source ; output 3800 sck high, low width t kh , t kl v dd = 2.7 v to 5.5 v; input 325 ? ? ns internal sck source ; output t kcy / 2- 50 v dd = 2. 0 v to 5 .5 v ; input 1600 internal sck source ; output t kcy / 2 - 150 si setup time to sck high t sik v dd = 2.7 v to 5.5 v ; input 100 ? ? ns v dd = 2.7 v to 5.5 v ; output 150 v dd = 2.0 v to 5.5 v ; input 150 v dd = 2.0 v to 5.5 v ; output 500 si hold time to sck high t ksi v dd = 2.7 v to 5.5 v ; input 400 ? ? ns v dd = 2.7 v to 5.5 v ; output 400 v dd = 2.0 v to 5.5 v ; input 600 v dd = 2.0 v to 5.5 v ; output 500 note: unless otherwise specified, instruction cycle time condition values assume a main system clock ( fx ) source.
S3C72I9/p72i9 electrical data 14 - 9 table 14 -7. a.c. electrical characteristics (continued) (t a = - 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units output delay for sck to so t kso v dd = 2.7 v to 5.5 v ; input ? ? 300 ns v dd = 2.7 v to 5.5 v ; output 250 v dd = 2.0 v to 5.5 v ; input 1000 v dd = 2.0 v to 5.5 v ; output 1000 interrupt input high, low width t inth, t intl int0 , int1, int2, int4, k 0 - k7 10 ? ? s reset input low width t rsl input 10 ? ? s note: minimum value for int0 is based on a clock of 2t cy or 128/fx as assigned by the imod0 register setting. 1.5 mhz cpu clock 1.05 mhz 750 khz 15.6 khz main oscillator frequency (divided by 4) 4.2 mhz 3 mhz 6 mhz 1 2 3 4 5 6 7 supply voltage (v) cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) 1.8 v figure 14 - 1 . standard operating voltage range
electrical data S3C72I9/p72i9 14 - 10 table 14 -8. ram data retention supply voltage in stop mode (t a = - 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 1.8 ? 5.5 v data retention supply current i dddr v dddr = 1.8 v ? 0.1 10 a release signal set time t srel ? 0 ? ? s oscillator stabilization wait time (1) t wait released by reset ? 2 17 /fx ? ms released by interrupt ? (2) ? notes : 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid instability during oscillator start-up. 2. use the basic timer mode register (bmod) interval timer to delay execution of cpu instructions during the wait time.
S3C72I9/p72i9 electrical data 14 - 11 timing waveforms execution of stop instrction internal reset operation ~ ~ v dddr ~ ~ stop mode idle mode normal mode data retention mode t srel t wait reset v dd figure 14 - 2 . stop mode release timing when initiated b y reset reset execution of stop instrction v dddr ~ ~ data retention mode v dd normal mode ~ ~ stop mode idle mode t srel t wait power-down mode terminating signal (interrupt request) figure 14 - 3 . stop mode release timing when initiated b y interrupt request
electrical data S3C72I9/p72i9 14 - 12 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 14 - 4 . a.c. timing measurement points (except for x in and xt in ) x in t xh t xl 1/fx v dd - 0.1 v 0.1 v figure 14 - 5 . clock timing measurement at x in xt in t xth t xtl 1/fxt v dd - 0.1 v 0.1 v figure 14 - 6 . clock timing measurement at xt in
S3C72I9/p72i9 electrical data 14 - 13 tcl0 t tih t til 1/f ti 0.8 v dd 0.2 v dd figure 14 - 7 . tcl timing reset t rsl 0.2 v dd figure 14 - 8 . input timing for reset reset signal int0, 1, 2, 4, k0 to k7 t inth t intl 0.8 v dd 0.2 v dd figure 14 - 9 . input timing for external interrupts and quasi-interrupts
electrical data S3C72I9/p72i9 14 - 14 output data input data sck t kh t kcy t kl 0.8 v dd 0.2 v dd t kso t si k t ksi 0.8 v dd 0.2 v dd si so figure 14 - 10 . serial data transfer timing
S3C72I9/p72i9 michani cal data 1 5- 1 1 5 michanical data overview the S3C72I9 microcontrollers are available in a 100-qfp-1420c package. note : dimensions are in millimeters. 100-qfp-1420c #100 #1 20.00 0.2 14.00 0.2 17.90 0.3 23.90 0.3 0.10 max 0.65 (0.83) 0.10 max (0.58) 0.80 0.20 0.05 min 2.65 0.10 3.00 max 0.15 +0.10 -0.05 0-8 0.3 0.1 0.80 0.20 figure 15-1. 100-qfp package dimension
S3C72I9/p72i9 s3p72 i9 otp 16- 1 16 s3p72i9 otp overview the s3p72i9 single-chip cmos microcontroller is the otp (one time programmable) version of the S3C72I9 microcontroller. it has an on-chip otp rom instead of masked rom. the eprom is accessed by serial data format. the s3p72i9 is fully compatible with the S3C72I9, both in function and in pin configuration. because of its simple programming requirements, the s3p72i9 is ideal for use as an evaluation chip for the S3C72I9.
s3p72i9 otp S3C72I9/p72i9 16- 2 seg4 seg3 seg2 seg1 seg0 v lc5 v lc4 v lc3 v lc2 v lc1 p0.0/ sck /k0 p0.1/so/k1 sdat /p0.2/si/k2 sclk /p0.3/buz/k3 v dd /v dd v ss /v ss x out x in v pp /test xt in xt out reset reset /reset p1.0/int0 p1.1/int1 p1.2/int2 p1.3/int4 p2.0/clo p2.1/lcdck p2.2/lcdsy p3.0/tclo0 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 p3.1/tclo1 p3.2/tcl0 p3.3/tcl1 com0 com1 com2 com3 com4 com5 com6 com7 p4.0/com8 p4.1/com9 p4.2/com10 p4.3/com11 p5.0/com12 p5.1/com13 p5.2/com14 p5.3/com15 p6.0/seg55/k4 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 p9.3/seg40 p9.2/seg41 p9.1/seg42 p9.0/seg43 p8.3/seg44 p8.2/seg45 p8.1/seg46 p8.0/seg47 p7.3/seg48 p7.2/seg49 p7.1/seg50 p7.0/seg51 p6.3/seg52/k7 p6.2/seg53/k6 p6.1/seg54/k5 s3p72i9 (100-qfp-1420c) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 note: the bolds indicate an otp pin name. figure 16-1. s3p72i9 pin assignments (100-qfp package)
S3C72I9/p72i9 s3p72 i9 otp 16- 3 table 16-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p0.2 sdat 13 i/o serial data pin. output port when reading and input port when writing. can be assigned as a input/push-pull output port. p0.3 sclk 14 i/o serial clock pin. input only pin. test v pp (test) 19 i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 22 i chip initialization v dd /v ss v dd /v ss 15/16 i logic power supply pin. v dd should be tied to + 5 v during programming. table 16-2. comparison of s3p72i9 and S3C72I9 features characteristic s3p72i9 S3C72I9 program memory 32 kbyte eprom 32 kbyte mask rom operating voltage (v dd ) 1.8 v to 5.5 v 1.8 v to 5.5 v otp programming mode v dd = 5 v, v pp (test) = 12.5 v pin configuration 100 qfp 100 qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the s3p72i9, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 16-3 below. table 16-3. operating mode selection criteria v dd v pp (test) reg/ mem address (a15-a0) r/w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note : "0" means low level; "1" means high level.
s3p72i9 otp S3C72I9/p72i9 16- 4 table 1 6-4. d.c. electrical characteristics (t a = - 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units supply current i dd1 ( 2 ) v dd = 5 v 10% c rystal oscillator c1 = c2 = 22 pf 6.0 mhz 4.19 mhz ? 5.1 3.9 10.0 7.5 ma v dd = 3 v 10% 6.0 mhz 4.19 mhz 2.5 1.8 4.0 3.0 i dd2 ( 2 ) idle mode; v dd = 5 v 10% c rystal oscillator c1 = c2 = 22 pf 6.0 mhz 4.19 mhz 1.3 1.2 2.5 1.8 v dd = 3 v 10% 6.0 mhz 4.19 mhz 0.5 0.44 1.5 1.0 i dd3 ( 3 ) v dd = 3 v 10% 32 khz crystal oscillator ? 22.8 35 a i dd4 ( 3 ) idle mode; v dd = 3 v 10% 32 khz crystal oscillator 6.4 15 i dd5 stop mode; v dd = 5 v 10% scmod = 0000b 2.5 5 stop mode; v dd = 3 v 10% xt = 0v 0.5 3 stop mode; v dd = 5 v 10% scmod = 0100b 0.2 3 stop mode; v dd = 3 v 10% 0.1 2 notes: 1. data includes power consumption for subsystem clock oscillation. 2 . when the system clock control register, scmod, is set to 1001b, main system clock oscillation stops and the subsystem clock is used. 3. currents in the following circuits are not included; on-chip pull-up resistors, internal lcd voltage dividing resistors, output po rt drive currents .
S3C72I9/p72i9 s3p72 i9 otp 16- 5 1.5 mhz cpu clock 1.05 mhz 750 khz 15.6 khz main oscillator frequency (divided by 4) 4.2 mhz 3 mhz 6 mhz 1 2 3 4 5 6 7 supply voltage (v) cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) 1.8 v figure 1 6-2. standard operating voltage range
S3C72I9/p72i9 development tools 17- 1 17 development tools overview samsung provides a powerful and easy-to-use development support system in turnkey form. the development support system is configured with a host system, debugging tools, and support software. for the host system, any standard computer that operates with ms-dos as its operating system can be used. one type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, smds2+, for s3c7, s3c9, s3c8 families of microcontrollers. the smds2+ is a new and improved version of smds2. samsung also offers support software that includes debugger, as s embler, and a program for setting options. shine samsung host interface for in - c ircuit emulator, shine, is a multi-window based debugger for smds2+. shine provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. it has an advanced, multiple-windowed user interface that emphasizes ease of use. each window can be sized, moved, scrolled, highlighted, added, or removed completely. sama assembler the samsung arrangeable microcontroller (sam) assembler, sama, is a universal assembler, and generates object code in standard hexadecimal format. assembled program code includes the object code that is used for rom data and required smds program control data. to assemble programs, sama requires a source file and an auxiliary definition (def) file with device specific information. sasm 57 the sasm 57 is an relocatable assembler for samsung's s3c7 -series microcontrollers. the sasm 57 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. the sasm 57 supports macros and conditional assembly. it runs on the ms-dos operating system. it produces the relocatable object code only, so the user should link object file. object files can be linked with other object files and loaded into memory. hex2rom hex2rom file generates rom code from hex file which has been produced by assembler. rom code must be needed to fabricate a microcontroller which has a mask rom. when generating the rom code (.obj file) by hex2rom, the value 'ff' is filled into the unused rom area upto the maximum rom size of the target device automatically. target boards target boards are available for all s3c7 -series microcontrollers. all required target system cables and adapters are included with the device-specific target board. otp s one time programmable microcontroller ( otp) for the S3C72I9 microcontroller and otp programmer (gang) are now available.
development tools S3C72I9/p72i9 17- 2 bus smds2+ rs-232c pod probe adapter prom/otp writer unit ram break/display unit trace/timer unit sam4 base unit power supply unit ibm-pc at or compatible tb72i9 target board eva chip target application system figure 17-1. smds product configuration (smds2+)
S3C72I9/p72i9 development tools 17- 3 tb72i9 target board the tb72i9 target board is used for the S3C72I9 microcontroller. it is supported by the smds2+ development system. tb72i9 sm1264a + idle + stop 100-pin connector 25 1 reset to user_v cc off on j101 50-pin connector 1 64 33 32 mds xt1 xtal 74hc11 144 qfp s3e72i0 eva chip 1 36 gnd v cc figure 17-2. tb72i9 target board configuration
development tools S3C72I9/p72i9 17- 4 table 17-1. power selection settings for tb72i9 'to user_vcc' settings operating mode comments to user_v cc off on target system smds2/smds2+ tb72i9 v cc v ss v cc the smds2 /smds2+ supplies v cc to the target board (evaluation chip) and the target system. to user_v cc off on target system smds2+ tb72i9 external v cc v ss v cc the smds2 /smds2+ supplies v cc only to the target board (evaluation chip). the target system must have its own power supply.
S3C72I9/p72i9 development tools 17- 5 table 17-2. sub-clock selection settings for tb72i9 sub clock setting operating mode comments txi mds xtal no connection smds2/smds2+ 100 pin connector eva chip s3e72i0 x in x out set the xt in switch to ?mds? when the target board is connected to the smds2/smds2+. txi mds xtal target board eva chip s3e72i0 x in x out xtal set the xt in switch to ?xtal? when the target board is used as a standalone unit, and is not connected to the smds2/smds2+. idle led this led is on when the evaluation chip ( s3e72i0 ) is in idle mode. stop led this led is on when the evaluation chip ( s3e72i0 ) is in stop mode.
development tools S3C72I9/p72i9 17- 6 j102 p6.1/seg54/k5 p6.3/seg52/k7 p7.1/seg50 p7.3/seg48 p8.1/seg46 p8.3/seg44 p9.1/seg42 p9.3/seg40 seg38 seg36 seg34 seg32 seg30 seg28 seg26 seg24 seg22 seg20 seg18 seg16 seg14 seg12 seg10 seg8 seg6 p6.2/seg53/k6 p7.0/seg51 p7.2/seg49 p8.0/seg47 p8.2/seg45 p9.0/seg43 p9.2/seg41 seg39 seg37 seg35 seg33 seg31 seg29 seg27 seg25 seg23 seg21 seg19 seg17 seg15 seg13 seg11 seg9 seg7 seg5 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 50-pin dip connector j101 seg4 seg2 seg0 vlc4 vlc2 p0.0/ sck /k0 p0.2/si/k2 v dd x out test xt out p1.0/int0 p1.2/int2 p2.0/clo p2.2/lcdsy p3.1/tclo1 p3.3/tcl1 com1 com3 com5 com7 p4.1/com9 p4.3/com11 p5.1/com13 p5.3/com15 seg3 seg1 vlc5 vlc3 vlc1 p0.1/so/k1 p0.3/buz/k3 v ss x in xt in reset p1.1/int1 p1.3/int4 p2.1/lcdck p3.0/tclo0 p3.2/tcl0 com0 com2 com4 com6 p4.0/com8 p4.2/com10 p5.0/com12 p5.2/com14 p6.0/seg55/k4 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 50-pin dip connector figure 17-3. 5 0-pin connector s for tb72i9 target board 50-pin dip connector target system 50-pin dip connector j102 51 52 99 100 j101 1 2 3 4 target cable for 50-pin connector part name: (as50d-a) order cods: sm6305 j102 51 52 99 100 j101 1 2 3 4 figure 17-4. tb72i9 adapter cable for 100 qfp package ( S3C72I9 )

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