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ds04-21363-2e fujitsu semiconductor data sheet assp dual serial input pll frequency synthesizer mb15f72sp n description the fujitsu mb15f72sp is a serial input phase locked loop (pll) frequency synthesizer with a 1300 mhz and a 350 mhz prescalers. a 64/65 or a 128/129 for the 1300 mhz prescaler, and a 8/9 or a 16/17 for the 350 mhz pres- caler can be selected for the prescaler that enables pulse swallow operation. mb15f72sp has the same configuration with mb15f02 or mb15f02l. the bicmos process is used , as a result a supply current is typically 2.7 ma typ. at 2.7 v.the supply voltage range is from 2.4 v to 3.6 v. a refined charge pump supplies well-balanced output current with 1.5 ma and 6 ma selectable by serial data. the new package(bcc20) decreases a area of mb15f72sp more than 30 % comparing with the former bcc16 (for dual pll). mb15f72sp is ideally suited for wireless mobile communications, such as pdc n features ? high frequency operation:rf synthesizer: 1300 mhz max :if synthesizer: 350 mhz max ? low power supply voltage: v cc = 2.4 to 3.6 v ? ultra low power supply current:i cc = 2.7 ma typ. (v cc = vp = 2.7 v, sw if = sw rf = 0, ta = + 2 5 c, in if, rf locking state) ? direct power saving function:power supply current in power saving mode ty p . 0 . 1 m a (v cc = vp = 2.7 v, ta = +25 c) max. 10 m a (v cc = vp = 2.7 v) (continued) n packages 20-pin plastic tssop (fpt-20p-m06) 20-pad plastic bcc (lcc-20p-m04)
mb15f72sp 2 (continued) ? software selectable charge pump current: 1.5 ma/6.0 ma (typ.) ? dual modulus prescaler: 1300 mhz prescaler (64/65 or 128/129 )/350 mhz prescaler (8/9 or 16/17) ? 23 bit shift resister ? serial input 14-bit programmable reference divider: r = 3 to 16,383 ? serial input programmable divider consisting of: - binary 7-bit swallow counter: 0 to 127 - binary 11-bit programmable counter: 3 to 2,047 ? onCchip phase control for phase comparator ? built-in digital locking detector circuit to detect pll locking and unlocking. ? operating temperature: ta = C40 c to +85 c ? sireal data format compatible with mb15f02sl ? small package bcc20 (3.4 mm 3.6mm 0.8mm) n pin assignments osc in gnd fin if xfin if gnd if v ccif ps if vp if do if ld/fout clock data le fin rf xfin rf gnd rf v ccrf ps rf vp rf do rf 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 gnd do if 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 19 18 17 20 gnd if v ccif vp if fin if ps if gnd rf le fin rf v ccrf ps rf xfin rf xfin if osc in ld/fout do rf vp rf data clock (tssop-20) top view (bcc-20) top view (fpt-20p-m06) (lcc-20p-m04)
mb15f72sp 3 n pin description pin no. pin name i/o descriptions tssop bcc 119osc in i the programmable reference divider input. tcxo should be connected with a ac coupling capacitor. 220gnd ? ground for osc input buffer and the shift register circuit. 31 fin if i prescaler input pin for the if-pll. connection to an external vco should be via ac coupling. 42xfin if i prescaler complimentary input pin for the if-pll section. this pin should be grounded via a capacitor. 53gnd if ? ground for the if-pll section. 64v ccif ? power supply voltage input pin for the if-pll section(except for the charge pump circuit), the osc input buffer and the shift register circuit. when power is off, latched data of if-pll is lost. 75ps if i power saving mode control for the if-pll section. this pin must be set at l power-on. (open is prohibited.) ps if = h ; normal mode / ps if = l ; power saving mode 86vp if ? power supply voltage input pin for the if-pll charge pump. 97d oif o charge pump output for the if-pll section. phase characteristics of the phase detector can be reversed by fcbit. 10 8 ld/fout o lock detect signal output (ld)/phase comparator monitoring output (fout).the output signal is selected by lds bit in the serial data. lds bit = h ; outputs fout signal / lds bit = l ; outputs ld signal 11 9 d orf o charge pump output for the rf-pll section. phase characterstics of the phase detector can be reversed by fcbitt. 12 10 vp rf ? power supply voltage input pin for the rf-pll charge pump. 13 11 ps rf i power saving mode control for the rf-pll section. this pin must be set at l power-on. (open is prohibited.) ps rf = h ; normal mode / ps rf = l ; power saving mode 14 12 v ccrf ? power supply voltage input pin for the rf-pll section (except for the charge pump circuit). 15 13 gnd rf ? ground for the rf-pll section. 16 14 xfin rf i prescaler complimentary input pin for the rf-pll section. this pin should be grounded via a capacitor. 17 15 fin rf i prescaler input pin for the rf-pll. connection to an external vco should be via ac coupling. 18 16 le i load enable signal input(with the schmitt trigger circuit). when le is set h, data in the shift register is transferred to the corresponding latch according to the control bit in a serial data. 19 17 data i serial data input(with the schmitt trigger circuit). a data is transferred to the corresponding latch(if-ref. counter, if-prog. counter, rf-ref. counter, rf-prog. counter) according to the control bit in a serial data. 20 18 clock i clock input for the 23-bit shift register (with the schmitt trigger circuit). one bit of data is shifted into the shift register on a rising edge of the clock.
mb15f72sp 4 n block diagram ( ) clock data le ps rf xfin rf fin rf osc in fin if ps if fc if sw if lds v ccif gnd if fp if do if ld if t1 t2 t1 t2 fc rf sw rf lds do rf or ld / fout ld fr if fr rf fp if fp rf fr if fr rf fp rf c n 1 c n 2 and v ccrf gnd rf vp rf ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) 6 4 53 9 7 10 8 11 9 15 12 13 gnd ( ) 2 20 10 14 12 20 18 19 17 ( ) 18 16 13 11 16 14 17 15 1 19 3 1 xfin if ( ) 4 2 7 5 vp if ( ) 86 o : tssop ( ) : bcc intermittent mode control (if-pll) prescaler (if-pll) (8/9, 16/17 schmitt circuit 3 bit latch 7 bit latch 11 bit latch binary 7-bit swallow counter (if-pll) binary 11-bit pro- grammable counter(if-pll) phase comp. (if-pll) charge pump (if-pll) current switch lock det. (if-pll) 2 bit latch 14 bit latch 1 bit latch binary 14-bit pro- grammable ref. counter(if-pll) c/p setting counter selector latch selector 23-bit shift register prescaler (rf-pll) (64/65, 128/129) intermittent mode control (rf-pll) phase comp. (rf-pll) charge pump (rf-pll) current switch lock det. (rf-pll) 3 bit latch 7 bit latch 11 bit latch 2 bit latch 14 bit latch 1 bit latch schmitt circuit schmitt circuit binary 14-bit pro- grammable ref. counter(rf-pll)) c/p setting counter binary 7-bit swallow counter (rf-pll) binary 11-bit pro- grammable counter (rf-pll)
mb15f72sp 5 n absolute maximum ratings warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min. max. power supply voltage v cc - 0.5 4.0 v vp v cc 4.0 v input voltage v i - 0.5 v cc + 0.5 v output voltage ld/fout v o gnd v cc v do if , do rf v do gnd vp v storage temperature tstg - 55 + 125 c parameter symbol value unit remark min. typ. max. power supply voltage v cc 2.4 2.7 3.6 v v ccrf = v ccif vp v cc 2.7 3.6 v input voltage v i gnd ? v cc v operating temperature ta - 40 ?+ 85 c
mb15f72sp 6 n electrical characteristics (continued) (v cc = 2.4 v to 3.6 v, ta = - 40 c to + 85 c) parameter sym- bol condition value unit min. typ. max. power supply current i ccif * 1 if pll ? 1.1 ? ma i ccrf *2 rf pll ? 1.6 ? ma power saving current i psif ps if = ps rf = l ? 0.1 *8 10 m a i psrf ps if = ps rf = l ? 0.1 *8 10 m a operating frequency fin if *3 fin if if pll 50 ? 350 mhz fin rf *3 fin rf rf pll 100 ? 1300 mhz osc in f osc ? 3 ? 40 mhz input sensitivity fin if pfin if if pll, 50 w system - 15 ?+ 2dbm fin rf pfin rf rf pll, 50 w system - 15 ?+ 2dbm osc in v osc ? 0.5 ? v cc v p - p h level input voltage data, le, clock v ih schmitt trigger input 0.7 v cc + 0.4 ?? v l level input voltage v il schmitt trigger input ?? 0.3 v cc - 0.4 v h level input voltage ps if , ps rf v ih ? 0.7 v cc ?? v l level input voltage v il ? ?? 0.3 v cc v h level input current data, le, clock, ps if , ps rf i ih *4 ? - 1.0 ?+ 1.0 m a l level input current i il *4 ? - 1.0 ?+ 1.0 m a h level input current osc in i ih ? 0 ?+ 100 m a l level input current i il *4 ? - 100 ? 0 m a h level output voltage ld/fout v oh v cc = vp = 2.7 v , i oh = - 1 ma v cc - 0.4 ?? v l level output voltage v ol v cc = vp = 2.7 v , i ol = 1 ma ?? 0.4 v h level output voltage do if , do rf v doh v cc = vp = 2.7 v , i doh = - 0.5 ma vp - 0.4 ?? v l level output voltage v dol v cc = vp = 2.7 v , i dol = 0.5 ma ?? 0.4 v high impedance cutoff current do if , do rf i off v cc = vp = 2.7 v v off = 0.5 v to vp - 0.5 v ?? 2.5 na h level output current ld/fout i oh *4 v cc = vp = 2.7 v ??- 1.0 ma l level output current i ol v cc = vp = 2.7 v 1.0 ?? ma
mb15f72sp 7 (continued) (v cc = 2.4 v to 3.6 v, ta = - 40 c to + 85 c) parameter symbol condition value unit min. typ. max. h level output current do if do rf i doh *4 v cc = vp = 2.7 v, v doh = vp/2, ta = + 25 c cs bit = h ?- 6.0 ? ma cs bit = l ?- 1.5 ? ma l level output current do if do rf i dol v cc = vp = 2.7 v, v dol = vp/2, ta = + 25 c cs bit = h ? 6.0 ? ma cs bit = l ? 1.5 ? ma charge pump current rate i dol /i doh i domt *5 v do = vp / 2 ? 3 ? % vs. v do i dovd *6 0.5 v v do vp - 0.5 v ? 10 ? % vs.ta i dota *7 - 40 c ta + 85 c, v do = vp / 2 ? 10 ? % *1 : fin if = 270 mhz, fosc = 12.8 mhz, v ccif = vp if = 2.7 v, sw if = 0, ta = +25 c, in locking state. *2 : fin rf = 910 mhz, fosc = 12.8 mhz, v ccrf = vp rf = 2.7 v, sw rf = 0, ta = +25 c, in locking state. *3 : ac coupling. 1000pf capacitor is connected under the condition of min. operating frequency. *4 : the symbol C (minus) means direction of current flow. *5 : v cc = vp = 2.7 v, ta = +25 c (||i 3 | C |i 4 ||)/[(|i 3 | + |i 4 |)/2] 100(%) *6 : v cc = vp = 2.7 v, ta = +25 c (applied to each i dol , i doh ) [(||i 2 | C |i 1 ||)/2]/[(|i 1 | + |i 2 |)/2] 100(%) *7 : v cc = vp = 2.7 v, ta = +25 c (applied to each i dol , i doh ) [||i do( + 85 c) | C|i do(C40 c) ||/2]/[|i do( + 85 c) | + |i do(C40 c) |/2] 100(%) *8 : fosc = 12.8 mhz, v ccrf = vp rf = v ccif = 2.7 v, ta = +25 c i 1 i 1 i 3 i 2 i 4 i dol i doh 0.5 vp / 2 vp vp - 0.5 charge pump output voltage (v)
mb15f72sp 8 n functional description 1. pulse swallow function : f vco = [(p n) + a] f osc ? r f vco : output frequency of external voltage controlled oscillator (vco) p : preset divide ratio of dual modulus prescaler (8 or 16 for if-pll, 64 or 128 for rf-pll) n : preset divide ratio of binary 11-bit programmable counter (3 to 2,047) a : preset divide ratio of binary 7-bit swallow counter (0 a 127, a < n) f osc : reference oscillation frequency (osc in input frequency) r : preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383) 2. serial data input serial data is entered using three pins, data pin, clock pin, and le pin. programmable dividers of if/rf-pll sec- tions, and programmable reference dividers of if/rf-pll sections are controlled individually. serial data of binary data is entered through data pin. on a rising edge of clock, one bit of serial data is transferred into the shift register. on a rising edge of load enable signal, the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting. (1) shift register configuration the programmable reference counter for the if-pll the programmable reference counter for the rf-pll the programmable counter and the swallow counter for the if-pll the programmable counter and the swallow counter for the rf-pll cn1 0 1 0 1 cn2 0 0 1 1 (lsb) (msb) cs : charge pump currnet select bit r1 to r14 : divide ratio setting bits for the programmable reference counter (3 to 16,383) t1, t2 : test purpose bit cn1, cn2 : control bit x : dummy bits (set 0 or 1) note : data input with msb first. ? programmable reference counter 1 2 34567891011121314151617181920212223 cn1 cn2 t1 t2 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 cs x x x x data flow
mb15f72sp 9 (2) data setting ? binary 14-bit programmable reference counter data setting (r1 to r14) note : divide ratio less than 3 is prohibited. ? binary 11-bit programmable counter data setting (n1 to n11) note : divide ratio less than 3 is prohibited. ? binary 7-bit swallow counter data setting (a1 to a7) divide ratio r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 300000000000011 4 16383 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 divide ratio n11 n10 n9 n8 n7 n6 n5 n4 n3 n2 n1 3 0 0000000 0 11 4 2047 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 divide ratioa7 a6a5a4a3a2a1 0 0 000000 1 127 0 1 0 1 0 1 0 1 0 1 0 1 1 1 (lsb) (msb) ? programmable counter a1 to a7 : divide ratio setting bits for the swallow counter (0 to 127) n1 to n11 : divide ratio setting bits for the programmable counter (3 to 2,047) lds : ld/fout signal select bit sw if /sw rf : divide ratio setting bit for the prescaler (if : sw if ,rf : sw rf ) fc if /fc rf : phase control bit for the phase detector (if: fc if , rf: fc rf ) cn1, cn2 : control bit note : data input with msb first. 1 2 3 4 5 6 7 8 9 101112131415161718192021 22 23 cn1 cn2 lds sw if / sw rf fc if / fc rf a1 a2 a3 a4 a5 a6 a7 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 data flow
mb15f72sp 10 ? prescaler data setting (sw) ? test purpose bit setting (t1, t2) ? phase comparator phase switching data setting (fc if , fc rf ) z : high-impedance depending upon the vco and lpf polarity, fc bit should be set. divide ratio sw = 1 sw = 0 prescaler divide ratio if-pll 8 / 916 / 17 prescaler divide ratio rf-pll 64 / 65 128 / 129 ? charge pump current setting (cs) ? ld/fout output select data setting (lds) current value cs ld/fout output signal lds 6.0 ma 1 fout signal 1 1.5 ma 0 ld signal 0 ld/fout pin state t1 t2 outputs fr if .0 0 outputs fr rf .1 0 outputs fp if .0 1 outputs fp rf .1 1 phase comparator input fc if = = = = 1 fc rf = 1 fc if = = = = 0 fc rf = 0 do if do rf do if do rf fr > fp h l fr < fp l h fr = fp z z (1) (2) (1) vco polarity fc = 1 (2) vco polarity fc = 0 note : give attention to the polarity for using active type lpf. vco output frequency lpf output voltage max. high vco output frequency
mb15f72sp 11 3. power saving mode (intermittent mode control circuit) the intermittent mode control circuit reduces the pll power consumption. by setting the ps pins low, the device enters into the power saving mode, reducing the current consumption. see the electrical characteristics chart for the specific value. the phase detector output, do, becomes high impedance. for the dual pll, the lock detector, ld, is as shown in the ld output logic table. setting the ps pins high, releases the power saving mode, and the device works normally. the intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. when the pll is returned to normal operation, the phase comparator output signal is unpredictable. this is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparator output, resulting in a vco frequency jump and an increase in lockup time. to prevent a major vco frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. notes when power (v cc ) is first applied, the device must be in standby mode, ps if = ps rf = low, for at least 1 m s. ps pins must be set at l for power-on. status ps if /ps rf pins normal mode h power saving mode l on off v cc clock data le ps if ps rf (1) (2) (3) (1) ps if = ps rf = l (power saving mode) at power-on (2) set serial data 1 m s later after power supply remains stable (v cc > 2.2 v). (3) release power saving mode (ps if , ps rf : l ? h) 100 ns later after setting serial data. t v 3 1 m s t ps 3 100 ns
mb15f72sp 12 4. serial data input timing frequency multiplier setting is performed through a serial interface using the data pin, clock pin, and le pin. setting data is read into the shift register at the rise of the clock signal, and transferred to a latch at the rise of the le signal. the following diagram shows the data input timing. lsb msb clock data le t 7 t 1 t 2 t 3 t 4 t 5 t 6 1st data invalid data control bit 2nd data parameter min. typ. max. unit t 1 20 ?? ns t 2 20 ?? ns t 3 30 ?? ns t 4 30 ?? ns parameter min. typ. max. unit t 5 100 ?? ns t 6 20 ?? ns t 7 100 ?? ns note : le should be l when the data is transferred into the shift register.
mb15f72sp 13 n phase comparator output waveform fr if / fr rf fp if / fp rf ld do if / do rf t wu t wl d o if / do rf z h l z h l ? ld output logic notes: phase error detection range = C2 p to +2 p pulses on do if /do rf signals are output to prevent dead zone during locking state. ld output becomes low when phase error is t wu or more. ld output becomes high when phase error is t wl or less and continues to be so for three cycles or more. t wu and t wl depend on osc in input frequency as follows. t wu > 2/fosc : e.g. t wu > 156.3 ns when fosc = 12.8 mhz t wu < 4/fosc : e.g. t wl < 312.5 ns when fosc = 12.8 mhz if-pll section rf-pll section ld output locking state/power saving state locking state/power saving state h locking state/power saving state unlocking state l unlocking state locking state/power saving state l unlocking state unlocking state l (fc bit = 1) (fc bit = 0)
mb15f72sp 14 n test circuit (for measuring input sensitivity fin/osc in ) 10987654321 11 12 13 14 15 16 17 18 19 20 s.g. s.g. s.g. 50 w 50 w 50 w 1000 pf 1000 pf 1000 pf 1000 pf 1000 pf 0.1 m f 0.1 m f 0.1 m f 0.1 m f v ccrf v ccif vp if vp rf fout osc in clock data le gnd fin if fin rf xfin rf xfin if gnd if gnd rf v ccif v ccrf ps if ps rf vp if vp rf do if do rf ld/ fout note : terminal number shows that of tssop-20. oscilloscope controller (divide ratio setting)
mb15f72sp 15 n typical characteristics 1. fin input sensitivity 10 0 - 20 - 10 - 30 - 25 - 15 - 5 5 - 40 - 50 - 45 - 35 0 200 400 600 800 1000 1200 1400 1600 1800 2000 v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v ta = + 25 c rf-pll input sensitivity - input frequency input frequency fin rf (mhz) input sensitivity pfin rf (dbm) if-pll input sensitivity - input frequency input frequency fin if (mhz) input sensitivity pfin if (dbm) spec 10 0 - 20 - 10 - 30 - 25 - 15 - 5 5 - 40 - 50 - 45 - 35 0 100 50 150 350 300 250 200 650 600 550 500 450 400 700 v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v ta = + 25 c spec
mb15f72sp 16 2. osc in input sensitivity 10 0 - 30 - 10 - 20 - 40 - 50 - 60 0 20 40 100 80 60 200 180 160 140 120 220 v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v ta = + 25 c input sensitivity vs input frequency input frequency f osc (mhz) input sensitivity v osc (dbm) spec
mb15f72sp 17 3. rf-pll do output current 10.0 - 10.0 1.0 0.0 ta = + 25 c v cc = vp = 2.7 v i dol i doh 0.0 2.0 2.7 10.0 - 10.0 0.0 ta = + 25 c v cc = vp = 2.7 v i dol i doh 0.0 1.0 2.0 2.7 i do - v do charge pump output current i do (ma) charge pump output voltage v do (v) i do - v do charge pump output current i do (ma) charge pump output voltage v do (v) ? 1.5 ma mode ? 6.0 ma mode
mb15f72sp 18 4. if-pll do output current 10.0 - 10.0 0.0 ta = + 25 c v cc = vp = 2.7 v i dol i doh 0.0 1.0 2.0 2.7 10.0 - 10.0 1.0 ta = + 25 c v cc = vp = 2.7 v 0.0 i dol i doh 0.0 2.0 2.7 i do - v do charge pump output current i do (ma) charge pump output voltage v do (v) i do - v do charge pump output current i do (ma) charge pump output voltage v do (v) ? 1.5 ma mode ? 6.0 ma mode
mb15f72sp 19 5. fin input impedance 266.06 w - 661.69 w 100 mhz 21.406 w - 146.27 w 500 mhz 11.1 w - 62.982 w 1 ghz 10.35 w - 38.861 w 1.3 ghz 1 : 2 : 3 : 4 : start 100.000 000 mhz stop 1 500.000 000 mhz 2 3 4 1 712.91 w - 967.81 w 50 mhz 251.59 w - 650.97 w 100 mhz 40.648 w - 241.14 w 300 mhz 20.391 w - 141.98 w 500 mhz 1 : 2 : 3 : 4 : start 50.000 000 mhz stop 500.000 000 mhz 3 4 2 1 fin rf input impedance fin if input impedance v cc = 2.7 v v cc = 2.7 v
mb15f72sp 20 6. osc in input impedance 10.693 k w - 11.664 k w 3 mhz 1.8725 k w - 6.3285 k w 10 mhz 124.25 w - 1.6726 k w 40 mhz 31.188 w - 664.28 w 100 mhz 1 : 2 : 3 : 4 : start 3.000 000 mhz stop 100.000 000 mhz 3 4 2 1 osc in input impedance v cc = 2.7 v
mb15f72sp 21 n reference information (for lock-up time, phase noise and reference leakage) (continued) s.g. osc in fin vco d o lpf test circuit spectrum analyzer 2.2 k w 0.047 pf 1.0 k w 2200 pf 4700 pf atten vavg 72 center span 200.0 khz 680.0000 mhz rbw 1.0 khz swp vbw 1.0 khz 500 ms d mkr - 73.67 db 10 db rl 25.0 khz 0 dbm 10 db / d mkr 25.0 khz - 73.67 db atten vavg 23 center span 20.00 khz 680.0000 mhz rbw 100 hz swp vbw 100 hz 1.60 s d mkr - 55.00 db 10 db rl 5.37 khz 0 dbm 10 db / d mkr 5.37 khz - 55.00 db f vco = 680 mhz k v = 50 mhz/v fr = 25 khz f osc = 14.4 mhz lpf v cc = 3.0 v v vco = 2.2 v ta = + 25 c cp : 6 ma mode ? pll reference leakage ? pll phase noise
mb15f72sp 22 (continued) 755.004250 mhz 755.000250 mhz 754.996250 mhz - 822 m s 4.178 ms 1.000 ms / div 9.178 ms 680.004000 mhz 680.000000 mhz 679.996000 mhz - 822 m s 4.178 ms 1.000 ms / div 9.178 ms - 822 m s 4.178 ms 1.000 ms / div 9.178 ms - 822 m s 4.178 ms 1.000 ms / div 9.178 ms 780.00 mhz 680.00 mhz 580.00 mhz 855.00 mhz 755.00 mhz 655.00 mhz ? pll lock up time ? pll lock up time 680 mhz ? 755 mhz within 1 khz lch ? hch 1.244 ms 755 mhz ? 680 mhz within 1 khz hch ? lch 1.133 ms
mb15f72sp 23 n application example 0.1 m f 18 17 20 19 16 15 14 13 12 11 34 12 5678910 1000 pf 1000 pf output 2.7 v mb15f72sp 1000 pf 1000 pf 1000 pf 2.7 v 0.1 m f 0.1 m f output lock det. vco lpf vco lpf tcxo do rf ps rf vp rf xfin rf gnd rf v ccrf fin rf le data clock do if ps if vp if ld/fout v ccif fin if xfin if gnd if osc in gnd 2.7 v 0.1 m f 2.7 v from controller notes : clock, data, le : schmitt trigger circuit is provided(insert a pull-down or pull-up registor to prevent oscillation when open-circuit in the input). terminal number shows that of tssop-20.
mb15f72sp 24 n usage precautions (1) v ccrf , vp rf , v ccif and vp if must equal equal voltage. even if either rf-pll or if-pll is not used, power must be supplied to both v ccrf , vp rf , v ccif and vp if to keep them equal. it is recommended that the non-use pll is controlled by power saving function. (2) to protect against damage by electrostatic discharge, note the following handling precautions: -store and transport devices in conductive containers. -use properly grounded workstations, tools, and equipment. -turn off power before inserting or removing this device into or from a socket. -protect leads with conductive sheet, when transporting a board mounted device. n ordering information part number package remarks mb15f72sppft 20-pin plastic tssop (fpt-20p-m06) MB15F72SPPV 20-pad plastic bcc (lcc-20p-m04)
mb15f72sp 25 n package dimensions (continued) 20-pin plastic tssop (fpt-20p-m06) c 1999 fujitsu limited f20026s-2c-2 6.50?.10(.256?004) * 4.40?.10 6.40?.20 (.252?008) (.173?004) * 0.10(.004) 0.65(.026) 0.24?.08 (.009?003) 1 10 20 11 "a" 0.17?.05 (.007?002) m 0.13(.005) details of "a" part 0~8 (.018/.030) 0.45/0.75 (0.50(.020)) 0.25(.010) (.041?002) 1.05?.05 (mounting height) 0.07 +0.03 ?.07 +.001 ?003 .003 (stand off) lead no. index dimensions in mm (inches) n ote 1 ) * : these dimensions do not include resin protrusion. note 2 ) pins width and pins thickness include plating thickness.
mb15f72sp 26 (continued) c 1999 fujitsu limited c20055s - 1c - 1 3.60?.10(.142?004) 11 16 16 11 16 1 6 3.40?.10 (.134?004) index area 0.05(.002) 0.80(.031)max (mounting height) 0.085?.04 (.003?002) (stand off) 0.25?.10 (.010?004) typ 0.50(.020) 3.00(.118)typ 2.80(.110)ref typ 0.50(.020) (.010?004) 0.25?.10 2.70(.106) typ "d" "b" "a" "c" 0.60?.10 (.024?004) 0.50?.10 (.020?004) details of "a" part (.020?004) 0.50?.10 0.30?.10 (.012?004) details of "b" part details of "c" part (.020?004) 0.50?.10 (.024?004) 0.60?.10 c0.20(.008) details of "d" part 0.40?.10 (.016?004) 0.30?.10 (.012?004) dimensions in mm (inches) 20-pad plastic bcc (lcc-20p-m04)
mb15f72sp fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka, nakahara-ku, kawasaki-shi, kanagawa 211-8588, japan tel: +81-44-754-3763 fax: +81-44-754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, usa tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fujitsu-fme.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmap.com.sg/ f0002 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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