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publication number 26842 revision b amendment +3 issue date november 2, 2005 am29pdl129h data sheet retired product this product has been retired and is not avai lable for designs. for new and current designs, s29pl129j supersedes am29pdl129h and is the factory-recommended migration path. please refer to the s29pl129j datasheet for specifications and ordering information. availability of this document is retained for reference and historical purposes only. july 2003 the following document specifies spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that originally developed the specification, these produc ts will be offered to customers of both amd and fujitsu. continuity of specifications there is no change to this datasheet as a result of offering the device as a spansion product. any changes that have been made are the result of n ormal datasheet improvement and are noted in the document revision summary, where supported. future routine revisions will occur when appro- priate, and changes will be noted in a revision summary. continuity of ordering part numbers amd and fujitsu continue to support existing part numbers beginning with ?am? and ?mbm?. to order these products, please use only the orderi ng part numbers listed in this document. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions.
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publication number: 26842 rev: b amendment/ +3 issue date: november 2, 2005 am29pdl129h 128 megabit (8 m x 16-bit) cmos 3.0 volt-only, page mode simultaneous read/write fl ash memory with enhanced versatileio tm control and dual chip enable inputs distinctive characteristics architectural advantages 128 mbit page mode device ? page size of 8 words: fast page read access from random locations within the page dual chip enable inputs ? two ce# inputs control selection of each half of the memory space single power s upply operation ? full voltage range: 2.7 to 3.6 volt read, erase, and program operations for battery-powered applications simultaneous read/write operation ? data can be continuously read from one bank while executing erase/program functions in another bank ? zero latency switching from write to read operations flexbank architecture ? 4 separate banks, with up to two simultaneous operations per device ? bank 1a: 48 mbit (32 kw x 96) ? bank 1b: 16 mbit (4 kw x 8 and 32 kw x 31) ? bank 2a: 16 mbit (4 kw x 8 and 32 kw x 31) ? bank 2b: 48 mbit (32 kw x 96) enhanced versatilei/o tm (v io ) control ? output voltage generated and input voltages tolerated on all control inputs and i/os is determined by the voltage on the v io pin ?v io options at 1.8 v and 3 v i/o secsi tm (secured silicon) sector region ? up to 128 words accessible through a command sequence ? up to 64 factory-locked words ? up to 64 customer-lockable words both top and bottom boot blocks in one device manufactured on 0.13 m process technology 20-year data retention at 125c minimum 1 million erase cy cle guarantee per sector performance characteristics high performance ? page access times as fast as 20 ns ? random access times as fast as 55 ns power consumption (typical values at 10 mhz) ? 45 ma active read current ? 15 ma program/erase current ? 1 a typical standby mode current software features software command-set compatible with jedec 42.4 standard ? backward compatible with am29f and am29lv families cfi (common flash interface) complaint ? provides device-specific information to the system, allowing host software to easily reconfigure for different flash devices erase suspend / erase resume ? suspends an erase operation to allow read or program operations in other sectors of same bank unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences hardware features ready/busy# pin (ry/by#) ? provides a hardware method of detecting program or erase cycle completion hardware reset pin (reset#) ? hardware method to reset the device to reading array data wp#/acc (write protect/acceleration) input ?at v il , hardware level protection for the first and last two 4k word sectors. ?at v ih , allows removal of sector protection ?at v hh , provides accelerated programming in a factory setting persistent sect or protection ? a command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector ? sectors can be locked and unlocked in-system at v cc level password sector protection ? a sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password package options ? 80-ball fine-pitch bga ? multi chip packages (mcp) this product has been retired and is not available for designs . for new and current designs, s 29pl129j supersedes am29pdl129h a nd is the factory-recom- mended migration path. please refer to the s 29pl129j datasheet for specific ations and ordering information. availability of thi s document is retained for reference and historical purposes only.
2 am29pdl129h november 2, 2005 general description the am29pdl129h is a 128 mbit, 3.0 volt-only page mode and simultaneous read/write flash memory device orga- nized as 8 mwords. the device is offered in an 80-ball fine- pitch bga package, and various multi-chip packages. the word-wide data (x16) appears on dq15-dq0. this device can be programmed in-system or in standard eprom pro- grammers. a 12.0 v v pp is not required for write or erase op- erations. the device offers fast page access times of 20 to 30 ns, with corresponding random access times of 55 to 85 ns, respec- tively, allowing high speed microprocessors to operate with- out wait states. to eliminate bus contention the device has separate chip enable (ce1#, ce2#), write enable (we#) and output enable (oe#) controls. dual chip enables allow ac- cess to two 64 mbit partitions of the 128 mbit memory space. simultaneous read/write operation with zero latency the simultaneous read/write architecture provides simul- taneous operation by dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. the de- vice can improve overall system performance by allowing a host system to program or erase in one bank, then immedi- ately and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time). this releases the system from waiting for the completion of a program or erase operation, greatly improv- ing system performance. the device can be organized in both top and bottom sector configurations. the banks are organized as follows: page mode features the page size is 8 words. after initial page access is accom- plished, the page mode operation provides fast read access speed of random locations within that page. standard flash memory features the device requires a single 3.0 volt power supply (2.7 v to 3.6 v or 2.7 v to 3.3 v) for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. the device is entirely command set compatible with the jedec 42.4 single-power-supply flash standard . com- mands are written to the command register using standard microprocessor write timing. register contents serve as in- puts to an internal state-mach ine that controls the erase and programming circuitry. write cycles also internally latch ad- dresses and data needed for the programming and erase operations. reading data out of the device is similar to read- ing from other flash or eprom devices. device programming occurs by executing the program com- mand sequence. the unlock by pass mode facilitates faster programming times by requiring on ly two write cycles to pro- gram data instead of four. device erasure occurs by execut- ing the erase command sequence. the host system can detect w hether a program or erase op- eration is complete by reading the dq7 (data# polling) and dq6 (toggle) status bits . after a program or erase cycle has been completed, the device is ready to read array data or ac- cept another command. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data con- tents of other sect ors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc de- tector that automatically inhi bits write operations during power transitions. the hardwar e sector protection feature disables both program and erase operations in any combina- tion of sectors of memory. this can be achieved in-system or via programming equipment. the erase suspend/erase resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. true background erase can thus be achieved. if a read is needed from the secsi sector area (one time pro- gram area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. the device offers two power-saving features. when ad- dresses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode. power con- sumption is greatly reduced in both these modes. amd?s flash technology combined years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effe ctiveness. the device electri- cally erases all bits within a sector simultaneously via fowler-nordheim tunneling. the data is programmed using hot electron injection. note: the next-generation s29pl129j will have a different bank configuration, as follows: chip enable configuration ce1# control ce2# control bank 1a 48 mbit (32 kw x 96) bank 2a 16 mbit (4 kw x 8 and 32 kw x 31) bank 1b 16 mbit (4 kw x 8 and 32 kw x 31) bank 2b 48 mbit (32 kw x 96) chip enable configuration ce1# control ce2# control bank 1a 16 mbit (4 kw x 8 and 32 kw x 31) bank 2a 48 mbit (32 kw x 96) bank 1b 48 mbit (32 kw x 96) bank 2b 16 mbit (4 kw x 8 and 32 kw x 31)
november 2, 2005 am29pdl129h 3 table of contents product selector guide . . . . . . . . . . . . . . . . . . . . . 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 simultaneous operation block diagram . . . . . . . 6 connection diagrams . . . . . . . . . . . . . . . . . . . . . . 7 pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ordering information . . . . . . . . . . . . . . . . . . . . . . . 9 device bus operations . . . . . . . . . . . . . . . . . . . . 10 table 1. am29pdl129h device bus operations ...........................10 random read (non- page read) ........................................... 10 page mode read .................................................................... 10 table 2. page select .......................................................................10 simultaneous operation ......................................................... 10 table 3. bank select .......................................................................11 table 4. am29pdl129h sector architecture ..................................12 table 5. addresses .......................................................................19 table 6. autoselect codes (high voltage method) ........................19 table 7. am29pdl129h boot sect or/sector block addresses for protection/unprotection ce1# control ...................................................................................20 table 8. am29pdl129h boot sect or/sector block addresses for protection/unprotection ce2# control ...................................................................................20 table 9. sector protection schemes ...............................................21 write protect (wp#) ................................................................ 21 persistent protection bit lock ................................................. 21 high voltage sector protec tion .............................................. 21 figure 1. ......................................................................................... 21 temporary sector unprotect .................................................. 21 figure 2. ......................................................................................... 21 flash memory region ............................................................ 21 factory-locked area (64 words) ............................................ 21 customer-lockable area (6 4 words) ...................................... 22 figure 3. secsi sector protection algorithm................................... 23 secsi sector protection bits ................................................... 24 figure 4. secsi sector protect verify.............................................. 24 common flash memory interfac e (cfi) . . . . . . . 24 command definitions . . . . . . . . . . . . . . . . . . . . . 27 enter /exit command seq uence ............................................ 27 figure 5. ......................................................................................... 27 ppb lock bit status .............................................................. 27 table 14. memory array command definitions ............................. 28 table 15. sector protection command definitions ........................ 29 absolute maximum ratings. . . . . . . . . . . . . . . . . 30 figure 6. maximum negative overshoot waveform ...................... 30 figure 7. maximum positive overshoot waveform........................ 30 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 31 test conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 8. test setup, vio = 2.7 ? 3.6 v........................................ 32 figure 9. input waveforms and measurement levels ................... 32 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33 ce1#/ce2# timing ................................................................. 33 figure 10. timing diagram for alternating between ce1# and ce2# control............................................................................................ 33 read-only operations ........................................................... 33 figure 11. read operation timings ............................................... 34 figure 12. page read operation timings...................................... 34 hardware reset (reset#) .................................................... 35 figure 13. reset timings ............................................................... 35 erase and program operations .............................................. 36 figure 14. program operation timings.......................................... 37 figure 15. accelerated program timing diagram.......................... 37 figure 16. chip/sector erase operation timings .......................... 38 figure 17. back-to-back read/write cycle timings ...................... 39 figure 18. data# polling timings (during embedded algorithms). 39 figure 19. toggle bit timings (d uring embedded algorithms)...... 40 figure 20. dq2 vs. dq6................................................................. 40 temporary sector unprotect .................................................. 41 figure 21. temporary sector u nprotect timing diagram .............. 41 figure 22. sector/sector block prot ect and unprotect timing diagram 42 alternate ce# controlled erase and program operations ..... 43 figure 23. alternate ce# cont rolled write (erase/program) operation timings.......................................................................... 44 erase and programming performance. . . . . . . . 45 latchup characteristics . . . . . . . . . . . . . . . . . . . . 45 bga ball capacitance . . . . . . . . . . . . . . . . . . . . . 45 data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 revision summary . . . . . . . . . . . . . . . . . . . . . . . . 46
4 am29pdl129h november 2, 2005 product selector guide block diagram note: ry/by# is an open drain output. part number am29pdl129h speed option v cc , v io = 2.7?3.6 v 53 63 v cc = 2.7?3.6 v, v io = 1.65?1.95 v 68 88 max access time, ns (t acc )55 65 65 85 max ce# access, ns (t ce )6070 max page access, ns (t pac c ) 20 25 30 30 max oe# access, ns (t oe ) v cc v ss state control command register pgm voltage generator v cc detector timer erase voltage generator input/output buffers sector switches chip enable output enable logic y-gating cell matrix address latch y-decoder x-decoder data latch reset# ry/by# (see note) a21?a3 a2?a0 ce1# we# dq15?dq0 v io oe# ce2#
november 2, 2005 am29pdl129h 5 simultaneous operation block diagram v cc v ss bank 1a address bank 1b address a21?a0 reset# we# ce1# dq0?dq15 ce2# state control & command register ry/by# bank 1a x-decoder oe# dq15?dq0 status control a21?a0 a21?a0 a21?a0 a21?a0 dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 mux mux mux bank 1b x-decoder y-gate bank 2a x-decoder bank 2b x-decoder y-gate bank 2a address bank 2b address ce1#=l ce2#=h ce1#=h ce2#=l wp#/acc
6 am29pdl129h november 2, 2005 connection diagrams note: on s29pl129j, g1= nc and j1= ce2# b2 d2 e2 f2 g2 h2 j2 d3 e3 f3 g3 h3 j3 d4 e4 f4 g4 h4 j4 d5 e5 f5 g5 h5 j5 d6 e6 f6 g6 h6 j6 b7 d7 e7 f7 g7 h7 j7 nc dq15 a16 a15 a14 a12 a13 nc dq14 dq13 dq7 a11 a10 a8 a9 dq12 v cc dq5 a19 a21 reset# we# dq10 dq11 dq2 a20 a18 wp#/acc ry/by# dq8 dq9 dq0 a5 a6 a17 a7 ce1# oe# k2 k3 k4 k5 k6 k7 v ss dq6 dq4 dq3 dq1 v ss a0 a1 a2 a4 a3 nc b1 d1 e1 f1 g1 h1 j1 v io nc ce2# nc nc nc nc nc a1 nc b8 d8 c2 c3 c4 c5 c6 c7 a2 a7 nc nc c1 c8 e8 f8 g8 h8 j8 nc nc k1 nc k8 nc l2 l7 nc nc m2 m7 nc nc l1 nc l8 nc m1 nc m8 nc v ss v io nc nc nc nc a8 nc 80-ball fine-pitch bga top view, balls facing down
november 2, 2005 am29pdl129h 7 pin description a21?a0 = 22-bit address bus for 2 x 64 mb de- vice. a9 supports 12 v autoselect in- puts. dq15?dq0 = 16-bit data inputs/outputs/float ce1#, ce2# = chip enable inputs. ce1# controls the 64 mb in banks 1a and 1b. ce2# controls the 64 mb in banks 2a and 2b. oe# = output enable input we# = write enable v ss = device ground nc = pin not connected internally ry/by# = ready/busy output and open drain. when ry/by#= v ih , the device is ready to accept read operations and commands. when ry/by#= v ol , the device is either executing an em- bedded algorithm or the device is executing a hardware reset opera- tion. wp#/acc = write protect/acceleration input. when wp/acc#= v il , the highest and lowest two 4k-word sectors are write protected regardless of other sector protection configurations. when wp/acc#= v ih , these sector are unprotected unless the dyb or ppb is programmed. when wp/ acc#= 12v, program and erase op- erations are accelerated. v io = input/output buffer power supply (1.65 v to 1.95 v or 2.7 v to 3.6 v) v cc = chip power supply (2.7 v to 3.6 v) reset# = hardware reset pin logic symbol 22 16 dq15?dq0 a21?a0 ce1# oe# we# reset# ry/by# wp#/acc v io (v ccq ) ce2#
8 am29pdl129h november 2, 2005 ordering information standard products amd standard products are available in several packages and o perating ranges. the order number (valid combination) is formed by a combination of the following: valid combinations valid combinations list configurations planned to be supported in volume for this device. consult th e local amd sales office to con- firm availability of specific valid combinations and to check on newly released combinations. note: for the am29pdl129h, the last digit of the speed grade specifies the v io range of the device. speed grades ending in 3 (for example: 53, 63) indicate a 3 volt v io range. speed grades ending in 8 (for example: 68, 88) indicate a 1.8 volt v io range. contact amd or fujitsu for availability of 1.8v v io range devices. am29pdl129 h 53 vk i optional processing blank = standard processing n = 16-byte esn devices (contact an amd representative for more information) temperature range i = industrial (?40 c to +85 c) package type vk = 80-ball fine-pitch ball grid array 0.8 mm pitch, 11.5 x 9 mm package (vbb080) speed option see product selector guide and valid combinations process technology h = 0.13 m device number/description am29pdl129h 128 megabit (8 m x 16-bit) cmos flash memory 3.0 volt-only read, program, and erase dual chip enable inputs valid combinations for bga packages order number package marking speed (ns) v io range am29pdl129h53 vki pd129h53v i 55 2.7?3.6 v am29pdl129h63 pd129h63v 65 2.7?3.6 v am29pdl129h68 pd129h68v 65 1.65?1.95 v am29pdl129h88 pd129h88v 85 1.65?1.95 v
november 2, 2005 am29pdl129h 9 device bus operations table 1. am29pdl129h device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 11.5?12.5 v, v hh = 8.5?9.5 v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out notes: 1. the sector protect and sector unpr otect functions may also be implem ented via programming equipment. . 2. wp#/acc must be high when writing to sectors sa1-133, sa1-134, sa2-0, or sa2-1. random read (non-page read) address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from the stable ad- dresses and stable ce# to valid data at the output in- puts. the output enable access time is the delay from the falling edge of the oe# to valid data at the output inputs (assuming the addresses have been stable for at least t acc ?t oe time). page mode read the device is capable of fast page mode read and is compatible with the page mode mask rom read oper- ation. this mode provides faster read access speed for random locations within a page. address bits a21? a3 select an 8-word page, and address bits a2?a0 se- lect a specific work within that page. this is an asyn- chronous operation with the microprocessor supplying the specific word location. the random or initial page access is t acc or t ce and subsequent page read accesses (as long as the loca- tions specified by the microprocessor fall within that page) are t pac c . when ce1# and ce2# are deas- serted (ce1#=ce2#=v ih ), the reassertion of ce1# or ce2# for subsequent access has access time of t acc or t ce . here again, ce1#/ce2# selects the device and oe# is the output control and should be used to gate data to the output inputs if the device is selected. fast page mode accesses are obtained by keeping a21? a3 constant and changing a2 to a0 to select the spe- cific word within that page. table 2. page select simultaneous operation in addition to the conventional features (read, pro- gram, erase-suspend read, and erase-suspend pro- gram), the device is capable of reading data from one bank of memory while a program or erase operation is in progress in another bank of memory (simultaneous operation), the bank can be selected by bank ad- dresses (a21?a20) with zero latency. the simultaneous operation can execute multi-func- tion mode in the same bank. operation ce1# ce2# oe# we# reset# wp#/acc addresses (a21?a0) dq15? dq0 read lh lh h x a in d out hl write lh hl h x (note 2) a in d in hl standby v io 0.3 v v io 0.3 v xx v io 0.3 v xxhigh-z output disable l l h h h x x high-z reset x x x x l x x high-z temporary sector unprotect (high voltage) xxxxv id xa in d in word a2 a1 a0 word 0 0 0 0 word 1 0 0 1 word 2 0 1 0 word 3 0 1 1 word 4 1 0 0 word 5 1 0 1 word 6 1 1 0 word 7 1 1 1
10 am29pdl129h november 2, 2005 table 3. bank select bank ce1# ce2# a21?a20 bank 1a 0 1 00, 01, 10 bank 1b 0 1 11 bank 2a 1 0 00 bank 2b 1 0 01, 10, 11
november 2, 2005 am29pdl129h 11 table 4. am29pdl129h sector architecture bank sector ce1# ce2# sector address (a21- a12) sector size (kwords) address range (x16) bank 1a sa1-0 0 1 0000000xxx 32 000000h?007fffh sa1-1 0 1 0000001xxx 32 008000h?00ffffh sa1-2 0 1 0000010xxx 32 010000h?017fffh sa1-3 0 1 0000011xxx 32 018000h?01ffffh sa1-4 0 1 0000100xxx 32 020000h?027fffh sa1-5 0 1 0000101xxx 32 028000h?02ffffh sa1-6 0 1 0000110xxx 32 030000h?037fffh sa1-7 0 1 0000111xxx 32 038000h?03ffffh sa1-8 0 1 0001000xxx 32 040000h?047fffh sa1-9 0 1 0001001xxx 32 048000h?04ffffh sa1-10 0 1 0001010xxx 32 050000h?057fffh sa1-11 0 1 0001011xxx 32 058000h?05ffffh sa1-12 0 1 0001100xxx 32 060000h?067fffh sa1-13 0 1 0001101xxx 32 068000h?06ffffh sa1-14 0 1 0001110xxx 32 070000h?077fffh sa1-15 0 1 0001111xxx 32 078000h?07ffffh sa1-16 0 1 0010000xxx 32 080000h?087fffh sa1-17 0 1 0010001xxx 32 088000h?08ffffh sa1-18 0 1 0010010xxx 32 090000h?097fffh sa1-19 0 1 0010011xxx 32 098000h?09ffffh sa1-20 0 1 0010100xxx 32 0a0000h?0a7fffh sa1-21 0 1 0010101xxx 32 0a8000h?0affffh sa1-22 0 1 0010110xxx 32 0b0000h?0b7fffh sa1-23 0 1 0010111xxx 32 0b8000h?0bffffh sa1-24 0 1 0011000xxx 32 0c0000h?0c7fffh sa1-25 0 1 0011001xxx 32 0c8000h?0cffffh sa1-26 0 1 0011010xxx 32 0d0000h?0d7fffh sa1-27 0 1 0011011xxx 32 0d8000h?0dffffh sa1-28 0 1 0011100xxx 32 0e0000h?0e7fffh sa1-29 0 1 0011101xxx 32 0e8000h?0effffh sa1-30 0 1 0011110xxx 32 0f0000h?0f7fffh sa1-31 0 1 0011111xxx 32 0f8000h?0fffffh sa1-32 0 1 0100000xxx 32 100000h?107fffh sa1-33 0 1 0100001xxx 32 108000h?10ffffh sa1-34 0 1 0100010xxx 32 110000h?117fffh sa1-35 0 1 0100011xxx 32 118000h?11ffffh sa1-36 0 1 0100100xxx 32 120000h?127fffh sa1-37 0 1 0100101xxx 32 128000h?12ffffh
12 am29pdl129h november 2, 2005 bank 1a sa1-38 0 1 0100110xxx 32 130000h?137fffh sa1-39 0 1 0100111xxx 32 138000h?13ffffh sa1-40 0 1 0101000xxx 32 140000h?147fffh sa1-41 0 1 0101001xxx 32 148000h?14ffffh sa1-42 0 1 0101010xxx 32 150000h?157fffh sa1-43 0 1 0101011xxx 32 158000h?15ffffh sa1-44 0 1 0101100xxx 32 160000h?167fffh sa1-45 0 1 0101101xxx 32 168000h?16ffffh sa1-46 0 1 0101110xxx 32 170000h?177fffh sa1-47 0 1 0101111xxx 32 178000h?17ffffh sa1-48 0 1 0110000xxx 32 180000h?187fffh sa1-49 0 1 0110001xxx 32 188000h?18ffffh sa1-50 0 1 0110010xxx 32 190000h?197fffh sa1-51 0 1 0110011xxx 32 198000h?19ffffh sa1-52 0 1 0110100xxx 32 1a0000h?1a7fffh sa1-53 0 1 0110101xxx 32 1a8000h?1affffh sa1-54 0 1 0110110xxx 32 1b0000h?1b7fffh sa1-55 0 1 0110111xxx 32 1b8000h?1bffffh sa1-56 0 1 0111000xxx 32 1c0000h?1c7fffh sa1-57 0 1 0111001xxx 32 1c8000h?1cffffh sa1-58 0 1 0111010xxx 32 1d0000h?1d7fffh sa1-59 0 1 0111011xxx 32 1d8000h?1dffffh sa1-60 0 1 0111100xxx 32 1e0000h?1e7fffh sa1-61 0 1 0111101xxx 32 1e8000h?1effffh sa1-62 0 1 0111110xxx 32 1f0000h?1f7fffh sa1-63 0 1 0111111xxx 32 1f8000h?1fffffh sa1-64 0 1 1000000xxx 32 200000h?207fffh sa1-65 0 1 1000001xxx 32 208000h?20ffffh sa1-66 0 1 1000010xxx 32 210000h?217fffh sa1-67 0 1 1000011xxx 32 218000h?21ffffh sa1-68 0 1 1000100xxx 32 220000h?227fffh sa1-69 0 1 1000101xxx 32 228000h?22ffffh sa1-70 0 1 1000110xxx 32 230000h?237fffh sa1-71 0 1 1000111xxx 32 238000h?23ffffh sa1-72 0 1 1001000xxx 32 240000h?247fffh sa1-73 0 1 1001001xxx 32 248000h?24ffffh sa1-74 0 1 1001010xxx 32 250000h?257fffh sa1-75 0 1 1001011xxx 32 258000h?25ffffh sa1-76 0 1 1001100xxx 32 260000h?267fffh sa1-77 0 1 1001101xxx 32 268000h?26ffffh table 4. am29pdl129h sector architecture bank sector ce1# ce2# sector address (a21- a12) sector size (kwords) address range (x16)
november 2, 2005 am29pdl129h 13 bank 1a sa1-78 0 1 1001110xxx 32 270000h?277fffh sa1-79 0 1 1001111xxx 32 278000h?27ffffh sa1-80 0 1 1010000xxx 32 280000h?287fffh sa1-81 0 1 1010001xxx 32 288000h?28ffffh sa1-82 0 1 1010010xxx 32 290000h?297fffh sa1-83 0 1 1010011xxx 32 298000h?29ffffh sa1-84 0 1 1010100xxx 32 2a0000h?2a7fffh sa1-85 0 1 1010101xxx 32 2a8000h?2affffh sa1-86 0 1 1010110xxx 32 2b0000h?2b7fffh sa1-87 0 1 1010111xxx 32 2b8000h?2bffffh sa1-88 0 1 1011000xxx 32 2c0000h?2c7fffh sa1-89 0 1 1011001xxx 32 2c8000h?2cffffh sa1-90 0 1 1011010xxx 32 2d0000h?2d7fffh sa1-91 0 1 1011011xxx 32 2d8000h?2dffffh sa1-92 0 1 1011100xxx 32 2e0000h?2e7fffh sa1-93 0 1 1011101xxx 32 2e8000h?2effffh sa1-94 0 1 1011110xxx 32 2f0000h?2f7fffh sa1-95 0 1 1011111xxx 32 2f8000h?2fffffh table 4. am29pdl129h sector architecture bank sector ce1# ce2# sector address (a21- a12) sector size (kwords) address range (x16)
14 am29pdl129h november 2, 2005 bank 1b sa1-96 0 1 1100000xxx 32 300000h?307fffh sa1-97 0 1 1100001xxx 32 308000h?30ffffh sa1-98 0 1 1100010xxx 32 310000h?317fffh sa1-99 0 1 1100011xxx 32 318000h?31ffffh sa1-100 0 1 1100100xxx 32 320000h?327fffh sa1-101 0 1 1100101xxx 32 328000h?32ffffh sa1-102 0 1 1100110xxx 32 330000h?337fffh sa1-103 0 1 1100111xxx 32 338000h?33ffffh sa1-104 0 1 1101000xxx 32 340000h?347fffh sa1-105 0 1 1101001xxx 32 348000h?34ffffh sa1-106 0 1 1101010xxx 32 350000h?357fffh sa1-107 0 1 1101011xxx 32 358000h?35ffffh sa1-108 0 1 1101100xxx 32 360000h?367fffh sa1-109 0 1 1101101xxx 32 368000h?36ffffh sa1-110 0 1 1101110xxx 32 370000h?377fffh sa1-111 0 1 1101111xxx 32 378000h?37ffffh sa1-112 0 1 1110000xxx 32 380000h?387fffh sa1-113 0 1 1110001xxx 32 388000h?38ffffh sa1-114 0 1 1110010xxx 32 390000h?397fffh sa1-115 0 1 1110011xxx 32 398000h?39ffffh sa1-116 0 1 1110100xxx 32 3a0000h?3a7fffh sa1-117 0 1 1110101xxx 32 3a8000h?3affffh sa1-118 0 1 1110110xxx 32 3b0000h?3b7fffh sa1-119 0 1 1110111xxx 32 3b8000h?3bffffh sa1-120 0 1 1111000xxx 32 3c0000h?3c7fffh sa1-121 0 1 1111001xxx 32 3c8000h?3cffffh sa1-122 0 1 1111010xxx 32 3d0000h?3d7fffh sa1-123 0 1 1111011xxx 32 3d8000h?3dffffh sa1-124 0 1 1111100xxx 32 3e0000h?3e7fffh sa1-125 0 1 1111101xxx 32 3e8000h?3effffh sa1-126 0 1 1111110xxx 32 3f0000h?3f7fffh sa1-127 0 1 1111111000 4 3f8000h?3f8fffh sa1-128 0 1 1111111001 4 3f9000h?3f9fffh sa1-129 0 1 1111111010 4 3fa000h?3fafffh sa1-130 0 1 1111111011 4 3fb000h?3fbfffh sa1-131 0 1 1111111100 4 3fc000h?3fcfffh sa1-132 0 1 1111111101 4 3fd000h?3fdfffh sa1-133 0 1 1111111110 4 3fe000h?3fefffh sa1-134 0 1 1111111111 4 3ff000h?3fffffh table 4. am29pdl129h sector architecture bank sector ce1# ce2# sector address (a21- a12) sector size (kwords) address range (x16)
november 2, 2005 am29pdl129h 15 bank 2a sa2-0 1 0 0000000000 4 000000h?000fffh sa2-1 1 0 0000000001 4 001000h?001fffh sa2-2 1 0 0000000010 4 002000h?002fffh sa2-3 1 0 0000000011 4 003000h?003fffh sa2-4 1 0 0000000100 4 004000h?004fffh sa2-5 1 0 0000000101 4 005000h?005fffh sa2-6 1 0 0000000110 4 006000h?006fffh sa2-7 1 0 0000000111 4 007000h?007fffh sa2-8 1 0 0000001xxx 32 008000h?00ffffh sa2-9 1 0 0000010xxx 32 010000h?017fffh sa2-10 1 0 0000011xxx 32 018000h?01ffffh sa2-11 1 0 0000100xxx 32 020000h?027fffh sa2-12 1 0 0000101xxx 32 028000h?02ffffh sa2-13 1 0 0000110xxx 32 030000h?037fffh sa2-14 1 0 0000111xxx 32 038000h?03ffffh sa2-15 1 0 0001000xxx 32 040000h?047fffh sa2-16 1 0 0001001xxx 32 048000h?04ffffh sa2-17 1 0 0001010xxx 32 050000h?057fffh sa2-18 1 0 0001011xxx 32 058000h?05ffffh sa2-19 1 0 0001100xxx 32 060000h?067fffh sa2-20 1 0 0001101xxx 32 068000h?06ffffh sa2-21 1 0 0001110xxx 32 070000h?077fffh sa2-22 1 0 0001111xxx 32 078000h?07ffffh sa2-23 1 0 0010000xxx 32 080000h?087fffh sa2-24 1 0 0010001xxx 32 088000h?08ffffh sa2-25 1 0 0010010xxx 32 090000h?097fffh sa2-26 1 0 0010011xxx 32 098000h?09ffffh sa2-27 1 0 0010100xxx 32 0a0000h?0a7fffh sa2-28 1 0 0010101xxx 32 0a8000h?0affffh sa2-29 1 0 0010110xxx 32 0b0000h?0b7fffh sa2-30 1 0 0010111xxx 32 0b8000h?0bffffh sa2-31 1 0 0011000xxx 32 0c0000h?0c7fffh sa2-32 1 0 0011001xxx 32 0c8000h?0cffffh sa2-33 1 0 0011010xxx 32 0d0000h?0d7fffh sa2-34 1 0 0011011xxx 32 0d8000h?0dffffh sa2-35 1 0 0011100xxx 32 0e0000h?0e7fffh sa2-36 1 0 0011101xxx 32 0e8000h?0effffh sa2-37 1 0 0011110xxx 32 0f0000h?0f7fffh sa2-38 1 0 0011111xxx 32 0f8000h?0fffffh table 4. am29pdl129h sector architecture bank sector ce1# ce2# sector address (a21- a12) sector size (kwords) address range (x16)
16 am29pdl129h november 2, 2005 bank 2b sa2-39 1 0 0100000xxx 32 100000h?107fffh sa2-40 1 0 0100001xxx 32 108000h?10ffffh sa2-41 1 0 0100010xxx 32 110000h?117fffh sa2-42 1 0 0100011xxx 32 118000h?11ffffh sa2-43 1 0 0100100xxx 32 120000h?127fffh sa2-44 1 0 0100101xxx 32 128000h?12ffffh sa2-45 1 0 0100110xxx 32 130000h?137fffh sa2-46 1 0 0100111xxx 32 138000h?13ffffh sa2-47 1 0 0101000xxx 32 140000h?147fffh sa2-48 1 0 0101001xxx 32 148000h?14ffffh sa2-49 1 0 0101010xxx 32 150000h?157fffh sa2-50 1 0 0101011xxx 32 158000h?15ffffh sa2-51 1 0 0101100xxx 32 160000h?167fffh sa2-52 1 0 0101101xxx 32 168000h?16ffffh sa2-53 1 0 0101110xxx 32 170000h?177fffh sa2-54 1 0 0101111xxx 32 178000h?17ffffh sa2-55 1 0 0110000xxx 32 180000h?187fffh sa2-56 1 0 0110001xxx 32 188000h?18ffffh sa2-57 1 0 0110010xxx 32 190000h?197fffh sa2-58 1 0 0110011xxx 32 198000h?19ffffh sa2-59 1 0 0110100xxx 32 1a0000h?1a7fffh sa2-60 1 0 0110101xxx 32 1a8000h?1affffh sa2-61 1 0 0110110xxx 32 1b0000h?1b7fffh sa2-62 1 0 0110111xxx 32 1b8000h?1bffffh sa2-63 1 0 0111000xxx 32 1c0000h?1c7fffh sa2-64 1 0 0111001xxx 32 1c8000h?1cffffh sa2-65 1 0 0111010xxx 32 1d0000h?1d7fffh sa2-66 1 0 0111011xxx 32 1d8000h?1dffffh sa2-67 1 0 0111100xxx 32 1e0000h?1e7fffh sa2-68 1 0 0111101xxx 32 1e8000h?1effffh sa2-69 1 0 0111110xxx 32 1f0000h?1f7fffh sa2-70 1 0 0111111xxx 32 1f8000h?1fffffh sa2-71 1 0 1000000xxx 32 200000h?207fffh sa2-72 1 0 1000001xxx 32 208000h?20ffffh sa2-73 1 0 1000010xxx 32 210000h?217fffh sa2-74 1 0 1000011xxx 32 218000h?21ffffh sa2-75 1 0 1000100xxx 32 220000h?227fffh sa2-76 1 0 1000101xxx 32 228000h?22ffffh sa2-77 1 0 1000110xxx 32 230000h?237fffh sa2-78 1 0 1000111xxx 32 238000h?23ffffh table 4. am29pdl129h sector architecture bank sector ce1# ce2# sector address (a21- a12) sector size (kwords) address range (x16)
november 2, 2005 am29pdl129h 17 bank 2b sa2-79 1 0 1001000xxx 32 240000h?247fffh sa2-80 1 0 1001001xxx 32 248000h?24ffffh sa2-81 1 0 1001010xxx 32 250000h?257fffh sa2-82 1 0 1001011xxx 32 258000h?25ffffh sa2-83 1 0 1001100xxx 32 260000h?267fffh sa2-84 1 0 1001101xxx 32 268000h?26ffffh sa2-85 1 0 1001110xxx 32 270000h?277fffh sa2-86 1 0 1001111xxx 32 278000h?27ffffh sa2-87 1 0 1010000xxx 32 280000h?287fffh sa2-88 1 0 1010001xxx 32 288000h?28ffffh sa2-89 1 0 1010010xxx 32 290000h?297fffh sa2-90 1 0 1010011xxx 32 298000h?29ffffh sa2-91 1 0 1010100xxx 32 2a0000h?2a7fffh sa2-92 1 0 1010101xxx 32 2a8000h?2affffh sa2-93 1 0 1010110xxx 32 2b0000h?2b7fffh sa2-94 1 0 1010111xxx 32 2b8000h?2bffffh sa2-95 1 0 1011000xxx 32 2c0000h?2c7fffh sa2-96 1 0 1011001xxx 32 2c8000h?2cffffh sa2-97 1 0 1011010xxx 32 2d0000h?2d7fffh sa2-98 1 0 1011011xxx 32 2d8000h?2dffffh sa2-99 1 0 1011100xxx 32 2e0000h?2e7fffh sa2-100 1 0 1011101xxx 32 2e8000h?2effffh sa2-101 1 0 1011110xxx 32 2f0000h?2f7fffh sa2-102 1 0 1011111xxx 32 2f8000h?2fffffh sa2-103 1 0 1100000xxx 32 300000h?307fffh sa2-104 1 0 1100001xxx 32 308000h?30ffffh sa2-105 1 0 1100010xxx 32 310000h?317fffh sa2-106 1 0 1100011xxx 32 318000h?31ffffh sa2-107 1 0 1100100xxx 32 320000h?327fffh sa2-108 1 0 1100101xxx 32 328000h?32ffffh sa2-109 1 0 1100110xxx 32 330000h?337fffh sa2-110 1 0 1100111xxx 32 338000h?33ffffh sa2-111 1 0 1101000xxx 32 340000h?347fffh sa2-112 1 0 1101001xxx 32 348000h?34ffffh sa2-113 1 0 1101010xxx 32 350000h?357fffh sa2-114 1 0 1101011xxx 32 358000h?35ffffh sa2-115 1 0 1101100xxx 32 360000h?367fffh sa2-116 1 0 1101101xxx 32 368000h?36ffffh sa2-117 1 0 1101110xxx 32 370000h?377fffh sa2-118 1 0 1101111xxx 32 378000h?37ffffh table 4. am29pdl129h sector architecture bank sector ce1# ce2# sector address (a21- a12) sector size (kwords) address range (x16)
18 am29pdl129h november 2, 2005 table 5. addresses table 6. autoselect codes (high voltage method) legend: l = logic low = v il , h = logic high = v ih , ba = bank address, sa = sector address, x = don?t care. note: the autoselect codes may also be accessed in-system via command sequences table 7. am29pdl129h boot sector/sector block addresses for protection/unprotection ce1# control bank 2b sa2-119 1 0 1110000xxx 32 380000h?387fffh sa2-120 1 0 1110001xxx 32 388000h?38ffffh sa2-121 1 0 1110010xxx 32 390000h?397fffh sa2-122 1 0 1110011xxx 32 398000h?39ffffh sa2-123 1 0 1110100xxx 32 3a0000h?3a7fffh sa2-124 1 0 1110101xxx 32 3a8000h?3affffh sa2-125 1 0 1110110xxx 32 3b0000h?3b7fffh sa2-126 1 0 1110111xxx 32 3b8000h?3bffffh sa2-127 1 0 1111000xxx 32 3c0000h?3c7fffh sa2-128 1 0 1111001xxx 32 3c8000h?3cffffh sa2-129 1 0 1111010xxx 32 3d0000h?3d7fffh sa2-130 1 0 1111011xxx 32 3d8000h?3dffffh sa2-131 1 0 1111100xxx 32 3e0000h?3e7fffh sa2-132 1 0 1111101xxx 32 3e8000h?3effffh sa2-133 1 0 1111110xxx 32 3f0000h?3f7fffh sa2-134 1 0 1111111xxx 32 3f8000h?3fffffh table 4. am29pdl129h sector architecture bank sector ce1# ce2# sector address (a21- a12) sector size (kwords) address range (x16) sector size address range am29pdl129h 128 words 000000h?00007fh factory-locked area 64 words 000000h-00003fh customer-lockable area 64 words 000040h-00007fh description ce1# ce2# oe# we# a21 to a12 a10 a9 a8 a7 a6 a5 to a4 a3 a2 a1 a0 dq15 to dq0 manufacturer id : amd lh lhxx v id x l l x l l l l 0001h hl device id read cycle 1 lh lhxx v id xl l l l l l h 227eh hl read cycle 2 lh h h h l 2221h hl read cycle 3 lh h h h h 2200h hl sector protection verification lh lhsax v id xl l l llhl 0001h (protected), 0000h (unprotected) hl indicator bit (dq7, dq6) lh lhxx v id xx l x llhh 00c0h (factory and customer locked), 0080h (factory locked) hl sector group a21-12 sector/sector block size sa1-0?sa1-3 00000xxxxx 128 (4x32) kwords
november 2, 2005 am29pdl129h 19 table 8. am29pdl129h boot sector/sector block addresses for protection/unprotection ce2# control sa1-4?sa1-7 00001xxxxx 128 (4x32) kwords sa1-8?sa1-11 00010xxxxx 128 (4x32) kwords sa1-12?sa1-15 00011xxxxx 128 (4x32) kwords sa1-16?sa1-19 00100xxxxx 128 (4x32) kwords sa1-20?sa1-23 00101xxxxx 128 (4x32) kwords sa1-24?sa1-27 00110xxxxx 128 (4x32) kwords sa1-28?sa1-31 00111xxxxx 128 (4x32) kwords sa1-32?sa1-35 01000xxxxx 128 (4x32) kwords sa1-36?sa1-39 01001xxxxx 128 (4x32) kwords sa1-40?sa1-43 01010xxxxx 128 (4x32) kwords sa1-44?sa1-47 01011xxxxx 128 (4x32) kwords sa1-48?sa1-51 01100xxxxx 128 (4x32) kwords sa1-52?sa1-55 01101xxxxx 128 (4x32) kwords sa1-56?sa1-59 01110xxxxx 128 (4x32) kwords sa1-60?sa1-63 01111xxxxx 128 (4x32) kwords sa1-64?sa1-67 10000xxxxx 128 (4x32) kwords sa1-68?sa1-71 10001xxxxx 128 (4x32) kwords sa1-72?sa1-75 10010xxxxx 128 (4x32) kwords sa1-76?sa1-79 10011xxxxx 128 (4x32) kwords sa1-80?sa1-83 10100xxxxx 128 (4x32) kwords sa1-84?sa1-87 10101xxxxx 128 (4x32) kwords sa1-88?sa1-91 10110xxxxx 128 (4x32) kwords sa1-92?sa1-95 10111xxxxx 128 (4x32) kwords sa1-96?sa1-99 11000xxxxx 128 (4x32) kwords sa1-100?sa1-103 11001xxxxx 128 (4x32) kwords sa1-104?sa1-107 11010xxxxx 128 (4x32) kwords sa1-108?sa1-111 11011xxxxx 128 (4x32) kwords sa1-112?sa1-115 11100xxxxx 128 (4x32) kwords sa1-116?sa1-119 11101xxxxx 128 (4x32) kwords sa1-120?sa1-123 11110xxxxx 128 (4x32) kwords sa1-124 1111100xxx 32 kwords sa1-125 1111101xxx 32 kwords sa1-126 1111110xxx 32 kwords sa1-127 1111111000 4 kwords sa1-128 1111111001 4 kwords sa1-129 1111111010 4 kwords sa1-130 1111111011 4 kwords sa1-131 1111111100 4 kwords sa1-132 1111111101 4 kwords sa1-133 1111111110 4 kwords sa1-134 1111111111 4 kwords sector group a21-12 sector/sector block size sector group a21-12 sector/sector block size sa2-0 0000000000 4 kwords sa2-1 0000000001 4 kwords sa2-2 0000000010 4 kwords sa2-3 0000000011 4 kwords sa2-4 0000000100 4 kwords sa2-5 0000000101 4 kwords sa2-6 0000000110 4 kwords sa2-7 0000000111 4 kwords sa2-8 0000001xxx 32 kwords sa2-9 0000010xxx 32 kwords sa2-10 0000011xxx 32 kwords sa2-11 - sa2-14 00001xxxxx 128 (4x32) kwords sa2-15 - sa2-18 00010xxxxx 128 (4x32) kwords sa2-19 - sa2-22 00011xxxxx 128 (4x32) kwords sa2-23 - sa2-26 00100xxxxx 128 (4x32) kwords sa2-27 - sa2-30 00101xxxxx 128 (4x32) kwords sa2-31 - sa2-34 00110xxxxx 128 (4x32) kwords sa2-35 - sa2-38 00111xxxxx 128 (4x32) kwords sa2-39 - sa2-42 01000xxxxx 128 (4x32) kwords sa2-43 - sa2-46 01001xxxxx 128 (4x32) kwords sa2-47 - sa2-50 01010xxxxx 128 (4x32) kwords sa2-51 - sa2-54 01011xxxxx 128 (4x32) kwords sa2-55 - sa2-58 01100xxxxx 128 (4x32) kwords sa2-59 - sa2-62 01101xxxxx 128 (4x32) kwords sa2-63 - sa2-66 01110xxxxx 128 (4x32) kwords sa2-67 - sa2-70 01111xxxxx 128 (4x32) kwords sa2-71 - sa2-74 10000xxxxx 128 (4x32) kwords sa2-75 - sa2-78 10001xxxxx 128 (4x32) kwords sa2-79 - sa2-82 10010xxxxx 128 (4x32) kwords sa2-83 - sa2-86 10011xxxxx 128 (4x32) kwords sa2-87 - sa2-90 10100xxxxx 128 (4x32) kwords sa2-91 - sa2-94 10101xxxxx 128 (4x32) kwords sa2-95 - sa2-98 10110xxxxx 128 (4x32) kwords sa2-99 - sa2-102 10111xxxxx 128 (4x32) kwords sa2-103 - sa2-106 11000xxxxx 128 (4x32) kwords sa2-107 - sa2-110 11001xxxxx 128 (4x32) kwords sa2-111 - sa2-114 11010xxxxx 128 (4x32) kwords sa2-115 - sa2-118 11011xxxxx 128 (4x32) kwords sa2-119 - sa2-122 11100xxxxx 128 (4x32) kwords sa2-123 - sa2-126 11101xxxxx 128 (4x32) kwords sa2-127 - sa2-130 11110xxxxx 128 (4x32) kwords sa2-131 - sa2-134 11111xxxxx 128 (4x32) kwords
20 am29pdl129h november 2, 2005 selecting a sector protection mode the device is shipped with all sectors unprotected. amd offers the option of programming and protecting sectors at the factory prior to shipping the device through amd?s expressflash? service. contact an amd representative for details. it is possible to determine whether a sector is pro- tected or unprotected. see autoselect mode for de- tails. table 9. sector protection schemes write protect (wp#) the write protect feature provides a hardware method of protecting sectors without using v id . this function is provided by the wp# pin and overrides the previ- ously discussed high voltage sector protection method. if the system asserts v il on the wp#/acc pin, the de- vice disables program and erase functions in the two outermost 4 kword sectors on both ends of the flash array independent of whether it was previously pro- tected or unprotected. if the system asserts v ih on the wp#/acc pin, the de- vice reverts to whether sectors were last set to be pro- tected or unprotected. that is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in high voltage sector protection . note that the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. persistent protection bit lock the persistent protection bit (ppb) lock is a volatile bit that reflects the state of the password mode lock- ing bit after power-up reset. if the password mode lock bit is also set after a hardware reset (reset# asserted) or a power-up reset, the only means for clearing the ppb lock bit in password protection mode is to issue the password unlock command. suc- cessful execution of the password unlock command clears the ppb lock bit, allowing for sector ppbs modifications. asserting reset#, taking the device through a power-on reset, or issuing the ppb lock bit set command sets the ppb lock bit to a ?1? when the password mode lock bit is not set. if the password mode locking bit is not set, including persistent protection mode, the ppb lock bit is cleared after power-up or hardware reset. the ppb lock bit is set by issuing the ppb lock bit set com- mand. once set the only means for clearing the ppb lock bit is by issuing a hardware or power-up reset. the password unlock command is ignored in persis- tent protection mode. high voltage sector protection sector protection and unprotection may also be imple- mented using programming equipment. the proce- dure requires high voltage (v id ) to be placed on the reset# pin. refer to figure 1 for details on this pro- cedure. note that for sector unprotect, all unprotected sectors must first be protected prior to the first sector write cycle. figure 1. temporary sector unprotect figure 2. flash memory region the secsi (secured silicon) sector feature provides a flash memory region that enables permanent part identification through an electronic serial number (esn) the 128-word secsi sector is divided into 64 factory-lockable words that can be programmed and locked by the customer. the secsi sector is located at addresses 000000h-00007fh in both persistent pro- tection mode and password protection mode. it uses indicator bits (dq6, dq7) to indicate the factory- locked and customer-locked status of the part. the system accesses the through a command se- quence (see ?enter /exit command sequence?). after the system has written the enter command sequence, it may read the by using the addresses normally occu- pied by the boot sectors. this mode of operation con- tinues until the system issues the exit command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. factory-locked area (64 words) the factory-locked area of the secsi sector (000000h- 00003fh) is locked when the part is shipped, whether or not the area was programmed at the factory. the secsi sector factory-locked indicator bit (dq7) is per- manently set to a ?1?. amd offers the expressflash service to program the factory-locked area with a ran- dom esn, a customer-defined code, or any combina- notes: 1. all protected sectors unprotected (if wp#/acc = v il , sectors will remain protected). 2. all previously protected sectors are protected once again.
november 2, 2005 am29pdl129h 21 tion of the two. because only amd can program and protect the factory-locked area, this method ensures the security of the esn once the product is shipped to the field. contact an amd representative for details on using amd?s expressflash service. note that the acc function and unlock bypass modes are not available when the secsi sector is enabled. customer-lockable area (64 words) the customer-lockable area of the secsi sector (000040h-00007fh) is shipped unprotected, which al- lows the customer to program and optionally lock the area as appropriate for the application. the secsi sector customer-locked indicator bit (dq6) is shipped as ?0? and can be permanently locked to ?1? by issuing the secsi protection bit program command. the secsi sector can be read any number of times, but can be programmed and locked only once. note that the accelerated programming (acc) and unlock by- pass functions are not available when programming the secsi sector. the customer-lockable area can be protected using one of the following procedures: follow the secsi sector protection algorithm as shown in . this allows in-system protection of the secsi sector without raising any device pin to a high voltage. note that this method is only applicable to the secsi sector.
22 am29pdl129h november 2, 2005 figure 3. secsi sector protection algorithm to verify the protect/unprotect status of the secsi sector, follow the algorithm shown in figure 4 . start secsi tm sector entry write aah to address 555h write 55h to address 2aah write 88h to address 555h secsi sector protection entry write aah to address 555h write 55h to address 2aah write 60h to address 555h plscnt = 1 protect secsi sector: write 68h to sector address with a7?a0 = 00011010 time out 256 s read from sector address with a7?a0 = 00011010 data = 01h? yes secsi sector protection completed secsi sector exit write 555h/aah write 2aah/55h write sa0+555h/90h write xxxh/00h verify secsi sector: write 48h to sector address with a7?a0 = 00011010 no
november 2, 2005 am29pdl129h 23 once the is locked and verified, the system must write the exit region command sequence to return to reading and writing the remainder of the array. the must be used with caution since, once locked, there is no procedure available for unlocking the area and none of the bits in the memory space can be modified in any way. secsi sector protection bits the secsi sector protection bits prevent programming of the secsi sector memory area. once set, the secsi sector memory area contents are non-modifiable. figure 4. secsi sector protect verify common flash memory interface (cfi) the common flash interface (cfi) spec ification outlines device and host system software interrogation hand- shake, which allows specific vendor-specified software algorithms to be used for entire families of devices. soft- ware support can then be device-independent, jedec id-independent, and forward- and backward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibil- ity. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h, any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 10 ? 13 . to terminate reading cfi data, the system must write the reset command. the cfi query mode is not ac- cessible when the device is executing an embedded program or embedded erase algorithm. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 10 ? 13 . the system must write the reset command to return the device to reading array data. for further information, please refer to the cfi specification and cfi publication 100, available via the world wide web at http://www.amd.com/flash/cfi. alternatively, contact an amd representative for copies of these documents. table 10. cfi query identification string addresses data description write 60h to any address write 40h to secsi sector address with a6 = 0, a1 = 1, a0 = 0 start reset# = v ih or v id wait 1 s read from secsi sector address with a6 = 0, a1 = 1, a0 = 0 if data = 00h, secsi sector is unprotected. if data = 01h, secsi sector is protected. remove v ih or v id from reset# write reset command secsi sector protect verify complete
24 am29pdl129h november 2, 2005 table 11. system interface string table 12. device geometry definition 10h 11h 12h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists) addresses data description 1bh 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0004h typical timeout per single byte/word write 2 n s 20h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 0009h typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0005h max. timeout for byte/word write 2 n times typical 24h 0000h max. timeout for buffer write 2 n times typical 25h 0004h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported) addresses data description 27h 0018h device size = 2 n byte 28h 29h 0001h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 0000h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 0003h number of erase block regions within device 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 00fdh 0000h 0000h 0001h erase block region 2 information (refer to the cfi specification or cfi publication 100)
november 2, 2005 am29pdl129h 25 35h 36h 37h 38h 0007h 0000h 0020h 0000h erase block region 3 information (refer to the cfi specification or cfi publication 100) 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information (refer to the cfi specification or cfi publication 100)
26 am29pdl129h november 2, 2005 table 13. primary vendor-specific extended query addresses data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 0031h major version number, ascii (r eflects modi fications to the silicon) 44h 0033h minor version number, ascii (ref lects modifications to the cfi table) 45h 000ch address sensitive unlock (bits 1-0) 0 = required, 1 = not required silicon revision number (bits 7-2) 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 0007h sector protect/unprotect scheme 01 =29f040 mode, 02 = 29f016 mode, 03 = 29f400, 04 = 29lv800 mode 4ah 00e7h simultaneous operation 00 = not supported, x = number of sectors excluding bank 1 4bh 0000h burst mode type 00 = not supported, 01 = supported 4ch 0002h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 0085h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 0095h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 0001h top/bottom boot sector flag 00h = uniform device, 02h = bottom boot device, 03h = top boot device, 04h = both top and bottom 50h 0001h program suspend 0 = not supported, 1 = supported 57h 0004h bank organization 00 = data at 4ah is zero, x = number of banks 58h 0027h bank 1 region information x = number of sectors in bank 1 59h 0060h bank 2 region information x = number of sectors in bank 2 5ah 0060h bank 3 region information x = number of sectors in bank 3 5bh 0027h bank 4 region information x = number of sectors in bank 4
november 2, 2005 am29pdl129h 27 command definitions enter /exit command sequence the region provides a secured data area containing a random, eight word electronic serial number (esn). the system can access the region by issuing the three-cycle enter command sequence. the device continues to access the region until the system issues the four-cycle exit command sequence. the exit om- mand sequence returns the device to normal opera- tion. the secsi sector is not accessible when the device is executing an embedded program or embed- ded erase algorithm. shows the address and data re- quirements for both command sequences. see also ?secsi sector flash memory region and enter secsi sector/exit secsi sector command sequence? for fur- ther information. note that the acc function and un- lock bypass modes are not available when the secsi sector is enabled. figure 5. if the persistent sector protection mode locking bit is verified as programmed without margin, the persistent sector protection mode locking bit program com- mand should be reissued to improve program margin. if the secsi sector protection bit is verified as pro- grammed without margin, the secsi sector protection bit program command should be reissued to improve program margin. ? after programming a ppb, two ad- ditional cycles are needed to determine whether the ppb has been programmed with margin. if the ppb has been programmed without margin, the program command should be reissued to improve the program margin. also note that the total number of ppb pro- gram/erase cycles is limited to 100 cycles. cycling the ppbs beyond 100 cycles is not guaranteed. after erasing the ppbs, two additional cycles are needed to determine whether the ppb has been erased with margin. if the ppbs has been erased with- out margin, the erase command should be reissued to improve the program margin. ppb lock bit status sector protection status the programming of either the ppb or dyb for a given sector or sector group can be verified by writing a sector protection status command to the device. note that there is no single command to independently verify the programming of a dyb for a given sector group.
28 am29pdl129h november 2, 2005 command definitions tables legend: ba = address of bank switching to autoselect mode, bypass mode, or erase operation. determined by a21:a20, see tables 4 and for more detail. pa = program address (a21:a0). addresses latch on falling edge of we# or ce1#/ce2# pulse, whichever happens later. pd = program data (dq15:dq0) written to location pa. data latches on rising edge of we# or ce1#/ce2# pulse, whichever happens first. ra = read address (a21:a0). rd = read data (dq15:dq0) from location ra. sa = sector address (a21:a12) for verifying (in autoselect mode) or erasing. wd = write data. see ?configuration register? definition for specific write data. data latched on rising edge of we#. x = don?t care notes: 1. see ta b l e 1 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells in table denote read cycles. all other cycles are write operations. 4. during unlock and command cycles, when lower address bits are 555 or 2aah as shown in table, address bits higher than a11 (except where ba is required) and data bits higher than dq7 are don?t cares. 5. no unlock or command cycles required when bank is reading array data. 6. the reset command is required to return to reading array (or to erase-suspend-read mode if previously in erase suspend) when bank is in autoselect mode, or if dq5 goes high (while bank is providing status information). 7. fourth cycle of autoselect command sequence is a read cycle. system must provide bank address to obtain manufacturer id or device id information. see autoselect command sequence for more information. 8. the data is c0h for factory or customer locked and 80h for factory locked. 9. the data is 00h for an unprotected sector group and 01h for a protected sector group. 10. device id must be read across cycles 4, 5, and 6. 11. system may read and program in non-erasing sectors, or enter autoselect mode, when in program/erase suspend mode. program/erase suspend command is valid only during a sector erase operation, and requires bank address. 12. program/erase resume command is valid only during erase suspend mode, and requires bank address. 13. command is valid when device is ready to read array data or when device is in autoselect mode. 14. must be at v id during the entire operation of command. 15. unlock bypass entry command is required prior to any unlock bypass operation. unlock bypass reset co mmand is required to return to the reading array. table 14. memory array command definitions command (notes) cycles bus cycles (notes 1?4) addr data addr data addr data addr data addr data addr data read (5) 1 ra rd reset (6) 1 xxx f0 autoselect (note 7) manufacturer id 4 555 aa 2aa 55 555 90 (ba)x00 01 device id (10) 6 555 aa 2aa 55 555 90 (ba)x01 7e (ba)x0e 21 (ba)x0f 00 secsi sector factory protect (8) 4 555 aa 2aa 55 555 90 x03 (see note 8) sector group protect verify (9) 4 555 aaa 2aa 55 555 90 (sa)x02 xx00/ xx01 program 4 555 aa 2aa 55 555 a0 pa pd chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 program/erase suspend (11) 1 ba b0 program/erase resume (12) 1 ba 30 cfi query (13) 1 55 98 accelerated program (15) 2 xx a0 pa pd unlock bypass entry (15) 3 555 aa 2aa 55 555 20 unlock bypass program (15) 2 xx a0 pa pd unlock bypass erase (15) 2 xx 80 xx 10 unlock bypass cfi (13, 15) 1 xx 98 unlock bypass reset (15) 2 xxx 90 xxx 00
november 2, 2005 am29pdl129h 29 legend: dyb = dynamic protection bit ow = address (a7:a0) is (00011010) pd[3:0] = password data (1 of 4 portions) ppb = persistent protection bit pwa = password address. a1:a0 selects portion of password. pwd = password data being verified. pl = password protection mode lock address (a7:a0) is (00001010) rd(0) = read data dq0 for protection indicator bit. rd(1) = read data dq1 for ppb lock status. sa = sector address where security command applies. address bits a21:a12 uniquely select any sector. sl = persistent protection mode lock address (a7:a0) is (00010010) wp = ppb address (a7:a0) is (00000010) (note16) x = don?t care ppmlb = password protection mode locking bit spmlb = persistent protection mode locking bit 1. see ta b l e 1 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells in table denote read cycles. all other cycles are write operations. 4. during unlock and command cycles, when lower address bits are 555 or 2aah as shown in table, address bits higher than a11 (except where ba is required) and data bits higher than dq7 are don?t cares. 5. the reset command returns device to reading array. 6. cycle 4 programs the addressed locking bit. cycles 5 and 6 validate bit has been fully programmed when dq0 = 1. if dq0 = 0 in cycle 6, program command must be issued and verified again. 7. data is latched on the rising edge of we#. 8. entire command sequence must be entered for each portion of password. 9. command sequence returns ffh if ppmlb is set. 10. the password is written over four consecutive cycles, at addresses 0-3. 11. a 2 s timeout is required between any two portions of password. 12. a 100 s timeout is required between cycles 4 and 5. 13. a 1.2 ms timeout is required between cycles 4 and 5. 14. cycle 4 erases all ppbs. cycles 5 and 6 validate bits have been fully erased when dq0 = 0. if dq0 = 1 in cycle 6, erase command must be issued and verified again. before issuing erase command, all ppbs should be programmed to prevent ppb overerasure. 15. dq1 = 1 if ppb locked, 0 if unlocked. 16. for pdl128g and pdl640g, the wp address is 0111010. the ep address (ppb erase address) is 1111010. 17. following the final cycle of the command sequence, the user must write the first three cycles of the autoselect command and then write a reset command. 18. if checking the dyb status of sectors in multiple banks, the user must follow note 17 before crossing a bank boundary. table 15. sector protection command definitions command (notes) cycles bus cycles (notes 1-4) addr data addr data addr data addr data addr data addr data addr data reset 1 xxx f0 secsi sector entry 3 555 aa 2aa 55 555 88 secsi sector exit 4 555 aa 2aa 55 555 90 xx 00 secsi protection bit program (5, 6) 6 555 aa 2aa 55 555 60 ow 68 ow 48 ow rd(0) secsi protection bit status 5 555 aa 2aa 55 555 60 ow 48 ow rd(0) password program (5, 7, 8) 4 555 aa 2aa 55 555 38 xx[0-3] pd[0-3] password verify (6, 8, 9) 4 555 aa 2aa 55 555 c8 pwa[0-3] pwd[0-3] password unlock (7, 10, 11) 7 555 aa 2aa 55 555 28 pwa[0] pwd[0] pwa[1] pwd[1] pwa[2] pwd[2] pwa[3] pwd[3] ppb program (5, 6, 12, 17) 6 555 aa 2aa 55 555 60 (sa)wp 68 (sa)wp 48 (sa)wp rd(0) ppb status 5 555 aa 2aa 55 555 60 (sa)wp 48 (sa)wp rd (0) all ppb erase (5, 6, 13, 14) 6 555 aa 2aa 55 555 60 wp 60 (sa) 40 (sa)wp rd(0) ppb lock bit set (17) 3 555 aa 2aa 55 555 78 ppb lock bit status (15) 4 555 aa 2aa 55 555 58 sa rd(1) dyb write (7) 4 555 aa 2aa 55 555 48 sa x1 dyb erase (7) 4 555 aa 2aa 55 555 48 sa x0 dyb status (6, 18) 4 555 aa 2aa 55 555 58 sa rd(0) ppmlb program (5, 6, 12) 6 555 aa 2aa 55 555 60 pl 68 pl 48 pl rd(0) ppmlb status (5) 5 555 aa 2aa 55 555 60 pl 48 pl rd(0) spmlb program (5, 6, 12) 6 555 aa 2aa 55 555 60 sl 68 sl 48 sl rd(0) spmlb status (5) 5 555 aa 2aa 55 555 60 sl 48 sl rd(0)
30 am29pdl129h november 2, 2005 absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . ?65 c to +150 c ambient temperature with power applied. . . . . . . . . . . . . . ?65 c to +125 c voltage with respect to ground v cc (note 1) . . . . . . . . . . . . . . . . .?0.5 v to +4.0 v a9 , oe# , and reset# (note 2) . . . . . . . . . . . . . . . . . . . .?0.5 v to +13.0 v (note 2) . . . . . . . . . . . . . . . . . . .?0.5 v to +10.5 v all other pins (note 1) . . . . . . ?0.5 v to v cc +0.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. see . during voltage transitions , input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 7 . 2. minimum dc input voltage on pins a9, oe#, reset#, and wp#/acc is ?0.5 v. during voltage transitions, a9, oe#, wp#/acc, and reset# may overshoot v ss to ? 2.0 v for periods of up to 20 ns. see . maximum dc input voltage on pin a9, oe#, and reset# is +12.5 v which may overshoot to +14.0 v for periods up to 20 ns. maximum dc input voltage on wp#/acc is +9.5 v which may overshoot to +12.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for exten ded periods may affect device reliability. figure 6. maximum negative overshoot waveform figure 7. maximum positive overshoot waveform operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . ?40c to +85c supply voltages v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7?3.6 v v io (see note) . . . . . . . . . . .1.65?1.95 v or 2.7?3.6 v for all ac and dc specifications, v io = v cc ; contact amd for other v io options. operating ranges de fine those limits between which the functionality of the device is guaranteed. 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v
november 2, 2005 am29pdl129h 31 dc characteristics cmos compatible notes: 1. valid ce1#/ce2# conditions: (ce1#= v il , ce2#= v ih ) or (ce1#= v ih , ce2#= v il ) 2. the i cc current listed is typically less than 5 ma/mhz, with oe# at v ih . 3. maximum i cc specifications are tested with v cc = v ccmax . 4. i cc active while embedded erase or embedded program is in progress. 5. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 150 ns. typical sleep mode current is 1 a. 6. not 100% tested. parameter symbol parameter description test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9, oe#, reset# input load current v cc = v cc max ; v id = 12.5 v 35 a i lr reset leakage current v cc = v cc max ; v id = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , oe# = v ih v cc = v cc max 1.0 a i cc1 v cc active read current (notes 1, 2, 3) oe# = v ih , v cc = v cc max (note 1) 5 mhz 20 30 ma 10 mhz 45 55 i cc2 v cc active write current (notes 1, 3, 4) oe# = v ih , we# = v il 15 25 ma i cc3 v cc standby current (note 3) ce1#, ce2#, reset#, wp/acc# = v io 0.3 v 15a i cc4 v cc reset current (note 3) reset# = v ss 0.3 v, ce# = v ss 15a i cc5 automatic sleep mode (notes 3, 5) v ih = v io 0.3 v; v il = v ss 0.3 v, ce# = v ss 15a i cc6 v cc active read-while-program current (notes 1, 2, 3) oe# = v ih word 21 45 ma i cc7 v cc active read-while-erase current (notes 1, 2, 3) oe# = v ih word 21 45 ma i cc8 v cc active program-while-erase- suspended current (notes 1, 3, 6) oe# = v ih 17 25 ma v il input low voltage v io = 1.65?1.95 v ?0.4 0.4 v v io = 2.7?3.6 v ?0.5 0.8 v v ih input high voltage v io = 1.65?1.95 v v io ?0.4 v io +0.4 v v io = 2.7?3.6 v 2.0 v cc +0.3 v v hh voltage for acc program acceleration v cc = 3.0 v 10% 8.5 9.5 v v id voltage for autoselect and temporary sector unprotect v cc = 3.0 v 10% 11.5 12.5 v v ol output low voltage i ol = 100 a, v cc = v cc min , v io = 1.65?1.95 v 0.1 v i ol = 2.0 ma, v cc = v cc min , v io = 2.7?3.6 v 0.4 v v oh output high voltage i oh = ?100 a, v cc = v cc min , v io = 1.65?1.95 v v io ?0.1 v i oh = ?2.0 ma, v cc = v cc min , v io = 2.7?3.6 v 2.4 v v lko low v cc lock-out voltage (note 6) 2.3 2.5 v
32 am29pdl129h november 2, 2005 test conditions table 16. test specifications note: for 70 pf output load capacitance, 2 ns will be added to certain read-only operation parameters. key to switching waveforms 2.7 k c l 6.2 k 3.6 v device under te s t note: diodes are in3064 or equivalent figure 8. test setup, v io = 2.7 ? 3.6 v * for v io = 1.65 ? 1.95 test setup, the device is tested using c l only test condition all speeds unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0?3.0 v input timing measurement reference levels 1.5 v output timing measurement reference levels 1.5 v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) v io 0.0 v v io /2 v io /2 output measurement level input figure 9. input waveforms and measurement levels
november 2, 2005 am29pdl129h 33 ac characteristics ce1#/ce2# timing read-only operations notes: 1. not 100% tested. 2. see figure 8 and table 16 for test specifications 3. valid ce1#/ce2# conditions: (ce1#= v il , ce2#= v ih ) or (ce1#= v ih , ce2#=v il ). 4. valid ce1#/ce2# transitions: (ce1#= ce2#= v ih ) to (ce1#= v il , ce2#=v ih ) or (ce1#= v ih , ce2#=v il ). 5. measurements performed by placing a 50 ohm termination on the data pin with a bias of v cc /2. the time from oe# high to the data bus driven to v cc /2 is taken as t df . 6. valid ce1#/ce2# transitions: (ce1#= v il , ce2#= v ih ) or (ce1#= v ih , ce2#=v il ) to (ce1#= ce2#= v ih ). 7. for 70 pf output load capacitance, 2 ns will be added to t acc , t ce , t pac c , t oe values for all speed options. parameter description all speed options unit jedec std t ccr ce1#/ce2# recover time min 30 ns ce1# t ccr t ccr ce2# figure 10. timing diagram for alternating between ce1# and ce2# control parameter description test setup speed options jedec std. 53 63 68 88 unit t avav t rc read cycle time (note 1) min 55 65 65 85 ns t avqv t acc address to output delay (note 3) ce#, oe# = v il max55656585ns t elqv t ce chip enable to output delay (note 4) oe# = v il max60657085ns t pac c page access time max 20 25 30 ns t glqv t oe output enable to output delay max 20 25 30 ns t ehqz t df chip enable to output high z (notes 1, 5, 6) max 16 ns t ghqz t df output enable to output high z (notes 1, 5) max 16 ns t axqx t oh output hold time from addresses, ce#/ce2# or oe#, whichever occurs first (notes 5, 6) min 5 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns
34 am29pdl129h november 2, 2005 ac characteristics figure 12. page read operation timings note: 1. during ce1# transitions, ce2#= v ih ; during ce2# transitions, ce1#= v ih t oh t ce data we# addresses ce1# or ce2# oe# high z valid data high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df figure 11. read operation timings note: 1. during ce1# transitions, ce2#= v ih ; during ce2# transitions, ce1#= v ih addresses ce1# or ce2# oe# a2 - a0 data same page aa ab ac ad qa qb qc qd t acc t pac c t pac c t pac c
november 2, 2005 am29pdl129h 35 ac characteristics hardware reset (reset#) note: not 100% tested. parameter description all speed options unit jedec std t ready reset# pin low (during embedded algorithms) to read mode (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s t rb ry/by# recovery time min 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce1# or ce2#, oe# t rh ce1# or ce2#, oe# reset timings during embedded algorithms reset# t rp t rb figure 13. reset timings note: 1. during ce1# transitions, ce2#= v ih ; during ce2# transitions, ce1#= v ih
36 am29pdl129h november 2, 2005 ac characteristics erase and program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. parameter speed options jedec std. description 53 63 68 88 unit t avav t wc write cycle time (note 1) min 55 65 65 85 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 30 35 ns t aht address hold time from ce1#, ce2#, or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 25 30 ns t whdx t dh data hold time min 0 ns t oeph output enable high duri ng toggle bit polling min 10 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce1# or ce2# setup time min 0 ns t wheh t ch ce1# or ce2# hold time min 0 ns t wlwh t wp write pulse width min 35 40 ns t whdl t wph write pulse width high min 20 25 ns t sr/w latency between read and write operations min 0 ns t whwh1 t whwh1 programming operation (note 2) typ 6 s t whwh1 t whwh1 accelerated programming operation (note 2) typ 4 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t vcs v cc setup time (note 1) min 50 s t rb write recovery time from ry/by# min 0 ns t busy program/erase valid to ry/by# delay max 90 ns
november 2, 2005 am29pdl129h 37 ac characteristics oe# we# ce1# or ce2# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa notes: 1. pa = program address, pd = program data, d out is the true data at the program address. 2. during ce1# transitions, ce2#= v ih ; during ce2# transitions, ce1#= v ih figure 14. program operation timings wp#/acc t vhh v hh v il or v ih v il or v ih t vhh figure 15. accelerated program timing diagram
38 am29pdl129h november 2, 2005 ac characteristics oe# ce1# or ce2# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch status d out t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy notes: 1. sa = sector address (for sect or erase), va = valid address for reading status data (.) 2. during ce1# transitions, ce2#= v ih ; during ce2# transitions, ce1#= v ih figure 16. chip/sector erase operation timings
november 2, 2005 am29pdl129h 39 ac characteristics oe# ce1# or ce2# we# addresses t oh data valid in valid in valid pa valid ra t wc t wph t ah t wp t ds t dh t as t rc t ce t ah valid out t oe t acc t oeh t ghwl t df valid in ce# controlled write cycles we# controlled write cycle valid pa valid pa t cp t cph t wc t wc read cycle t sr/w t as note: 1. during ce1# transitions, ce2#= v ih ; during ce2# transitions, ce1#= v ih figure 17. back-to-back read/write cycle timings we# ce1# or ce2# oe# high z t oe high z dq7 dq6?dq0 ry/by# t busy complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement status data tr u e valid data valid data t acc t rc note: 1. va = valid address. illustration shows fi rst status cycle after command sequence, last status read cycle, and array data read cycle. during ce1# transitions, ce2#= v ih ; 2. during ce2# transitions, ce1#= v ih figure 18. data# polling timings (during embedded algorithms)
40 am29pdl129h november 2, 2005 ac characteristics oe# ce1# or ce2# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6/dq2 valid data valid status valid status valid status ry/by# notes: 1. va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. 2. during ce1# transitions, ce2#= v ih ; during ce2# transitions, ce1#= v ih figure 19. toggle bit timings (during embedded algorithms) note: 1. dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. figure 20. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
november 2, 2005 am29pdl129h 41 ac characteristics temporary sector unprotect note: not 100% tested. parameter all speed options jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t vhh v hh rise and fall time (see note) min 250 ns t rsp reset# setup time for temporary sector unprotect min 4 s t rrb reset# hold time from ry/by# high for temporary sector unprotect min 4 s reset# t vidr v id v il or v ih v id v il or v ih ce1# or ce2# we# ry/by# t vidr t rsp program or erase command sequence t rrb note: during ce1# transitions, ce2#= v ih ; during ce2# transitions, ce1#= v ih figure 21. temporary sector unprotect timing diagram
42 am29pdl129h november 2, 2005 ac characteristics sector group protect: 150 s sector group unprot ect: 15 ms 1 s reset# sa, a6, a1, a0 data ce1# or ce2# we# oe# 60h 60h 40h valid* valid* valid* status sector group protect/unprotect verify v id v ih * for sector protect, a6 = 0, a1 = 1, a0 = 0. for sector unprotect, a6 = 1, a1 = 1, a0 = 0. notes: 1. during ce1# transitions, ce2#= v ih ; during ce2# transitions, ce1#= v ih figure 22. sector/sector block protect and unprotect timing diagram
november 2, 2005 am29pdl129h 43 ac characteristics alternate ce# controlled er ase and program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. parameter speed options jedec std. description 53 63 68 88 unit t avav t wc write cycle time (note 1) min 55 65 65 85 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 30 35 ns t dveh t ds data setup time min 25 30 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce1# or ce2# pulse width min 35 40 ns t ehel t cph ce1# or ce2# pulse width high min 20 25 ns t whwh1 t whwh1 programming operation (note 2) ty p 6 s t whwh1 t whwh1 accelerated programming operation (note 2) typ 4 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec
44 am29pdl129h november 2, 2005 ac characteristics t ghel t ws oe# ce1# or ce2# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy notes: 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device. 4. during ce1# transitions, ce2#= v ih ; during ce2# transitions, ce1#= v ih figure 23. alternate ce# controlled write (erase/program) operation timings
november 2, 2005 am29pdl129h 45 erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0 v v cc , 1,000,000 cycles. additionally, programming typicals assume checkerboard pat tern. all values are subject to change. 2. under worst case conditions of 90 c, v cc = 2.7 v, 1,000,000 cycles. all values are subject to change. 3. the typical chip programming time is considerably less t han the maximum chip programming ti me listed, since most bytes program faster than the ma ximum program times listed. 4. in the pre-programming step of the embedded erase algorit hm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the tw o- or four-bus-cycle sequence for the program command. see tables for further information on command definitions. 6. the device has a minimum erase and pr ogram cycle endurance of 1,000,000 cycles. latchup characteristics note: includes all pins except v cc . test conditions: v cc = 3.0 v, one pin at a time, v io = v cc bga ball capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. data retention parameter typ (note 1) max (note 2) unit comments sector erase time 0.4 5 sec excludes 00h programming prior to erasure (note 4) chip erase time 108 sec word program time 6 210 s excludes system level overhead (note 5) accelerated word program time 4 120 s chip program time (note 3) 50 200 sec description min max input voltage with respect to v ss on all pins except i/o pins (including a9, oe#, and reset#) ?1.0 v 13 v input voltage with respect to v ss on all i/o pins ?1.0 v v cc + 1.0 v v cc current ?100 ma +100 ma parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 4.2 5.0 pf c out output capacitance v out = 0 5.4 6.5 pf c in2 control pin capacitance v in = 0 3.9 4.7 pf parameter description t est conditions min unit minimum pattern data retention time 150 c10years 125 c20years
46 am29pdl129h november 2, 2005 revision summary revision a (september 30, 2002) initial release. revision a+1 (october 30, 2002) product selector guide modified format of product selector guide table. ordering information changed tbd to vk under the package type classifi- cation. added vk packages to valid combinations table. global changed 55 speed option to 53, changed 65 speed option to 63 and 68. table 1. am29pdl127h device bus operations added note #2. requirements for reading array data reworded page mode read section common flash memory interface (cfi) changed wording in last sentence of third paragraph from, ?...the autoselect mode.? to ?...reading array data.? changed cfi website address. command definitions changed wording in last sentence of first paragraph from, ?...resets the device to reading array data.? to ...?may place the device to an unknown state. a reset command is then required to return the device to reading array data.? customer lockable: secsi sector not programmed or protected at the factory. added second bullet, secsi sector-protect verify text and figure 3. secsi sector flash memory region and enter secsi sector/exit secsi sector command sequence added notes, ? note that the acc function and unlock bypass modes are not available when the secsi sector is enabled. ? sector erase command sequence and chip erase command sequence added ?? table 14. ?memory array command definitions changed the first address of the unlock bypass reset command sequence from ba to xxx. cmos compatible added i lr parameter to table. deleted i acc parameter from table. revision a+2 (january 24, 2003) ordering information corrected the ordering part number and package markings for the 83 and 88 speed options. revision a+3 (february 26, 2003) table 16. test specifications updated output load capacitance. revision a + 4 (april 22, 2003) inserted and revised cross references. revision a+5 (june 20, 2003) distinctive characteristics changed the active read current to 55 ma. product selector guide added row to table to expand speed options and allow for another v cc range. physical dimensions removed the laa064 package. revision b (july 29, 2003) global changed most ce# references to ce1#. changed bank c to bank 1a, bank d to bank 1b, bank a to bank 2a, and bank b to bank 2b. sector configuration table corrected ce1# and ce2# bank references. table 4. am29pdl129h sector architecture changed the bank order to 1a, 1b, 2a, and 2b.
november 2, 2005 am29pdl129h 47 table 7. am29pdl129h boot sector/sector block addresses for protection/unprotection broke table up into ce1# and ce2# versions and made modifications to table values to reflect change. wp# hardware protection indicated that a write protect pin that can prevent pro- gram or erase operations in sectors sa1-133, sa1- 134, sa2-0 and sa2-1. table 15. sector protection command definitions corrected typos in the ppb status row. added note 17 to ppb program and ppb lock bit set commands. added note 18 to dyb status. test conditions added note to figure 10. table 16. test specifications added specific speed options to table. cmos compatible table added ce# = v ss to i cc4 and i cc5. figure 11. input waveforms and measurement levels modified values to read v cc. revision b+1 (august 8, 2003) ordering information corrected typo in package marking. revision b+2 (december 5, 2003) global deleted the 83 speed option (85 ns t acc , v io = 2.7? 3.6v). replaced the 88 speed option (85 ns t acc , v io = 1.65?1.95v) with 78 (70 ns t acc , v io = 1.65?1.95v). distinctive characteristics performance characteristics: under power consump- tion bullet, changed active read current from 55 to 45 ma; changed program/erase current from 25 to 15 ma. connection diagrams corrected signal descriptions for balls g1 and j1 on 80-ball fine-pitch bga package (vbb080). dc characteristics changed i ol test conditions for v ol from 4.0 ma to 2.0 ma. table 16, test specifications changed c l from 70 pf to 30 pf. added note for 70 pf load capacitance. ac characteristics read-only operations table: added note for 70 pf load capacitance. secsi tm (secured silicon) sector flash memory region customer-lockable area: added sector protection fig- ure and changed figure reference in this section from figure 1 to figure 3. table 16. sector protection command definitions corrected number of cycles for secsi protection bit status, ppmlb status, and spmlb status from 4 to 5 cycles. for these command sequences, inserted a cycle before the final read cycle (rd0). revision b+3 (november 2, 2005) updated migration statement on cover page and first page of data sheet. this product has been retired and is not available for designs. for new and current designs, am29pdl129j supersedes am29pdl129h and is the factory-recom- mended migration path. please refer to the am29pdl129j datasheet for specifications and order- ing information. availability of this document is retained for reference and historical purposes only. updated trademarks. trademarks copyright ? 2000 ? 2005 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are registered trademarks of advanced micro devices, inc. expressflash is a trademark of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies .

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