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oki semiconducto r fedl9209-01 issue date: oct. 20, 2004 ml9209-xx vacuum fluorescent display tube controller driver 1/29 general description the ml9209-xx is an alphanumeric type vacuum fluorescent display (vfd) tube controller driver ic which can display alphanumeric characters, symbols, and bar charts. vacuum fluorescent display tube drive signals are generated by serial data sent from a micro-controller. a display system is easily realized by internal rom and ram for character display. -01 is available as a general-purpose code. custom codes are provided on customer?s request. features ? logic power supply and vacuum fluorescent display tube driving power supply (v dd ) : 3.3 v 10% or 5.0 v 10% ? vacuum fluorescent display tube driving power supply (v fl ) : v dd ? 20 v to v dd ? 42 v ? vfd driver output current (vfd driver output can be connected directly to the vfd tube. no pull-down resistor is required.) ? segment driver (seg1?16) : ?6 ma (v fl = v dd ? 42 v) ? segment driver (ad1, 2) : ?15 ma (v fl = v dd ? 42 v) ? grid driver (com1?16) : ?30 ma (v fl = v dd ? 42 v) ? content of display ? cgrom : 16 segments 240 types (character data) ? cgram : 16 segments 16 types (character data) ? adram : 16 (display digit) 2 bits (symbol data) ? dcram : 16 (display digit) 8 bits (register for character data display) ? display control function ? display digits : 1 to 16 digits ? display duty (brightness adjustment) : 16 stages ? all display lights on/off ? four interfaces with microcontroller: da, cs , cp , reset ? instruction executable with 1 byte (excluding data write for each ram) ? built-in oscillation circuit (resistor & capacitor connected externally) ? package options: 44-pin plastic qfp (qfp44-p-910-0.80-2k) (ml9209-xxga)
fedl9209-01 oki semiconductor ml9209-xx 2/29 block diagram v dd gnd v fl r ese t da cp cs osc0 seg1 seg16 ad1 ad2 com1 com16 dcram 16w 8b cgram 16w 16b adram 16w 2b 8 bit shift register command decoder control circuit timing generator 1 oscillator timing generator 2 digit control duty control grid driver ad driver segment driver write address counter read address counter address selector cgrom 240w 16b
fedl9209-01 oki semiconductor ml9209-xx 3/29 pin configuration (top view) 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 seg6 seg5 seg4 seg3 seg2 seg1 a d2 a d1 v dd d a cp 44 43 42 41 40 39 38 37 36 35 34 seg16 seg15 seg14 seg13 seg12 v fl seg11 12 13 14 15 16 17 18 19 20 21 22 com12 com13 com14 com15 com16 v f l v dd osc0 gnd rese t c s seg10 seg9 seg8 seg7 44-pin plastic qfp
fedl9209-01 oki semiconductor ml9209-xx 4/29 pin description pin symbol type connects to description 28?38, 40?44 seg1?16 o vfd tube anode electrode vfd tube anode electrode drive output. directly connected to the vfd tube and no pull-down resistor is required. i oh > ?6 ma 1?16 com1?16 o vfd tube grid electrode vfd tube grid electrode drive output. directly connected to the vfd tube and no pull-down resistor is required. i oh > ?30 ma 26, 27 ad1?2 o vfd tube anode electrode vfd tube anode electrode drive output. directly connected to the vfd tube and no pull-down resistor is required. i oh > ?15 ma 18, 25 v dd 20 gnd 17,39 v fl ? power supply the voltage supply between v dd and gnd is for the power supply for the internal logic. the voltage supply between v dd and v fl is for the power supply for driving the vfd tube. apply power to v dd first, then to v fl . 24 da i microcontroller serial data input pin (positive logic). data is input from the lsb. 23 cp i microcontroller shift clock input pin. serial data is shifted in on a rising edge of cp . 22 cs i microcontroller chip select input pin. serial data transfer is disabled when cs pin is ?h? level. 21 reset l microcontroller reset input. setting this pin to ?low? initializes all the functions. initial status is as follows. ? address of each ram.............. address ?00?h ? data of each ram ................... content is undefined ? display digit ............................ 16 digits ? brightness adjustment............. 0/16 ? all display lights on or off .... off mode ? all outputs............................... low level pin for rc oscillation. resistors and capacitors are connected externally and constants vary depending on the v dd voltage used. the target oscillation frequency is 2mhz. 19 osc0 i/o c 1 , r 1 osc0 r 1 c 1 (rc oscillator circuit) *refer to the application circuit.
fedl9209-01 oki semiconductor ml9209-xx 5/29 absolute maximum ratings parameter symbol condition rating unit supply voltage (1) v dd ? ?0.3 to +6.5 v supply voltage (2) v fl ? v dd ? 45 v input voltage v ln ? ?0.3 to v dd +0.3 v power dissipation p d ta 25 c 541 mw storage temperature t stg ? ?55 to +150 c l o1 com1?16 ?40 to 0.0 ma l o2 ad1?2 ?20 to 0.0 ma output current i o3 seg1?16 ?10 to 0.0 ma recommended operating conditions-1 ? when the unit power supply voltage is 5.0 v (typ.) parameter symbol condition min. typ. max. unit supply voltage (1) v dd ? 4.5 5.0 5.5 v supply voltage (2) v fl ? v dd ?42 ? v dd ?20 v high level input voltage v ih all input pins except osc0 0.7 v dd ? ? v low level input voltage v il all input pins except osc0 ? ? 0.3 v dd v cp frequency f c ? ? ? 2.0 mhz self-oscillation frequency f osc r 1 = 8.2 k ? 5%, c 1 = 82 pf 5% 1.4 2.0 2.6 mhz frame frequency f fr digit = 1 t o16, r 1 = 8.2 k ? 5%, c 1 = 82 pf 5% 170 244 318 hz operating temperature t op ? ?40 ? 85 c recommended operating conditions-2 ? when the unit power supply voltage is 3.3 v (typ.) parameter symbol condition min. typ. max. unit supply voltage (1) v dd ? 3.0 3.3 3.6 v supply voltage (2) v fl ? v dd ?42 ? v dd ?20 v high level input voltage v ih all input pins except osc0 0.8 v dd ? ? v low level input voltage v il all input pins except osc0 ? ? 0.2 v dd v cp frequency f c ? ? ? 2.0 mhz self-oscillation frequency f osc r 1 = 6.8 k ? 5%, c 1 = 82 pf 5% 1.4 2.0 2.6 mhz frame frequency f fr digit = 1 to 16, r 1 = 6.8 k ? 5%, c 1 = 82 pf 5% 170 244 318 hz operating temperature t op ? ?40 ? 85 c
fedl9209-01 oki semiconductor ml9209-xx 6/29 electrical ch aracteristics dc characteristics-1 (v dd = 5.0 v 10%, v fl = v dd ? 42 v, ta = ?40 to +85 c, unless otherwise specified) parameter symbol applied pin condition min. max. unit high level input voltage v ih cs , cp , da, reset ? 0.7 v dd ? v low level input voltage v il cs , cp , da, reset ? ? 0.3 v dd v high level input current i ih cs , cp , da, reset v ih = v dd ?1.0 1.0 a low level input current i il cs , cp , da, reset v il = 0.0 v ?1.0 1.0 a v oh1 com1?16 i oh1 = ?30 ma v dd ? 1.5 ? v v oh2 ad1?2 i oh2 = ?15 ma v dd ? 1.5 ? v high level output voltage v oh3 seg1?16 i oh3 = ?6 ma v dd ? 1.5 ? v low level output voltage v ol1 com1?16 ad1?2 seg1?16 ? ? v fl + 1.0 v i dd1 duty = 15/16 digit =1?16 all output lights on ? 4 ma supply current i dd2 v dd f osc = 2 mhz, no load duty = 0/16 digit = 1?8 all output lights off ? 3 ma
fedl9209-01 oki semiconductor ml9209-xx 7/29 dc characteristics-2 (v dd = 3.3 v 10%, v fl = v dd ? 42 v, ta = ?40 to +85 c, unless otherwise specified) parameter symbol applied pin condition min. max. unit high level input voltage v ih cs , cp , da, reset ? 0.8 v dd ? v low level input voltage v il cs , cp , da, reset ? ? 0.2 v dd v high level input current i ih cs , cp , da, reset v ih = v dd ?1.0 1.0 a low level input current i il cs , cp , da, reset v il = 0.0 v ?1.0 1.0 a v oh1 com1?16 i oh1 = ?30 ma v dd ? 1.5 ? v v oh2 ad1?2 i oh2 = ?15 ma v dd ? 1.5 ? v high level output voltage v oh3 seg1?16 i oh3 = ?6 ma v dd ? 1.5 ? v low level output voltage v ol1 com1?16 ad1?2 seg1?16 ? ? v fl + 1.0 v i dd1 duty = 15/16 digit =1?16 all output lights on ? 3 ma supply current i dd2 v dd f osc = 2 mhz, no load duty = 0/16 digit = 1?8 all output lights off ? 2 ma
fedl9209-01 oki semiconductor ml9209-xx 8/29 ac characteristics-1 (v dd = 5.0 v 10%, v fl = v dd ? 42 v, ta = ?40 to +85 c, unless otherwise specified) parameter symbol condition min. max. unit cp frequency f c ? ? 2.0 mhz cp pulse width t cw ? 250 ? ns da setup time t ds ? 250 ? ns da hold time t dh ? 250 ? ns cs setup time t css ? 250 ? ns cs hold time t csh r 1 = 8.2 k ? 5%, c 1 = 82 pf 5% 16 ? s cs wait time t csw ? 250 ? ns data processing time t doff r 1 = 8.2 k ? 5%, c 1 = 82 pf 5% 8 ? s reset pulse width t wres ? 250 ? ns reset time t rson ? 250 ? ns da wait time t rsoff ? 250 ? ns t r t r = 20 to 80% ? 2.0 s all driver output slew rate t f c l = 100 pf t f = 80 to 20% ? 2.0 s ac characteristics-2 (v dd = 3.3 v 10%, v fl = v dd ? 42 v, ta = ?40 to +85 c, unless otherwise specified) parameter symbol condition min. max. unit cp frequency f c ? ? 2.0 mhz cp pulse width t cw ? 250 ? ns da setup time t ds ? 250 ? ns da hold time t dh ? 250 ? ns cs setup time t css ? 250 ? ns cs hold time t csh r 1 = 6.8 k ? 5%, c 1 = 82 pf 5% 16 ? s cs wait time t csw ? 250 ? ns data processing time t doff r 1 = 6.8 k ? 5%, c 1 = 82 pf 5% 8 ? s reset pulse width t wres ? 250 ? ns reset execution time t rson ? 250 ? ns da wait time t rsoff ? 250 ? ns t r t r = 20 to 80% ? 2.0 s all driver output slew rate t f c l = 100 pf t f = 80 to 20% ? 2.0 s
fedl9209-01 oki semiconductor ml9209-xx 9/29 timing diagrams 1) data input timing symbol v dd = 3.3 v 10% v dd = 5.0 v 10% v ih 0.8 v dd 0.7 v dd v il 0.2 v dd 0.3 v dd c s c p da t css t ds t dh t doff t cw t cw t csh t csw valid valid valid valid v ih v ih f c v il v il v ih v il 2) data input timing v dd r eset da t rson t wres 0.8 v dd v ih 0.0 v v il v ih v il 0.5 v dd t rsoff 3) output timing all driver outputs t f t r 0.8 v dd 0.2 v fl
fedl9209-01 oki semiconductor ml9209-xx 10/29 4) digit output timing (16-digit, 15/16-duty) com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 ad1-2 seg1-16 v fl t 1 = 1024t t 2 = 60t t 3 = 4t frame cycle display timing blank timing v dd v fl v dd t = 8 (f osc = 2.0 mhz, t 1 = 4.096 ms) (f osc = 2.0 mhz, t 2 = 240 s) (f osc = 2.0 mhz, t 3 = 16 s) f osc 1
fedl9209-01 oki semiconductor ml9209-xx 11/29 functional description command list command lsb first byte msb lsb second byte msb b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 1 dcram data write x0 x1 x2 x3 1 0 0 0 c0 c1 c2 c3 c4 c5 c6 c7 c0 c1 c2 c3 c4 c5 c6 c7 2nd byte 2 cgram data write x0 x1 x2 x3 0 1 0 0 c8 c9 c10 c11 c12 c13 c14 c15 3rd byte 3 adram data write x 0 x 1 x 2 x 3 1 1 0 0 c0 c1 * * * * * * 5 display duty set d0 d1 d2 d3 1 0 1 0 6 number of digits set k0 k1 k2 k3 0 1 1 0 7 all display lights on/off l h * * 1 1 1 0 others (test mode) * : don?t care xn : address setting for each ram cn : character code setting for each ram dn : display duty setting kn : setting of the number of display digits h : all display lights on setting l : all display lights off setting when data is written to ram (dcram, cgram, and adram) continuously, addresses are internally incremented automatically. therefore it is not necessary to specify the 1st byte to write ram data for the 2nd and subsequent bytes. note: the test mode is used for inspection before shipment. it is not a user function. positional relationship between segn and adn (one digit) seg1 c0 seg2 c1 seg3 c2 seg4 c3 c4 seg5 c5 seg6 seg7 c6 seg8 c7 c14 seg15 c10 seg11 c11 seg12 c13 seg14 c9 seg10 c15 seg16 seg13 c12 seg9 c8 c0?7: corresponds to the 2nd byte of the cgram data write command. c8?15: corresponds to the 3rd byte of the cgram data write command.
fedl9209-01 oki semiconductor ml9209-xx 12/29 data transfer method and command write method display control command and data are written by an 8-bit serial transfer. write timing is shown in the figure below. setting the cs pin to ?low? level enables a data transfer. data is 8 bits and is sequentially input into the da pin from lsb (lsb first). as shown in the figure below, data is read by the shift register at the rising edge of the shift clock, which is input into the cp pin. if 8-bit data is input, internal load signals are automatically generated and data is written to each register and ram. therefore it is not necessary to input load signals from the outside. setting the cs pin to ?high? disables data transfer. data input from the point when the cs pin changes from ?high? to ?low? is recognized in 8-bit units. *1 when data is written to ram (dcram, cgram, adram) continuously, addresses are internally incremented automatically. therefore it is not necessary to specify the 1st byte to write ram data for the 2nd and subsequent bytes. reset function reset is executed when the reset pin is set to ?l?, (when turning power on, for example) and initializes all functions. initial status is as follows. ? address of each ram..................... address 00h ? data of each ram .......................... all contents are undefined. ? number of displa y digits ................. 16 digits ? brightness ad justment..................... 0/16 ? all display lights on or off .......... off mode ? segment output............................... all segm ent outputs go ?low.? ? ad output....................................... all ad outputs go ?low.? be sure to execute the reset operation when turning power on and set again according to ?setting flowchart? after reset. t doff lsb c s c p msb 1st byte lsb msb 2nd byte command and address data t csh lsb msb 3rd byte character code data of the next address character code data when data is written to dcram(*1) da b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7
fedl9209-01 oki semiconductor ml9209-xx 13/29 description of commands and functions 1. ?dcram data write? command (specifies the address of dcram and writes the character code of cgrom and cgram.) dcram (data control ram) has a 4-bit address to store character codes of cgrom and cgram. a character code specified by dcram is converted to an alphanumeric character pattern via cgrom or cgram. the dcram can store 16 characters worth of character codes. [command format] x0 x1 x2 x3 1 0 0 0 b0 b1 b2 b3 b4 b5 b6 b7 1st byte (1st) lsb msb c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (2nd) lsb msb : setup and dcram address in the write mode of dcram data are specified. ( exam p le: s p ecif y dcram address 0h. ) : specify character code of cgrom and cgram. (it is written into dcram address 00h.) to specify the character code of cgrom and cgram to the next address continuously, specify only character code as follows. since the address of dcram is automatically incremented, address specification is unnecessary. c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (3rd) lsb msb c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (4th) lsb msb : specify character code of cgrom and cgram. (it is written into dcram address 1h.) : specify character code of cgrom and cgram. (it is written into dcram address 2h.) b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (17th) lsb msb c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (18th) lsb msb : specify character code of cgrom and cgram. (it is written into dcram address fh.) : specify character code of cgrom and cgram. (it is rewritten into dcram address 0h.) c0 c1 c2 c3 c4 c5 c6 c7 x0 (lsb) to x3 (msb): dcram address (4 bits: 16 characters worth) c0 (lsb) to c7 (msb): character code of cgrom and cgram (8 bits: 256 characters worth)
fedl9209-01 oki semiconductor ml9209-xx 14/29 [relationship between dcram addresses setup and com positions] hex x0 x1 x2 x3 com position hexx0x1x2x3 com position 0 0 0 0 0 com1 8 0 0 0 1 com9 1 1 0 0 0 com2 9 1 0 0 1 com10 2 0 1 0 0 com3 a 0 1 0 1 com11 3 1 1 1 0 com4 b 1 1 0 1 com12 4 0 0 1 0 com5 c 0 0 1 1 com13 5 1 0 1 0 com6 d 1 0 1 1 com14 6 0 1 1 0 com7 e 0 1 1 1 com15 7 1 1 1 0 com8 f 1 1 1 1 com16
fedl9209-01 oki semiconductor ml9209-xx 15/29 2. ?cgram data write? command (specifies the address of cgram and writes character pattern data.) cgram (character generator ram) has a 4-bit address to store alphanumeric character patterns. a character pattern stored in cgram can be displayed by specifying the character code (address) by dcram. the addresses of cgram are assigned to 00h to 0fh (all the other addresses are the cgrom addresses). the cgram can store 16 types of character patterns. [command format] c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (2nd) lsb msb : specify 1st-column data. (it is written into cgram address 00h.) c8 c9 c10 c11 c12 c13 c14c15 b0 b1 b2 b3 b4 b5 b6 b7 3rd byte (3rd) lsb msb : specify 2nd-column data. (it is written into cgram address 00h.) x0 x1 x2 x3 0 1 0 0 b0 b1 b2 b3 b4 b5 b6 b7 1st byte (1st) lsb msb : setup and cgram address in the write-in mode of cgram data are specified. (example: specify cgram address 00h.) to specify character pattern data continuously to the next address, specify only character pattern data as follows. since the address of cgram is automatically incremented, address specification is unnecessary. data from the 2nd to 6th byte (character pattern) is regarded as one data item taken together, so 250 ns is sufficient for t doff time between bytes. c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (4th) lsb msb : c8 c9 c10 c11 c12 c13 c14 c15 b0 b1 b2 b3 b4 b5 b6 b7 3rd byte (5th) lsb msb : specify 1st-column data. (it is written into cgram address 01h.) specify 2nd-column data. (it is written into cgram address 01h.) x0 (lsb) to x3 (msb): cgram address (4 bits: 16 characters worth) c0 (lsb) to c15 (msb): character data of cgram (16 bits: 16 outputs per digit)
fedl9209-01 oki semiconductor ml9209-xx 16/29 [positional relationship between cgram addresses setup and cgrom addresses] hex x0 x1 x2 x3 cgrom address hexx0x1x2x3 cgrom address 0 0 0 0 0 ram00 8 0 0 0 1 ram08 1 1 0 0 0 ram01 9 1 0 0 1 ram09 2 0 1 0 0 ram02 a 0 1 0 1 ram0a 3 1 1 1 0 ram03 b 1 1 0 1 ram0b 4 0 0 1 0 ram04 c 0 0 1 1 ram0c 5 1 0 1 0 ram05 d 1 0 1 1 ram0d 6 0 1 1 0 ram06 e 0 1 1 1 ram0e 7 1 1 1 0 ram07 f 1 1 1 1 ram0f refer to the rom code tables attached later in this document. positional relationship between cgrom and cgram outputs seg1 c0 seg2 c1 seg3 c2 seg4 c3 c4 seg5 c5 seg6 seg7 c6 seg8 c7 c14 seg15 c10 seg11 c11 seg12 c13 seg14 c9 seg10 c15 seg16 seg13 c12 seg9 c8 c0?7: corresponds to the 2nd byte of the cgram data write command. c8?15: corresponds to the 3rd byte of the cgram data write commnad. *on cgrom a cgrom (character generator rom) has an 8-bit address to generate alphanumeric type matrix character patterns. it has a capacity of 240 x 16 bits and can store 240 types of character patterns.
fedl9209-01 oki semiconductor ml9209-xx 17/29 3. ?adram data write? command (specifies the address of adram and writes symbol data) adram (additional data ram) has a 2-bit address to store symbol data. symbol data specified by adram is directly output without cgrom and cgram. (the adram can store two types of symbol patterns for each digit.) the terminal to which the contents of adram are output can be used as a cursor. [command format] c0 c1 * * * * * * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (2nd) lsb msb : specify symbol data. (example: specify adram address 0h.) x0 x1 x2 x3 1 1 0 0 b0 b1 b2 b3 b4 b5 b6 b7 1st byte (1st) lsb msb : setup and dcram address in the write-in mode o f dcram data are specified. (example: specify adram address 0h.) to specify symbol data continuously to the next address, specify only symbol data as follows. since the address of adram is automatically incremented, address specification is unnecessary. c0 c1 * * * * * * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (3rd) lsb msb : specify symbol data. (it is written into adram address 1h.) c0 c1 * * * * * * b0 b1 b2 b3 b4 b5 b6 b7 lsb msb : c0 c1 * * * * * * b0 b1 b2 b3 b4 b5 b6 b7 lsb msb : c0 c1 * * * * * * b0 b1 b2 b3 b4 b5 b6 b7 lsb msb : 2nd byte (4th) 2nd byte (17th) 2nd byte (18th) specify symbol data. (it is written into adram address 2h.) specify symbol data. (it is written into adram address fh.) specify symbol data. (it is rewritten into adram address 0h.) x0 (lsb) to x3 (msb) : adram address (4 bits: 16 characters worth) c0 (lsb) to c1 (msb) : symbol data (2 bits: 2 symbols per digit) * : don?t care
fedl9209-01 oki semiconductor ml9209-xx 18/29 [relationship between adram addresses setup and com positions] hex x0 x1 x2 x3 com positions hexx0x1x2x3 com positions 0 0 0 0 0 com1 8 0 0 0 1 com9 1 1 0 0 0 com2 9 1 0 0 1 com10 2 0 1 0 0 com3 a 0 1 0 1 com11 3 1 1 1 0 com4 b 1 1 0 1 com12 4 0 0 1 0 com5 c 0 0 1 1 com13 5 1 0 1 0 com6 d 1 0 1 1 com14 6 0 1 1 0 com7 e 0 1 1 1 com15 7 1 1 1 0 com8 f 1 1 1 1 com16
fedl9209-01 oki semiconductor ml9209-xx 19/29 5. ?display duty set? command (writes display duty value into the duty cycle register.) for display duty, brightness can be adjusted in 16 stages using 4-bit data. when power is turned on or when the reset signal is input, the duty cycle register value is ?0?. always execute this command before turning the display on, then set a desired duty value. [command format] d0 d1 d2 d3 1 0 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1st byte lsb msb : setup and duty value in display duty specification mode are specified. d0 (lsb) to d3 (msb) : display duty data (4 bits: 16 stages worth) [relation between setup data and controlled com duty] hex d0 d1 d2 d3 com duty hex d0 d1 d2 d3 com duty 0 0 0 0 0 0/16 0 0 0 0 1 8/16 1 1 0 0 0 1/16 1 1 0 0 1 9/16 2 0 1 0 0 2/16 2 0 1 0 1 10/16 3 1 1 0 0 3/16 3 1 1 0 1 11/16 4 0 0 1 0 4/16 4 0 0 1 1 12/16 5 1 0 1 0 5/16 5 1 0 1 1 13/16 6 0 1 1 0 6/16 6 0 1 1 1 14/16 7 1 1 1 0 7/16 7 1 1 1 1 15/16 * the state when power is turned on or when the reset signal is input.
fedl9209-01 oki semiconductor ml9209-xx 20/29 6. ?number of display digits set? command (writes the number of display digits into the number-of-display-digits register.) for the number of display digits, 1 to 16 digits can be specified using 4-bit data. when power is turned on or when a reset signal is input, the number-of-display-digits register value is ?0?. always execute this command before turning the display on, then set a desired value. [command format] k0 k1 k2 k3 0 1 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1st byte lsb msb : setup in display digits specification mode and digits value is specified. k0 (lsb) to k3 (msb) : data of the number of display digits (4 bits: 16 digits worth) [relation between data to be set and the number of digits of com to be controlled] hex d0 d1 d2 d3 no. of digits of com hex d0 d1 d2 d3 no. of digits of com 0 0 0 0 0 com1?16 0 0 0 0 1 com1?18 1 1 0 0 0 com1 1 1 0 0 1 com1?9 2 0 1 0 0 com1?2 2 0 1 0 1 com1?10 3 1 1 0 0 com1?3 3 1 1 0 1 com1?11 4 0 0 1 0 com1?4 4 0 0 1 1 com1?12 5 1 0 1 0 com1?5 5 1 0 1 1 com1?13 6 0 1 1 0 com1?6 6 0 1 1 1 com1?14 7 1 1 1 0 com1?7 7 1 1 1 1 com1?15 * the state when power is turned on or when the reset signal is input.
fedl9209-01 oki semiconductor ml9209-xx 21/29 7. ?all display lights on? and ?all display lights off? commands (turns the entire display on and off, respectively.) all display lights on is used primarily for display testing. all display lights off is primarily used for display blink and to prevent false display upon power-on. [command format] l h * * 1 1 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1st byte lsb msb : select all display lights on or off and specif y their operation. l: all display lights off h: all display lights on * : don?t care [data to be setup and display state of seg and ad] l h display state of seg and ad 0 0 normal display 1 0 sets all outputs to low * the state when power is turned on or when reset signal is input 0 1 sets all outputs to high 1 1 sets all outputs to high * priority is given to the all display lights on command.
fedl9209-01 oki semiconductor ml9209-xx 22/29 setting flowchart (power applying included) setup of the number display digits setup of display duty cgram cgram character code a nother ram to be set? release all display lights off mode adram adram character code dcram data write mode (including address setting) dcram character code dcram character code write ended? * select a ram to be used. * display operation active address is incremented automatically no no no yes yes yes yes end of setting no apply v fl * status of all outputs by reset signal input apply v dd all display lights off data write mode (including address setting) data write mode (including address setting) a ddress is incremented automatically a ddress is incremented automatically adram character code write ended? cgram character code write ended? power-off flowchart display operation active turn off v dd turn off v fl
fedl9209-01 oki semiconductor ml9209-xx 23/29 note on applying power to prevent the ic from malfunctioning, turn on the logic power supply first, and then turn on the driver power supply when applying power. also, for power-off, turn off the driver power supply first, then turn off the logic power supply. v dd ? 42v 5v or 3.3v 2.0 s max. 2.0 s max. v fl v dd
fedl9209-01 oki semiconductor ml9209-xx 24/29 application circuit ML9209-01 micro- controller 16 16 2 r eset v dd com1-16 seg1-16 ad1-2 v dd gnd gnd r 1 c 1 v fl osc0 da c p c s output port r 2 c 2 c 3 v dd v fl zd alphanumeric fluorescent display tubes grid (digit) anode (segment) anode (segment) heater transformer v dd gnd gnd v dd c 4 notes: 1. the v dd voltage depends on the power supply voltage of the microcontroller used. adjust the value of the constants r 1 and c 1 to the power supply voltage used. 2. the v fl voltage depends on the vacuum fluorescent display tube used. adjust the value of the constants r 2 and zd to the voltage used. reference data shown below is a chart showing the v fl voltage vs. output current of each driver. care must be taken that the entire power consumption will not ex ceed the power dissipation. ?30 ?25 ?20 ?15 ?10 ?5 0 ?17 ?22 ?27 ?32 ?37 ?42 output current (ma) v fl voltage (v dd ? n) v fl voltage vs. output current of each driver com1?com16 (condition: v oh = v dd ? 1.5 v) ad1?ad2 (condition: v oh = v dd ? 1.5 v) seg1?seg16 (condition: v oh = v dd ? 1.5 v) (v)
fedl9209-01 oki semiconductor ml9209-xx 25/29 ML9209-01 rom code *rom code_a is the character set for sega1 to sega16. *00000000b(00h) to 00001111b(0fh) are the cgram_a addresses msb lsb 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 ram 0001 ram 0010 ram 0011 ram 0100 ram 0101 ram 0110 ram 0111 ram 1000 ram 1001 ram 1010 ram 1011 ram 1100 ram 1101 ram 1110 ram 1111 ram
fedl9209-01 oki semiconductor ml9209-xx 26/29 16 se g ment 14 se g ment 7 se g ment seg1 seg2 seg8 seg9 seg3 seg15 seg11 seg7 seg13 seg4 seg6 seg5 seg14 seg10 seg16 seg12 seg8 seg9 seg3 seg15 seg11 seg7 seg13 seg4 seg6 seg14 seg10 seg16 seg12 seg1 seg1 seg6 seg2 seg7 seg5 seg3 seg4 16 se g ment desi g n 14 se g ment desi g n7 se g ment desi g n msb 0000 0001 0010 0011 0100 0101 0110 0111 0001 0010 0011 0100 0111 lsb 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ram ram ram ram ram ram ram ram ram ram ram ram ram ram ram ram
fedl9209-01 oki semiconductor ml9209-xx 27/29 package dimensions qfp44-p-910-0.80-2k package material epoxy resin lead frame material 42 alloy pin treatment sn/pb package weight (g) 0.41 typ. 5 rev. no./last revised 5/nov. 20, 2002 notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact oki?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). (unit: mm)
fedl9209-01 oki semiconductor ml9209-xx 28/29 revision history page document no. date previous edition current edition description fedl9209-01 oct. 20, 2004 ? ? final edition 1
fedl9209-01 oki semiconductor ml9209-xx 29/29 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party?s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not, unless specifically authorized by oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and n ecessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2004 oki electric industry co., ltd.

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