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? semiconductor MSM54V16272 1/39 ? semiconductor MSM54V16272 262,144-word 16-bit multiport dram description the MSM54V16272 is a 4-mbit cmos multiport dram composed of a 262,144-word by 16-bit dynamic ram, and a 512-word by 16-bit sam. its ram and sam operate independently and asynchronously. it supports three types of operations: random access to ram port, high speed serial access to sam port, and bidirectional transfer of data between any selected row in the ram port and the sam port. in addition to the conventional multiport dram operating modes, the MSM54V16272 features block write and flash write functions on the ram port, and a split data transfer capability on the sam port. the sam port requires no refresh operation because it uses static cmos flip-flops. features ? single power supply: 3.3 v 0.3 v ? full ttl compatibility ? multiport organization ram : 256k word 16 bits sam : 512 word 16 bits ? fast page mode ? write per bit ? byte read/write ? masked flash write ? masked block write (8 columns ) ? package options: 64-pin 525 mil plastic ssop (ssop64-p-525-0.80-k) (product : MSM54V16272-xxgs-k) 70/64-pin 400 mil plastic tsop (type ii) (tsopii70/64-p-400-0.65-k) (product : MSM54V16272-xxts-k) xx indicates speed rank. product family ? ras only refresh ? cas before ras refresh ? cas before ras self-refresh ? hidden refresh ? serial read/write ? 512 tap location ? bidirectional data transfer ? split transfer ? masked write transfer ? refresh: 512 cycles/8 ms access time cycle time power dissipation ram ram operating standby sam sam 60 ns 120 ns 160 ma 8 ma 18 ns 22 ns 70 ns 140 ns 150 ma 8 ma 20 ns 22 ns family MSM54V16272-60 MSM54V16272-70 e2l0024-17-y1 this version: jan. 1998 previous version: dec. 1996
? semiconductor MSM54V16272 2/39 pin configuration (top view) note: the same power supply voltage must be provided to every v cc pin, and the same gnd voltage level must be provided to every v ss pin. pin name function a0 - a8 address input ras row address strobe casl column address strobe lower trg transfer/output enable casu column address strobe upper pin name function sc serial clock se sam port enable dsf special function input v cc power supply (3.3 v) nc no connection dq0 - dq15 ram inputs/outputs sdq0 - sdq15 sam inputs/outputs qsf special function output v ss ground (0 v) we write enable 64-pin plastic ssop 70/64-pin plastic tsop ( ii ) (k type) dq15 sdq15 dq14 sdq14 v cc dq13 sdq13 dq12 sdq12 v ss dq11 sdq11 dq10 sdq10 v cc dq9 sdq9 sdq7 dq7 sdq6 dq6 v ss sdq5 dq5 sdq4 dq4 v ss sdq0 dq0 sdq1 dq1 v cc sdq2 dq2 v cc sc v ss v cc sdq3 dq3 v ss se trg a5 a4 v cc dq8 v ss dsf nc casu qsf a0 a1 a2 a3 v ss sdq8 casl we a6 a7 a8 ras 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 dq15 sdq15 dq14 sdq14 v cc dq13 sdq13 dq12 sdq12 v ss dq11 sdq11 dq10 sdq10 v cc dq9 sdq9 sdq7 dq7 sdq6 dq6 v ss sdq5 dq5 sdq4 dq4 v ss sdq0 dq0 sdq1 dq1 v cc sdq2 dq2 v cc sc v ss v cc sdq3 dq3 v ss se trg a5 a4 v cc dq8 v ss dsf nc casu qsf a0 a1 a2 a3 v ss sdq8 casl we a6 a7 a8 ras 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36
? semiconductor MSM54V16272 3/39 block diagram column address buffer row address buffer refresh counter a0 - a8 sam address buffer sam address counter sam stop control row decoder column decoder sense amp. 512 512 16 ram array gate sam gate sam sdq 0 - 15 qsf serial decoder block write control i/o control flash write control sam input buffer sam output buffer column mask register color register mask register ram input buffer ram output buffer timing generator ras casu / casl trg we dsf sc se v cc v ss dq 0 - 15 se
? semiconductor MSM54V16272 4/39 electrical characteristics absolute maximum ratings parameter symbol rating unit input output voltage v t C0.5 to 4.6 v output current i os 50 ma power dissipation p d 1w operating temperature t opr 0 to 70 c storage temperature t stg C55 to 150 c condition ta = 25c ta = 25c ta = 25c (note: 1) recommended operating conditions parameter symbol unit power supply voltage v cc v input high voltage v ih v input low voltage v il v min. 3.0 2.0 C0.3 typ. 3.3 max. 3.6 v cc + 0.3 0.8 (ta = 0c to 70c) (note: 2) capacitance parameter symbol min. unit input capacitance c i pf input/output capacitance c io pf max. 6 7 output capacitance c o (qsf) pf 7 (v cc = 3.3 v 0.3 v, f = 1 mhz, ta = 25c) note: this parameter is periodically sampled and is not 100% tested. dc characteristics 1 parameter symbol condition output "h" level voltage v oh i oh = C2 ma output "l" level voltage v ol i ol = 2 ma input leakage current i li 0 v in v cc all other pins not under test = 0 v min. 2.4 C10 max. 0.4 10 unit v m a output leakage current i lo 0 v out v cc output disable C10 10
? semiconductor MSM54V16272 5/39 dc characteristics 2 -60 -70 unit note symbol item (ram) sam max. max. operating current standby ( ras , cas cycling, t rc = t rc min.) active standby current ( ras , cas = v ih ) ras only refresh current ( ras cycling, cas = v ih , t rc = t rc min.) page mode current ( ras = v il , cas cycling, t pc = t pc min.) cas before ras refresh current ( ras cycling, cas before ras , t rc = t rc min.) data transfer current ( ras , cas cycling, t rc = t rc min.) flash write current ( ras , cas cycling, t rc = t rc min.) block write current ( ras , cas cycling, t rc = t rc min.) standby active standby active standby active standby active standby active standby active standby active (v cc = 3.3 v 0.3 v, ta = 0c to 70c) 120 110 ma 3, 4 i cc1 160 150 17 88 55 55 3, 4 120 110 3, 4 160 150 17 120 110 3, 4 160 150 18 100 90 3, 4 140 130 3, 4 110 100 3, 4 150 140 17 110 100 3, 4 150 140 3, 4 110 100 3, 4 150 140 3, 4 i cc1 a i cc2 i cc2 a i cc3 i cc3 a i cc4 i cc4 a i cc5 i cc5 a i cc6 i cc6 a i cc7 i cc7 a i cc8 i cc8 a cas before ras self-refresh current ( ras , cas 0.2 v) standby 1 1 3, 4 i cc9
? semiconductor MSM54V16272 6/39 ac characteristics (1/3) parameter symbol note unit t rc t prwc t aa t cac t cpa t rasp t cas t rcd -70 -60 t pc t rac t off t rsh t csh t t t rp t ras t rad t asr t rah t asc t cah t ar t rcs t rch t rrh t wcs t wch t wcr t wp t rwl t cwl t rwc t ral t crp t cp access time from column address column address hold time referenced to ras column address set-up time row address set-up time access time from cas column address hold time cas pulse width cas precharge time (fast page mode) access time from cas precharge cas to ras precharge time cas hold time write command to cas lead time output buffer turn-off delay fast page mode cycle time fast page mode read modify write cycle time row address hold time ras pulse width (fast page mode only) random read or write cycle time ras to cas delay time read command hold time read command set-up time read modify write cycle ras precharge time read command hold time referenced to ras write command to ras lead time access time from ras ras to column address delay time column address to ras lead time ras pulse width ras hold time transition time (rise and fall) write command hold time referenced to ras write command set-up time write command pulse width write command hold time ns ns ns ns ns ns ns ns 14 ns ns 10 ns ns ns ns ns 14 11 11 8, 14 8, 15 8, 15 8, 14 7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns min. 124 2 70 81 15 15 35 0 50 20 55 70 12 0 10 0 10 55 0 0 0 0 10 55 10 15 15 170 35 10 10 min. 104 2 60 76 15 15 30 0 40 15 45 60 12 0 10 0 10 50 0 0 0 0 10 50 10 15 15 140 30 5 10 ns ns 13 max. 35 20 40 35 100k 10k 70 17 10k 50 35 max. 30 15 35 35 100k 10k 60 15 10k 42 30
? semiconductor MSM54V16272 7/39 ac characteristics (2/3) parameter symbol note unit t ds t rwd t cwd t dzc t dzo t csr t ref t wsr -70 -60 t dhr t awd t oea t chr t rpc t oez t oeh t roh t rwh t fsc t cfh t ms t mh t ths t thh t tls t tlh t dh t rth t ath t cth t fsr t rfh t fhr column address to we delay time cas hold time for cas before ras cycle cas set-up time for cas before ras cycle cas to we delay time data hold time data hold time referenced to ras data set-up time data to cas delay time data to trg delay time dsf set-up time referenced to ras write per bit mask data hold time write per bit mask data set-up time trg command hold time refresh period dsf hold time referenced to ras (1) ras hold time referenced to trg ras precharge to cas active time ras to we delay time we hold time access time from trg we set-up time output buffer turn-off delay from trg dsf hold time referenced to ras (2) dsf hold time referenced to cas trg low hold time referenced to column address trg low hold time referenced to cas dsf set-up time referenced to cas trg high hold time trg high set-up time trg low hold time trg low set-up time trg low hold time referenced to ras ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns 13 13 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 12 12 13 min. 0 40 0 0 0 5 90 0 55 55 10 10 0 15 10 0 10 0 10 0 10 0 10 12 60 25 20 0 10 55 min. 0 35 0 0 0 5 80 0 50 50 10 10 0 10 10 0 10 0 10 0 10 0 10 10 50 20 15 0 10 50 max. 15 8 20 10k 10k max. 15 8 15 10k 10k t chs cas hold time ( cas before ras self-refresh) ns 0 0 t rps ras precharge time ( cas before ras self-refresh) ns 140 120 t rass ras pulse width ( cas before ras self-refresh) m s 100 100
? semiconductor MSM54V16272 8/39 ac characteristics (3/3) parameter symbol note unit t tsd t scc t scp t sca t soh t sts t tqd t cqd -70 -60 t sdz t sc t sea t sth t sqd t se t sep t sez t rqd t sze t szs t sws t swh t swis t swih t srs t sdd t sds t sdh access time from sc sc-qsf delay time sc pulse width (sc high time) sc cycle time sc precharge time (sc low time) ras to serial input delay time split transfer hold time split transfer set-up time serial output buffer turn-off delay from ras trg to first sc delay time (read transfer) se pulse width access time from se se precharge time serial write disable hold time serial write disable set-up time serial write enable set-up time serial input to se delay time serial input to first sc delay time serial output buffer turn-off delay from se serial output hold time from sc last sc to ras set-up time (serial input) serial write enable hold time trg -qsf delay time cas -qsf delay time ras -qsf delay time serial input hold time serial input set-up time ns ns ns ns ns ns ns ns ns ns 9 ns ns ns ns ns 9 19 10 ns ns ns ns ns ns ns ns ns ns ns ns 10 t trp t tp t rsd t asd t csd t tsl column address to first sc delay time ras to first sc delay time (read transfer) trg to ras precharge time last sc to trg lead time trg precharge time cas to first sc delay time (read transfer) min. 10 5 5 10 25 20 10 5 10 25 0 0 0 0 10 0 10 25 40 0 10 50 20 70 35 20 5 min. 10 5 3 10 20 18 10 5 10 20 0 0 0 0 10 0 10 20 30 0 10 40 20 60 30 20 5 ns ns ns ns ns ns max. 17 25 40 17 25 15 35 75 max. 15 20 30 15 20 15 30 70
? semiconductor MSM54V16272 9/39 notes: 1. exposure beyond the "absolute maximum ratings" may cause permanent damage to the device. 2. all voltages are referenced to v ss . 3. these parameters depend on the cycle rate. 4. these parameters depend on output loading. specified values are obtained with the output open. 5. an initial pause of 200 m s is required after power up followed by any 8 ras cycles ( trg = "high") and any 8 sc cycles before proper device operation is achieved. in the case of using an internal refresh counter, a minimum of 8 cas before ras cycles instead of 8 ras cycles are required. 6. ac measurements assume t t = 5 ns. 7. v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. also, transition times are measured between v ih and v il . 8. ram port outputs are measured with a load equivalent to 1 ttl load and 50 pf. dout reference levels : v oh /v ol = 2.0 v/0.8 v. 9. sam port outputs are measured with a load equivalent to 1 ttl load and 30 pf. dout reference levels : v oh /v ol = 2.0 v/0.8 v. 10. t off (max.), t oez (max.), t sdz (max.) and t sez (max.) define the time at which the outputs achieve the open circuit condition, and are not referenced to output voltage levels. this parameter is sampled and not 100% tested. 11. either t rch or t rrh must be satisfied for a read cycle. 12. these parameters are referenced to cas leading edge of early write cycles, and to we leading edge in trg controlled write cycles and read modify write cycles. 13. t wcs , t rwd , t cwd and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), the cycle is an early write cycle, and the data out pin will remain open circuit throughout the entire cycle; if t rwd 3 t rwd (min.), t cwd 3 t cwd (min.) and t awd 3 t awd (min.), the cycle is a read modify write cycle, and the data out will contain data read from the selected cell; if neither of the above sets of conditions are satisfied, the condition of the data out is indeterminate. 14. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only: if t rcd is greater than the specified t rcd (max.) limit, then access time is controlled by t cac . 15. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only: if t rad is greater than the specified t rad (max.) limit, then access time is controlled by t aa . 16. input levels at the ac testing are 3.0 v/0 v. 17. address (a0 - a8) may be changed two times or less while ras = v il . 18. address (a0 - a8) may be changed once or less while cas = v ih and ras = v il . 19. this is guaranteed by design. (t soh /t coh = t sca /t cac - output transition time) this parameter is not 100% tested.
? semiconductor MSM54V16272 10/39 timing waveform read cycle ras casl address dsf we dq0 - 7 trg t rc t ras t rp t rcd t cas t rsh t csh t crp t ar t rad t ral t fsr row column t rah t asc t cah t rfh t cfh t fsc t fhr t rcs t rch t cac t rac t aa t rrh t off valid data t oea t roh t oez t thh t ths t asr "h" or "l" open dq8 - 15 valid data open casu t rcd t cas t rsh t csh t crp
? semiconductor MSM54V16272 11/39 fast page mode read cycle ras casl address dsf we t rasp t rp t rcd t cas t csh t crp t ar t rad t fsr row column t rah t asc t cah t rfh t cfh t fsc t fhr t rcs t rrh t asr column column t cp t pc t cas t cp t cas t rsh t asc t cah t asc t cah t ral t cfh t cfh t rch t rcs t rch t rcs casu t rcd t cas t crp t cp t cas t cp t cas t csh t pc t rsh trg "h" or "l" t oea t oez t thh t ths valid data dq8 - 15 t cac t cac t cac t cpa t cpa open valid data valid data t aa t aa t aa valid data dq0 - 7 t rac t off open valid data valid data t off t off t rch t fsc t fsc
? semiconductor MSM54V16272 12/39 write cycle function table write mask data: "low" = mask, "high" = no mask column mask data dq0 - 15 dq0 dq1 dq2 dq3 column mask data column 0 (a0 = 0, a1 = 0, a2 = 0) column 1 (a0 = 1, a1 = 0, a2 = 0) column 2 (a0 = 0, a1 = 1, a2 = 0) column 3 (a0 = 1, a1 = 1, a2 = 0) low : mask high : no mask dq4 column 4 (a0 = 0, a1 = 0, a2 = 1) dq5 column 5 (a0 = 1, a1 = 0, a2 = 1) dq6 column 6 (a0 = 0, a1 = 1, a2 = 1) dq7 column 7 (a0 = 1, a1 = 1, a2 = 1) dq8 column 0 (a0 = 0, a1 = 0, a2 = 0) dq9 column 1 (a0 = 1, a1 = 0, a2 = 0) dq10 column 2 (a0 = 0, a1 = 1, a2 = 0) dq11 column 3 (a0 = 1, a1 = 1, a2 = 0) dq12 column 4 (a0 = 0, a1 = 0, a2 = 1) dq13 column 5 (a0 = 1, a1 = 0, a2 = 1) dq14 column 6 (a0 = 0, a1 = 1, a2 = 1) dq15 column 7 (a0 = 1, a1 = 1, a2 = 1) lower byte upper byte low : mask high : no mask code rwm bwm fwm rw bw lcr a dsf 0 0 1 0 0 1 ras falling edge c we 0 0 0 1 1 1 d dq write mask write mask write mask x x x b dsf 0 1 x 0 1 1 cas falling edge e dq valid data column mask x valid data column mask color data function masked write masked block write masked flash write normal write block write load color register
? semiconductor MSM54V16272 13/39 early write cycle ras casl address t rc t ras t rp t rcd t cas t rsh t csh t crp t ar t rad t ral row column t rah t asc t cah t asr "h" or "l" dsf ab t rfh t fsc t cfh t fsr we c t rwh t wp t wsr dq0 - 7 de t mh t ds t dh t ms trg t thh t ths t rwl t cwl t fhr t wcr t dhr dq8 - 15 de t mh t ds t dh t ms t dhr casu t rcd t cas t rsh t csh t crp t wcs t wch
? semiconductor MSM54V16272 14/39 late write cycle ras casl address t rc t ras t rp t rcd t cas t rsh t csh t crp t ar t rad t ral row column t rah t asc t cah t asr "h" or "l" dsf ab t rfh t fsc t cfh t fsr we c t rwh t wp t wsr dq0 - 7 de t mh t ds t dh t ms trg t oeh t ths t rwl t cwl t fhr t wcr t dhr t rcs dq8 - 15 de t mh t ds t dh t ms t dhr casu t rcd t cas t rsh t csh t crp
? semiconductor MSM54V16272 15/39 read modify write cycle ras casl address t rwc t ras t rp t rcd t cas t rsh t csh t crp t ar t rad t ral row column t rah t asc t cah t asr "h" or "l" dsf ab t rfh t fsc t cfh t fsr we c t rwh t wp t wsr dq0 - 7 de t mh t ds t dh t ms trg t oeh t ths t rwl t cwl t fhr t rwd t rac t rcs t awd t dzc t oea t oez valid data t cac t thh t dzo t cwd dq8 - 15 de t mh t ds t dh t ms valid data casu t rcd t cas t rsh t csh t crp
? semiconductor MSM54V16272 16/39 fast page mode early write cycle t dh t ds t ds t dh t dh t ds t mh t ms ras casl address t rasp t rp t rcd t cas t rsh t csh t crp t ar t rad t ral row column t rah t asc t cah t asr "h" or "l" dsf ab t rfh t fsc t cfh t fsr we c t rwh t wp t wsr dq0 - 7 trg t thh t ths t cwl t fhr column t asc t cah b t fsc t cfh column t asc t cah b t fsc t cfh de e e t wp t wp t cwl t cwl t cas t cas t cp t cp t pc t dh t ds t ds t dh t dh t ds t mh t ms dq8 - 15 d e e e casu t rcd t cas t rsh t csh t crp t cas t cas t cp t cp t pc
? semiconductor MSM54V16272 17/39 fast page mode read modify write cycle t mh t ms ras casl address t rasp t rp t rcd t cas t rsh t csh t crp t ar t rad t ral row column t rah t asc t cah t asr "h" or "l" dsf ab t rfh t fsc t cfh t fsr we c t rwh t wp t wsr dq0 - 7 trg t thh t ths t cwl t fhr column t asc t cah b t fsc t cfh column t asc t cah b t fsc t cfh d in t ds t dh t awd t cas t cas t cp t cp t prwc t wp t wp t cwd t cwd t cwd t rcs t awd t cwl t cwl t awd out t cac t aa in t ds t dh out t cac t aa in t ds t dh out t cac t aa t oez t oea t oez t oea t oez t oea t mh t ms dq8 - 15 d in out in out in out casu t rcd t cas t rsh t csh t crp t cas t cas t cp t cp t prwc
? semiconductor MSM54V16272 18/39 ras only refresh cycle ras casl/u address t rc t ras t rp t crp row t rah t asr "h" or "l" dsf we dq0 - 15 trg t thh t ths t rfh t fsr t rpc open
? semiconductor MSM54V16272 19/39 cas before ras refresh cycle ras casl/u address t rc t ras t rp t csr "h" or "l" dsf we dq0 - 15 trg t rpc t rp t rpc t chr inhibit falling transition open t off
? semiconductor MSM54V16272 20/39 ras casl/u t rass t rps t rpc t off "h" or "l" dq0 - 15 t chs open t rp t csr t rpc cas before ras self-refresh cycle note: address, dsf, we , trg = "h" or "l"
? semiconductor MSM54V16272 21/39 hidden refresh cycle ras casl/u address t rc t ras t rp t rcd t chr t rsh t crp t ar t rad t ral row column t rah t asc t cah t asr "h" or "l" dsf t rfh t fsc t cfh t fsr we dq0 - 15 valid data trg t thh t ths t fhr t rrh t ras t rcs t off t aa t rac t cac t oez t oea open
? semiconductor MSM54V16272 22/39 read transfer 1 note 1: se = "l" note 2: there must be no rising transitions note 3: qsf = "l"-- lower sam (0 - 255) is active qsf = "h"-- upper sam (256 - 511) is active ras casl/u address dsf we dq0 - 15 trg t rc t ras t rp t rcd t cas t rsh t csh t ar t rad t ral t fsr row sam start t rah t asc t cah t rfh t asr "h" or "l" t wsr t rwh t tp t tlh t tls t trp t asd t csd t rsd sc t sc note 2 t srs t tsd t scp t scc t sc din t sih sdq0 - 15 t sis data out t sca t szs t soh t sca qsf t tqd t cqd t rqd note 3 note 3 open
? semiconductor MSM54V16272 23/39 read transfer 2 (real time read transfer) note 1: se = "l" note 2: qsf = "l"-- lower sam (0 - 255) is active qsf = "h"-- upper sam (256 - 511) is active ras casl/u address dsf we dq0 - 15 trg t rc t ras t rp t rcd t cas t rsh t csh t ar t rad t ral t fsr row sam start t rah t asc t cah t rfh t asr "h" or "l" t wsr t rwh t tp t tls t trp t ath t cth sc t scp t sc sdq0 - 15 data out qsf t tqd note 2 note 2 t rth t scc t tsl t tsd data out data out data out t sca t soh t sca t soh open
? semiconductor MSM54V16272 24/39 split read transfer note 1: se = "l" note 2: qsf = "l"-- lower sam (0 - 255) is active qsf = "h"-- upper sam (256 - 511) is active note 3: si is the sam start address in before srt note 4: stop i and stop j are programmable stop addresses ras casl/u address dsf we dq0 - 15 trg t rc t ras t rp t rcd t cas t rsh t csh t ar t rad t ral t fsr row sam start sj t rah t asc t cah t rfh t asr "h" or "l" t wsr t rwh t tlh t tls t cth t ath t rth sc stop i s i stop j - 1 stop j s j t sts sdq0 - 15 qsf t sqd note 2 note 2 data out data out t soh data out t sca t sc t soh t sca data out data out data out note 2 t sqd t scp t scc open
? semiconductor MSM54V16272 25/39 masked write transfer note 1: se = "l" note 2: there must be no rising transitions note 3: qsf = "l"-- lower sam (0 - 255) is active qsf = "h"-- upper sam (256 - 511) is active ras casl/u address dsf we dq0 - 15 trg t rc t ras t rp t rcd t cas t rsh t csh t ar t rad t ral t fsr row sam start t rah t asc t cah t rfh t asr "h" or "l" t wsr t rwh t tlh t tls t csd t rsd sc t sc note 2 t srs t scp t scc t sc dout t sdz sdq0 - 15 t sdh t sds t sdh qsf t sdd t cqd t rqd note 3 note 3 mask data t mh t ms dout t soh data in t sds data in open
? semiconductor MSM54V16272 26/39 masked split write transfer note 1: se = "l" note 2: qsf = "l"-- lower sam (0 - 255) is active qsf = "h"-- upper sam (256 - 511) is active note 3: si is the sam start address in before swt note 4: stop i and stop j are programmable stop addresses ras casl/u address dsf we dq0 - 15 trg t rc t ras t rp t rcd t cas t rsh t csh t ar t rad t ral t fsr row sam start sj t rah t asc t cah t rfh t asr "h" or "l" t wsr t rwh t tlh t tls t cth t ath t rth sc stop i s i stop j - 1 stop j s j t sts sdq0 - 15 qsf t sqd note 2 note 2 data in data in t sds data in t sc t sdh note 2 t sqd t scp t scc data in data in data in t sds t sdh t ms t mh mask data open
? semiconductor MSM54V16272 27/39 serial read cycle serial write cycle se sc sdq0 - 15 t sep data out data t sez t soh data out data out t scc t sea t soh t soh t sca t sc data t scp t sca t sca se sc sdq0 - 15 t sep t sc t swh t scc data in data in t sdh t sds data in data in t swih t sze t sds t sdh t scp t swis t sws "h" or "l"
? semiconductor MSM54V16272 28/39 pin functions address input: a0 - a8 the 18 address bits decode 16 bits of the 4,194,304 locations in the MSM54V16272 memory array. the address bits are multiplexed to 9 address input pins (a0 - a8) as standard dram. 9 row address bits are latched at the falling edge of ras . the following 9 column address bits are latched at the falling edge of cas . row address strobe: ras ras is a basic ram control signal. the ram port is in standby mode when the ras level is "high". as the standard drams ras signal function, ras is the control input that latches the row address bits, and a random access cycle begins at the falling edge of ras . in addition to the conventional ras signal function, the level of the input signals cas , trg , we and dsf at the falling edge of ras , determines the MSM54V16272 operation mode. column address strobe: casl and casu as the standard drams cas signal function, cas is the control input signal that latches the column address input, and the state of the special function input dsf to select in conjunction with the ras control, either read/write operations or the special block write feature on the ram port when the dsf is held "low" at the falling edge of ras . cas also acts as a ram port output enable signal. data transfer/output enable: trg trg is also a control input signal having multiple functions. as the standard drams oe signal function, trg is used as an output enable control when trg is "high" at the falling edge of ras . in addition to the conventional oe signal function, a data transfer operation is started between the ram port and the sam port when trg is "low" at the falling edge of ras . write per bit/write enable: we we is control input signal having multiple functions. as the standard drams we signal function, this is used to write data into the memory on the ram port when we is "high" at the falling edge of ras . in addition to the conventional we signal function, the we determines the write-per-bit function, when we is "low" at the falling edge of ras during ram port operations. the we also determines the direction of data transfer between the ram and sam. when the we is "high" at the falling edge of ras , the data is transferred from ram to sam (read transfer). when the we is "low" at the falling edge of ras , the data is transferred sam to ram (write transfer).
? semiconductor MSM54V16272 29/39 write mask data/data input and output: dq0 - dq15 in conventional write-per bit mode, the dq pins function as mask data at the falling edge of ras . data is written only to high dq pins. data on low dq pins is masked and internal data is retained. after that, they function as input/output pins similar to a standard dram. serial clock: sc sc is a main serial cycle control input signal. all operations of the sam port are synchronized with the serial clock sc. data is shifted in or out of the sam registers at the rising edge of sc. in a serial read cycle, the output data becomes valid on the sdq pins after the maximum specified serial access time t sca from the rising edge of sc. in a serial write cycle, data on sdq pins at the rising edge of sc are fetched into the sam register. serial enable: se the se is a serial access enable control and serial read/write control signal. in a serial read cycle, se is used as an output control. in a serial write cycle, se is used as a write enable control. when se is "high", serial access is disabled. however, the serial address pointer location is still incremented when sc is clocked even when se is "high". special function input: dsf the dsf is latched at the falling edge of ras and cas . it allows for the selection of several ram ports and transfer operating modes. in addition to the conventional multiport dram, the special functions consisting of flash write, block write, load/read color register, and split read/write transfer can be invoked. special function output: qsf qsf is an output signal, which during split register mode indicates which half of the split sam is being accessed. qsf "low" indicates that the lower split sam (0 - 255) is being accessed. qsf "high" indicates that the upper sam (256 - 511) is being accessed. qsf is enabled by se . when se is "high", qsf is in high impedance. serial input/output: sdq0 - sdq15 serial input/output mode is determined by the most recent read or write transfer cycle. when a read transfer cycle is performed, the sam port is in the output mode. when a write or pseudo write transfer cycle is performed, the sam port is switched from output mode to input mode.
? semiconductor MSM54V16272 30/39 ras code address cas trg we dsf dsf ras cas write register 0*** **** cbr cas / we mask ras w/io cas function cbr refresh 11*0row* ror ras only refresh 1000*rowtapwm1* yes mwt masked write transfer 1001*rowtapwm1* yes mswt masked split write transfer 1010*rowtap* * rt read transfer 1011*rowtap* * srt split read transfer 11000row column wm1 din, dout yes rwm read/write (mask) 11001row column wm1 yes use bwm masked block write 1101*row*wm1 yes use fwm masked flash write 11100row column * din, dout no rw read/write (no mask) 11101row * no use bw block write (no mask) 11111row* * load lcr load color register a3c - 8c column a3c - 8c column select column select color data color operation modes table-1 shows the function truth table for a listing of all available ram ports, and transfer operations of the MSM54V16272. the ram port and data transfer operations are determined by the state of cas , trg , we and dsf at the falling edge of ras , and by the level of dsf at the falling edge of cas . table-1. function truth table if the dsf is "high" at the falling edge of ras , special functions such as split transfer, flash write, load color register can be invoked. if the dsf is "low" at the falling edge of ras and "high" at the falling edge of cas , the block write feature can be invoked.
? semiconductor MSM54V16272 31/39 ram port operation ram read cycle: ras falling edge --- trg = cas = "h", dsf = "l" cas falling edge --- dsf = "l" row address is entered at the falling edge of ras and column address at the falling edge of cas to the device as in conventional dram. when the we is "high" and trg is "low" while cas is "low", the data outputs through dq pins. ram write cycle: ras falling edge --- trg = cas = "h", dsf = "l" cas falling edge --- dsf = "l" 1) write cycle with no mask: ras falling edge -- we = "h" if we is set "low" at the falling edge of cas after ras goes "low", a write cycle is excuted. if we is set "low" before the cas falling edge, this cycle becomes an early write cycle, and all dq pins attain high impedance. if we is "low" when cas goes "low", the write affects only those corresponding 8 bits with the latched data. if we is set "low" after the cas falling edge, this cycle becomes a late write cycle, and all 16 data are latched on the falling edge of we . byte write occurs if either casl or casu falls during the cycle. dq pins don't achieve high impedance in this cycle, so data should be entered with trg in "high". 2) write cycle with mask: ras falling edge -- we = "l" if we is set "low" at the falling edge of ras , the mask write mode can be invoked. mask data is loaded and used. the mask data on dq0 - dq15 is latched into the write mask register at the falling edge of ras . when the mask data is low, writing is inhibited into the ram and the mask data is high, data is written into the ram. this mask data is in effect during the ras cycle. in page mode cycle the mask data is retained during page access.
? semiconductor MSM54V16272 32/39 load/read color register: ras falling edge --- cas = trg = we = dsf = "h" cas falling edge --- dsf = "h" the MSM54V16272 is provided with an on-chip 16-bit color register for use during the flash write or block write operation. each bit of the color register corresponds to one of the dram i/o blocks. the data presented on the dqi lines is subsequently latched into the color register at the falling edge of either cas or we whichever occurs later. the read color register cycle is activated by holding we "high" at the falling edge of cas , and throughout the remainder of the cycle. the data in the color register becomes valid on the dqi lines after the specified access times from ras and trg are satisfied. during the load/read color register cycle, the memory cells on the row address latched at the falling edge of ras are refreshed. flash write: ras falling edge --- cas = trg = dsf = "h", we = "l" flash write allows for the data in the color register to be written into all the memory locations of a selected row. each bit of the color register corresponds to one of the dram i/o blocks. the flash write operation can be selectively controlled on an i/o basis in the same manner as the write per bit operation. the mask data is the same as that of a ram write cycle.
? semiconductor MSM54V16272 33/39 block write: ras falling edge --- cas = trg = "h", dsf = "l" cas falling edge --- dsf = "h" block write allows for the data in the color register to be written into 8 consecutive column address locations, starting from a selected column address in a selected row. the block write operation can be selectively controlled on an i/o basis, and a column mask capability is also available. this function is implemented as lower byte and upper byte. during a block write cycle, the 3 least significant column address locations (a0c, a1c and a2c) are internally controlled, and only the 6 most significant column addresses (a3c - a8c) are latched at the falling edge of cas . 1) no mask block write: we "high" at the falling edge of ras the data on 16 dq pins is cleared by the data of the color register. 2) masked block write: we "low" at the falling edge of ras the mask data is the same as that of a ram write cycle. (new mask and persistent mask) 1 dq0 8 column 8 dq (lower byte) note : location "*" can not be loaded. color register i/o mask column mask 11001110 11111010 10010011 lower byte bit 0 bit 15 upper byte 01110011 01101011 00111100 1 * * 1 * * 1 1 1 * * 1 * * 1 0 0 * * 0 * * 0 0 0 * * 0 * * 0 1 1 * * 1 * * 1 * * * * * * * * 1 1 * * 1 * * 1 * * * * * * * * * * * * * * * * * * 1 1 1 1 * * * * 1 1 1 1 * * * * * * * * * * * * 0 0 0 0 * * * * * * * * * * * * 1 1 1 1 * * * * 1 1 1 1 * * column 7 column 6 column 5 column 4 column 3 column 2 column 1 column 0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 8 column 8 dq (upper byte) example of block write
? semiconductor MSM54V16272 34/39 sam port operation single register mode high speed serial read or write operations can be performed through the sam port independent of the ram port operation, except during read/write transfer cycles. the preceding transfer operation determines the direction of data flow through the sam port. if the preceding transfer is a read transfer, the sam port is in the output mode. if the preceding transfer is write transfer, the sam port is in the input mode. serial data can be read out of the sam after a read transfer has been performed. the data is shifted out of the sam starting at any of the 512 bits locations. the tap location corresponds to the column address selected at the falling edge of cas during the read or write transfer cycle. the sam registers are configured as a circular data register. the data is shifted out sequentially. it starts from the selected tap location at the most significant bit (511), then wraps around to the least significant bit (0). split register mode in split register mode data can be shifted into or out of one half of the sam, while a split read or split write transfer is being performed on the other half of the sam. conventional (non split) read, or write transfer cycle must precede any split read or split write transfers. the split read and write transfers will not change the sam port mode set by the preceding conventional transfer operation. in the split register mode, serial data can be shifted in or out of one of the split sam registers, starting from any at the 256 tap locations, excluding the last address of each split sam the data is shifted in or out sequentially starting from the selected tap location at the most significant bit (255 or 511) of the first split sam, and then the sam pointer moves to the tap location selected for the second split sam to shift data in or out sequentially, starts from this tap location at the most significant bit (511 or 255), and finally wraps around to the least significant bit. 0 12 255 tap 256 257 511 tap
? semiconductor MSM54V16272 35/39 data transfer operations the MSM54V16272 features two types of bidirectional data transfer capability between ram and sam. 1) conventional (non split) transfer: 512 words by 16 bits of data can be loaded from ram to sam (read transfer), or from sam to ram (write transfer). 2) split transfer: 256 words by 16 bits of data can be loaded from the lower/upper half of the ram to the lower/upper half of the sam (split read transfer), or from the lower/upper half of sam to the lower/upper half of ram (split write transfer). the conventional transfer and split transfer modes are controlled by the dsf input signal. data transfer is invoked by holding the trg signal "low" at the falling edge of ras . the MSM54V16272 supports 4 types of transfer operations: read transfer, split read transfer, write transfer and split write transfer as shown in the truth table. the type of transfer operation is determined by the state of cas , we and dsf latched at the falling edge of ras . during conventional transfer operations, the sam port is switched from input to output mode (read transfer), or output to input mode (write transfer). it remains unchanged during split transfer operation (split read transfer or split write transfer). both ram and sam are divided by the most significant row address (ax8), as shown in figure 1. therefore, no data transfer between ax8 = 0 side ram and ax8 = 1 side ram can be provided through the sam. care must be taken if the split read transfer on ax8 = 1 side (or ax8 = 0 side) is provided after the read transfer or the split read transfer, is provided on ax8 = 0 side (or ax8 = 1 side). figure 1. ram and sam configuration 256 256 16 memory array 256 256 16 memory array 256 256 16 memory array 256 256 16 memory array serial decoder upper sam 256 16 lower sam 256 16 upper sam 256 16 lower sam 256 16 ax8 = 0 ax8 = 1 sam i/o buffer sdq0 - 15
? semiconductor MSM54V16272 36/39 read transfer: ras falling edge --- cas = we = "h", trg = dsf = "l" read transfer consists of loading a selected row of data from the ram into the sam register. a read transfer is invoked by holding cas "high", trg "low", we "high", and dsf "low" at the falling edge of ras . the row address selected at the falling edge of ras determines the ram row to be transferred into the sam. the transfer cycle is completed at the rising edge of trg . when the transfer is completed, the sam port is set into the output mode. in a read/real time read transfer cycle, the transfer of a new row of data is completed at the rising edge of trg , and this data becomes valid on the sdq lines after the specified access time t sca from the rising edge of the subsequent sc cycles. the start address of the serial pointer of the sam is determined by the column address selected at the falling edge of cas . in a read transfer cycle (which is preceded by a write transfer cycle), sc clock must be held at a constant v il or v ih after the sc high time has been satisfied. a rising edge of the sc clock must not occur until after the specified delay t tsd from the rising edge of trg . in a real time read transfer cycle (which is preceded by another read transfer cycle), the previous row data appears on the sqd lines until the trg signal goes "high", and the serial access time t sca for the following serial clock is satisfied. this feature allows for the first bit of the new row of data to appear on the serial output as soon as the last bit of the previous row has been strobed without any timing loss. to make this continuous data flow possible, the rising edge of trg must be synchronized with ras , cas , and the subsequent rising edge of sc (t rth , t cth and t tsl /t tsd must be satisfied). masked write transfer: ras falling edge --- cas = "h", trg = dsf = "l" we = "l" write transfer cycle consists of loading the content of the sam register into a selected row of the ram. this write transfer operation, which is the same as a mask write operation in ram, can be selectively controlled for 16 dqis by inputing the mask data from dq0 - dq15 at the falling edge of ras . if the sam data to be transferred must first be loaded through the sam, a masked write transfer operation (all dq pins "low" at falling edge of ras ) must precede the write transfer cycles. a masked write transfer is invoked by holding cas "high", trg "low", we "low", and dsf "low" at the falling edge of ras . the row address selected at the falling edge of ras determines the ram row address into which the data will be transferred. the column address selected at the falling edge of cas determines the start address of the serial pointer of the sam. after the write transfer is completed, the sdq lines are set in the input mode so that serial data synchronized with the sc clock can be loaded. when consecutive write transfer operations are performed, new data must not be written into the serial register until the ras cycle of the preceding write transfer is completed. consequently, the sc clock must be held at a constant v il or v ih during the ras cycle. a rising edge of the sc clock is only allowed after the specified delay t csd from the falling edge of the cas , at which time a new row of data can be written in the serial register. data transferred to sam by read transfer cycle or split read transfer cycle can be written to the other address of ram by write transfer cycle. however, the address to write data must be the same as that of the read transfer cycle (row address ax8).
? semiconductor MSM54V16272 37/39 split data transfer and qsf the MSM54V16272 features a bidirectional split data transfer capability between the ram and sam. during split data transfer operation, the serial register is split into two halves which can be controlled independently. split read or split write transfer operation can be performed to or from one half of the serial register, while serial data can be shifted into or out of the other half of the serial register. the most significant column address location (a8c) is controlled internally to determine which half of the serial register will be reloaded from the ram. qsf is an output which indicates which half of the serial register is in an active state. qsf changes state when the last sc clock is applied to active split sam. split read transfer: ras falling edge --- cas = we = dsf = "h", trg = "l" split read transfer consists of loading 256 words by 16 bits of data from a selected row of the split ram into the corresponding non-active split sam register. serial data can be shifted out from the other half of the split sam register simultaneously. during split read transfer operation, the ram port input clocks do not have to be synchronized with the serial clock sc, thus eliminating timing restrictions as in the case of real time read transfers. a split read transfer can be performed after a delay of t sts from the change of state of the qsf output is satisfied. conventional (non-split) read transfer operation must precede split read transfer cycles. masked split write transfer: ras falling edge --- cas = dsf = "h", trg = "l" we = "l" split write transfer consists of loading 256 words by 16 bits of data from the non-active split sam register into a selected row of the corresponding split ram. serial data can be shifted into the other half of the split sam register simultaneously. during split write transfer operation, the ram port input clocks do not have to be synchronized with the serial clock sc, thus allowing for real time transfer. this write transfer operation, which is the same as a mask write operation in ram, can be selectively controlled for 16 dqis by inputing the mask data from dq0 - dq15 at the falling edge of ras . a split write transfer can be performed after a delay of t sts from the change of state of the qsf output is satisfied. a masked write transfer operation must precede split write transfer. the purpose is to switch the sam port from output mode to input mode, and to set the initial tap location prior to split write transfer operations. power up power must be applied to the ras and trg input signals to pull them "high" before, or at the same time as, the v cc supply is turned on. after power-up, a pause of 200 m s minimum is required with ras and trg held "high". after the pause, a minimum of 8 ras and 8 sc dummy cycles must be performed to stabilize the internal circuitry, before valid read, write or transfer operations can begin. during the initialization period, the trg signal must be held "high". if the internal refresh counter is used, a minimum 8 cas before ras cycles are required instead of 8 ras cycles. (note) initial state after power up the initial state can not be guaranteed for various power up conditions and input signal levels. therefore, it is recommended that the initial state be set after the initialization of the device is performed and before valid operations begin.
? semiconductor MSM54V16272 38/39 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). ssop64-p-525-0.80-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.34 typ. mirror finish
? semiconductor MSM54V16272 39/39 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). tsop ii 70/64-p-400-0.65-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.59 typ. mirror finish

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